WO2022011956A1 - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
WO2022011956A1
WO2022011956A1 PCT/CN2020/136391 CN2020136391W WO2022011956A1 WO 2022011956 A1 WO2022011956 A1 WO 2022011956A1 CN 2020136391 W CN2020136391 W CN 2020136391W WO 2022011956 A1 WO2022011956 A1 WO 2022011956A1
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Prior art keywords
unit
temperature
semiconductor device
temperature sensitive
memory chip
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PCT/CN2020/136391
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English (en)
French (fr)
Inventor
寗树梁
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to EP20937169.9A priority Critical patent/EP3965105B1/en
Priority to US17/389,636 priority patent/US11430709B2/en
Publication of WO2022011956A1 publication Critical patent/WO2022011956A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K15/00—Testing or calibrating of thermometers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K15/00—Testing or calibrating of thermometers
    • G01K15/005—Calibration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002—Characteristic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips

Definitions

  • the present invention relates to the field of memory, and in particular, to a semiconductor device.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, and its memory array area is composed of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line The data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • DRAM Dynamic Random Access Memory
  • the technical problem to be solved by the present invention is to provide a semiconductor device, which can detect the temperature of the memory chip, prevent the memory chip from starting and running at low temperature, shorten the writing time, and improve the writing stability of the memory chip; and the temperature detection
  • the module circuit has a simple structure and is easy to implement, and the temperature-sensitive unit shares the processing unit, so that the temperature detection module occupies a small area and does not affect the effective area of the memory chip; at the same time, the temperature-sensitive unit can be accurately calibrated to improve the accuracy of temperature detection.
  • the present invention provides a semiconductor device, which includes a plurality of memory chips and a temperature detection module, wherein the temperature detection module includes: a plurality of temperature sensitive units arranged on the memory chips to detect the The temperature of the memory chip; a processing unit, the processing unit is shared by a plurality of the temperature-sensitive units, the processing unit is used for processing the signal of at least one of the temperature-sensitive units, and the processing unit includes a calibration value storage unit and A calibration unit, the calibration value storage unit is configured to store a calibration value corresponding to the temperature-sensitive unit, and the calibration unit is configured to calibrate the temperature-sensitive unit according to the calibration value.
  • the temperature detection module includes: a plurality of temperature sensitive units arranged on the memory chips to detect the The temperature of the memory chip; a processing unit, the processing unit is shared by a plurality of the temperature-sensitive units, the processing unit is used for processing the signal of at least one of the temperature-sensitive units, and the processing unit includes a calibration value storage unit and A calibration unit, the calibration value storage unit is configured
  • the calibration unit is an adjustable resistor, which is connected in parallel with the temperature-sensitive unit, and the calibration unit is adjusted to a resistance value corresponding to the temperature-sensitive unit according to the calibration value, so as to calibrate the temperature-sensitive unit.
  • the calibration unit includes a plurality of sub-resistors and a plurality of switches, the sub-resistors are connected in series, and each of the switches is connected in parallel with at least one of the sub-resistors. the resistance value of the calibration unit.
  • the on-off of the switch is controlled according to the calibration value.
  • the temperature sensitive unit is a diode
  • the negative terminal of the diode is electrically connected to the ground terminal
  • the positive terminal of the diode is electrically connected to the processing unit
  • the calibration unit is connected in parallel with the temperature sensitive unit
  • the One end of the calibration unit is electrically connected to the ground terminal
  • the other end is electrically connected to the positive terminal of the diode.
  • the temperature detection module further includes a non-volatile storage unit, connected to the calibration value storage unit, for backing up the calibration value.
  • the backup is stored in the non-volatile storage unit.
  • the calibration value in the property storage unit is stored in the calibration value storage unit.
  • the processing unit includes at least one control switch, and the control switch is electrically connected to the temperature-sensitive unit to control the on-off of the temperature-sensitive unit.
  • the processing unit further includes a constant-value resistor, the constant-value resistor has a first end and a second end, the first end is electrically connected to a power source, and the second end is electrically connected to the control switch.
  • the processing unit further includes an A/D conversion module, the A/D conversion module has an input end and an output end, the input end is electrically connected with the second end of the fixed-value resistor, and the output end is used for outputting digital signal, the A/D conversion module is used to convert the analog signal at the second end of the fixed-value resistor into a digital signal.
  • the A/D conversion module has an input end and an output end, the input end is electrically connected with the second end of the fixed-value resistor, and the output end is used for outputting digital signal, the A/D conversion module is used to convert the analog signal at the second end of the fixed-value resistor into a digital signal.
  • the A/D conversion module includes: a resistance unit having a first end and a second end, the first end of the resistance unit is electrically connected to the power supply, the second end of the resistance unit is electrically connected to the ground terminal,
  • the resistance unit has a plurality of lead terminals, and the voltage of each lead end is different; a plurality of comparison units, the signal of the input end of the A/D conversion module is used as the input signal of the comparison unit, and the plurality of lead ends of the resistance unit are used as the input signal of the comparison unit.
  • the signals are respectively used as reference signals of a plurality of the comparison units, and the comparison units output digital signals.
  • the A/D conversion module further includes an encoder, and the encoder receives and encodes the output signal of the comparison unit.
  • the A/D conversion module further includes an output device connected to the comparison unit for outputting the digital signal.
  • the resistance unit includes a plurality of sub-resistors connected in series, and the number of the sub-resistors spaced between each lead end of the resistance unit and the second end of the resistance unit is different, so that the voltage of each lead end is different. different.
  • the temperature-sensitive units correspond to the storage chips one-to-one, and each of the storage chips is provided with one of the temperature-sensitive units.
  • the temperature sensitive unit and the memory chip share the same ground terminal.
  • the semiconductor device further includes a control chip, and the memory chip and the temperature detection module are electrically connected to the control chip.
  • processing unit is provided on the control chip or on one of the memory chips.
  • a plurality of the memory chips are stacked up on the control chip in sequence.
  • the semiconductor device further includes a circuit substrate, the circuit substrate has connection lines, the memory chip and the control chip are both located on the circuit substrate, and the memory chip and the control chip are connected by the connection lines in the circuit substrate.
  • control chip is used to heat the memory chip before starting the memory chip, and judge whether the temperature detected by the temperature sensitive unit reaches a set threshold, and if it reaches the set threshold, control the memory chip to start.
  • the temperature sensitive unit and the memory chip are powered by different power sources.
  • the power supply of the temperature sensitive unit is earlier than the power supply of the memory chip.
  • the advantage of the present invention is that the temperature of the memory chip is detected by the temperature detection module, and the temperature detected by the temperature detection module provides a reference for the startup and operation of the memory chip, thereby avoiding the startup and operation of the memory chip at low temperature, shortening the writing time, and improving the storage capacity.
  • the stability of chip writing in addition, the temperature detection module of the present invention has a simple circuit structure and is easy to implement, and the temperature sensitive units share the processing unit, so that the temperature detection module occupies a small area without affecting the effective area of the memory chip; The sensitive unit is precisely calibrated to improve the accuracy of temperature detection.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a semiconductor device of the present invention
  • FIG. 2 is a circuit diagram of a temperature detection module in the semiconductor device of the present invention.
  • FIG. 3 is a schematic structural diagram of a second embodiment of the semiconductor device of the present invention.
  • FIG. 4 is a circuit diagram of an embodiment of an adjustable resistor
  • FIG. 5 is a schematic structural diagram of a third embodiment of the semiconductor device of the present invention.
  • FIG. 6 is a schematic diagram of electrical connection of the first embodiment of the semiconductor device of the present invention.
  • FIG. 7 is a schematic structural diagram of a fourth embodiment of the semiconductor device of the present invention.
  • the present invention provides a semiconductor device, which uses a temperature sensitive unit to detect the temperature of the memory chip, so as to provide a reference for the start-up and operation of the memory chip, thereby preventing the memory chip from starting and operating at a low temperature, shortening the writing time, and improving the performance of the memory chip. Stability of memory chip writing.
  • the semiconductor device of the present invention can also perform self-calibration, which greatly improves the accuracy of temperature detection.
  • FIG. 1 is a schematic structural diagram of a first embodiment of the semiconductor device of the present invention
  • FIG. 2 is a circuit diagram of a temperature detection module in the semiconductor device of the present invention. Please refer to FIGS. 1 and 2.
  • the semiconductor device of the present invention includes a plurality of memory chips 100 and a temperature Detection module 110 .
  • the semiconductor device further includes a control chip 120 , the memory chip 100 and the temperature detection module 110 are electrically connected to the control chip 120 .
  • the control chip 120 is used to control the startup and operation of the memory chip 100 and the temperature detection module 110 .
  • the startup of the memory chip 100 includes power-on and self-checking, and the operation of the memory chip 100 includes writing data to the memory chip 100 , reading data from the memory chip 100 , and deleting the data accessed in the memory chip 100 . Wait.
  • the functions of the control chip 120 in controlling the startup of the memory chip 100 in the embodiment of the present invention can also be realized by setting a control circuit in the memory chip 100. In this case, the existence of the control chip 120 is not required, and the art Those skilled in the art should understand that it can be set by themselves as required.
  • the memory chip 100 is an existing memory capable of data writing, data reading and/or data deletion, and the memory chip 100 is formed by a semiconductor integrated manufacturing process.
  • the memory chip 100 may include a memory array and peripheral circuits connected to the memory array.
  • the memory array includes a plurality of memory cells and bit lines, word lines, and metal wirings (metal contact lines) connected to the memory cells. part), the storage unit is used for storing data, and the peripheral circuit is a related circuit when operating the storage array.
  • the memory chip 100 is a DRAM memory chip, and the DRAM memory chip includes a plurality of memory cells.
  • the memory cells generally include capacitors and transistors, the gates of the transistors are connected to the word lines, and the drains are connected to the word lines. It is connected to the bit line, and the source is connected to the capacitor.
  • the memory chip 100 may be other types of memory chips.
  • the temperature detection module 110 includes a plurality of temperature sensitive units 111 and a processing unit 112 .
  • a plurality of the temperature sensitive units 111 are disposed on at least part of the memory chips 100 to detect the temperature of at least part of the memory chips 100 and output analog signals corresponding to the temperatures.
  • the control chip 120 controls the memory chip 100 to start up.
  • the specific size of the set threshold can be set according to actual needs or experience.
  • the temperature sensitive unit 111 and the memory chip 100 may be in a one-to-one relationship or a one-to-many relationship.
  • the number of the memory chips 100 is multiple, the number of the temperature sensitive units 111 is also multiple, and the number of the temperature sensitive units 111 is the same as the number of the memory chips 100, the The temperature-sensitive units 111 are in a one-to-one relationship with the memory chips 100 , and one of the temperature-sensitive units 111 is disposed in one of the memory chips 100 and is used to detect the temperature of the memory chip 100 .
  • the number of the memory chips 100 is plural, and the number of the temperature sensitive units 111 is also plural, as shown in FIG. 1 , which is schematically drawn in FIG. 1 .
  • Each memory chips 100 and four temperature sensitive units 111 are shown, a plurality of the memory chips 100 are stacked and arranged, and the temperature sensitive units 111 are arranged in a one-to-one correspondence with the memory chips 100 for detecting the temperature of the memory chip 100 .
  • the The temperature sensitive unit 111 and the memory chip 100 may have a one-to-one relationship and a one-to-many relationship at the same time, or only a one-to-many relationship. That is, there may be a situation where one temperature sensitive unit 111 detects the temperature of only one memory chip 100 and one temperature sensitive unit 111 detects the temperature of multiple memory chips 100 , or only one temperature sensitive unit 111 detects a plurality of the temperature of the memory chip 100 .
  • the temperature sensitive unit 111 may be formed in the memory chip 100 through a semiconductor integrated fabrication process. If the temperature sensitive unit 111 is only used to detect the temperature of one memory chip 100, it can be formed in the memory chip 100. For example, in this embodiment, as shown in FIG. 1, the temperature sensitive unit 111 and the memory chip 100 are in one-to-one correspondence, and each memory chip 100 is provided with a temperature-sensitive unit 111 . If the temperature sensitive unit 111 is used to detect the temperature of a plurality of memory chips 100 , it may be formed in any one of the plurality of memory chips 100 , or formed in the center or the lowest memory chip 100 . Inside. For example, in the second embodiment of the present invention, please refer to FIG. 3 , which is a schematic structural diagram of the second embodiment of the semiconductor device of the present invention. The temperature sensitive unit 111 is disposed on the bottommost memory chip 100 and the third memory chip in the middle. 100, it can measure the temperature of the four memory chips 100.
  • the processing unit 112 is shared by a plurality of the temperature sensitive units 111 , and the processing unit 112 is used for processing the signal of at least one of the temperature sensitive units 111 .
  • the processing unit 112 is shared by a plurality of the temperature sensitive units 111 of the semiconductor device of the present invention, so that the occupied area of the temperature detection module is greatly reduced, and the effective area of the memory chip is not affected.
  • the semiconductor device of the present invention includes a plurality of temperature sensitive units 111. If the plurality of temperature sensitive units 111 are calibrated with the same calibration value, errors will occur. Therefore, the semiconductor device of the present invention performs targeted calibration on different temperature sensitive units 111, which greatly improves the accuracy of temperature detection.
  • the processing unit 112 includes a calibration value storage unit 1123 and a calibration unit 1124 .
  • the calibration value storage unit 1123 is used for storing the calibration value corresponding to the temperature sensitive unit 111 .
  • the temperature detection module 110 includes four temperature sensitive units 111, and each temperature sensitive unit 111 corresponds to a calibration value.
  • the calibration unit 1124 is used for calibrating the temperature sensitive unit 111 according to the calibration value. For example, when the processing unit 112 performs signal processing on the first temperature sensitive unit 111, the calibration unit 1124 calibrates the first temperature sensitive unit 111 according to the calibration value corresponding to the first temperature sensitive unit 111.
  • the calibration unit 1124 calibrates the second temperature sensitive unit 111 according to the calibration value corresponding to the second temperature sensitive unit 111, and so on, so as to be able to The purpose of performing targeted calibration on different temperature sensitive units 111 is achieved, calibration errors are avoided, and the accuracy of temperature measurement is improved.
  • control chip 120 can control the calibration unit 1124 to calibrate the temperature sensitive unit 111 according to the calibration value in the calibration value storage unit 1123 .
  • the calibration unit 1124 is an adjustable resistor, which is connected in parallel with the temperature sensitive unit 111 .
  • the control chip 120 can control the calibration unit 1124 according to the calibration value, so that the resistance value of the calibration unit 1124 is adjusted to a suitable resistance value corresponding to the temperature-sensitive unit 111 , so as to calibrate the temperature-sensitive unit 111 .
  • the calibration value is a resistance value, and each temperature sensitive unit 111 corresponds to a resistance value.
  • FIG. 4 is a circuit diagram of an embodiment of an adjustable resistor.
  • the adjustable resistor includes a plurality of sub-resistors R1n and a plurality of switches S1n.
  • the sub-resistors R1n are connected in series, each switch S1n is connected in parallel with at least one of the sub-resistors R1n, and the resistance value of the adjustable resistor can be changed by changing the on-off of a plurality of the switches S1n.
  • sub-resistors R11-R15 and switches S11-S15 are schematically shown, and each sub-resistor is connected in parallel with a switch.
  • the sub-resistor R11 is connected in parallel with the switch S11
  • the sub-resistor R12 is connected in parallel with the switch S12
  • the sub-resistor R13 is connected in parallel with the switch S13
  • the sub-resistor R14 is connected in parallel with the switch S14
  • the sub-resistor R15 is connected in parallel with the switch S15.
  • two or more sub-resistors may also be connected in series and then connected in parallel with one switch.
  • R13 is connected in series with switch S11 in parallel.
  • the on-off of the switch S1n is controlled according to the calibration value, so as to change the resistance value of the adjustable resistor.
  • the resistance value corresponding to the calibration value is greater than the resistance value of the current adjustable resistance, that is, the resistance value of the adjustable resistance needs to be increased, then the switch S1n is turned off, and the sub-resistor connected in parallel with it is connected to the circuit;
  • the switch S1n is turned on, so that the switch S1n is connected to the circuit, and the The parallel sub-resistors are disconnected.
  • the switch S11 when the resistance value of the adjustable resistor needs to be increased, the switch S11 is turned off, and the sub-resistor R11 connected in parallel with the switch S11 is connected to the circuit; when the adjustable resistor needs to be decreased When the resistance value of the resistor is reached, the switch S11 is turned on, so that the switch S11 is connected to the circuit, and the sub-resistor R11 connected in parallel with it is short-circuited.
  • the resistance values of the sub-resistors R1n are the same, so as to simplify the difficulty of layout layout, which is simple and easy to implement, and convenient for manufacture.
  • the sub-resistor R1n is a polysilicon resistor or an N-type diffused resistor or a P-type diffused resistor. Further, the sub-resistors R1n are electrically connected through a first layer of metal wires, and the sub-resistors R1n and the switch S1n are electrically connected through a second layer of metal wires. This approach enables further ease of manufacture, improved stability and accuracy.
  • the switch S1n can be a transistor, such as an NMOS transistor or a PMOS transistor, which has a stable structure and is easy to manufacture.
  • adjustable resistance unit 1111 provided by the present invention.
  • other circuit structures may also be used to implement the adjustable resistance unit 1111 .
  • the temperature detection module 110 further includes a non-volatile storage unit 113 .
  • the non-volatile storage unit 113 is connected to the calibration value storage unit 1123 for backing up the calibration value.
  • the non-volatile storage unit 113 can back up the calibration value according to a preset period.
  • the preset period may be a preset time period after the semiconductor device is powered on. For example, after the semiconductor device is powered on, the calibration value is backed up in the non-volatile storage unit 113 in a cycle of 10 minutes, that is, after the semiconductor device is powered on.
  • the calibration value is backed up in the non-volatile storage unit every ten minutes; or the calibration value is backed up in the non-volatile storage unit every one hour as a cycle, that is, after the semiconductor device is powered on, it will be stored in the non-volatile storage unit every one hour.
  • the calibration value code is backed up in the nonvolatile storage unit 113 .
  • the non-volatile storage unit 113 can also store the calibration value in the chip when the chip is factory-set, and the semiconductor device will first store the calibration value in the non-volatile storage unit 113 each time it is powered on and used subsequently.
  • the calibration value is imported into the calibration value storage unit 1123 .
  • the semiconductor device of the present invention backs up the calibration value in the non-volatile storage unit 113. If the semiconductor device is powered off, the calibration value will still be recorded in the non-volatile storage unit 113 and will not be cleared, and can be used as a reference for subsequent calibration. in accordance with.
  • the calibration value backed up in the nonvolatile storage unit 113 can be loaded into the calibration value storage unit 1123 again.
  • the loaded calibration value is used as a reference for subsequent calibration, so as to avoid the situation that the calibration value is lost due to the power failure of the semiconductor device.
  • the processing unit 112 includes at least one control switch Sx, and the control switch Sx is electrically connected to the temperature detection unit 111 to select the temperature detection unit 111 that needs to be processed by the processing unit 112 .
  • the control switch Sx is closed, the temperature sensitive unit 111 is electrically connected to the processing unit 112 , and when the control switch Sx is open, the temperature sensitive unit 111 is electrically connected to the processing unit 112 Disconnect the electrical connection.
  • the temperature sensitive unit 111 is a diode, the negative terminal of the diode is electrically connected to the ground terminal VSS, and the positive terminal of the diode is electrically connected to the processing unit 112 through the control switch Sx,
  • the calibration unit 1124 is connected in parallel with the diode, one end of the calibration unit 1124 is electrically connected to the ground terminal VSS, and the other end is electrically connected to the positive end of the diode through the control switch Sx.
  • the diode is sensitive to temperature, and as the temperature of its surrounding environment changes, its current changes, which can then be used to measure the temperature of the surrounding environment.
  • control switches Sx are in one-to-one correspondence with the temperature sensitive units 111 , that is, one control switch is electrically connected to one temperature sensitive unit 111 to realize precise control.
  • the number of the temperature sensitive units 111 is four
  • the processing unit 112 includes four control switches S1-S4, each control switch is electrically connected to one temperature sensitive unit 111, to control the electrical connection between the corresponding temperature sensitive unit 111 and the processing unit 112 .
  • the control chip 120 can obtain the calibration value corresponding to the temperature sensitive unit 111 turned on by the closed control switch, and adjust the calibration unit 1124 according to the calibration value, thereby calibrating the temperature sensitive unit 111 .
  • the control switch S1 when the electrical signal of the temperature sensitive unit 111 corresponding to the control switch S1 needs to be processed, the control switch S1 is closed, and the other control switches are disconnected, so that the temperature sensitive unit 111 corresponding to the control switch S1 is electrically connected to the processing unit 112, The signal processing is realized, and at the same time, the control chip 120 obtains the calibration value corresponding to the temperature sensitive unit 111 turned on by the control switch S1, and adjusts the calibration unit 1124 according to the calibration value, so as to perform the calibration on the temperature sensitive unit 111.
  • the control switch S2 when the electrical signal of the temperature sensitive unit 111 corresponding to the control switch S2 needs to be processed, the control switch S2 is closed, and the other control switches are disconnected, so that the temperature sensitive unit 111 corresponding to the control switch S2 is electrically connected to the processing unit 112, The signal processing is realized.
  • the control chip 120 obtains the calibration value corresponding to the temperature sensitive unit 111 turned on by the control switch S2, and adjusts the calibration unit 1124 according to the calibration value, so that the temperature sensitive unit 111 is adjusted.
  • the control switch S3 when the electrical signal of the temperature sensitive unit 111 corresponding to the control switch S3 needs to be processed, the control switch S3 is closed, and other control switches are disconnected, so that the temperature sensitive unit 111 corresponding to the control switch S3 is electrically connected to the processing unit 112, The signal processing is realized.
  • the control chip 120 obtains the calibration value corresponding to the temperature sensitive unit 111 turned on by the control switch S3, and adjusts the calibration unit 1124 according to the calibration value, so as to perform the calibration on the temperature sensitive unit 111.
  • one end of the control switch Sx is electrically connected to the temperature sensitive unit 111, and the other end is connected to the calibration unit 1124, that is, the temperature sensitive unit 111 and the calibration unit 1124 are respectively connected to the control switch Sx
  • the calibration unit 1124 and the temperature sensitive unit 111 are both connected to the same end of the control switch Sx, that is, the calibration unit 1124 and the temperature sensitive unit 111 are all electrically connected to one end or the other end of the control switch Sx.
  • the processing unit 112 further includes a constant value resistor Ra and an A/D conversion module 1121 .
  • the constant value resistor Ra has a first end and a second end.
  • the first terminal is electrically connected to the power supply Vtemp, and the second terminal is electrically connected to the control switch Sx.
  • the A/D conversion module 1121 has an input end and an output end, the input end is electrically connected to the second end of the fixed-value resistor Ra, and the output end is used for outputting digital signals, and the A/D conversion module 1121 is used to convert the analog signal at the second end of the fixed-value resistor Ra into a digital signal.
  • the A/D conversion module 1121 includes a resistance unit and a plurality of comparison units Px.
  • the resistance unit has a first end and a second end.
  • the first end of the resistance unit is electrically connected to a power source.
  • the resistance unit and the temperature sensitive unit 111 may use the same power supply, or may use different power supplies.
  • the A/D conversion module 1121 is set in the memory chip 100, the first end of the resistance unit and the temperature sensitive unit 111 can use the same power supply Vtemp; if the A/D conversion module 1121 is set In the control chip 120, the first end of the resistance unit and the temperature sensitive unit 111 may use different power supplies, and the resistance unit may use the power supply VDD.
  • the second terminal of the resistance unit is electrically connected to the ground terminal VSS.
  • the resistance unit has a plurality of lead-out terminals Ax, and the voltage of each lead-out terminal Ax is different.
  • the resistance unit includes a plurality of sub-resistors Rx connected in series, and the number of the sub-resistors Rx spaced between each lead end Ax of the resistance unit and the second end of the resistance unit is different, So that the voltage of each terminal Ax is different.
  • a sub-resistor R1 is spaced between the lead-out terminal A1 and the second end of the resistance unit, and sub-resistors R1 and R2 are spaced between the lead-out end A2 and the second end of the resistance unit, so the voltages of the lead-out end A1 and the lead-out end A2 are different.
  • the number of sub-resistors Rx spaced between each lead end Ax of the resistance unit and the second end of the resistance unit is incremented by a preset value.
  • the preset value may be a certain value or a variable value. Referring to FIG. 2 , in this embodiment, the number of sub-resistors Rx spaced between each lead end Ax of the resistance unit and the second end of the resistance unit increases by a constant value of 1. However, in other embodiments of the present invention, the fixed value can also be incremented by 2 or the like.
  • the preset value is a variable value
  • the preset value has a changing trend. The change trend is set according to the voltage increase of the lead-out terminal Ax.
  • the change trend of the preset value is increased; if the voltage of the lead-out end Ax is increased If the increase is decreasing, the change trend of the preset value is decreasing; if the voltage increase of the lead terminal Ax is increasing first and then decreasing, the change trend of the preset value is increasing first and then decreasing.
  • the resistance values of the sub-resistors Rx are the same or different, so that the voltage increase changes between the lead-out terminals Ax are consistent or inconsistent. Wherein, if the resistance values of the sub-resistors Rx are the same, the difficulty of layout layout can be simplified, which is simple and easy to implement, and convenient for manufacture.
  • the signal at the input end of the A/D conversion module is used as the input signal of the comparison unit Px, that is, the analog signal output by the temperature sensitive unit is used as the input signal of the comparison unit Px.
  • the signals of the multiple terminals Ax of the resistance unit are respectively used as the reference signals of the multiple comparison units Px.
  • the lead-out terminal Ax corresponds to the comparison unit Px one-to-one.
  • the signal of the lead-out terminal A1 is used as the reference signal of the comparison unit P1
  • the signal of the lead-out terminal A2 is used as the reference signal of the comparison unit P2, and so on, the lead-out terminal Ax and the comparison unit Px are one A correspondence.
  • the comparison unit Px outputs a digital signal. According to the digital signal output by the comparison unit Px, the temperature of the memory chip 100 detected by the temperature sensitive unit 111 can be obtained.
  • the voltage of the lead end Ax changes unevenly , so that the reference signals of the plurality of comparison units Px change non-uniformly, and in different voltage regions, the reference signals of the comparison units Px have different amplitudes, which can change the measurement accuracy of the voltage region.
  • the preset value is changed in a small range, so that the increase of the reference signal is small, the number of signal sampling points is increased, and the measurement accuracy of the region is improved.
  • the preset value is greatly changed, so that the increase of the reference signal is large, the number of signal sampling points is reduced, and the measurement efficiency is improved.
  • the voltage region that needs to be accurately measured is 1.2V-1.7V
  • the corresponding reference signal range is 1.2V-1.7V
  • the preset The increase of the set value is small.
  • the increase of the preset value is 1, so that the increase of the reference signal is 0.1V, so that the number of sampling points in the voltage region can be increased, and the measurement accuracy can be improved.
  • the increase of the preset value is large, for example, the increase of the preset value is 3, so that the increase of the reference signal is 0.3V, and the number of sampling points is appropriately reduced to improve the measurement efficiency.
  • the A/D conversion module 1121 further includes an output unit 1122, the output unit 1122 is connected to the comparison unit Px, and is used for outputting the digital signal. Further, in this embodiment, the A/D conversion module 1121 further includes an encoding unit EEC, the encoding unit EEC receives the digital signal output by the comparison unit Px, and performs encoding, and the formed signal is input to the output Unit 1120, the output unit 1122 outputs the encoded digital signal.
  • the processing unit 112 is disposed on the control chip 120 or disposed on one of the memory chips 100 .
  • the processing unit 112 is disposed on the control chip 120 .
  • the processing unit 112 is disposed on one of the memory chips 100 .
  • FIG. 5 which is a schematic structural diagram of a third embodiment of the semiconductor device of the present invention, in this embodiment, the processing unit 112 is disposed on the memory chip 100 at the bottom layer.
  • FIG. 6 is a schematic diagram of electrical connection of the semiconductor device according to the first embodiment of the present invention. Please refer to FIG. 6 .
  • the temperature sensitive unit 111 is powered by the power supply Vtemp
  • the memory chip 100 is powered by the VDD.
  • the ground terminal VSS, the power supply VDD and the power supply Vtemp are provided by the control chip 120 . Since the temperature sensitive unit 111 and the memory chip 100 are powered by different power sources, the power supplies of the temperature sensitive unit 111 and the memory unit 100 can be independently controlled, so as to realize the The memory chip 100 is not activated at the same time.
  • the present invention can control the activation of the temperature sensitive unit 111 and the memory chip 100 respectively, that is, the activation of the temperature sensitive unit 111 is not affected by whether the memory chip 100 is activated, so that the detection of the temperature of the memory chip 100 is not affected by the memory chip 100.
  • the influence of whether the chip 100 is started can provide a reference for the start and operation of the memory chip 100 , thereby preventing the memory chip 100 from starting or running at a low temperature, and improving the stability of the memory chip 100 .
  • temperature has a great influence on the performance of the memory chip 100 , especially when the memory chip 100 is activated. If the memory chip 100 is started at a low temperature, the time for writing data into the memory chip 100 will change (eg, lengthen), which will affect the stability of the memory chip 100 writing. temperature so that the memory chip 100 can be activated within a suitable temperature.
  • the power supply of the temperature sensitive unit 111 in the present invention is earlier than the power supply of the memory chip 100 , that is, before the memory chip 100 is started, the temperature sensitive unit 111 has been started, so that the temperature before the start of the memory chip 100 can be obtained.
  • the temperature provides a reference for the startup of the memory chip 100 .
  • the power supply time difference between the temperature sensitive unit 111 and the memory chip 100 depends on the temperature change rate of the memory chip 100.
  • the temperature change rate of the memory chip 100 is large, the time it takes for the memory chip 100 to reach the preset temperature If the power supply time difference between the temperature sensitive unit 111 and the memory chip 100 is small, if the temperature change rate of the memory chip 100 is small and the time for the memory chip 100 to reach the preset temperature is long, the temperature sensitive The power supply time difference between the unit 111 and the memory chip 100 is large.
  • the temperature sensitive unit 111 and the memory chip 100 share the same ground terminal VSS.
  • the advantage is that, on the one hand, the leakage current of the memory chip 100 in the non-starting stage will not be increased, and on the other hand, the number of pins will be reduced and space will be saved.
  • the memory chip 100 is formed with a through-silicon via interconnection structure 101 , and the memory chip 100 and the control chip 120 are electrically connected through the through-silicon via interconnection structure 101 , and the temperature-sensitive unit 111 is electrically connected to the control chip 120 .
  • the processing unit 112 is electrically connected.
  • the memory chip 100 is electrically connected to the ground terminal VSS and the power supply VDD through the through silicon via interconnection structure 101
  • the temperature sensitive unit 111 is electrically connected to the power supply Vtemp and the ground terminal VSS.
  • each memory chip 100 when a plurality of memory chips 100 are stacked, each memory chip 100 can be connected to the control chip 120 through different through-silicon via interconnect structures; when there are a plurality of temperature-sensitive units 111 , there may be each In the case where one temperature sensitive unit 111 is connected to the processing unit 112 through different through silicon via interconnection structures, there may also be a situation where multiple temperature sensitive units 111 share the through silicon via interconnection structure to be connected to the processing unit 112 . It can be understood that the memory chip 100 and the temperature sensitive unit 111 are connected to the power supply through different through silicon via interconnect structures, so that the temperature sensitive unit 111 and the memory chip 100 can be powered by different power sources . Further, the power supply of a plurality of the temperature sensitive units 111 may also share the TSV interconnection structure.
  • the memory chip 100 and the temperature sensitive unit 111 may also be electrically connected to the control chip 120 and the processing unit 112 through metal wires (formed by a wire bonding process).
  • FIG. 7 is a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present invention.
  • the semiconductor device further includes a circuit substrate 130 having connections in the circuit substrate 130 . Circuits (not shown in the drawings), the memory chips 100 and the control chips 120 are both located on the circuit substrate 130 , and the memory chips 100 and the control chips 120 are connected by connecting lines in the circuit substrate 130 .
  • the temperature sensitive unit 111 is provided in the memory chip 100
  • the processing unit 112 is provided in the control chip 120 .
  • the circuit substrate 130 includes but is not limited to a PCB circuit board.
  • the semiconductor device of the present invention uses the temperature detection module to detect the temperature of the memory chip.
  • the temperature detected by the temperature detection module reaches the set threshold, or after the temperature of the memory chip 100 reaches the set threshold, the memory chip is activated and the temperature
  • the temperature detected by the detection module provides a reference for the startup and operation of the memory chip, thereby preventing the memory chip from starting and operating at low temperature, shortening the writing time, and improving the writing stability of the memory chip.
  • the control chip 120 of the present invention can also be started before the memory chip 100 is started, and the control chip 120 uses the heat generated by itself to heat the memory chip 100 after being started to rapidly increase the temperature of the memory chip 100 .
  • control chip 120 controls the temperature sensitive unit 111 to start up to detect the temperature of the memory chip 100 .
  • the temperature sensitive unit 111 can also transmit the detected temperature to the control chip 120 as data of the control chip 120 .
  • the control chip 120 can determine whether the temperature detected by the temperature sensitive unit 111 reaches the set threshold, and if the temperature reaches the set threshold, the memory chip 100 is controlled to start up.
  • the control unit 120 determines that the temperature detected by the temperature sensitive unit 111 reaches the set threshold, the control unit 120 first controls the distance from the control chip 120 The most recent memory chip 100 is activated, and then the other memory chips 100 above are controlled to be activated in sequence.
  • the control unit 120 determines that the temperature detected by a temperature-sensitive unit 111 reaches a set threshold, and then controls the storage corresponding to the temperature-sensitive unit 111 Chip 100 starts up.
  • the control unit 120 determines that the temperature detected by a temperature-sensitive unit 111 reaches a set threshold, and then controls the storage corresponding to the temperature-sensitive unit 111 Chip 100 starts up.
  • there are 4 memory chips 100 in the stacked structure as shown in FIG. 1 and each memory chip 100 has a corresponding temperature sensitive unit 111 , so each temperature sensitive unit 111 can affect the temperature of the corresponding memory chip 100 .
  • the control chip 120 will sequentially determine whether the temperature detected by the four temperature sensitive units 111 reaches the set threshold value, if the temperature detected by a certain temperature sensitive unit 111 reaches the set threshold value , then control the memory chip corresponding to the temperature sensitive unit 111 to start up. For example, when the temperature detected by the temperature sensitive unit 111 in the bottommost memory chip 100 in the stack structure first reaches the set threshold, the control chip 120 first controls the stack structure. The memory chip 100 at the bottom layer starts up, and then, when the temperature detected by the temperature sensitive unit 111 corresponding to the memory chip 100 in the penultimate layer in the stack structure also reaches the set threshold, the control unit 301 then controls the memory chip 100 in the stack structure. The memory chip 100 in the penultimate layer is activated, and the memory chips 100 in the upper two layers are activated and so on.
  • the aforementioned control structure and control method can further improve the accuracy of the start-up timing of each memory chip 100, and can further reduce the need for each memory chip 100 in a low temperature environment.
  • the writing time during data writing further improves the stability of writing to each memory chip 100 .
  • the temperature of the memory chip 100 can be increased to a set threshold by controlling the chip 120, thereby preventing the bit lines, word lines, and metal connections (metal contacts) in the memory chip 100 from being
  • the resistance increases due to the low ambient temperature, thereby reducing the writing time when writing data to the storage chip in a low temperature environment, and improving the writing stability of the storage chip.
  • the set threshold can be set in the control chip 120, and the specific size of the set threshold can be set according to actual needs or experience.
  • control chip 120 may have an additional heating circuit (not shown in the drawings).
  • the heating circuit is used for heating the memory chip 100 . Before or after the control chip 120 heats the memory chip 100, the control chip 120 judges whether the temperature of the memory chip 100 detected by the temperature sensitive unit 111 reaches the set threshold, and if it does not reach the set threshold, Then, the heating circuit is controlled to heat the memory chip 100 , and if the set threshold is reached, the heating circuit is controlled to stop heating the memory chip 100 . In this way, precise control of the heating process is achieved, so that the temperature of the memory chip 100 can be kept near the set threshold, preventing the temperature of the memory chip 100 from being too high or too low, so that the writing time to the memory can always be kept short.

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Abstract

一种半导体装置，其包括多个存储芯片（100）、温度检测模块（110），温度检测模块（110）包括：多个温度敏感单元（111），设置在存储芯片（100）上，以检测存储芯片（100）的温度；处理单元（112），多个温度敏感单元（111）共用处理单元（112），处理单元（112）用以对至少一温度敏感单元（111）的信号进行处理，处理单元（112）包括校准值存储单元（1123）及校准单元（1124），校准值存储单元（1123）用于存储与温度敏感单元（111）对应的校准值，校准单元（1124）用于根据校准值校准温度敏感单元（111）。温度检测模块（110）检测的温度为存储芯片（100）的启动及运行提供参考，从而避免存储芯片（100）在低温下启动及运行，提高存储芯片（100）写入的稳定性。另外，温度敏感单元（111）共用处理单元（112），使得温度检测模块（110）占用面积小，且能够对温度敏感单元（111）进行精确校准，提高测量准确度。

Description

半导体装置
相关申请引用说明
本申请要求于2020年07月17日递交的中国专利申请号202010689795.7，申请名为“半导体装置”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及存储器领域，尤其涉及一种半导体装置。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其存储阵列区由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
温度对存储器写入存在较大影响，在低温环境中，对存储器进行写入时，存在写入时间较长，写入的稳定性不高的问题。
发明内容
本发明所要解决的技术问题是，提供一种半导体装置，其能够检测存储芯片的温度，避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性；且温度检测模块电路结构简单，易于实现，温度敏感单元共用处理单元，使得温度检测模块占用面积小，不会对存储芯片有效面积产生影响；同时能够对温度敏感单元进行精确校准，提高温度检测的准确度。
为了解决上述问题，本发明提供了一种半导体装置，其包括多个存储芯片、温度检测模块，所述温度检测模块包括：多个温度敏感单元，设置在所述存储芯片上，以检测所述存储芯片的温度；处理单元，多个所述温度敏感单元共用所述处理单元，所述处理单元用以对至少一所述温度敏感单元的信号进行处理，所述处理单元包括校准值存储单元及校准单元，所述校准值存储单元用于存储与所述温度敏感单元对应的校准值，所述校准单元用于根据所述校准值校准所述温度敏感单元。
进一步，所述校准单元为可调电阻，其与所述温度敏感单元并联，所述校准单元根据所述校准值调节为与所述温度敏感单元对应的电阻值，以校准所述温度敏感单元。
进一步，所述校准单元包括多个子电阻及多个开关，所述子电阻串联连接，每一所述 开关至少与一个所述子电阻并联，通过改变多个所述开关的通断，来改变所述校准单元的电阻值。
进一步，根据所述校准值控制所述开关的通断。
进一步，所述温度敏感单元为二极管，所述二极管的负端与接地端电连接，所述二极管的正端与所述处理单元电连接，所述校准单元与所述温度敏感单元并联，所述校准单元的一端与接地端电连接，另一端与所述二极管的正端电连接。
进一步，所述温度检测模块还包括一非易失性存储单元，与所述校准值存储单元连接，用于备份所述校准值，当所述半导体装置上电时，备份在所述非易失性存储单元中的校准值存储至所述校准值存储单元中。
进一步，所述处理单元包括至少一控制开关，所述控制开关与所述温度敏感单元电连接，以控制所述温度敏感单元的通断。
进一步，所述处理单元还包括定值电阻，所述定值电阻具有第一端及第二端，所述第一端与电源电连接，所述第二端与所述控制开关电连接。
进一步，所述处理单元还包括A/D转换模块，所述A/D转换模块具有输入端及输出端，所述输入端与定值电阻的第二端电连接，所述输出端用于输出数字信号，所述A/D转换模块用于将所述定值电阻第二端的模拟信号转换为数字信号。
进一步，所述A/D转换模块包括：电阻单元，具有第一端及第二端，所述电阻单元的第一端与电源电连接，所述电阻单元的第二端与接地端电连接，所述电阻单元具有多个引出端，每一引出端的电压不同；多个比较单元，所述A/D转换模块输入端的信号作为所述比较单元的输入信号，所述电阻单元的多个引出端信号分别作为多个所述比较单元的参考信号，所述比较单元输出数字信号。
进一步，所述A/D转换模块还包括编码器，所述编码器接收所述比较单元的输出信号，并进行编码。
进一步，所述A/D转换模块还包括输出器，所述输出器与所述比较单元连接，用于将所述数字信号输出。
进一步，所述电阻单元包括多个串联连接的子电阻，所述电阻单元的每一引出端与所述电阻单元的第二端之间间隔的子电阻的数量不同，以使每一引出端的电压不同。
进一步，所述温度敏感单元与所述存储芯片一一对应，在每一所述存储芯片上均设置有一个所述温度敏感单元。
进一步，所述温度敏感单元与所述存储芯片共用同一接地端。
进一步，所述半导体装置还包括控制芯片，所述存储芯片及所述温度检测模块与所述控制芯片电连接。
进一步，所述处理单元设置在所述控制芯片上或者设置在其中一个所述存储芯片上。
进一步，多个所述存储芯片依次向上堆叠在所述控制芯片上。
进一步，所述半导体装置还包括线路基板，所述线路基板中具有连接线路，所述存储芯片以及控制芯片均位于线路基板上，所述存储芯片和控制芯片通过线路基板中的连接线路连接。
进一步，所述控制芯片用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度敏感单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
进一步，所述温度敏感单元与所述存储芯片采用不同的电源供电。
进一步，所述温度敏感单元的供电早于所述存储芯片的供电。
本发明的优点在于，利用温度检测模块检测存储芯片的温度，温度检测模块检测的温度为存储芯片的启动及运行提供参考，从而避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性；另外，本发明温度检测模块电路结构简单，易于实现，温度敏感单元共用处理单元，使得温度检测模块占用面积小，不会对存储芯片有效面积产生影响；同时能够对温度敏感单元进行精确校准，提高温度检测的准确度。
附图说明
图1是本发明半导体装置的第一实施例的结构示意图；
图2是本发明半导体装置中温度检测模块的电路图；
图3是本发明半导体装置第二实施例的结构示意图；
图4是可调电阻一实施例的电路图；
图5是本发明半导体装置第三实施例的结构示意图；
图6是本发明半导体装置的第一实施例的电连接示意图；
图7是本发明半导体装置的第四实施例的结构示意图。
具体实施方式
下面结合附图对本发明提供的半导体装置的实施例做详细说明。
如背景技术所言，温度对存储器写入存在较大影响，在低温环境中，对存储器进行写入时，存在写入时间较长，写入的稳定性不高的问题。
研究发现，现有的存储器工作在低温环境中时，由于温度下降会使得存储器中的位线、字线、以及金属连线(金属接触部)等的电阻会增大，电阻的增大，会使得向存储器中写入数据时的时间会变化或加长，影响了存储器写入的稳定性。
因此，本发明提供一种半导体装置，其采用温度敏感单元检测所述存储芯片的温度，以为存储芯片的启动及运行提供参考，从而避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性。同时，本发明半导体装置还能够进行自校准，大大提高了温度检测的准确度。
图1是本发明半导体装置的第一实施例的结构示意图，图2是本发明半导体装置中温度检测模块的电路图，请参阅图1及图2，本发明半导体装置包括多个存储芯片100及温度检测模块110。
进一步，所述半导体装置还包括控制芯片120，所述存储芯片100及所述温度检测模块110与所述控制芯片120电连接。所述控制芯片120用于控制所述存储芯片100及所述温度检测模块110的启动及运行。所述存储芯片100的启动包括上电以及自检测，所述存储芯片100的运行包括向存储芯片100中写入数据，从存储芯片100读取数据，以及将存储芯片100中存取的数据删除等。需要注意的是，本发明实施例中控制芯片120在控制存储芯片100启动等方面的功能，也可通过在存储芯片100设置控制电路来实现，此时，可无需控制芯片120的存在，本领域内技术人员应当理解，可根据需要自行设置。
所述存储芯片100为现有能进行数据写入、数据读取和/或数据删除的存储器，所述存储芯片100通过半导体集成制作工艺形成。具体的说，所述存储芯片100可以包括存储阵列和与存储阵列连接的外围电路，所述存储阵列包括多个存储单元和与存储单元连接的位线、字线、以及金属连线(金属接触部)，所述存储单元用于存储数据，所述外围电路为在对存储阵列进行操作时的相关电路。本实施例中，所述存储芯片100为DRAM存储芯片，所述DRAM存储芯片中包括多个存储单元，所述存储单元通常包括电容器和晶体管，所述晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连。在其他实施例中所述存储芯片100可以为其他类型的存储芯片。
所述温度检测模块110包括多个温度敏感单元111及处理单元112。
多个所述温度敏感单元111设置在至少部分所述存储芯片100上，以检测至少部分所述存储芯100片的温度，并输出与所述温度对应的模拟信号。当所述温度敏感单元111检测的温度达到设定阈值时，所述控制芯片120控制所述存储芯片100启动。其中，设定阈 值的具体大小可以根据实际需要或者经验进行设定。
所述温度敏感单元111与所述存储芯片100可为一对一关系，或者一对多关系。
当所述存储芯片100的个数为多个，所述温度敏感单元111的个数也为多个，且所述温度敏感单元111的个数与所述存储芯片100的个数相同时，所述温度敏感单元111与所述存储芯片100为一对一关系，一个所述温度敏感单元111设置在一个所述存储芯片100中，且用于检测该存储芯片100的温度。具体地说，在本实施例中，所述存储芯片100的个数为多个，所述温度敏感单元111的个数也为多个，如图1所示，在图1中示意性地绘示四个存储芯片100及四个温度敏感单元111，多个所述存储芯片100堆叠设置，所述温度敏感单元111与所述存储芯片100一一对应设置，用于检测该存储芯片100的温度。
当所述存储芯片100的个数为多个，所述温度敏感单元111的个数也为多个，但所述温度敏感单元111的个数小于所述存储芯片100的个数时，所述温度敏感单元111与所述存储芯片100可能同时存在一对一关系及一对多关系，或者仅存在一对多关系。即可能存在一个所述温度敏感单元111仅检测一个存储芯片100的温度和一个温度敏感单元111检测多个所述存储芯片100的温度的情况，或者仅存在一个温度敏感单元111检测多个所述存储芯片100的温度的情况。
进一步，所述温度敏感单元111可通过半导体集成制作工艺形成在存储芯片100中。若所述温度敏感单元111仅用于检测一个存储芯片100的温度，则其可形成在该存储芯片100中，例如，在本实施例中，如图1所示，温度敏感单元111与存储芯片100一一对应，在每一存储芯片100中均设置一个温度敏感单元111。若所述温度敏感单元111用于检测多个存储芯片100的温度时，其可形成在该多个存储芯片100中的任意一个存储芯片100内，或者形成在居中的或最底层的存储芯片100内。例如，在本发明第二实施例中，请参阅图3，其为本发明半导体装置第二实施例的结构示意图，温度敏感单元111设置在最底层的存储芯片100及居中的第三个存储芯片100内，其能够测量四个存储芯片100的温度。
多个所述温度敏感单元111共用所述处理单元112，所述处理单元112用以对至少一所述温度敏感单元111的信号进行处理。
本发明半导体装置的多个所述温度敏感单元111共用所述处理单元112，使得温度检测模块的占用面积大大减小，不会对存储芯片有效面积产生影响。
本发明半导体装置包括多个温度敏感单元111，若是多个温度敏感单元111均采用相同的校准值进行校准，会导致出现误差。因此，本发明半导体装置对不同的温度敏感单元111 进行有针对性地校准，大大提高了温度检测的准确度。
具体地说，请继续参阅图2，所述处理单元112包括校准值存储单元1123及校准单元1124。所述校准值存储单元1123用于存储与所述温度敏感单元111对应的校准值。例如，在本实施例中，所述温度检测模块110包括四个温度敏感单元111，则每一温度敏感单元111对应一校准值。所述校准单元1124用于根据所述校准值校准所述温度敏感单元111。例如，当处理单元112对第一个温度敏感单元111进行信号处理时，所述校准单元1124根据第一个温度敏感单元111对应的校准值对该第一个温度敏感单元111进行校准，当处理单元112对第二个温度敏感单元111进行信号处理时，所述校准单元1124根据第二个温度敏感单元111对应的校准值对该第二个温度敏感单元111进行校准，依此类推，从而能够实现对不同的温度敏感单元111进行针对性校准的目的，避免校准误差，提高温度测量的准确度。
进一步，所述控制芯片120能够控制所述校准单元1124根据所述校准值存储单元1123中的校准值对温度敏感单元111进行校准。
在第一实施例中，所述校准单元1124为可调电阻，其与所述温度敏感单元111并联。所述控制芯片120能够根据所述校准值控制所述校准单元1124，使其电阻值调节为与所述温度敏感单元111对应的适合电阻值，以校准所述温度敏感单元111。可以理解的是，在该实施例中，所述校准值为电阻值，每一温度敏感单元111对应一电阻值。
本实施例列举了一种可调电阻的电路结构。请参阅图4，其为可调电阻一实施例的电路图，所述可调电阻包括多个子电阻R1n及多个开关S1n。其中，所述子电阻R1n串联连接，每一所述开关S1n至少与一个所述子电阻R1n并联，通过改变多个所述开关S1n的通断，来改变所述可调电阻的电阻值。
在该实施例中，示意性地绘示了子电阻R11～R15，开关S11～S15，每一个子电阻均与一个开关并联。具体地说，子电阻R11与开关S11并联，子电阻R12与开关S12并联，子电阻R13与开关S13并联，子电阻R14与开关S14并联，子电阻R15与开关S15并联。在本发明其他实施例中，也可是两个及以上子电阻串联后与一个开关并联，例如，子电阻R11与子电阻R12串联后与开关S11并联，或子电阻R11、子电阻R12及子电阻R13串联后与开关S11并联。
其中，根据所述校准值控制所述开关S1n的通断，以改变所述可调电阻的电阻值。当所述校准值对应的电阻值大于当前可调电阻的电阻值时，即需要增大所述可调电阻的电阻值，则断开所述开关S1n，使与其并联的子电阻接入电路；当所述校准值对应的电阻值小于 当前可调电阻的电阻值时，即需要减小所述可调电阻的电阻值，则接通所述开关S1n，使所述开关S1n接入电路，与其并联的子电阻被断开。例如，在该实施例中，当需要增大所述可调电阻的电阻值，则断开所述开关S11，使与开关S11并联的子电阻R11接入电路；当需要减小所述可调电阻的电阻值时，接通所述开关S11，使所述开关S11接入电路，与其并联的子电阻R11被短路。
进一步，在本实施例中，所述子电阻R1n的电阻值相同，以简化版图布局难度，简单易行，便于制造。所述子电阻R1n为多晶硅电阻或者N型扩散电阻或者P型扩散电阻。进一步，所述子电阻R1n之间通过第一层金属线电连接，所述子电阻R1n与所述开关S1n之间通过第二层金属线电连接。这种方式能够进一步易于制造，提高稳定性和精确性。
进一步，所述开关S1n可为晶体管，例如NMOS管或PMOS管，其结构稳定，且易于制造。
上述仅为本发明提供的一种可调电阻单元1111的实施例，在本发明其他实施例中，也可采用其他电路结构实现可调电阻单元1111。
进一步，所述温度检测模块110还包括一非易失性存储单元113。所述非易失性存储单元113与所述校准值存储单元1123连接，用于备份所述校准值。其中，所述非易失性存储单元113可按预设周期备份所述校准值。所述预设周期可为半导体装置上电后的预设时间周期，例如半导体装置上电后以10分钟作为一个周期将校准值备份在非易失性存储单元113中，即半导体装置上电后每隔十分钟将校准值备份在非易失性存储单元中；或者以一个小时作为一个周期将校准值备份在非易失性存储单元中，即半导体装置上电后每隔一个小时将存储在校准值码备份在非易失性存储单元113中。所述非易失存储单元113也可在芯片出厂设置时即将所述校准值存入其中，所述半导体装置在后续每次上电使用时，均首先将所述非易失存储单元113中的校准值导入到所述校准值存储单元1123中。
本发明半导体装置在非易失性存单元113中备份校准值，若半导体装置掉电，所述校准值依然会记录在非易失性存单元113中，不会被清除，可作为后续校准的依据。
备份在所述非易失性存储单元113中的校准值能够再次载入至所述校准值存储单元1123中。载入的校准值作为后续校准的参考，从而可避免半导体装置掉电导致的校准值丢失的情况。
进一步，所述处理单元112包括至少一控制开关Sx，所述控制开关Sx与所述温度检测单元111电连接，以选择需要被处理单元112进行信号处理的所述温度检测单元111。具体 地说，当所述控制开关Sx闭合时，所述温度敏感单元111与所述处理单元112电连接，当所述控制开关Sx断开时，所述温度敏感单元111与所述处理单元112解除电连接。
在第一实施例中，所述温度敏感单元111为二极管，所述二极管的负端与接地端VSS电连接，所述二极管的正端通过所述控制开关Sx与所述处理单元112电连接，所述校准单元1124与所述二极管并联，所述校准单元1124的一端与接地端VSS电连接，另一端通过所述控制开关Sx与所述二极管的正端电连接。所述二极管对温度敏感，随着其周围环境温度的变化，其电流发生变化，进而能够用于测量周围环境的温度。
优选地，所述控制开关Sx与所述温度敏感单元111一一对应，即一个控制开关与一个温度敏感单元111电连接，以实现精确控制。具体地说，在本实施例中，所述温度敏感单元111的数量为四个，则所述处理单元112包括四个控制开关S1～S4，每一控制开关与一个温度敏感单元111电连接，以控制其对应的温度敏感单元111与处理单元112的电连接。其中，所述控制芯片120能够获取闭合的控制开关所导通的温度敏感单元111对应的校准值，并根据所述校准值调节所述校准单元1124，从而对该温度敏感单元111进行校准。
例如，当需要对与控制开关S1对应的温度敏感单元111的电信号进行处理时，闭合控制开关S1，其他控制开关断开，使得控制开关S1对应的温度敏感单元111与处理单元112电连接，实现信号的处理，同时，所述控制芯片120获取控制开关S1所导通的温度敏感单元111对应的校准值，并根据所述校准值调节所述校准单元1124，从而对该温度敏感单元111进行校准；当需要对与控制开关S2对应的温度敏感单元111的电信号进行处理时，闭合控制开关S2，其他控制开关断开，使得控制开关S2对应的温度敏感单元111与处理单元112电连接，实现信号的处理，同时，所述控制芯片120获取控制开关S2所导通的温度敏感单元111对应的校准值，并根据所述校准值调节所述校准单元1124，从而对该温度敏感单元111进行校准；当需要对与控制开关S3对应的温度敏感单元111的电信号进行处理时，闭合控制开关S3，其他控制开关断开，使得控制开关S3对应的温度敏感单元111与处理单元112电连接，实现信号的处理，同时，所述控制芯片120获取控制开关S3所导通的温度敏感单元111对应的校准值，并根据所述校准值调节所述校准单元1124，从而对该温度敏感单元111进行校准；当需要对与控制开关S4对应的温度敏感单元111的电信号进行处理时，闭合控制开关S4，其他控制开关断开，使得控制开关S4对应的温度敏感单元111与处理单元112电连接，实现信号的处理，同时，所述控制芯片120获取控制开关S4所导通的温度敏感单元111对应的校准值，并根据所述校准值调节所述校准单元1124，从而对该温 度敏感单元111进行校准。
在该实施例中，所述控制开关Sx的一端与温度敏感单元111电连接，另一端与校准单元1124连接，即所述温度敏感单元111及所述校准单元1124分别连接至所述控制开关Sx的两端，而在本发明另一实施例中，所述校准单元1124与所述温度敏感单元111均连接至所述控制开关Sx的同一端，即所述校准单元1124与所述温度敏感单元111均与所述控制开关Sx的一端或者另一端电连接。当所述控制开关Sx闭合时，所述温度敏感单元111的数据被所述处理单元112进行处理，当所述控制开关Sx断开时，所述处理单元112不对所述温度敏感单元111的数据进行处理。
进一步，请继续参阅图2，在本实施例中，所述处理单元112还包括定值电阻Ra及A/D转换模块1121。
所述定值电阻Ra具有第一端及第二端。所述第一端与电源Vtemp电连接，所述第二端与所述控制开关Sx电连接。所述A/D转换模块1121具有输入端及输出端，所述输入端与所述定值电阻Ra的第二端电连接，所述输出端用于输出数字信号，所述A/D转换模块1121用于将所述定值电阻Ra第二端的模拟信号转换为数字信号。
所述A/D转换模块1121包括电阻单元及多个比较单元Px。
所述电阻单元具有第一端及第二端。所述电阻单元的第一端与电源电连接。所述电阻单元可与所述温度敏感单元111采用同一电源，也可采用不同电源。例如，若所述A/D转换模块1121设置在存储芯片100中，则所述电阻单元的第一端可与所述温度敏感单元111采用同一电源Vtemp；若所述A/D转换模块1121设置在控制芯片120中，则所述电阻单元的第一端可与所述温度敏感单元111采用不同的电源，所述电阻单元可采用电源VDD。所述电阻单元的第二端与接地端VSS电连接。其中，所述电阻单元具有多个引出端Ax，每一引出端Ax的电压不同。
在本实施例中，所述电阻单元包括多个串联连接的子电阻Rx，所述电阻单元的每一引出端Ax与所述电阻单元的第二端之间间隔的子电阻Rx的数量不同，以使每一引出端Ax的电压不同。例如，引出端A1与电阻单元的第二端之间间隔子电阻R1，引出端A2与电阻单元的第二端之间间隔子电阻R1及R2，则引出端A1与引出端A2的电压不同。
其中，所述电阻单元的每一引出端Ax与所述电阻单元的第二端之间间隔的子电阻Rx的数量以预设数值递增。其中，所述预设数值可为一定值，也可为可变数值。请参阅图2，在本实施例中，所述电阻单元的每一引出端Ax与所述电阻单元的第二端之间间隔的子电阻 Rx的数量以定值1递增。而在本发明其他实施例中，也可以定值2等数量递增。当所述预设数值为可变数值时，所述预设数值具有一变化趋势。所述变化趋势根据所述引出端Ax的电压增幅设定，例如，若所述引出端Ax的电压增幅为递增，则所述预设数值的变化趋势为递增；若所述引出端Ax的电压增幅为递减，则所述预设数值的变化趋势为递减；若所述引出端Ax的电压增幅为先增加再减小，则所述预设数值的变化趋势为先增加再减小。
进一步，所述子电阻Rx的电阻值相同或不同，以使得所述引出端Ax之间的电压增幅变化一致或不一致。其中，若所述子电阻Rx的电阻值相同，则能够简化版图布局难度，简单易行，便于制造。
所述A/D转换模块输入端的信号作为所述比较单元Px的输入信号，即所述温度敏感单元输出的模拟信号作为所述比较单元Px的输入信号。所述电阻单元的多个引出端Ax信号分别作为多个所述比较单元Px的参考信号。所述引出端Ax与所述比较单元Px一一对应。例如，所述引出端A1信号作为所述比较单元P1的参考信号，所述引出端A2信号作为所述比较单元P2的参考信号，依此类推，所述引出端Ax与所述比较单元Px一一对应。所述比较单元Px输出数字信号。根据所述比较单元Px输出的数字信号，可获得所述温度敏感单元111检测的存储芯片100的温度。
当所述电阻单元的每一引出端Ax与所述电阻单元的第二端之间间隔的子电阻Rx的数量以可变的预设数值递增时，所述引出端Ax的电压非均匀地改变，以使多个所述比较单元Px的参考信号非均匀地改变，则在不同的电压区域，所述比较单元Px的参考信号的增幅不同，进而能够改变该电压区域的测量精度。具体地说，对需要精确测量的电压区域，所述预设数值以小幅度改变，以使参考信号的增幅小，提高信号采样点数，进而提高该区域的测量精度，对不需要精确测量的电压区域，所述预设数值以大幅度改变，以使参考信号的增幅大，减少信号采样点数，进而提高测量效率。例如，在本发明一实施例中，需要精确测量的电压区域为1.2V～1.7V，其对应的参考信号范围即为1.2V～1.7V，则在1.2V～1.7V电压区域，所述预设数值的增幅小，例如，所述预设数值的增幅为1，使得参考信号的增幅为0.1V，从而能够增加该电压区域的采样点数，提高测量精度，而在电压小于1.2V及大于1.7V的电压区域，所述预设数值的增幅大，例如，所述预设数值的增幅为3，使得参考信号的增幅为0.3V，适当减少采样点数，提高测量效率。
进一步，所述A/D转换模块1121还包括输出单元1122，所述输出单元1122与所述比较单元Px连接，用于将所述数字信号输出。进一步，在本实施例中，所述A/D转换模块 1121还包括编码单元EEC，所述编码单元EEC接收所述比较单元Px输出的数字信号，并进行编码，其形成的信号输入所述输出单元1120，所述输出单元1122将编码后的数字信号输出。
进一步，所述处理单元112设置在所述控制芯片120上或者设置在其中一个所述存储芯片100上。在本实施例中，请参阅图1，所述处理单元112设置在所述控制芯片120上。在本发明其他实施例中，所述处理单元112设置在其中一个所述存储芯片100上。例如，如图5所示，其为本发明半导体装置第三实施例的结构示意图，在该实施例中，所述处理单元112设置在最底层的所述存储芯片100上。
进一步，所述温度敏感单元111与所述存储芯片100采用不同的电源供电。图6是本发明半导体装置的第一实施例的电连接示意图，请参阅图6，所述温度敏感单元111采用电源Vtemp供电，所述存储芯片100采用VDD供电。其中，所述接地端VSS、电源VDD及电源Vtemp由所述控制芯片120提供。由于所述温度敏感单元111与所述存储芯片100采用不同的电源供电，因此，可独立地控制所述温度敏感单元111及所述存储单元100的供电，从而实现所述温度敏感单元111与所述存储芯片100的不同时启动。
因此，本发明可分别控制所述温度敏感单元111与所述存储芯片100的启动，即温度敏感单元111的启动不受存储芯片100是否启动的影响，使得对存储芯片100温度的检测不受存储芯片100是否启动的影响，从而能够为存储芯片100的启动及运行提供参考，进而能够避免存储芯片100在低温下启动或者运行，提高存储芯片100的稳定性。
如前所述，温度对存储芯片100的性能有很大影响，特别是在存储芯片100启动时。若存储芯片100在低温下启动，会使向存储芯片100中写入数据的时间变化(如加长)，影响了存储芯片100写入的稳定性，则在存储芯片100启动之前需要测量存储芯片的温度，以使存储芯片100能够在合适的温度内启动。
因此，本发明所述温度敏感单元111的供电早于所述存储芯片100的供电，即在所述存储芯片100启动之前，所述温度敏感单元111已经启动，从而可获得存储芯片100启动之前的温度，为存储芯片100的启动提供参考。所述温度敏感单元111与所述存储芯片100的供电时间差取决于所述存储芯片100的温度变化速率，若所述存储芯片100的温度变化速率大，所述存储芯片100达到预设温度的时间短，则所述温度敏感单元111与所述存储芯片100的供电时间差小，若所述存储芯片100的温度变化速率小，所述存储芯片100达到预设温度的时间长，则所述温度敏感单元111与所述存储芯片100的供电时间差大。
进一步，请参阅图6，所述温度敏感单元111与所述存储芯片100共用同一接地端VSS。其优点在于，一方面不会增加存储芯片100未启动阶段的泄露电流，另一方面，会减少引脚的数目，节省空间。
进一步，请继续参阅图1，所述存储芯片100中形成有硅通孔互连结构101，通过硅通孔互连结构101将存储芯片100与控制芯片120进行电连接，将温度敏感单元111与处理单元112电连接。同时，通过硅通孔互连结构101将存储芯片100与接地端VSS及电源VDD电连接，将温度敏感单元111与电源Vtemp及接地端VSS电连接。
在第一实施例中，多个存储芯片100堆叠设置时，每一个存储芯片100可以通过不同的硅通孔互连结构与控制芯片120连接；当具有多个温度敏感单元111时，可能存在每一个温度敏感单元111通过不同的硅通孔互连结构与处理单元112连接的情况，也可能存在多个温度敏感单元111共用硅通孔互连结构与处理单元112连接的情况。可以理解的是，所述存储芯片100与所述温度敏感单元111通过不同的硅通孔互连结构与电源连接，以使所述温度敏感单元111及所述存储芯片100能够采用不同的电源供电。进一步，多个所述温度敏感单元111的供电也可共用硅通孔互连结构。
在其他实施例中，所述存储芯片100及所述温度敏感单元111还可以通过金属引线(通过引线键合工艺形成)与所述控制芯片120及处理单元112电连接。
在第一实施例中，请继续参阅图1，多个存储芯片100依次堆叠设置在所述控制芯片120上，所述控制芯片120与堆叠结构中最底层的存储芯片100键合在一起。而在本发明另一实施例中，例如，请参阅图7，其为本发明半导体装置的第四实施例的结构示意图，所述半导体装置还包括线路基板130，所述线路基板130中具有连接线路(附图中未绘示)，所述存储芯片100以及控制芯片120均位于线路基板130上，所述存储芯片100和控制芯片120通过线路基板130中的连接线路连接。在该实施例中，所述温度敏感单元111设置在存储芯片100中，所述处理单元112设置在控制芯片120中。其中，所述线路基板130包括但不限于PCB电路板。
本发明半导体装置利用温度检测模块检测存储芯片的温度，当所述温度检测模块检测的温度达到设定阈值时，或者所述存储芯片100的温度达到设定阈值之后，所述存储芯片启动，温度检测模块检测的温度为存储芯片的启动及运行提供参考，从而避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性。
当存储芯片100处于低温环境中，若对其进行加热，则能够迅速提高存储芯片100的 温度，从而加快存储芯片100的启动。因此，本发明所述控制芯片120还能够在存储芯片100启动之前先进行启动，控制芯片120利用启动后自身产生的热量对存储芯片100进行加热，以快速提高存储芯片100的温度。
在所述控制芯片120启动后，所述控制芯片120控制所述温度敏感单元111启动，以检测所述存储芯片100的温度。所述温度敏感单元111还能够将检测的温度传送给控制芯片120，以作为控制芯片120的数据。
所述控制芯片120能够判断所述温度敏感单元111检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片100启动。
若存在一个所述温度敏感单元111检测多个存储芯片100的温度的情况，当控制单元120判定该温度敏感单元111检测的温度达到设定阈值，则控制单元120先控制离所述控制芯片120最近的存储芯片100启动，然后再控制上面的其他存储芯片100依次启动。
若存在所述温度敏感单元111与所述存储芯片100一一对应的情况，所述控制单元120判断某一个温度敏感单元111检测的温度达到设定阈值，则控制该温度敏感单元111对应的存储芯片100启动。具体地说，如图1所示的堆叠结构中有4个存储芯片100，每一个存储芯片100中对应具有一个温度敏感单元111，因而每一个温度敏感单元111会对对应的存储芯片100的温度进行检测，获得四个温度检测值，所述控制芯片120会依次判断4个所述温度敏感单元111检测的温度是否达到设定阈值时，若某一个温度敏感单元111检测的温度达到设定阈值，则控制该温度敏感单元111对应的存储芯片启动，比如堆叠结构中最底层的存储芯片100中的温度敏感单元111检测的温度先达到设定阈值时，则控制芯片120先控制所述堆叠结构最底层的那一个存储芯片100启动，接着，堆叠结构中倒数第二层中那个存储芯片100中对应的温度敏感单元111检测的温度也达到设定阈值时，则控制单元301接着控制堆叠结构中倒数第二层的那个存储芯片100启动，上面两层的存储芯片100的启动以此类推。
对于半导体装置存在多个存储芯片100时，前述的这种控制结构和控制方式能使得每一个存储芯片100启动时机的精度进一步提高，并能进一步减小低温环境下的对每一个存储芯片100进行数据写入时的写入时间，进一步提高了对每一个存储芯片100写入的稳定性。
当本发明半导体装置工作在低温环境时，通过控制芯片120可以使得存储芯片100升温到设定阈值，从而可以防止存储芯片100中的位线、字线、以及金属连线(金属接触部) 由于环境温度过低带来的电阻的增大，从而减小了低温环境下的对存储芯片进行数据写入时的写入时间，提高了存储芯片写入的稳定性。所述设定阈值可以设定在控制芯片120中，设定阈值的具体大小可以根据实际需要或者经验进行设定。
在另一实施例中，所述控制芯片120中可以具有额外的加热电路(附图中未绘示)。所述加热电路用于对所述存储芯片100进行加热。所述控制芯片120在对所述存储芯片100进行加热之前或之后，所述控制芯片120判断所述温度敏感单元111检测的存储芯片100的温度是否达到设定阈值，若未达到设定阈值，则控制所述加热电路对存储芯片100进行加热，如达到设定阈值，则控制所述加热电路停止对存储芯片100进行加热。从而实现对加热过程的精确控制，使得存储芯片100的温度能保持在设定阈值附近，防止存储芯片100的温度过高或过低，从而使得对存储器的写入时间始终能保持较短。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (22)

  1. 一种半导体装置，其特征在于，包括多个存储芯片、温度检测模块，所述温度检测模块包括：
    多个温度敏感单元，设置在至少部分所述存储芯片上，以检测至少部分所述存储芯片的温度；
    处理单元，多个所述温度敏感单元共用所述处理单元，所述处理单元用以对至少一所述温度敏感单元的信号进行处理，所述处理单元包括校准值存储单元及校准单元，所述校准值存储单元用于存储与所述温度敏感单元对应的校准值，所述校准单元用于根据所述校准值校准所述温度敏感单元。
  2. 根据权利要求1所述的半导体装置，其特征在于，所述校准单元为可调电阻，其与所述温度敏感单元并联，所述校准单元根据所述校准值调节电阻值，以校准所述温度敏感单元。
  3. 根据权利要求2所述的半导体装置，其特征在于，所述校准单元包括多个子电阻及多个开关，所述子电阻串联连接，每一所述开关至少与一个所述子电阻并联，通过改变多个所述开关的通断，来改变所述校准单元的电阻值。
  4. 根据权利要求3所述的半导体装置，其特征在于，根据所述校准值控制所述开关的通断。
  5. 根据权利要求2所述的半导体装置，其特征在于，所述温度敏感单元为二极管，所述二极管的负端与接地端电连接，所述二极管的正端与所述处理单元电连接，所述校准单元与所述二极管并联，所述校准单元的一端与接地端电连接，另一端与所述二极管的正端电连接。
  6. 根据权利要求1所述的半导体装置，其特征在于，所述温度检测模块还包括一非易失性存储单元，与所述校准值存储单元连接，用于备份所述校准值，备份在所述非易失性存储单元中的校准值能够再次载入至所述校准值存储单元中。
  7. 根据权利要求1所述的半导体装置，其特征在于，所述处理单元包括至少一控制开关，所述控制开关与所述温度敏感单元电连接，以选择需要被处理单元进行信号处理的所述温度检测单元。
  8. 根据权利要求7所述的半导体装置，其特征在于，所述处理单元还包括定值电阻，所述定值电阻具有第一端及第二端，所述第一端与电源电连接，所述第二端与所述控制开关电连接。
  9. 根据权利要求8所述的半导体装置，其特征在于，所述处理单元还包括A/D转换模块，所述A/D转换模块具有输入端及输出端，所述输入端与定值电阻的第二端电连接，所述输出端用于输出数字信号，所述A/D转换模块用于将所述定值电阻第二端的模拟信号转换为数字信号。
  10. 根据权利要求9所述的半导体装置，其特征在于，所述A/D转换模块包括：
    电阻单元，具有第一端及第二端，所述电阻单元的第一端与电源电连接，所述电阻单元的第二端与接地端电连接，所述电阻单元具有多个引出端，每一引出端的电压不同；
    多个比较单元，所述A/D转换模块输入端的信号作为所述比较单元的输入信号，所述电阻单元的多个引出端信号分别作为多个所述比较单元的参考信号，所述比较单元输出数字信号。
  11. 根据权利要求10所述的半导体装置，其特征在于，所述A/D转换模块还包括编码器，所述编码器接收所述比较单元的输出信号，并进行编码。
  12. 根据权利要求11所述的半导体装置，其特征在于，所述A/D转换模块还包括输出器，所述输出器与所述比较单元连接，用于将所述数字信号输出。
  13. 根据权利要求10所述的半导体装置，其特征在于，所述电阻单元包括多个串联连接的子电阻，所述电阻单元的每一引出端与所述电阻单元的第二端之间间隔的子电阻的数量不同，以使每一引出端的电压不同。
  14. 根据权利要求1所述的半导体装置，其特征在于，所述温度敏感单元与所述存储芯片一一对应，在每一所述存储芯片上均设置有一个所述温度敏感单元。
  15. 根据权利要求1所述的半导体装置，其特征在于，所述温度敏感单元与所述存储芯片共用同一接地端。
  16. 根据权利要求1所述的半导体装置，其特征在于，所述半导体装置还包括控制芯片，所述存储芯片及所述温度检测模块与所述控制芯片电连接。
  17. 根据权利要求16所述的半导体装置，其特征在于，所述处理单元设置在所述控制芯片上或者设置在其中一个所述存储芯片上。
  18. 根据权利要求16所述的半导体装置，其特征在于，多个所述存储芯片依次向上堆叠在所述控制芯片上。
  19. 根据权利要求16所述的半导体装置，其特征在于，所述半导体装置还包括线路基板， 所述线路基板中具有连接线路，所述存储芯片以及控制芯片均位于线路基板上，所述存储芯片和控制芯片通过线路基板中的连接线路连接。
  20. 根据权利要求16所述的半导体装置，其特征在于，所述控制芯片用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度敏感单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
  21. 根据权利要求1所述的半导体装置，其特征在于，所述温度敏感单元与所述存储芯片采用不同的电源供电。
  22. 根据权利要求21所述的半导体装置，其特征在于，所述温度敏感单元的供电早于所述存储芯片的供电。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118899270B (zh) * 2024-07-12 2025-05-13 深圳市安信达存储技术有限公司 温度调节方法及封装存储芯片
CN120721238A (zh) * 2025-08-21 2025-09-30 中山大学 一种基于tsv的三维分布温度传感器和温度检测方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162604A (zh) * 2006-10-12 2008-04-16 海力士半导体有限公司 输出半导体存储设备的温度数据的电路及方法
US9013932B1 (en) * 2013-11-06 2015-04-21 SK Hynix Inc. Semiconductor devices and semiconductor systems including the same
CN107393577A (zh) * 2017-08-21 2017-11-24 睿力集成电路有限公司 应用于半导体存储器的zq校准控制
CN110299171A (zh) * 2018-03-22 2019-10-01 东芝存储器株式会社 存储器系统，电源控制电路及存储器系统中的控制方法
CN212303077U (zh) * 2020-07-17 2021-01-05 长鑫存储技术有限公司 半导体装置

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100541824B1 (ko) 2003-10-06 2006-01-10 삼성전자주식회사 반도체 집적회로에 채용하기 적합한 온도감지 회로
US7266031B2 (en) 2003-11-19 2007-09-04 Infineon Technologies Ag Internal voltage generator with temperature control
KR100577560B1 (ko) 2003-12-23 2006-05-08 삼성전자주식회사 온도감지 데이터에 응답하는 내부회로를 갖는 반도체메모리장치
US7356426B2 (en) 2004-09-30 2008-04-08 Intel Corporation Calibration of thermal sensors for semiconductor dies
US20060290366A1 (en) 2005-06-28 2006-12-28 Intel Corporation Monitoring multiple electronic devices under test
KR101224919B1 (ko) 2006-02-07 2013-01-22 삼성전자주식회사 온도 변화에 따라 고전압 발생 회로의 출력 전압 레벨을조절하는 반도체 메모리 장치
US7383149B1 (en) * 2006-04-19 2008-06-03 Darryl Walker Semiconductor device having variable parameter selection based on temperature and test method
US7603249B1 (en) * 2006-04-19 2009-10-13 Darryl Walker Semiconductor device having variable parameter selection based on temperature and test method
DE102006018921A1 (de) 2006-04-24 2007-11-08 Infineon Technologies Ag Integrierter Halbleiterspeicher mit Auffrischung von Speicherzellen
KR20090032705A (ko) 2007-09-28 2009-04-01 삼성전자주식회사 온도 변화에 적응적인 클럭을 이용하는 저장장치 및 이를이용한 방송수신장치
JP2009170605A (ja) * 2008-01-15 2009-07-30 Denso Corp 電子装置
JP2011052980A (ja) * 2009-08-31 2011-03-17 Denso Corp 温度検出器、温度検出器用抵抗器の調整装置、温度検出器用抵抗器の調整方法および半導体装置
KR101132795B1 (ko) 2010-02-25 2012-04-02 주식회사 하이닉스반도체 온도센서
KR101817156B1 (ko) * 2010-12-28 2018-01-10 삼성전자 주식회사 관통 전극을 갖는 적층 구조의 반도체 장치, 반도체 메모리 장치, 반도체 메모리 시스템 및 그 동작방법
JP5786571B2 (ja) 2011-09-07 2015-09-30 富士電機株式会社 パワー半導体装置の温度測定装置
KR102098248B1 (ko) * 2013-06-03 2020-04-07 삼성전자 주식회사 온도에 따라 완화된 타이밍 요건으로 사용되는 메모리 장치 및 이를 이용하는 메모리 콘트롤러
US20150043266A1 (en) 2013-08-09 2015-02-12 Samsung Electronics Co., Ltd. Enhanced temperature range for resistive type memory circuits with pre-heat operation
JP6065979B2 (ja) 2013-08-23 2017-01-25 三菱電機株式会社 半導体装置
US9194754B2 (en) * 2014-03-28 2015-11-24 Darryl G. Walker Power up of semiconductor device having a temperature circuit and method therefor
JP2016046617A (ja) * 2014-08-21 2016-04-04 ルネサスエレクトロニクス株式会社 半導体装置
KR20160056056A (ko) 2014-11-11 2016-05-19 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
CN104807561B (zh) 2015-04-29 2017-11-28 清华大学深圳研究生院 电阻型温度传感芯片的校准电路和校准方法
US9520189B1 (en) * 2015-10-29 2016-12-13 International Business Machines Corporation Enhanced temperature compensation for resistive memory cell circuits
US9927986B2 (en) * 2016-02-26 2018-03-27 Sandisk Technologies Llc Data storage device with temperature sensor and temperature calibration circuitry and method of operating same
US10564900B2 (en) 2016-03-04 2020-02-18 Western Digital Technologies, Inc. Temperature variation compensation
JP6756965B2 (ja) * 2016-12-09 2020-09-16 富士通株式会社 半導体装置及び半導体装置の制御方法
KR20190036893A (ko) 2017-09-28 2019-04-05 삼성전자주식회사 메모리 장치 및 그것의 제어 방법
EP3700004A4 (en) 2018-06-14 2021-03-10 Lg Chem, Ltd. DEVICE AND METHOD OF MEASURING THE TEMPERATURE OF A BATTERY
CN208953151U (zh) 2018-10-18 2019-06-07 杭州士兰微电子股份有限公司 过温检测装置
JP2020077443A (ja) * 2018-11-05 2020-05-21 キオクシア株式会社 メモリシステム
US20210362492A1 (en) 2018-11-16 2021-11-25 Hewlett-Packard Development Company, L.P. Temperature sensing
WO2020204158A1 (ja) 2019-04-04 2020-10-08 株式会社村田製作所 増幅回路及び増幅装置
JP6818919B1 (ja) 2020-02-06 2021-01-27 三菱電機株式会社 温度センサモジュール
CN212303079U (zh) 2020-07-17 2021-01-05 长鑫存储技术有限公司 半导体装置
CN212303078U (zh) 2020-07-17 2021-01-05 长鑫存储技术有限公司 半导体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162604A (zh) * 2006-10-12 2008-04-16 海力士半导体有限公司 输出半导体存储设备的温度数据的电路及方法
US9013932B1 (en) * 2013-11-06 2015-04-21 SK Hynix Inc. Semiconductor devices and semiconductor systems including the same
CN107393577A (zh) * 2017-08-21 2017-11-24 睿力集成电路有限公司 应用于半导体存储器的zq校准控制
CN110299171A (zh) * 2018-03-22 2019-10-01 东芝存储器株式会社 存储器系统，电源控制电路及存储器系统中的控制方法
CN212303077U (zh) * 2020-07-17 2021-01-05 长鑫存储技术有限公司 半导体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3965105A4 *

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