WO2022017402A1 - 一种芯片转移方法、电子设备 - Google Patents

一种芯片转移方法、电子设备 Download PDF

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Publication number
WO2022017402A1
WO2022017402A1 PCT/CN2021/107476 CN2021107476W WO2022017402A1 WO 2022017402 A1 WO2022017402 A1 WO 2022017402A1 CN 2021107476 W CN2021107476 W CN 2021107476W WO 2022017402 A1 WO2022017402 A1 WO 2022017402A1
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WIPO (PCT)
Prior art keywords
fibers
adjacent
layer
motherboard
chip
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2021/107476
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English (en)
French (fr)
Inventor
龙浩晖
魏山山
佘勇
方建平
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP21845429.6A priority Critical patent/EP4181180B1/en
Priority to US18/006,066 priority patent/US12512360B2/en
Publication of WO2022017402A1 publication Critical patent/WO2022017402A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/01—Manufacture or treatment
    • H10H29/02—Manufacture or treatment using pick-and-place processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7428—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer

Definitions

  • the present application relates to the technical field of micro light-emitting diode displays, and in particular, to a chip transfer method and electronic equipment.
  • micro LED light emitting diode
  • the micro LED technology forms micron-scale micro LEDs on a donor substrate, such as a wafer. Then, the micro LEDs on the above-mentioned donor substrate are transferred to a receptor substrate, such as a circuit board, and arranged in an array. Each micro LED can be driven to light up individually as a pixel, so that the display screen can present a picture with higher detail and higher contrast.
  • Micro LED inherits the characteristics of high efficiency, high brightness, high reliability and fast response time of LED, and has the characteristics of self-illumination, which has the advantages of energy saving, simple structure, small size and thin shape.
  • OLED organic light emitting diode
  • micro LED displays are easier and more accurate to debug colors, have longer luminous life and higher brightness, and have better material stability and life. Long, no image burn-in and other advantages.
  • massively parallel pick and place technology can be used to pick up micro LEDs on the donor substrate in batches through the transfer head and transfer them to the substrate. Since the transfer head needs to move repeatedly between the donor substrate and the donor substrate, it takes a certain amount of time to pick and place the micro LEDs during each movement. Therefore, when making a display screen with higher resolution, the production efficiency is too low due to the huge number of micro LEDs to be transferred, which is insufficient to support the expectations of the market and production cost.
  • the present application provides a chip transfer method and electronic device for improving the problem of low efficiency of mass transfer micro LED technology.
  • a chip transfer method for transferring a chip in a motherboard to a substrate.
  • the method includes: first, providing a scaling layer.
  • the stretchable layer may include a plurality of first fibers and a plurality of second fibers, and a laminated first cloth layer and a second cloth layer.
  • the first fibers and the second fibers intersect between the first cloth layer and the second cloth layer, and there are multiple intersection points between the first fibers and the second fibers.
  • a first distance H1 is controlled between two adjacent intersection points, and a second distance H2 is controlled between the first cloth layer and the second cloth layer.
  • the first cloth layer in the stretchable layer is close to the chip, and the second cloth layer is far away from the chip. Then, the plurality of chips are separated, and the separated plurality of chips are connected to the first fiber and the second fiber, respectively. Next, the plurality of chips pasted with the stretchable layer are respectively arranged in a plurality of preset positions of the substrate. Finally, the first and second fibers are removed.
  • the stretchable layer can be pasted with each chip in the motherboard.
  • the first distance H1 can be the same as the distance between two chips on the motherboard.
  • the plurality of chips on the stretchable layer can be arranged on each preset position on the substrate.
  • the first and second fibers are then removed to complete the mass transfer of the chip.
  • the chip transfer method provided by the present application only the stretchable layer needs to be pasted with a plurality of chips on the motherboard. Then, the chip on the stretchable layer is arranged on the substrate. In this way, most or even all chips on the same motherboard can be transferred to the substrate at one time. Therefore, in the process of chip transfer, there is no need for the transfer head to go back and forth between the mother board and the substrate, so as to improve the efficiency of mass transfer of chips.
  • providing the stretchable layer includes crossing a plurality of first warp threads and a plurality of first weft threads to form a first cloth layer.
  • the spacing between two adjacent first warp threads is the same as the first spacing H1
  • the spacing between two adjacent first weft threads is the same as the first spacing H1.
  • a plurality of second warp threads and a plurality of second weft threads are intersected to form a second fabric layer.
  • the interval between two adjacent second warp threads is the same as the first interval H1
  • the interval between two adjacent second weft threads is the same as the first interval H1.
  • the vertical projection of the second warp thread on the first cloth layer is located between two adjacent first warp threads, and the vertical projection of the second weft thread on the first cloth layer is located between two adjacent second weft threads.
  • the positions of the crossed first weft threads and the first warp threads in the first fabric layer and the crossed second weft threads and the second warp threads in the second fabric layer in the stretchable layer can be controlled, so that the first The spacing H1 can be the same as the spacing between two chips of the motherboard.
  • the first fibers intersect the first and second warp threads, and the second fibers intersect the first and second weft threads. In this way, both the first fibers and the second fibers can be made to cross the first cloth layer and the second cloth layer.
  • the above-mentioned attaching the stretchable layer to the chip includes: aligning and attaching an intersection point to a chip in the motherboard. Since the position of the intersection can be controlled, the chips on the motherboard can be pasted as required.
  • aligning and pasting an intersection point with a chip in the motherboard includes: on the first cloth layer, coating an adhesive layer at the intersection point. Then, the side surface of the stretchable layer coated with the adhesive layer is pasted on the motherboard, so that the vertical projection of a cross point on the motherboard overlaps with one chip in the motherboard. In this way, an adhesive layer can be formed on the first cloth layer, and the stretchable layer can be pasted on the mother board through the adhesive layer.
  • aligning and pasting a cross point with a chip in the motherboard includes dispensing glue on the motherboard to form a plurality of adhesive layers, and a vertical projection of one adhesive layer on the motherboard overlaps with a chip in the motherboard. Then, the surface of the side where the first fabric layer is located is pasted on the mother board through a plurality of adhesive layer arrays, so that the vertical projection of a cross point on the mother board overlaps with one adhesive layer.
  • An adhesive layer array is formed by dispensing glue at the position of each chip on the motherboard, and the stretchable layer is pasted on the motherboard through the adhesive layer array.
  • aligning and pasting an intersection point with a chip in the motherboard includes: coating a colloidal material layer on the motherboard, and patterning the colloidal material layer, so that a plurality of adhesive layers are formed on the motherboard, one The vertical projection of the adhesive layer on the motherboard overlaps with a chip in the motherboard. Then, the side surface on which the first fabric layer is located is pasted on the mother board through an adhesive layer, so that the vertical projection of a cross point on the mother board overlaps with an adhesive layer. In this way, multiple adhesive layers on the mother board can be formed in the same mask exposure process, thus improving the efficiency of the manufacturing process.
  • the motherboard includes a substrate for carrying chips.
  • Attaching the stretchable layer to the chip includes attaching the stretchable layer to the side surface of the substrate away from the chip. In this way, the surface of the side where the first electrode and the second electrode are located in the chip can be prevented from contacting the adhesive layer, thereby affecting the performance of the chip.
  • the chip includes a first electrode and a second electrode.
  • Disposing the plurality of chips on the stretchable layer on the plurality of preset positions of the substrate includes: adopting a flip-chip process, at the preset positions, the first electrode and the second electrode of a chip are close to the substrate, and are welded on the substrate.
  • the above flip-chip process enables the first electrodes and the second electrodes of the chip to be directly welded on the substrate, thereby improving the efficiency of transmitting electrical signals to the first electrodes and the second electrodes.
  • the method further includes: stretching the first fiber and the second fiber, so that the first fiber and the second fiber are drawn together.
  • there is a welding distance Hb between two adjacent preset positions on the substrate, and H3 Hb. In this way, all chips on the stretch layer can be transferred to the substrate.
  • the spacing between two adjacent first warp threads is the same as the first spacing H1, and the spacing between two adjacent first weft threads is the same as the first spacing H1, including: setting the periphery of the motherboard A plurality of first positioning posts; a first positioning post is arranged between every two adjacent first warp threads, and is in contact with two adjacent first warp threads.
  • a plurality of second positioning posts are provided around the motherboard.
  • a second positioning column is arranged between every two adjacent first weft threads, and is in contact with two adjacent first weft threads.
  • the direction of the first geometric length L1 of the first positioning column is perpendicular to the two adjacent first warp lines; the direction of the second geometric length L2 of the second positioning column is perpendicular to the two adjacent first weft lines.
  • the first positioning post is arranged between two adjacent first warp threads and is in contact with two adjacent first warp threads, by setting the first geometric length L1 of the first positioning post, the The purpose of controlling the distance between two adjacent first warp threads to be the same as the first distance H1 can be achieved.
  • the second geometric length L2 of the second positioning column the purpose of controlling the distance between two adjacent first wefts to be the same as the first distance H1 can be achieved.
  • the direction of the second geometric length L2 of the second positioning column is perpendicular to the two adjacent first wefts, respectively.
  • stretching the first fiber and the second fiber, and controlling the first fiber and the second fiber to have a third distance H3 between two adjacent cores on the first fiber and the second fiber includes: stretching the first fiber and the second fiber.
  • the direction of the first geometric width B1 of the first positioning column is perpendicular to the two adjacent second fibers respectively; the direction of the second geometric width B2 of the second positioning column is perpendicular to the two adjacent first fibers respectively.
  • the first positioning column is originally arranged between two adjacent first warp threads, and the first warp threads and the stretched second fibers are arranged in the same direction. Therefore, after the first warp thread is removed, each of the first positioning posts turned 90° can be disposed between every two adjacent second fibers and contact with two adjacent second fibers.
  • the second positioning column is originally arranged between two adjacent first weft threads, and the first weft threads and the stretched first fibers are arranged in the same direction.
  • each of the above-mentioned second positioning posts turned by 90° can be disposed between two adjacent first fibers and in contact with two adjacent first fibers. Based on this, through the first positioning column, the first distance H1 between two adjacent first warp threads can be controlled, and the third distance H3 between two adjacent second fibers can also be controlled. The first spacing H1 between two adjacent first wefts can be controlled through the second positioning column, and the third spacing H3 between two adjacent first fibers can also be controlled. In this way, there is no need to separately increase the positioning columns when positioning the first fibers and the second fibers, thereby reducing the number of positioning columns and simplifying the positioning process.
  • the first fibers and the second fibers are drawn from a wave shape to a straight shape.
  • the third distance H3 between two adjacent chips on the first fiber and the second fiber may be approximately the same as twice the second distance H2.
  • the third distance H3 between the two adjacent chips on the first fiber and the second fiber can be made to be the same as the two adjacent preset positions on the substrate.
  • the welding pitch Hb between them is the same or approximately the same.
  • the motherboard includes a substrate for carrying chips, and the substrate has a plurality of first alignment marks.
  • the method further includes overlapping the position of a first warp thread or a first weft thread in the stretchable layer with at least one first alignment mark. In this way, by aligning the stretchable layer with the motherboard, it is ensured that a vertical projection of an intersection point on the motherboard is located at the position of a chip on the motherboard.
  • the substrate has at least one second alignment mark.
  • the above-mentioned method further includes disposing the plurality of chips on the stretchable layer before the plurality of preset positions of the substrate.
  • a chip on the first fiber and the second fiber is controlled to overlap with a second alignment mark. Therefore, it can be ensured that each chip has a one-to-one correspondence with a preset position of the substrate.
  • the materials of the first warp threads and the first weft threads, and the second warp threads and the second weft threads include the first material.
  • the material of the first fiber and the second fiber includes the second material.
  • the first material and the second material are different.
  • At least removing the part of the first cloth layer located between two adjacent intersections includes: putting the stretchable layer with the chips pasted into the first solvent for dissolving the first material.
  • the first warp threads and the first weft threads, and the materials of the second warp threads and the second weft threads composed of the first material can be dissolved, while the first warp threads and the second weft threads composed of the second material can be dissolved.
  • the fibers and the second fibers may be insoluble in the first solvent described above.
  • removing at least the part of the first cloth layer located between two adjacent intersections includes: using a laser to pair the first warp, the part between the two adjacent intersections, and the first weft , the part between two adjacent intersections is cut.
  • the required lines can be selectively cut by setting the wavelength band of the laser.
  • the above method further includes: removing the second warp and the second weft, so that the first cloth layer and the second weft can be separated.
  • the second fabric layer is removed.
  • separating the plurality of chips includes cutting the motherboard to separate the plurality of chips.
  • the above-mentioned motherboard may be a wafer, so that a plurality of chips are formed on the substrate of the wafer at one time through the wafer preparation method.
  • removing the first fibers and the second fibers includes: using a laser stripping process to separate the adhesive layer from the chip, and extracting the first fibers and the second fibers.
  • the adhesive layer is irradiated with a laser to release its viscosity, so that the first fiber and the second fiber are only placed on the top of the chip and not attached to the chip, and then the first fiber and the second fiber are removed to remove the first fiber and the second fiber.
  • the purpose of the first fiber and the second fiber is used to remove the first fiber and the second fiber.
  • an electronic device including a display screen, and the display screen is prepared by any one of the above-mentioned chip transfer methods.
  • the electronic device has the same technical effect as the chip transfer method provided by the foregoing embodiments, and details are not described herein again.
  • FIG. 1a is a schematic structural diagram of an electronic device provided by an embodiment of the application.
  • Fig. 1b is a schematic diagram of an explosion structure of the electronic device shown in Fig. 1a;
  • Fig. 1c is a schematic diagram of an arrangement of micro LED chips in the display screen in Fig. 1b;
  • FIG. 1d is a schematic structural diagram of the pixel driving circuit provided on the substrate in FIG. 1c;
  • Fig. 2a is a schematic structural diagram of the micro LED chip in Fig. 1c;
  • Fig. 2b is a schematic structural diagram of a motherboard having the micro LED chip shown in Fig. 2a;
  • 3a is a schematic diagram of a chip transfer method provided by an embodiment of the present application.
  • FIG. 3b is a schematic diagram of another chip transfer method provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a chip transfer method provided by an embodiment of the present application.
  • FIG. 5a is a schematic structural diagram of a telescopic layer provided by an embodiment of the present application.
  • FIG. 5b is a schematic structural diagram of another telescopic layer provided by an embodiment of the present application.
  • FIG. 6a is a schematic diagram of locating a telescopic layer according to an embodiment of the present application.
  • FIG. 6b is a schematic structural diagram of the first positioning column in FIG. 6a;
  • Fig. 6c is another structural schematic diagram of the first positioning column in Fig. 6a;
  • FIG. 7 is a schematic diagram of pasting a stretchable layer and a motherboard according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of aligning the telescopic layer and the motherboard according to an embodiment of the present application.
  • FIG. 9a is a schematic diagram of forming an adhesive layer on the telescopic layer according to an embodiment of the present application.
  • Fig. 9b is another schematic diagram of pasting the stretchable layer and the motherboard according to the embodiment of the application.
  • Fig. 9c is another schematic diagram of pasting the stretchable layer and the motherboard according to the embodiment of the present application.
  • FIG. 10a is a schematic diagram of forming an adhesive layer in a motherboard where a chip is located according to an embodiment of the present application
  • FIG. 10b is another schematic diagram of forming an adhesive layer in a motherboard where a chip is located according to an embodiment of the present application;
  • 11a is a schematic diagram of forming a colloidal material layer on a motherboard according to an embodiment of the present application.
  • Fig. 11b is a schematic diagram of patterning the colloidal material layer shown in Fig. 11a;
  • FIG. 11c is another schematic diagram of pasting the stretchable layer and the motherboard according to the embodiment of the present application.
  • 12a is a schematic diagram of forming a colloidal material layer on a motherboard according to an embodiment of the present application
  • Fig. 12b is a schematic diagram of patterning the colloidal material layer shown in Fig. 12a;
  • Fig. 12c is another schematic diagram of pasting the stretchable layer and the motherboard according to the embodiment of the present application.
  • FIG. 13 is a schematic diagram of cutting a mother board pasted with a telescopic layer according to an embodiment of the application
  • Figure 14a is a schematic structural diagram after cutting the part of the first cloth layer in Figure 13;
  • Fig. 14b is a schematic structural diagram after the second cloth layer in Fig. 14a is removed;
  • Fig. 15 is another structural schematic diagram after the second cloth layer in Fig. 14a is removed;
  • FIG. 16 is a schematic structural diagram of the first fiber and the second fiber shown in FIG. 15 after drawing;
  • 17a is a schematic diagram of flipping the first positioning column according to an embodiment of the present application.
  • Fig. 17b is a schematic diagram of positioning the second fiber by using the first positioning column shown in Fig. 17a;
  • FIG. 18 is a schematic diagram of the positioning of the first fiber and the second fiber after drawing provided by an embodiment of the present application.
  • 19 is a schematic structural diagram of welding the chips on the stretched first fibers and the second fibers to a substrate;
  • 20 is a schematic diagram of aligning the first fiber and the second fiber after drawing with the substrate
  • 21 is a schematic diagram of a flip-chip structure provided by an embodiment of the present application.
  • FIG. 22 is a schematic structural diagram after removing the adhesive layer in FIG. 20;
  • FIG. 23 is a schematic view of the structure after removing the first fibers and the second fibers in FIG. 22 .
  • azimuth terms such as “upper”, “lower”, “horizontal”, and “longitudinal” may include, but are not limited to, definitions relative to the schematic placement of components in the drawings. It should be understood that, These directional terms may be relative concepts, and they are used for relative description and clarification, which may vary accordingly depending on the orientation in which the components are placed in the figures.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary.
  • electrical connection may be a direct electrical connection, or an indirect electrical connection achieved through an intermediate medium.
  • the embodiment of the present application provides a chip transfer method, which can be used to manufacture an electronic device with a display function.
  • the electronic device can be applied to various communication systems or communication protocols, such as: global system of mobile communication (GSM), code division multiple access (CDMA) system, wideband code division multiple access ( Wideband code division multiple access wireless, WCDMA), general packet radio service (general packet radio service, GPRS), long term evolution (long term evolution, LTE) and so on.
  • the electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a TV, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) ) terminal equipment and other electronic products with display function.
  • the embodiments of the present application do not specifically limit the specific form of the above-mentioned electronic device. For the convenience of description, the following description is made by taking the electronic device 01 as a mobile phone as shown in FIG. 1a as an example.
  • the electronic device 01 mainly includes a micro (micro) LED display panel (display panel, DP) 10 as shown in FIG. 1a, and a middle frame 11 and a housing 12 as shown in FIG. 1b.
  • the micro LED display screen 10 and the housing 12 are respectively located on both sides of the middle frame 11 and are connected to the middle frame 11 , and the middle frame 11 can be used to carry the micro LED display screen 10 .
  • the electronic device 01 may further include a printed circuit board (PCB) and a battery 13 disposed on the side surface of the middle frame 11 facing the housing 12 .
  • the housing 12 is connected with the middle frame 11 to form an accommodating cavity for accommodating the above-mentioned electronic devices such as PCB and battery. Therefore, it is possible to prevent water vapor and dust from outside from invading into the accommodating cavity, thereby affecting the performance of the above-mentioned electronic device.
  • the above-mentioned micro LED display screen 10 has an active display area (AA).
  • the AA area is used for displaying images, and the area around the AA area is used for setting the driving circuit.
  • the AA area is provided with a plurality of micro (micro) LED chips 101 (hereinafter referred to as: micro LED chips) as shown in FIG. 1c.
  • micro LED chips 101 can be used as a pixel of the micro LED display Driven to emit light individually.
  • a plurality of adjacent micro LED chips for emitting light of three primary colors such as the red-emitting micro-LED chip 101_R, the green-emitting micro-LED chip 101_G, and the blue-emitting micro-LED chip 101_B can constitute one pixel unit 102 .
  • the red light-emitting micro LED chip 101_R can be used as a red pixel
  • the green light-emitting micro LED chip 101_G can be used as a green pixel
  • the blue light-emitting micro LED chip 101_B can be used as a blue pixel.
  • the above-mentioned pixel unit 102 can be used as a repeating unit of pixel arrangement.
  • the pixel arrangement of the micro LED display screen 10 is the red pixel (micro LED chip 101_R), the green pixel (micro LED chip 101_G) and the blue pixel (micro LED chip 101_G) in the same pixel unit 102.
  • the LED chips 101_B) are located in the same row and have the same area as an example.
  • the arrangement of red, green, and blue primary color pixels can be determined according to requirements, which is not limited in this application.
  • the arrangement of the pixels of the above-mentioned micro LED display screen 10 may also be a Pentile pixel arrangement (also referred to as a P arrangement), an RGB-Delta pixel arrangement (also referred to as a P arrangement) with unequal areas of red pixels, blue pixels and green pixels. It can be called D arrangement) and so on.
  • the micro LED display screen 10 further includes a substrate 20 as shown in FIG. 1c.
  • the substrate 20 includes pixel driving circuits 201 arranged in an array as shown in FIG. 1d. Therefore, the above-mentioned substrate 20 may also be referred to as an array substrate.
  • the pixel driving circuit 201 may include a plurality of transistors T and at least one capacitor C. 1d, the pixel driving circuit 201 is a 2T1C structure, that is, including two transistors, such as thin film transistors (thin film transistors, TFT), such as T1 and T2, and a capacitor C as an example for description.
  • TFT thin film transistors
  • a pixel driving circuit 201 can be connected with the first electrode 110 of a micro LED chip 101 as shown in FIG. 2a, such as the anode (anode, a) in FIG. 1d, and the second electrode 120, such as the cathode ( cathode, c) electrical connection.
  • the pixel driving circuit 201 can individually apply voltage to the first electrode 110 and the second electrode 120 of each micro LED chip 101, and control the flow through the light emitting layer 130 in the micro LED chip 101 (as shown in FIG. 2a ). ) current. Therefore, the number of photons excited in the light-emitting layer 130 can be controlled, so as to achieve the purpose of controlling the light-emitting brightness of the micro LED chip 101 .
  • the manufacturing process of the micro LED chip 101 may be, as shown in FIG. 2b , the epitaxial layer 140 (including the above-mentioned light-emitting layer 130) as shown in FIG. 2a is fabricated on the motherboard 21, such as the substrate 100 of a wafer (wafer). . Next, the first electrode 110 and the second electrode 120 are formed on the above-mentioned epitaxial layer 140 . Then, the motherboard 21 can be cut to obtain a plurality of micro LED chips 101, so as to separate the plurality of LED chips 101.
  • the present application does not limit the material of the above-mentioned substrate 100, which may be sapphire, glass, silicon wafer, organic matter, or the like.
  • the motherboard 21 may be a carrier board for carrying a plurality of chips 101 .
  • the plurality of micro LED chips 101 on the carrier board need to be separated, the plurality of micro LED chips 101 can be separated from the carrier board, so that the carrier board does not need to be cut.
  • the following descriptions are all exemplified by taking the motherboard 21 as a wafer as an example.
  • the cut micro LED chip 101 can be transferred to the above-mentioned substrate 20 having the pixel driving circuit 201, and the first electrode 110 and the second electrode 120 of the micro LED chip 101 can be connected with the pixel
  • the drive circuit 201 is electrically connected.
  • the motherboard 21 can be used as a substrate for providing the micro LED chips 101, and the above-mentioned array substrate with the pixel driving circuit 201 can be used as a substrate for receiving the micro LED chips 101. substrate 20 .
  • the materials of the light emitting layers 130 of the multiple micro LED chips 101 in the same motherboard 21 are the same, so the light emitted by the multiple micro LED chips 101 in the same motherboard 21 is also the same .
  • the motherboard 21_R with the red-emitting micro LED chip 101_R and the motherboard 21_G with the green-emitting micro LED chip 101_G may be respectively fabricated .
  • the motherboard 21_B on which the blue light-emitting micro LED chip 101_B is made is separately separated.
  • the plurality of micro LED chips 101_R, the plurality of micro LED chips 101_G, and the plurality of micro LED chips 101_B are sequentially transferred to the same substrate 20 .
  • the motherboard 21 on which the blue-emitting micro LED chips 101_B are made may be separated and transferred to the substrate 20 .
  • a micro LED chip 101_B is selected, and a first phosphor layer (not shown in the figure) is coated on its light-emitting surface, and the first phosphor layer can be excited by blue light. glows red.
  • another micro LED chip 101_B is selected, and a second phosphor layer (not shown in the figure) is coated on the light-emitting surface thereof, and the second phosphor layer can emit green light under the excitation of blue light.
  • the phosphor layer is no longer coated on the surface of the other micro LED chip 101_B, so that it still emits blue light, thereby realizing the display of three primary colors.
  • the motherboard 21 on which the micro LED chips 101 for emitting ultraviolet light are made can be separated and transferred to the substrate 20 .
  • different fluorescent layers are respectively coated on the light-emitting surfaces of the three micro LED chips 101 in the same pixel unit 102 on the substrate 20, so that the different fluorescent layers can emit red light respectively under the excitation of the above-mentioned ultraviolet light , green light and blue light, thus realizing three primary color display.
  • the initial spacing Ha between two adjacent micro LED chips 101 in the motherboard 21 refers to the preset distance between the centers of the two adjacent micro LED chips 101 in the motherboard 21.
  • the initial distance Ha between two adjacent micro LED chips 101 in the above-mentioned motherboard 21 may also be, in the motherboard 21 The distance between a point within a certain range of the center of one micro LED chip 101 and a point within a certain range of the center of another micro LED chip 101 adjacent to the micro LED chip 101 .
  • the welding distance Hb between two adjacent preset positions on the substrate 20 refers to the preset distance between the respective centers of the two adjacent micro LED chips 101 after the micro LED chip 101 is expected to be welded on the substrate 20 . distance.
  • the welding distance Hb between the above-mentioned two adjacent preset positions can also be, after the micro LED chip 101 is expected to be welded on the substrate 20, the distance between one micro LED chip 101 The distance from a point within a certain range of its center to a point within a certain range of its center in another micro LED chip 101 adjacent to the micro LED chip 101 .
  • the following embodiments of the present application are taken as an example in which the distance between any two adjacent micro LED chips is the above-mentioned initial distance Ha along the horizontal or vertical direction in the motherboard 21, and the horizontal or vertical direction on the substrate 20 is used as an example.
  • the spacing between any adjacent preset positions is described by the above-mentioned welding spacing Hb as an example.
  • the chip transfer method for batch transferring the micro LED chips 101 in the motherboard 21 to the substrate 20 provided by the embodiment of the present application will be described in detail below. As shown in FIG. 4 , the chip transfer method includes S101 to S105 .
  • the stretchable layer 30 may include a plurality of first fibers 301 and a plurality of second fibers 302 , and a first cloth layer 31 and a second cloth layer 32 that are laminated.
  • the first fibers 301 extending in the first direction X and the second fibers 302 extending in the second direction Y intersect between the first fabric layer 31 and the second fabric layer 32, the first fibers 301 and the second fibers 302 There are multiple intersections 300 therebetween.
  • the first direction X and the second direction Y intersect, for example, they may be arranged vertically.
  • the first direction X and the second direction Y may constitute an XOY plane
  • the first cloth layer 31 may be parallel to the XOY plane
  • the second cloth layer 32 may be parallel to the XOY plane.
  • the stacking of the first fabric layer 31 and the second fabric layer 32 means that, along the Z direction perpendicular to the XOY plane, the first fabric layer 31 may be located below the second fabric layer 32, or the first fabric layer 31 may be located above the second cloth layer 32 .
  • FIG. 5 a is an example for illustrating that the first cloth layer 31 is located below the second cloth layer 32 .
  • the fact that the first fibers 301 and the second fibers 302 intersect between the first fabric layer 31 and the second fabric layer 32 means that the first fibers 301 are between the first fabric layer 31 and the second fabric layer 32 along the Extending in the first direction X (ie transverse direction), the second fibers 302 extend along the second direction Y (longitudinal direction) between the first cloth layer 31 and the second cloth layer 32 . Since the first direction X and the second direction Y intersect, for example, they may be arranged vertically. Therefore, one laterally extending first fiber 301 will intersect with a plurality of longitudinally extending second fibers 302 .
  • a longitudinally extending second fiber 302 will intersect a plurality of transversely extending first fibers 301 .
  • the first fibers 301 and the second fibers 302 may cross between the first cloth layer 31 and the second cloth layer 32 horizontally and vertically.
  • any two first fibers 301 may be parallel to each other, and any two second fibers 302 may be parallel to each other.
  • first distance H1 between two adjacent intersections 300
  • second distance H2 between the first cloth layer 31 and the second cloth layer 32
  • the size of the above-mentioned first spacing H1 can be set according to the position of the micro LED chips 101 to be transferred. .
  • two adjacent intersections 300 refer to two adjacent intersections 300 in a horizontal direction or a vertical position.
  • first direction X ie lateral direction
  • second direction Y ie, longitudinal direction
  • the above S101 may specifically include: first, as shown in FIG. 5b , cross a plurality of first warp threads 312 and a plurality of first weft threads 311 to form a first cloth layer 31 .
  • the distance between two adjacent first warp threads 312 is the same as the first distance H1
  • the distance between two adjacent first weft threads 311 is the same as the first distance H1.
  • any two first weft threads 311 may be parallel to each other, for example, as shown in FIG.
  • any two first warp threads 312 are parallel to each other, for example, any one of the first warp threads 312 may be parallel to the second direction Y, that is, arranged longitudinally.
  • the intersection of the plurality of first warp threads 312 and the plurality of first weft threads 311 means that one horizontally arranged first weft thread 311 will intersect with a plurality of longitudinally arranged first warp threads 312 .
  • one longitudinally arranged first warp 312 will cross a plurality of transversely arranged first wefts 311 .
  • the second cloth layer 32 is formed by intersecting a plurality of second warp threads 322 and a plurality of second weft threads 321 .
  • the distance between two adjacent second warp threads 322 is the same as the first distance H1
  • the distance between two adjacent second weft threads 321 is the same as the first distance H1.
  • the vertical projection of the second warp thread 322 on the first cloth layer 31 is located between two adjacent first warp threads 312, and the vertical projection of the second weft thread 321 on the first cloth layer 31 is located between two adjacent first cloth layers 31. Between the two wefts 321.
  • any two second wefts 321 may be parallel to each other.
  • any second weft 321 may be parallel to the first direction X, that is, arranged laterally.
  • Any two second meridians 322 are parallel to each other, for example, any one of the second meridians 322 may be parallel to the second direction Y, that is, arranged longitudinally.
  • the intersection of the plurality of second warp threads 322 and the plurality of second weft threads 321 means that one horizontally arranged second weft thread 321 crosses a plurality of longitudinally arranged second warp threads 322 .
  • one longitudinally arranged second warp 322 will cross a plurality of transversely arranged second wefts 321 .
  • the first cloth layer 31 may be parallel to the XOY plane as shown in FIG. 5b.
  • the above-mentioned vertical projection of the second warp 322 on the first fabric layer 31 refers to the projection of the second warp 322 on the first fabric layer 31 along the Z direction perpendicular to the XOY plane.
  • the vertical projection of the second weft 321 on the first cloth layer 31 refers to the projection of the second weft 321 on the first cloth layer 31 along the Z direction perpendicular to the XOY plane.
  • the following "vertical projection" method can be obtained in the same way, and will not be repeated one by one.
  • first fibers 301 cross the first warp 312 located below and the second warp 322 located above along the first direction X.
  • second fibers 302 cross the first weft 311 located below and the second weft 321 located above in the second direction Y. In this way, the first fibers 301 and the second fibers 302 can be crossed horizontally and vertically between the first cloth layer 31 and the second cloth layer 32 .
  • the second distance H2 in FIG. 5b is the distance between the second warp 322 in the second fabric layer 32 and the vertical projection of the second warp 322 on the first fabric layer 31 (represented by thin dotted lines) spacing representation.
  • the representations of the second distance H2 in the following drawings are the same, and will not be repeated one by one.
  • first fibers 301 and the second fibers 302 cross vertically and horizontally between the first fabric layer 31 and the second fabric layer 32 means that the first fibers 301 and the second fibers 302 not only cross horizontally and vertically, but also The first fibers 301 and the second fibers 302 also intersect with the first cloth layer 31 and the second cloth layer 32 described above.
  • the method for controlling the distance between two adjacent first warp threads 312 and the distance between two adjacent first weft threads 311 may be as shown in FIG.
  • a plurality of first positioning posts 41 are disposed around the board 21 , and one first positioning post 41 is disposed between every two adjacent first meridians 312 and is in contact with two adjacent first meridians 312 .
  • a plurality of second positioning pillars 42 are arranged around the motherboard 21 , and one second positioning pillar 42 is arranged between every two adjacent first weft threads 311 and is in phase with two adjacent first weft threads 311 . get in touch with.
  • the direction of the second geometric length L2 of the second positioning column 42 is perpendicular to the two adjacent first wefts 311 respectively.
  • a clamping member (not shown in the figure) can be used to control the distance between the two adjacent first warp threads 312.
  • the manipulator clamps both ends of each of the first warp threads 312 and the first weft threads 311 to prevent the first warp threads 312 and the first weft threads 311 from being in a loose state.
  • the second distance H2 (as shown in FIG. 5 b ) between the first cloth layer 31 and the second cloth layer 32 can also be adjusted by moving the manipulator.
  • the above description is given by taking an example that the cross-sections of the first positioning column 41 and the second positioning column 42 (parallel to the motherboard 21 ) are rectangular.
  • the first positioning column 41 may be a rectangular parallelepiped.
  • the cross-sectional dimensions of the first positioning column 41 and the second positioning column 42 may also be circular.
  • the first positioning column 41 may be a cylinder.
  • the first geometric length L1 of the first positioning post 41 refers to the distance between opposite sides of the first positioning post 41 along a direction perpendicular to the first meridian 312, such as the first direction X, .
  • the second geometric length L2 of the second positioning column 42 refers to the distance between two opposite sides of the second positioning column 42 along a direction perpendicular to the first weft 311 , eg, the second direction Y.
  • the above description is based on an example that the distance between any two adjacent micro LED chips 101 in the motherboard 21 is the above-mentioned first distance H1 (as shown in FIG. 7 ).
  • the spacing between two adjacent micro LED chips 101 in the motherboard 21 may also be different.
  • the first geometric length L1 of the first positioning column 41 and the second geometric length L2 of the second positioning column 42 can be set according to the spacing requirements, so as to meet the requirements of the difference between the two adjacent micro LED chips 101. spacing requirements.
  • the first cloth layer 31 can be close to the micro LED chip 101, and the second cloth layer 32 can be far away from the micro LED chip 101.
  • the positions of the first cloth layer 31 and the second cloth layer 32 may be interchanged. The following descriptions are given by taking the example that the first fabric layer 31 is closer to the micro LED chip 101 .
  • an intersection 300 of the first fiber 301 and the second fiber 302 in the stretchable layer 30 is aligned and pasted with a micro LED chip 101 in the motherboard 21 , so that the plurality of intersections 300 in the stretchable layer 30 and the plurality of micro LED chips 101 in the motherboard 21 are pasted one by one.
  • the alignment of an intersection 300 and a micro LED chip 101 in the motherboard 21 means that after the stretchable layer 30 and the micro LED chip 101 are pasted, the vertical projection of an intersection 300 on the motherboard 21 is the same as the micro LED chip 101 . At least a portion of the LED chips 101 overlap.
  • the vertical projection of an intersection 300 on the motherboard 21 may overlap the center of a micro LED chip 101 , or the vertical projection of an intersection 300 on the motherboard 21 may overlap with the center perimeter of a micro LED chip 101 Partially overlapping.
  • the vertical projection of a cross point 300 on the motherboard 21 may completely overlap with a micro LED chip 101 . Therefore, when S102 is executed, a cross point 300 can be accurately pasted with the position of a micro LED chip 101 in the motherboard 21 .
  • FIG. 8 is an example of setting one first alignment mark 51 at four corner positions around the substrate 100 as an example.
  • the material of the first alignment mark 51 may be a metal material, which is formed by a photolithography process (including processes such as masking, exposure, development, and etching).
  • a camera such as a charge coupled device (charge coupled device, CCD) may be used to acquire the positions of the first alignment mark 51 and the stretchable layer 30 .
  • the processor (not shown in the figure) can use the aforementioned manipulator to control the position of a first warp 312 or a first weft 311 on the edge of the telescopic layer 30 according to the acquisition result of the CCD, so that it can be connected with at least one first pair of The positions of the position markers 51 are overlapped, so as to achieve the purpose of aligning the stretchable layer 30 with the motherboard 21 .
  • the leftmost first meridian 312 in FIG. 8 overlaps with the positions of the upper and lower first alignment marks 51 on the left side of the substrate 100 .
  • the rightmost first meridian 312 overlaps with the positions of the upper and lower first alignment marks 51 on the right side of the substrate 100 .
  • the stretchable layer 30 and the The alignment accuracy of the motherboard 21 may not be lower than 0.5 ⁇ m. That is, the alignment accuracy between the stretchable layer 30 and the motherboard 21 is not lower than 5% of the size of a single side of the micro LED chip 101 .
  • the above S102 may include, as shown in FIG. 9a , first, at least on the first cloth layer 31 , coating the adhesive layer 60 at the intersection 300 of the first fiber 301 and the second fiber 302 . Then, as shown in FIG. 9 b , the side surface of the stretchable layer 30 coated with the adhesive layer 60 is pasted on the motherboard 21 so that the vertical projection of a cross point 300 on the motherboard 21 is the same as that of a micro in the motherboard 21 .
  • the LED chips 101 overlap.
  • the first embodiment may be, as shown in FIG. 9b, a cross point 300 in the stretchable layer 30 is separated from the micro LED chip 101 (the micro LED chip 101) through the adhesive layer 60 and the substrate 100 in the motherboard 21.
  • One side surface A1 located below the substrate 100 is pasted. In this way, the surface of the side where the first electrode 110 and the second electrode 120 are located in the micro LED chip 101 can be prevented from contacting the adhesive layer 60, thereby affecting the performance of the micro LED chip 101.
  • the micro LED chip 101 is located on the surface A2 of the substrate 100 , the surface A2 is disposed opposite to the surface A1 , and the surface A1 of the substrate 100 faces the stretchable layer 30 .
  • the vertical projection of an intersection 300 on the substrate 100 overlaps with the vertical projection of a micro LED chip 101 on the substrate 100 , thereby ensuring that an intersection 300 is aligned with a micro LED chip 101 in the motherboard 21 paste.
  • the second embodiment may be, as shown in FIG. 9c , a cross point 300 in the stretchable layer 30 passes through the adhesive layer 60 and the micro LED chip 101 (the micro LED chip 101 is located above the substrate 100 and is represented by a solid line).
  • the side surface away from the substrate 100 is pasted.
  • the surface A2 of the substrate 100 faces the stretchable layer 30, and the first fibers 301 and the second fibers 302 and the micro LED chip 101 are all located on the side where the surface A2 of the substrate 100 is located.
  • the vertical projection of an intersection 300 on the substrate 100 can still overlap with the vertical projection of a micro LED chip 101 on the substrate 100 by an intersection 300 .
  • the above S102 may include, as shown in FIG. 10a , firstly, dispensing glue on the motherboard 21 to form a plurality of glue layers 60 .
  • the vertical projection of one adhesive layer 60 on the motherboard 21 overlaps with a micro LED chip 101 in the motherboard 21, that is, the vertical projection of one adhesive layer 60 on the substrate 100 overlaps with a micro LED chip 101 on the substrate Vertical projections on 100 overlap.
  • a plurality of adhesive layers 60 can be formed through a dispensing process. of dispensing arrays.
  • the micro LED chip 101 is located on the surface A2 of the substrate 100 , and the surface A1 of the substrate 100 faces the adhesive layer 60 .
  • the side surface of the stretchable layer 30 where the first fabric layer 31 is located is pasted on the motherboard 21 through the above-mentioned adhesive layer 60 , so as to make a vertical projection of an intersection 300 on the motherboard 21 Overlap with a glue layer 60 .
  • the vertical projection of an adhesive layer 60 on the motherboard 21 overlaps with a micro LED chip 101 in the motherboard 21, so it can be ensured that a cross point 300 is pasted in alignment with a micro LED chip 101 through an adhesive layer 60 .
  • FIG. 9 b the side surface of the stretchable layer 30 where the first fabric layer 31 is located is pasted on the motherboard 21 through the above-mentioned adhesive layer 60 , so as to make a vertical projection of an intersection 300 on the motherboard 21 Overlap with a glue layer 60 .
  • the vertical projection of an adhesive layer 60 on the motherboard 21 overlaps with a micro LED chip 101 in the motherboard 21, so it can be ensured that a cross point 300 is pasted in alignment with a micro LED chip 101 through an adhesive layer 60 .
  • the adhesive layer 60 may be formed on the side surface of the micro LED chip 101 (the micro LED chip 101 is located above the substrate 100 and represented by a solid line) away from the substrate 100 through a dispensing process. At this time, the surface A2 of the substrate 100 faces the adhesive layer 60 .
  • the side surface of the stretchable layer 30 where the first fabric layer 31 is located is pasted on the motherboard 21 through the above-mentioned adhesive layer 60 , and a cross point 300 is connected to a micro LED in the motherboard 21 .
  • the chip 101 is adhered to the phase.
  • the first fibers 301 and the second fibers 302 and the micro LED chip 101 are all located on the side where the surface A2 of the substrate 100 is located.
  • the above S102 may include, as shown in FIG. 11 a , coating a colloidal material layer 61 on the motherboard 21 .
  • a colloidal material layer 61 may be coated on the side surface A1 of the substrate 100 away from the micro LED chip 101 (the micro LED chip 101 is indicated by a dotted line below the substrate 100).
  • the colloidal material layer 61 may cover the surface A1 of the substrate 100, so the surface A1 is not shown in FIG. 11a.
  • the micro LED chip 101 is located on the surface A2 of the substrate 100.
  • a mask exposure process can be used to pattern the colloidal material layer 61 , so that a plurality of adhesive layers 60 as shown in FIG.
  • the side surface of the stretchable layer 30 where the first fabric layer 31 is located is pasted on the motherboard 21 through the above-mentioned adhesive layer 60 , so that an intersection 300 and a micro LED in the motherboard 21 are The chip 101 is pasted in alignment. At this time, an intersection 300 is pasted to the side surface A1 of the substrate 100 away from the micro LED chip 101 through the above-mentioned adhesive layer 60 .
  • a colloidal material layer 61 may be coated on the side surface of the micro LED chip 101 away from the substrate 100.
  • the colloidal material layer 61 can cover the micro LED chip 101 and the substrate 100 .
  • a mask exposure process can be used to pattern the colloidal material layer 61, so that the adhesive layer 60 as shown in FIG. 12b is formed at the position of each micro LED chip 101 in the motherboard 21.
  • the side surface of the stretchable layer 30 where the first fabric layer 31 is located is pasted on the motherboard 21 through the above-mentioned adhesive layer 60 , so that an intersection 300 is connected to the substrate 100 of the motherboard 21 .
  • the previous micro LED chip 101 is pasted in position.
  • the first fibers 301 and the second fibers 302 and the micro LED chip 101 are all located on the side where the surface A2 of the substrate 100 is located.
  • An intersection 300 is pasted with the surface of the side of the micro LED chip 101 away from the substrate 100 through the above-mentioned adhesive layer 60 .
  • the glue layer 60 can be UV glue.
  • the UV glue can undergo a cross-linking reaction under the irradiation of a specific UV band to complete the curing. Wherein, the higher the curing degree, the stronger the adhesive layer 60 is.
  • the above-mentioned adhesive layer 60 may be formed by mixing at least one of acrylate or epoxy acrylate with a photoinitiator. In this case, when the adhesive layer 60 is irradiated with UV light with a wavelength of 345 nm, 365 nm, 385 nm or 405 nm, the adhesive layer 60 can undergo a cross-linking reaction to achieve curing.
  • UV curing treatment it is also possible to selectively perform UV curing treatment on specific positions of the adhesive layer 60 , so that the viscosity of the specific positions is higher, and the viscosity of other positions is lower.
  • a cross point 300 is pasted with the position of a micro LED chip 101 in the motherboard 21. Therefore, UV curing can be performed on a position of the adhesive layer 60 corresponding to one intersection 300 , thereby enhancing the adhesiveness of the adhesive layer 60 in this part.
  • the viscosity of the rest of the adhesive layer 60 is relatively weak, which facilitates the removal of the adhesive layer 60 in the subsequent process.
  • the above description is given by taking the example of pasting the side surface of the stretchable layer 30 where the first fabric layer 31 is located and the location of a micro LED chip 101 in the motherboard 21 as an example.
  • the side surface where the second fabric layer 32 is located can also be pasted with the location of a micro LED chip 101 in the motherboard 21 .
  • the pasting process is the same as the above, and will not be repeated here. .
  • a laser cutting process may be used to cut the substrate 100 of the motherboard 21, Thereby, the plurality of micro LED chips 101 are separated.
  • the above-mentioned motherboard 21 is a carrier board for carrying the micro LED chips 101
  • the plurality of micro LED chips 101 may be removed from the carrier board in the process of performing the above S103. break away.
  • the above S103 may specifically include, as shown in FIG. 14a , firstly using a laser to align the part of the first warp 312 between two adjacent intersections 300 and the first weft 311 The portion located between the intersections of two adjacent first fibers 301 and second fibers 302 is cut.
  • a laser may be used to focus the part of the first warp 312 between two adjacent intersections 300 and the part of the first weft 311 between two adjacent intersections 300, so that the part is Under the action of the laser, it can be cut, but the rest of the stretchable layer 30 will not be cut.
  • the material of the first cloth layer 31 may be different from the materials of the first fibers 301 and the second fibers 302 .
  • the material of the first cloth layer 31 can absorb the energy emitted by the laser, so that sublimation or melting occurs under the action of the energy, so that the first warp 312 in the first cloth layer 31 is located between two adjacent intersections 300 , and the portion of the first weft 311 located between two adjacent intersections 300 is cut off.
  • the materials of the first fiber 301 and the second fiber 302 can transmit the above-mentioned laser light and avoid absorbing the energy of the laser light, so that the first fiber 301 and the second fiber 302 will not be cut under the laser irradiation.
  • the second fabric layer 32 is not pasted with the adhesive layer 60, the second warp threads 322 and the second weft threads 321 can be directly extracted to form the structure shown in FIG. 14b, in which the first fibers 301 remain in FIG. 14b. , the second fibers 302 and some materials in the first cloth layer 31 . At this time, the second cloth layer 32 can be completely removed.
  • the materials of the first warp threads 312 and the first weft threads 311 and the second warp threads 322 and the second weft threads 321 may include the first material.
  • the material of the first fibers 301 and the second fibers 302 may include the second material. The first material and the second material are different.
  • the above S103 may specifically include placing the stretchable layer 30 pasted with the micro LED chip 101 into the first solvent for dissolving the first material.
  • the first warp threads 312 and the first weft threads 311, and the materials of the second warp threads 322 and the second weft threads 321, which are composed of the first material can be dissolved, and the second material
  • the constituted first fibers 301 and second fibers 302 may be insoluble in the above-mentioned first solvent.
  • the structure shown in FIG. 15 can be formed, and the first fiber 301 and the second fiber 302 are left in FIG. 15 .
  • the first cloth layer 31 and the second cloth layer 32 can be completely or almost completely removed.
  • the configuration of the first material, the second material, and the first solvent will be described below.
  • the first material that constitutes the first warp threads 312 and the first weft threads 311 and the materials of the second warp threads 322 and the second weft threads 321 can be cotton
  • the second material that constitutes the first fibers 301 and the second fibers 302 can be wool
  • the first solvent may be sulfuric acid having a concentration of 75% and a temperature of 24°C. In this way, cotton can be dissolved in the first solvent, but wool cannot be dissolved in the first solvent, so that the first cloth layer 31 and the second cloth layer 32 can be removed, and the first fibers 301 and the second fibers 302 can be retained. Purpose.
  • the first material constituting the first warp threads 312 and the first weft threads 311 and the materials of the second warp threads 322 and the second weft threads 321 can be acetate fibers, and the first fibers 301 and the second fibers 302 are constituted
  • the second material can be polyester.
  • the first solvent may be glacial acetic acid at a temperature of 24°C. In this way, the acetate fiber can be dissolved in the first solvent, but the polyester cannot be dissolved in the first solvent, so that the first cloth layer 31 and the second cloth layer 32 can be removed, and the first fibers 301 and the second fibers can be retained.
  • the first material constituting the first warp threads 312 and the first weft threads 311, and the materials of the second warp threads 322 and the second weft threads 321 may be cotton
  • the first material constituting the first fibers 301 and the second fibers 302 may be cotton.
  • the second material can be acrylic.
  • the first solvent may be fruit acid having a concentration of 75% and a temperature of 24°C. In this way, cotton fibers can be dissolved in the first solvent, while acrylic fibers cannot be dissolved in the first solvent, so that the first cloth layer 31 and the second cloth layer 32 can be removed, and the first fibers 301 and 302 can be retained. the goal of.
  • the first warp threads 312 and the first weft threads 311, and the second warp threads 322 and the second weft threads 321 may be It is prone to fracture under tension.
  • the first warp threads 312 and the first weft threads 311, as well as the second warp threads 322 and the second weft threads 321 will be broken, so as to remove the first cloth layer 31 located in the opposite direction.
  • the purpose of the portion between adjacent two intersections 300 is prone to fracture under tension.
  • the first fibers 301 and the second fibers 302 change from a wave shape to a straight shape.
  • the third distance H3 between the two adjacent micro LED chips 101 on the first fiber 301 and the second fiber 302 can be approximately 2 times the second distance H3
  • the spacing H2 is the same. In this way, after the first fibers 301 and the second fibers 302 are stretched, the third distance H3 between the two adjacent micro LED chips 101 on the first fibers 301 and the second fibers 302 can be consistent with the substrate 20 .
  • the welding spacing Hb between the two upper adjacent preset positions 70 is the same or approximately the same.
  • the first fiber 301 and the second fiber 302 are stretched between two adjacent micro LED chips 101
  • the distances along the horizontal direction (the first direction X) and the vertical direction (the second direction Y) are the above-mentioned third distance H3 as an example, and the distance between any adjacent preset positions on the substrate 20 along the horizontal direction or the vertical direction is the above-mentioned distance.
  • the welding pitch Hb will be explained as an example.
  • the above-mentioned preset position 70 may not be a mark that actually exists on the substrate 20 and can be recognized by human eyes.
  • the above-mentioned preset position 70 may be a preset position stored inside the chip welding device and used for welding the micro LED chip 101 as required. This position can be obtained by the alignment mark on the CCD acquisition substrate 20 .
  • performing the stretching of the first fibers 301 and the second fibers 302 may specifically include, firstly stretching the first fibers 301 and the second fibers 302 by the above-mentioned manipulator, so as to expand the adjacent two fibers. spacing between the micro LED chips 101 . Then, the plurality of first positioning posts 41 are turned over by 90° as shown in FIG. 17a. It can be seen from the above that the first positioning column 41 is originally disposed between two adjacent first warp threads 312 , and the first warp threads 312 and the stretched second fibers 302 are both disposed along the second direction Y.
  • each of the first positioning posts 41 turned 90° can be arranged between every two adjacent second fibers 302, as shown in FIG.
  • the two fibers 302 are in contact.
  • the first positioning column 41 is disposed between two adjacent second fibers 302 and is in contact with the two adjacent second fibers 302, the first geometric width B1 of the first positioning column 41 is set by setting the first positioning column 41. , the purpose of controlling the distance between two adjacent second fibers 302 to be the same as the third distance H3 can be achieved.
  • the above-mentioned plurality of second positioning columns 42 are turned over by 90°. It can be seen from the above that, as shown in FIG. 6a , the second positioning column 42 is originally arranged between two adjacent first weft threads 311 , and the first weft threads 311 and the stretched first fibers 301 are both arranged along the first direction X . Therefore, after the first weft 311 is removed, as shown in FIG. 18 , each of the second positioning posts 42 flipped by 90° can be disposed between two adjacent first fibers 301 and adjacent to two adjacent first fibers 301 contacts.
  • the first geometric width B1 of the first positioning column 41 refers to the distance between opposite sides of the first positioning column 41 along a direction perpendicular to the second fibers 302 , eg, the first direction X.
  • the second geometric width B2 of the second positioning column 42 refers to the distance between two opposite sides of the second positioning column 42 along a direction perpendicular to the first fibers 301 , eg, the second direction Y.
  • the above description is given by taking an example that the distance between any two adjacent micro LED chips 101 that are soldered on the substrate 20 is the same as the above-mentioned third distance H3 (as shown in FIG. 19 ). In other embodiments of the present application, the distances between two adjacent micro LED chips 101 soldered on the substrate 20 may also be different.
  • the first geometrical width B1 of the first positioning column 41 and the second geometrical width B2 of the second positioning column 42 can be set according to the spacing requirements, so as to meet the requirements of different adjacent micro LED chips 101 spacing requirements.
  • the first distance H1 between two adjacent first warp threads 312 can be controlled, and the third distance between two adjacent second fibers 302 can also be controlled.
  • H3 controls.
  • the first spacing H1 between two adjacent first weft threads 311 can be controlled through the second positioning column 42
  • the third spacing H3 between two adjacent first fibers 301 can also be controlled. In this way, there is no need to separately increase the positioning columns when positioning the first fibers 301 and the second fibers 302 , thereby reducing the number of positioning columns and simplifying the positioning process.
  • the micro LED chip 101 and the preset position 70 ( As shown in Figure 16) for alignment.
  • the micro LED chip 101 and the preset position 70 ( As shown in Figure 16) for alignment.
  • at least one second alignment mark 52 may be fabricated on the substrate 20 .
  • the manufacturing method of the second alignment mark 52 is the same as the manufacturing method of the first alignment mark 51 , and details are not described herein again.
  • the second alignment mark 52 and the positions of the micro LED chips 101 on the first fiber 301 and the second fiber 302 can be acquired by using a CCD.
  • the processor (not shown in the figure) can use the above-mentioned manipulator to control the position of a micro LED chip 101 on the first fiber 301 and the second fiber 302 to overlap with the position of a second alignment mark 52 according to the acquisition result of the CCD, Thereby, the purpose of aligning the micro LED chip 101 with the preset position 70 of the substrate 20 is achieved.
  • the first fibers 301 and the second fibers 302 can be pasted on the surface A1 of the substrate 100 , and the micro LED chip 101 is disposed on the surface A2 of the substrate 100 , the surface A1 and the surface A2 are set opposite to each other.
  • a flip-chip process can be used to solder a micro LED chip 101 to a preset position 70 (as shown in FIG. 16 ) on the substrate 20 .
  • the first electrode 110 and the second electrode 120 of the micro LED chip 101 are disposed close to the substrate 20, so that they can be directly soldered on the substrate 20 and connected with the pixel driving circuit 201 on the substrate 20 (as shown in FIG. 1d ). shown) electrical connection. In this way, the transmission efficiency of the circuit on the substrate 20 for providing electrical signals to the first electrode 110 and the second electrode 120 of the micro LED chip 101 can be improved.
  • the technology for packaging the micro LED chip 101 using the above flip-chip process is also different.
  • the technology for packaging the micro LED chip 101 using the above flip-chip process may be referred to as a chip on board (COB) technology.
  • COB chip on board
  • the technology of encapsulating the micro LED chip 101 using the flip-chip process may be referred to as chip on glass (COG) technology.
  • the substrate 20 when the substrate for carrying the above-mentioned pixel driving circuit 201 is a plastic substrate, the technology of using the above-mentioned flip-chip micro LED chip 101 for packaging can be referred to as a chip on plastic substrate packaging technology (chip on plastic, COP).
  • chip on plastic, COP chip on plastic
  • the first fibers 301 and the second fibers 302 and the micro LED chip 101 are all located on the side where the surface A2 of the substrate 100 is located.
  • the first electrode 110 and the second electrode 120 of the micro LED chip 101 are disposed away from the substrate 20, and a via hole (not shown in the figure) can be formed on the micro LED chip 101 through the epitaxial layer 140, so that the An electrode 110 and a second electrode 120 are soldered on the substrate 20 through different via holes.
  • a laser lift off (LLO) process may be used first to irradiate the adhesive layer 60 to release the adhesiveness of the adhesive layer 60 so that the adhesive layer 60 is separated from the micro LED chip 101 .
  • LLO laser lift off
  • the first fiber 301 and the second fiber 302 are only placed above the micro LED chip 101 and are not pasted with the micro LED chip 101 .
  • the first fibers 301 and the second fibers 302 are extracted to achieve the purpose of removing the first fibers 301 and the second fibers 302 .
  • the substrate 20 ie, the micro LED panel
  • the substrate 20 ie, the micro LED panel
  • the micro LED chips 101 are welded as shown in FIG. 23 can be cleaned, thereby completing the mass transfer process of the micro LED chips 101 .
  • the stretchable layer 30 before stretching can be pasted with each micro LED chip 101 in the motherboard 21 .
  • both the second warp threads 322 and the second weft threads 321 in the second fabric layer 32 and the first fabric layer 31 have the above-mentioned second distance H2 . Since the first fibers 301 intersect with the second warp threads 322 and the second fibers 302 intersect with the second weft threads 321 , the first fibers 301 and the second fibers 302 in the stretchable layer 30 before stretching can be wavy.
  • the first weft threads 311 and the first warp threads 312 in the first fabric layer 31 and the second weft threads 321 and the second warp threads 322 in the second fabric layer 32 can be aligned with each other.
  • the first distance H1 between two adjacent intersection points of the first fiber 301 and the second fiber 302 crossing the first cloth layer 31 and the second cloth layer 32 is controlled. Therefore, the first spacing H1 can be the same as the initial spacing Ha between two adjacent micro LED chips 101 in the motherboard 21 .
  • an intersection 300 is pasted with the position of one micro LED chip 101 in the motherboard 21.
  • the substrate of the mother board 21 can be cut, and the above-mentioned first cloth layer 31 and second cloth layer 32 can be removed.
  • the first fibers 301 and the second fibers 302 in the stretchable layer 30 are stretched to increase the space between the two adjacent micro LED chips 101 on the first fibers 301 and the second fibers 302
  • the distance between two adjacent micro LED chips 101 is changed from the original first distance H1 to the third distance H3.
  • the third distance H3 is the same as the welding distance Hb between two adjacent preset positions 70 on the substrate 20 .
  • the micro LED chips 101 located on the stretched first fibers 301 and the second fibers 302 can be welded to each of the preset positions 70 on the substrate 20 one by one. Then, the above-mentioned first fibers 301 and second fibers 302 are removed, and the formed micro LED chips 101 are cleaned to complete the mass transfer of the micro LED chips 101 .
  • the transfer head does not need to go back and forth between the mother board 21 serving as the donor substrate and the substrate 20, so as to achieve the purpose of improving the mass transfer efficiency of chips.
  • the micro LED chip in the motherboard is pasted before the film is not stretched, and then the micro LED chip is bound after stretching the film. on the circuit board.
  • the deformation amount of the film is determined by the material constituting the film, and the film is composed of the same material, the deformation amount of the film before and after stretching is basically the same. Therefore, the displacement of the micro LED chip at any position on the film is basically the same before and after the film is stretched.
  • the first distance H1 between any two adjacent intersection points of the first fibers 301 and the second fibers 302, and the first fibers 301 and the second fibers 302 can be adjusted according to requirements.
  • the arched height before unstretching ie the second distance H2 between the first cloth layer 31 and the second cloth layer 32
  • the application range is wider.

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Abstract

提供一种芯片转移方法、电子设备，涉及微发光二极管显示技术领域，用于改善巨量转移micro LED技术效率低的问题。该方法包括：首先，提供伸缩层。其中，伸缩层包括第一布料层和第二布料层，以及位于两者间的多条第一纤维、多条第二纤维。第一纤维与第二纤维之间具有多个交叉点。接下来，将伸缩层与芯片粘贴，且第一布料层相对于第二布料层更靠近芯片。接下来，分离多个芯片，分离的多个芯片分别与第一纤维和第二纤维相连接。接下来，将与伸缩层粘贴的多个芯片分别设置于基板的多个预设位置。最后，去除第一纤维和第二纤维。在芯片转移的过程中，无需转移头来回往复于母板与基板之间，达到提高芯片巨量转移效率的目的。

Description

一种芯片转移方法、电子设备
本申请要求于2020年07月24日提交国家知识产权局、申请号为202010726049.0、申请名称为“一种芯片转移方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及微发光二极管显示技术领域，尤其涉及一种芯片转移方法、电子设备。
背景技术
随着显示技术的发展，微元件化的制作工艺成为显示面板的一种发展趋势，例如微(mirco)发光二极管(light emitting diode，LED)技术。该micro LED技术是在供体(donor)基板，例如晶圆(wafer)上形成微米等级的micro LED。然后，将上述供体基板上的micro LED转移至受体(receptor)基板，例如电路板上，并阵列排布。每个micro LED可以作为一个像素(pixel)单独被驱动点亮，从而能够使得显示屏呈现出细腻度更高、对比度更强的画面。micro LED继承了LED的高效率、高亮度、高可靠度及反应时间快等特点，并且具自发光的特性，更具节能、机构简易、体积小、薄型等优势。此外，相比有机发光二极管(organic light emitting diode，OLED)显示屏，micro LED显示屏色彩更容易准确的调试，有更长的发光寿命和更高的亮度以及具有较佳的材料稳定性、寿命长、无影像烙印等优点。
目前，可以采用巨量并行拾放(massively parallel pick and place)技术，通过转移头分批次对供体基板上的micro LED进行拾取，并转移至基板上。由于转移头需要在供体基板和供体基板之间反复移动，且每次移动过程中对micro LED的拾取和放置均需要一定时间。因此，在制作分辨率较高的显示屏时，由于需转移的micro LED的数量巨大，导致生产效率太低，从而不足以支撑市场以及制作成本的期望。
发明内容
本申请提供一种芯片转移方法、电子设备，用于改善巨量转移micro LED技术效率低的问题。
为达到上述目的，本申请采用如下技术方案：
本申请的一方面，提供一种芯片转移方法，用于将母板中的芯片转移至基板。该方法包括：首先，提供伸缩层。其中，伸缩层可以包括多条第一纤维和多条第二纤维，以及层叠的第一布料层和第二布料层。第一纤维和第二纤维交叉于第一布料层和第二布料层之间，第一纤维与第二纤维之间具有多个交叉点。控制相邻两个交叉点之间具有第一间距H1，并控制第一布料层和第二布料层之间具有第二间距H2。接下来，将伸缩层与芯片粘贴。其中，该伸缩层中的第一布料层靠近芯片，第二布料层远离芯片。然后，分离多个芯片，分离的多个芯片分别与第一纤维和第二纤维相连接。接下来，将与伸缩层粘贴的多个芯片分别设置于基板的多个预设位置。最后，去除第一纤维和 第二纤维。
综上所述，本申请提供的一种芯片转移方法中，可以将伸缩层与母板中的每个芯片粘贴。第一布料层和第二布料层之间具有第二间距H2，能够使得拉伸之前伸缩层中的第一纤维和第二纤维呈波浪状。此外，通过对第一纤维和第二纤维的相邻两个交叉点之间的第一间距H1进行控制，使得第一间距H1能够与母板上两个芯片之间的间距相同。在此情况下，当将未拉伸之前的伸缩层与母板上的多个芯片粘贴后，第一纤维和第二纤维的一个交叉点与母板上一个芯片所在位置相粘贴。在此基础上，当伸缩层与母板粘贴后，可以对母板中的多个芯片进行分离。接下来，可以将位于伸缩层上的多个芯片设置于基板上的各个预设位置上。然后去除第一纤维和第二纤维，以完成芯片的巨量转移。由上述可知，本申请提供的芯片转移方式中，只需要将伸缩层与母板上的多个芯片相粘贴。然后，将伸缩层上的芯片设置于基板上。这样一来，可以将同一个母板上的大部分，甚至所有的芯片一次性的全部转移至基板上。因此在芯片转移的过程中，无需转移头来回往复于母板与基板之间，达到提高芯片巨量转移效率的目的。
可选的，提供伸缩层包括将多条第一经线和多条第一纬线交叉形成第一布料层。其中，相邻两条第一经线之间的间距与第一间距H1相同，相邻两条第一纬线之间的间距与第一间距H1相同。并且，将多条第二经线和多条第二纬线交叉形成第二布料层。其中，相邻两条第二经线之间的间距与第一间距H1相同，相邻两条第二纬线之间的间距与第一间距H1相同。第二经线在第一布料层上的垂直投影，位于相邻两条第一经线之间，第二纬线在第一布料层上的垂直投影，位于相邻两条第二纬线之间。这样一来，可以对伸缩层中，第一布料层中交叉的第一纬线和第一经线，以及第二布料层中交叉的第二纬线和第二经线的位置进行控制，从而使得第一间距H1能够与母板两个芯片之间的间距相同。
可选的，第一纤维与第一经线和第二经线交叉，并且第二纤维与第一纬线和第二纬线交叉。这样一来，可以使得第一纤维和第二纤维均与第一布料层和第二布料层交叉。
可选的，上述将伸缩层与芯片粘贴包括：将一个交叉点与母板中的一个芯片对位粘贴。由于交叉点的位置可以控制，所以能够根据需要对母板上的芯片进行粘贴。
可选的，母板中相邻两个芯片之间具有初始间距Ha，Ha＝H1。这样一来，伸缩层上的多个交叉点可以与母版中多个芯片一一对位粘贴，从而可以将母板中的芯片全部转移。
可选的，将一个交叉点与母板中的一个芯片对位粘贴包括：在第一布料层上，交叉点处涂覆胶层。然后，将伸缩层涂覆有胶层的一侧表面粘贴于母板上，使得一个交叉点在母板上的垂直投影与母板中的一个芯片重叠。这样可以在第一布料层上形成胶层，并通过该胶层将伸缩层粘贴于母板上。
可选的，将一个交叉点与母板中的一个芯片对位粘贴包括在母板上点胶形成多个胶层，一个胶层在母板上的垂直投影与母板中一个芯片重叠。然后，将第一布料层所在的一侧表面通过多个胶层阵列粘贴于母板上，使得一个交叉点在母板上的垂直投影与一个胶层重叠。通过在母板上的每个芯片所在的位置点胶形成胶层阵列，并通过该 胶层阵列将伸缩层粘贴于母板上。
可选的，将一个交叉点与母板中的一个芯片对位粘贴包括：在母板上涂覆胶体材料层，并对胶体材料层进行图案化，使得母板上形成多个胶层，一个胶层在母板上的垂直投影与母板中一个芯片重叠。然后，将第一布料层所在的一侧表面通过胶层粘贴于母板上，使得一个交叉点在母板上的垂直投影与一个胶层重叠。这样一来，母板上多个胶层可以在同一次掩膜曝光工艺中形成，因此可以提高制作工艺的效率。
可选的，母板包括用于承载芯片的衬底。将伸缩层与芯片粘贴包括将伸缩层粘贴于衬底远离芯片的一侧表面上。这样一来，可以避免芯片中第一电极和第二电极所在的一侧表面接触到胶层，从而对芯片的性能造成影响。
可选的，芯片包括第一电极和第二电极。将伸缩层上的多个芯片分别设置于基板的多个预设位置包括：采用倒装工艺，在预设位置，将一个芯片的第一电极和第二电极靠近基板，并焊接于基板上。上述倒装工艺可以使得芯片的第一电极和第二电极直接焊接于基板上，从而提高向第一电极和第二电极传输电信号的效率。
可选的，分离多个芯片之后，将伸缩层上的多个芯片分别设置于基板的多个预设位置之前，方法还包括：将第一纤维和第二纤维拉伸，使第一纤维和第二纤维上相邻两个芯片之间具有第三间距H3。其中，基板上相邻两个预设位置之间具有焊接间距Hb，H3＝Hb。这样一来，可以将伸缩层上的所有芯片均转移至基板上。
可选的，相邻两条第一经线之间的间距与所述第一间距H1相同，相邻两条第一纬线之间的间距与第一间距H1相同包括：在母板的周边设置多个第一定位柱；将一个第一定位柱设置于每相邻两条第一经线之间，且与相邻两条第一经线相接触。第一定位柱具有第一几何长度L1，L1＝H1。并且，在母板的周边设置多个第二定位柱。此外，将一个第二定位柱设置于每相邻两条第一纬线之间，且与相邻两条第一纬线相接触。第二定位柱具有第二几何长度L2，L2＝H1。其中，第一定位柱的第一几何长度L1的方向与相邻两条第一经线分别垂直；第二定位柱的第二几何长度L2的方向与相邻两条第一纬线分别垂直。这样一来，由于第一定位柱设置于相邻两条第一经线之间，且与相邻两条第一经线相接触，因此通过设置第一定位柱的第一几何长度L1，就可以达到控制邻两条第一经线之间的间距，使其与第一间距H1相同的目的。此外，通过设置第二定位柱的第二几何长度L2，就可以达到控制邻两条第一纬线之间的间距，使其与第一间距H1相同的目的。其中，第二定位柱的第二几何长度L2的方向与相邻两条第一纬线分别垂直。
可选的，将第一纤维和第二纤维拉伸，控制第一纤维和第二纤维上相邻两个芯片之间具有第三间距H3包括：对第一纤维和第二纤维进行拉伸。接下来，将多个第一定位柱翻转90°，并将一个第一定位柱设置于每相邻两条第二纤维之间，且与相邻两条第二纤维相接触；第一定位柱具有第一几何宽度B1，B1＝H3。然后，将多个第二定位柱翻转90°，并将一个第二定位柱设置于每相邻两条第一纤维之间，且与相邻两条第一纤维相接触；第二定位柱具有第二几何宽度B2，B2＝H3。其中，第一定位柱的第一几何宽度B1的方向与相邻两条第二纤维分别垂直；第二定位柱的第二几何宽度B2的方向与相邻两条第一纤维分别垂直。由上述可知，原本第一定位柱设置于相邻两条第一经线之间，而第一经线和拉伸后的第二纤维均沿同一方向设置。因此当第一经线 去除后，上述翻转90°的每个第一定位柱可以设置于每相邻两条第二纤维之间，且与相邻两条第二纤维相接触。同理原本第二定位柱设置于相邻两条第一纬线之间，而第一纬线和拉伸后的第一纤维均沿同一方向设置。因此当第一纬线去除后，上述翻转90°的每个第二定位柱可以设置于相邻两条第一纤维之间，且与相邻两条第一纤维相接触。基于此，通过第一定位柱，即可以对相邻两条第一经线之间的第一间距H1进行控制，还可以对相邻两条第二纤维之间的第三间距H3进行控制。通过第二定位柱即可以对相邻两条第一纬线之间的第一间距H1进行控制，还可以对相邻两条第一纤维之间的第三间距H3进行控制。这样一来，无需在对第一纤维和第二纤维定位时单独增加定位柱，从而能够减少定位柱的数量，简化定位过程。
可选的，第二间距H2和焊接间距Hb之间满足：H2＝Hb/2。这样一来，第一纤维和第二纤维拉伸之前，第一纤维和第二纤维为波浪形，波浪拱起的高度即为上述第二间距H2。在对第一纤维和第二纤维拉伸过程中，第一纤维和第二纤维拉伸由波浪状变成直线状。当第一纤维和第二纤维的弹性形变量较小时，第一纤维和第二纤维上相邻两个芯片之间的第三间距H3可以近似与2倍的第二间距H2相同。这样一来，可以在对第一纤维和第二纤维拉伸后，使得第一纤维和第二纤维上相邻两个芯片之间的第三间距H3，与基板上相邻两个预设位置之间的焊接间距Hb相同或近似相同。
可选的，母板包括用于承载芯片的衬底，衬底上具有多个第一对位标。将伸缩层与芯片粘贴之前，方法还包括将伸缩层中的一条第一经线或者一条第一纬线的位置与至少一个第一对位标重叠。这样一来，通过对伸缩层与母板进行对位，以确保一个交叉点在母板上的垂直投影，位于母板上一个芯片所在位置处。
可选的，基板上具有至少一个第二对位标。上述将伸缩层上的多个芯片分别设置于基板的多个预设位置之前，方法还包括。控制第一纤维和第二纤维上的一个芯片与一个第二对位标重叠。从而可以确保每个芯片与基板的一个预设位置一一对应。
可选的，第一经线和第一纬线，以及第二经线和第二纬线的材料包括第一材料。第一纤维、第二纤维的材料包括第二材料。第一材料和第二材料不同。至少去除第一布料层中，位于相邻两个交叉点之间的部分包括：将粘贴有芯片的伸缩层放入用于溶解第一材料的第一溶剂中。这样一来，在该第一溶剂的作用下，可以将由第一材料构成的第一经线和第一纬线，以及第二经线和第二纬线的材料溶解，而由第二材料构成的第一纤维和第二纤维可以不溶于上述第一溶剂中。
可选的，至少去除第一布料层中，位于相邻两个交叉点之间的部分包括：采用激光对第一经线中，位于相邻两个交叉点之间的部分，以及第一纬线中，位于相邻两个交叉点之间的部分进行切割。通过设置激光的波段可以选择性的对需要的线条进行切割。
可选的，分离多个所述芯片之后，将第一纤维和第二纤维拉伸之前，上述方法还包括：去除所述第二经线和所述第二纬线，从而可以将第一布料层和第二布料层均去除。
可选的，分离多个所述芯片包括对母板进行切割，以将多个芯片分离。在此情况下，上述母板可以为晶圆，从而通过晶圆的制备方法一次在晶圆的衬底上形成多个芯片。
可选的，去除第一纤维和第二纤维包括：采用激光剥离工艺，将胶层与芯片分离，并抽去第一纤维和第二纤维。采用激光对胶层进行照射，以释放其粘性，使得第一纤维和第二纤维仅仅放置于芯片上方，并未与芯片相粘贴，然后再将第一纤维和第二纤维抽去，达到去除第一纤维和第二纤维的目的。
本申请的另一方面，提供一种电子设备，包括显示屏，该显示屏采用如上所述的任意一种芯片转移方法制备。该电子设备具有与前述实施例提供的芯片转移方法相同的技术效果，此处不再赘述。
附图说明
图1a为本申请实施例提供的一种电子设备的结构示意图；
图1b为图1a所示的电子设备的爆炸结构示意图；
图1c为图1b中显示屏中micro LED芯片的一种排布方式示意图；
图1d为图1c中基板上设置的像素驱动电路的一种结构示意图；
图2a为图1c中micro LED芯片的一种结构示意图；
图2b为具有图2a所示的micro LED芯片的母板的一种结构示意图；
图3a为本申请实施例提供的一种芯片转移方式的示意图；
图3b为本申请实施例提供的另一种芯片转移方式的示意图；
图4为本申请实施例提供的一种芯片转移方式的流程图；
图5a为本申请实施例提供的一种伸缩层的结构示意图；
图5b为本申请实施例提供的另一种伸缩层的结构示意图；
图6a为本申请实施例提供的一种对伸缩层进行定位的示意图；
图6b为图6a中第一定位柱的一种结构示意图；
图6c为图6a中第一定位柱的另一种结构示意图；
图7为本申请实施例提供的将伸缩层与母板粘贴的一种示意图；
图8为本申请实施例提供的将伸缩层与母板对位的一种示意图；
图9a为本申请实施例提供的在伸缩层上形成胶层的一种示意图；
图9b为本申请实施例提供的将伸缩层与母板粘贴的另一种示意图；
图9c为本申请实施例提供的将伸缩层与母板粘贴的另一种示意图；
图10a为本申请实施例提供的在母板中芯片所在位置形成胶层的一种示意图；
图10b为本申请实施例提供的在母板中芯片所在位置形成胶层的另一种示意图；
图11a为本申请实施例提供的在母板上形成胶体材料层的示意图；
图11b为对图11a所示的胶体材料层进行图案化的示意图；
图11c为本申请实施例提供的将伸缩层与母板粘贴的另一种示意图；
图12a为本申请实施例提供的在母板上形成胶体材料层的示意图；
图12b为对图12a所示的胶体材料层进行图案化的示意图；
图12c为本申请实施例提供的将伸缩层与母板粘贴的另一种示意图；
图13为本申请实施例提供的将与伸缩层粘贴的母板进行切割的示意图；
图14a为将图13中的第一布料层的部分进行切割后的结构示意图；
图14b为将图14a中的第二布料层去除后的一种结构示意图；
图15为将图14a中的第二布料层去除后的另一种结构示意图；
图16为将图15所示的第一纤维和第二纤维拉伸后的结构示意图；
图17a为本申请实施例提供的对第一定位柱进行翻转的示意图；
图17b为采用图17a所示的第一定位柱对第二纤维进行定位的示意图；
图18为本申请实施例提供的对拉伸后的第一纤维和第二纤维定位的示意图；
图19为将拉伸后的第一纤维和第二纤维上的芯片焊接于基板上的结构示意图；
图20为将拉伸后的第一纤维和第二纤维与基板进行对位的示意图；
图21为本申请实施例提供的芯片倒装结构的示意图；
图22为去除图20中的胶层后的结构示意图；
图23为去除图22中的第一纤维和第二纤维后的结构示意图。
附图标记：
01-电子设备；10-micro LED显示屏；11-中框；12-壳体；13-电池；101-micro LED芯片；102-像素单元；20-基板；201-像素驱动电路；100-衬底；110-第一电极；120-第二电极；130-发光层；140-外延层；21-母板；30-伸缩层；31-第一布料层；32-第二布料层；301-第一纤维；302-第二纤维；311-第一纬线；312-第一经线；321-第二纬线；322-第二经线；41-第一定位柱；42-第二定位柱；300-交织点；51-第一对位标；52-第二对位标；60-胶层；61-胶体材料层；70-预设位置。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请实施例中，“上”、“下”、“横向”、“纵向”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，“电连接”可以是直接的电性连接，或者通过中间媒介实现间接的电性连接。
本申请实施例提供一种芯片转移方法，可以用于制作具有显示功能的电子设备。该电子设备可以应用于各种通信系统或通信协议，例如：全球移动通信系统(global system of mobile communication，GSM)、码分多址(code division multiple access，CDMA)系统、宽带码分多址(wideband code division multiple access wireless，WCDMA)、通用分组无线业务(general packet radio service，GPRS)、长期演进(long term evolution，LTE)等。该电子设备可以包括手机(mobile phone)、平板电脑(pad)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality AR)终端设备等具有显示功能的电子产品。本申请 实施例对上述电子设备的具体形式不做特殊限制，以下为了方便说明，是以电子设备01为如图1a所示的手机为例进行的说明。
该电子设备01主要包括如图1a所示的微型(micro)LED显示屏(display panel，DP)10，以及如图1b所示的中框11和壳体12。micro LED显示屏10和壳体12分别位于中框11的两侧，且与中框11相连接，中框11可以用于承载micro LED显示屏10。此外，电子设备01还可以包括设置于中框11朝向壳体12的一侧表面上的印刷电路板(printed circuit boards，PCB)和电池13。壳体12与中框11相连接形成用于容纳上述PCB、电池等电子器件的容纳腔。从而可以防止外界的水汽和尘土侵入该容纳腔内，对上述电子器件的性能造成影响。
上述micro LED显示屏10具有有效显示区(active area，AA)。AA区用于显示图像，该AA区周边的区域用于设置驱动电路。该AA区内设置有多个如图1c所示的微型(micro)LED芯片101(以下简称：micro LED芯片)，每个micro LED芯片101可以作为micro LED显示屏10的像素(pixel)，被单独驱动发光。基于此，多个相邻的，且分别用于发出三原色光线的micro LED芯片，例如发红光的micro LED芯片101_R、发绿光的micro LED芯片101_G以及发蓝光的micro LED芯片101_B可以构成一个像素单元102。
在此情况下，发红光的micro LED芯片101_R可以作为红色像素，发绿光的micro LED芯片101_G可以作为绿色像素，发蓝光的micro LED芯片101_B可以作为蓝色像素。此外，在AA区内，上述像素单元102可以作为像素排布的重复单元。
需要说明的是，图1c是以micro LED显示屏10的像素排布方式为同一个像素单元102中的红色像素(micro LED芯片101_R)、绿色像素(micro LED芯片101_G)以及蓝色像素(micro LED芯片101_B)依次位于同一排，且面积相等为例进行的说明。关于红、绿、蓝三原色像素的排列方式可以根据需求而定，本申请对此不做限定。例如，上述micro LED显示屏10的像素的排列方式还可以为红色像素、蓝色像素以及绿色像素面积不相等的Pentile像素排列方式(也可以称为P排列)、RGB-Delta像素排列方式(也可以称为D排列)等。
为了能够对micro LED显示屏10中的每个micro LED芯片101单独进行驱动，该micro LED显示屏10还包括如图1c所示的基板20。基板20包括如图1d所示的，阵列排布的像素驱动电路201。因此上述基板20也可以称为阵列基板(array substrate)。该像素驱动电路201可以包括多个晶体管T和至少一个电容C。其中，图1d是以像素驱动电路201为2T1C结构，即包括两个晶体管，例如薄膜晶体管(thin film transistor，TFT)，例如T1和T2，以及一个电容C为例进行的说明。
在此情况下，一个像素驱动电路201可以与如图2a所示的一个micro LED芯片101的第一电极110，例如图1d中的阳极(anode，a)，以及第二电极120，例如阴极(cathode，c)电连接。这样一来，可以通过像素驱动电路201单独对向每个micro LED芯片101的第一电极110和第二电极120施加电压，并控制流过micro LED芯片101中发光层130(如图2a所示)的电流。从而可以控制发光层130中激发出光子的数量，达到控制micro LED芯片101发光亮度的目的。
上述micro LED芯片101的制作过程可以为，如图2b所示，在母板21，例如晶 圆(wafer)的衬底100上制作如图2a所示的外延层140(包括上述发光层130)。接下来，在上述外延层140上制作第一电极110和第二电极120。然后对母板21进行切割可以得到多个micro LED芯片101，以将多个LED芯片101分离。
需要说明的是，本申请对上述衬底100的材料不做限定，可以为蓝宝石、玻璃、硅片、有机物等。此外，上述是以母板21为晶圆为例进行的说明，在本申请的另一些实施例中，母板21可以为用于承载多个芯片101的承载板。在此情况下，当需要将该承载板上的多个micro LED芯片101分离时，将多个micro LED芯片101从承载板上脱离即可，从而无需对承载板进行切割。以下为了方便说明，均是以母板21为晶圆为例进行的举例说明。
接下来，为了制作micro LED显示屏10，可以将切割后的micro LED芯片101转移至上述具有像素驱动电路201的基板20，并将micro LED芯片101的第一电极110和第二电极120与像素驱动电路201电连接。基于此，在转移上述micro LED显示屏10的过程中，母板21可以作为用于提供micro LED芯片101的基板，而上述具有像素驱动电路201的阵列基板可以作为用于接受micro LED芯片101的基板20。
在制作micro LED芯片101的过程中，同一片母板21中的多个micro LED芯片101的发光层130的材料相同，因此同一片母板21中的多个micro LED芯片101发出的光线也相同。基于此，在本申请的一些实施例中，如图3a所示，可以分别对制作有发红光的micro LED芯片101_R的母板21_R、制作有发绿光的micro LED芯片101_G的母板21_G、制作有发蓝光的micro LED芯片101_B的母板21_B分别进行分离。接下来，依次将多个micro LED芯片101_R、多个micro LED芯片101_G以及多个micro LED芯片101_B转移至同一个基板20上。
或者，在本申请的另一些实施例中，如图3b所示，可以对制作有发蓝光的micro LED芯片101_B的母板21进行分离，并将其转移至基板20上。接下来，在基板20上位于同一个像素单元102中，选取一个micro LED芯片101_B，并在其发光面涂覆第一荧光层(图中未示出)，该第一荧光层可以在蓝光激发下发出红光。此外，选取另一个micro LED芯片101_B，并在其发光面涂覆第二荧光层(图中未示出)，该第二荧光层可以在蓝光激发下发出绿光。此外，在另一个micro LED芯片101_B的表面不再涂覆荧光层，使其仍然发蓝光，从而实现三原色显示。
或者，在本申请的另一些实施例中，可以对制作有发紫外光的micro LED芯片101的母板21进行分离，并将其转移至基板20上。接下来，在基板20上位于同一个像素单元102中的三个micro LED芯片101的发光面分别涂覆不同的荧光层，使得不同的荧光层能够在上述紫外光的激发下，分别发出红光、绿光以及蓝光，从而实现三原色显示。
以图3b所示的micro LED芯片批量转移方式为例，母板21中相邻两个micro LED芯片之间具有初始间距Ha。当将母板21中的micro LED芯片转移至基板20上后，基板20上相邻两个用于焊接micro LED芯片101的预设位置之间具有焊接间距Hb。其中，Hb＞Ha。
需要说明的是，母板21中相邻两个micro LED芯片101之间的初始间距Ha是指，母板21中相邻两个micro LED芯片101各自的中心之间的预设距离。或者，当上述母 板21为晶圆时，在晶圆制作工艺精度允许的范围内，上述母板21中相邻两个micro LED芯片101之间的初始间距Ha也可以是，母板21中一个micro LED芯片101中距离其中心一定范围内的一点，到与该micro LED芯片101相邻的另一个micro LED芯片101中距离其中心一定范围内的一点之间的距离。
此外，基板20上相邻两个预设位置之间的焊接间距Hb是指，预计将micro LED芯片101焊接于基板20上后，相邻两个micro LED芯片101各自的中心之间的预设距离。或者，在焊接对位精度允许的范围内，上述相邻两个预设位置之间的焊接间距Hb也可以是，预计将micro LED芯片101焊接于基板20上后，一个micro LED芯片101中距离其中心一定范围内的一点，到与该micro LED芯片101相邻的另一个micro LED芯片101中距离其中心一定范围内的一点之间的距离。
本申请以下实施例为了方便说明，是以母板21中沿横向或者纵向，任意相邻两个micro LED芯片之间的间距均为上述初始间距Ha为例，且基板20上沿横向或者纵向，任意相邻预设位置之间的间距均为上述焊接间距Hb为例进行的说明。
以下对本申请实施例提供的用于将母板21中的micro LED芯片101，批量转移至基板20上的芯片转移方法进行详细的说明。该芯片转移方法如图4所示包括S101～S105。
S101、提供伸缩层30。
如图5a所示，伸缩层30可以包括多条第一纤维301和多条第二纤维302，以及层叠的第一布料层31和第二布料层32。沿第一方向X延伸的第一纤维301，以及与沿第二方向Y延伸的第二纤维302交叉于第一布料层31和第二布料层32之间，第一纤维301与第二纤维302之间具有多个交叉点300。其中，第一方向X和第二方向Y相交，例如可以垂直设置。
需要说明的是，如图5a所示，上述第一方向X和第二方向Y可以构成XOY平面，第一布料层31可以与该XOY平面平行，第二布料层32可以与该XOY平面平行。在此情况下，第一布料层31和第二布料层32层叠是指，沿垂直于XOY平面的Z方向，第一布料层31可以位于第二布料层32的下方，或者，第一布料层31可以位于第二布料层32的上方。其中，图5a是以第一布料层31位于第二布料层32的下方为例进行的说明。
示例的，第一纤维301和第二纤维302交叉于第一布料层31和第二布料层32之间是指，第一纤维301在第一布料层31和第二布料层32之间，沿第一方向X(即横向)延伸，第二纤维302在第一布料层31和第二布料层32之间，沿第二方向Y(纵向)延伸。由于第一方向X和第二方向Y相交，例如可以垂直设置，因此，一条横向延伸的第一纤维301会与多条纵向延伸的第二纤维302交叉。同理，一条纵向延伸的第二纤维302会与多条横向延伸的第一纤维301交叉。在此情况下，第一纤维301和第二纤维302可以横纵交叉于第一布料层31和第二布料层32之间。可选的，任意两条第一纤维301之间可以相互平行，任意两条第二纤维302之间可以相互平行。
此外，上述伸缩层30中，相邻两个交叉点300之间具有第一间距H1，并且第一布料层31和第二布料层32之间具有第二间距H2。在本申请的一些实施例中，如图3b所示，母板21中相邻两个micro LED芯片101之间可以具有初始间距Ha。上述第 一间距H1与上述初始间距Ha之间可以满足：H1＝Ha。或者，在本申请的另一些实施例中，当无需将母板21中所有的micro LED芯片101进行转移时，上述第一间距H1的大小可以根据需要转移的micro LED芯片101的位置进行设定。
需要说明的是，本申请实施例中，相邻两个交叉点300是指沿横向，或者纵向位置相邻的两个交叉点300。例如，如图5a所示，在第一方向X(即横向)上，处于相邻位置的两个交叉点300。或者，在第二方向Y(即纵向)上，处于相邻位置的两个交叉点300。
在本申请的一些实施例中，上述S101具体可以包括：首先，如图5b所示，将多条第一经线312和多条第一纬线311交叉形成第一布料层31。其中，相邻两条第一经线312之间的间距与第一间距H1相同，相邻两条第一纬线311之间的间距与第一间距H1相同。需要说明的是，本申请实施例中，任意两条第一纬线311之间可以相互平行，例如如图5b所示，任意一条第一纬线311可以与第一方向X平行，即横向设置。任意两条第一经线312之间相互平行，例如任意一条第一经线312可以与第二方向Y平行，即纵向设置。在此情况下，多条第一经线312和多条第一纬线311交叉是指，一条横向设置的第一纬线311会与多条纵向设置的第一经线312交叉。同理，一条纵向设置的第一经线312会与多条横向设置的第一纬线311交叉。
此外，将多条第二经线322和多条第二纬线321交叉形成第二布料层32。其中，相邻两条第二经线322之间的间距与第一间距H1相同，相邻两条第二纬线321之间的间距与第一间距H1相同。上述第二经线322在第一布料层31上的垂直投影，位于相邻两条第一经线312之间，第二纬线321在第一布料层31上的垂直投影，位于相邻两条第二纬线321之间。
同理，任意两条第二纬线321之间可以相互平行，例如如图5b所示，任意一条第二纬线321可以与第一方向X平行，即横向设置。任意两条第二经线322之间相互平行，例如任意一条第二经线322可以与第二方向Y平行，即纵向设置。在此情况下，多条第二经线322和多条第二纬线321交叉是指，一条横向设置的第二纬线321会与多条纵向设置的第二经线322交叉。同理，一条纵向设置的第二经线322会与多条横向设置的第二纬线321交叉。
此外，由上述可知，第一布料层31可以与如图5b所示的XOY平面平行。基于此，上述第二经线322在第一布料层31上的垂直投影是指，第二经线322沿垂直于XOY平面的Z方向在第一布料层31上形成的投影。同理，第二纬线321在第一布料层31上的垂直投影是指，第二纬线321沿垂直于XOY平面的Z方向在第一布料层31上形成的投影。以下“垂直投影”的方式同理可得，不再一一赘述。
在此基础上，第一纤维301沿第一方向X与位于下方的第一经线312和位于上方的第二经线322交叉。此外，第二纤维302沿第二方向Y与位于下方的第一纬线311和位于上方的第二纬线321交叉。这样一来，可以实现将第一纤维301和第二纤维302横纵交叉于第一布料层31和第二布料层32之间。
需要说明的是，图5b中第二间距H2是以第二布料层32中的第二经线322和该第二经线322在第一布料层31上的垂直投影(采用细点画线表示)之间的间距表示。以下附图中第二间距H2的表示方式相同，不再一一赘述。
在此情况下，第一纤维301和第二纤维302横纵交叉于第一布料层31和第二布料层32之间是指，第一纤维301和第二纤维302不仅横纵交叉，此外，第一纤维301和第二纤维302还与上述第一布料层31和第二布料层32交叉。
由上述可知，在形成上述第一布料层31的过程中，需要控制相邻两条第一经线312之间的间距、相邻两条第一纬线311之间的间距与第一间距H1相同。在本申请的一些实施例中，对相邻两条第一经线312之间的间距、相邻两条第一纬线311之间的间距进行控制的方法可以如图6a所示，可以在母板21的周边设置多个第一定位柱41，并将一个第一定位柱41设置于每相邻两条第一经线312之间，且与相邻两条第一经线312相接触。
第一定位柱41具有第一几何长度L1，L1＝H1。其中，第一定位柱41的第一几何长度L1的方向与相邻两条第一经线312分别垂直。这样一来，由于第一定位柱41设置于相邻两条第一经线312之间，且与相邻两条第一经线312相接触，因此通过设置第一定位柱41的第一几何长度L1，就可以达到控制邻两条第一经线312之间的间距，使其与第一间距H1相同的目的。
此外，在母板21的周边设置多个第二定位柱42，并将一个第二定位柱42设置于每相邻两条第一纬线311之间，且与相邻两条第一纬线311相接触。该第二定位柱42具有第二几何长度L2，L2＝H1。这样一来，通过设置第二定位柱42的第二几何长度L2，就可以达到控制邻两条第一纬线311之间的间距，使其与第一间距H1相同的目的。其中，第二定位柱42的第二几何长度L2的方向与相邻两条第一纬线311分别垂直。
需要说明的是，在控制相邻两条第一经线312之间的间距、相邻两条第一纬线311之间的间距的过程中，可以通过夹持部件(图中未示出)，例如机械手对每条第一经线312、第一纬线311的两端进行夹持，避免第一经线312、第一纬线311处于松弛的状态。在此情况下，还可以通过移动机械手，对第一布料层31和第二布料层32之间具有第二间距H2(如图5b所示)进行调节。例如，在本申请的一些实施例中，上述第二间距H2和焊接间距Hb之间可以满足：H2＝Hb/2，从而再后续步骤中将第一纤维301和第二纤维302拉伸后，能够使得伸缩层30上相邻两个micro LED芯片101之间的间距由原本的初始间距Ha扩大到焊接间距Hb。
上述是以第一定位柱41、第二定位柱42的截面(与母板21平行)为矩形为例进行的说明。在此情况下，如图6b所示，以第一定位柱41为例，该第一定位柱41可以为长方体。或者，在本申请的另一些实施例中，上述第一定位柱41、第二定位柱42的截面尺寸还可以为圆形。在此情况下，如图6c所示，以第一定位柱41为例，该第一定位柱41可以为圆柱体。
因此，如图6a所示，上述第一定位柱41的第一几何长度L1是指沿垂直于第一经线312的方向，例如第一方向X，第一定位柱41相对两边之间的距离。同理，第二定位柱42的第二几何长度L2是指沿垂直于第一纬线311的方向，例如第二方向Y，第二定位柱42相对两边之间的距离。
此外，上述是以采用第一定位柱41和第二定位柱42对第一布料层31中，相邻两条第一经线312之间的间距、相邻两条第一纬线311之间的间距进行控制的方法进行 的说明。对第二布料层32中相邻两条第二经线322之间的间距、相邻两条第二纬线321之间的间距进行控制的方法同上所述，此处不再赘述。
需要说明的是，上述均是以母板21中任意相邻两个micro LED芯片101之间的间距均为上述第一间距H1(如图7所示)为例进行的说明。在本申请的另一些实施例中，母板21中相邻两个micro LED芯片101之间的间距还可以不同。在此情况下，可以根据间距的需要对上述第一定位柱41的第一几何长度L1、第二定位柱42的第二几何长度L2进行设置，以满足不同的相邻两micro LED芯片101之间间距的要求。
S102、如图7所示，将伸缩层30与母板21中的micro LED芯片101粘贴。
在本申请的一些实施例中，伸缩层30与micro LED芯片101粘贴后，第一布料层31可以靠近micro LED芯片101，第二布料层32可以远离micro LED芯片101。或者，在本申请的另一些实施例中，可以将第一布料层31和第二布料层32的位置可以互换。以下均是以第一布料层31更靠近micro LED芯片101为例进行的说明。
此外，当需要将母板21中的micro LED芯片101全部进行转移时，伸缩层30中第一纤维301和第二纤维302的一个交叉点300与母板21中一个micro LED芯片101对位粘贴，使得伸缩层30中多个交叉点300与母板21中多个micro LED芯片101一一对位粘贴。
需要说明的是，一个交叉点300与母板21中一个micro LED芯片101对位粘贴是指，伸缩层30与micro LED芯片101粘贴后，一个交叉点300在母板21上的垂直投影与micro LED芯片101的至少一部分重叠。例如，一个交叉点300在母板21上的垂直投影可以与一个micro LED芯片101的中心重叠，或者，一个交叉点300在母板21上的垂直投影可以与一个micro LED芯片101的中心周边的部分重叠。又或者，一个交叉点300在母板21上的垂直投影可以与一个micro LED芯片101完全重叠。从而在执行S102时，可以使得一个交叉点300与母板21中一个micro LED芯片101所在位置准确粘贴。
需要说明的是，上述是以需要将母板21中的micro LED芯片101全部进行转移时对S102进行的举例说明，当只需要将母板21中的micro LED芯片101进行部分转移时，在执行S102的过程中，伸缩层30中第一纤维301和第二纤维302的一些交叉点300可以与母板21中的多个micro LED芯片101一一对位相粘贴，而伸缩层30中的另一些交叉点300无需粘贴micro LED芯片101。从而实现母板21中的micro LED芯片101的部分转移，以适应micro LED显示屏10对于不同分辨率的要求。以下为了方便说明，均是以将母板21中的micro LED芯片101全部进行转移为例进行的说明。在本申请的一些实施例中，为了对伸缩层30与母板21进行对位，如图8所示，可以在母板21中用于承载micro LED芯片101的衬底100上制作多个第一对位标51。上述多个第一对位标51可以位于衬底100的周边。例如，图8是以在衬底100周边的四个角位置分别设置一个第一对位标51为例进行的说明。其中，上述第一对位标51的材料可以为金属材料，通过光刻工艺(包括：掩膜、曝光、显影以及刻蚀等工艺)形成。
接下来，在执行上述S102之前，可以采用照相机，例如电荷耦合器件(charge coupled device，CCD)获取第一对位标51以及伸缩层30的位置。处理器(图中未示出)可以根据CCD的采集结果，利用上述机械手控制伸缩层30中边缘的一条第一经 线312或者一条第一纬线311的位置，使其能够与至少一个第一对位标51的位置重叠，从而达到将伸缩层30与母板21进行对位的目的。其中，图8中最左端的一条第一经线312与衬底100左侧上、下两个第一对位标51的位置均重叠。最右侧的一条第一经线312与衬底100右侧上、下两个第一对位标51的位置均重叠。
示例的，在执行S102的过程中，为了提高一个交叉点300与母板21中一个micro LED芯片101所在位置的粘贴精度，当上述micro LED芯片101的单边尺寸为10μm时，伸缩层30与母板21的对位精度可以不低于0.5μm。即伸缩层30与母板21的对位精度不低于micro LED芯片101的单边尺寸的5％。
以下对执行上述S102的过程中，如何将伸缩层30粘贴于母板21上的方法进行举例说明。
在本申请的一些实施例中，上述S102可以包括，如图9a所示，首先，至少在第一布料层31上，第一纤维301和第二纤维302的交叉点300处涂覆胶层60。然后，如图9b所示，将伸缩层30涂覆有胶层60的一侧表面粘贴于母板21上，并使得一个交叉点300在母板21上的垂直投影与母板21中一个micro LED芯片101重叠。
基于此，本申请实施例中，将一个交叉点300与母板21中一个micro LED芯片101对位粘贴可以有两种方式。第一种实施方式可以为，如图9b所示，将伸缩层30中，一个交叉点300，通过上述胶层60与上述母板21中的衬底100远离micro LED芯片101(micro LED芯片101位于衬底100下方采用虚线表示)的一侧表面A1相粘贴。这样一来，可以避免micro LED芯片101中第一电极110和第二电极120所在的一侧表面接触到胶层60，从而对micro LED芯片101的性能造成影响。
此时，micro LED芯片101位于衬底100的表面A2上，该表面A2与表面A1相对设置，且衬底100的表面A1朝向伸缩层30。并且，一个交叉点300在衬底100上的垂直投影，与一个micro LED芯片101在衬底100上的垂直投影重叠，从而可以确保一个交叉点300与母板21中一个micro LED芯片101对位粘贴。
第二种实施方式可以为，如图9c所示，将伸缩层30中，一个交叉点300，通过上述胶层60与micro LED芯片101(micro LED芯片101位于衬底100上方采用实线表示)远离衬底100的一侧表面相粘贴。此时，衬底100的表面A2朝向伸缩层30，第一纤维301和第二纤维302以及micro LED芯片101均位于衬底100的表面A2所在的一侧。一个交叉点300在衬底100上的垂直投影，仍然可以与一个micro LED芯片101在衬底100上的垂直投影重叠一个交叉点300。
或者，在本申请的另一些实施例中，上述S102可以包括，如图10a所示，首先在母板21上点胶形成多个胶层60。其中，一个胶层60在母板21上的垂直投影与该母板21中一个micro LED芯片101重叠，即一个胶层60在衬底100上的垂直投影，与一个micro LED芯片101在衬底100上的垂直投影重叠。例如，如图10a所示，可以在衬底100远离micro LED芯片101(micro LED芯片101位于衬底100下方采用虚线表示)的一侧表面A1，通过点胶工艺形成由多个胶层60构成的点胶阵列。此时，micro LED芯片101位于衬底100的表面A2上，衬底100的表面A1朝向胶层60。
接下来，如图9b所示，将伸缩层30中第一布料层31所在的一侧表面通过上述胶层60粘贴于母板21上，以使得一个交叉点300在母板21上的垂直投影与一个胶层 60重叠。由上述可知，一个胶层60在母板21上的垂直投影与该母板21中一个micro LED芯片101重叠，所以可以确保一个交叉点300通过一个胶层60与一个micro LED芯片101对位粘贴。或者，又例如，如图10b所示，可以在micro LED芯片101(micro LED芯片101位于衬底100上方采用实线表示)远离衬底100的一侧表面，通过点胶工艺形成胶层60。此时，衬底100的表面A2朝向胶层60。
接下来，如图9c所示，将伸缩层30中第一布料层31所在的一侧表面通过上述胶层60粘贴于母板21上，并使得一个交叉点300与母板21中一个micro LED芯片101对位相粘贴。此时，第一纤维301和第二纤维302以及micro LED芯片101均位于衬底100的表面A2所在的一侧。
在本申请的另一些实施例中，上述S102可以包括，如图11a所示，在母板21上涂覆胶体材料层61。例如，如图11a所示，可以在衬底100远离micro LED芯片101(micro LED芯片101位于衬底100下方采用虚线表示)的一侧表面A1，涂覆胶体材料层61。该胶体材料层61可以覆盖衬底100的表面A1，因此图11a中未将表面A1示出。此时，micro LED芯片101位于衬底100的表面A2上。然后，可以采用掩膜曝光工艺对胶体材料层61进行图案(pattern)化，使得母板21上形成多个如图11b所示的胶层60。其中，一个胶层60在母板21上的垂直投影与母板21中一个micro LED芯片101重叠。这样一来，母板21上多个胶层60可以在同一次掩膜曝光工艺中形成，因此可以提高制作工艺的效率。
接下来，如图11c所示，将伸缩层30中第一布料层31所在的一侧表面通过上述胶层60粘贴于母板21上，以使得一个交叉点300与母板21中一个micro LED芯片101对位粘贴。此时，一个交叉点300，通过上述胶层60与衬底100远离micro LED芯片101的一侧表面A1相粘贴。
或者，又例如，如图12a所示，可以在micro LED芯片101远离衬底100的一侧表面，涂覆胶体材料层61。该胶体材料层61可以覆盖micro LED芯片101以及衬底100。然后，可以采用掩膜曝光工艺对胶体材料层61进行图案化，使得母板21中每个micro LED芯片101所在位置形成如图12b所述的胶层60。
接下来，如图12c所示，将伸缩层30中第一布料层31所在的一侧表面通过上述胶层60粘贴于母板21上，并使得一个交叉点300与母板21的衬底100上一个micro LED芯片101对位粘贴。此时，第一纤维301和第二纤维302以及micro LED芯片101均位于衬底100的表面A2所在的一侧。一个交叉点300，通过上述胶层60与micro LED芯片101远离衬底100的一侧表面相粘贴。
需要说明的是，上述仅仅是对执行S102进行的举例说明，其余方式在此不再一一赘述。以下为了方便说明，均是以一个交叉点300，通过上述胶层60与衬底100远离micro LED芯片101的一侧表面A1相粘贴为例进行的说明。
本申请上述胶层60的材料不进行限定。例如，该胶层60可以为UV胶水。该UV胶水在特定的UV波段照射下可以发生交联反应，完成固化。其中，固化程度越高，胶层60的粘性越强。示例的，上述胶层60可以采用丙烯酸酯或者环氧丙烯酸酯中的至少一种与光引发剂混合而成。在此情况下，当采用波长为345nm、365nm、385nm或405nm的UV光对胶层60进行照射时，该胶层60可以发生交联反应实现固化。
基于此，还可以选择性的对胶层60特定的位置进行UV固化处理，使得特定位置的粘性较大，其余位置的粘性较小。例如，由上述可知，在执行S102的过程中，一个交叉点300与母板21中一个micro LED芯片101所在位置相粘贴。因此，可以对胶层60中与一个交叉点300对应的位置，进行UV固化，从而增强胶层60在该部分的粘性。此时，胶层60中其余部分的粘性较弱，从而有利于在后续工艺中将胶层60去除。
此外，上述均是以伸缩层30中第一布料层31所在的一侧表面与母板21中一个micro LED芯片101所在位置相粘贴为例进行的说明。在本申请的另一些实施例中，也可以将第二布料层32所在的一侧表面与母板21中一个micro LED芯片101所在位置相粘贴，该粘贴过程同上所述，此处不再赘述。
S103、分离多个micro LED芯片101，分离的多个micro LED芯片101分别与第一纤维301和第二纤维302相连接。
具体的，在申请一个实施例中，当上述母板21为晶圆时，在执行上述S103的过程中，如图13所示，可以采用激光切割工艺对母板21的衬底100进行切割，从而将多个多个micro LED芯片101分离。或者，在本申请的另一些实施例中，当上述母板21为用于承载micro LED芯片101的承载板时，可以在执行上述S103的过程中，将多个micro LED芯片101从承载板上脱离。
在执行S103之后，可以去除第一布料层31中位于相邻两个交叉点300之间的部分。
例如，在本申请的一些实施例中，上述S103可以具体包括，如图14a所示，先采用激光对第一经线312位于相邻两个交叉点300之间的部分，以及第一纬线311位于相邻两个第一纤维301和第二纤维302交叉点之间的部分进行切割。
示例的，可以采用激光对第一经线312位于相邻两个交叉点300之间的部分，以及第一纬线311位于相邻两个交叉点300之间的部分进行对焦，以使得该部分在激光作用下，能够被切断，而伸缩层30的其余部分不会被切断。
或者，第一布料层31的材料可以与第一纤维301和第二纤维302的材料不同。例如第一布料层31的材料可以吸收激光发出的能量，从而在该能量的作用下发生升华或者熔化，从而使得第一布料层31中第一经线312位于相邻两个交叉点300之间的部分，以及第一纬线311位于相邻两个交叉点300之间的部分的部分被切断。然而，第一纤维301和第二纤维302的材料能够透过上述激光，而避免吸收激光的能量，从而使得第一纤维301和第二纤维302在激光照射下不会被切断。
接下来，由于第二布料层32并未与胶层60相粘贴，所以可以直接将第二经线322和第二纬线321抽取，形成如图14b所示的结构，图14b中剩余第一纤维301、第二纤维302以及第一布料层31中的部分材料。此时上述第二布料层32可以完全去除。或者，可以在采用激光对第一布料层31进行切割的同时，也可以将第二布料层32中第二经线322位于相邻两个交叉点300之间的部分，以及第二纬线321位于相邻两个交叉点300之间的部分切断。这样一来，无需执行上述将第二经线322和第二纬线321抽取的步骤。
或者，在本申请的另一些实施例中，上述第一经线312和第一纬线311，以及第二经线322和第二纬线321的材料可以包括第一材料。第一纤维301和第二纤维302 的材料可以包括第二材料。该第一材料和第二材料不同。
在此情况下，上述S103可以具体包括，将粘贴有micro LED芯片101的伸缩层30放入用于溶解第一材料的第一溶剂中。这样一来，在该第一溶剂的作用下，可以将由第一材料构成的第一经线312和第一纬线311，以及第二经线322和第二纬线321的材料溶解，而由第二材料构成的第一纤维301和第二纤维302可以不溶于上述第一溶剂中。这样一来，可以形成如图15所示的结构，图15中剩余第一纤维301和第二纤维302。此时上述第一布料层31和第二布料层32可以完全或者近似完全去除。
以下对上述第一材料、第二材料以及上述第一溶剂的设置方式进行说明。
示例的，上述构成第一经线312和第一纬线311，以及第二经线322和第二纬线321的材料的第一材料可以为棉，构成第一纤维301、第二纤维302的第二材料可以为羊毛。此外，第一溶剂可以为浓度为75％、温度为24℃的硫酸。这样一来，棉可以溶解于第一溶剂中，而羊毛无法溶解于上述第一溶剂中，从而达到去除第一布料层31和第二布料层32，保留第一纤维301、第二纤维302的目的。
或者，又例如，上述构成第一经线312和第一纬线311，以及第二经线322和第二纬线321的材料的第一材料可以为醋酯纤维，构成第一纤维301、第二纤维302的第二材料可以为涤纶。此外，第一溶剂可以为温度为24℃的冰醋酸。这样一来，醋酯纤维可以溶解于第一溶剂中，而涤纶无法溶解于上述第一溶剂中，从而达到去除第一布料层31和第二布料层32，保留第一纤维301、第二纤维302的目的。
或者，在例如，构成第一经线312和第一纬线311，以及第二经线322和第二纬线321的材料的第一材料可以为棉纶，构成第一纤维301和第二纤维302的第二材料可以为腈纶。此外，第一溶剂可以为浓度为75％、温度为24℃的果酸。这样一来，棉纶可以溶解于第一溶剂中，而腈纶无法溶解于上述第一溶剂中，从而达到去除第一布料层31和第二布料层32，保留第一纤维301、第二纤维302的目的。
需要说明的是，上述仅仅是对第一材料、第二材料以及上述第一溶剂的设置方式的举例说明，其他示例在此不再一一赘述。
或者，在本申请的另一些实施例中，相对于第一纤维301和第二纤维302而言，第一经线312和第一纬线311，以及第二经线322和第二纬线321，可以在受拉状态下容易发生断裂。这样一来，在拉伸伸缩层30的过程中，第一经线312和第一纬线311，以及第二经线322和第二纬线321会发生断裂，从而达到去除第一布料层31中位于相邻两个交叉点300之间的部分的目的。
在此基础上，在本申请的一些实施例中，上述芯片转移的方法还可以包括，如图16所示，将第一纤维301和第二纤维302拉伸，控制第一纤维301和第二纤维302上相邻两个micro LED芯片101之间具有第三间距H3。其中，基板20上相邻两个预设位置70之间具有焊接间距Hb，H3＝Hb。
由上述可知，在第一布料层31和第二布料层32去除之前，第一布料层31和第二布料层32之间具有第二间距H2(如图13所示)，该第二间距H2和焊接间距Hb之间可以满足：H2＝Hb/2。因此，第一纤维301和第二纤维302拉伸之前，第一纤维301和第二纤维302为波浪形，波浪拱起的高度即为上述第二间距H2。
基于此，在将第一纤维301和第二纤维302拉伸后，第一纤维301和第二纤维302 在拉伸过程中，第一纤维301和第二纤维302由波浪状变成直线状。当第一纤维301和第二纤维302的弹性形变量较小时，第一纤维301和第二纤维302上相邻两个micro LED芯片101之间的第三间距H3可以近似与2倍的第二间距H2相同。这样一来，可以在将第一纤维301和第二纤维302拉伸后，使得第一纤维301和第二纤维302上相邻两个micro LED芯片101之间的第三间距H3，与基板20上相邻两个预设位置70之间的焊接间距Hb相同或近似相同。
需要说明的是，本申请以下实施例为了方便说明，是以第一纤维301和第二纤维302拉伸后，该第一纤维301和第二纤维302上相邻两个micro LED芯片101之间沿横向(第一方向X)、纵向(第二方向Y)的距离均为上述第三间距H3为例，且基板20上沿横向或者纵向，任意相邻预设位置之间的间距均为上述焊接间距Hb为例进行的说明。
此外，上述预设位置70可以不是实际存在于基板20上的，且可以通过人眼识别的标记。上述预设位置70可以是芯片焊接设备内部，根据需要存储的用于对micro LED芯片101进行焊接时预设的位置。该位置可以通过CCD采集基板20上的对位标获得。
在本申请的一些实施例中，执行将第一纤维301和第二纤维302拉伸具体可以包括，首先通过上述机械手将上述第一纤维301和第二纤维302进行拉伸，以扩大相邻两个micro LED芯片101之间的间距。然后，将多个第一定位柱41如图17a所示翻转90°。由上述可知，原本第一定位柱41设置于相邻两条第一经线312之间，而第一经线312和拉伸后的第二纤维302均沿第二方向Y设置。因此当第一经线312去除后，上述翻转90°的每个第一定位柱41如图17b所示，可以设置于每相邻两条第二纤维302之间，且与相邻两条第二纤维302相接触。第一定位柱41具有第一几何宽度B1，B1＝H3。
这样一来，由于第一定位柱41设置于相邻两条第二纤维302之间，且与相邻两条第二纤维302相接触，因此通过设置第一定位柱41的第一几何宽度B1，就可以达到控制邻两条第二纤维302之间的间距，使其与第三间距H3相同的目的。
接下来，同理将上述多个第二定位柱42翻转90°。由上述可知，如图6a所示，原本第二定位柱42设置于相邻两条第一纬线311之间，而第一纬线311和拉伸后的第一纤维301均沿第一方向X设置。因此当第一纬线311去除后，上述翻转90°的每个第二定位柱42如图18所示，可以设置于相邻两条第一纤维301之间，且与相邻两条第一纤维301相接触。第二定位柱42具有第二几何宽度B2，B2＝H3。
其中，上述第一定位柱41的第一几何宽度B1是指沿垂直于第二纤维302的方向，例如第一方向X，第一定位柱41相对两边之间的距离。同理，第二定位柱42的第二几何宽度B2是指沿垂直于第一纤维301的方向，例如第二方向Y，第二定位柱42相对两边之间的距离。
需要说明的是，上述是以焊接于基板20上的，任意相邻两个micro LED芯片101之间的间距均与上述第三间距H3(如图19所示)相同为例进行的说明。在本申请的另一些实施例中，焊接于基板20上的，相邻两个micro LED芯片101之间的间距还可以不同。在此情况下，可以根据间距的需要对上述第一定位柱41的第一几何宽度B1、第二定位柱42的第二几何宽度B2进行设置，以满足不同的相邻两个micro LED芯片 101之间间距的要求。
由上述可知，通过第一定位柱41，即可以对相邻两条第一经线312之间的第一间距H1进行控制，还可以对相邻两条第二纤维302之间的第三间距H3进行控制。通过第二定位柱42即可以对相邻两条第一纬线311之间的第一间距H1进行控制，还可以对相邻两条第一纤维301之间的第三间距H3进行控制。这样一来，无需在对第一纤维301和第二纤维302定位时单独增加定位柱，从而能够减少定位柱的数量，简化定位过程。
S104、如图19所示，将与伸缩层30粘贴的多个micro LED芯片101分别设置于基板20的多个预设位置70(如图16所示)。
为了在执行上述S104的过程中，能够确保每个micro LED芯片101与基板20的一个预设位置一一对应，在执行上述S104之前，可以对micro LED芯片101与基板20的预设位置70(如图16所示)进行对位。具体的，如图20所示，在基板20上，可以制作至少一个第二对位标52。第二对位标52的制作方法与第一对位标51的制作方法同理，此处不再赘述。
接下来，可以采用CCD获取第二对位标52以及第一纤维301和第二纤维302上micro LED芯片101的位置。处理器(图中未示出)可以根据CCD的采集结果，利用上述机械手控制第一纤维301和第二纤维302上的一个micro LED芯片101的位置与一个第二对位标52的位置重叠，从而达到对micro LED芯片101与基板20的预设位置70进行对位的目的。
由上述可知，在本申请的一些实施例中，如图11c所示，第一纤维301和第二纤维302可以粘贴于衬底100的表面A1，micro LED芯片101设置于衬底100的表面A2，表面A1和表面A2相对设置。这样一来，执行上述S104后，如图21所示，可以采用倒装工艺，将一个micro LED芯片101焊接于基板20上的一个预设位置70(如图16所示)处。在此情况下，该micro LED芯片101的第一电极110和第二电极120靠近基板20设置，从而可以直接焊接于该基板20上，并与该基板20上的像素驱动电路201(如图1d所示)电连接。这样一来，可以提高基板20上的电路向micro LED芯片101的第一电极110和第二电极120提供电信号的传输效率。
需要说明的是，根据基板20的类型不同，采用上述倒装工艺对micro LED芯片101进行封装的技术也不同。例如，当基板20为PCB时，采用上述倒装工艺对micro LED芯片101进行封装的技术可以称为板上芯片封装技术(chip on board，COB)。或者，当基板20中，用于承载上述像素驱动电路201的基板为玻璃基板时，采用上述倒装工艺micro LED芯片101进行封装的技术可以称为玻璃上芯片封装技术(chip on glass，COG)。又或者，当基板20中，用于承载上述像素驱动电路201的基板为塑料基板时，采用上述倒装工艺micro LED芯片101进行封装的技术可以称为塑料基板上芯片封装技术(chip on plastic，COP)。
或者，在本申请的一些实施例中，如图12c所示，第一纤维301和第二纤维302以及micro LED芯片101均位于衬底100的表面A2所在的一侧。在此情况下，micro LED芯片101的第一电极110和第二电极120远离基板20设置，可以通过在micro LED芯片101上制作贯穿外延层140的过孔(图中未示出)，使得第一电极110以及第二 电极120通过不同的过孔焊接于该基板20上。
S105、去除第一纤维301和第二纤维302。
具体的，首先可以采用激光剥离(laser lift off，LLO)工艺，对胶层60进行照射，以释放胶层60的粘性，使得胶层60与micro LED芯片101分离。在此情况下，如图22所示，第一纤维301和第二纤维302仅仅放置于micro LED芯片101上方，并未与micro LED芯片101相粘贴。接下来，将第一纤维301和第二纤维302抽去，达到去除第一纤维301和第二纤维302的目的。
然后，可以对如图23所示的焊接有micro LED芯片101的基板20(即micro LED面板)进行清洗，从而完成了micro LED芯片101的巨量转移过程。
综上所述，本申请实施例提供的一种芯片转移方法中，可以将拉伸之前的伸缩层30与母板21中的每个micro LED芯片101粘贴。如图7所示，第一布料层31和第二布料层32之间具有第二间距H2。此时，第二布料层32中的第二经线322、第二纬线321均与第一布料层31之间具有上述第二间距H2。由于第一纤维301与第二经线322交叉，第二纤维302与第二纬线321交叉，因此能够使得拉伸之前伸缩层30中的第一纤维301和第二纤维302呈波浪状。
此外，该伸缩层30中，第一布料层31中十字交叉的第一纬线311和第一经线312，以及第二布料层32中十字交叉的第二纬线321和第二经线322，能够对交叉于第一布料层31和第二布料层32上的，第一纤维301和第二纤维302的相邻两个交叉点之间的第一间距H1进行控制。从而使得第一间距H1能够与母板21中相邻两个micro LED芯片101之间的初始间距Ha相同。在此情况下，当将未拉伸之前的伸缩层30与母板21中的每个micro LED芯片101粘贴后，一个交叉点300与母板21中一个micro LED芯片101所在位置相粘贴。
在此基础上，当未拉伸之前的伸缩层30与母板21粘贴后，可以对母板21的衬底进行切割，并去除上述第一布料层31和第二布料层32。接下来，如图16所示，对伸缩层30中的第一纤维301和第二纤维302进行拉伸，增大第一纤维301和第二纤维302上相邻两个micro LED芯片101之间的间距，使得相邻两个micro LED芯片101之间的间距由原来的第一间距H1，变化至第三间距H3。该第三间距H3与基板20上相邻两个预设位置70之间的焊接间距Hb相同。基于此，可以将位于拉伸后的第一纤维301和第二纤维302上的micro LED芯片101一一焊接于基板20上的各个预设位置70处上。然后去除上述第一纤维301和第二纤维302，并对形成的micro LED芯片101进行清洗，以完成micro LED芯片101的巨量转移。
由上述可知，本申请提供的芯片转移方式中，只需要将未拉伸的伸缩层30与母板21中的各个micro LED芯片101相粘贴。然后，对该伸缩层30进行拉伸，以扩大该伸缩层30上相邻两个micro LED芯片101的间距，使其与基板20上相邻的预设位置70之间的间距相匹配。这样一来，可以将同一个母板21中的大部分，甚至所有的micro LED芯片101一次性的全部转移至基板20上。因此在芯片巨量转移的过程中，无需转移头来回往复于作为供体基板的母板21，与基板20之间，达到提高芯片巨量转移效率的目的。
此外，相关技术提供的方案中，可以采用一整张材质相同且质地均匀的薄膜，在 薄膜未拉伸之前将母板中的micro LED芯片粘贴，然后对薄膜进行拉伸后将micro LED芯片绑定于电路板上。该方案中，由于薄膜的形变量由构成该薄膜的材料决定，而该薄膜采用同一材料构成，因此在拉伸前后薄膜各处的形变量基本相当。所以薄膜上任意位置的micro LED芯片在薄膜拉伸前后的位移量基本相同。然而，本申请提供的芯片转移方法，可以根据需要对第一纤维301和第二纤维302中，任意相邻两个交叉点之间的第一间距H1，以及第一纤维301和第二纤维302未拉伸前的拱起高度(即第一布料层31和第二布料层32之间的第二间距H2)进行控制，从而能够满足母板21中部分micro LED芯片101初始位置的不同需求，以及在基板20上部分micro LED芯片101绑定位置的不同需求，应用范围更加广泛。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种芯片转移方法，用于将芯片从母板转移至基板，其特征在于，所述方法包括：
    提供伸缩层；所述伸缩层包括多条第一纤维和多条第二纤维，以及层叠设置的第一布料层和第二布料层；所述第一纤维和所述第二纤维交叉于所述第一布料层和所述第二布料层之间，所述第一纤维与所述第二纤维之间具有多个交叉点，其中，相邻两个所述交叉点之间具有第一间距H1，所述第一布料层和所述第二布料层之间具有第二间距H2；
    将所述伸缩层与所述芯片粘贴，所述第一布料层靠近所述芯片，所述第二布料层远离所述芯片；
    分离多个所述芯片，分离的多个所述芯片分别与所述第一纤维和所述第二纤维相连接；
    将与所述伸缩层粘贴的多个所述芯片分别设置于所述基板的多个预设位置；
    去除所述第一纤维和所述第二纤维。
  2. 根据权利要求1所述的芯片转移方法，其特征在于，所述提供伸缩层包括：
    将多条第一经线和多条第一纬线交叉形成所述第一布料层，其中，相邻两条所述第一经线之间的间距与所述第一间距H1相同，相邻两条所述第一纬线之间的间距与所述第一间距H1相同；
    将多条第二经线和多条第二纬线交叉形成所述第二布料层，其中，相邻两条所述第二经线之间的间距与所述第一间距H1相同，相邻两条所述第二纬线之间的间距与所述第一间距H1相同，所述第二经线在所述第一布料层上的垂直投影位于相邻两条所述第一经线之间，所述第二纬线在所述第一布料层上的垂直投影位于相邻两条所述第二纬线之间。
  3. 根据权利要求2所述的芯片转移方法，其特征在于，
    所述第一纤维与所述第一经线和所述第二经线交叉；
    所述第二纤维与所述第一纬线和所述第二纬线交叉。
  4. 根据权利要求2或3所述的芯片转移方法，其特征在于，所述将所述伸缩层与所述芯片粘贴包括：将一个所述交叉点与所述母板中的一个所述芯片对位粘贴。
  5. 根据权利要求4所述的芯片转移方法，其特征在于，所述母板中相邻两个所述芯片之间具有初始间距Ha，Ha＝H1。
  6. 根据权利要求4或5所述的芯片转移方法，其特征在于，所述将一个所述交叉点与所述母板中的一个所述芯片对位粘贴包括：
    在所述第一布料层上，所述交叉点处涂覆胶层；
    将所述伸缩层涂覆有胶层的一侧表面粘贴于所述母板上，使得一个所述交叉点在所述母板上的垂直投影与所述母板中的一个芯片重叠。
  7. 根据权利要求4或5所述的芯片转移方法，其特征在于，所述将一个所述交叉点与所述母板中的一个所述芯片对位粘贴包括：
    在所述母板上点胶形成多个胶层，一个所述胶层在所述母板上的垂直投影与所述母板中一个芯片重叠；
    将所述第一布料层所在的一侧表面通过多个所述胶层粘贴于所述母板上，使得一个所述交叉点在所述母板上的垂直投影与一个所述胶层重叠。
  8. 根据权利要求4或5所述的芯片转移方法，其特征在于，所述将一个所述交叉点与所述母板中的一个所述芯片对位粘贴包括：
    在所述母板上涂覆胶体材料层，并对所述胶体材料层进行图案化，使得所述母板上形成多个胶层，一个所述胶层在所述母板上的垂直投影与所述母板中一个芯片重叠；
    将所述第一布料层所在的一侧表面通过所述胶层粘贴于所述母板上，使得一个所述交叉点在所述母板上的垂直投影与一个所述胶层重叠。
  9. 根据权利要求4-8任一项所述的芯片转移方法，其特征在于，所述母板包括用于承载所述芯片的衬底；所述将所述伸缩层与所述芯片粘贴包括：将所述伸缩层粘贴于所述衬底远离所述芯片的一侧表面上。
  10. 根据权利要求9所述的芯片转移方法，其特征在于，所述芯片包括第一电极和第二电极；所述将所述伸缩层上的多个芯片分别设置于所述基板的多个预设位置包括：采用倒装工艺，在所述预设位置，将一个所述芯片的第一电极和第二电极靠近所述基板，并焊接于所述基板上。
  11. 根据权利要求2-10任一项所述的芯片转移方法，其特征在于，所述分离多个所述芯片之后，将所述伸缩层上的多个芯片分别设置于所述基板的多个预设位置之前，所述方法还包括：
    将所述第一纤维和所述第二纤维拉伸，使所述第一纤维和所述第二纤维上相邻两个芯片之间具有第三间距H3；其中，所述基板上相邻两个预设位置之间具有焊接间距Hb，H3＝Hb。
  12. 根据权利要求2-11任一项所述的芯片转移方法，其特征在于，所述相邻两条所述第一经线之间的间距与所述第一间距H1相同，相邻两条所述第一纬线之间的间距与所述第一间距H1相同包括：
    在所述母板的周边设置多个第一定位柱；将一个所述第一定位柱设置于每相邻两条所述第一经线之间，且与相邻两条所述第一经线相接触；所述第一定位柱具有第一几何长度L1；L1＝H1；
    在所述母板的周边设置多个第二定位柱；将一个所述第二定位柱设置于每相邻两条所述第一纬线之间，且与相邻两条所述第一纬线相接触；所述第二定位柱具有第二几何长度L2；L2＝H1；
    其中，所述第一定位柱的第一几何长度L1的方向与相邻两条所述第一经线分别垂直；所述第二定位柱的第二几何长度L2的方向与相邻两条所述第一纬线分别垂直。
  13. 根据权利要求12所述的芯片转移方法，其特征在于，所述将所述第一纤维和所述第二纤维拉伸，控制所述第一纤维和所述第二纤维上相邻两个芯片之间具有第三间距H3包括：
    对所述第一纤维和所述第二纤维进行拉伸；
    将多个所述第一定位柱翻转90°，并将一个所述第一定位柱设置于每相邻两条所述第二纤维之间，且与相邻两条所述第二纤维相接触；所述第一定位柱具有第一几何宽度B1；B1＝H3；
    将多个所述第二定位柱翻转90°，并将一个所述第二定位柱设置于每相邻两条所述第一纤维之间，且与相邻两条所述第一纤维相接触；所述第二定位柱具有第二几何宽度B2；B2＝H3；
    其中，所述第一定位柱的第一几何宽度B1的方向与相邻两条所述第二纤维分别垂直；所述第二定位柱的第二几何宽度B2的方向与相邻两条所述第一纤维分别垂直。
  14. 根据权利要求11所述的芯片转移方法，其特征在于，所述第二间距H2和所述焊接间距Hb之间满足：H2＝Hb/2。
  15. 根据权利要求2或3所述的芯片转移方法，其特征在于，所述母板包括用于承载所述芯片的衬底，所述衬底上具有多个第一对位标；
    所述将所述伸缩层与所述芯片粘贴之前，所述方法还包括：
    将所述伸缩层中的一条所述第一经线或者一条所述第一纬线与至少一个所述第一对位标重叠。
  16. 根据权利要求2或3所述的芯片转移方法，其特征在于，所述基板上具有至少一个第二对位标；
    所述将所述伸缩层上的多个芯片分别设置于所述基板的多个预设位置之前，所述方法还包括：控制所述第一纤维和所述第二纤维上的一个所述芯片与一个所述第二对位标重叠。
  17. 根据权利要求11所述的芯片转移方法，其特征在于，所述分离多个所述芯片之后，将所述第一纤维和所述第二纤维拉伸之前，所述方法还包括：去除所述第一布料层中，位于相邻两个所述交叉点之间的部分。
  18. 根据权利要求17所述的芯片转移方法，其特征在于，所述第一经线和所述第一纬线，以及所述第二经线和所述第二纬线的材料包括第一材料；所述第一纤维和所述第二纤维的材料包括第二材料；所述第一材料和所述第二材料不同；
    所述去除所述第一布料层中，位于相邻两个所述交叉点之间的部分包括：将粘贴有所述芯片的伸缩层放入用于溶解所述第一材料的第一溶剂中。
  19. 根据权利要求17所述的芯片转移方法，其特征在于，
    所述去除所述第一布料层中，位于相邻两个所述交叉点之间的部分包括：
    采用激光对所述第一经线中，位于相邻两个所述交叉点之间的部分，以及所述第一纬线中，位于相邻两个所述交叉点之间的部分进行切割。
  20. 根据权利要求19所述的芯片转移方法，其特征在于，所述分离多个所述芯片之后，将所述第一纤维和所述第二纤维拉伸之前，所述方法还包括：去除所述第二经线和所述第二纬线。
  21. 根据权利要求1所述的芯片转移方法，其特征在于，所述分离多个所述芯片包括对所述母板进行切割，以将多个所述芯片分离。
  22. 根据权利要求6-8任一项所述的芯片转移方法，其特征在于，所述去除所述第一纤维和所述第二纤维包括：采用激光剥离工艺，将所述胶层与所述芯片分离，并抽去所述第一纤维和所述第二纤维。
  23. 一种电子设备，其特征在于，包括显示屏，所述显示屏采用如权利要求1-22任一项所述的芯片转移方法制备。
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