WO2022042016A1 - 存储器 - Google Patents

存储器 Download PDF

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Publication number
WO2022042016A1
WO2022042016A1 PCT/CN2021/103706 CN2021103706W WO2022042016A1 WO 2022042016 A1 WO2022042016 A1 WO 2022042016A1 CN 2021103706 W CN2021103706 W CN 2021103706W WO 2022042016 A1 WO2022042016 A1 WO 2022042016A1
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WO
WIPO (PCT)
Prior art keywords
command
memory
clock
port
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/103706
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English (en)
French (fr)
Inventor
寗树梁
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to EP21859858.9A priority Critical patent/EP4030261A4/en
Priority to US17/409,915 priority patent/US11837322B2/en
Publication of WO2022042016A1 publication Critical patent/WO2022042016A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular, to a memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line
  • the data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • DRAM is applied in more and more fields, such as DRAM is more and more used in various fields, users have higher and higher requirements for DRAM performance indicators, and will have different requirements for DRAM due to different application fields.
  • the technical problem solved by the embodiments of the present application is to provide a memory that solves the problems of high power consumption and high cost of the memory.
  • an embodiment of the present application provides a memory, a memory including: a control chip; It is configured that the same clock signal is used, and a plurality of the memory chips respectively perform information exchange with the control chip under different clock states of the clock signal.
  • the plurality of memory chips include: a first memory chip and a second memory chip; the first memory chip is configured to perform information interaction with the control chip at a rising edge of the clock signal; the first memory chip The two memory chips are configured to exchange information with the control chip at the falling edge of the clock signal.
  • the clock signal includes a command clock and a data clock
  • the plurality of storage chips perform information interaction with the control chip under different clock states of the clock signal, including: the first storage chip
  • the second memory chip interacts with the control chip at the rising edge of the command clock and/or the data clock; the second memory chip communicates with the control chip at the falling edge of the command clock and/or the data clock information exchange.
  • the clock state includes a first preset edge of the command clock and a second preset edge of the data clock; the first preset edge is a first rising edge or a first falling edge, the first preset edge The two preset edges are the second rising edge or the second falling edge.
  • each of the memory chips includes at least one channel, and the channel includes: a plurality of memory blocks, each of the memory blocks includes a plurality of memory cells, and the plurality of the memory blocks are configured to alternately perform read and write operations;
  • a command port the command port is configured to receive a command signal at a corresponding clock edge of the command clock, and the command signal is used to control read and write operations of the memory block;
  • a data port the data port is configured to: A data signal to be written into the memory block is received or a data signal is sent at a corresponding clock edge of the data clock; wherein, the corresponding clock edge includes the rising edge or the falling edge, and the command port includes a row address port and column address port, the row address port is used to receive the row address signal of the location of the target memory unit, the column address port is used to receive the column address signal of the location of the target memory unit, the target memory unit is the The selected storage unit among the plurality of storage units.
  • command clock and the data clock are the same clock signal.
  • the plurality of memory chips sharing channels and the control chip are electrically connected, including: the two memory chips sharing channels are electrically connected to the control chip; each of the memory chips uses the same clock
  • the command port of each of the memory chips uses different clock edges to receive or send signals
  • the data ports of each of the memory chips use different clock edges to receive or send signals.
  • the command signal includes an activation command and a read command corresponding to each activation command; the channel is further configured to, after the command port receives the activation command for one of the memory blocks, the The command port receives the read command corresponding to the activation command.
  • the channel is further configured such that the data port transmits the data signal after the command port receives the read command.
  • the command signal includes an activation command and a plurality of read commands corresponding to each activation command; the channel is further configured to, after the command port receives the activation command for one of the memory blocks, The command port receives one of the read commands corresponding to the active command on a plurality of corresponding clock edges, so that the command port receives a plurality of the read commands corresponding to the active command on a plurality of consecutive corresponding clock edges Order.
  • the channel is further configured such that the data port transmits a plurality of the data signals respectively on a plurality of consecutive corresponding clock edges, and the number of the data signals is the same as the number of the received read commands .
  • the command signal includes an activation command and a read command corresponding to the activation command; the channel is further configured such that after the command port alternately receives activation commands for different memory blocks, the command port alternately The read command corresponding to the activate command is received.
  • the channel is further configured such that after the command port receives the read command, the data port alternately transmits the data signals corresponding to different memory blocks.
  • the command signal includes an active command and a plurality of read commands corresponding to each of the active commands; the channel is further configured such that the command port alternately receives the active commands for different memory blocks, and all The command port alternately receives a plurality of the read commands corresponding to each of the active commands.
  • the activation command includes the row address signal
  • the read command includes the column address signal
  • the channel is further configured such that: the activation command and the read command pass through the command port received on different ports.
  • the channel is further configured: for any of the storage blocks, the time difference between receiving the activation command and receiving the read command corresponding to the activation command is greater than or equal to tRCD, where tRCD is the storage block The minimum preparation time required for a read operation after the activation command has been received.
  • the memory chip includes a plurality of the channels, and the memory chip further includes a common circuit shared by the channels.
  • the memory chip further includes: a test port, and in the test mode, a plurality of the channels share the same test port for testing.
  • the common circuit includes a test control circuit, and the test control circuit is used for test control of a plurality of the channels.
  • a plurality of the memory chips are sequentially stacked on the control chip, and the channel includes a through-silicon via structure.
  • the embodiments of the present application provide a memory with superior structure and performance, wherein a plurality of memory chips share a channel and are electrically connected to a control chip, the plurality of memory chips are configured to use the same clock signal, and the plurality of memory chips are in different clock states respectively information exchange with the control chip. Since multiple memory chips share a channel and are electrically connected to the control chip, there is no need to set a channel for each memory chip to be electrically connected to the control chip, which is beneficial to reduce the number of channels required by the memory, thereby reducing the cost and power consumption of the memory .
  • FIG. 1 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • FIG. 2 is a timing diagram of operating signals corresponding to two memory chips sharing a channel in a memory provided by an embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of a memory provided by another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a memory chip in FIG. 3;
  • Fig. 5 is a kind of working sequence diagram of the first memory chip and the second memory chip in Fig. 3;
  • FIG. 6 is another operation timing diagram of the first memory chip and the second memory chip in FIG. 3 .
  • the present application provides a memory, a plurality of memory chips, the plurality of memory chips are electrically connected to a control chip through a shared channel, the plurality of memory chips are configured to use the same clock signal, and the plurality of memory chips are respectively Information exchange with the control chip is performed under different clock states of the clock signal. Since multiple memory chips share channels, the number of channels required by the memory can be saved without affecting the quality of the information interaction between the multiple memory chips and the control chip, thereby saving the area of the memory, reducing the cost of the memory, and reducing the size of the memory. power consumption.
  • FIG. 1 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • the memory includes: a control chip 114; a plurality of memory chips 100, the plurality of memory chips 100 share a channel 01 and are electrically connected to the control chip 114, and the plurality of memory chips 100 are configured to use the same clock signal, and the plurality of memory chips 100 respectively perform information exchange with the control chip 114 under different clock states of the clock signal.
  • the memory can transmit data in all different clock states of the clock signal, that is, the memory can transmit data on both the rising edge and the falling edge of the clock signal.
  • the clock signal in this embodiment may be one clock or multiple clocks, which is not limited in this embodiment.
  • the memory may be a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • a plurality of memory chips 100 can be stacked on the control chip 114 in sequence, which is beneficial to improve the storage density and reduce the distance between the memory chips 100 and the control chip 114 ; alternatively, a plurality of memory chips 100 can also be placed on the control chip 114 Arranged side by side, it is beneficial to reduce the longitudinal thickness of the memory.
  • a plurality of memory chips 100 are stacked on the control chip 114 in sequence, and the channel 01 includes a through silicon via (TSV, Through Silicon Via).
  • the plurality of memory chips 100 include: a first memory chip 110 and a second memory chip 120; the first memory chip 110 is configured to exchange information with the control chip 114 at the rising edge of the clock signal; the second memory chip 110 The chip 120 is configured to exchange information with the control chip 114 on the falling edge of the clock signal.
  • the working mode of the first memory chip 110 is to transmit data on the rising edge of the clock signal
  • the working mode of the second memory chip 120 is to transmit data on the falling edge of the clock signal
  • the overall macro operating mode of the first memory chip 110 and the second memory chip 120 is: data is transmitted on both the rising edge and the falling edge of the clock signal. Therefore, it is sufficient for a single memory chip 100 to transmit data on either the rising edge or the falling edge of the clock signal, but for the memory as a whole, the effect of transmitting data on both the rising and falling edges of the clock signal can be achieved.
  • FIG. 1 Two different channels 01 are illustrated in FIG. 1 , and two memory chips 100 share one of the channels 01 , and the other two memory chips 100 share the other channel 01 . Specifically, as shown in FIG. 1 , two adjacent memory chips 100 share the same channel 01 , or two spaced memory chips 100 share the same channel 01 . It can be understood that the memory may include any number of channels 01, and the two memory chips 100 share the same channel 01.
  • the clock signal includes a command clock and a data clock
  • the plurality of memory chips 100 respectively perform information exchange with the control chip 114 under different clock states of the clock signal, including: the first memory chip 110 is in the command clock and/or the data clock.
  • the rising edge exchanges information with the control chip 114 ; the second memory chip 120 exchanges information with the control chip 114 at the falling edge of the command clock and/or the data clock.
  • the clock state includes the first preset edge of the command clock and the second preset edge of the data clock; the first preset edge is the first rising edge or the first falling edge, and the second preset edge is the second rising edge or the second falling edge.
  • Each memory chip 100 exchanges information with the control chip 114 on the first preset edge of the command clock, and each memory chip 100 exchanges information with the control chip 114 on the second preset edge of the data clock. More specifically, the memory chip 100 is configured to receive a command signal on the first preset edge of the command clock, and the command signal is used to control the read and write operations of the memory chip 100; the memory chip 100 is further configured to receive a command signal on the first preset edge of the data clock.
  • the second preset edge receives a data signal to be written into the memory chip 100 or sends a data signal.
  • the first memory chip 110 is configured to receive the command signal on the first rising edge of the command clock, and receive the data signal to be written or send the data signal on the second rising edge of the data clock;
  • the second memory chip 120 It is configured to receive the command signal on the first falling edge of the clock signal, receive the data signal to be written or send the data signal on the second falling edge of the data clock.
  • the command clock and the data clock are the same clock signal, and the corresponding first preset edge and the second preset edge are the same preset edge.
  • FIG. 2 is a timing diagram of operating signals corresponding to two memory chips sharing a channel in the memory provided by this embodiment, and the command clock and the data clock are the same clock signal, CK is the clock signal, and DATA1 is the first memory chip 110 transmits data , DATA2 is a timing diagram of data transmission by the second memory chip 120, and DATA is a timing diagram of combining DATA1 and DATA2.
  • the first memory chip 110 receives the activation command signal; at the mth rising edge of the clock signal, the first storage chip 110 receives the read command signal; at the nth rising edge of the clock signal, The first memory chip 110 transmits data.
  • the second memory chip 120 On the first falling edge of the clock signal, the second memory chip 120 receives the activation command signal; on the mth falling edge of the clock signal, the second memory chip 120 receives the read command signal; on the nth falling edge of the clock signal, The second memory chip 120 transmits data. In this way, the first memory chip 110 transmits data at different rising edges of the clock signal, and the second memory chip 120 transmits data at different falling edges of the clock signal, until the data transmission is completed.
  • the above description takes the memory read operation as an example for description.
  • the first memory chip 110 and the second memory chip 120 also transmit data alternately.
  • the number of channels 01 in the memory is reduced without affecting the bandwidth of the information interaction between the control chip 114 and the multiple memory chips 100, thereby reducing the memory capacity. manufacturing cost and power consumption.
  • Another embodiment of the present application further provides a memory, which is substantially the same as the foregoing memory, and the main differences include a more detailed description of each memory chip.
  • the memory provided in this embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those of the foregoing embodiments, reference may be made to the descriptions of the foregoing embodiments, which will not be repeated below.
  • FIG. 3 is a schematic structural diagram of a memory provided by another embodiment of the present application
  • FIG. 4 is a structural schematic diagram of a memory chip in FIG. 3 .
  • the memory includes: a control chip 214; a plurality of memory chips 200, the plurality of memory chips 200 share the channel 02 and are electrically connected to the control chip 214, and the plurality of memory chips 200 are configured to use The same clock signal, and a plurality of memory chips 200 respectively perform information exchange with the control chip 214 under different clock states of the clock signal; Including a command clock and a data clock, the first memory chip 210 exchanges information with the control chip 214 on the rising edge of the command clock and/or the data clock, and the second memory chip 220 communicates with the control chip 214 on the falling edge of the command clock and/or the data clock.
  • the chip 214 performs information exchange.
  • Each memory chip 200 includes at least one channel 20, and the channel 20 includes: a plurality of memory blocks 201, each memory block 201 includes a plurality of memory units, and the plurality of memory blocks 201 are configured to alternately perform read and write operations; command ports 202, The command port 202 is configured to receive a command signal at the corresponding clock edge of the command clock, and the command signal is used to control the read and write operations of the memory block 201; the data port 203, the data port 203 is configured to receive the pending signal at the corresponding clock edge of the data clock.
  • the corresponding clock edge refers to the rising edge or falling edge of the command clock corresponding to the information exchange of the memory chip 200 , and the rising edge or falling edge of the data clock corresponding to the information exchange of the memory chip 200 .
  • command port referred to in this embodiment includes a port for transmitting command signals and address signals, but is not limited thereto.
  • each channel 20 includes four memory blocks 201 as an example.
  • bank10 , bank11 , bank12 and bank13 are used to illustrate four memory blocks 201 in a channel 20 . It can be understood that, in other embodiments, the number of memory blocks included in each channel 20 may also be any other number, such as 2 or 6, and so on.
  • the data port 203 is used for receiving data to be stored in the storage unit or sending data read out from the storage unit.
  • the memory chip 200 includes a plurality of channels 20 , and the memory chip 200 further includes a common circuit 204 shared by the plurality of channels 20 .
  • the shared circuit 204 may be a test control circuit, and the test control circuit is used for test control of the multiple channels 20 .
  • the shared circuit may also be at least one of a temperature sensor circuit, an analog circuit or a charge pump circuit.
  • the memory may further include: a test port, and in the test mode, a plurality of channels 20 share the same test port for testing. Due to the setting of the shared test port, it is beneficial to reduce the number of ports in the memory, thereby reducing the difficulty of using the probe card to test the memory, and reducing the difficulty of manufacturing the probe card.
  • the command clock has a first preset edge
  • the data clock has a second preset edge
  • the first preset edge is the first rising edge or the first falling edge
  • the corresponding clock edge of the aforementioned command clock is the first rising edge edge or the first falling edge
  • the second preset edge is the second rising edge or the second falling edge
  • the corresponding clock edge of the aforementioned data clock is the second rising edge or the second falling edge.
  • the command clock and the data clock are the same clock signal
  • the first preset edge and the second preset edge are the same preset edge
  • the preset edge may be one of a rising edge or a falling edge.
  • the command clock and the data clock may also be different clock signals, and accordingly, the clock edge of the command clock and the clock edge of the data clock need to be distinguished.
  • the two memory chips 200 share the channel 02, and the two memory chips 200 share the channel 02 and are electrically connected to the control chip 214.
  • the first memory chip 210 and the second memory chip 220 are used to connect the two memory chips 200 to each other. differentiate.
  • Each memory chip 200 uses the same clock signal, and the command port 202 of each memory chip 200 uses different clock edges to receive or send signals, and the data ports 203 of each memory chip 200 use different clock edges to receive or send signals.
  • the command port 202 of the first memory chip 210 uses the first rising edge to receive or send signals
  • the command port 202 of the second memory chip 220 uses the first falling edge to receive or send signals
  • the data port of the first memory chip 210 203 uses the second rising edge to receive or transmit the signal
  • the data port 203 of the second memory chip 220 uses the second falling edge to receive or transmit the signal.
  • the command signal includes an activation command and a read command corresponding to each activation command.
  • the channel 20 is further configured such that, after the command port 202 receives an activation command for a memory block 201, the command port 202 receives a read command corresponding to the activation command.
  • the activate command includes row address signals, which are received through row address port 212 ; the read command includes column address signals, which are received through column address port 222 .
  • the activation command and the read command may also contain other control signals other than the row address signal or the column address signal, and these other control signals are used to help or assist the memory chip 200 to identify whether the command is an activation command or a read command.
  • the channel 20 is further configured such that the activation command and the read command are received through different ports in the command port 202, so that the activation command and the read command can be received simultaneously.
  • the command signal includes an activation command and a read command corresponding to the activation command; the channel 20 is further configured such that after the command port 202 alternately receives activation commands for different memory blocks 201, the command port 202 alternately receives the activation commands corresponding to the activation commands. read command. Specifically, after the row address ports 212 alternately receive activation commands for different memory blocks 201, the column address ports 222 alternately receive read commands corresponding to the activation commands.
  • the channel 20 is also configured such that after the command port 202 receives the read command, the data port 203 alternately transmits data signals corresponding to different memory blocks 201 .
  • FIG. 5 is a working timing diagram of the first memory chip 210 and the second memory chip 220 .
  • the working principle of the memory will be described below with reference to the timing diagram.
  • the same clock signal is used for the command clock and the data clock.
  • the clock signal is indicated by CK
  • the timing diagram of the activation command signal for the first memory chip 210 is shown in ACT1
  • the activation command signal for the second memory chip 220 is shown in ACT2.
  • RD1 shows the timing diagram of the read command signal for the first memory chip 210
  • RD2 shows the timing diagram of the read command signal for the second memory chip 220
  • DATA1 shows the data port 203 of the first memory chip 210
  • DATA2 shows the timing diagram of the data signal of the data port 203 of the second memory chip 220 .
  • the first memory chip 210 includes four memory blocks 201 of bank10, bank11, and bank12, and the activation command signal includes ACT10/ACT11/AC1T2/ACT13 for activating bank10, bank11, bank12, and bank13, respectively.
  • ACT10 and Bank10 corresponds to bank11
  • ACT11 corresponds to bank11
  • the read command signal includes RD10/RD11/RD12/RD13 corresponding to bank10, bank11, and bank12 one-to-one with bank13
  • the data signal includes DATA10/DATA11/DATA12/DATA13
  • activation command ACT10 Corresponding to bank10, one read command RD10 and data signal DATA10
  • the activation command ACT11 corresponds to bank11
  • the activation command ACT12 corresponds to bank12
  • the activation command ACT13 corresponds to bank13
  • one read command RD13 and data signal DATA13 that is, one
  • the activation signals ACT20/ACT21/ACT22/ACT23 For a detailed description of the activation signals ACT20/ACT21/ACT22/ACT23, the read command signals RD20/RD21/RD22/RD23, and the data signals DATA20/DATA21/DATA22/DATA23 corresponding to the second memory chip 220, reference may be made to the foregoing description.
  • the command port 202 and the data port 203 use the rising edge of the clock to receive or send signals as an example: the command port 202 receives a signal for a memory block 201 at the rising edge of the clock signal. After the activation command ACT10, the command port 202 receives a read command RD10 corresponding to the activation command ACT10 on the rising edge; after the command port 202 receives the read command RD10, the data port 203 sends the data signal DATA10 on the rising edge of the clock signal.
  • the process after the command port 202 receives the activation command ACT11/ACT12/ACT13 is similar to the above.
  • the row address port 212 in the command port 202 receives the activation command ACT10 to activate bank10 at the first rising edge of the clock signal, and the row address port 212 in the command port 202 receives the activation command ACT11 at the second rising edge of the clock signal
  • the activation command ACT11 receives the activation command ACT12 that activates bank12 at the third rising edge of the clock signal, and receives the activation command ACT12 that activates bank13 at the fourth rising edge of the clock signal;
  • the column address port 222 in the command port 202 is in the first
  • the n rising edges receive the read command RD10 corresponding to the active command ACT10, the command port 202 receives the read command RD11 corresponding to the active command ACT11 at the n+1 rising edge, and receives the active command ACT2 at the n+2 rising edge
  • the corresponding read command RD12 receives the read command RD13 corresponding to the activation command ACT13 at the n+3th rising edge, where n
  • the data port 203 sends the data signal DATA10 corresponding to the memory block bank10 on the mth rising edge of the clock signal, and the data port 203 sends the data signal DATA11 corresponding to the memory block bank11 on the m+1th rising edge of the clock signal.
  • the data signal DATA12 corresponding to bank12 is sent on the m+2th rising edge
  • the data signal DATA13 corresponding to bank13 is sent on the m+3th rising edge, where m is any natural number, and for each memory block 201 In other words, the corresponding m is greater than n.
  • the activation commands ACT10 , ACT11 , ACT12 , and ACT13 are respectively received at successive rising edges as an example, that is, the activation commands corresponding to different memory blocks 201 are respectively received at successive rising edges. In other embodiments , and can also receive activation commands corresponding to different memory blocks on non-consecutive rising edges.
  • the row address port 212 can receive the activation command ACT12 during the period when the column address port 222 receives the read command RD12, so that there is no need to wait for all read commands.
  • the activation command can only be received after all the command signals are received, so that the data bus can be filled, that is, the data port 203 can continuously transmit data to avoid the idle problem of the data bus within a certain period of time, thereby helping to improve the storage speed of the memory.
  • the command port 202 and the data port 203 use the falling edge of the clock to receive or send signals: the command port 202 receives a signal for a memory block 201 at the falling edge of the clock signal. After the activation command ACT20, the command port 202 receives a read command RD20 corresponding to the activation command ACT20 on the rising edge; after the command port 202 receives the read command RD20, the data port 203 sends the data signal DATA20 on the falling edge of the clock signal.
  • the process of sending the second memory chip 220 to send the data signals DATA21/DATA22/DATA23 will not be described in detail.
  • the first memory chip 210 and the second memory chip 220 receive or transmit signals on the rising edge or the falling edge of the clock, respectively, the first memory chip 210 and the second memory chip 220 sharing the channel 02 transmit data without interfering with each other.
  • the command signal includes an activation command and a plurality of read commands corresponding to each activation command; the channel 20 is further configured such that, after the command port 202 receives an activation command for a memory block 201, the command port 202 is in multiple Each corresponding clock edge receives a read command corresponding to the active command, so that the command port 202 receives a plurality of read commands corresponding to the active command at a plurality of consecutive corresponding clock edges.
  • the channel 20 is also configured such that the data port 203 respectively transmits a plurality of data signals on a plurality of consecutive corresponding clock edges, and the number of the data signals is the same as the number of the received read commands.
  • the command signal may include an activation command and a plurality of read commands corresponding to each activation command; the channel 20 may also be configured such that after the command port 202 alternately receives activation commands for different memory blocks 201, the command port 202 alternately receives and Multiple read commands for each active command. Specifically, after the command port 202 alternately receives the activation commands for different memory blocks 201, the command port 202 receives a read command corresponding to the activation command at each clock edge of the plurality of corresponding clock edges, so that the command port 202 is in continuous operation.
  • a plurality of clock edges receive a plurality of read commands corresponding to the activation command, until the command port 202 receives a plurality of read commands corresponding to the activation command for one memory block 201, after which the command port 202 receives the activation for another memory block 201.
  • Command corresponding to multiple read commands
  • FIG. 6 is another working timing diagram of the first memory chip 210 and the second memory chip 220 .
  • the working principle of the memory will be described below with reference to FIG. 6 , taking one activation command corresponding to four read commands as an example.
  • each signal in FIG. 6, please refer to the description corresponding to FIG. 5.
  • the main differences corresponding to FIG. 5 include: the activation command ACT10 for activating bank10 corresponds to 4 read commands RD10 and 4 data signals DATA10, which are used to activate
  • the activation command ACT1 of bank11 corresponds to four read commands RD11 and the data signal DATA11, and so on, that is, one activation command corresponds to a plurality of different read commands.
  • the command port 202 receives the activation command ACT10 for a memory block 201 at the rising edge of the clock signal
  • the command port 202 202 receives four read commands RD10 corresponding to the active command ACT10 at four consecutive rising edges
  • the data port 203 sends four data signals DATA10 at the rising edge of the clock signal.
  • the command port 202 receives 4 read commands RD11 corresponding to the activation command ACT11 at 4 consecutive rising edges.
  • the data port 203 After the command port 202 receives the read command RD11, the data port 203 sends four data signals DATA11 at the rising edge of the clock signal, and the process after the command port 202 receives the activation commands ACT12 and ACT13 is similar to the above.
  • the second memory chip 220 transmits or receives signals at the falling edge of the clock signal.
  • the working principle of the second memory chip 220 reference may be made to the working principle of the first memory chip 210 .
  • the channel 20 is also configured such that: for any memory block 201, the time difference between receiving the activation command signal and receiving the corresponding read command signal is greater than or equal to tRCD, where tRCD is the memory block 201 when the activation command signal is received.
  • tRCD is the memory block 201 when the activation command signal is received
  • tRCD is: the interval from the row valid to the read/write command is defined as tRCD, that is, the delay from RAS to CAS, RAS is the row address strobe signal, referred to as the row address signal, and CAS is the column address signal.
  • the address strobe pulse signal is referred to as the column address signal, and tRCD can be understood as the row strobe period. In this way, it can be ensured that the memory block 201 has been fully activated before or when the read command is received, and the read operation can be performed when the read command is received, thereby further improving the storage speed of the memory.
  • the time difference between ACT10 and RD10 is tRCD; for bank11, the time difference between ACT11 and RD11 may be greater than or equal to tRCD, the situation of bank12 and bank13 will not be listed one by one here.
  • tRCD time difference between the received command signal and the corresponding read command signal
  • different storage blocks 201 use the same command port 202 and data port 203 . In other embodiments, different memory blocks may also use different command ports and different data ports.
  • the row address port 212 since the row address port 212 is separated from the column address port 222, the row address signal and the column address signal can be transmitted at the same time, avoiding data reception caused by errors caused by the handshake or synchronization of the command clock and the data clock. Or send errors, so it is beneficial to avoid the problem that the data line is not full in certain time periods, and to ensure that the data line is always full of data, thereby increasing the storage speed of the memory and improving the storage performance of the memory.

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Abstract

一种存储器，包括：控制芯片(114)；多个存储芯片(100)，多个存储芯片(100)共用信道(01)与控制芯片(114)电连接，多个存储芯片(100)被配置为，采用相同的时钟信号，且多个存储芯片(100)分别在时钟信号的不同的时钟状态下与控制芯片(114)进行信息交互。能够减少存储器的信道数量。

Description

存储器
交叉引用
本申请引用于2020年8月26日递交的名称为“存储器”的第2020108741835号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
随着DRAM应用的领域越来越多，如DRAM越来越多地应用于各种领域，用户对于DRAM性能指标的要求越来越高，且会由于应用领域不同而对DRAM有着不同的要求。
发明内容
本申请实施例解决的技术问题为提供一种存储器，解决存储器功耗大、成本高的问题。
为解决上述问题，本申请实施例提供一种存储器，一种存储器，包括：控制芯片；多个存储芯片，多个所述存储芯片共用信道与所述控制芯片电连接， 多个所述存储芯片被配置为，采用相同的时钟信号，且多个所述存储芯片分别在所述时钟信号的不同的时钟状态下与所述控制芯片进行信息交互。
另外，所述多个存储芯片包括：第一存储芯片和第二存储芯片；所述第一存储芯片被配置为，在所述时钟信号的上升沿与所述控制芯片进行信息交互；所述第二存储芯片被配置为，在所述时钟信号的下降沿与所述控制芯片进行信息交互。
另外，所述时钟信号包括命令时钟和数据时钟，所述多个所述存储芯片分别在所述时钟信号的不同的时钟状态下与所述控制芯片进行信息交互，包括：所述第一存储芯片在所述命令时钟和/或所述数据时钟的上升沿与所述控制芯片进行信息交互；所述第二存储芯片在所述命令时钟和/或所述数据时钟的下降沿与所述控制芯片进行信息交互。
另外，所述时钟状态包括所述命令时钟的第一预设沿以及所述数据时钟的第二预设沿；所述第一预设沿为第一上升沿或者第一下降沿，所述第二预设沿为第二上升沿或者第二下降沿。
另外，每一所述存储芯片包括至少一个通道，所述通道包括：多个存储块，每一所述存储块包括多个存储单元，多个所述存储块被配置为交替进行读写操作；命令端口，所述命令端口被配置为在所述命令时钟的对应时钟沿接收命令信号，所述命令信号用于控制所述存储块的读写操作；数据端口，所述数据端口被配置为，在所述数据时钟的对应时钟沿接收待写入到所述存储块的数据信号或者发送数据信号；其中，所述对应时钟沿包括所述上升沿或者所述下降沿，所述命令端口包括行地址端口和列地址端口，所述行地址端口用于接收目标存储单元所在位置的行地址信号，所述列地址端口用于接收目标存储单元 所在位置的列地址信号，所述目标存储单元为所述多个存储单元中选中的存储单元。
另外，所述命令时钟和所述数据时钟为同一时钟信号。
另外，所述多个所述存储芯片共用信道与所述控制芯片电连接，包括：两个所述存储芯片共用信道与所述控制芯片电连接；每一所述存储芯片采用相同的所述时钟信号，且各所述存储芯片的所述命令端口采用不同的时钟沿接收或者发送信号，各所述存储芯片的所述数据端口采用不同的时钟沿接收或者发送信号。
另外，所述命令信号包括激活命令以及与每一所述激活命令对应的读命令；所述通道还被配置为，所述命令端口接收针对一所述存储块的所述激活命令后，所述命令端口接收与所述激活命令对应的所述读命令。
另外，所述通道还被配置为，在所述命令端口接收所述读命令之后，所述数据端口发送所述数据信号。
另外，所述命令信号包括激活命令以及与每一所述激活命令对应的多个读命令；所述通道还被配置为，所述命令端口接收针对一所述存储块的所述激活命令后，所述命令端口在多个对应时钟沿接收一与所述激活命令对应的所述读命令，以使所述命令端口在连续多个对应时钟沿接收多个与所述激活命令对应的所述读命令。
另外，所述通道还被配置为，所述数据端口在连续多个所述对应时钟沿分别发送多个所述数据信号，所述数据信号的数量与所接受到的所述读命令的数量相同。
另外，所述命令信号包括激活命令和与所述激活命令对应的读命令；所 述通道还被配置为，所述命令端口交替接收针对不同所述存储块的激活命令后，所述命令端口交替接收与所述激活命令对应的所述读命令。
另外，所述通道还被配置为，在所述命令端口接收所述读命令之后，所述数据端口交替发送与不同所述存储块对应的所述数据信号。
另外，所述命令信号包括激活命令以及与每一所述激活命令对应的多个读命令；所述通道还被配置为，所述命令端口交替接收针对不同存储块的所述激活命令，且所述命令端口交替接收与每一所述激活命令对应的多个所述读命令。
另外，其特征在于，所述激活命令包括所述行地址信号，所述读命令包括所述列地址信号；所述通道还被配置为：所述激活命令和所述读命令通过所述命令端口中的不同端口接收。
另外，所述通道还被配置为：对于任意所述存储块，接收所述激活命令和接收与所述激活命令对应的所述读命令的时间差大于或等于tRCD，所述tRCD为所述存储块在接收到所述激活命令之后可进行读操作所需的最短准备时间。
另外，所述存储芯片包括多个所述通道，所述存储芯片还包括多个所述通道共用的共用电路。
另外，所述存储芯片还包括：测试端口，在测试模式下，多个所述通道共用同一所述测试端口进行测试。
另外，所述共用电路包括测试控制电路，所述测试控制电路用于对多个所述通道的测试控制。
另外，多个所述存储芯片依次堆叠于所述控制芯片上，所述信道包括硅 通孔结构。
与相关技术相比，本申请实施例提供的技术方案具有以下优点：
本申请实施例提供一种结构性能优越的存储器，多个存储芯片共用信道与控制芯片电连接，多个存储芯片被配置为，采用相同的时钟信号，且多个存储芯片分别在不同的时钟状态下与控制芯片进行信息交互。由于多个存储芯片共用信道与控制芯片电连接，因此无需为每个存储芯片分别设置一个与控制芯片电连接的信道，有利于减少存储器所需的信道的数量，从而降低存储器的成本、功耗。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请一实施例提供的存储器的结构示意图；
图2为本申请一实施例提供的存储器中共用信道的两个存储芯片对应的工作信号的时序图；
图3为本申请另一实施例提供的存储器的结构示意图；
图4为图3中一存储芯片的结构示意图；
图5为图3中第一存储芯片以及第二存储芯片的一种工作时序图；
图6为图3中第一存储芯片以及第二存储芯片的另一种工作时序图。
具体实施方式
由背景技术可知，现有技术的存储器的性能有待提高。
为解决上问题，本申请实施提供一种存储器，多个存储芯片，多个存储 芯片共用信道与控制芯片电连接，多个存储芯片被配置为，采用相同的时钟信号，且多个存储芯片分别在时钟信号的不同的时钟状态下与控制芯片进行信息交互。由于多个存储芯片共用信道，因而在不影响多个存储芯片与控制芯片信息交互的质量的前提下，节省存储器所需的信道数量，从而节省存储器的面积，降低存储器的成本，减小存储器的功耗。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请一实施例提供的存储器的结构示意图。
参考图1，本实施例中，存储器包括：控制芯片114；多个存储芯片100，多个存储芯片100共用信道01与控制芯片114电连接，多个存储芯片100被配置为，采用相同的时钟信号，且多个存储芯片100分别在时钟信号的不同的时钟状态下与控制芯片114进行信息交互。
由于多个存储芯片100分别在时钟信号的不同的时钟状态下与控制芯片114进行信息交互，若为一个时钟信号的情况下，单个存储芯片100在时钟信号的上升沿或者下降沿中的一者传输数据，就能够使得存储器在时钟信号的所有不同时钟状态下均能传输数据，即存储器在时钟信号的上升沿以及下降沿均能够传输数据。本实施例的时钟信号可以为一个时钟，也可以为多个时钟，本实施例对此不做限定。
以下将结合附图对本实施例提供的存储器进行详细说明。
本实施例中，存储器可以为动态随机存储器(DRAM)。
具体地，多个存储芯片100可以在控制芯片114上依次层叠设置，有利于提高存储密度且减小存储芯片100与控制芯片114的距离；或者，多个存储芯片100也可以在控制芯片114上并排设置，有利于减小存储器的纵向厚度。本实施例中，多个存储芯片100依次堆叠于控制芯片114上，且信道01包括硅通孔结构(TSV，Through Silicon Via)。
本实施例中，多个存储芯片100包括：第一存储芯片110和第二存储芯片120；第一存储芯片110被配置为，在时钟信号的上升沿与控制芯片114进行信息交互；第二存储芯片120被配置为，在时钟信号的下降沿与控制芯片114进行信息交互。
第一存储芯片110的工作模式为时钟信号的上升沿传输数据，第二存储芯片120的工作模式为时钟信号的下降沿传输数据；然而，由于第一存储芯片110以及第二存储芯片120工作在同一时钟信号的不同时钟状态下，使得第一存储芯片110和第二存储芯片120整体上的宏观工作模式为：在时钟信号的上升沿以及下降沿均传输数据。因此，对于单个存储芯片100而言满足在时钟信号的上升沿或者下降沿中的一者传输数据，但是对于存储器整体而言即可达到在时钟信号的上升沿和下降沿均传输数据的效果。
图1中示意出了两个不同的信道01，且其中两个存储芯片100共用其中一信道01，另外两个存储芯片100共用另一信道01。具体地，可以为：如图1所示，相邻的两个存储芯片100共用同一信道01，或者，相间隔的两个存储芯片100共用同一信道01。可以理解的是，存储器可以包括任意数量个信道01，且两个存储芯片100共用同一信道01。
此外，时钟信号包括命令时钟和数据时钟，多个存储芯片100分别在时钟信号的不同的时钟状态下与控制芯片114进行信息交互，包括：第一存储芯片110在命令时钟和/或数据时钟的上升沿与控制芯片114进行信息交互；第二存储芯片120在命令时钟和/或数据时钟的下降沿与控制芯片114进行信息交互。
具体地，时钟状态包括命令时钟的第一预设沿以及数据时钟的第二预设沿；第一预设沿为第一上升沿或者第一下降沿，第二预设沿为第二上升沿或者第二下降沿。每一存储芯片100在命令时钟的第一预设沿与控制芯片114进行信息交互，每一存储芯片100在数据时钟的第二预设沿与控制芯片114进行信息交互。更具体地，存储芯片100被配置为，在命令时钟的第一预设沿接收命令信号，命令信号用于控制存储芯片100的读写操作；存储芯片100还被配置为，在数据时钟的第二预设沿接收待写入到存储芯片100的数据信号或者发送数据信号。举例来说，第一存储芯片110被配置为，在命令时钟的第一上升沿接收命令信号，在数据时钟的第二上升沿接收待写入的数据信号或者发送数据信号；第二存储芯片120被配置为，在时钟信号的第一下降沿接收命令信号，在数据时钟的第二下降沿接收待写入的数据信号或者发送数据信号。本实施例中，命令时钟与数据时钟为同一时钟信号，相应的第一预设沿与第二预设沿为同一预设沿。
图2为本实施例提供的存储器中共用信道的两个存储芯片对应的工作信号的时序图，且命令时钟与数据时钟为同一时钟信号，CK为时钟信号，DATA1为第一存储芯片110传输数据的时序图，DATA2为第二存储芯片120传输数据的时序图，DATA为将DATA1和DATA2合并的时序图。
以下将结合图2对本实施例提供的存储器的工作原理进行说明。
在时钟信号的第一个上升沿，第一存储芯片110接收激活命令信号；在时钟信号的第m个上升沿，第一存储芯片110接收读命令信号；在时钟信号的第n个上升沿，第一存储芯片110传输数据。在时钟信号的第一个下降沿，第二存储芯片120接收激活命令信号；在时钟信号的第m个下降沿，第二存储芯片120接收读命令信号；在时钟信号的第n个下降沿，第二存储芯片120传输数据。如此，在时钟信号的不同上升沿第一存储芯片110传输数据，在时钟信号的不同下降沿第二存储芯片120传输数据，直至完成数据的传输。
可以理解的是，上述是以存储器进行读取操作为例进行说明的，存储器进行写入操作期间同样是第一存储芯片110以及第二存储芯片120交替传输数据。
本实施例提供的存储器，由于多个存储芯片100共用信道01，在不影响控制芯片114与多个存储芯片100信息交互的带宽的前提下，减少了存储器的信道01数量，从而降低了存储器的制造成本以及功耗。
本申请另一实施例还提供一种存储器，该存储器与前述存储器大致相同，主要区别包括对每一存储芯片进行了更详细的说明。以下将结合附图对本实施例提供的存储器进行详细说明，需要说明的是，与前述实施例相同或者相应的部分，可参考前述实施例的说明，以下将不做赘述。
图3为本申请另一实施例提供的存储器的结构示意图，图4为图3中一存储芯片的结构示意图。
参考图3及图4，本实施例中，存储器包括：控制芯片214；多个存储芯片200，多个存储芯片200共用信道02与控制芯片214电连接，多个存储芯片200被配置为，采用相同的时钟信号，且多个存储芯片200分别在时钟信号的 不同的时钟状态下与控制芯片214进行信息交互；具体地，存储芯片200包括第一存储芯片210和第二存储芯片220，时钟信号包括命令时钟和数据时钟，第一存储芯片210在命令时钟和/或数据时钟的上升沿与控制芯片214进行信息交互，且第二存储芯片220在命令时钟和/或数据时钟的下降沿与控制芯片214进行信息交互。
每一存储芯片200包括至少一个通道20，通道20包括：多个存储块201，每一存储块201包括多个存储单元，多个存储块201被配置为交替进行读写操作；命令端口202，命令端口202被配置为在命令时钟的对应时钟沿接收命令信号，命令信号用于控制存储块201的读写操作；数据端口203，数据端口203被配置为，在数据时钟的对应时钟沿接收待写入到存储块201的数据信号或者发送数据信号；其中，对应时钟沿包括前述的上升沿或者下降沿，命令端口202包括行地址端口212和列地址端口222，行地址端口212用于接收目标存储单元所在位置的行地址信号，列地址端口222用于接收目标存储单元所在位置的列地址信号，目标存储单元为多个存储单元中选中的存储单元。
可以理解的是，对应时钟沿指的是，该存储芯片200进行信息交互对应的命令时钟的上升沿或者下降沿，该存储芯片200进行信息交互对应的数据时钟的上升沿或者下降沿。
需要注意的是，本实施例所称的命令端口包括传输命令信号和地址信号的端口，但也不限于此。
以下将结合附图对本实施例提供的存储器进行详细说明。
每一存储块201中的多个存储单元可以呈阵列式分布。本实施例中，以每一通道(channel)20包括4个存储块201作为示例，图4中以bank10、bank11、 bank12以bank13示意出一通道20中的4个存储块201。可以理解的是，在其他实施例中，每一通道20包括的存储块的数量也可以为其他任意数量个，例如为2个或者6个等。
数据端口203用于接收待存入存储单元中的数据或发送从存储单元中读出的数据。
存储芯片200包括多个通道20，且存储芯片200还包括多个通道20共用的共用电路204。本实施例中，该共用电路204可以为测试控制电路，测试控制电路用于对多个通道20的测试控制。在其他实施例中，该共用电路也可以为温度传感器电路、模拟电路或者电荷泵电路中的至少一种。
存储器还可以包括：测试端口，且在测试模式下多个通道20共用同一测试端口进行测试。由于共用测试端口的设置，有利于减少存储器中端口的数量，从而降低采用探针卡对存储器进行测试的难度，且降低探针卡的制造难度。
具体地，命令时钟具有第一预设沿，数据时钟具有第二预设沿，且第一预设沿为第一上升沿或者第一下降沿，前述的命令时钟的对应时钟沿为第一上升沿或者第一下降沿，第二预设沿为第二上升沿或者第二下降沿，前述的数据时钟的对应时钟沿为第二上升沿或者第二下降沿。本实施例中，命令时钟和数据时钟为同一时钟信号，第一预设沿与第二预设沿为同一预设沿，该预设沿可以为上升沿或者下降沿中的一种。如此，有利于简化电路设计，避免由于命令时钟和数据时钟握手或同步产生的错误而导致的数据接收或发送错误，提高存储器的存储正确率。需要说明的是，在其他实施例中，命令时钟和数据时钟也可以为不同的时钟信号，相应的，需区分命令时钟的时钟沿以及数据时钟的时钟沿。
另外，本实施例中，两个存储芯片200共用信道02，且两个存储芯片200共用信道02与控制芯片214电连接，以第一存储芯片210以及第二存储芯片220将两个存储芯片200区分开。每一存储芯片200采用相同的时钟信号，且各存储芯片200的命令端口202采用不同的时钟沿接收或者发送信号，各存储芯片200的数据端口203采用不同的时钟沿接收或者发送信号。
举例来说，第一存储芯片210的命令端口202采用第一上升沿接收或者发送信号，第二存储芯片220的命令端口202采用第一下降沿接收或者发送信号，第一存储芯片210的数据端口203采用第二上升沿接收或者发送信号，第二存储芯片220的数据端口203采用第二下降沿接收或者发送信号。
具体地，命令信号包括激活命令以及与每一激活命令对应的读命令。通道20还被配置为，命令端口202接收针对一存储块201的激活命令后，命令端口202接收与激活命令对应的读命令。更具体地，激活命令包括行地址信号，其中行地址信号通过行地址端口212接收；读命令包括列地址信号，其中列地址信号通过列地址端口222接收。需要注意的是，激活命令和读命令中还可能包含除行地址信号或列地址信号以外的其他控制信号，这些其他控制信号用于帮助或辅助存储芯片200识别该命令是否是激活命令或读命令，且这些其他控制信号可通过除行地址端口212和列地址端口222之外的其他命令端口接收；如此，行地址端口212可以连续地接收行地址信号，列地址端口222可以连续地接收列地址信号。相应的，通道20还被配置为：激活命令和读命令通过命令端口202中的不同端口接收，从而可以实现激活命令和读命令的同时接收。
本实施例中，命令信号包括激活命令和与激活命令对应的读命令；通道20还被配置为，命令端口202交替接收针对不同存储块201的激活命令后，命 令端口202交替接收激活命令对应的读命令。具体地，行地址端口212交替接收针对不同存储块201的激活命令后，列地址端口222交替接收激活命令对应的读命令。
此外，通道20还被配置为，在命令端口202接收读命令之后，数据端口203交替发送与不同存储块201对应的数据信号。
图5为第一存储芯片210以及第二存储芯片220的一种工作时序图，以下将结合时序图对该存储器的工作原理进行说明。
图5中命令时钟以及数据时钟采用同一时钟信号，以CK示意出时钟信号，ACT1示意出针对第一存储芯片210的激活命令信号的时序图，ACT2示意出针对第二存储芯片220的激活命令信号的时序图，RD1示意出针对第一存储芯片210的读命令信号的时序图，RD2示意出针对第二存储芯片220的读命令信号的时序图，DATA1示意出第一存储芯片210的数据端口203的数据信号的时序图，DATA2示意出第二存储芯片220的数据端口203的数据信号的时序图。
其中，以第一存储芯片210包括bank10、bank11、bank12以bank13四个存储块201作为示例，激活命令信号包括分别用于激活bank10、bank11、bank12以bank13的ACT10/ACT11/AC1T2/ACT13，ACT10与bank10对应，ACT11与bank11对应，以此类推；读命令信号包括与bank10、bank11、bank12以bank13一一对应的RD10/RD11/RD12/RD13，数据信号包括DATA10/DATA11/DATA12/DATA13；激活命令ACT10与bank10、1个读命令RD10以及数据信号DATA10对应，激活命令ACT11与bank11、1个读命令RD11以及数据信号DATA11对应，激活命令ACT12与bank12、1个读命令RD12以及数据信号DATA12对应，激活命令ACT13与bank13、与1个读命令RD13 以及数据信号DATA13对应，即一激活命令对应一读命令。有关第二存储芯片220对应的激活信号ACT20/ACT21/ACT22/ACT23、读命令信号RD20/RD21/RD22/RD23、数据信号DATA20/DATA21/DATA22/DATA23的详细说明可参考前述说明。
如图5所示，对于第一存储芯片210，以命令端口202和数据端口203采用时钟的上升沿接收或者发送信号作为示例：命令端口202在时钟信号的上升沿接收到针对一存储块201的激活命令ACT10后，命令端口202在上升沿接收与激活命令ACT10对应的1个读命令RD10；在命令端口202接收读命令RD10之后，数据端口203在时钟信号的上升沿发送数据信号DATA10。关于命令端口202接收到激活命令ACT11/ACT12/ACT13后的流程与前述类似。具体地，命令端口202中的行地址端口212在时钟信号的第一个上升沿接收激活bank10的激活命令ACT10，命令端口202中的行地址端口212在时钟信号的第二个上升沿接收激活bank11的激活命令ACT11，在时钟信号的第三个上升沿接收激活bank12的激活命令ACT12，在时钟信号的第四个上升沿接收激活bank13的激活命令ACT12；命令端口202中的列地址端口222在第n个上升沿接收与激活命令ACT10对应的读命令RD10，命令端口202在第n+1个上升沿接收与激活命令ACT11对应的读命令RD11，在第n+2个上升沿接收与激活命令ACT2对应的读命令RD12，在第n+3个上升沿接收与激活命令ACT13对应的读命令RD13，其中，n为任意自然数。相应的，数据端口203在时钟信号的第m个上升沿发送与存储块bank10对应的数据信号DATA10，数据端口203在时钟信号的第m+1个上升沿发送与存储块bank11对应的数据信号DATA11，在第m+2个上升沿发送与bank12对应的数据信号DATA12，在第m+3个上升 沿发送与bank13对应的数据信号DATA13，其中，m为任意自然数，且对于每一存储块201而言，对应的m大于n。
需要说明的是，图5中以在连续的上升沿分别接收激活命令ACT10、ACT11、ACT12、ACT13作为示例，即在连续的上升沿分别接收不同存储块201对应的激活命令，在其他实施例中，也可以在非连续的上升沿分别接收不同存储块对应的激活命令。
从图5中不难发现，由于行地址端口212与列地址端口222不共用，因此在列地址端口222接收读命令RD12期间，行地址端口212可以接收激活命令ACT12，如此，无需等待所有的读命令信号都接收完毕之后才能接收激活命令，使得数据总线能够被填满，即数据端口203可以连续传输数据，避免数据总线在一定时间段内出现的空闲问题，从而有利于提升存储器的存储速度。
此外，如图5所示，对于第二存储芯片220，以命令端口202和数据端口203采用时钟的下降沿接收或者发送信号：命令端口202在时钟信号的下降沿接收到针对一存储块201的激活命令ACT20后，命令端口202在上升沿接收与激活命令ACT20对应的1个读命令RD20；在命令端口202接收读命令RD20之后，数据端口203在时钟信号的下降沿发送数据信号DATA20。有关发第二存储芯片220发送数据信号DATA21/DATA22/DATA23的过程将不做详细赘述。
由于第一存储芯片210和第二存储芯片220分别在时钟的上升沿或者下降沿接收或者发送信号，因此共用信道02的第一存储芯片210以及第二存储芯片220传输数据互不干扰。
在另一个例子中，命令信号包括激活命令以及与每一激活命令对应的多个读命令；通道20还被配置为，命令端口202接收针对一存储块201的激活命 令后，命令端口202在多个对应时钟沿接收一与激活命令对应的读命令，以使命令端口202在连续多个对应时钟沿接收多个与激活命令对应的读命令。通道20还被配置为，数据端口203在连续多个对应时钟沿分别发送多个数据信号，数据信号的数量与所接收到的读命令的数量相同。
此外，命令信号可以包括激活命令以及与每一激活命令对应的多个读命令；通道20还可以被配置为，命令端口202交替接收针对不同存储块201的激活命令后，命令端口202交替接收与每一激活命令对应的多个读命令。具体地，命令端口202交替接收针对不同存储块201的激活命令后，命令端口202在多个对应时钟沿中的每一时钟沿接收一与激活命令对应的读命令，以使命令端口202在连续多个时钟沿接收多个与激活命令对应的读命令，直至命令端口202接收完针对一存储块201的激活命令对应的多个读命令，之后，命令端口202接收针对另一存储块201的激活命令对应的多个读命令。
图6为第一存储芯片210以及第二存储芯片220的另一种工作时序图，以下将结合图6对该存储器的工作原理进行说明，以一个激活命令对应4个读命令作为示例。
有关图6中各信号的说明可参考图5对应的说明，与图5对应的主要区别包括：用于激活bank10的激活命令ACT10与4个读命令RD10以及4个数据信号DATA10对应，用于激活bank11的激活命令ACT1与4个读命令RD11以及数据信号DATA11对应，以此类推，即一激活命令对应多个不同的读命令。
以在时钟信号的上升沿接收或发送信号的第一存储芯片210作为示例：如图6所示，命令端口202在时钟信号的上升沿接收到针对一存储块201的激活命令ACT10后，命令端口202在4个连续的上升沿接收与激活命令ACT10 对应的4个读命令RD10，在命令端口202接收读命令RD10之后，数据端口203在时钟信号的上升沿发送四个数据信号DATA10。在接收到针对另一存储块201的激活命令ACT11后，命令端口202在4个连续的上升沿接收与激活命令ACT11对应的4个读命令RD11，在命令端口202接收读命令RD11之后，数据端口203在时钟信号的上升沿发送四个数据信号DATA11，关于命令端口202接收到激活命令ACT12以及ACT13后的流程与前述类似。
第二存储芯片220在时钟信号的下降沿发送或者接收信号，有关第二存储芯片220的工作原理可参考第一存储芯片210的工作原理。
需要说明的是，本实施例中，通道20还被配置为：对于任意存储块201，接收激活命令信号与接收对应的读命令信号的时间差大于或等于tRCD，tRCD为存储块201在接收到激活命令信号之后可进行读操作所需的最短准备时间。具体地，关于tRCD的定义为：从行有效到读/写命令发出之间的间隔被定义为tRCD，即RAS到CAS的延迟，RAS为行地址选通脉冲信号简称行地址信号，CAS为列地址选通脉冲信号简称列地址信号，tRCD可理解为行选通周期。如此，可以保证存储块201在接收到读命令之前或接收到读命令时已经被完全激活，在接收到读命令时即可进行读操作，从而进一步地提高存储器的存储速度。
具体地，以第一存储芯片210作为示例，如图5及图6，对于bank10而言，ACT10与RD10之间的时间差为tRCD；对于bank11而言，ACT11与RD11之间的时间差可以大于或等于tRCD，关于bank12以及bank13的情形在此不再一一列举。不管一个激活命令对应一个读命令还是对应多个读命令，均可以通过合理的设置保证对于任意存储块201，接收命令信号与接收对应的读命令信号的时间差大于或等于tRCD。
本实施例提供的存储器中，不同的存储块201采用相同的命令端口202以及数据端口203。在其他实施例中，不同的存储块也可以采用不同的命令端口以及不同的数据端口。
本实施例提供的存储器，由于行地址端口212与列地址端口222分开，因而可以实现行地址信号和列地址信号同时传输，避免由于命令时钟和数据时钟握手或同步产生的错误而导致的数据接收或发送错误，因此有利于避免在某些时间段上数据线未被占满的问题，保证数据线始终被数据占满，从而提高存储器的存储速度，改善存储器的存储性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种存储器，其特征在于，包括：
    控制芯片；
    多个存储芯片，多个所述存储芯片共用信道与所述控制芯片电连接，多个所述存储芯片被配置为，采用相同的时钟信号，且多个所述存储芯片分别在所述时钟信号的不同的时钟状态下与所述控制芯片进行信息交互。
  2. 如权利要求1所述的存储器，其特征在于，所述多个存储芯片包括：第一存储芯片和第二存储芯片；所述第一存储芯片被配置为，在所述时钟信号的上升沿与所述控制芯片进行信息交互；所述第二存储芯片被配置为，在所述时钟信号的下降沿与所述控制芯片进行信息交互。
  3. 如权利要求2所述的存储器，其特征在于，所述时钟信号包括命令时钟和数据时钟，所述多个所述存储芯片分别在所述时钟信号的不同的时钟状态下与所述控制芯片进行信息交互，包括：所述第一存储芯片在所述命令时钟和/或所述数据时钟的上升沿与所述控制芯片进行信息交互；所述第二存储芯片在所述命令时钟和/或所述数据时钟的下降沿与所述控制芯片进行信息交互。
  4. 如权利要求3所述的存储器，其特征在于，所述时钟状态包括所述命令时钟的第一预设沿以及所述数据时钟的第二预设沿；所述第一预设沿为第一上升沿或者第一下降沿，所述第二预设沿为第二上升沿或者第二下降沿。
  5. 如权利要求3所述的存储器，其特征在于，每一所述存储芯片包括至少一个通道，所述通道包括：多个存储块，每一所述存储块包括多个存储单元，多个所述存储块被配置为交替进行读写操作；命令端口，所述命令端口被配置为在所述命令时钟的对应时钟沿接收命令信号，所述命令信号用于控制所述 存储块的读写操作；数据端口，所述数据端口被配置为，在所述数据时钟的对应时钟沿接收待写入到所述存储块的数据信号或者发送数据信号；其中，所述对应时钟沿包括所述上升沿或者所述下降沿，所述命令端口包括行地址端口和列地址端口，所述行地址端口用于接收目标存储单元所在位置的行地址信号，所述列地址端口用于接收目标存储单元所在位置的列地址信号，所述目标存储单元为所述多个存储单元中选中的存储单元。
  6. 如权利要求3所述的存储器，其特征在于，所述命令时钟和所述数据时钟为同一时钟信号。
  7. 如权利要求5所述的存储器，其特征在于，所述多个所述存储芯片共用信道与所述控制芯片电连接，包括：两个所述存储芯片共用信道与所述控制芯片电连接；每一所述存储芯片采用相同的所述时钟信号，且各所述存储芯片的所述命令端口采用不同的时钟沿接收或者发送信号，各所述存储芯片的所述数据端口采用不同的时钟沿接收或者发送信号。
  8. 如权利要求5所述的存储器，其特征在于，所述命令信号包括激活命令以及与每一所述激活命令对应的读命令；所述通道还被配置为，所述命令端口接收针对一所述存储块的所述激活命令后，所述命令端口接收与所述激活命令对应的所述读命令。
  9. 如权利要求8所述的存储器，其特征在于，所述通道还被配置为，在所述命令端口接收所述读命令之后，所述数据端口发送所述数据信号。
  10. 如权利要求5所述的存储器，其特征在于，所述命令信号包括激活命令以及与每一所述激活命令对应的多个读命令；所述通道还被配置为，所述命令端口接收针对一所述存储块的所述激活命令后，所述命令端口在多个对应时钟 沿接收一与所述激活命令对应的所述读命令，以使所述命令端口在连续多个对应时钟沿接收多个与所述激活命令对应的所述读命令。
  11. 如权利要求10所述的存储器，其特征在于，所述通道还被配置为，所述数据端口在连续多个所述对应时钟沿分别发送多个所述数据信号，所述数据信号的数量与所接收到的所述读命令的数量相同。
  12. 如权利要求5所述的存储器，其特征在于，所述命令信号包括激活命令和与所述激活命令对应的读命令；所述通道还被配置为，所述命令端口交替接收针对不同所述存储块的激活命令后，所述命令端口交替接收与所述激活命令对应的所述读命令。
  13. 如权利要求12所述的存储器，其特征在于，所述通道还被配置为，在所述命令端口接收所述读命令之后，所述数据端口交替发送与不同所述存储块对应的所述数据信号。
  14. 如权利要求5所述的存储器，其特征在于，所述命令信号包括激活命令以及与每一所述激活命令对应的多个读命令；所述通道还被配置为，所述命令端口交替接收针对不同存储块的所述激活命令，且所述命令端口交替接收与每一所述激活命令对应的多个所述读命令。
  15. 如权利要求8、11、12或14所述的存储器，其特征在于，所述激活命令包括所述行地址信号，所述读命令包括所述列地址信号；所述通道还被配置为：所述激活命令和所述读命令通过所述命令端口中的不同端口接收。
  16. 如权利要求15所述的存储器，其特征在于，所述通道还被配置为：对于任意所述存储块，接收所述激活命令和接收与所述激活命令对应的所述读命令的时间差大于或等于tRCD，所述tRCD为所述存储块在接收到所述激活命 令之后可进行读操作所需的最短准备时间。
  17. 如权利要求5所述的存储器，其特征在于，所述存储芯片包括多个所述通道，所述存储芯片还包括多个所述通道共用的共用电路。
  18. 如权利要求17所述的存储器，其特征在于，所述存储芯片还包括：测试端口，在测试模式下，多个所述通道共用同一所述测试端口进行测试。
  19. 如权利要求17所述的存储器，其特征在于，所述共用电路包括测试控制电路，所述测试控制电路用于对多个所述通道的测试控制。
  20. 如权利要求1所述的存储器，其特征在于，多个所述存储芯片依次堆叠于所述控制芯片上，所述信道包括硅通孔结构。
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