WO2022062485A1 - 接触窗结构、金属插塞及其形成方法、半导体结构 - Google Patents

接触窗结构、金属插塞及其形成方法、半导体结构 Download PDF

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Publication number
WO2022062485A1
WO2022062485A1 PCT/CN2021/099873 CN2021099873W WO2022062485A1 WO 2022062485 A1 WO2022062485 A1 WO 2022062485A1 CN 2021099873 W CN2021099873 W CN 2021099873W WO 2022062485 A1 WO2022062485 A1 WO 2022062485A1
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Prior art keywords
hole
layer
forming
central
contact window
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PCT/CN2021/099873
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English (en)
French (fr)
Inventor
刘杰
吴秉桓
应战
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to EP21773256.9A priority Critical patent/EP4002437B1/en
Priority to US17/401,461 priority patent/US12002748B2/en
Publication of WO2022062485A1 publication Critical patent/WO2022062485A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H10W20/0696—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs by using sacrificial placeholders, e.g. using sacrificial plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers

Definitions

  • the present disclosure relates to the field of semiconductors, and in particular, to a contact window structure, a metal plug, a method for forming the same, and a semiconductor structure.
  • the design of multi-layer metal interconnect lines with two or more layers has become a method commonly used in VLSI technology.
  • the conduction between different metal layers or between the metal layer and the pad layer can be achieved through metal plugs. Due to the higher and higher integration of the device, the aspect ratio of the via hole formed in the process of forming the metal plug is continuously improved, which leads to a compromise in the performance of the circuit requirements put forward by the design side.
  • the technical problem to be solved by the embodiments of the present disclosure is to provide a contact window structure, a metal plug and a method for forming the same, which can reduce the phenomenon that the critical dimension at the bottom of the via is smaller than the critical dimension at the top of the via, and overcome the size of the via during the etching process. Miniature problem.
  • Embodiments of the present disclosure provide a method for forming a contact window structure, including:
  • An annular gasket is formed on the surface of the target layer, and a central through hole exposing part of the surface of the target layer is arranged in the middle of the annular gasket;
  • the annular spacer is removed to form a contact window structure.
  • the forming process of the annular spacer includes:
  • the forming process of the annular spacer includes:
  • the surface of the mask material layer and the spacer material layer on the bottom surface of the first through hole are removed by etching, and an annular spacer is formed on the sidewall surface of the first through hole.
  • the masking material layer is removed, and a dielectric layer is formed on the target layer and the annular spacer, or after the annular spacer is formed, all remaining the mask material layer, and a dielectric layer is formed on the mask material layer.
  • the formed dielectric layer when the dielectric layer is formed, can completely fill the central through hole in the middle of the annular spacer.
  • the dielectric layer when the dielectric layer is formed, the dielectric layer partially fills or does not fill the central through hole, and an air gap is formed between the annular spacers.
  • a sacrificial layer is filled in the central through hole in the middle of the annular spacer, and when the dielectric layer is etched to form an etching hole, the etching rate of the sacrificial layer is greater than the etching rate of the dielectric layer.
  • the thickness of the annular spacer is more than 3 times the size of the central through hole.
  • a portion of the target layer is etched away.
  • a substrate is provided in which the target layer is formed, the substrate exposing a surface of the target layer.
  • Embodiments of the present disclosure also provide a method for forming a metal plug, including:
  • Metal is filled in the contact window structure to form a metal plug.
  • the embodiment of the present disclosure also provides a contact window structure, including:
  • a contact window structure located in the dielectric layer includes a connected etching hole and a central through hole, the etching hole is located above the central through hole, the central through hole exposes a part of the surface of the target layer, and the central through hole is The size of the hole is larger than the size of the bottom of the etched hole.
  • Embodiments of the present disclosure also provide a semiconductor structure, including:
  • annular gasket located on the surface of the target layer, a central through hole exposing part of the surface of the target layer is arranged in the middle of the annular gasket;
  • An etching hole in the dielectric layer communicated with the central through hole.
  • Embodiments of the present disclosure also provide a metal plug, including:
  • a contact window structure located in the dielectric layer includes a connected etching hole and a central through hole, the etching hole is located above the central through hole, the central through hole exposes a part of the surface of the target layer, and the central through hole is The size of the hole is larger than the size of the bottom of the etched hole;
  • the method for forming a contact window structure provides a target layer; an annular gasket is formed on the surface of the target layer, and a central through hole that exposes part of the surface of the target layer is provided in the middle of the annular gasket; and the target layer is formed to cover the target layer. layer and the dielectric layer of the annular gasket; etching the dielectric layer to form an etching hole in the dielectric layer that communicates with the central through hole; removing the annular gasket to form a contact window structure.
  • the size of the central through hole can be increased, so that the size of the bottom of the contact window structure can be increased, and the metal plug is formed in the contact window structure.
  • the contact area between the bottom of the metal plug and the target layer is increased, reducing the contact resistance between the two, and due to the existence of the annular spacer, the depth or aspect ratio of the etched hole formed in the dielectric layer will be reduced. Therefore, when forming the etching hole, it is not necessary to increase the size of the etching hole or even reduce the size of the etching hole to improve the integration degree, that is, the contact window structure can be formed.
  • the size of the top portion can be kept the same as the size of the top portion formed in the related art or have a smaller size, so that the size of the bottom portion of the formed contact window structure is increased.
  • the forming process of the annular spacer includes: forming a columnar structure on a partial surface of the target layer; forming a spacer on a sidewall and a top surface of the columnar structure, a substrate and a surface of a part of the target layer material layer; maskless etching removes the spacer material layer on the top surface of the columnar structure and the surface of the substrate and part of the target layer, and forms an annular spacer on the sidewall surface of the columnar structure; after forming the annular spacer The columnar structure is then removed.
  • the size and shape of the annular spacer formed in this way are more precise and have a higher sidewall topography.
  • the forming process of the annular spacer includes: forming a masking material layer on the surface of the substrate and a portion of the target layer, wherein the masking material layer is formed with a surface that exposes the portion of the target layer. a first through hole; a spacer material layer is formed on the sidewall and bottom surface of the first through hole and the surface of the mask material layer; maskless etching removes the surface of the mask material layer and the first The gasket material layer on the bottom surface of the through hole forms an annular gasket on the side wall surface of the first through hole.
  • the size and shape of the annular spacer formed in this way are more precise and have a higher sidewall topography.
  • the size of the bottom of the contact window structure will become larger, and when the metal plug is formed in the contact window structure, the contact area between the bottom of the metal plug and the target layer is increased, and the contact area between the two is reduced. Contact resistance.
  • FIG. 1 is a schematic structural diagram of a through hole formed in the related art
  • FIGS. 2 to 14 are schematic cross-sectional structural diagrams illustrating a process of forming a contact window structure according to an embodiment of the disclosure.
  • the formation process of the metal plug in the related art includes: forming a target metal layer 102 in a substrate 101 , the target metal layer 102 being flush with the surface of the substrate 101 ; forming on the substrate 101 and the target metal layer 102 Dielectric layer 103; forming a through hole (or contact window structure) 104 in the dielectric layer 103 exposing the surface of the target metal layer; filling metal (not shown in the figure) in the through hole (or contact window structure) to form a metal plug plug (not shown in the figure).
  • the aspect ratio of the via hole formed in the dielectric layer is also continuously improved, and the high aspect ratio via hole 104 has always been a great challenge for the etching process.
  • the through hole is gradually narrowed, and the critical dimension 21 at the bottom of the through hole 104 is smaller than the critical dimension at the top of the through hole 104 .
  • the performance of the circuit requirements proposed by the design side will also be compromised.
  • the size of the opening of the bottom layer of the via often limits the resistance value of the entire contact window, and the reduced size will greatly reduce the contact area with the target metal layer.
  • a shrinking phenomenon occurs in the existing process of forming vias, especially for high aspect ratio vias, which causes the size of the bottom of the via to be smaller than that of the top and increases the contact resistance.
  • embodiments of the present disclosure provide a contact window structure, a metal plug, a method for forming the same, and a semiconductor structure, and the method for forming the contact window structure provides a target layer; an annular spacer is formed on the surface of the target layer, A central through hole that exposes part of the surface of the target layer is arranged in the middle of the annular gasket; a dielectric layer covering the target layer and the annular gasket is formed; the dielectric layer is etched to form a communication with the central through hole in the dielectric layer etch hole; remove the annular spacer to form a contact window structure.
  • the size of the central through hole can be increased, so that the size of the bottom of the contact window structure can be increased, and the metal plug is formed in the contact window structure.
  • the contact area between the bottom of the metal plug and the target layer is increased, reducing the contact resistance between the two, and due to the existence of the annular spacer, the depth or aspect ratio of the etched hole formed in the dielectric layer will be reduced. Therefore, when forming the etching hole, it is not necessary to increase the size of the etching hole or even reduce the size of the etching hole to improve the integration degree, that is, the contact window structure can be formed.
  • the size of the top portion can be kept the same as the size of the top portion formed in the related art or have a smaller size, so that the size of the bottom portion of the formed contact window structure is increased.
  • a substrate 201 having a target layer 202 formed therein is provided, and the substrate 201 exposes a surface of the target layer 202 .
  • the substrate 201 may be a semiconductor substrate
  • the target layer 202 may be a doped region (such as a doped region doped with N-type impurity ions or doped with P-type impurity ions) located in the semiconductor substrate. region) or a metal suicide region (such as a nickel suicide region or a cobalt suicide region) in a semiconductor substrate.
  • the material of the semiconductor substrate can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or It can also be other materials, such as III-V group compounds such as gallium arsenide.
  • the base 201 may include a semiconductor substrate and an interlayer dielectric layer on the semiconductor substrate, and the target layer 202 is located in the interlayer dielectric layer.
  • the interlayer dielectric layer may be a single-layer or multi-layer stack structure
  • the target layer 202 may be a metal layer
  • the metal layer may be connected to a conductive structure (such as a conductive plug) formed in the underlying dielectric layer.
  • the surface of the target layer 202 may be flush with the surface of the substrate 201 or slightly higher than the surface of the substrate 102 .
  • target layers 202 There may be one or more ( ⁇ 2) target layers 202 formed in the substrate 201. When there are multiple target layers 202, the adjacent target layers are separated. In this embodiment, only the substrate is used.
  • a target layer 202 in 201 is illustrated as an example.
  • annular spacer needs to be formed on the target layer 202 subsequently.
  • a columnar structure 204 is formed on a part of the surface of the target layer 202 .
  • the columnar structure 204 determines the position and shape of the subsequently formed annular spacer.
  • the shape of the columnar structure can be cylindrical or elliptical, or other suitable shapes (cube or cuboid).
  • the bottom area of the columnar structures 204 is smaller than the area of the target layer 202 .
  • the material of the columnar structure 204 may be different from the material of the target layer 202 , the substrate 201 and the subsequently formed annular spacer.
  • the columnar structure 204 is subsequently removed, the columnar structure 204 is relatively relative to the target layer 202 , the substrate 201 and the annular gasket.
  • the wafer has a high etch selectivity ratio, reducing or preventing etch damage to the target layer 202, the substrate 201 and the annular spacer.
  • the material of the columnar structure 204 may be a photoresist material or a mask material, and the mask material may be silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, polysilicon, amorphous silicon, amorphous carbon, One or more of low-K dielectric materials.
  • the formation process of the columnar structure 204 includes: forming a photoresist layer on the substrate 201 and the target layer 202; The adhesive layer is exposed and developed to form columnar structures on the target layer 202 .
  • the formation process of the columnar structure 204 includes: forming a mask material layer on the substrate 201 and the target layer 202; etch to form columnar structures on the target layer 202 .
  • a spacer material layer 205 is formed on the sidewalls and top surfaces of the columnar structures 204 , the surfaces of the substrate 201 and part of the target layer 202 .
  • the gasket material layer 205 is subsequently used to form annular gaskets.
  • the material of the spacer material layer 205 is different from the material of the subsequently formed dielectric layer.
  • the dielectric layer has a high etching selectivity ratio relative to the annular spacer.
  • the material of the spacer material layer 205 may be one or more of silicon nitride, silicon oxide, silicon carbonitride, and silicon oxynitride.
  • the formation of the spacer material layer adopts a chemical vapor deposition process.
  • the thickness of the spacer material layer 205 determines the width of the subsequently formed annular spacer and the enlarged size of the central through hole.
  • the thickness of the spacer material layer is more than three times the size of the columnar structure or the central through hole formed subsequently. Under the aforesaid specific ratio, the size of the bottom of the central through hole can be effectively enlarged in the subsequent process, so that the central through hole can meet the actual requirements.
  • the thicker the deposited shim material layer the larger the size area of the window opened after the shim material is removed.
  • the top surface of the columnar structure 204 and the spacer material layer on the surface of the substrate 201 and part of the target layer 202 are removed by maskless etching, and a ring-shaped spacer 203 is formed on the sidewall surface of the columnar structure 204 .
  • the etching of the gasket material layer adopts an anisotropic dry etching process, which may be a plasma etching process.
  • the size of the central through hole can be enlarged, so that the size of the bottom of the contact window structure can be enlarged.
  • the contact window structure When the metal plug is formed, the contact area between the bottom of the metal plug and the target layer is increased, and the contact resistance between the two is reduced. The width ratio will be reduced, which will reduce the difficulty of forming the hole and etching. Therefore, when forming the etching hole, it is not necessary to increase the size of the etching hole or even reduce the size of the etching hole to improve the integration degree.
  • the size of the top of the contact window structure can be kept the same as the size of the top formed in the related art or have a smaller size, so that the size of the bottom of the formed contact window structure is increased.
  • the columnar structure is removed, and a central through hole 213 is formed in the middle of the annular spacer 203 , and the central through hole 213 exposes a part of the surface of the target layer 202 .
  • wet etching or dry etching can be used to remove the columnar structure.
  • an etching with a high etching selectivity ratio of the columnar structure to the annular spacer 203 , the target layer 202 and the substrate 201 can be used. solution or etching gas.
  • FIGS. 6 to 8 Another embodiment of the present disclosure further provides a method for forming the annular spacer 203 , please refer to FIGS. 6 to 8 .
  • a mask material layer is formed on part of the surfaces of the substrate 201 and the target layer 202 .
  • a first through hole 207 exposing a part of the surface of the target layer 202 is formed in the mask material layer 206 .
  • the material of the mask material layer 206 can be one or more of photoresist, silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, polysilicon, amorphous silicon, amorphous carbon, and low-K dielectric materials. kind.
  • the formation process of the mask material layer 206 may be a chemical vapor deposition process.
  • the material of the mask material layer 206 is photoresist, and the first through holes 207 are formed in the mask material layer 206 through exposure and development processes.
  • a first through hole 207 may be formed in the mask material layer 206 through an etching process.
  • the shape and position of the first through hole 207 define the shape and position of the subsequently formed annular gasket.
  • a spacer material layer 208 is formed on the sidewall and bottom surfaces of the first through hole 207 and the surface of the mask material layer 206 .
  • the layer of gasket material 208 is subsequently used to form an annular gasket.
  • the material of the spacer material layer 208 is different from the material of the subsequently formed dielectric layer.
  • the dielectric layer has a high etching selectivity ratio relative to the annular spacer.
  • the material of the spacer material layer 208 may be one or more of silicon nitride, silicon oxide, silicon carbonitride, and silicon oxynitride.
  • the formation of the spacer material layer adopts a chemical vapor deposition process.
  • the thickness of the spacer material layer 208 determines the width of the subsequently formed annular spacer and the enlarged size of the central through hole. In one embodiment, the thickness of the spacer material layer 208 is more than three times the size of the columnar structure or the central through hole formed subsequently.
  • the surface of the mask material layer 206 and the spacer material layer on the bottom surface of the first through hole are removed by maskless etching, and an annular spacer 203 is formed on the sidewall surface of the first through hole.
  • a central through hole 213 is formed in the middle of the gasket 203 .
  • the etching of the gasket material layer adopts an anisotropic dry etching process, which may be a plasma etching process.
  • the mask material layer 206 is removed after the annular spacer 203 is formed, and the mask material layer 206 may be removed by a wet or dry etching process.
  • the mask material layer 206 is an isolation material that can be used for electrical isolation between devices, for example, when the mask material layer is made of the same material as the dielectric layer to be formed subsequently, when the mask material layer 206 is formed After the annular spacer 203 is formed, the mask material layer 206 is retained, and a dielectric layer is formed directly on the mask material layer 206 subsequently, so that no additional steps are required to remove the mask material layer 206 .
  • FIGS. 9 and 10 are schematic top views of the annular gasket 203 formed above.
  • the shape of the annular spacer 203 shown in 10 is an elliptical annular shape, which can reduce the resistance of the metal plugs subsequently formed in the contact window structure.
  • the shape of the annular spacer can also be a long strip, which can reduce the resistance of the metal plug formed in the contact window structure subsequently.
  • FIG. 11 is performed on the basis of FIG. 5 , and a dielectric layer 211 covering the substrate 201 , the target layer 202 and the annular spacer 203 is formed.
  • the material of the dielectric layer 211 is different from the material of the annular spacer 203 , and the material of the dielectric layer 211 may be one of silicon nitride, silicon oxide, silicon nitride carbide, and silicon oxynitride.
  • the dielectric layer 211 is formed by chemical vapor deposition.
  • the dielectric layer 211 may be planarized by a planarization process, so that the dielectric layer 211 has a flat surface, and the planarization process may be a chemical mechanical polishing process.
  • the formed dielectric layer 211 can completely fill the central through hole in the middle of the annular spacer 203 .
  • the dielectric layer 211 may partially fill or not fill the central through hole, an air gap is formed between the annular spacers, and after an etching hole is formed in the dielectric layer, etching continues During etching, the central through hole in the middle of the annular spacer 203 can be easily re-exposed, so as to prevent the size of the etched hole from being affected by too long etching time.
  • the air gap is formed by adjusting the step coverage of the deposition process when the dielectric layer 211 is formed.
  • a sacrificial layer may be filled in the central through hole in the middle of the annular spacer 203, and when the dielectric layer is subsequently etched to form an etching hole, the sacrificial layer may be filled with a sacrificial layer.
  • the etching rate is greater than the etching rate for the dielectric layer, so that the central through hole between the annular spacers 203 is also easily re-exposed, preventing the size of the etching hole from being affected by an excessively long etching time.
  • the material of the sacrificial layer may be a semiconductor insulating material such as silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbide.
  • the dielectric layer 211 is etched, and an etching hole 212 communicating with the central through hole 213 is formed in the dielectric layer 211 .
  • a patterned mask layer (such as a patterned photoresist layer or a patterned hard mask layer and a photolithography layer is formed on the dielectric layer 211 )
  • the stacking structure of the adhesive layer the dielectric layer 211 is etched using the patterned mask layer as a mask.
  • the etching hole 212 After the etching hole 212 is formed, continue to etch the material filled in the central through hole 213 at the bottom of the etching hole 212, such as a dielectric layer material or a sacrificial layer material, so that the central through hole 213 is re-exposed and the etching through The hole 212 communicates with the central through hole 213 .
  • the material filled in the central through hole 213 at the bottom of the etching hole 212 such as a dielectric layer material or a sacrificial layer material
  • the etching hole 212 formed in the dielectric layer 211 still has a high aspect ratio, so the size of the top of the formed etching hole 212 is smaller than the size of the bottom, that is, from the upper surface of the dielectric layer 211 . In the direction of the lower surface, the size of the etching hole 212 gradually decreases. In other embodiments, the top and bottom dimensions of the etched holes may also be the same.
  • the dielectric layer 211 may be etched by an anisotropic dry etching process, such as an anisotropic plasma etching process.
  • an anisotropic dry etching process such as an anisotropic plasma etching process.
  • the dielectric layer 211 has a high etching selectivity ratio relative to the annular spacer 203 (specifically, the etching selectivity ratio may be greater than or equal to 2:1).
  • the annular spacer 203 may define the bottom position of the etching hole 212 , and the diameter of the bottom of the etching hole 212 is smaller than the outer diameter of the annular spacer 203 .
  • the annular spacer 203 (refer to FIG. 12 ) is removed along the etching hole 212 and the central through hole 213 , so that the size of the central through hole 213 becomes larger, and the etching hole 212 and the enlarged central through hole 213 Form the contact window structure.
  • the annular spacer can be removed by an isotropic wet or dry etching process.
  • the annular spacer 203 is removed by wet etching, and the etching solution used in the wet etching is hot phosphoric acid.
  • the size of the central through hole 213 will become larger, so that the size 22 of the central through hole 213 will be larger than the size 23 of the bottom of the etched hole 212, that is, the size of the bottom of the formed contact window structure Compared with the size of the bottom of the contact window structure formed in the related art, the size of the bottom of the contact window structure will increase.
  • the metal plug is subsequently formed in the contact window structure, the contact area between the bottom of the metal plug and the target layer is increased, and the contact between the two is reduced. resistance.
  • a part of the target layer 202 is etched away.
  • metal is filled in the contact window structure to form a metal plug 214 .
  • the material of the metal plug 214 is metal or other suitable conductive materials.
  • the formation process of the metal plug 214 is as follows: forming a conductive material layer on the surface of the contact window structure and the dielectric layer 211, the conductive material layer filling the contact window structure, the The conductive material layer can be metal (such as tungsten), and the conductive material layer is formed by a sputtering process; the conductive material layer higher than the surface of the dielectric layer 211 is removed by a chemical mechanical polishing process, and a metal plug is formed in the contact window structure. Plug 214.
  • a capacitor structure is formed in the contact structure after the contact structure is formed.
  • Embodiments of the present disclosure also provide a semiconductor structure, referring to FIG. 12 , including:
  • annular gasket 203 located on the surface of the target layer 202, a central through hole 213 exposing a part of the surface of the target layer 202 is disposed in the middle of the annular gasket 203;
  • the etching hole 212 in the dielectric layer 211 communicates with the central through hole 213 .
  • FIG. 13 Another embodiment of the present disclosure also provides a contact window structure, please refer to FIG. 13 , including:
  • a contact window structure located in the dielectric layer 211 includes a connected etching hole 212 and a central through hole 213, the etching hole 212 is located above the central through hole 213, and the central through hole 213 exposes a portion of the target layer surface, and the size of the central through hole 213 is larger than the size of the bottom of the etched hole 212 .
  • Another embodiment of the present disclosure further provides a metal plug, referring to FIG. 14 , including:
  • the contact window structure located in the dielectric layer 211 includes a connected etching hole 212 (refer to FIG. 13 ) and a central through hole 213 (refer to FIG. 13 ).
  • the etching hole 212 is located above the central through hole 213, so The central through hole 213 exposes a part of the surface of the target layer, and the size of the central through hole 213 is larger than the size of the bottom of the etching hole 212;
  • Metal plugs 214 that fill the contact structure.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种接触窗结构、金属插塞及其形成方法，所述接触窗结构的形成方法、半导体结构，在目标层表面上形成环形垫片，所述环形垫片中间具有暴露出目标层部分表面的中央通孔；形成覆盖所述基底、目标层和环形垫片的介质层；刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔；沿刻蚀孔和中央通孔去除所述环形垫片，使得中央通孔的尺寸变大，所述刻蚀孔与尺寸变大后的中央通孔构成接触窗结构。

Description

接触窗结构、金属插塞及其形成方法、半导体结构
相关申请的交叉引用
本公开基于申请号为202011001855.8、申请日为2020年9月22日、申请名称为“接触窗结构、金属插塞及其形成方法、半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本公开。
技术领域
本公开涉及半导体领域，尤其涉及一种接触窗结构、金属插塞及其形成方法、半导体结构。
背景技术
随着集成电路向超大规模集成电路发展，集成电路内部的电路密度越来越大，所包含的元件数量也越来越多，这种发展使得晶圆表面无法提供足够的面积来制作所需的互连线。
为了满足元件缩小后的互连线需求，两层及两层以上的多层金属互连线的设计成为超大规模集成电路技术所通常采用的一种方法。目前，不同金属层或者金属层与衬垫层的导通可以通过金属插塞实现。由于器件集成度越来越高，在形成金属插塞的过程中形成的通孔的深宽比不断提高，这导致设计端提出的电路要求表现打折扣。
发明内容
本公开实施例所要解决的技术问题是提供一种接触窗结构、金属插塞及其形成方法，减少发生通孔底部关键尺寸小于通孔顶部关键尺寸的现象，克服刻蚀过程中通孔的尺寸微缩问题。
本公开实施例提供了一种接触窗结构的形成方法，包括：
提供目标层；
在所述目标层表面形成环形垫片，所述环形垫片中间设置有暴露出目标层部分表面的中央通孔；
形成覆盖所述目标层和环形垫片的介质层；
刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔；
去除所述环形垫片，形成接触窗结构。
在一种实施例中，所述环形垫片的形成过程包括：
在所述目标层部分表面上形成柱状结构；
在所述柱状结构的侧壁和顶部表面和部分目标层的表面形成垫片材料层；
刻蚀去除所述柱状结构顶部表面以及部分目标层的表面的垫片材料层，在所述柱状结构的侧壁表面形成环形垫片；
去除所述柱状结构。
在一种实施例中，所述环形垫片的形成过程包括：
在所述目标层部分表面上形成掩膜材料层，所述掩膜材料层中形成有暴露出所述目标层部分表面的第一通孔；
在所述第一通孔的侧壁和底部表面以及所述掩膜材料层的表面形成垫片材料层；
刻蚀去除所述掩膜材料层的表面以及第一通孔底部表面的垫片材料层，在所述第一通孔的侧壁表面形成环形垫片。
在一种实施例中，在形成所述环形垫片后，去除所述掩膜材料层，在所述目标层和环形垫片上形成介质层，或者在形成所述环形垫片后，保留所述掩膜材料层，在所述掩膜材料层上形成介质层。
在一种实施例中，形成所述介质层时，所述形成的介质层可以完全填充所述环形垫片中间的中央通孔。
在一种实施例中，形成所述介质层时，所述介质层部分填充或者不填充所述中央通孔，在所述环形垫片之间形成空气隙。
在一种实施例中，在形成所述介质层之前，在所述环形垫片中间的中央通孔中填充牺牲层，在刻蚀介质层形成刻蚀孔时，对所述牺牲层的刻蚀速率大于对所述介质层的刻蚀速率。
在一种实施例中，所述环形垫片的厚度为所述中央通孔尺寸的3倍以上。
在一种实施例中，在形成接触窗的过程中，所述目标层有部分被刻蚀掉。
在一种实施例中，提供基底，所述目标层形成于基底中，所述基底露出所述目标层的表面。
本公开实施例还提供了一种金属插塞的形成方法，包括：
形成前述所述的接触窗结构；
在所述接触窗结构中填充金属，形成金属插塞。
本公开实施例还提供了一种接触窗结构，包括：
目标层；
位于目标层上的介质层；
位于介质层中的接触窗结构，所述接触窗结构包括连通的刻蚀孔和中央通孔，所述刻蚀孔位于中央通孔上方，所述中央通孔暴露出目标层的部分表面，且所述中央通孔的尺寸大于所述刻蚀孔底部的尺寸。
本公开实施例还提供了一种半导体结构，包括：
目标层；
位于所述目标层表面的环形垫片，所述环形垫片中间设置有暴露出目标层部分表面的中央通孔；
覆盖所述目标层和环形垫片的介质层；
位于所述介质层中与中央通孔连通的刻蚀孔。
本公开实施例还提供了一种金属插塞，包括：
目标层；
位于目标层上的介质层；
位于介质层中的接触窗结构，所述接触窗结构包括连通的刻蚀孔和中央通孔，所述刻蚀孔位于中央通孔上方，所述中央通孔暴露出目标层的部分表面，且所述中央通孔的尺寸大于所述刻蚀孔底部的尺寸；
填充所述接触窗结构的金属插塞。
与相关技术相比，本公开实施例技术方案具有以下优点：
本公开实施例的接触窗结构的形成方法，提供目标层；在所述目标层表面形成环形垫片，所述环形垫片中间设置有暴露出目标层部分表面的中央通孔；形成覆盖所述目标层和环形垫片的介质层；刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔；去除所述环形垫片，形成接触窗结构。通过形成环形垫片，在形成接触窗结构时，去除所述环形垫片后，可以使得中央通孔的尺寸变大，从而使得接触窗结构底部的尺寸会变大，在接触窗结构中形成金属插塞时，使得金属插塞底部与目标层的接触面积增大，减小了两者的接触电阻，并且由于环形垫片的存在，使得介质层中形成的刻蚀孔的深度或深宽比会减小，使得形成孔刻蚀难度减小，因而在形成刻蚀孔时，无需增大刻蚀孔的尺寸甚至可以减小刻蚀孔的尺寸以提高集成度，即可以使得形成的接触窗结构顶部的尺寸可以与相关技术形成的顶部尺寸保持不变或者具有更小的尺寸的同时，使得形成的接触窗结构底部的尺寸被增大。
在一些实施例中，所述环形垫片的形成过程包括：在所述目标层部分表面上形成柱 状结构；在所述柱状结构的侧壁和顶部表面、基底和部分目标层的表面形成垫片材料层；无掩膜刻蚀去除所述柱状结构顶部表面以及基底和部分目标层的表面的垫片材料层，在所述柱状结构的侧壁表面形成环形垫片；在形成所述环形垫片后去除所述柱状结构。这样方法形成的环形垫片的尺寸和形状的精度较高，并具有较高的侧壁形貌。
在一些实施例中，所述环形垫片的形成过程包括：在所述基底和目标层部分表面上形成掩膜材料层，所述掩膜材料层中形成有暴露出所述目标层部分表面的第一通孔；在所述第一通孔的侧壁和底部表面以及所述掩膜材料层的表面形成垫片材料层；无掩膜刻蚀去除所述掩膜材料层的表面以及第一通孔底部表面的垫片材料层，在所述第一通孔的侧壁表面形成环形垫片。这样方法形成的环形垫片的尺寸和形状的精度较高，并具有较高的侧壁形貌。
本公开实施例的接触窗结构，接触窗结构底部的尺寸会变大，在接触窗结构中形成金属插塞时，使得金属插塞底部与目标层的接触面积增大，减小了两者的接触电阻。
附图说明
图1为相关技术形成的通孔的结构示意图；
图2-图14为本公开实施例接触窗结构的形成过程的剖面结构示意图。
具体实施方式
相关技术中的金属插塞的形成过程参考图1，包括：在基底101中形成目标金属层102，所述目标金属层102与基底101的表面齐平；在基底101和目标金属层102上形成介质层103；在介质层103中形成暴露出目标金属层表面的通孔(或接触窗结构)104；在通孔(或接触窗结构)中填充金属(图中未示出)，形成金属插塞(图中未示出)。
随着器件的集成度越来越高，所述介质层中形成的通孔的深宽比也不断提高，高深宽比的通孔104对于刻蚀工艺来说一直是非常大的挑战。通常在向下刻蚀过程中，通孔会逐渐变窄，通孔104底部的关键尺寸21小于通孔104的顶部的关键尺寸。在此微缩的过程中，设计端所提出的电路要求表现也会打折扣。另外，通孔底层开窗尺寸大小往往会限制住整个接触窗的电阻值，经微缩的尺寸会大大降低与目标金属层的接触面积。如背景技术所言，现有形成的通孔的过程中会发生微缩现象，尤其是高深宽比通孔，该现象导致通孔底部尺寸相较于顶部尺寸变小，并且增大接触电阻。
为此，本公开实施例提供了一种接触窗结构、金属插塞及其形成方法、半导体结构，所述接触窗结构的形成方法，提供目标层；在所述目标层表面形成环形垫片，所述环形垫片中间设置有暴露出目标层部分表面的中央通孔；形成覆盖所述目标层和环形垫片的 介质层；刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔；去除所述环形垫片，形成接触窗结构。通过形成环形垫片，在形成接触窗结构时，去除所述环形垫片后，可以使得中央通孔的尺寸变大，从而使得接触窗结构底部的尺寸会变大，在接触窗结构中形成金属插塞时，使得金属插塞底部与目标层的接触面积增大，减小了两者的接触电阻，并且由于环形垫片的存在，使得介质层中形成的刻蚀孔的深度或深宽比会减小，使得形成孔刻蚀难度减小，因而在形成刻蚀孔时，无需增大刻蚀孔的尺寸甚至可以减小刻蚀孔的尺寸以提高集成度，即可以使得形成的接触窗结构顶部的尺寸可以与相关技术形成的顶部尺寸保持不变或者具有更小的尺寸的同时，使得形成的接触窗结构底部的尺寸被增大。
为使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开实施例的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
参考图2，提供基底201，所述基底201中形成有目标层202，所述基底201露出所述目标层202的表面。
在一实施例中，所述基底201可以为半导体衬底，所述目标层202可以为位于半导体衬底中的掺杂区(比如掺杂有N型杂质离子或掺杂有P型杂质离子的区域)或者位于半导体衬底中的金属硅化物区(比如硅化镍区或硅化钴区)。所述半导体衬底的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。
在其他实施例中，所述基底201可以包括半导体衬底和位于半导体衬底上的层间介质层，所述目标层202位于层间介质层中。所述层间介质层可以为单层或多层堆叠结构，所述目标层202可以为金属层，所述金属层可以与下层介质层中形成的导电结构(比如导电插塞)连接。
所述目标层202的表面可以与所述基底201的表面齐平，或者略高于所述基底102的表面。
所述基底201中形成目标层202可以为一个或多个(≥2个)，所述目标层202为多个时，相邻目标层之间是分立的，本实施例中仅以所述基底201中具有一个目标层202作为示例进行说明。
所述目标层202上后续需要形成环形垫片。为了后续形成环形垫片，在一实施例中， 在所述目标层202部分表面上形成柱状结构204。
所述柱状结构204决定了后续形成的环形垫片位置和形状。所述柱状结构的形状可以为圆柱状或椭圆柱状，或者其他合适的形状(立方体状或长方体状)。所述柱状结构204的底部面积小于所述目标层202的面积。
所述柱状结构204的材料与目标层202、基底201和后续形成的环形垫片的材料可以不相同，在后续去除柱状结构204时，使得柱状结构204相对于目标层202、基底201和环形垫片具有高的刻蚀选择比，减少或防止对目标层202、基底201和环形垫片的刻蚀损伤。
所述柱状结构204材料可以为光刻胶材料或掩膜材料，所述掩膜材料可以为氮化硅、氧化硅、碳氮化硅、氮氧化硅、多晶硅、无定型硅、无定型碳、低K介质材料中一种或几种。
在一实施例中，所述柱状结构204材料为光刻胶材料时，所述柱状结构204的形成过程包括：在所述基底201和目标层202上形成光刻胶层；对所述光刻胶层进行曝光和显影，在所述目标层202上形成柱状结构。
在另一实施例中，所述柱状结构204材料为掩膜材料时，所述柱状结构204的形成过程包括：在所述基底201和目标层202上形成掩膜材料层；对所述进行刻蚀，在所述目标层202上形成柱状结构。
参考图3，在所述柱状结构204的侧壁和顶部表面、基底201和部分目标层202的表面形成垫片材料层205。
所述垫片材料层205后续用于形成环形垫片。所述垫片材料层205的材料与后续形成的介质层的材料不相同，后续在介质层中形成刻蚀孔时，使得介质层相对于所述环形垫片具有高的刻蚀选择比。
所述垫片材料层205的材料可以为氮化硅、氧化硅、碳氮化硅、氮氧化硅中的一种或几种。形成所述垫片材料层采用化学气相沉积工艺。
所述垫片材料层205的厚度决定后续形成的环形垫片的宽度以及中央通孔被扩大的尺寸。所述垫片材料层的厚度为柱状结构或者后续形成的中央通孔的尺寸的3倍以上。在前述特定比例下，在后续过程中能够有效扩大中央通孔底部尺寸，使得中央通孔满足实际需求。沉积的垫片材料层厚度越厚，垫片材料移除后所开窗的尺寸面积越大。
参考图4，无掩膜刻蚀去除所述柱状结构204顶部表面以及基底201和部分目标层202的表面的垫片材料层，在所述柱状结构204的侧壁表面形成环形垫片203。
刻蚀所述垫片材料层采用各项异性的干法刻蚀工艺，可以为等离子体刻蚀工艺。
通过形成的环形垫片203，后续形成接触窗结构时，当去除所述环形垫片时，可以使得中央通孔的尺寸变大，从而使得接触窗结构底部的尺寸会变大，在接触窗结构中形成金属插塞时，使得金属插塞底部与目标层的接触面积增大，减小了两者的接触电阻，并且由于环形垫片的存在，使得介质层中形成的刻蚀孔的深度或深宽比会减小，使得形成孔刻蚀难度减小，因而在形成刻蚀孔时，无需增大刻蚀孔的尺寸甚至可以减小刻蚀孔的尺寸以提高集成度，即可以使得形成的接触窗结构顶部的尺寸可以与相关技术形成的顶部尺寸保持不变或者具有更小的尺寸的同时，使得形成的接触窗结构底部的尺寸被增大。
参考图5，去除所述柱状结构，在所述环形垫片203中间形成中央通孔213，所述中央通孔213暴露出所述目标层202的部分表面。
去除所述柱状结构可以采用湿法刻蚀或干法刻蚀，去除所述柱状结构时可以采用对柱状结构相对于环形垫片203、目标层202和基底201具有高刻蚀选择比的刻蚀溶液或刻蚀气体。
本公开另一实施例还提供了一种环形垫片203的形成方法，请参考图6-图8，首先请参考图6，在所述基底201和目标层202部分表面上形成掩膜材料层206，所述掩膜材料层206中形成有暴露出所述目标层202部分表面的第一通孔207。
所述掩膜材料层206的材料可以为光刻胶、氮化硅、氧化硅、碳氮化硅、氮氧化硅、多晶硅、无定型硅、无定型碳、低K介质材料中一种或几种。所述掩膜材料层206的形成工艺可以为化学气相沉积工艺。
在一实施例中，所述掩膜材料层206的材料为光刻胶，通过曝光和显影工艺在所述掩膜材料层206中形成第一通孔207。所述掩膜材料层206为其他材料时，可以通过刻蚀工艺在所述掩膜材料层206中形成第一通孔207。
所述第一通孔207的形状和位置限定后续形成的环形垫片的形状和位置。
参考图7，在所述第一通孔207的侧壁和底部表面以及所述掩膜材料层206的表面形成垫片材料层208。
所述垫片材料层208后续用于形成环形垫片。所述垫片材料层208的材料与后续形成的介质层的材料不相同，后续在介质层中形成刻蚀孔时，使得介质层相对于所述环形垫片具有高的刻蚀选择比。
所述垫片材料层208的材料可以为氮化硅、氧化硅、碳氮化硅、氮氧化硅中的一种 或几种。形成所述垫片材料层采用化学气相沉积工艺。
所述垫片材料层208的厚度决定后续形成的环形垫片的宽度以及中央通孔被扩大的尺寸。在一实施例中，所述垫片材料层208的厚度为柱状结构或者后续形成的中央通孔的尺寸的3倍以上。
参考图8，无掩膜刻蚀去除所述掩膜材料层206的表面以及第一通孔底部表面的垫片材料层，在所述第一通孔的侧壁表面形成环形垫片203，环形垫片203中间形成中央通孔213。
刻蚀所述垫片材料层采用各项异性的干法刻蚀工艺，可以为等离子体刻蚀工艺。
在一实施例中，在形成环形垫片203后去除所述掩膜材料层206，去除所述掩膜材料层206可以采用湿法或干法刻蚀工艺。
在另一实施例中，当所述掩膜材料层206为隔离材料，可以用于器件之间的电学隔离时，比如所述掩膜材料层与后续形成的介质层的材料相同时，在形成环形垫片203后，保留所述掩膜材料层206，后续在所述掩膜材料层206上直接形成介质层，从而无需额外的步骤去除所述掩膜材料层206。
参考图9和图10，图9和图10为前述形成的环形垫片203的俯视结构示意图，图9中所示的环形垫片203的形状为圆环形，利于接触窗结构的设计，图10中所示的环形垫片203的形状为椭圆环形，可以降低后续在接触窗结构中形成的金属插塞的电阻。在其他实施例中，所述环形垫片的形状还可以为长条形，可以降低后续在接触窗结构中形成的金属插塞的电阻。
参考图11，图11在图5的基础上进行，形成覆盖所述基底201、目标层202和环形垫片203的介质层211。
所述介质层211的材料与所述环形垫片203的材料不相同，所述介质层211材料可以为氮化硅、氧化硅、氮碳化硅、氮氧化硅中一种。
通过化学气相沉积形成所述介质层211。在一实施例中，可以通过平坦化工艺平坦化所述介质层211，使得介质层211具有平坦的表面，所述平坦化工艺可以为化学机械研磨工艺。
在一实施例中，所述形成的介质层211可以完全填充所述环形垫片203中间的中央通孔。在另一实施例中，所述介质层211可以部分填充或者不填充所述中央通孔，在所述环形垫片之间形成空气隙，后续在介质层中形成刻蚀孔后，继续往下刻蚀时，很容易就可以使得所述环形垫片203中间的中央通孔被重新暴露，防止刻蚀时间过长对刻蚀孔 的尺寸产生影响。在一实施例中，在形成介质层211时通过调节沉积工艺的台阶覆盖率，形成所述空气隙。
在另一实施例中，在形成所述介质层之前，可以在所述环形垫片203中间的中央通孔中填充牺牲层，后续在刻蚀介质层形成刻蚀孔时，对所述牺牲层的刻蚀速率大于对所述介质层的刻蚀速率，使得环形垫片203之间的中央通孔也很容易被重新暴露，防止刻蚀时间过长对刻蚀孔的尺寸产生影响。在一实施例中，所述介质层材料为氧化硅时，所述牺牲层的材料可以为氮化硅、氮氧化硅、碳氮化硅或碳氧化硅等半导体绝缘材料。参考图12，刻蚀所述介质层211，在所述介质层211中形成与中央通孔213连通的刻蚀孔212。
在一实施例中，在刻蚀所述介质层211之前，在所述介质层211上形成图形化的掩膜层(比如图形化的光刻胶层或者图形化的硬掩膜层与光刻胶层的堆叠结构)，以所述图形化的掩膜层为掩膜，刻蚀所述介质层211。
在形成刻蚀孔212后，继续刻蚀所述刻蚀孔212底部的中央通孔213中被填充的材料，比如介质层材料或牺牲层材料，使得中央通孔213被重新暴露，并使得刻蚀通孔212和中央通孔213连通。
在一实施例中，所述介质层211中形成的刻蚀孔212仍具有高的深宽比，因而形成的刻蚀孔212顶部的尺寸会小于底部的尺寸，即从介质层211的上表面到下表面的方向上，所述刻蚀孔212的尺寸逐渐减小。在其它实施例中，所述刻蚀孔的顶部尺寸和底部尺寸也可以相同。
在一实施例中，刻蚀所述介质层211可以采用各项异性的干法刻蚀工艺，比如各项异性的等离子体刻蚀工艺。刻蚀所述介质层211形成刻蚀孔212时，所述介质层211相对于环形垫片203具有高的刻蚀选择比(具体的所述刻蚀选择比可以大于等于2:1)，通过环形垫片203可以限定所述刻蚀孔212的底部位置，所述刻蚀孔212底部的直径小于所述环形垫片203外径。
参考图13，沿刻蚀孔212和中央通孔213去除所述环形垫片203(参考图12)，使得中央通孔213的尺寸变大，所述刻蚀孔212与尺寸变大后的中央通孔213构成接触窗结构。
去除所述环形垫片可以采用各项同性的湿法或干法刻蚀工艺。在一实施例中，当所述环形垫片203的材料为氮化硅时，采用湿法刻蚀去除所述环形垫片203，所述湿法刻蚀采用的刻蚀溶液为热磷酸。
去除所述刻蚀垫片后，所述中央通孔213的尺寸会变大，使得中央通孔213的尺寸22会大于所述刻蚀孔212底部的尺寸23，即形成的接触窗结构的底部的尺寸相对于相关技术形成的的接触窗结构底部的尺寸会增大，后续在接触窗结构中形成金属插塞时，使得金属插塞底部与目标层的接触面积增大，减小了两者的接触电阻。
在一实施例中，在形成接触窗的过程中，所述目标层202有部分被刻蚀掉。
在一实施例中，请参考图14，在形成所述接触窗结构后，在所述接触窗结构中填充金属，形成金属插塞214。
所述金属插塞214的材料为金属或其他合适的导电材料。
在一实施例中，所述金属插塞214的形成过程为：在所述接触窗结构和介质层211的表面上形成导电材料层，所述导电材料层填充满所述接触窗结构，所述导电材料层可以金属(比如钨)，通过溅射工艺形成所述导电材料层；采用化学机械研磨工艺去除所述高于介质层211表面的导电材料层，在所述接触窗结构中形成金属插塞214。
在另一实施例中，在形成所述接触窗结构后，在所述接触窗结构中形成电容结构。
本公开实施例还提供了一种半导体结构，参考图12，包括：
目标层202；
位于所述目标层202表面的环形垫片203，所述环形垫片203中间设置有暴露出目标层202部分表面的中央通孔213；
覆盖所述目标层202和环形垫片203的介质层211；
位于所述介质层211中与中央通孔213连通的刻蚀孔212。
需要说明的是，本实施例中(半导体结构)与前述实施例中(接触窗结构的形成过程)中相似或相同结构的限定或描述，在本实施例中不再限定，具体请参考前述实施例相应部分的限定或描述。
本公开另一实施例还提供了一种接触窗结构，请参考图13，包括：
目标层202；
位于目标层202上的介质层211；
位于介质层211中的接触窗结构，所述接触窗结构包括连通的刻蚀孔212和中央通孔213，所述刻蚀孔212位于中央通孔213上方，所述中央通孔213暴露出目标层的部分表面，且所述中央通孔213的尺寸大于所述刻蚀孔212底部的尺寸。
需要说明的是，本实施例中(接触窗结构)与前述实施例中(接触窗结构的形成过程)中相似或相同结构的限定或描述，在本实施例中不再限定，具体请参考前述实施例 相应部分的限定或描述。
本公开另一实施例还提供了一种金属插塞，参考图14，包括：
目标层202；
位于目标层202上的介质层211；
位于介质层211中的接触窗结构，所述接触窗结构包括连通的刻蚀孔212(参考图13)和中央通孔213(参考图13)，所述刻蚀孔212位于中央通孔213上方，所述中央通孔213暴露出目标层的部分表面，且所述中央通孔213的尺寸大于所述刻蚀孔212底部的尺寸；
填充所述接触窗结构的金属插塞214。
需要说明的是，本实施例中(金属插塞)与前述实施例中(接触窗结构的形成过程)中相似或相同结构的限定或描述，在本实施例中不再限定，具体请参考前述实施例相应部分的限定或描述。
本公开实施例虽然已以较佳实施例公开如上，但其并不是用来限定本公开实施例，任何本领域技术人员在不脱离本公开实施例的精神和范围内，都可以利用上述揭示的方法和技术内容对本公开实施例技术方案做出可能的变动和修改，因此，凡是未脱离本公开实施例技术方案的内容，依据本公开实施例的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本公开实施例技术方案的保护范围。

Claims (20)

  1. 一种接触窗结构的形成方法，包括：
    提供目标层；
    在所述目标层表面形成环形垫片，所述环形垫片中间设置有暴露出目标层部分表面的中央通孔；
    形成覆盖所述目标层和环形垫片的介质层；
    刻蚀所述介质层，在所述介质层中形成与中央通孔连通的刻蚀孔；
    去除所述环形垫片，形成接触窗结构。
  2. 如权利要求1所述的接触窗结构的形成方法，其中，所述环形垫片的形成过程包括：
    在所述目标层部分表面上形成柱状结构；
    在所述柱状结构的侧壁和顶部表面和部分目标层的表面形成垫片材料层；
    刻蚀去除所述柱状结构顶部表面以及部分目标层的表面的垫片材料层，在所述柱状结构的侧壁表面形成环形垫片；
    去除所述柱状结构。
  3. 如权利要求1所述的接触窗结构的形成方法，其中，所述环形垫片的形成过程包括：
    在所述目标层部分表面上形成掩膜材料层，所述掩膜材料层中形成有暴露出所述目标层部分表面的第一通孔；
    在所述第一通孔的侧壁和底部表面以及所述掩膜材料层的表面形成垫片材料层；
    刻蚀去除所述掩膜材料层的表面以及第一通孔底部表面的垫片材料层，在所述第一通孔的侧壁表面形成环形垫片。
  4. 如权利要求3所述的接触窗结构的形成方法，其中，在形成所述环形垫片后，去除所述掩膜材料层，在所述目标层和环形垫片上形成介质层，或者在形成所述环形垫片后，保留所述掩膜材料层，在所述掩膜材料层上形成介质层。
  5. 如权利要求1所述的接触窗结构的形成方法，其中，形成所述介质层时，所述形成的介质层完全填充所述环形垫片中间的中央通孔。
  6. 如权利要求1所述的接触窗结构的形成方法，其中，形成所述介质层时，所述 介质层部分填充或者不填充所述中央通孔，在所述环形垫片之间形成空气隙。
  7. 如权利要求1所述的接触窗结构的形成方法，其中，在形成所述介质层之前，在所述环形垫片中间的中央通孔中填充牺牲层，在刻蚀介质层形成刻蚀孔时，对所述牺牲层的刻蚀速率大于对所述介质层的刻蚀速率。
  8. 如权利要求1所述的接触窗结构的形成方法，其中，所述环形垫片的厚度为所述中央通孔尺寸的3倍以上。
  9. 如权利要求1所述的接触窗结构的形成方法，其中，在形成接触窗的过程中，所述目标层有部分被刻蚀掉。
  10. 如权利要求1所述的接触窗结构的形成方法，其中，提供基底，所述目标层形成于基底中，所述基底露出所述目标层的表面。
  11. 一种金属插塞的形成方法，包括：
    采用权利要求1-10任一项所述的方法形成接触窗结构；
    在所述接触窗结构中填充金属，形成金属插塞。
  12. 一种接触窗结构，包括：
    目标层；
    位于目标层上的介质层；
    位于介质层中的接触窗结构，所述接触窗结构包括连通的刻蚀孔和中央通孔，所述刻蚀孔位于中央通孔上方，所述中央通孔暴露出目标层的部分表面，且所述中央通孔的尺寸大于所述刻蚀孔底部的尺寸。
  13. 如权利要求12所述的接触窗结构，其中，还包括基底；所述目标层位于基底中，所述基底露出所述目标层的表面。
  14. 一种半导体结构，包括：
    目标层；
    位于所述目标层表面的环形垫片，所述环形垫片中间设置有暴露出目标层部分表面的中央通孔；
    覆盖所述目标层和环形垫片的介质层；
    位于所述介质层中与中央通孔连通的刻蚀孔。
  15. 如权利要求14所述的半导体结构，其中，所述环形垫片的厚度为所述中央通孔尺寸的3倍以上。
  16. 如权利要求14所述的半导体结构，其中，所述介质层的材料与所述环形垫片的 材料不相同。
  17. 如权利要求14所述的半导体结构，其中，所述环形垫片的形状为圆环形、椭圆形和长方形中的一种。
  18. 如权利要求14所述的半导体结构，其中，所述刻蚀孔顶部的尺寸小于或等于底部的尺寸。
  19. 一种金属插塞，包括：
    目标层；
    位于目标层上的介质层；
    位于介质层中的接触窗结构，所述接触窗结构包括连通的刻蚀孔和中央通孔，所述刻蚀孔位于中央通孔上方，所述中央通孔暴露出目标层的部分表面，且所述中央通孔的尺寸大于所述刻蚀孔底部的尺寸；
    填充所述接触窗结构的金属插塞。
  20. 如权利要求19所述的金属插塞，其中，还包括基底；所述目标层位于基底中，所述基底露出所述目标层的表面。
PCT/CN2021/099873 2020-09-22 2021-06-11 接触窗结构、金属插塞及其形成方法、半导体结构 Ceased WO2022062485A1 (zh)

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