WO2022062717A1 - 半导体结构形成方法以及半导体结构 - Google Patents

半导体结构形成方法以及半导体结构 Download PDF

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Publication number
WO2022062717A1
WO2022062717A1 PCT/CN2021/110982 CN2021110982W WO2022062717A1 WO 2022062717 A1 WO2022062717 A1 WO 2022062717A1 CN 2021110982 W CN2021110982 W CN 2021110982W WO 2022062717 A1 WO2022062717 A1 WO 2022062717A1
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Prior art keywords
layer
conductive
contact
height
forming
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English (en)
French (fr)
Inventor
卢经文
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to EP21871094.5A priority Critical patent/EP4195253A4/en
Publication of WO2022062717A1 publication Critical patent/WO2022062717A1/zh
Priority to US17/844,242 priority patent/US12557271B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a method for forming a semiconductor structure and a semiconductor structure.
  • the electrical connection between the transistor and the capacitor in the Dynamic Random Access Memory (DRAM) needs to be realized by depositing a capacitive contact structure, and the resistance of the capacitive contact structure formed by the deposition affects the current between the transistor and the capacitor. , thereby affecting the electrical conductivity of the device.
  • DRAM Dynamic Random Access Memory
  • the current method for forming the capacitive contact structure cannot effectively reduce the resistance of the formed capacitive contact structure, thereby affecting the conductivity of the formed dynamic random access memory.
  • An embodiment of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, on which a discretely arranged bit line structure and a dielectric layer are formed, and an extending direction of the dielectric layer intersects an extending direction of the bit line structure, The bit line structure and the dielectric layer enclose discrete capacitor contact openings; a first conductive layer filling the capacitor contact openings is formed, and the height of the top surface of the first conductive layer is lower than the height of the top surface of the bit line structure; the first conductive layer is formed on the top of the first conductive layer The conductive contact layer on the surface, the thickness of the first part and/or the second part of the conductive contact layer is greater than the thickness of the third part; the first part is the contact part between the conductive contact layer and the bit line structure, and the second part is the conductive contact layer With the contact part of the dielectric layer, the first part, the second part and the third part together form a conductive contact layer; form a separate second conductive layer that is
  • An embodiment of the present application further provides a semiconductor structure, including: a semiconductor substrate, a bit line structure and a dielectric layer are provided on the semiconductor substrate, an extension direction of the dielectric layer intersects with an extension direction of the bit line structure, and the bit line structure and the dielectric layer are surrounded by Discrete capacitor contact openings; a first conductive layer, located at the bottom of the capacitor contact opening, the height of the top surface of the first conductive layer is lower than the height of the top surface of the bit line structure; the conductive contact layer, located on the top surface of the first conductive layer, the conductive contact layer The thickness of the first part and/or the second part is greater than the thickness of the third part, wherein the first part is the contact part of the conductive contact layer and the bit line structure, the second part is the contact part of the conductive contact layer and the dielectric layer, The first part, the second part and the third part together form a conductive contact layer; the second conductive layer is electrically connected to the conductive contact layer and used to adjust the arrangement of the capaci
  • 1 to 22 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure provided by an embodiment of the present application.
  • the method for forming the capacitive contact structure in the related art cannot effectively reduce the resistance of the formed capacitive contact structure, thereby affecting the conductivity of the formed dynamic random access memory.
  • an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, on which a discretely arranged bit line structure and a dielectric layer are formed, and the extension direction of the dielectric layer is related to the bit line structure.
  • the extension direction of the first conductive layer intersects, and the bit line structure and the dielectric layer enclose a discrete capacitor contact opening; a first conductive layer is formed to fill the capacitor contact opening, and the height of the top surface of the first conductive layer is lower than the height of the top surface of the bit line structure;
  • the conductive contact layer on the top surface of the first conductive layer, the thickness of the first part and/or the second part of the conductive contact layer is greater than the thickness of the third part;
  • the first part is the contact part between the conductive contact layer and the bit line structure, the second part
  • the part is the contact part between the conductive contact layer and the dielectric layer, and the first part, the second part and the third part together constitute the conductive contact layer; a separate second conductive layer electrically connected to the conductive contact layer is formed, and the second conductive layer is used for Adjust the arrangement of the capacitor contact structures formed by filling the capacitor contact openings.
  • FIGS. 1 to 22 are schematic structural diagrams corresponding to each step of the method for forming a semiconductor structure provided by the embodiment of the present application, and the method for forming the semiconductor structure in the embodiment of the present application will be described in detail below.
  • a semiconductor substrate 101 is provided, on which a discretely arranged bit line structure 102 and a dielectric layer 103 are formed, and the extension direction of the dielectric layer 103 intersects with the extension direction of the bit line structure 102 , and the bit line structure 102 and The dielectric layer encloses discrete capacitor contact openings 104 .
  • the semiconductor substrate 101 includes structures such as buried word lines, shallow trench isolation structures, and active regions 111 .
  • the bit line structure 102 includes a bottom dielectric layer (not shown), a bit line contact layer 112 , a metal layer 122 and a top dielectric layer 132 which are stacked in sequence.
  • the material of the bit line contact layer 112 includes tungsten or polysilicon; the material of the bottom dielectric layer (not shown) and the top dielectric layer 135 includes silicon nitride, silicon dioxide or silicon oxynitride; the metal layer 122 can be a conductive material or It is composed of a variety of conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and tungsten composites.
  • the material of the dielectric layer 103 includes silicon nitride, silicon dioxide or silicon oxynitride. In the embodiment of the present application, the material of the dielectric layer 103 may be the same as the material of the top dielectric layer 132 .
  • the top surface and sidewalls of the bit line structure 102 are also covered with a protection structure, and the protection structure is used to electrically isolate the bit line structure 102 from the capacitor contact structure formed subsequently.
  • the protection structure is a stacked layer structure formed in sequence, and the stacked layer structure includes a top dielectric layer 132, a second dielectric layer 142 and a third dielectric layer 152 that are sequentially formed on the sidewalls of the bit line structure, wherein
  • the material of the third dielectric layer 152 and the material of the top dielectric layer 132 may be the same, and the material of the second dielectric layer 142 and the material of the top dielectric layer 132 may be different.
  • the protection structure is realized by means of a stacked structure, which has good electrical isolation and is used to reduce the parasitic resistance between the bit line structure 102 and the subsequently formed capacitive contact structure.
  • the area surrounded by the adjacent bit line structure 102 and the adjacent dielectric layer 103 is used as the capacitor contact opening 104 for the subsequent formation of the capacitor contact structure.
  • a first conductive layer 201 filling the capacitor contact opening 104 is formed, and the height of the top surface of the first conductive layer 201 is lower than that of the top surface of the bit line structure 102 .
  • a first conductive film (not shown) filling the capacitor contact opening 104 is formed, and the first conductive film (not shown) covers the bit line structure 102 and the dielectric layer 103 .
  • the first conductive film (not shown) is etched until discrete first conductive structures 211 are formed.
  • the first conductive film (not shown) is etched by chemical mechanical polishing until the top surfaces of the bit line structure 102 and the dielectric layer 103 are exposed to form the first conductive structure 211 .
  • the top of the first conductive film (not shown) is polished by chemical mechanical polishing to form a discrete first conductive structure 211 , which has a higher removal rate than the etching process and is beneficial to shorten the process cycle.
  • a first conductive layer 201 is formed by etching a partial height of the first conductive structure 211 .
  • the first conductive layer 201 is the bottom conductive layer of the subsequently formed capacitive contact structure, and is used for electrical connection with the active region 111 in the semiconductor substrate 101.
  • the material of the first conductive layer 201 includes doped polysilicon, polysilicon and other semiconductor conductive materials, In the embodiment of the present application, the material of the first conductive layer 201 is doped polysilicon.
  • the first conductive layer 201 is formed with trenches.
  • trenches 205 are formed in the first conductive layer 201 , and the trenches 205 are located between the first conductive layer 201 and the bit line.
  • the method of forming trench 205 is as follows:
  • a first sacrificial layer 202 is formed on the top and sidewalls of the bit line structure 102 , the top and sidewalls of the dielectric layer 103 , and the top of the first conductive layer 201 .
  • the material of the first sacrificial layer 202 is different from the material of the dielectric layer 103 and the first conductive layer 201, so as to facilitate the subsequent targeted etching and removal by wet etching technology.
  • the material of the first sacrificial layer 202 is silicon oxide.
  • a barrier layer 203 filling the capacitor contact opening 104 is formed.
  • the material of the barrier layer 203 may be photoresist.
  • the step of forming the barrier layer 203 includes: forming a barrier film (not shown) filling the capacitor contact opening 104 , and the height of the top surface of the barrier film (not shown) is higher than the height of the top surface of the first sacrificial layer 202 height, the barrier film (not shown) is etched to form a discrete barrier layer 203 .
  • the blocking film (not shown) is etched by chemical mechanical polishing to form the blocking layer 203 .
  • the top of the barrier film (not shown) is polished by chemical mechanical polishing to form a discrete barrier layer 203 , which has a higher removal rate than the etching process and is beneficial to shorten the process cycle.
  • the etching region is located on the top and sidewalls of the bit line structure 102 and the first sacrificial layer on the top and sidewalls of the dielectric layer 103 to form through holes (not shown), through A hole (not shown) exposes the first conductive layer 201 , a part of the first conductive layer 201 is etched based on a through hole (not shown), a trench 205 is formed, and the barrier layer 203 (refer to FIG. 4 ) and the remaining first conductive layer 205 are removed. sacrificial layer 202 (refer to FIG. 4 ).
  • a conductive contact layer 206 is formed on the top surface of the first conductive layer 201.
  • the thickness of the first part and/or the second part of the conductive contact layer 206 is greater than the thickness of the third part, and the first part is conductive
  • the contact part of the contact layer 206 and the bit line structure 102, the second part is the contact part of the conductive contact layer 206 and the dielectric layer 103, the third part is the middle part of the conductive contact layer 206, the first part, the second part and the third part
  • the conductive contact layer 206 with the edge thickness greater than the middle thickness is formed to increase the contact area between the first conductive layer 201 and the subsequently formed second conductive layer, thereby reducing the resistance of the subsequently formed capacitive contact structure .
  • the embodiments of the present application provide three different methods for forming the conductive contact layer 206, so as to form the conductive contact layer 206 with different shapes.
  • the conductive contact layer 206 formed by the first method does not need to form the trench 205 in the first conductive layer 201, that is, the first method is implemented on the basis of FIG. 3; and the second method and the third method are used to form the conductive contact
  • the layer 206 needs to form a trench 205 in the first conductive layer 201 , that is, the second method and the third method are implemented on the basis of FIG. 5 .
  • Method 1 Referring to FIGS. 6 to 8 , a conductive contact layer 206 is formed on the top of the first conductive layer 201 .
  • the height of the top surface of the conductive contact layer 206 is higher than that of the top surface of the bit line structure 102 .
  • Forming the conductive contact layer 206 includes the following steps:
  • a conductive contact film 216 is formed covering the top surface of the first conductive layer 201, the top surface and sidewalls of the bit line structure 102, and the top surface and sidewalls of the dielectric layer 103, and a second conductive contact film 216 is formed to fill the openings in the conductive contact film 216.
  • Sacrificial layer 207 is formed covering the top surface of the first conductive layer 201, the top surface and sidewalls of the bit line structure 102, and the top surface and sidewalls of the dielectric layer 103, and a second conductive contact film 216 is formed to fill the openings in the conductive contact film 216.
  • the conductive contact film 216 is used for the subsequent formation of the conductive contact layer 206 .
  • the material of the conductive contact film 216 is titanium nitride.
  • the second sacrificial layer 207 is used as a mask, a portion of the conductive contact film 216 is etched and removed to form the conductive contact layer 206 and the etched through hole exposing the conductive contact layer, and the bottom of the through hole is etched
  • the height of the surface is higher than the height of the top surface of the second sacrificial layer 207 , that is, the height of the first part and the height of the second part of the formed etched through hole are higher than the height of the third part.
  • the second sacrificial layer 207 is removed, and the morphology of the formed conductive contact layer 206 is shown in FIG. 8 .
  • Method 2 Referring to FIGS. 9-11 , a conductive contact layer 206 filling the trench 205 and covering the first conductive layer 201 is formed.
  • the height of the top surface of the conductive contact layer 206 is higher than the height of the top surface of the bit line structure 102 .
  • Forming the conductive contact layer 206 includes the following steps:
  • a conductive contact film 216 is formed covering the top surface of the first conductive layer 201, the top surface and sidewalls of the bit line structure 102, the top surface and sidewalls of the dielectric layer 103, and filling the trenches 205, forming a filling conductive contact film 216 The opening in the second sacrificial layer 207.
  • part of the conductive contact film 216 is etched and removed to form a conductive contact layer 206 and an etched through hole exposing the conductive contact layer, and the bottom of the through hole is etched
  • the height of the surface is higher than the height of the top surface of the second sacrificial layer 207 , that is, the height of the first part and the height of the second part of the formed etched through hole are higher than the height of the third part.
  • the second sacrificial layer 207 is removed, and the morphology of the formed conductive contact layer 206 is shown in FIG. 11 .
  • Method 3 Referring to FIGS. 9 and 12 , a conductive contact layer 206 filling the trench 205 and covering the first conductive layer 201 is formed.
  • the height of the top surface of the conductive contact layer 206 is higher than that of the top surface of the bit line structure 102 .
  • Forming the conductive contact layer 206 includes the following steps:
  • a conductive contact film 216 is formed covering the top surface of the first conductive layer 201, the top surface and sidewalls of the bit line structure 102, the top surface and sidewalls of the dielectric layer 103, and filling the trenches 205, forming a filling conductive contact film 216 The opening in the second sacrificial layer 207.
  • part of the conductive contact film 216 is etched and removed to form a conductive contact layer 206 and an etched through hole exposing the conductive contact layer, and the height of the bottom surface of the through hole is etched is flush with the height of the top surface of the second sacrificial layer 207 . That is, the height of the first part and the height of the second part of the formed etched through hole are higher than the height of the third part.
  • the second sacrificial layer 207 is removed, and the morphology of the formed conductive contact layer 206 is shown in FIG. 12 .
  • the first height is less than or equal to the third height, and/or the second height is less than or equal to the third height; wherein, the first height is a direction perpendicular to the semiconductor substrate, and the first height is The height of the part, the second height is the height of the second part in the direction perpendicular to the semiconductor substrate, and the third height is the height of the capacitor contact opening in the direction parallel to the semiconductor substrate.
  • a second conductive layer 301 electrically connected to the conductive contact layer 206 is formed.
  • the second conductive layer 301 is used to adjust the arrangement of the capacitive contact structure formed by filling the capacitive contact opening 104 .
  • the conductive contact layer 206 formed in FIG. 11 is used as an example for description, which does not constitute a limitation on the premise of the second conductive layer 301 .
  • the conductive contact layer 206 formed in FIG. 12 further forms a second conductive layer 301 .
  • the embodiment of the present application provides two methods for forming the second conductive layer 301 , and the following describes the two methods for forming the second conductive layer 301 in this embodiment in detail with reference to the accompanying drawings.
  • a second conductive film 311 that fills the capacitor contact opening 104 and covers the bit line structure 102 and the dielectric layer 103 is formed.
  • the second conductive film 311 is used for subsequent etching to form a second conductive layer.
  • Two conductive layers 301 , the second conductive layer 301 is used to electrically connect the first conductive layer 201 through the conductive contact layer 306 , so as to realize the electrical connection between the subsequently formed capacitive contact and the active region 111 .
  • the material of the second conductive film 311 is tungsten, a compound of tungsten, or the like.
  • the second conductive layer 301 is formed by patterning the second conductive film 311 .
  • a mask layer 312 and a patterned photoresist 303 are sequentially formed on the second conductive film 311 .
  • the mask layer 312 is etched and removed based on the patterned photoresist 303 until the top surface of the second conductive film 311 is exposed, and the patterned photoresist 303 is removed.
  • the second conductive film 311 is etched until a discrete second conductive layer 301 is formed, the second conductive layer 301 is partially located on the bit line structure 102 and in the capacitor contact opening 104 The height of the top surface of the second conductive layer is lower than the height of the top surface of the bit line structure 102 .
  • an insulating layer 304 filling the gap between the second conductive layers 301 is formed for the subsequent formation of a capacitor structure.
  • the first conductive layer 201 , the conductive contact layer 206 and the second conductive layer 301 together form the filling capacitor contact opening 104 of the capacitive contact structure.
  • a second conductive bottom layer 401 filling the capacitor contact opening 104 is formed, and the height of the top surface of the second conductive bottom layer 401 is flush with the height of the top surface of the bit line structure 102 .
  • the material of the second conductive bottom layer 401 is tungsten, a compound of tungsten, or the like.
  • a third sacrificial layer 402 is formed on the top surface of the second conductive bottom layer 401, the top surface of the bit line structure 102 and the top surface of the dielectric layer 103.
  • the material of the third sacrificial layer 402 may be photoresist .
  • the second sacrificial layer 402 is patterned to form dislocation contact openings, and the dislocation contact openings expose part of the second conductive bottom layer 401 .
  • a second conductive top layer 403 filling the dislocation contact openings is formed, the material of the second conductive top layer 403 is the same as that of the second conductive bottom layer 401 , and the second conductive top layer 403 and the second conductive bottom layer 401 together constitute the second conductive layer 301.
  • the third sacrificial layer 402 is etched and removed and an insulating layer 404 filling the gap between the second conductive top layers 403 is formed for the subsequent formation of the capacitor structure.
  • the conductive top layer 403 and the second conductive bottom layer 401 together constitute a capacitive contact structure filling the capacitive contact opening 104 .
  • the dislocation openings are formed first, and then the second conductive layer 301 is formed by filling the dislocation contact openings, so that the capacitor contact openings 104 are completely filled with conductive material, which further improves the conductivity of the subsequently formed capacitor contact structure.
  • the dislocation contact opening can be defined by forming the insulating layer 404 , thereby avoiding the formation of the second conductive opening. After the top layer 403 , the second sacrificial layer 402 needs to be removed to form the insulating layer 403 .
  • the second conductive bottom layer 401 on the top surface of the second conductive bottom layer 401 .
  • An insulating film (not shown) is formed on the top surface of the bit line structure 102 and the top surface of the dielectric layer 103, the insulating film (not shown) is patterned, and a dislocation contact opening is formed, and the dislocation contact opening exposes part of the second conductive bottom layer 401, and the remaining insulation 21 , a second conductive top layer 403 filling the dislocation contact openings is formed, and the second conductive top layer 403 and the second conductive bottom layer 401 together constitute the second conductive layer 301 .
  • the contact area between the first conductive layer and the second conductive layer is increased by forming the conductive contact layer with the edge thickness greater than the middle thickness, thereby reducing the formed contact area.
  • the resistance of the capacitive contact structure further enables the formed dynamic random access memory to have better conductivity.
  • Another embodiment of the present application provides a semiconductor structure.
  • the semiconductor structure includes: a semiconductor substrate 101 with a bit line structure 102 and a dielectric layer 103 on the semiconductor substrate 101, the extension direction of the dielectric layer 103 intersects with the extension direction of the bit line structure 102, and the bit line structure 102 and the dielectric layer 103 are enclosed and separated
  • the first conductive layer 201 is located at the bottom of the capacitor contact opening 104, and the height of the top surface of the first conductive layer 201 is lower than the height of the top surface of the bit line structure 102; the conductive contact layer 206 is located in the first conductive layer 201 On the top surface, the thickness of the first part and/or the second part of the conductive contact layer 206 is greater than the thickness of the third part, wherein the first part is the contact part of the conductive contact layer 206 and the bit line structure 102, and the second part is the conductive contact layer 206.
  • the contact part of the contact layer 206 and the dielectric layer 103, the third part is the middle part of the conductive contact layer 206, the first part, the second part and the third part together constitute the conductive contact layer 206; the second conductive layer 301, electrically connected to the conductive
  • the contact layer 206 is used to adjust the arrangement of the capacitor contact structure formed by filling the capacitor contact opening 104 .
  • the semiconductor substrate 101 includes structures such as buried word lines, shallow trench isolation structures, and active regions 111 .
  • the bit line structure 102 includes a bottom dielectric layer (not shown), a bit line contact layer 112 , a metal layer 122 and a top dielectric layer 132 which are stacked in sequence.
  • the material of the bit line contact layer 112 includes tungsten or polysilicon; the material of the bottom dielectric layer (not shown) and the top dielectric layer 135 includes silicon nitride, silicon dioxide or silicon oxynitride; the metal layer 122 can be a conductive material or It is composed of a variety of conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and tungsten composites.
  • the material of the dielectric layer 103 includes silicon nitride, silicon dioxide or silicon oxynitride. In the embodiment of the present application, the material of the dielectric layer 103 may be the same as the material of the top dielectric layer 132 .
  • the top surface and sidewalls of the bit line structure 102 are also covered with a protection structure, and the protection structure is used to electrically isolate the bit line structure 102 from the capacitor contact structure formed subsequently.
  • the protection structure is a stacked layer structure formed in sequence, and the stacked structure includes a top dielectric layer 132, a second dielectric layer 142 and a third dielectric layer 152 that are sequentially formed on the sidewalls of the bit line structure, wherein the first The material of the third dielectric layer 152 and the material of the top dielectric layer 132 may be the same, and the material of the second dielectric layer 142 and the material of the top dielectric layer 132 may be different.
  • the protection structure is realized by means of a stacked structure, which has good electrical isolation and is used to reduce the parasitic resistance between the bit line structure 102 and the subsequently formed capacitive contact structure.
  • the area surrounded by the adjacent bit line structure 102 and the adjacent dielectric layer 103 is used as the capacitor contact opening 104 for the subsequent formation of the capacitor contact structure.
  • the first conductive layer 201 is the bottom conductive layer of the subsequently formed capacitive contact structure, and is used for electrical connection with the active region 111 in the semiconductor substrate 101.
  • the material of the first conductive layer 201 includes doped polysilicon, polysilicon and other semiconductor conductive materials, In this embodiment, the material of the first conductive layer 201 is doped polysilicon.
  • the material of the conductive contact layer 206 is titanium nitride.
  • the first conductive layer 201 has a trench 205 , and the trench 205 is located at the contact position of the first conductive layer 201 and the bit line structure 102 , and the contact of the first conductive layer 201 and the dielectric layer 103 In place, the conductive contact layer 206 also serves to fill the trenches. That is, the top surfaces of the first, second, and third portions of the conductive contact layer 206 are at the same height, and the bottom surface of the first and/or second portion is lower than the bottom surface of the third portion.
  • the conductive contact layer 206 includes a body portion and an extension portion, the body portion is located on the top surface of the first conductive layer 201 , and the extension portion is located on the sidewall of the bit line structure 102 and/or the sidewall of the dielectric layer 103 , And the extension part is also located on the body part. That is, the bottom surfaces of the first, second and third parts of the conductive contact layer 206 are located at the same height, and the top surface height of the first part and/or the second part is higher than that of the top surface of the third part.
  • the first conductive layer 201 has a trench 205 , and the trench 205 is located at the contact position of the first conductive layer 201 and the bit line structure 102 , and the contact of the first conductive layer 201 and the dielectric layer 103 .
  • the conductive contact layer 206 is also used to fill the trench; the conductive contact layer 206 includes a body portion and an extension portion, the body portion is located on the top surface of the first conductive layer 201 , and the extension portion is located on the sidewall of the bit line structure 102 and/or the dielectric layer 103 the side wall, and the extension part is also located on the body part.
  • the height of the top surface of the first part and/or the second part of the conductive contact layer 206 is higher than the height of the top surface of the third part; the height of the bottom surface of the first part and/or the second part is lower than that of the bottom surface of the third part. high.
  • the first height is less than or equal to a third height, and/or the second height is less than or equal to the third height; wherein, the first height is a direction perpendicular to the semiconductor substrate, and the first height is The height of the part, the second height is the height of the second part in the direction perpendicular to the semiconductor substrate, and the third height is the height of the capacitor contact opening in the direction parallel to the semiconductor substrate.
  • the second conductive layer 301 includes a second conductive top layer 403 and a second conductive bottom layer 401 .
  • the second conductive bottom layer 401 is used to fill the capacitor contact opening 104
  • the second conductive top layer 403 is located on top of the second conductive bottom layer 401 and the bit line structure 102 , and is used to adjust the arrangement of the capacitor contact structure formed by filling the capacitor contact opening 104 .
  • the material of the second conductive layer 301 is tungsten, a compound of tungsten, or the like.
  • the edge thickness of the conductive contact layer is larger than the middle thickness, so as to increase the contact area between the first conductive layer and the second conductive layer, thereby reducing the formed contact area.
  • the resistance of the capacitive contact structure further enables the formed dynamic random access memory to have better conductivity.
  • the embodiments of the present application may be implemented in cooperation with the above embodiments.
  • the technical details mentioned in the above embodiments are still valid in the embodiments of the present application, and the technical effects that can be achieved in the above embodiments can also be realized in the embodiments of the present application. In order to reduce repetition, details are not repeated here.
  • the technical details mentioned in the embodiments of the present application can also be applied to the above-mentioned embodiments.
  • modules involved in the embodiments of this application are all logical modules.
  • a logical unit may be a physical unit, a part of a physical unit, or multiple A composite implementation of physical units.
  • the embodiments of the present application do not introduce units that are not closely related to solving the technical problems raised by the present application, but this does not mean that there are no other units in the embodiments of the present application. .

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

本申请实施例提供一种半导体结构形成方法以及半导体结构，其中，半导体结构形成方法包括：提供半导体基底，半导体基底上形成有分立排布的位线结构和介质层，且介质层的延伸方向与位线结构的延伸方向相交，位线结构与介质层围成分立的电容接触开口；形成填充电容接触开口的第一导电层，第一导电层顶部表面的高度低于位线结构顶部表面的高度；形成位于第一导电层顶部表面的导电接触层，导电接触层的第一部位和/或第二部位的厚度大于第三部位的厚度；形成电连接导电接触层的且分立的第二导电层，第二导电层用于调整填充电容接触开口形成的电容接触结构的排布方式。

Description

半导体结构形成方法以及半导体结构
相关申请的交叉引用
本申请基于申请号为202011012799.8、申请日为2020年09月23日、发明名称为“半导体结构形成方法以及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域，特别涉及一种半导体结构形成方法以及半导体结构。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)中晶体管与电容器之间的电连接需要通过沉积电容接触结构来实现，而沉积形成的电容接触结构的电阻大小影响晶体管与电容器之间的电流大小，从而影响器件的导电性能。
目前形成电容接触结构的方法无法有效降低形成的电容接触结构的电阻，从而导致影响形成的动态随机存取存储器的导电性能。
发明内容
本申请实施例提供了一种半导体结构形成方法，包括：提供半导体基底，半导体基底上形成有分立排布的位线结构和介质层，且介质层的延伸方向与位线结构的延伸方向相交，位线结构与介质层围成分立的电容接触开口；形成填充电容接触开口的第一导电层，第一导电层顶部表面的高度低于位线结构顶部表面的高度；形成位于第一导电层顶部表面的导电接触层，导电接触层的第一部位和/或第二部位的厚度大于第三部位的厚度；第一部位为导电接触层与位线结构的接触部位，第二部位为导电接触层与介质层的接触部位，第一部位、第二部位和第三部位共同构成导电接触层；形成电连接导电接触层的且分立的第二导电层，第二导电层用于调整填充电容接触开口形成的电容接触结构的排布方式。
本申请实施例还提供了一种半导体结构，包括：半导体基底，半导体基底上具有位线结构和介质层，介质层的延伸方向与位线结构的延伸方向相交，位线结构与介质层围成分立的电容接触开口；第一导电层，位于电容接触开口底部，第一导电层顶部表面的高度低于位线结构顶部表面的高度；导电接触层，位于第一导电层顶部表面，导电接触层的第一部位和/或第二部位的厚度大于第三部位的厚度，其中，第一部位为导电接触层与位线结构的接触部位，第二部位为导电接触层与介质层的接触部位，第一部位、第二部位和第三部位共同构成导电接触层；第二导电层，电连接导电接触层，用于调整填充电容接触开口形成的电容接触结构的排布方式。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申 明，附图中的图不构成比例限制。
图1～图22为本申请实施例提供的半导体结构形成方法各步骤对应的结构示意图。
具体实施方式
目前，相关技术中的形成电容接触结构的方法无法有效降低形成的电容接触结构的电阻，从而导致影响形成的动态随机存取存储器的导电性能。
为解决上述问题，本申请实施例提供了一种半导体结构形成方法，包括：提供半导体基底，半导体基底上形成有分立排布的位线结构和介质层，且介质层的延伸方向与位线结构的延伸方向相交，位线结构与介质层围成分立的电容接触开口；形成填充电容接触开口的第一导电层，第一导电层顶部表面的高度低于位线结构顶部表面的高度；形成位于第一导电层顶部表面的导电接触层，导电接触层的第一部位和/或第二部位的厚度大于第三部位的厚度；第一部位为导电接触层与位线结构的接触部位，第二部位为导电接触层与介质层的接触部位，第一部位、第二部位和第三部位共同构成导电接触层；形成电连接导电接触层的且分立的第二导电层，第二导电层用于调整填充电容接触开口形成的电容接触结构的排布方式。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1～图22为本申请实施例提供的半导体结构形成方法的各步骤对应的结构示意图，下面对本申请实施例的半导体结构形成方法进行详细说明。
参考图1，提供半导体基底101，半导体基底101上形成有分立排布的位线结构102和介质层103，且介质层103的延伸方向与位线结构102的延伸方向相交，位线结构102与介质层围成分立的电容接触开口104。
半导体基底101内包括埋入式字线、浅沟槽隔离结构、有源区111等结构。位线结构102包括依次堆叠设置的底层介质层(未图示)、位线接触层112、金属层122以及顶层介质层132。
位线接触层112的材料包括钨或多晶硅；底层介质层(未图示)和顶层介质层135的材料包括氮化硅、二氧化硅或氮氧化硅；金属层122可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等。
介质层103的材料包括氮化硅、二氧化硅或氮氧化硅，在本申请实施例中，介质层103的材料可以与顶层介质层132的材料相同。
本申请实施例中，位线结构102的顶部表面和侧壁还覆盖有保护结构，保护结构用于电隔离位线结构102与后续形成的电容接触结构。
在本申请实施例中，保护结构为依次形成的叠层结构，所述叠层结构包括依次形成在位线结构侧壁的顶层介质层132、第二介质层142和第三介质层152，其中第三介质层152的材料与顶层介质层132的材料可以相同，第二介质层142的材料与顶层介质层132的材料可以不同。保护结构通过叠层结构的方式实现，具有较好电隔离作用，且用于降低位线结构102与后续形成的电容接触结构之间的寄生电阻。
相邻位线结构102与相邻介质层103围成的区域作为电容接触开口104，用于后续形成电容接触结构。
参考图2和图3，形成填充电容接触开口104的第一导电层201，第一导电层201顶部表面的高度低于位线结构102顶部表面的高度。
在一些实施例中，形成填充电容接触开口104的第一导电膜(未图示)，第一导电膜(未图示)覆盖位线结构102和介质层103。
参考图2，刻蚀第一导电膜(未图示)，直至形成分立的第一导电结构211。
在一些实施例中，采用化学机械研磨的方式刻蚀第一导电膜(未图示)，直至暴露出位线结构102和介质层103的顶部表面，以形成第一导电结构211。采用化学机械研磨的方式对第一导电膜(未图示)的顶部进行打磨，形成分立的第一导电结构211，相对于刻蚀工艺具有较高的去除速率，有利于缩短工艺周期。
参考图3，刻蚀部分高度的第一导电结构211形成第一导电层201。
第一导电层201为后续形成的电容接触结构的底层导电层，用于与半导体基底101中的有源区111电连接，第一导电层201的材料包括掺杂多晶硅、多晶硅等半导体导电材料，本申请实施例中，第一导电层201的材料为掺杂多晶硅。
在本申请实施例中，形成的第一导电层201中具有沟槽，参考图4和图5，在第一导电层201中形成沟槽205，沟槽205位于第一导电层201与位线结构102的接触位置，以及第一导电层201与介质层103的接触位置。形成沟槽205的方法如下：
参考图4，形成位于位线结构102顶部和侧壁、介质层103顶部和侧壁以及第一导电层201顶部的第一牺牲层202。第一牺牲层202的材料与介质层103和第一导电层201的材料不同，以便于后续采用湿法刻蚀技术针对性刻蚀去除。在本申请实施例中，第一牺牲层202的材料为氧化硅。
形成填充电容接触开口104的阻挡层203，本申请实施例中，阻挡层203的材料可以为光刻胶。
在一些实施例中，形成阻挡层203的步骤包括：形成填充电容接触开口104的阻挡膜(未图示)，阻挡膜(未图示)顶部表面的高度高于第一牺牲层202顶部表面的高度，刻蚀阻挡膜(未图示)，形成分立的阻挡层203。
在一些实施例中，采用化学机械研磨的方式刻蚀阻挡膜(未图示)，以形成阻挡层203。采用化学机械研磨的方式对阻挡膜(未图示)的顶部进行打磨，形成分立的阻挡层203，相对于刻蚀工艺具有较高的去除速率，有利于缩短工艺周期。
参考图5，以阻挡层203为掩膜，刻蚀区域位于所示位线结构102顶部和侧壁以及介质层103顶部和侧壁的第一牺牲层，形成通孔(未图示)，通孔(未图示)暴露出第一导电层201，基于通孔(未图示)刻蚀部分第一导电层201，形成沟槽205，去除阻挡层203(参考图4)以及剩余的第一牺牲层202(参考图4)。
参考图6～图12，形成位于第一导电层201顶部表面的导电接触层206，导电接触层206的第一部位和/或第二部位的厚度大于第三部位的厚度，第一部位为导电接触层206与位线结构102的接触部位，第二部位为导电接触层206与介质层103的接触部位，第三部位为导电接触层206的中部部位，第一部位、第二部位和第三部位共同构成导电接触层206。本申请实施例通过形成边缘厚度大于中间厚度的导电接触层206，以增大第一导电层201和后续形成的第二导电层之间的接触面积，从而减小后续形成的电容接触结构的电阻。
本申请实施例给出了三种不同的导电接触层206的形成方法，以形成不同形貌的导电接触层206。
需要说明的是，采用方法一形成的导电接触层206无需在第一导电层201中形成沟槽205，即方法一是在图3的基础上实施的；而采用方法二和方法三形成导电接触层206需要在第一导电层201中形成沟槽205，即方法二和方法三是在图5的基础上 实施的。
方法一：参考图6～图8，形成位于第一导电层201顶部的导电接触层206，导电接触层206顶部表面的高度高于位线结构102顶部表面的高度。形成导电接触层206包括以下步骤：
参考图6，形成覆盖第一导电层201顶部表面、位线结构102顶部表面和侧壁、介质层103顶部表面和侧壁的导电接触膜216，形成填充导电接触膜216中的开口的第二牺牲层207。
导电接触膜216用于后续形成导电接触层206，本申请实施例中，导电接触膜216的材料为氮化钛。
参考图7和图8，以所述第二牺牲层207为掩膜，刻蚀去除部分导电接触膜216，形成导电接触层206以及暴露出导电接触层的刻蚀通孔，刻蚀通孔底部表面的高度高于第二牺牲层207顶部表面的高度，即形成的刻蚀通孔的第一部位的高度和第二部位的高度高于第三部位的高度。形成导电接触层206后，去除所述第二牺牲层207，形成的导电接触层206的形貌如图8中所示。
方法二：参考图9～图11，形成填充沟槽205且覆盖第一导电层201的导电接触层206，导电接触层206顶部表面的高度高于位线结构102顶部表面的高度。形成导电接触层206包括以下步骤：
参考图9，形成覆盖第一导电层201顶部表面、位线结构102顶部表面和侧壁、介质层103顶部表面和侧壁，且填充沟槽205的导电接触膜216，形成填充导电接触膜216中的开口的第二牺牲层207。
参考图10和图11，以所述第二牺牲层207为掩膜，刻蚀去除部分导电接触膜216，形成导电接触层206以及暴露出导电接触层的刻蚀通孔，刻蚀通孔底部表面的高度高于第二牺牲层207顶部表面的高度，即形成的刻蚀通孔的第一部位的高度和第二部位的高度高于第三部位的高度。形成导电接触层206后，去除所述第二牺牲层207，形成的导电接触层206的形貌如图11中所示。
方法三：参考图9和图12，形成填充沟槽205且覆盖第一导电层201的导电接触层206，导电接触层206顶部表面的高度高于位线结构102顶部表面的高度。形成导电接触层206包括以下步骤：
参考图9，形成覆盖第一导电层201顶部表面、位线结构102顶部表面和侧壁、介质层103顶部表面和侧壁，且填充沟槽205的导电接触膜216，形成填充导电接触膜216中的开口的第二牺牲层207。
参考图12，以所述第二牺牲层207为掩膜，刻蚀去除部分导电接触膜216，形成导电接触层206以及暴露出导电接触层的刻蚀通孔，刻蚀通孔底部表面的高度与第二牺牲层207顶部表面的高度齐平。即形成的刻蚀通孔的第一部位的高度和第二部位的高度高于第三部位的高度。形成导电接触层206后，去除所述第二牺牲层207，形成的导电接触层206的形貌如图12中所示。
本申请实施例中，第一高度小于等于第三高度，和/或第二高度小于等于所述第三高度；其中，所述第一高度为垂直于所述半导体基底方向上，所述第一部位的高度，所述第二高度为垂直于所述半导体基底方向上，所述第二部位的高度，所述第三高度为平行于所述半导体基底方向上，所述电容接触开口的高度。通过使得形成的导电接触层206的边缘部位的尺寸小于电容接触开口104的尺寸，进而使得后续形成的电容接触结构具有较高的稳定性。
参考图13～图22，形成电连接导电接触层206的第二导电层301，第二导电层301用于调整填充电容接触开口104形成的电容接触结构的排布方式。
需要说明的是，附图13～图22中以图11形成的导电接触层206为例进行描述，并不构成对第二导电层301前提的限定，在其他实施例中，可以基于图9和图12形成的导电接触层206进一步形成第二导电层301。
本申请实施例给出了两种形成第二导电层301的方法，以下结合附图对本实施例给出的两种形成第二导电层301的方法进行详细描述。
在一些实施例中，参考图13，形成填充电容接触开口104且覆盖位线结构102和介质层103的第二导电膜311，第二导电膜311用于后续刻蚀形成第二导电层，第二导电层301，第二导电层301用于通过导电接触层306电连接第一导电层201，以实现后续形成的电容接触与有源区111之间的电连接。本申请实施例中，第二导电膜311的材料为钨以及钨的复合物等。
参考图14～图16，图形化第二导电膜311形成第二导电层301。
参考图14，在第二导电膜311上依次形成掩膜层312和图形化的光刻胶303。
参考图15，基于图形化的光刻胶303刻蚀去除掩膜层312直至暴露出第二导电膜311的顶部表面，并且去除图形化的光刻胶303。
参考图16，基于所示掩膜层312，刻蚀第二导电膜311，直至形成分立的第二导电层301，第二导电层301部分位于位线结构102上，且位于电容接触开口104中的第二导电层顶部表面的高度低于位线结构102顶部表面的高度。
参考图17，形成填充第二导电层301之间间隙的绝缘层304，用于后续形成电容结构，此时第一导电层201、导电接触层206和第二导电层301共同构成填充电容接触开口104的电容接触结构。
在其它实施例中，参考图18，形成填充电容接触开口104的第二导电底层401，第二导电底层401顶部表面的高度与位线结构102顶部表面的高度齐平，本申请实施例中，第二导电底层401的材料为钨以及钨的复合物等。
参考图19，在第二导电底层401顶部表面，位线结构102顶部表面和介质层103顶部表面形成第三牺牲层402，本申请实施例中，第三牺牲层402的材料可以为光刻胶。图形化第二牺牲层402形成错位接触开口，错位接触开口暴露出部分第二导电底层401。
参考图20，形成填充错位接触开口的第二导电顶层403，第二导电顶层403的材料与第二导电底层401的材料相同，第二导电顶层403和第二导电底层401共同构成第二导电层301。
参考图21，刻蚀去除第三牺牲层402并形成填充第二导电顶层403之间间隙的绝缘层404，用于后续形成电容结构，此时第一导电层201、导电接触层206、第二导电顶层403和第二导电底层401共同构成填充电容接触开口104的电容接触结构。
先形成错位开口然后通过填充错位接触开口形成第二导电层301，使得电容接触开口104中被导电材料完全填充，进一步提高了后续形成的电容接触结构的导电性。
需要说明的是，由于形成第三牺牲层402的作用为定义错位接触开口的位置，在一个例子中，参考图22，可以通过形成绝缘层404来定义错位接触开口，从而避免在形成第二导电顶层403之后还需要去除第二牺牲层402再形成绝缘层403。
在一些实施例中，参考图22，在第二导电底层401顶部表面。位线结构102顶部表面和介质层103顶部表面形成绝缘膜(未图示)，图形化绝缘膜(未图示)，形成错位接触开口，错位接触开口暴露出部分第二导电底层401，剩余绝缘膜作为绝缘层403；参考图21，形成填充错位接触开口的第二导电顶层403，第二导电顶层403和第二导电底层401共同构成第二导电层301。
与相关技术相比，在垂直于半导体基底表面方向上，通过形成边缘厚度大于中间 厚度的导电接触层，以增大第一导电层和第二导电层之间的接触面积，从而减小形成的电容接触结构的电阻，进而使得形成的动态随机存取存储器具有较好的导电性能。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本申请实施例的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在本申请实施例的保护范围内。
本申请另一实施例提供一种半导体结构。
参考图8、图11、图12和图21，以下将结合附图对本申请实施例提供的半导体结构进行详细说明，与上述实施例相同或相应的部分，以下将不做赘述。
半导体结构，包括：半导体基底101，半导体基底101上具有位线结构102和介质层103，介质层103的延伸方向和位线结构102的延伸方向相交，位线结构102与介质层103围成分立的电容接触开口104；第一导电层201，位于电容接触开口104底部，第一导电层201顶部表面的高度低于位线结构102顶部表面的高度；导电接触层206，位于第一导电层201顶部表面，导电接触层206的第一部位和/或第二部位的厚度大于第三部位的厚度，其中，第一部位为导电接触层206与位线结构102的接触部位，第二部位为导电接触层206与介质层103的接触部位，第三部位为导电接触层206的中间部位，第一部位、第二部位和第三部位共同构成导电接触层206；第二导电层301，电连接导电接触层206，用于调整填充电容接触开口104形成的电容接触结构的排布方式。
半导体基底101内包括埋入式字线、浅沟槽隔离结构、有源区111等结构。位线结构102包括依次堆叠设置的底层介质层(未图示)、位线接触层112、金属层122以及顶层介质层132。
位线接触层112的材料包括钨或多晶硅；底层介质层(未图示)和顶层介质层135的材料包括氮化硅、二氧化硅或氮氧化硅；金属层122可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等。
介质层103的材料包括氮化硅、二氧化硅或氮氧化硅，在本申请实施例中，介质层103的材料可以与顶层介质层132的材料相同。
本申请实施例中，位线结构102的顶部表面和侧壁还覆盖有保护结构，保护结构用于电隔离位线结构102与后续形成的电容接触结构。
在一些实施例中，保护结构为依次形成的叠层结构，所述叠层结构包括依次形成在位线结构侧壁的顶层介质层132、第二介质层142和第三介质层152，其中第三介质层152的材料与顶层介质层132的材料可以相同，第二介质层142的材料与顶层介质层132的材料可以不同。保护结构通过叠层结构的方式实现，具有较好电隔离作用，且用于降低位线结构102与后续形成的电容接触结构之间的寄生电阻。
相邻位线结构102与相邻介质层103围成的区域作为电容接触开口104，用于后续形成电容接触结构。
第一导电层201为后续形成的电容接触结构的底层导电层，用于与半导体基底101中的有源区111电连接，第一导电层201的材料包括掺杂多晶硅、多晶硅等半导体导电材料，在本实施例中，第一导电层201的材料为掺杂多晶硅。
本申请实施例中，导电接触层206的材料为氮化钛。
在一些实施例中，参考图8，第一导电层201具有沟槽205，沟槽205位于第一导电层201与位线结构102的接触位置，以及第一导电层201和介质层103的接触位置，导电接触层206还用于填充沟槽。即导电接触层206的第一部位、第二部位和第三部位的顶部表面位于同一高度，第一部位和/或第二部位的底部表面高度低于第三部 位底部表面的高度。
在一些实施例中，参考图12，导电接触层206包括本体部和延伸部，本体部位于第一导电层201顶部表面，延伸部位于位线结构102侧壁和/或介质层103侧壁，且延伸部还位于本体部上。即导电接触层206的第一部位、第二部位和第三部位的底部表面位于同一高度，第一部位和/或第二部位的顶部表面高度高于第三部位顶部表面的高度。
在一些实施例中，参考图11，第一导电层201具有沟槽205，沟槽205位于第一导电层201与位线结构102的接触位置，以及第一导电层201和介质层103的接触位置，导电接触层206还用于填充沟槽；导电接触层206包括本体部和延伸部，本体部位于第一导电层201顶部表面，延伸部位于位线结构102侧壁和/或介质层103侧壁，且延伸部还位于本体部上。即导电接触层206的第一部位和/或第二部位的顶部表面高度高于第三部位顶部表面的高度；第一部位和/或第二部位的底部表面高度低于第三部位底部表面的高度。
在一些实施例中，第一高度小于等于第三高度，和/或第二高度小于等于所述第三高度；其中，所述第一高度为垂直于所述半导体基底方向上，所述第一部位的高度，所述第二高度为垂直于所述半导体基底方向上，所述第二部位的高度，所述第三高度为平行于所述半导体基底方向上，所述电容接触开口的高度。通过使得形成的导电接触层206的边缘部位的尺寸小于电容接触开口104的尺寸，进而使得后续形成的电容接触结构具有较高的稳定性。
参考图21，第二导电层301包括第二导电顶层403和第二导电底层401。第二导电底层401用于填充电容接触开口104，第二导电顶层403位于第二导电底层401和位线结构102顶部，用于调整填充电容接触开口104形成的电容接触结构的排布方式。
本申请实施例中，第二导电层301的材料为钨以及钨的复合物等。
相比于相关技术而言，在垂直于半导体基底表面方向上，导电接触层的边缘厚度大于中间厚度，以增大第一导电层和第二导电层之间的接触面积，从而减小形成的电容接触结构的电阻，进而使得形成的动态随机存取存储器具有较好的导电性能。
由于上述半导体结构形成方法的实施例与本申请半导体结构的实施例相类似，因此本申请实施例可与上述实施例互相配合实施。上述实施例中提到的技术细节在本申请实施例中依然有效，在上述实施例中所能达到的技术效果在本申请实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本申请实施例中提到的技术细节也可应用在上述实施例中。
值得一提的是，本申请实施例中所涉及到的各模块均为逻辑模块，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本申请实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本申请实施例中不存在其它的单元。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的一些实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请实施例的精神和范围。

Claims (19)

  1. 一种半导体结构形成方法，包括：
    提供半导体基底，所述半导体基底上形成有分立排布的位线结构和介质层，且所述介质层的延伸方向与所述位线结构的延伸方向相交，所述位线结构与所述介质层围成分立的电容接触开口；
    形成填充所述电容接触开口的第一导电层，所述第一导电层顶部表面的高度低于所述位线结构顶部表面的高度；
    形成位于第一导电层顶部表面的导电接触层，所述导电接触层的第一部位和/或第二部位的厚度大于第三部位的厚度；
    所述第一部位为所述导电接触层与所述位线结构的接触部位，所述第二部位为所述导电接触层与所述介质层的接触部位，所述第一部位、所述第二部位和所述第三部位共同构成所述导电接触层；
    形成电连接所述导电接触层的且分立的第二导电层，所述第二导电层用于调整填充所述电容接触开口形成的电容接触结构的排布方式。
  2. 根据权利要求1所述的半导体结构形成方法，其中，第一高度小于等于第三高度，和/或第二高度小于等于所述第三高度；其中，所述第一高度为垂直于所述半导体基底方向上所述第一部位的高度，所述第二高度为垂直于所述半导体基底方向上所述第二部位的高度，所述第三高度为平行于所述半导体基底方向上所述电容接触开口的高度。
  3. 根据权利要求1或2所述的半导体结构形成方法，其中，所述形成填充所述电容接触开口的第一导电层，包括：
    形成填充所述电容接触开口的第一导电膜；
    刻蚀所述第一导电膜，直至形成分立的第一导电结构；
    刻蚀部分高度的所述第一导电结构，形成所述第一导电层。
  4. 根据权利要求3所述的半导体结构形成方法，其中，采用化学机械研磨的方式刻蚀所述第一导电膜。
  5. 根据权利要求3所述的半导体结构形成方法，其中，所述形成位于第一导电层顶部表面的导电接触层，包括：
    形成覆盖所述第一导电层顶部表面、所述位线结构顶部表面和侧壁、所述介质层顶部表面和侧壁的导电接触膜；
    形成填充所述导电接触膜中的开口的第二牺牲层；
    以所述第二牺牲层为掩膜，刻蚀去除部分所述导电接触膜，形成所述导电接触层以及暴露出所述导电接触层的刻蚀通孔，所述刻蚀通孔底部表面的高度高于所述第二牺牲层底部表面的高度。
  6. 根据权利要求3所述的半导体结构形成方法，其中，所述形成位于第一导电层顶部表面的导电接触层，包括：
    在所述第一导电层中形成沟槽，所述沟槽位于所述第一导电层与所述位线结构的接触位置，以及所述第一导电层与所述介质层的接触位置；
    形成填充所述沟槽且覆盖所述第一导电层的导电接触层，所述导电接触层顶部表面的高度低于所述位线结构顶部表面的高度。
  7. 根据权利要求6所述的半导体结构形成方法，其中，所述在所述第一导电层中形成沟槽，包括：
    形成位于所述位线结构顶部和侧壁、所述介质层顶部和侧壁以及所述第一导电层 顶部的第一牺牲层；
    形成填充所述电容接触开口的阻挡层；
    以所述阻挡层为掩膜，刻蚀去除位于所述位线结构顶部和侧壁以及所述介质层顶部和侧壁的所述第一牺牲层，形成通孔，所述通孔暴露出所述第一导电层；
    基于所述通孔刻蚀部分所述第一导电层，形成所述沟槽；
    去除所述阻挡层以及剩余的所述第一牺牲层。
  8. 根据权利要求7所述的半导体结构形成方法，其中，所述形成填充所述第一牺牲层凹槽的阻挡层，包括：
    形成填充所述电容接触开口的阻挡膜，所述阻挡膜顶部表面的高度高于所述第一牺牲层顶部表面的高度；
    刻蚀所述阻挡膜，形成分立的所述阻挡层。
  9. 根据权利要求8所述的半导体结构形成方法，其中，采用化学机械研磨的方式刻蚀所述阻挡膜。
  10. 根据权利要求6至9任一项所述的半导体结构形成方法，其中，所述形成填充所述沟槽且覆盖所述第一导电层的导电接触层，包括：
    形成覆盖所述第一导电层顶部表面、所述位线结构顶部表面和侧壁、所述介质层顶部表面和侧壁且填充所述沟槽的导电接触膜；
    形成填充所述导电接触膜中的开口的第二牺牲层；
    以所述第二牺牲层为掩膜，刻蚀去除部分所述导电接触膜，形成所述导电接触层以及暴露出所述导电接触层的刻蚀通孔，所述刻蚀通孔底部表面的高度与所述第二牺牲层底部表面的高度齐平。
  11. 根据权利要求6至9任一项所述的半导体结构形成方法，其中，形成填充所述沟槽且覆盖所述第一导电层的导电接触层，包括以下步骤：
    形成覆盖所述第一导电层顶部表面、所述位线结构顶部表面和侧壁、所述介质层顶部表面和侧壁且填充所述沟槽的导电接触膜；
    形成填充所述导电接触膜中的开口的第二牺牲层；
    以所述第二牺牲层为掩膜，刻蚀去除部分所述导电接触膜，形成所述导电接触层以及暴露出所述导电接触层的刻蚀通孔，所述刻蚀通孔底部表面的高度高于所述第二牺牲层底部表面的高度。
  12. 根据权利要求3所述的半导体结构形成方法，其中，形成所述第二导电层，包括以下步骤：
    形成填充所述电容接触开口且覆盖所述位线结构和所述介质层的第二导电膜；
    图形化所述第二导电膜，形成所述第二导电层。
  13. 根据权利要求3所述的半导体结构形成方法，其中，所述形成电连接所述导电接触层的且分立的第二导电层，包括：
    形成填充所述电容接触开口的第二导电底层，所述第二导电底层顶部表面的高度与所述位线接触层顶部表面的高度齐平；
    在所述第二导电底层顶部表面、所述位线结构顶部表面和所述介质层顶部表面形成第三牺牲层；
    图形化所述第三牺牲层形成错位接触开口，所述错位接触开口暴露出部分所述第二导电底层；
    形成填充所述错位接触开口的第二导电顶层，所述第二导电底层和所述第二导电顶层共同构成所述第二导电层；
    刻蚀去除所述第三牺牲层。
  14. 根据权利要求3所述的半导体结构形成方法，其中，所述形成电连接所述导电接触层的且分立的所述第二导电层，包括：
    形成填充所述电容接触开口的第二导电底层，所述第二导电底层顶部表面的高度与所述位线接触层顶部表面的高度齐平；
    在所述第二导电底层顶部表面、所述位线结构顶部表面和所述介质层顶部表面形成绝缘膜；
    图形化所述绝缘膜形成错位接触开口，所述错位接触开口暴露出部分所述第二导电底层，剩余所述绝缘膜作为绝缘层；
    形成填充所述错位接触开口的第二导电顶层，所述第二导电底层和所述第二导电顶层共同构成所述第二导电层。
  15. 一种半导体结构，包括：
    半导体基底，所述半导体基底上具有位线结构和介质层，所述介质层的延伸方向与所述位线结构的延伸方向相交，所述位线结构与所述介质层围成分立的电容接触开口；
    第一导电层，位于所述电容接触开口底部，所述第一导电层顶部表面的高度低于所述位线结构顶部表面的高度；
    导电接触层，位于所述第一导电层顶部表面，所述导电接触层的第一部位和/或第二部位的厚度大于第三部位的厚度，其中，所述第一部位为所述导电接触层与所述位线结构的接触部位，所述第二部位为所述导电接触层与所述介质层的接触部位，所述第一部位、所述第二部位和所述第三部位共同构成所述导电接触层；
    第二导电层，电连接所述导电接触层，用于调整填充所述电容接触开口形成的电容接触结构的排布方式。
  16. 根据权利要求15所述的半导体结构，其中，第一高度小于等于第三高度，和/或第二高度小于等于所述第三高度；其中，所述第一高度为垂直于所述半导体基底方向上所述第一部位的高度，所述第二高度为垂直于所述半导体基底方向上所述第二部位的高度，所述第三高度为平行于所述半导体基底方向上所述电容接触开口的高度。
  17. 根据权利要求15所述的半导体结构，其中，所述导电接触层的所述第一部位和/或所述第二部位的厚度大于所述第三部位的厚度，包括：
    所述第一导电层具有沟槽，所述沟槽位于所述第一导电层与所述位线结构的接触位置，以及所述第一导电层与所述介质层的接触位置，所述导电接触层还用于填充所述沟槽。
  18. 根据权利要求15至17任一项所述的半导体结构，其中，所述导电接触层包括本体部和延伸部，所述本体部位于所述第一导电层顶部表面，所述延伸部位于所述位线结构侧壁和/或所述介质层侧壁，且所述延伸部还位于所述本体部上。
  19. 根据权利要求18所述的半导体结构，其中，所述第二导电层包括第二导电顶层和第二导电底层；
    所述第二导电底层用于填充所述电容接触开口；
    所述第二导电顶层位于所述第二导电底层和所述位线结构顶部，用于调整填充所述电容接触开口形成的电容接触结构的排布方式。
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