WO2022062974A1 - 氮化物外延结构和半导体器件 - Google Patents

氮化物外延结构和半导体器件 Download PDF

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WO2022062974A1
WO2022062974A1 PCT/CN2021/118342 CN2021118342W WO2022062974A1 WO 2022062974 A1 WO2022062974 A1 WO 2022062974A1 CN 2021118342 W CN2021118342 W CN 2021118342W WO 2022062974 A1 WO2022062974 A1 WO 2022062974A1
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layer
double
nitride
substrate
structures
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陈智斌
罗睿宏
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to JP2023519134A priority patent/JP7557056B2/ja
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Priority to US18/189,581 priority patent/US20230290742A1/en
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Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a nitride epitaxial structure and a semiconductor device.
  • Gallium nitride (GaN) materials are widely used in power electronic devices, radio frequency devices and optoelectronic devices due to their advantages of large band gap and high mobility. Among them, the most widely used is High Electron Mobility Transistor. , HEMT). Gallium nitride materials are usually epitaxially grown on silicon substrates. However, due to the large lattice mismatch and thermal expansion coefficient mismatch of more than 17% between GaN and silicon, there are huge stresses in GaN-on-silicon that can cause warpage in epitaxy, affecting GaN Epitaxial wafer uniformity and reliability. And as the substrate size increases, the effect of warpage becomes more pronounced.
  • HEMT High Electron Mobility Transistor
  • the existing technology mainly regulates stress through graded AlGaN structure and superlattice structure.
  • the graded AlGaN structure has the disadvantages of poor dynamic performance and poor crystal quality.
  • the stress control ability and crystal quality of the superlattice structure are better than those of the graded AlGaN structure, but it is difficult to balance the withstand voltage performance and crystal quality.
  • embodiments of the present application provide a nitride epitaxial structure and a semiconductor device.
  • a buffer layer with a specific structure between the substrate and the epitaxial layer, the lattice mismatch between the release substrate and the epitaxial layer can be effectively alleviated.
  • the stress generated by the thermal mismatch reduces the warpage during and after epitaxy, and improves the uniformity and reliability of the nitride epitaxial structure. It can also improve the crystal quality and withstand voltage performance of the epitaxial layer, thereby effectively improving the performance of semiconductor devices.
  • a first aspect of the embodiments of the present application provides a nitride epitaxial structure, including:
  • the nucleation layer is an aluminum nitride layer or a gallium nitride layer;
  • a buffer layer formed on the nucleation layer, the buffer layer includes K stacked Group III nitride bilayer structures, the K ⁇ 3; each of the bilayer structures includes a stacked upper layer and a lower layer , the forbidden band width of the upper layer material is greater than the forbidden band width of the lower layer material; the band gap difference of each of the two-layer structures is the difference between the forbidden band width of the upper layer material and the forbidden band width of the lower layer material value; the band gap differences of the K double-layer structures show a gradual trend as a whole along the thickness direction of the buffer layer;
  • An epitaxial layer is formed on the buffer layer, and the material of the epitaxial layer includes Group III nitride.
  • the nucleation layer can provide a nucleation center for the subsequent growth of the nitride epitaxial layer, relieve the lattice mismatch between the substrate and the epitaxial layer, and can also effectively prevent impurities brought by the substrate from causing the growth of the subsequent nitride epitaxial layer.
  • the buffer layer is arranged between the substrate and the epitaxial layer, which can effectively relieve the stress caused by lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, reduce the warpage during and after epitaxy, and improve nitride epitaxy. Structure uniformity and reliability.
  • the buffer layer is configured as a stack of a plurality of group III nitride double-layer structures with graded band gap differences, and the dynamic performance is better, which can effectively balance the crystal quality and withstand voltage performance, reduce the risk of leakage, and effectively improve the performance of semiconductor devices. performance.
  • the dynamic performance generally refers to the recovery ability of the transistor after increasing the electrical stress, which can be measured by indicators such as Dron (dynamic resistance).
  • the materials of the upper layer and the lower layer are respectively selected from one of GaN, AlN, InN, or a combination thereof, AlGaN, InGaN, InAlN, and InAlGaN.
  • the material composition of the upper layer/lower layer of the double-layer structure may be AlN/GaN, AlGaN/GaN, AlN/AlGaN or AlGaN/AlGaN.
  • the thickness of the lower layer is greater than twice the thickness of the upper layer.
  • Lattice relaxation can be effectively avoided by providing a relatively thick lower layer and a relatively thick upper layer.
  • the material is in a strained state, that is, the lattice constant of the upper layer material is stretched or compressed by the lower layer material and is consistent with the lower layer material, so that it can play an effective role; when the thickness of the upper layer is large. , the material will return to its own lattice constant, resulting in lattice relaxation.
  • the band gap difference of the K double-layer structures gradually decreases from the side of the nucleation layer to the side of the epitaxial layer.
  • the band gap difference is large, due to the large difference in lattice constant between the materials of the double-layer structure, it is beneficial to filter dislocations, but at the same time, due to the strong polarization effect, it is easy to cause leakage; on the contrary, when the band gap difference is relatively large Hour is good for reducing leakage, but not good for filtering dislocations.
  • the double-layer structure with a large band gap difference By arranging the double-layer structure with a large band gap difference on the side close to the nucleation layer, it is beneficial to annihilate dislocations in the early stage of epitaxy and reduce the influence of leakage;
  • the layer side is beneficial to reduce leakage and improve the withstand voltage performance.
  • the difference between the maximum band gap difference and the minimum band gap difference is greater than the Group III nitride with the largest forbidden band width and the smallest forbidden band width constituting the double-layer structure. 20% of the band gap difference of the Group III nitrides.
  • the K double-layer structures are composed of two kinds of Group III nitrides, GaN and AlN, and the average Al composition content in each of the double-layer structures is 5%-50%.
  • the average Al composition content refers to the average molar percentage of Al element in the Group III metal element in each bilayer structure. Controlling the Al content of each double-layer structure within an appropriate range can ensure that the buffer layer has better crystal quality.
  • the average content of Al components in each of the double-layer structures is the same.
  • the average Al component content of the K double-layer structures exhibits a gradual trend along the thickness direction of the buffer layer.
  • the average Al composition content of multiple bilayer structures is designed to be graded, which is beneficial to stress regulation.
  • any two adjacent double-layer structures may have different band gap differences, or some adjacent double-layer structures may have the same band gap difference.
  • the repetition period of the adjacent double-layered structures having the same band gap difference may be 1-10.
  • the thickness of each of the double-layer structures is set to be less than 100 nm.
  • the material of the epitaxial layer includes one or more of GaN, AlN, InN, AlGaN, InGaN, InAlN, and InAlGaN.
  • the thickness of the epitaxial layer is greater than or equal to 300 nm.
  • the thickness of the existing gallium nitride epitaxial layer is limited by stress and generally has a small thickness, while the nitride epitaxial wafer of the embodiment of the present application can eliminate the stress well, so it can theoretically achieve an infinite thickness.
  • the thickness of the epitaxial layer may be greater than or equal to 5 ⁇ m, and may also be greater than or equal to 10 ⁇ m.
  • the substrates include silicon substrates, sapphire substrates, silicon-on-insulator substrates (SOI substrates), gallium nitride substrates, gallium arsenide substrates, indium phosphide substrates, and nitride Aluminum substrate, silicon carbide substrate, quartz substrate or diamond substrate.
  • SOI substrates silicon-on-insulator substrates
  • gallium nitride substrates gallium arsenide substrates
  • indium phosphide substrates indium phosphide substrates
  • Aluminum substrate silicon carbide substrate, quartz substrate or diamond substrate.
  • the thickness of the nucleation layer is 10 nm-300 nm.
  • the nitride epitaxial structure further includes a transition layer disposed between the nucleation layer and the epitaxial layer, and the material of the transition layer is AlGaN.
  • the transition layer is made of the same material as the nucleation layer.
  • the thickness of the transition layer is 10 nm-300 nm.
  • the nitride epitaxial structure further includes other functional layers disposed on the epitaxial layer. type GaN layer, etc.
  • the embodiments of the present application further provide a semiconductor device including the nitride epitaxial structure described in the first aspect of the embodiments of the present application.
  • the semiconductor device may be a power device, a radio frequency device or an optoelectronic device. Specific examples are field effect transistors, light emitting diodes, laser diodes, and the like.
  • the nitride epitaxial structure provided by the embodiments of the present application by arranging a nucleation layer on the substrate, and arranging a buffer layer on the nucleation layer, it can effectively alleviate the lattice mismatch and thermal loss between the release substrate and the epitaxial layer. It can reduce the warpage during and after epitaxy, improve the uniformity and reliability of the nitride epitaxy structure, and then improve the performance of semiconductor devices.
  • the semiconductor device provided by the embodiment of the present application since the nitride epitaxial structure provided by the embodiment of the present application is adopted, a device with a large size and a thick nitride epitaxial layer can be obtained, which can effectively reduce the cost of the device and improve the performance of the device.
  • FIG. 1 is a schematic structural diagram of a nitride epitaxial structure provided in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a nitride epitaxial structure provided in another embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a nitride epitaxial structure provided in another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a buffer layer in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a nitride epitaxial structure provided in an embodiment of the present application.
  • FIG. 6 is a flow chart of the preparation process of the nitride epitaxial structure provided in the embodiment of the present application.
  • Example 7A is a TEM (Transmission Electron Microscope, transmission electron microscope) pattern of the double-layer structure on the side of the buffer layer close to the substrate in the nitride epitaxial structure of Example 2;
  • EDS Electronic Datapersive Spectroscopy, energy dispersive spectroscopy
  • 8A is a TEM spectrum of the double-layer structure on the side of the buffer layer close to the epitaxial layer in the nitride epitaxial structure of the second embodiment
  • 8B is an EDS spectrum of the double-layer structure on the side of the buffer layer close to the epitaxial layer in the nitride epitaxial structure of the second embodiment.
  • an embodiment of the present application provides a nitride epitaxial structure 100, including a substrate 10, a nucleation layer 20, a buffer layer 30, and an epitaxial layer 40, where the nucleation layer 20 is an AlN layer or a GaN layer, is formed on the substrate 10 , the buffer layer 30 is formed on the nucleation layer 20 , the epitaxial layer 40 is formed on the buffer layer 30 , and the material of the epitaxial layer 40 includes group III nitrides.
  • the buffer layer 30 includes K stacked group III nitride double-layer structures 200, K ⁇ 3; each double-layer structure 300 includes a lower layer 301 and an upper layer 302, and the forbidden band width of the material of the upper layer 302 is larger than that of the material of the lower layer 301
  • the band gap is formed by the band gap difference; the band gap difference of each double-layer structure 300 is the difference between the band gap width of the upper layer 302 material and the band gap width of the lower layer 301 material; the band gap difference of the K double-layer structures is along the The thickness direction of the buffer layer 30 shows a gradual trend as a whole.
  • the nitride epitaxial structure provided by the embodiment of the present application has good uniformity of the epitaxial layer and high crystal quality, and can be applied to a semiconductor device to improve the performance of the device.
  • the nitride epitaxial structure can have a nitride epitaxial layer with a large size of 6 inches or more and a thickness of 5 microns or more, so as to meet the needs of the large-size epitaxial structure.
  • the substrate 10 may be a silicon substrate, a sapphire substrate, a silicon-on-insulator substrate (SOI substrate), a gallium nitride substrate, a gallium arsenide substrate, an indium phosphide substrate, or an indium nitride substrate.
  • the aluminum substrate, the silicon carbide substrate, the quartz substrate or the diamond substrate can also be any known substrate which can be used for preparing the Group III nitride thin film.
  • the crystal orientation of the silicon substrate is not limited. For example, it can be a silicon substrate with a (111) crystal plane index, a silicon substrate with a (100) crystal plane index, or a silicon substrate with other crystal plane indexes. .
  • the nucleation layer 20 is a layer of aluminum nitride or gallium nitride thin film, the nucleation layer 20 completely covers the substrate 10, and on the one hand, the nucleation layer 20 can provide a nucleation center for the subsequent growth of the nitride epitaxial layer
  • the stress caused by the lattice mismatch between the substrate 10 and the epitaxial layer 40 can be alleviated, and at the same time, the influence of impurities brought by the substrate 10 on the growth of the subsequent nitride epitaxial layer can be effectively blocked, reducing the crystallinity. lattice defects, reduce the dislocation density, and improve the crystal quality of the nitride epitaxial layer.
  • the nucleation layer 20 is relatively thin and is single crystal or quasi-single crystal, so it can relieve the stress caused by the lattice mismatch between the substrate 10 and the epitaxial layer 40, and will not bring about the crystal quality of the subsequent nitride epitaxial layer. impact, and can effectively control costs.
  • the thickness of the nucleation layer 20 may be 10 nm-300 nm. In other embodiments of the present application, the thickness of the nucleation layer 20 may be 20 nm-200 nm. In other embodiments of the present application, the thickness of the nucleation layer 20 may also be 50 nm-150 nm.
  • the nucleation layer 20 may be prepared by a metal organic chemical vapor deposition method or a molecular beam epitaxy method.
  • Metal-organic Chemical Vapor Deposition is a chemical vapor deposition technology that utilizes the thermal decomposition reaction of organometallic compounds to grow thin films by vapor phase epitaxy.
  • Organic compounds of group elements and hydrides of V and VI elements are used as crystal growth source materials to grow III-V and II-VI compound films on the substrate by thermal decomposition reaction.
  • the method of metal organic chemical vapor deposition can improve the crystal quality of the subsequent epitaxial layer nitride.
  • the buffer layer 30 includes K stacked Group III nitride double-layer structures 300 .
  • the value of K may be 3-100. In other embodiments, the value of K may be 10-60. In some other embodiments, the value of K may also be 20-50.
  • the material of the upper layer 302 and the lower layer 301 can be selected from one of GaN, AlN, InN or a combination of AlGaN, InGaN, InAlN, and InAlGaN, respectively.
  • AlGaN is a combination of GaN and AlN Group III nitrides
  • InGaN is a combination of GaN and InN Group III nitrides
  • InAlN is a combination of AlN and InN Group III nitrides.
  • InAlGaN is a combination of three Group III nitrides of GaN, AlN, and InN.
  • the forbidden band width of GaN is 3.4 eV
  • the forbidden band width of AlN is 6.2 eV
  • the forbidden band width of InN is 0.7 eV.
  • the thickness of the buffer layer 30 can be set according to the withstand voltage level.
  • the buffer layer needs to be set to 2 ⁇ m-3 ⁇ m for the withstand voltage level of 100V, and the buffer layer needs to be set to more than 5 ⁇ m for the withstand voltage level of 600V.
  • the thickness of the buffer layer 30 is greater than 300 nm.
  • the thickness of each double-layer structure is less than 100 nm, and specifically, the thickness of each double-layer structure may be 10 nm-80 nm, 20 nm-60 nm.
  • a suitable thickness of the bilayer structure is beneficial to avoid the occurrence of relaxation phenomenon.
  • the thickness of the lower layer 301 is greater than twice the thickness of the upper layer 302 .
  • Lattice relaxation can be effectively avoided by providing a relatively thick lower layer and a relatively thick upper layer.
  • the material is in a strained state, that is, the lattice constant of the upper layer material is stretched or compressed by the lower layer material and is consistent with the lower layer material, so that the superlattice can be effectively played; while the thickness of the upper layer is in a state of strain.
  • the thicknesses of the upper layers may be equal, and the thicknesses of the lower layers may be equal.
  • the band gap difference of the K double-layer structures 300 gradually decreases from the side of the nucleation layer 200 to the side of the epitaxial layer 400 .
  • the band gap difference is large, due to the large difference in lattice constant between the materials of the double-layer structure, it is beneficial to filter dislocations, but at the same time, due to the strong polarization effect, it is easy to cause leakage; on the contrary, when the band gap difference is relatively large Hour is good for reducing leakage, but not good for filtering dislocations.
  • the double-layer structure with a large band gap difference By arranging the double-layer structure with a large band gap difference on the side close to the nucleation layer, it is beneficial to filter dislocations, and at the same time, because it is far away from the AlGaN barrier layer and the channel layer, the adverse effect caused by leakage is small;
  • the double-layer structure with smaller band gap difference is arranged on the side close to the epitaxial layer, which is beneficial to reduce the polarization effect and improve the withstand voltage performance.
  • the K double-layer structures 300 may also be arranged according to the band gap difference gradually increasing from the side of the nucleation layer 200 to the side of the epitaxial layer 400 as required.
  • the difference between the maximum band gap difference and the minimum band gap difference is greater than the group III nitride with the largest forbidden band width and the group III with the smallest forbidden band width constituting the double-layer structure. 20% of the difference in the band gap of the nitride.
  • the Group III nitrides constituting the double-layer structure include GaN and AlN, wherein the forbidden band width of GaN is 3.4eV, and the forbidden band width of AlN is 6.2eV, which constitutes a double-layer structure.
  • the 20% of the difference between the group III nitrides with the largest forbidden band width and the group III nitrides with the smallest forbidden band width of the layer structure is 20% ⁇ (6.2-3.4) eV.
  • the Group III nitrides constituting the double-layer structure include InN, GaN and AlN, wherein the forbidden band width of InN is 0.7 eV, and the forbidden band width of GaN is 3.4 eV,
  • the forbidden band width of AlN is 6.2eV
  • 20% of the difference between the forbidden band width of the group III nitride with the largest forbidden band width and the group III nitride with the smallest forbidden band width constituting the double-layer structure is 20% ⁇ (6.2-0.7) eV.
  • the K double-layer structures 200 are composed of two kinds of Group III nitrides, GaN and AlN, and the composition of the upper layer/lower layer of the double-layer structure can be expressed as Al x Ga 1-x N/A y Ga 1- y N (0 ⁇ x ⁇ 1, y>0).
  • the bilayer structure of this composition due to the gradual change of the band gap difference, can be equivalent to the gradual change of the Al composition content difference. Since the change trend of the band gap is approximately linear with the content of Al composition in AlGaN, that is, the higher the content of Al in AlGaN, the larger the band gap, so the gradual trend of the band gap difference of the double-layer structure can be equivalent to that of the double-layer structure.
  • the Al component content in this application refers to the molar percentage of Al element in the Group III metal element.
  • its forbidden band width can be approximately equal to [6.2x+(1-x)3.4]eV. Therefore, by controlling the Al composition content of the upper layer and the lower layer in each bilayer structure, the Al composition content difference of the bilayer structure shows a gradual trend, and the band gap difference of the K bilayer structures can be gradually changed. For example, as shown in FIGS.
  • the K double-layer structures 200 include a first double-layer structure Al x1 Ga 1-x1 N/Al y1 Ga 1-y1 N, a second double-layer structure Al x2 Ga 1-x2 N/Al y2 Ga 1-y2 N, the third double-layer structure Al x3 Ga 1-x3 N/Al y3 Ga 1-y3 N... and the K-th double-layer structure Al xk Ga 1-xk N/Al yk Ga 1 -yk N.
  • any two adjacent double-layer structures have different band gap differences.
  • any two adjacent double-layer structures have different compositions.
  • some adjacent double-layer structures may also have the same band gap difference.
  • the repetition period of the adjacent double-layered structures having the same band gap difference may be 1-10.
  • the repetition period of the double-layer structure with different band gaps can be the same or different.
  • the K double-layer structures are composed of two kinds of Group III nitrides, GaN and AlN, and the average Al composition content in each double-layer structure may be 5%-50%.
  • the average Al content in each bilayer structure is 8%-38%.
  • the average Al content in each bilayer structure is 15%-30%.
  • the average Al content in each Group III nitride bilayer structure is 20%-25%.
  • the average Al composition content refers to the average molar percentage of Al element in the Group III metal element in each bilayer structure. Controlling the average Al content of each double-layer structure within a suitable range can ensure that the buffer layer has better crystal quality.
  • the average Al composition content in each bilayer structure can be expressed as [( Tup ⁇ x+ Tdown ⁇ y)/(T (up + Tdown )] ⁇ 100%, where Tup and Tdown represent the thicknesses of the upper and lower layers of the double-layer structure, respectively, and x and y represent the Al content of the upper and lower layers, respectively.
  • the average content of Al composition in each double-layer structure is the same.
  • the average Al component content of the K double-layer structures has a gradual trend along the thickness direction of the buffer layer.
  • the average Al composition content of multiple bilayer structures is designed to be graded, which is beneficial to stress regulation.
  • the band gap differences of the K double-layer structures in the present application show a gradual trend as a whole along the thickness direction of the buffer layer, which may be a strict gradual increase or a gradual decrease change along the thickness direction of the buffer layer, or an overall There is a gradual increase or decrease, but there are a few special changes that are opposite to the overall gradual trend, for example, in the buffer layer with a gradually increasing band gap as a whole, there is a small amount of double-layer structure with a decreasing band gap difference.
  • the material of the epitaxial layer includes one or more of GaN, AlN, InN, AlGaN, InGaN, InAlN, and InAlGaN.
  • the material of the epitaxial layer 40 includes Group III nitride, and specifically, may be one or more of GaN, AlN, InN, AlGaN, InGaN, InAlN, and InAlGaN.
  • the thickness of the epitaxial layer 40 is greater than or equal to 300 nm.
  • the thickness of the existing gallium nitride epitaxial layer is generally small due to the stress, while the nitride epitaxial structure of the embodiment of the present application can eliminate the stress well, so it can be applied to the preparation of thick film epitaxial layer, and theoretically can be infinite thickness.
  • the thickness of the epitaxial layer may be greater than or equal to 5 ⁇ m, or greater than or equal to 10 ⁇ m, for example, 15 ⁇ m-100 ⁇ m.
  • the epitaxial layer 40 may completely cover the nucleation layer 20 or may partially cover the nucleation layer 20 .
  • different nitride epitaxial layers can be applied to different semiconductor devices, for example, GaN, AlGaN, and AlN can be applied to power devices, and In-containing nitride epitaxial layers can be applied to optoelectronic devices.
  • the epitaxial layer 40 may also be doped with other elements.
  • carbon may be doped to form a high resistance and improve the withstand voltage performance.
  • the nitride epitaxial structure 100 further includes a transition layer 50 disposed between the nucleation layer 30 and the epitaxial layer 40 , and the transition layer 50 may be an AlGaN layer.
  • the thickness of the transition layer may be 10 nm-300 nm.
  • the arrangement of the transition layer 50 is beneficial to control the stress of the epitaxial structure.
  • the nitride epitaxial structure 100 further includes other functional layers 60 disposed on the epitaxial layer 40 .
  • the specific structural composition of the other functional layers 60 can be set according to actual application requirements. In an embodiment of the present application, it may specifically include an AlN insertion layer 61 , an AlGaN barrier layer 62 , and a P-type GaN layer 63 that are sequentially arranged on the epitaxial layer 40 . In other embodiments, other functional layers 60 may also have other structural compositions.
  • an embodiment of the present application further provides a method for preparing a nitride epitaxial structure, including:
  • a nucleation layer is formed on the substrate, and the nucleation layer is an AlN layer or a GaN layer.
  • the nucleation layer 20 may be prepared on the substrate 10 by means of metal organic chemical vapor deposition or molecular beam epitaxy. Before preparing the nucleation layer 20, the substrate 10 may be subjected to conventional cleaning processes.
  • the nucleation layer 20 is prepared on the substrate 10 by means of metal organic chemical vapor deposition.
  • the substrate 10 may be placed in a metal organic chemical vapor deposition reaction chamber, and at 900- Under the temperature of 1100° C. and the pressure of 30-60 Torr, hydrogen and ammonia gas are introduced for 3-5 minutes to obtain the processed substrate 10, and then hydrogen, ammonia gas, and aluminum source or gallium source are introduced into the treated lining.
  • Aluminum nitride or gallium nitride is deposited on the bottom 10 to obtain the nucleation layer 20 .
  • the parameters in the deposition process are not limited to the above ranges.
  • Gallium sources include, but are not limited to, trimethylgallium and triethylgallium.
  • Aluminum sources include, but are not limited to, trimethylaluminum, triethylaluminum.
  • the buffer layer 30 may be prepared by metal organic chemical vapor deposition. Specifically, the substrate with the nucleation layer obtained after step S01 is placed in a metal organic chemical vapor deposition reaction chamber, at a temperature of 900-1100° C. and a pressure of 30-60 Torr, and then hydrogen and ammonia gas are introduced into it. , and the third main group metal source, and epitaxially grow on the buffer layer 30 to obtain a group III nitride to obtain the buffer layer 30 .
  • the third main group metal source is an organic compound containing the third main group metal element, such as trimethylgallium, triethylgallium, trimethylaluminum, triethylaluminum and the like.
  • the content of each Group III nitride in the buffer layer can be changed by changing the input amount of the third main group metal source, and nitride layers with different thicknesses can be obtained by controlling the deposition time.
  • the epitaxial layer 40 may be prepared by metal organic chemical vapor deposition. Specifically, the substrate 10 obtained after step S02 is placed in a metal organic chemical vapor deposition reaction chamber, and at a temperature of 900-1100° C. and a pressure of 30-60 Torr, hydrogen and ammonia gas are introduced for 3-5 minutes to obtain The treated substrate 10 is then fed with hydrogen gas, ammonia gas, and a third main group metal source, and epitaxially grown on the buffer layer 30 to obtain a group III nitride, and the epitaxial layer 40 is formed.
  • the Group III nitride can be, for example, one or more of GaN, AlN, InN, AlGaN, InGaN, InAlN, and InAlGaN.
  • the third main group metal source is an organic compound containing the third main group metal element, such as trimethylgallium, triethylgallium, trimethylaluminum, triethylaluminum and the like.
  • the above-mentioned preparation method may further include forming a transition layer 50 between the buffer layer 30 and the epitaxial layer 40 . That is, before step S03 , a transition layer 50 is prepared on the buffer layer 30 , and then the epitaxial layer 40 is grown on the transition layer 50 .
  • the material of the transition layer 50 can be an AlGaN layer.
  • This embodiment of the present application further provides a semiconductor device, including the nitride epitaxial structure provided in the above-mentioned embodiment of the present application.
  • the nitride epitaxial structure of the embodiment of the present application can be directly used as a part of the semiconductor device, or can be peeled off and applied to the semiconductor device middle.
  • the semiconductor device includes, but is not limited to, a power device (ie, a power electronic device), a radio frequency device, or an optoelectronic device.
  • the power device and the radio frequency device may be transistors, specifically, field effect transistors, such as high electron mobility transistors (High Electron Mobility Transistor, HEMT).
  • HEMT High Electron Mobility Transistor
  • the optoelectronic devices are, for example, Light Emitting Diode (LED) and Laser Diode (LD). Specifically, it can be a nitride-based light-emitting diode, or a nitride-based quantum well laser diode.
  • a nitride epitaxial structure includes a substrate, and a nucleation layer, a buffer layer, an epitaxial layer and other functional layers sequentially arranged on the substrate.
  • the substrate is made of Si, sapphire, GaN, SiC, diamond, SOI and other materials;
  • the nucleation layer is an AlN nucleation layer with a thickness of 50nm-400nm;
  • the buffer layer is a graded band gap structure layer, including 11 upper/lower layers is the double-layer structure of Al x Ga 1-x N/A y Ga 1-y N, the average Al content of each double-layer structure is 20%, the value and thickness of x, y in each double-layer structure
  • the upper and lower T are shown in Table 1.
  • the epitaxial layer is a GaN layer, which may include structures such as carbon-doped GaN or AlGaN, with a thickness of 100nm-3 ⁇ m.
  • Other functional layers may include an AlN insertion layer sequentially arranged on the epitaxial layer with a thickness of 1 nm; an AlGaN barrier layer with an Al composition range of 10%-30% and a thickness of 10-30nm; a p-GaN layer, with P-type impurities passing through Mg doping is achieved with thicknesses ranging from 30nm to 120nm.
  • the double-layer structures numbered 1-11 are stacked in sequence, the double-layer structure numbered 1 is arranged close to the epitaxial layer, and the double-layer structure numbered 11 is arranged close to the nucleation layer.
  • the cycle number 5 in Table 1 means that the double-layer structure of each serial number is repeated 5 times, that is, the repetition period of the double-layer structure with different band gap differences is the same, forming 11 groups of double-layer structures, each of which is 5 identical Double layer structure stacked. That is, the buffer layer includes 5 stacked Al 0.5 Ga 0.5 N/Al 0.17 Ga 0.83 N double-layer structures, 5 stacked Al 0.55 Ga 0.45 N/Al 0.165 Ga 0.835 N double-layer structures, and so on.
  • the buffer layer includes 51 double-layer structures whose upper/lower layers are AlxGa1 - xN / AlyGa1 -yN , and the values of x, y, and The upper layer thickness T and the lower layer thickness T are shown in Table 2.
  • the double-layer structures numbered 1-51 are stacked in sequence, the double-layer structure numbered 1 is arranged close to the epitaxial layer, and the double-layer structure numbered 51 is arranged close to the nucleation layer.
  • the cycle number 1 in Table 2 means that there is only one double-layer structure for each serial number. It can be known from Table 2 that in the nitride epitaxial structure of Example 2, the difference in the Al composition of the 51 double-layer structures of the buffer layer gradually decreases from the side of the nucleation layer to the side of the epitaxial layer, that is, 51 double-layer structures. The band gap difference of the layer structure gradually decreases from the side of the nucleation layer to the side of the epitaxial layer.
  • Example 2 the average Al content of each double-layer structure in Example 2 is the same, and both are 20%.
  • the band gap difference gradient pitch of the buffer layer of the second embodiment is smaller, which can better adjust the stress between the substrate and the epitaxial layer.
  • FIG. 7A is a TEM spectrum of the double-layer structure of the buffer layer near the substrate side in the nitride epitaxial structure of the second embodiment
  • FIG. 7B is the double-layer structure of the buffer layer near the substrate side in the nitride epitaxial structure of the second embodiment.
  • the double-layer structure in FIG. 7B corresponds to the three double-layer structures with serial numbers 49-51 in Table 2. It can be known from FIG. 7A and FIG. 7B that the Al group in the upper layer with the larger band gap in the double-layer structure near the substrate side The score is close to 100% and tends to decrease toward the side away from the substrate.
  • FIG. 8A is a TEM spectrum of the double-layer structure of the buffer layer near the epitaxial layer in the nitride epitaxial structure of the second embodiment
  • FIG. 8B is the double-layer structure of the buffer layer near the epitaxial layer in the nitride epitaxial structure of the second embodiment.
  • the double-layer structure in Fig. 8B corresponds to the three double-layer structures numbered 1-3 in Table 2. Comparing Fig. 7B and Fig. 8B, it can be seen that the difference in Al content of the double-layer structure near the substrate side is higher than that near the epitaxy The difference in the Al content of the bilayer structure on the layer side is large.
  • the buffer layer includes 11 groups of double-layer structures in which the upper/lower layers are AlxGa1 - xN / AlyGa1 -yN , and the values of x, y, and The upper layer thickness T and the lower layer thickness T are shown in Table 3.
  • the double-layer structures numbered 1-11 are stacked in sequence, the double-layer structure numbered 1 is arranged close to the epitaxial layer, and the double-layer structure numbered 11 is arranged close to the nucleation layer.
  • the cycle number 5 in Table 1 means that the double-layer structure of each serial number is repeated 5 times, that is, the repetition period of the double-layer structure with different band gap differences is the same, forming 11 groups of double-layer structures, each of which is 5 identical Double layer structure stacked. It can be known from Table 3 that in the nitride epitaxial structure of Example 3, the difference in the Al composition content of the 11 double-layer structures of the buffer layer gradually decreases from the nucleation layer side to the epitaxial layer side, that is, 11 double-layer structures.
  • the band gap difference of the layer structure gradually decreases from the side of the nucleation layer to the side of the epitaxial layer.
  • the average Al composition content of the 11 groups of double-layer structures in Example 3 also gradually decreases from the side of the nucleation layer to the side of the epitaxial layer.

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Abstract

本申请实施例提供一种氮化物外延结构，包括：衬底；成核层，形成于衬底上，成核层为氮化铝层或氮化镓层；缓冲层，形成于成核层上，包括K个堆叠的第Ⅲ族氮化物双层结构，K≥3；每一双层结构均包括层叠的上层和下层，每一双层结构的带隙差为上层材质的禁带宽度与下层材质的禁带宽度的差值；K个双层结构的带隙差沿缓冲层的厚度方向整体呈渐变趋势；外延层，形成于缓冲层上，外延层的材质包括第Ⅲ族氮化物。通过设置具有多个带隙差渐变的双层结构的缓冲层，可有效缓解衬底与外延层的晶格失配，而且可以很好地平衡晶体质量与耐电压性能，从而有效提升半导体器件的性能。本申请实施例还提供了包含该氮化物外延结构的半导体器件。

Description

氮化物外延结构和半导体器件
本申请要求于2020年9月25日提交中国专利局、申请号为202011025013.6、申请名称为“氮化物外延结构和半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种氮化物外延结构和半导体器件。
背景技术
氮化镓(GaN)材料由于禁带宽度大、迁移率高等优势，被广泛用于电力电子器件、射频器件和光电器件中，其中，最广泛应用的是高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)。氮化镓材料通常是在硅衬底上外延生长得到。然而，由于GaN与硅之间存在超过17％的大晶格失配和热膨胀系数失配，因此在硅基氮化镓中会存在巨大应力，这些应力会导致外延中产生翘曲，从而影响GaN外延片的均匀性和可靠性。而且随着衬底尺寸的增大，翘曲的影响也越加显著。目前，现有技术主要通过渐变AlGaN结构和超晶格结构来调控应力。然而渐变AlGaN结构存在动态性能较差，且晶体质量不好的缺点。而超晶格结构的应力控制能力和晶体质量虽优于渐变AlGaN结构，但难以平衡耐电压性能和晶体质量。
发明内容
鉴于此，本申请实施例提供一种氮化物外延结构和半导体器件，通过在衬底与外延层之间设置特定结构的缓冲层，可有效缓解释放衬底和外延层之间由于晶格失配和热失配产生的应力，降低外延过程中和外延后翘曲，提升氮化物外延结构的均匀性和可靠性；还可以提高外延层晶体质量和耐电压性能，从而有效提升半导体器件的性能。
具体地，本申请实施例第一方面提供一种氮化物外延结构，包括：
衬底；
成核层，形成于所述衬底上，所述成核层为氮化铝层或氮化镓层；
缓冲层，形成于所述成核层上，所述缓冲层包括K个堆叠的第Ⅲ族氮化物双层结构，所述K≥3；每一所述双层结构均包括层叠的上层和下层，所述上层材质的禁带宽度大于所述下层材质的禁带宽度；每一所述双层结构的带隙差为所述上层材质的禁带宽度与所述下层材质的禁带宽度的差值；所述K个双层结构的带隙差沿所述缓冲层的厚度方向整体呈渐变趋势；
外延层，形成于所述缓冲层上，所述外延层的材质包括第Ⅲ族氮化物。
其中，成核层可为后续生长氮化物外延层提供成核中心，缓解衬底与外延层的晶格失配，同时还可以有效阻挡衬底带来的杂质对后续氮化物外延层的生长产生的影响，提高外延层的晶体质量。缓冲层设置在衬底与外延层之间，可以有效缓解释放衬底和外延层之间由于晶格失配和热失配产生的应力，降低外延过程中和外延后翘曲，提升氮化物外延结构的均匀性和可靠性。且缓冲层通过设置为多个渐变带隙差的第Ⅲ族氮化物双层结构的堆叠，动态性能较好，可以有效地平衡晶体质量与耐电压性能，降低漏电风险，从而有效提升半导体器件的性能。而且，通过在不同位置适应性地采用不同带隙差的双层结构可以同时兼顾过滤位错和提 升耐压性能的优势，根据实际需要找到两种性能的平衡。其中，动态性能一般指增加电应力后晶体管的恢复能力，可以用Dron(动态电阻)等指标衡量。
本申请实施方式中，每一双层结构中，所述上层和所述下层的材质分别选自GaN、AlN、InN或其组合AlGaN、InGaN、InAlN、InAlGaN中的一种。具体地，所述双层结构的上层/下层材质组成可为AlN/GaN、AlGaN/GaN、AlN/AlGaN或AlGaN/AlGaN。
本申请实施方式中，所述下层的厚度大于两倍所述上层的厚度。通过设置相对较厚的下层和相对较厚的上层可以有效避免晶格驰豫。对于异质外延，上层的厚度较小时，材料处于应变状态，即上层材料的晶格常数被下层材料拉伸或压缩后和下层材料保持一致，从而能够有效发挥作用；而上层的厚度较大时，材料会恢复到自身的晶格常数，产生晶格驰豫。
本申请实施方式中，所述K个双层结构的带隙差自所述成核层一侧向所述外延层一侧逐渐减小。当带隙差较大时，由于双层结构的材料之间的晶格常数差异较大，有利于过滤位错，但同时由于极化效应较强，容易导致漏电；相反，当带隙差较小时则有利于降低漏电，但不利于过滤位错。通过将带隙差较大的双层结构设置在靠近成核层一侧有利于在外延初期湮灭位错，并减小漏电的影响；而将带隙差较小的双层结构设置在靠近外延层一侧则有利于减小漏电，提升耐压性能。
本申请实施方式中，所述K个双层结构中，最大带隙差与最小带隙差的差值大于构成所述双层结构的禁带宽度最大的第Ⅲ族氮化物与禁带宽度最小的第Ⅲ族氮化物的禁带宽度差值的20％。通过将整个缓冲层的K个双层结构的最大带隙差与最小带隙差的差值控制在较适合的范围，可以更好地平衡调节晶体质量与耐电压性能。
本申请实施方式中，所述K个双层结构由GaN和AlN两种第Ⅲ族氮化物构成，每一所述双层结构中的平均Al组分含量为5％-50％。平均Al组分含量是指在每一双层结构中，Al元素占第III族金属元素的平均摩尔百分比。将每一双层结构的Al组分含量控制在适合的范围，可以保证缓冲层具有较好的晶体质量。
本申请实施方式中，每一所述双层结构中的平均Al组分含量相同。通过保持Al组分不变，可以使得在设计高温翘曲的预补偿时只需要考虑膜层厚度影响而不用考虑Al组分变化影响，简化参数设计。
本申请实施方式中，所述K个双层结构的平均Al组分含量沿所述缓冲层的厚度方向呈渐变趋势。将多个双层结构的平均Al组分含量设计成渐变，有利于应力调控。
本申请实施方式中，所述K个双层结构中，可以是任意相邻两个双层结构都具有不同带隙差，也可以是部分相邻的双层结构具有相同带隙差。其中，相邻层叠在一起的具有相同带隙差的双层结构的重复周期可以是1-10。
本申请实施方式中，为避免驰豫发生，每一所述双层结构的厚度设置在小于100nm。
本申请实施方式中，所述外延层的材质包括GaN、AlN、InN、AlGaN、InGaN、InAlN、InAlGaN中的一种或多种。
本申请实施方式中，所述外延层的厚度大于或等于300nm。现有氮化镓外延层的厚度受应力所限一般厚度较小，而本申请实施例的氮化物外延片可以很好地消除应力，因此理论上可以做到无限厚度。在本申请一些实施方式中，外延层的厚度可以是大于或等于5μm，也可以是大于或等于10μm。
本申请实施方式中，所述衬底包括硅衬底、蓝宝石衬底、绝缘体上硅衬底(SOI衬底)、氮化镓衬底、砷化镓衬底、磷化铟衬底、氮化铝衬底、碳化硅衬底、石英衬底或金刚石衬底。
本申请实施方式中，所述成核层的厚度为10nm-300nm。
本申请实施方式中，所述的氮化物外延结构还包括设置于所述成核层与所述外延层之间的过渡层，所述过渡层的材质为AlGaN。本申请实施方式中，所述过渡层与所述成核层的材质相同。本申请实施方式中，所述过渡层的厚度为10nm-300nm。
本申请实施方式中，所述的氮化物外延结构还包括设置于所述外延层上的其他功能层，其他功能层可以根据实际应用需要设置，具体可以是包括AlN插入层、AlGaN阻挡层、P型GaN层等。
第二方面，本申请实施例还提供了一种半导体器件，包括本申请实施例第一方面所述的氮化物外延结构。所述半导体器件可以是功率器件、射频器件或光电器件。具体例如为场效应晶体管、发光二极管、激光二极管等。
本申请实施例提供的氮化物外延结构，通过在衬底上设置成核层，并在成核层上设置缓冲层，能够有效缓解释放衬底和外延层之间由于晶格失配和热失配产生的应力，降低外延过程中和外延后翘曲，提升氮化物外延结构的均匀性和可靠性，进而提升半导体器件的性能。本申请实施例提供的半导体器件，由于采用本申请实施例提供的氮化物外延结构，可以获得大尺寸，厚氮化物外延层器件，可有效降低器件成本，提高器件性能。
附图说明
图1是本申请一实施方式中提供的氮化物外延结构的结构示意图；
图2是本申请另一实施方式中提供的氮化物外延结构的结构示意图；
图3是本申请又一实施方式中提供的氮化物外延结构的结构示意图；
图4是本申请一实施方式中缓冲层的结构示意图；
图5是本申请一实施方式中提供的氮化物外延结构的结构示意图；
图6是本申请实施方式中提供的氮化物外延结构的制备工艺流程图；
图7A为实施例二的氮化物外延结构中缓冲层靠近衬底一侧的双层结构的TEM(Transmission Electron Microscope,透射电子显微镜)图谱；
图7B为实施例二的氮化物外延结构中缓冲层靠近衬底一侧的双层结构的EDS(Energy Dispersive Spectroscopy，能量色散光谱)图谱；
图8A为实施例二的氮化物外延结构中缓冲层靠近外延层一侧的双层结构的TEM图谱；
图8B为实施例二的氮化物外延结构中缓冲层靠近外延层一侧的双层结构的EDS图谱。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例进行说明。
参见图1和图2，本申请实施例提供一种氮化物外延结构100，包括衬底10、成核层20、缓冲层30、以及外延层40，成核层20为AlN层或GaN层，形成于衬底10上，缓冲层30形成于成核层20上，外延层40形成于缓冲层30上，外延层40的材质包括第Ⅲ族氮化物。其中，缓冲层30包括K个堆叠的第Ⅲ族氮化物双层结构200，K≥3；每一双层结构300均包括下层301和上层302，上层302材质的禁带宽度大于下层301材质的禁带宽度，从而形成带隙差；每一双层结构300的带隙差为上层302材质的禁带宽度与下层301材质的禁带宽度的差值；K个双层结构的带隙差沿缓冲层30的厚度方向整体呈渐变趋势。本申请实施例提供的氮化物外延结构，外延层均匀性好、晶体质量高，可应用于半导体器件中，以提高器件性能。该氮化物外延结构可具有6英寸以上大尺寸、5微米及以上厚度的氮化物外延层，满足大尺寸外延结构需求。
需要说明的是，本申请的双层结构中的上层和下层，其中，“上”、“下”不代表具体的方位。本领域中，对于超晶格双层结构，一般将禁带宽度大的写上面，禁带宽度小的写下面，即使实际生长中两层顺序互换也不会在书写时换过来。
本申请实施方式中，衬底10可以是硅衬底、蓝宝石衬底、绝缘体上硅衬底(SOI衬底)、氮化镓衬底、砷化镓衬底、磷化铟衬底、氮化铝衬底、碳化硅衬底、石英衬底或金刚石衬底，还可以是现有已知的任意一种可用于制备第Ⅲ族氮化物薄膜的衬底。其中，硅衬底的晶体取向不限，例如可以是(111)晶面指数的硅衬底，也可以是(100)晶面指数的硅衬底，还可以是其他晶面指数的硅衬底。
本申请实施方式中，成核层20为一层氮化铝或氮化镓薄膜，成核层20完全覆盖衬底10，成核层20一方面可为后续生长氮化物外延层提供成核中心，另一方面可以缓解衬底10与外延层40之间由于晶格失配产生的应力，同时还可以有效阻挡衬底10带来的杂质给后续氮化物外延层的生长产生的影响，减少晶格缺陷，降低位错密度，提高氮化物外延层的晶体质量。另外，成核层20较薄，为单晶、准单晶，因此可缓解衬底10与外延层40之间晶格失配产生的应力，不会给后续氮化物外延层的晶体质量带来影响，还可以有效控制成本。本申请一些实施方式中，成核层20的厚度可以为10nm-300nm。本申请另一些实施方式中，成核层20的厚度可以为20nm-200nm。本申请其他一些实施方式中，成核层20的厚度也可以为50nm-150nm。
本申请实施方式中，成核层20可以是采用金属有机化学气相沉积的方式或分子束外延方式制备得到。其中，金属有机化学气相沉积(MOCVD,Metal-organic Chemical Vapor Deposition)是一种利用有机金属化合物热分解反应进行气相外延生长薄膜的化学气相沉积技术，具体地可将金属有机化合物以Ⅲ族、Ⅱ族元素的有机化合物和V、Ⅵ族元素的氢化物等作为晶体生长源材料，以热分解反应方式在衬底上生长Ⅲ-V族、Ⅱ-Ⅵ族化合物薄膜。其中，金属有机化学气相沉积的方式可以提升后续外延层氮化物的晶体质量。
本申请实施方式中，缓冲层30包括K个堆叠的第Ⅲ族氮化物双层结构300，在一些实施方式中，K的取值可以是3-100。在另一些实施方式中，K的取值可以是10-60。在其他一些实施方式中，K的取值还可以是20-50。每一双层结构中，上层302和下层301的材质可分别选自GaN、AlN、InN或其组合AlGaN、InGaN、InAlN、InAlGaN中的一种。其中，AlGaN是由GaN、AlN两种第Ⅲ族氮化物组合而成，InGaN是由GaN、InN两种第Ⅲ族氮化物组合而成，InAlN是由AlN、InN两种第Ⅲ族氮化物组合而成，InAlGaN是由GaN、AlN、InN三种第Ⅲ族氮化物组合而成。其中，GaN的禁带宽度为3.4eV，AlN的禁带宽度为6.2eV，InN的禁带宽度为0.7eV，具体地，双层结构300的上层/下层材质组成可以是AlN/GaN、AlGaN/GaN、AlN/AlGaN或AlGaN/AlGaN。
本申请实施方式中，缓冲层30的厚度可以根据耐压等级进行设置，如耐压等级100V一般缓冲层需要设置为2μm-3μm，耐压等级600V则缓冲层需要设置为5μm以上。本申请一些实施方式中，缓冲层30的厚度大于300nm。其中，每一双层结构的厚度小于100nm，具体地，每一双层结构的厚度可以是10nm-80nm，20nm-60nm。适合的双层结构厚度有利于避免驰豫现象的发生。每一双层结构300中，下层301的厚度大于两倍上层302的厚度。通过设置相对较厚的下层和相对较厚的上层可以有效避免晶格驰豫。对于异质外延，上层的厚度较小时，材料处于应变状态，即上层材料的晶格常数被下层材料拉伸或压缩后和下层材料保持一致，从而能够有效发挥超晶格作用；而上层的厚度较大时，材料会恢复到自身的晶格常数，产生晶格驰豫。K个双层结构300中，各上层的厚度可以是相等，各下层的厚度可以是相等。
本申请一些实施方式中，K个双层结构300的带隙差自成核层200一侧向外延层400一侧逐渐减小。当带隙差较大时，由于双层结构的材料之间的晶格常数差异较大，有利于过滤位错，但同时由于极化效应较强，容易导致漏电；相反，当带隙差较小时则有利于降低漏电，但不利于过滤位错。通过将带隙差较大的双层结构设置在靠近成核层一侧有利于过滤位错，同时由于其离AlGaN势垒层和沟道层较远，漏电造成的不利影响较小；而将带隙差较小的双层结构设置在靠近外延层一侧则有利于降低极化效应，提升耐压性能。在其他一些实施方式中，也可以是根据需要将K个双层结构300按照带隙差自成核层200一侧向外延层400一侧逐渐增大进行排布。
本申请实施方式中，K个双层结构中，最大带隙差与最小带隙差的差值大于构成双层结构的禁带宽度最大的第Ⅲ族氮化物与禁带宽度最小的第Ⅲ族氮化物的禁带宽度差值的20％。例如，在K个AlGaN/AlGaN双层结构中，构成双层结构的第Ⅲ族氮化物包括GaN和AlN，其中GaN的禁带宽度为3.4eV，AlN的禁带宽度为6.2eV，则构成双层结构的禁带宽度最大的第Ⅲ族氮化物与禁带宽度最小的第Ⅲ族氮化物的禁带宽度差值的20％即为20％×(6.2-3.4)eV。又例如，在K个InAlGaN/InAlGaN双层结构中，构成双层结构的第Ⅲ族氮化物包括InN、GaN和AlN，其中InN的禁带宽度为0.7eV，GaN的禁带宽度为3.4eV，AlN的禁带宽度为6.2eV，则构成双层结构的禁带宽度最大的第Ⅲ族氮化物与禁带宽度最小的第Ⅲ族氮化物的禁带宽度差值的20％即为20％×(6.2-0.7)eV。
本申请一些实施方式中，K个双层结构200由GaN和AlN两种第Ⅲ族氮化物构成，双层结构上层/下层的组成可表示为Al xGa 1-xN/Al yGa 1-yN(0<x≤1，y>0)。该组成的双层结构，由于带隙差的渐变趋势可等价于Al组分含量差值的渐变趋势。由于禁带宽度变化趋势与AlGaN中的Al组分含量近似为线性关系，即AlGaN中Al组分含量越高禁带宽度越大，因此双层结构的带隙差的渐变趋势可等价于双层结构的Al组分含量差值的渐变趋势。需要说明的是，本申请中Al组分含量是指Al元素占第III族金属元素的摩尔百分比。对于Al xGa 1-xN，其禁带宽度可近似等于[6.2x+(1-x)3.4]eV。因此，通过控制各双层结构中上层和下层的Al组分含量，使得双层结构的Al组分含量差值呈渐变趋势，即可实现K个双层结构的带隙差渐变。例如，如图2和图3所示，K个双层结构200包括第一双层结构Al x1Ga 1-x1N/Al y1Ga 1-y1N，第二双层结构Al x2Ga 1-x2N/Al y2Ga 1-y2N，第三双层结构Al x3Ga 1-x3N/Al y3Ga 1-y3N……和第K双层结构Al xkGa 1-xkN/Al ykGa 1-ykN。若由第一双层结构向第K双层结构带隙差逐渐减小，则x1-y1>x2-y2>x3-y3>…>xk-yk，即由第一双层结构向第K双层结构Al组分含量差值逐渐减小。该实施方式中，任意相邻两个双层结构都具有不同带隙差。具体地，任意相邻两个双层结构具有不同组分构成。在本申请另一些实施方式中，K个双层结构中，也可以是部分相邻的双层结构具有相同带隙差。其中，相邻层叠在一起的具有相同带隙差的双层结构的重复周期可以是1-10。对于不同带隙差的双层结构的重复周期可以是相同，也可以是不相同，例如，如图4所示，在Al xGa 1-xN/Al yGa 1-yN组成的缓冲层中，不同带隙差的双层结构的重复周期相同，均为2，即可以是第一双层结构带隙差＝第二双层结构带隙差>第三双层结构带隙差＝第四双层结构带隙差…>第K双层结构带隙差。不同带隙差的双层结构的重复周期不相同，例如，第一双层结构带隙差＝第二双层结构带隙差＝第三双层结构带隙差>第四双层结构带隙差＝第五双层结构带隙差>第六双层结构带隙差…>第K双层结构带隙差。
本申请实施方式中，K个双层结构由GaN和AlN两种第Ⅲ族氮化物构成，每一双层结构中的平均Al组分含量可为5％-50％。在一些实施方式中，每一双层结构中的平均Al组分含量为8％-38％。在另一些实施方式中，每一双层结构中的平均Al组分含量为15％-30％。在其 他一些实施方式中，每一第Ⅲ族氮化物双层结构中的平均Al组分含量为20％-25％。平均Al组分含量是指在每一双层结构中，Al元素占第III族金属元素的平均摩尔百分比。将每一双层结构的平均Al组分含量控制在适合的范围，可以保证缓冲层具有较好的晶体质量。对于Al xGa 1-xN/Al yGa 1-yN双层结构，每一双层结构中的平均Al组分含量可表示为[(T 上×x+T 下×y)/(T 上+T 下)]×100％，其中，T 上和T 下分别表示双层结构的上层与下层的厚度，x和y分别表示上层与下层的Al组分含量。本申请一些实施方式中，每一双层结构中的平均Al组分含量相同，通过保持Al组分不变，可以使得在设计高温翘曲的预补偿时只需要考虑膜层厚度影响而不用考虑Al组分变化影响，简化参数设计。本申请另一些实施方式中，K个双层结构的平均Al组分含量沿缓冲层的厚度方向呈渐变趋势。将多个双层结构的平均Al组分含量设计成渐变，有利于应力调控。
另外，本申请中K个双层结构的带隙差沿缓冲层的厚度方向整体呈渐变趋势，可以是沿缓冲层的厚度方向呈严格的逐渐增大或逐渐减小变化，也可以是整体上呈逐渐增大或逐渐减小变化，但存在少量特殊的与整体渐变趋势相反的变化情况，例如在带隙差整体呈逐渐增大的缓冲层中存在少量带隙差减小的双层结构。
本申请实施方式中，外延层的材质包括GaN、AlN、InN、AlGaN、InGaN、InAlN、InAlGaN中的一种或多种。本申请实施方式中，外延层40的材质包括第Ⅲ族氮化物，具体地例如可以是GaN、AlN、InN、AlGaN、InGaN、InAlN、InAlGaN中的一种或多种。外延层40的厚度大于或等于300nm。现有氮化镓外延层的厚度受应力所限一般厚度较小，而本申请实施例的氮化物外延结构可以很好地消除应力，因此可适用于厚膜外延层的制备，理论上可以无限厚度。在本申请一些实施方式中，外延层的厚度可以是大于或等于5μm，也可以是大于或等于10μm，例如15μm-100μm。外延层40可以是完全覆盖成核层20，也可以是部分覆盖成核层20。
本申请实施方式中，不同氮化物外延层可以适用不同半导体器件，如GaN、AlGaN、AlN可适用功率器件，而含In的氮化物外延层可适用于光电器件。
本申请实施方式中，为配合使用性能要求，外延层40中也可掺入其他元素，例如为了提升绝缘性，可掺入碳，形成高电阻，提高耐压性能。
如图5所示，氮化物外延结构100还包括设置于成核层30与外延层40之间的过渡层50，过渡层50可以是AlGaN层。过渡层的厚度可以是10nm-300nm。过渡层50的设置有利于调控外延结构应力。
本申请实施方式中，如图5所示，氮化物外延结构100还包括设置于外延层40上的其他功能层60，其他功能层60的具体结构组成可以根据实际应用需要设置。本申请一实施方式中，具体可以是包括依次设置在外延层40上的AlN插入层61、AlGaN阻挡层62、P型GaN层63。在其他一些实施方式中，其他功能层60也可以是具有其他结构组成。
如图6所示，本申请实施例还提供一种氮化物外延结构的制备方法，包括：
S01、在衬底上形成成核层，成核层为AlN层或GaN层。
其中，具体可以是采用金属有机化学气相沉积或分子束外延的方式在衬底10上制备成核层20。在制备成核层20之前，可以先对衬底10进行常规的清洁处理。
本申请一具体实施方式中，采用金属有机化学气相沉积的方式在衬底10上制备成核层20，具体地可以是，将衬底10置于金属有机化学气相沉积反应室中，于900-1100℃的温度和30-60Torr的压力下，通入氢气和氨气3min-5min，得到处理后的衬底10，然后通入氢气、氨气、以及铝源或镓源，在处理后的衬底10上沉积得到氮化铝或氮化镓，即得到成核层20。 本申请实施方式中，沉积过程中的各参数并不局限于上述范围。镓源包括但不限于为三甲基镓、三乙基镓。铝源包括但不限于为三甲基铝、三乙基铝。
S02、在成核层上形成缓冲层。
本申请实施方式中，缓冲层30可以是通过金属有机化学气相沉积的方式制备得到。具体地，将经步骤S01后获得的具有成核层的衬底置于金属有机化学气相沉积反应室中，于900-1100℃的温度和30-60Torr的压力下，然后通入氢气、氨气、以及第三主族金属源，在缓冲层30上外延生长得到第Ⅲ族氮化物，得到缓冲层30。第三主族金属源为含第三主族金属元素的有机化合物，如三甲基镓、三乙基镓、三甲基铝、三乙基铝等。通过改变第三主族金属源的通入量可以改变缓冲层中各第Ⅲ族氮化物的含量，通过控制沉积时间可以获得不同厚度的氮化物层。
S03、在缓冲层上外延生长第Ⅲ族氮化物，形成外延层。
本申请实施方式中，外延层40可以是通过金属有机化学气相沉积的方式制备得到。具体地，将经步骤S02后获得的衬底10置于金属有机化学气相沉积反应室中，于900-1100℃的温度和30-60Torr的压力下，通入氢气和氨气3-5min，得到处理后的衬底10，然后通入氢气、氨气、以及第三主族金属源，在缓冲层30上外延生长得到第Ⅲ族氮化物，形成外延层40。其中，第Ⅲ族氮化物具体地例如可以是GaN、AlN、InN、AlGaN、InGaN、InAlN、InAlGaN中的一种或多种。第三主族金属源为含第三主族金属元素的有机化合物，如三甲基镓、三乙基镓、三甲基铝、三乙基铝等。
本申请实施方式中，上述制备方法还可以包括在缓冲层30与外延层40之间形成过渡层50。即在步骤S03之前，先在缓冲层30上制备一层过渡层50，再在过渡层50上生长外延层40。过渡层50的材质可为Al GaN层。
本申请实施例还提供一种半导体器件，包括本申请实施例上述提供的氮化物外延结构，本申请实施例氮化物外延结构可以直接作为半导体器件的一部分，也可以是将剥离下来应用于半导体器件中。该半导体器件包括但不限于为功率器件(即电力电子器件)、射频器件或光电器件。其中功率器件、射频器件可以是晶体管，具体可为场效应晶体管，如 高电子迁移率 晶体管(High Electron Mobility Transistor，HEMT)。光电器件例如为发光二极管(Light Emitting Diode，LED)，激光二极管(Laser diode，LD)。具体可为氮化物基发光二极管，氮化物基量子阱激光二极管。
下面分多个实施例对本申请实施例进行进一步的说明。
实施例一
一种氮化物外延结构，包括衬底，以及依次设置在衬底上的成核层、缓冲层、外延层和其他功能层。衬底采用Si、蓝宝石、GaN、SiC、金刚石、SOI等材料；成核层为AlN成核层，厚度在50nm-400nm之间；缓冲层为渐变带隙差结构层，包括11个上层/下层为Al xGa 1-xN/Al yGa 1-yN的双层结构，每一双层结构的平均Al组分含量均为20％，每一个双层结构中x、y取值和厚度T 上、T 下如表1所示。外延层为GaN层，可包含碳掺杂的GaN或AlGaN等结构，厚度为100nm-3μm。其他功能层可包括依次设置在外延层上的AlN插入层，厚度为1nm；AlGaN阻挡层层，Al组分范围10％-30％，厚度为10-30nm；p-GaN层，P型杂质通过Mg掺杂实现，厚度范围为30nm-120nm。
表1 实施例一的缓冲层参数
Figure PCTCN2021118342-appb-000001
其中，序号为1-11的双层结构依次层叠设置，序号为1的双层结构靠近外延层设置，序号为11的双层结构靠近成核层设置。表1中的周期数5是指每个序号的双层结构均重复5次，即不同带隙差的双层结构的重复周期相同，形成11组双层结构，每一组为5个相同的双层结构堆叠。即缓冲层包括5个堆叠的Al 0.5Ga 0.5N/Al 0.17Ga 0.83N双层结构、5个堆叠的Al 0.55Ga 0.45N/Al 0.165Ga 0.835N双层结构……依此类推。由表1可以获知，实施例一的氮化物外延结构，缓冲层的11组双层结构的Al组分含量差值由成核层一侧向外延层一侧逐渐减小，也即11组双层结构的带隙差由成核层一侧向外延层一侧逐渐减小。另外，实施例一的每一组双层结构的平均Al组分含量相同，均为20％。
实施例二
与实施例一的区别仅在于，缓冲层包括51个上层/下层为Al xGa 1-xN/Al yGa 1-yN的双层结构，每一个双层结构中x、y取值、上层厚度T 上、下层厚度T 下如表2所示。
表2 实施例二的缓冲层参数
Figure PCTCN2021118342-appb-000002
Figure PCTCN2021118342-appb-000003
其中，序号为1-51的双层结构依次层叠设置，序号为1的双层结构靠近外延层设置，序号为51的双层结构靠近成核层设置。表2中的周期数1是指每个序号的双层结构只有一个。由表2可以获知，实施例二的氮化物外延结构，缓冲层的51个双层结构的Al组分含量差值由成核层一侧向外延层一侧逐渐减小，也即51个双层结构的带隙差由成核层一侧向外延层一侧逐渐减小。另外，实施例二的每一双层结构的平均Al组分含量相同，均为20％。相对于实施例一，实施例二的缓冲层的带隙差渐变间距更小，能更好地调节衬底与外延层之间的应力。
图7A为实施例二的氮化物外延结构中缓冲层靠近衬底一侧的双层结构的TEM图谱，图7B 为实施例二的氮化物外延结构中缓冲层靠近衬底一侧的双层结构的EDS图谱。图7B中的双层结构对应表2中序号为49-51的三个双层结构，由图7A和图7B可以获知，靠近衬底一侧的双层结构中带隙大的上层中Al组分接近100％，并向远离衬底一侧呈降低趋势。图8A为实施例二的氮化物外延结构中缓冲层靠近外延层一侧的双层结构的TEM图谱，图8B为实施例二的氮化物外延结构中缓冲层靠近外延层一侧的双层结构的EDS图谱。图8B中的双层结构对应表2中序号为1-3的三个双层结构，对比图7B和图8B可以看出，靠近衬底一侧的双层结构的Al含量差值比靠近外延层一侧的双层结构的Al含量差值大。
注：EDS图谱中有Ga、Al、N三种元素的曲线，N元素占比约50％，故Al元素曲线上各点对应的纵坐标值×2为Al组分含量，由于测量误差等因素，实测值与设计值可能存在一定差异。
实施例三
与实施例一的区别在于，缓冲层包括11组上层/下层为Al xGa 1-xN/Al yGa 1-yN的双层结构，每一组双层结构中x、y取值、上层厚度T 上、下层厚度T 下如表3所示。
表3 实施例三的缓冲层参数
Figure PCTCN2021118342-appb-000004
其中，序号为1-11的双层结构依次层叠设置，序号为1的双层结构靠近外延层设置，序号为11的双层结构靠近成核层设置。表1中的周期数5是指每个序号的双层结构均重复5次，即不同带隙差的双层结构的重复周期相同，形成11组双层结构，每一组为5个相同的双层结构堆叠。由表3可以获知，实施例三的氮化物外延结构，缓冲层的11组双层结构的Al组分含量差值由成核层一侧向外延层一侧逐渐减小，也即11个双层结构的带隙差由成核层一侧向外延层一侧逐渐减小。另外，实施例三的11组双层结构的平均Al组分含量也由成核层一侧向外延层一侧逐渐减小。

Claims (16)

  1. 一种氮化物外延结构，其特征在于，包括：
    衬底；
    成核层，形成于所述衬底上，所述成核层为氮化铝层或氮化镓层；
    缓冲层，形成于所述成核层上，所述缓冲层包括K个堆叠的第Ⅲ族氮化物双层结构，所述K≥3；每一所述双层结构均包括层叠的上层和下层，所述上层材质的禁带宽度大于所述下层材质的禁带宽度；每一所述双层结构的带隙差为所述上层材质的禁带宽度与所述下层材质的禁带宽度的差值；所述K个双层结构的带隙差沿所述缓冲层的厚度方向整体呈渐变趋势；
    外延层，形成于所述缓冲层上，所述外延层的材质包括第Ⅲ族氮化物。
  2. 如权利要求1所述的氮化物外延结构，其特征在于，所述上层和所述下层的材质分别选自GaN、AlN、InN或其组合中的一种。
  3. 如权利要求1或2所述的氮化物外延结构，其特征在于，所述下层的厚度大于两倍所述上层的厚度。
  4. 如权利要求1-3任一项所述的氮化物外延结构，其特征在于，所述K个双层结构的带隙差自所述成核层一侧向所述外延层一侧逐渐减小。
  5. 如权利要求1-4任一项所述的氮化物外延结构，其特征在于，所述K个双层结构中，最大带隙差与最小带隙差的差值大于构成所述双层结构的禁带宽度最大的第Ⅲ族氮化物与禁带宽度最小的第Ⅲ族氮化物的禁带宽度差值的20％。
  6. 如权利要求1-5任一项所述的氮化物外延结构，其特征在于，所述K个双层结构由GaN和AlN构成，每一所述双层结构中的平均Al组分含量为5％-50％。
  7. 如权利要求6所述的氮化物外延结构，其特征在于，每一所述双层结构中的平均Al组分含量相同。
  8. 如权利要求6所述的氮化物外延结构，其特征在于，所述K个双层结构的平均Al组分含量沿所述缓冲层的厚度方向呈渐变趋势。
  9. 如权利要求1-8任一项所述的氮化物外延结构，其特征在于，每一所述双层结构的厚度小于100nm。
  10. 如权利要求1-9任一项所述的氮化物外延结构，其特征在于，所述外延层的材质包括GaN、AlN、InN、AlGaN、InGaN、InAlN、InAlGaN中的一种或多种。
  11. 如权利要求1-10任一项所述的氮化物外延结构，其特征在于，所述外延层的厚度大于或等于300nm。
  12. 如权利要求1-11任一项所述的氮化物外延结构，其特征在于，所述衬底包括硅衬底、蓝宝石衬底、绝缘体上硅衬底、氮化镓衬底、砷化镓衬底、磷化铟衬底、氮化铝衬底、碳化硅衬底、石英衬底或金刚石衬底。
  13. 如权利要求1-12任一项所述的氮化物外延结构，其特征在于，所述成核层的厚度为10nm-300nm。
  14. 一种半导体器件，其特征在于，包括如权利要求1-13任一项所述的氮化物外延结构。
  15. 如权利要求14所述的半导体器件，其特征在于，所述半导体器件包括功率器件、射频器件或光电器件。
  16. 如权利要求14或15所述的半导体器件，其特征在于，所述半导体器件包括场效应晶体管、发光二极管或激光二极管。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115116828A (zh) * 2022-06-29 2022-09-27 江苏第三代半导体研究院有限公司 基于氮化物单晶衬底的同质外延结构及其均匀性调控方法
CN115132841A (zh) * 2022-06-28 2022-09-30 闽都创新实验室 一种氮化镓基外延片及其制备方法与功率射频器件
CN115287751A (zh) * 2022-06-22 2022-11-04 西安电子科技大学 一种基于AlPN成核层的低射频损耗硅基GaN薄膜及制备方法
WO2024125814A1 (de) * 2022-12-13 2024-06-20 Azur Space Solar Power Gmbh Halbleiterscheibe

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116454118A (zh) * 2022-04-21 2023-07-18 南京百识电子科技有限公司 氮化物半导体外延结构
CN117199122A (zh) * 2022-05-26 2023-12-08 华为技术有限公司 半导体器件、电子芯片和电子设备
CN117476825B (zh) * 2023-12-25 2024-04-12 北京中博芯半导体科技有限公司 AlGaN外延结构的生长方法及应用
CN121087618B (zh) * 2025-11-06 2026-02-17 芯联动力科技(绍兴)有限公司 外延结构及制备方法、hemt器件及制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130168691A1 (en) * 2010-06-25 2013-07-04 Toyoda Gosei Co., Ltd. Method of manufacturing semiconductor light emitting element, semiconductor light emitting element, electronic device, and machine device
CN103236477A (zh) * 2013-04-19 2013-08-07 安徽三安光电有限公司 一种led外延结构及其制备方法
CN103806104A (zh) * 2014-02-19 2014-05-21 中国科学院半导体研究所 一种高Al组分AlGaN薄膜的制备方法
CN104885198A (zh) * 2013-01-04 2015-09-02 同和电子科技有限公司 Iii族氮化物外延基板以及其的制造方法
CN109216520A (zh) * 2017-06-29 2019-01-15 环球晶圆股份有限公司 半导体元件及其形成方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367581A (zh) * 2013-07-26 2013-10-23 东南大学 一种具有电子阻挡层结构的发光二极管
JP5698321B2 (ja) * 2013-08-09 2015-04-08 Ｄｏｗａエレクトロニクス株式会社 Ｉｉｉ族窒化物半導体エピタキシャル基板およびｉｉｉ族窒化物半導体発光素子ならびにこれらの製造方法
FR3028670B1 (fr) * 2014-11-18 2017-12-22 Commissariat Energie Atomique Structure semi-conductrice a couche de semi-conducteur du groupe iii-v ou ii-vi comprenant une structure cristalline a mailles cubiques ou hexagonales
CN104393130B (zh) * 2014-12-15 2017-04-12 聚灿光电科技股份有限公司 一种GaN基LED外延结构及其制备方法
CN206516634U (zh) * 2016-12-26 2017-09-22 英诺赛科（珠海）科技有限公司 含有氮镓铝和氮镓铟的缓存层的半导体器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130168691A1 (en) * 2010-06-25 2013-07-04 Toyoda Gosei Co., Ltd. Method of manufacturing semiconductor light emitting element, semiconductor light emitting element, electronic device, and machine device
CN104885198A (zh) * 2013-01-04 2015-09-02 同和电子科技有限公司 Iii族氮化物外延基板以及其的制造方法
CN103236477A (zh) * 2013-04-19 2013-08-07 安徽三安光电有限公司 一种led外延结构及其制备方法
CN103806104A (zh) * 2014-02-19 2014-05-21 中国科学院半导体研究所 一种高Al组分AlGaN薄膜的制备方法
CN109216520A (zh) * 2017-06-29 2019-01-15 环球晶圆股份有限公司 半导体元件及其形成方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4207247A4

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115287751A (zh) * 2022-06-22 2022-11-04 西安电子科技大学 一种基于AlPN成核层的低射频损耗硅基GaN薄膜及制备方法
CN115132841A (zh) * 2022-06-28 2022-09-30 闽都创新实验室 一种氮化镓基外延片及其制备方法与功率射频器件
CN115116828A (zh) * 2022-06-29 2022-09-27 江苏第三代半导体研究院有限公司 基于氮化物单晶衬底的同质外延结构及其均匀性调控方法
CN115116828B (zh) * 2022-06-29 2024-08-06 江苏第三代半导体研究院有限公司 基于氮化物单晶衬底的同质外延结构及其均匀性调控方法
WO2024125814A1 (de) * 2022-12-13 2024-06-20 Azur Space Solar Power Gmbh Halbleiterscheibe
TWI879216B (zh) * 2022-12-13 2025-04-01 德商艾澤太空太陽能公司 半導體晶圓

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