WO2022068266A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

Info

Publication number
WO2022068266A1
WO2022068266A1 PCT/CN2021/100206 CN2021100206W WO2022068266A1 WO 2022068266 A1 WO2022068266 A1 WO 2022068266A1 CN 2021100206 W CN2021100206 W CN 2021100206W WO 2022068266 A1 WO2022068266 A1 WO 2022068266A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
bit line
hole
etching
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/100206
Other languages
English (en)
French (fr)
Inventor
孙玉乐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to EP21873928.2A priority Critical patent/EP4181202A4/en
Priority to US17/401,412 priority patent/US11930633B2/en
Publication of WO2022068266A1 publication Critical patent/WO2022068266A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present application relates to the technical field of semiconductors, and in particular, to a semiconductor device and a preparation method thereof.
  • a dynamic random access memory (Dynamic Random Access Memory, DRAM) structural unit includes a logic circuit area and a cell area for storing charges.
  • DRAM Dynamic Random Access Memory
  • the embodiments of the present application provide a method for fabricating a semiconductor device, which can control the outline of a contact point of a bit line and improve the electrical connection effect.
  • an embodiment of the present application provides a method for fabricating a semiconductor device, including: providing a substrate, wherein a word line structure is formed in the substrate, a support structure is formed on the substrate, and the The support structure includes a bit line support layer and a word line support layer located above the word line structure, a bit line structure is formed in the bit line support layer, and the bit line support layer includes a first oxide layer and a first nitrogen compound layer, the bit line structure is formed in the first nitride layer, the first oxide layer is formed on both sides of the bit line structure and in the first nitride layer; patterning the support structure forming a first through hole corresponding to the bit line structure in the bit line support layer; etching the bit line support layer along the first through hole to a preset height, adjusting etching parameters and etching the selective etching ratio of the gas to the oxide layer and the nitride layer, and continue to etch the bit line support layer until the bit line structure is exposed to form
  • the word line support layer includes a second nitride layer, a second oxide layer and a third nitride layer arranged in a stack, and the support structure is patterned to support the bit line In the step of forming a first via hole corresponding to the bit line structure in the layer, a second via hole corresponding to the word line structure is formed in the bit line support layer at the same time to expose the second oxide layer .
  • a first etching gas is used to The support structure is etched, and the etching selectivity ratio of the first etching gas to the oxide layer and the nitride layer is 0.1 to 0.5.
  • the step of etching the bit line support layer along the first through hole to a predetermined height includes simultaneously etching the second oxide layer along the second through hole etching, in this step, the second oxide layer and the bit line support layer are etched by using a second etching gas.
  • the etching parameters and the selective etching ratio of the etching gas to the oxide layer and the nitride layer are adjusted, and the bit line support layer is continuously etched until the bit line is exposed
  • the structure step includes: using a third etching gas and adjusting etching parameters to continue etching along the first through hole and the second through hole until the word line structure and the bit line structure are exposed.
  • the etching selectivity ratio of the second etching gas to the nitride layer and the oxide layer is 0.5 to 0.8.
  • the etching selectivity ratio of the third etching gas to the nitride layer and the oxide layer is 1.2 to 1.5.
  • the etching parameter is an etching bias
  • the power of the etching bias is 700W (watts) to 1100W.
  • the step of patterning the support structure to form a first via corresponding to the bit line structure in the bit line support layer further comprises: forming on the support structure mask layer and photoresist layer; patterning the photoresist layer, so that the photoresist layer in the first through hole and the second through hole area is removed; transferring the pattern of the photoresist layer to the mask layer, forming a patterned mask layer; using the mask layer as a mask, removing part of the support structure to form the first through hole and the second through hole.
  • the following steps are further included: filling the first through hole to form a bit line contact point, and filling the second through hole to form a word line contact point.
  • the first through hole is filled to form a bit line contact point
  • the second through hole is filled to form a word line contact point, and the following steps are performed; removing the photoresist layer and the mask layer.
  • An embodiment of the present application further proposes a semiconductor device, including: a substrate; a word line structure formed in the substrate; and a bit line structure formed on the substrate and spanning the word line structure; a support structure formed on the substrate and including a bit line support layer and a word line support layer, the bit line support layer including a first oxide layer and a first nitrogen compound layer, the bit line structure is formed in a first nitride layer, the first oxide layer is formed on both sides of the bit line structure and in the first nitride layer, the word line support layer including a second nitride layer, a second oxide layer and a third nitride layer arranged in a stack, the second oxide layer is formed between the second nitride layer and the third nitride layer, and the bit line supports A first through hole is formed in the layer to expose the bit line structure, a second through hole is formed in the word line support layer to expose the word line structure; a polymer layer, the polymer layer is formed on the The first through
  • the inner wall surface of the polymer layer is formed as an inclined surface facing the side wall of the bit line structure from the side wall of the first through hole.
  • the inclined surface is formed as a stepped surface or an arc-shaped surface.
  • the semiconductor device further includes a bit line contact point and a word line contact point, the bit line contact point is filled and formed in the first through hole, and the word line contact point is filled and formed in the second through hole.
  • FIG. 1 is an implementation flowchart of a method for fabricating a semiconductor device according to an embodiment of the present application
  • FIGS. 2 , 4 , 6 , 8 , and 10 and 12 are cross-sectional views along a first direction of each step of a method for fabricating a semiconductor device according to an embodiment of the present application;
  • 3 , 5 , 7 , 9 , 11 , and 13 are cross-sectional views along the second direction of each step of a method for fabricating a semiconductor device according to an embodiment of the present application.
  • Bit line structure 21: Bit line conductive layer, 22: Bit line polysilicon layer;
  • bit line support layer 31: first nitride layer, 32: first oxide layer;
  • word line support layer 51: second nitride layer, 52: second oxide layer, 53: third nitride layer;
  • 71 first through hole
  • 72 second through hole
  • 73 bit line contact point
  • 74 word line contact point
  • 81 a first mask layer
  • 82 a photoresist layer
  • 83 a second mask layer.
  • the manufacturing method of the semiconductor device may include the following steps:
  • Step S101 providing a substrate, a word line structure is formed in the substrate, a support structure is formed on the substrate, and the support structure includes a bit line support layer and a word line support layer located above the word line structure , a bit line structure is formed in the bit line support layer, the bit line support layer includes a first oxide layer and a first nitride layer, the bit line structure is formed in the first nitride layer, and the first nitride layer is formed.
  • An oxide layer is formed on both sides of the bit line structure and within the first nitride layer;
  • Step S102 patterning the support structure to form a first through hole corresponding to the bit line structure in the bit line support layer;
  • Step S103 Etch the bit line support layer along the first through hole to a preset height, adjust the etching parameters and the selective etching ratio of the etching gas to the oxide layer and the nitride layer, and adjust the bit line support layer.
  • the line support layer continues to be etched until the bit line structure is exposed, so as to form a polymer layer over the bit line structure, the polymer layer is formed on a portion of the sidewall of the first through hole and located at all the both sides of the bit line structure.
  • FIGS. 3 , 5 , 7 , 9 , 11 and 13 are cross-sectional views along the second direction of each step of the method for fabricating the semiconductor device 100 according to an embodiment of the present invention.
  • a substrate 1 is provided with a word line structure 4 formed therein and a support structure formed thereon, the support structure comprising a bit line support layer 3 and The word line support layer 5 located above the word line structure 4, the bit line structure 2 is formed in the bit line support layer 3, the bit line support layer 3 includes a first oxide layer 32 and a first nitride layer 31, The bit line structure 2 is formed in the first nitride layer 31, and the first oxide layer 32 is formed on both sides of the bit line structure 2 and is located in the first nitride layer 31;
  • the supporting layer 3 continues to be etched until the bit line structure 2 is exposed, so as to form a polymer layer 6 over the bit line structure 2 , and the polymer layer 6 is formed on a part of the side of the first through hole 71 on the walls and on both sides of the bit line structure 2 .
  • a substrate 1 is provided, a plurality of active regions are formed in the substrate 1, and a plurality of word line trenches penetrating the active regions are formed, and the trenches are filled with dielectrics and wires
  • bit line structure 2 is formed on substrate 1 and spans word line structure 4 .
  • a support structure is formed on the substrate 1, and the support structure is a stack structure formed by stacking an oxide layer and a nitride layer, wherein the nitride layer may be a silicon nitride layer, and the oxide layer may be a silicon oxide layer.
  • the support structure may include a bit line support layer 3 and a word line support layer 5, the bit line structure 2 is formed in the bit line support layer 3, the word line structure 4 is formed in the substrate 1, and the word line support layer 5 is formed in the word line structure 4 above.
  • the bit line support layer 3 may include a first nitride layer 31 and a first oxide layer 32, both of which are formed on the substrate 1, and the bit line The structure 2 is formed in the first nitride layer 31, the first nitride layer 31 wraps the bit line structure 2, the first oxide layer 32 is formed in the first nitride layer 31 and is formed on the side of the bit line structure 2, wherein, The upper surface of the first oxide layer 32 is higher than the upper surface of the bit line structure 2 and lower than the upper surface of the first nitride layer 31 .
  • the bit line structure 2 may include a bit line conductive layer 21 and a bit line polysilicon layer 22 , the bit line conductive layer 21 is located above the bit line polysilicon layer 22 , and the sidewalls of the bit line conductive layer 21 are in phase with the sidewalls of the bit line polysilicon layer 22 . flush.
  • the word line structure 4 includes a second nitride layer 51 , a second oxide layer 52 and a third nitride layer 53 which are stacked and disposed, and the third nitride layer 53 is formed over the word line structure 4 .
  • a mask layer and a photoresist layer 82 are formed on the support structure.
  • the mask layer may include a first mask layer 81 and a second mask layer 83.
  • the second mask layer 83 and the photoresist layer 82 are sequentially formed on the surface of the support structure.
  • the first mask layer 81 can be a carbon layer
  • the second mask layer 83 can be a hard mask layer such as a nitride layer.
  • the resist layer 82 is a photoresist layer, which can be formed on the surface of the second mask layer 83 by a spin coating process.
  • the photoresist layer 82 is patterned so that the photoresist layer 82 in the regions of the first through hole 71 and the second through hole 72 is removed, and the first through hole 71 is defined by the photoresist layer 82 . and the position of the second through hole 72, the pattern of the photoresist layer 82 is transferred into the mask layer and a hole through the mask layer is formed to form a patterned mask layer, so that the mask layer can be used as a mask to support the support The structure is patterned to form a first via 71 in the bit line support layer 3 and a second via 72 in the word line support layer 5 .
  • the patterned support structure is used to fill and form contact circuits such as the bit line contact 73 and the word line contact 74, wherein the step of patterning the support structure can be performed in steps, so that the etching process
  • the bit line structure 2 and the word line structure 4 can be etched simultaneously, and the outer contour of the formed bit line contact point 73 can be controlled and improved, so as to facilitate the formation and electrical connection of the bit line contact point 73 .
  • patterning the support structure to fill and form the contact circuit includes the following steps:
  • the support structure is patterned to form first vias 71 corresponding to the bit line structure 2 in the bit line support layer 3 , and at the same time to form a position corresponding to the word line structure 4 in the word line support layer 5
  • the corresponding second through holes 72 are formed to expose the second oxide layer 52.
  • the first etching gas can be used to etch the bit line support layer 3 and the word line support layer 5.
  • FIG. The selective etching ratio of the first etching gas to the oxide layer and the nitride layer is 0.1 to 0.5.
  • the etching rate of the first etching gas to oxide and nitride is different, and the etching selectivity ratio of the oxide layer to the nitride layer is greater than or equal to 0.1 and less than or equal to 0.5.
  • the etching gas is more efficient for etching nitrides than for oxides.
  • the second nitride layer 51 and part of the first nitride layer 31 are formed on the upper part of the support structure, and the etching in this step is mainly used to etch the nitride layer of the support structure, so Using the first etching gas with a faster etching rate for the nitride can speed up the etching rate of the bit line support layer 3 and the nitride layer on the upper part of the word line support layer 5, thereby increasing the etching efficiency and reducing the etching rate.
  • the second oxide layer 52 is under the second nitride layer 51. Due to the change of the material to be etched, the etching gas can be adjusted to change the etching selectivity ratio of oxide and nitride.
  • the step of etching the second oxide layer along the second through hole 72 at the same time includes 52 etching, in this step, the second oxide layer 52 and the bit line support layer 3 are etched by using a second etching gas.
  • bit line support layer 3 in the step of etching the bit line support layer 3 along the first through hole 71 to a predetermined height, including using a second etching gas to etch along the first through hole 71
  • the bit line support layer 3 is etched to a predetermined height; at the same time, the second oxide layer 52 is etched along the second through hole 72 by using the second etching gas.
  • the upper surface of the bit line structure 2 is higher than the upper surface of the word line structure 4.
  • the etching gas is adjusted to The etching selectivity ratio of the oxide layer and the nitride layer is changed, so that the second oxide layer 52 above the word line structure 4 is etched faster, and the etching efficiency of the word line support layer 5 is accelerated.
  • the etching gas is adjusted, and the second etching gas is used to etch the bit line support layer 3 and the word line support layer 5 until The bit line support layer 3 is etched along the first through hole 71 to a predetermined height position.
  • the etching selectivity ratio of the second etching gas to the nitride layer and the oxide layer is 0.5 to 0.8.
  • the etching efficiency of the second etching gas to the oxide is greater than that of the nitride. As shown in FIG. 8 and FIG.
  • the second etching gas is used to etch the second oxide layer 52 to the second through hole 72 .
  • the lower surface of the second through hole 72 is lower than the lower surface of the first through hole 71 , which speeds up the etching rate of the word line support layer 5 .
  • the etching parameters and the selective etching ratio of the etching gas to the oxide layer and the nitride layer are adjusted, and the etching of the bit line support layer 3 is continued until the bit line structure 2 is exposed.
  • the steps include: using a third etching gas and adjusting etching parameters to continue etching along the first through hole 71 and the second through hole 72 to expose the word line structure 4 and the bit line structure 2 .
  • Step 2 includes: adjusting the etching parameters and the selective etching ratio of the etching gas to the oxide layer and the nitride layer, and using the third etching gas to continue etching the bit line support along the first through hole 71 layer 3 until the bit line structure 2 is exposed, and the word line support layer 5 is continuously etched along the second through hole 72 with the third etching gas until the word line structure 4 is exposed.
  • the oxide layer and the nitride layer are selectively etched by adjusting the etching parameters and the etching gas, and continue to etch down along the first through hole 71 and the second through hole 72 until exposed.
  • the third etching gas can be used to etch the bit line support layer 3 and the word line support layer 5 respectively, and the third etching gas can etch the nitride layer and the oxide layer.
  • the selective etching ratio of the oxide layer is 1.2 to 1.5, that is to say, the third etching gas is adjusted so that the etching rate of the nitride is greater than that of the oxide, so that the third etching gas in the bit line support layer 3
  • the etching rate of the nitride layer 31 is faster than the etching rate of the first oxide layer 32, so that the polymer layer 6 with a certain shape is easily formed on the sidewall of the first through hole 71, so that the bit line support layer 3 can be controlled.
  • the contour of the sidewall of the inner first through hole 71 is convenient to control and improve the contour of the bit line contact point 73 formed subsequently, and improve the electrical connection performance of the bit line contact point 73 .
  • etching the second oxide layer 52 in the word line support layer 5 does not allow by-products to be formed, so that the sidewall profile of the second through hole 72 is relatively flat and not easy to bend, so as to facilitate the formation of the subsequent word line contact points 74 .
  • the etching parameters are adjusted, the etching parameters may be an etching bias, and the power of the etching bias may be 700W to 1100W, so that the nitride layer on the sidewalls of the second through holes 72 is easily formed.
  • a polymer layer 6 having a curved inner wall surface is formed.
  • the oxide layer of the word line support layer 5 is etched, it is not easy to form by-products, and thus it is not easy to form a curved inner wall, so that the outer contour of the subsequently filled word line contact point 74 can be controlled.
  • the first through hole 71 is filled to form a bit line contact point 73
  • the second through hole 72 is filled to form a word line contact point 74
  • the bit line contact point 73 is electrically connected to the bit line structure 2
  • the word line contacts 74 are electrically connected to the word line structures 4 .
  • the mask layer and photoresist layer 82 are removed, and the mask layer over the support structure is pickled to control the formation of bit line contacts 73 and word line contacts
  • the outer contour of the point 74 improves the electrical connection effect between the bit line contact point 73 and the word line contact point 74 .
  • the embodiment of the present application further provides a semiconductor device 100, and the semiconductor device 100 is formed by using the method for fabricating the semiconductor device 100 in the above-mentioned embodiment.
  • a semiconductor device 100 may include: a substrate 1 , a word line structure 4 , a bit line structure 2 , a support structure and a polymer layer 6 .
  • the word line structure 4 is formed within the substrate 1, the bit line structure 2 is formed on the substrate 1 and spans the word line structure 4; the support structure, the support structure is formed on the substrate 1 and includes the bit line support layer 3 and the word line support Layer 5, the bit line support layer 3 includes a first oxide layer 32 and a first nitride layer 31, the bit line structure 2 is formed in the first nitride layer 31, and the first oxide layer 32 is formed on both sides of the bit line structure 2. and located in the first nitride layer 31, the word line support layer 5 includes a second nitride layer 51, a second oxide layer 52 and a third nitride layer 53 which are stacked and arranged, and the second oxide layer 52 is formed on the first nitride layer 51.
  • a first through hole 71 is formed in the bit line support layer 3 to expose the bit line structure 2
  • a second through hole 72 is formed in the word line support layer 5 to expose Word line structure 4; polymer layer 6, the polymer layer 6 is formed within the first through hole 71 and on a portion of the sidewall of the first through hole 71 above the first oxide layer.
  • the inner wall surface of the polymer layer 6 is formed as an inclined surface from the sidewall of the first through hole 71 toward the sidewall of the bit line structure 2 , and further, the inclined surface is formed as a stepped surface or Arc face.
  • the semiconductor device 100 further includes a bit line contact point 73 and a word line contact point 74 .
  • the bit line contact point 73 is filled and formed in the first through hole 71
  • the word line contact point 74 is filled and formed in the second through hole. within 72.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种半导体器件及其制备方法，制备方法包括：提供衬底(1)，衬底(1)内形成有字线结构(4)，位线支撑层（3）包括第一氧化物层（32）和第一氮化物层（31），位线结构（2）形成在第一氮化物层（31）内，第一氧化物层（32）形成在所述位线结构（2）两侧且位于第一氮化物层（31）内；图形化支撑结构以在位线支撑层（3）内形成与位线结构（2）对应的第一通孔（71）；沿第一通孔（71）刻蚀位线支撑层（3）至预设高度，调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，并对位线支撑层（3）继续刻蚀，直至暴露位线结构（2），以在位线结构（2）的上方形成聚合物层（6），聚合物层（6）形成在第一通孔（71）的部分侧壁上且位于位线结构（2）的两侧。

Description

半导体器件及其制备方法
相关申请的交叉引用
本申请基于申请号为202011049179.1、申请日为2020年09月29日、申请名称为“半导体器件及其制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体技术领域，具体涉及一种半导体器件及其制备方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)结构单元包括逻辑电路区和存储电荷的单元(cell)区。一方面，随着几何尺寸按照摩尔定律不断减小，连接电路的接触电阻也在不断增大，为了保证低连接电阻的同时，还需提高晶体管区与电容区的高电性连接。另一方面，随着电路接触点在不断的减小，以及在蚀刻过程受到副产物的影响，很难控制连接电路的接触处的外形轮廓。
发明内容
本申请实施例在于提供一种半导体器件的制备方法，能够控制位线接触点的外形轮廓，提高电连接效果。
为解决上述技术问题，本申请实施例中提供了一种半导体器件的制备方法，包括：提供衬底，所述衬底内形成有字线结构，所述衬底上形成有支撑结构，所述支撑结构包括位线支撑层和位于所述字线结构上方的字线支撑层，所述位线支撑层内形成有位线结构，所述位线支撑层包括第一氧化物层和第一氮化物层，所述位线结构形成在第一氮化物层内，所述第一氧化物层形成在所述位线结构两侧且位于所述第一氮化物层内；图形化所述支撑结构以在所述位线支撑层内形成与所述位线结构对应的第一通孔；沿所述第一通孔刻蚀所述位线支撑层至预设高度，调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，并对所述位线支撑层继续刻蚀，直至暴露所述位线结构，以在所述位线结构的上方形成聚合物层，所述聚合物层形成在所述第一通孔的部分侧 壁上且位于所述位线结构的两侧。
根据本申请的一些实施例，所述字线支撑层包括层叠设置的第二氮化物层、第二氧化物层和第三氮化物层，在图形化所述支撑结构以在所述位线支撑层内形成与所述位线结构对应的第一通孔的步骤中，同时在所述位线支撑层内形成与所述字线结构对应的第二通孔以暴露所述第二氧化物层。
在本申请的一些实施例中，在图形化所述支撑结构以在所述位线支撑层内形成与所述位线结构对应的第一通孔步骤中，采用第一刻蚀气体对所述支撑结构进行刻蚀，所述第一刻蚀气体对氧化物层和氮化物层的刻蚀选择比为0.1至0.5。
在本申请的一些实施例中，在沿所述第一通孔刻蚀所述位线支撑层至预设高度步骤中，包括同时沿所述第二通孔对所述第二氧化物层刻蚀，此步骤中采用第二刻蚀气体对第二氧化物层和所述位线支撑层进行刻蚀。
在本申请的一些实施例中，在调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，并对所述位线支撑层继续刻蚀，直至暴露所述位线结构的步骤中包括：采用第三刻蚀气体并调节刻蚀参数沿所述第一通孔和所述第二通孔继续刻蚀至暴露所述字线结构和所述位线结构。
在本申请的一些实施例中，所述第二刻蚀气体对氮化物层和氧化物层的刻蚀选择比为0.5至0.8。
在本申请的一些实施例中，所述第三刻蚀气体对氮化物层和氧化物层的刻蚀选择比为1.2至1.5。
在本申请的一些实施例中，所述刻蚀参数为刻蚀偏压，所述刻蚀偏压的功率为700W(瓦)至1100W。
在本申请的一些实施例中，在图形化所述支撑结构以在所述位线支撑层内形成与所述位线结构对应的第一通孔的步骤进一步包括：在所述支撑结构上形成掩膜层及光阻层；图形化所述光阻层，使得所述第一通孔和所述第二通孔区域的光阻层被去除；将所述光阻层的图案转移到所述掩膜层，形成图形化的掩膜层；以所述掩膜层为掩膜，去除部分所述支撑结构以形成所述第一通孔和所述第二通孔。
在本申请的一些实施例中，还包括以下步骤，于所述第一通孔内填充形成位线接触点，于所述第二通孔内填充形成字线接触点。
在本申请的一些实施例中，在于所述第一通孔内填充形成位线接触点，于所述第二通孔内填充形成字线接触点之后执行以下步骤；去除所述光阻层和所述掩膜层。
本申请实施例还提出了一种半导体器件，包括：衬底；字线结构，所述字线结构形成在所述衬底内；位线结构，所述位线结构形成在所述衬底上且跨越所述字线结构；支撑结构，所述支撑结构形成在所述衬底上且包括位线支撑层和字线支撑层，所述位线支撑层包括第一氧化物层和第一氮化物层，所述位线结构形成在第一氮化物层内，所述第一氧化物层形成在所述位线结构两侧且位于所述第一氮化物层内，所述字线支撑层包括层叠设置的第二氮化物层、第二氧化物层和第三氮化物层，所述第二氧化物层形成在第二氮化物层和第三氮化物层之间，所述位线支撑层内形成有第一通孔以暴露所述位线结构，所述字线支撑层内形成有第二通孔以暴露所述字线结构；聚合物层，所述聚合物层形成在所述第一通孔内且形成在所述第一氧化层上方的所述第一通孔的部分侧壁上。
在本申请的一些实施例中，所述聚合物层的内壁面形成为由所述第一通孔的侧壁朝向所述位线结构的侧壁的倾斜面。
在本申请的一些实施例中，所述倾斜面形成为阶梯状面或弧形面。
在本申请的一些实施例中，所述半导体器件还包括位线接触点和字线接触点，所述位线接触点填充形成在所述第一通孔内，所述字线接触点填充形成在所述第二通孔内。
附图说明
图1为根据本申请实施例的半导体器件的制备方法的实现流程图；
图2、图4、图6、图8以及图10、图12为根据本申请实施例的半导体器件的制备方法的各步骤的沿第一方向的剖面图；
图3、图5、图7、图9以及图11、图13为根据本申请实施例的半导体器件的制备方法的各步骤的沿第二方向的剖面图。
附图标记：
100：半导体器件；
1：衬底；
2：位线结构，21：位线导电层，22：位线多晶硅层；
3：位线支撑层，31：第一氮化物层，32：第一氧化物层；
4：字线结构，
5：字线支撑层，51：第二氮化物层，52：第二氧化物层，53：第三氮化物层；
6：聚合物层；
71：第一通孔，72：第二通孔，73：位线接触点，74：字线接触点；
81：第一掩膜层，82：光阻层，83：第二掩膜层。
具体实施方式
以下结合附图和具体实施方式对本申请实施例提出的一种半导体器件的制备方法作进一步详细说明。
下面参考附图描述根据本申请实施例的半导体器件的制备方法。
如图1所示，本申请实施例的半导体器件的制备方法可以包括以下步骤：
步骤S101：提供衬底，所述衬底内形成有字线结构，所述衬底上形成有支撑结构，所述支撑结构包括位线支撑层和位于所述字线结构上方的字线支撑层，所述位线支撑层内形成有位线结构，所述位线支撑层包括第一氧化物层和第一氮化物层，所述位线结构形成在第一氮化物层内，所述第一氧化物层形成在所述位线结构两侧且位于所述第一氮化物层内；
步骤S102：图形化所述支撑结构以在所述位线支撑层内形成与所述位线结构对应的第一通孔；
步骤S103：沿所述第一通孔刻蚀所述位线支撑层至预设高度，调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，并对所述位线支撑层继续刻蚀，直至暴露所述位线结构，以在所述位线结构的上方形成聚合物层，所述聚合物层形成在所述第一通孔的部分侧壁上且位于所述位线结构的两侧。
如图2至图13所示为根据本发明申请实施例各步骤的半导体器件的剖面图。其中图2、图4、图6、图8、图10以及图12为根据本发明申请实施例的半导体器件100的制备方法的各步骤的沿第一方向的剖面图，图3、图5、图7、图9、图11以及图13为根据本发明实施例的半导体器件100的制备方法的各步骤的沿第二方向的剖面图。
如图2、3和10所示，提供衬底1，所述衬底1内形成有字线结构4，所述衬底1上形成有支撑结构，所述支撑结构包括位线支撑层3和位于字线结构4上方的字线支撑层5，所述位线支撑层3内形成有位线结构2，所述位线支撑层3包括第一氧化物层32和第一氮化物层31，所述位线结构2形成在第一氮化物层31内，所述第一氧化物层32形成在所述位线结构2两侧且位于所述第一氮化物层31内；
图形化所述支撑结构以在所述位线支撑层3内形成与所述位线结构2对应的第一通孔71；
沿所述第一通孔71刻蚀所述位线支撑层3至预设高度，调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，并对所述位线支撑层3继续刻蚀，直至暴露所述位线结构2，以在所述位线结构2的上方形成聚合物层6，所述聚合物层6形成在所述第一通孔71的部分侧壁上且位于所述位线结构2的两侧。
如图2和图3所示，提供一衬底1，在衬底1中形成多个有源区，并形成多条贯穿有源区的字线沟槽，对沟槽进行电介质和导线的填充以形成字线结构4，位线结构2形成在衬底1上且跨越字线结构4。
衬底1上形成有支撑结构，支撑结构为由氧化物层和氮化物层堆叠形成的叠层结构，其中氮化物层可以为氮化硅层，氧化物层可以为氧化硅层。支撑结构可包括位线支撑层3和字线支撑层5，位线结构2形成在位线支撑层3，字线结构4形成在衬底1内，字线支撑层5形成在字线结构4的上方。
如图2所示，位线支撑层3可以包括第一氮化物层31和第一氧化物层32，第一氧化物层32和第一氮化物层31均形成在衬底1上，位线结构2形成在第一氮化物层31内，第一氮化物层31包裹位线结构2，第一氧化物层32形成在第一氮化物层31内且形成在位线结构2侧面，其中，第一氧化物层32的上表面高于位线结构2的上表面且低于第一氮化物层31的上表面。位线结构2可以包括位线导电层21和位线多晶硅层22，位线导电层21位于位线多晶硅层22的上方，位线导电层21的侧壁与位线多晶硅层22的侧壁相平齐。
如图3所示，字线结构4包括层叠设置的第二氮化物层51、第二氧化物层52和第三氮化物层53，第三氮化物层53形成在字线结构4的上方。
结合图2和图3所示，在支撑结构的上形成有掩膜层和光阻层82，所述掩膜层可以包括第一掩膜层81和第二掩膜层83，第一掩膜层81、第二掩膜层83、光阻层82依次形成在支撑结构表面，第一掩膜层81可以为碳层，第二掩膜层83可以为硬掩模层例如氮化物层等，光阻层82为光刻胶层，可通过旋涂工艺形成在第二掩膜层83表面。
如图4和图5所示，图形化光阻层82，对应使得第一通孔71和第二通孔72区域的光阻层82被去除，通过光阻层82定义出第一通孔71和第二通孔72的位置，将光阻层82的图案转移到掩膜层内并形成贯穿掩膜层的孔洞以形成图形化的掩膜层，这 样可以掩膜层为掩膜，对支撑结构进行图形处理以便于在位线支撑层3内形成第一通孔71，于字线支撑层5内形成第二通孔72。
结合图6至图13所示，图形化支撑结构以用于填充形成接触电路例如位线接触点73和字线接触点74，其中图形化支撑结构的步骤可以分步进行，以使得刻蚀过程中能够同时刻蚀至位线结构2和字线结构4，并能够控制改善形成的位线接触点73的外部轮廓，以便于位线接触点73的形成和电连接。
其中图形化支撑结构以填充形成接触电路包括以下步骤：
如图6和图7所示，图形化支撑结构以在位线支撑层3内形成与位线结构2对应的第一通孔71，同时在字线支撑层5内形成与字线结构4位置对应的第二通孔72以暴露第二氧化物层52，在此步骤中可采用第一刻蚀气体对位线支撑层3和字线支撑层5进行刻蚀。第一刻蚀气体对氧化物层和氮化物层的选择刻蚀比为0.1至0.5。即在同一刻蚀条件下，第一刻蚀气体对氧化物和氮化物的刻蚀速率不同，氧化物层与氮化物层的刻蚀选择比大于等于0.1且小于等于0.5，在此步骤中第一刻蚀气体对氮化物的刻蚀效率比对氧化物的刻蚀效率较快。
在本申请的一些实施例中，第二氮化物层51和部分第一氮化物层31形成在支撑结构的上部，此步骤刻蚀时主要用于对支撑结构的氮化物层进行刻蚀，因此采用对氮化物刻蚀速率较快的第一刻蚀气体，能够加快对位线支撑层3和字线支撑层5上部的氮化物层的刻蚀速率，从而能够增加刻蚀效率，减小刻蚀时间，第二氮化物层51下方为第二氧化物层52，由于待刻蚀材料变化，可调节刻蚀气体改变对氧化物和氮化物的刻蚀选择比。
在一些实施例中，在沿所述第一通孔71刻蚀所述位线支撑层3至预设高度的步骤中，包括同时沿所述第二通孔72对所述第二氧化物层52刻蚀，此步骤中采用第二刻蚀气体对第二氧化物层52和所述位线支撑层3进行刻蚀。
在另一些可能的实施方式中，在沿所述第一通孔71刻蚀所述位线支撑层3至预设高度步骤中，包括采用第二刻蚀气体沿所述第一通孔71刻蚀所述位线支撑层3至预设高度；同时采用所述第二刻蚀气体沿所述第二通孔72对所述第二氧化物层52进行刻蚀。
如图8和图9所示，位线结构2的上表面高于字线结构4的上表面，为了能够同时刻蚀至位线结构2表面和字线结构4表面，通过调节刻蚀气体来改变对氧化物层和氮化物层的刻蚀选择比，使得字线结构4上方的第二氧化物层52刻蚀的更快，加快 字线支撑层5的刻蚀效率。
在本申请实施例中，在刻蚀支撑结构至暴露第二氧化物层52后，调节刻蚀气体，采用第二刻蚀气体对位线支撑层3和字线支撑层5进行刻蚀，直至沿第一通孔71刻蚀位线支撑层3至预设高度位置。其中，第二刻蚀气体对氮化物层和氧化物层的刻蚀选择比为0.5至0.8，此步骤中第二刻蚀气体对氧化物的刻蚀效率大于对氮化物的刻蚀效率。结合图8和图9所示，当采用第二刻蚀气体将位线支撑层3刻蚀至预设高度后，第二刻蚀气体沿第二通孔72刻蚀第二氧化物层52至一定深度，此时第二通孔72的下表面低于第一通孔71的下表面，加快了字线支撑层5的刻蚀速率。
在一些实施例中，在调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，并对所述位线支撑层3继续刻蚀，直至暴露所述位线结构2的步骤中包括：采用第三刻蚀气体并调节刻蚀参数沿所述第一通孔71和所述第二通孔72继续刻蚀至暴露所述字线结构4和所述位线结构2。
在另一些实施方式中，在调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，并对所述位线支撑层3继续刻蚀，直至暴露所述位线结构2的步骤中包括：调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，采用第三刻蚀气体沿所述第一通孔71继续刻蚀所述位线支撑层3，直至暴露所述位线结构2，和采用所述第三刻蚀气体沿所述第二通孔72继续刻蚀所述字线支撑层5，直至暴露所述字线结构4。
如图10和图11所示，调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀，继续沿第一通孔71和第二通孔72向下刻蚀，直至暴露字线结构4和位线结构2，在此步骤中，可采用第三刻蚀气体分别对位线支撑层3和字线支撑层5进行刻蚀，第三刻蚀气体对氮化物层和氧化物层的选择刻蚀比为1.2至1.5，也就是说，调节后第三刻蚀气体使得对氮化物的刻蚀速率大于氧化物的刻蚀速率，由此在位线支撑层3内对第一氮化物层31刻蚀速率大于对第一氧化物层32刻蚀速率快，从而容易在第一通孔71的侧壁上形成一定形状的聚合物层6，从而可控制位线支撑层3内第一通孔71的侧壁轮廓，以便于控制并改善后续形成的位线接触点73的外形轮廓，提高位线接触点73的电连接性能。同时在字线支撑层5内刻蚀第二氧化物层52不容形成副产物，从而使得第二通孔72的侧壁轮廓较为平整，不易弯曲，以有利于后续字线接触点74的形成。其中，在此步骤调节刻蚀参数，所述刻蚀参数可以为刻蚀偏压，刻蚀偏压的功率可以为700W至1100W，由此从而容易在第二通孔72的侧壁氮化物层形成具有 弯曲内壁面的聚合物层6。同时在对字线支撑层5的氧化物层刻蚀时也不容易形成副产物，进而不容易形成曲面内壁，从而能够控制后续填充的字线接触点74的外部轮廓。
如图12和图13所示，于第一通孔71内填充形成位线接触点73，于第二通孔72内填充形成字线接触点74，位线接触点73与位线结构2电连接，字线接触点74与字线结构4电连接。在形成位线接触点73和字线接触点74之前，去除掩膜层和光阻层82，并对支撑结构上方的掩膜层进行酸洗，以控制形成的位线接触点73和字线接触点74的外轮廓，提高位线接触点73和字线接触点74的电连接效果。
本申请实施例还提出了一种半导体器件100，所述半导体器件100采用上述实施例的半导体器件100的制备方法形成。
如图13所示，根据本申请实施例的半导体器件100可以包括：衬底1、字线结构4、位线结构2、支撑结构和聚合物层6。
字线结构4形成在衬底1内，位线结构2形成在衬底1上且跨越字线结构4；支撑结构，支撑结构形成在衬底1上且包括位线支撑层3和字线支撑层5，位线支撑层3包括第一氧化物层32和第一氮化物层31，位线结构2形成在第一氮化物层31内，第一氧化物层32形成在位线结构2两侧且位于第一氮化物层31内，字线支撑层5包括层叠设置的第二氮化物层51、第二氧化物层52和第三氮化物层53，第二氧化物层52形成在第二氮化物层51和第三氮化物层53之间，位线支撑层3内形成有第一通孔71以暴露位线结构2，字线支撑层5内形成有第二通孔72以暴露字线结构4；聚合物层6，聚合物层6形成在第一通孔71内且形成在第一氧化层上方的第一通孔71的部分侧壁上。
在本申请的一些实施例中，聚合物层6的内壁面形成为由第一通孔71的侧壁朝向位线结构2的侧壁的倾斜面，进一步地，倾斜面形成为阶梯状面或弧形面。
如图13所示，半导体器件100还包括位线接触点73和字线接触点74，位线接触点73填充形成在第一通孔71内，字线接触点74填充形成在第二通孔72内。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种半导体器件的制备方法，包括：
    提供衬底，所述衬底内形成有字线结构，所述衬底上形成有支撑结构，所述支撑结构包括位线支撑层和位于所述字线结构上方的字线支撑层，所述位线支撑层内形成有位线结构，所述位线支撑层包括第一氧化物层和第一氮化物层，所述位线结构形成在第一氮化物层内，所述第一氧化物层形成在所述位线结构两侧且位于所述第一氮化物层内；
    图形化所述支撑结构以在所述位线支撑层内形成与所述位线结构对应的第一通孔；
    沿所述第一通孔刻蚀所述位线支撑层至预设高度，调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，并对所述位线支撑层继续刻蚀，直至暴露所述位线结构，以在所述位线结构的上方形成聚合物层，所述聚合物层形成在所述第一通孔的部分侧壁上且位于所述位线结构的两侧。
  2. 根据权利要求1所述的半导体器件的制备方法，其中，所述字线支撑层包括层叠设置的第二氮化物层、第二氧化物层和第三氮化物层，在图形化所述支撑结构以在所述位线支撑层内形成与所述位线结构对应的第一通孔的步骤中，同时在所述位线支撑层内形成与所述字线结构对应的第二通孔以暴露所述第二氧化物层。
  3. 根据权利要求2所述的半导体器件的制备方法，其中，在图形化所述支撑结构以在所述位线支撑层内形成与所述位线结构对应的第一通孔步骤中，采用第一刻蚀气体对所述支撑结构进行刻蚀，所述第一刻蚀气体对氧化物层和氮化物层的刻蚀选择比为0.1至0.5。
  4. 根据权利要求2所述的半导体器件的制备方法，其中，在沿所述第一通孔刻蚀所述位线支撑层至预设高度步骤中，包括同时沿所述第二通孔对所述第二氧化物层刻蚀，此步骤中采用第二刻蚀体对第二氧化物层和所述位线支撑层进行刻蚀。
  5. 根据权利要求2所述的半导体器件的制备方法，其中，在调节刻蚀参数和刻蚀气体对氧化物层和氮化物层的选择刻蚀比，并对所述位线支撑层继续刻蚀，直至暴露所述位线结构的步骤中包括：采用第三刻蚀气体并调节刻蚀参数沿所述第一通孔和所述第二通孔继续刻蚀至暴露所述字线结构和所述位线结构。
  6. 根据权利要求4所述的半导体器件的制备方法，其中，所述第二刻蚀气体对 氮化物层和氧化物层的刻蚀选择比为0.5至0.8。
  7. 根据权利要求5所述的半导体器件的制备方法，其中，所述第三刻蚀气体对氮化物层和氧化物层的刻蚀选择比为1.2至1.5。
  8. 根据权利要求5所述的半导体器件的制备方法，其中，所述刻蚀参数为刻蚀偏压，所述刻蚀偏压功率为700瓦W至1100W。
  9. 根据权利要求2至8任一项所述的半导体器件的制备方法，其中，在图形化所述支撑结构以在所述位线支撑层内形成与所述位线结构对应的第一通孔的步骤进一步包括：
    在所述支撑结构上形成掩膜层及光阻层；
    图形化所述光阻层，使得所述第一通孔和所述第二通孔区域的光阻层被去除；
    将所述光阻层的图案转移到所述掩膜层，形成图形化的掩膜层；
    以所述掩膜层为掩膜，去除部分所述支撑结构以形成所述第一通孔和所述第二通孔。
  10. 根据权利要求9所述的半导体器件的制备方法，其中，还包括以下步骤，于所述第一通孔内填充形成位线接触点，于所述第二通孔内填充形成字线接触点。
  11. 根据权利要求9所述的半导体器件的制备方法，其中，在于所述第一通孔内填充形成位线接触点，于所述第二通孔内填充形成字线接触点之后执行以下步骤；去除所述光阻层和所述掩膜层。
  12. 一种半导体器件，包括：
    衬底；
    字线结构，所述字线结构形成在所述衬底内；
    位线结构，所述位线结构形成在所述衬底上且跨越所述字线结构；
    支撑结构，所述支撑结构形成在所述衬底上且包括位线支撑层和字线支撑层，所述位线支撑层包括第一氧化物层和第一氮化物层，所述位线结构形成在第一氮化物层内，所述第一氧化物层形成在所述位线结构两侧且位于所述第一氮化物层内，所述字线支撑层包括层叠设置的第二氮化物层、第二氧化物层和第三氮化物层，所述第二氧化物层形成在第二氮化物层和第三氮化物层之间，所述位线支撑层内形成有第一通孔以暴露所述位线结构，所述字线支撑层内形成有第二通孔以暴露所述字线结构；
    聚合物层，所述聚合物层形成在所述第一通孔内且形成在所述第一氧化层上方的所述第一通孔的部分侧壁上。
  13. 根据权利要求12所述的半导体器件，其中，所述聚合物层的内壁面形成为由所述第一通孔的侧壁朝向所述位线结构的侧壁的倾斜面。
  14. 根据权利要求13所述的半导体器件，其中，所述倾斜面形成为阶梯状面或弧形面。
  15. 根据权利要求12所述的半导体器件，其中，还包括位线接触点和字线接触点，所述位线接触点填充形成在所述第一通孔内，所述字线接触点填充形成在所述第二通孔内。
PCT/CN2021/100206 2020-09-29 2021-06-15 半导体器件及其制备方法 Ceased WO2022068266A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21873928.2A EP4181202A4 (en) 2020-09-29 2021-06-15 SEMICONDUCTOR COMPONENT AND PRODUCTION METHOD THEREOF
US17/401,412 US11930633B2 (en) 2020-09-29 2021-08-13 Semiconductor device and method for preparing semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011049179.1 2020-09-29
CN202011049179.1A CN114334833B (zh) 2020-09-29 2020-09-29 半导体器件及其制备方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/401,412 Continuation US11930633B2 (en) 2020-09-29 2021-08-13 Semiconductor device and method for preparing semiconductor device

Publications (1)

Publication Number Publication Date
WO2022068266A1 true WO2022068266A1 (zh) 2022-04-07

Family

ID=80949239

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/100206 Ceased WO2022068266A1 (zh) 2020-09-29 2021-06-15 半导体器件及其制备方法

Country Status (2)

Country Link
CN (1) CN114334833B (zh)
WO (1) WO2022068266A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160351501A1 (en) * 2015-05-27 2016-12-01 SK Hynix Inc. Semiconductor device having air-gap and method for manufacturing the same
CN109003938A (zh) * 2018-07-26 2018-12-14 长鑫存储技术有限公司 半导体接触结构、存储器结构及其制备方法
CN109768014A (zh) * 2017-11-09 2019-05-17 三星电子株式会社 存储器件及其制造方法
CN111584489A (zh) * 2020-05-29 2020-08-25 福建省晋华集成电路有限公司 半导体存储器件与其制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100449030B1 (ko) * 2002-01-24 2004-09-16 삼성전자주식회사 스택형 캐패시터 및 그의 제조방법
KR100481209B1 (ko) * 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
KR100558194B1 (ko) * 2003-10-17 2006-03-10 삼성전자주식회사 높은 식각 선택비를 갖는 식각 조성물, 이의 제조 방법,이를 이용한 산화막의 선택적 식각 방법 및 반도체 장치의제조 방법
JP2009267432A (ja) * 2009-06-29 2009-11-12 Elpida Memory Inc 半導体集積回路装置の製造方法
CN102386127B (zh) * 2010-09-03 2014-05-21 中芯国际集成电路制造(上海)有限公司 制作半导体器件结构的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160351501A1 (en) * 2015-05-27 2016-12-01 SK Hynix Inc. Semiconductor device having air-gap and method for manufacturing the same
CN109768014A (zh) * 2017-11-09 2019-05-17 三星电子株式会社 存储器件及其制造方法
CN109003938A (zh) * 2018-07-26 2018-12-14 长鑫存储技术有限公司 半导体接触结构、存储器结构及其制备方法
CN111584489A (zh) * 2020-05-29 2020-08-25 福建省晋华集成电路有限公司 半导体存储器件与其制作方法

Also Published As

Publication number Publication date
CN114334833B (zh) 2024-07-02
CN114334833A (zh) 2022-04-12

Similar Documents

Publication Publication Date Title
JP5084074B2 (ja) 半導体素子の自己整合コンタクト形成方法
KR950012554B1 (ko) 고집적 반도체소자의 전하저장전극 제조방법
CN112992669B (zh) 半导体结构及其形成方法
WO2021258561A1 (zh) 存储器的形成方法及存储器
CN103390551B (zh) 半导体装置图案化结构的制作方法
CN104517955B (zh) 半导体基板及其制造方法
CN112447513A (zh) 半导体结构及其形成方法
WO2021233269A1 (zh) 半导体器件中孔、半导体器件的制备方法及半导体器件
WO2022068266A1 (zh) 半导体器件及其制备方法
US11930633B2 (en) Semiconductor device and method for preparing semiconductor device
US20220020630A1 (en) Manufacturing method of semiconductor structure
CN115223863A (zh) 半导体结构的制作方法
CN115241201A (zh) 一种三维存储器的制作方法以及三维存储器
CN113658955B (zh) 一种半导体结构及其形成方法
CN114093754B (zh) 一种硬掩模图案的制造方法和dram电容的制造方法
KR100440079B1 (ko) 반도체소자의 자기정렬적인 콘택 형성방법
KR100440076B1 (ko) 반도체소자의 자기정렬적인 콘택 형성방법
CN116417332B (zh) 半导体结构的制造方法
KR100319166B1 (ko) 반도체소자의 금속배선 형성방법
CN113964089B (zh) 半导体结构的形成方法及半导体结构
US20220216217A1 (en) Method for forming bit line contact structure and semiconductor structure
KR100910868B1 (ko) 반도체소자 제조 방법
KR20010064074A (ko) 반도체 소자의 자기정렬 콘택홀 형성방법
KR100310543B1 (ko) 반도체소자의 형성방법
KR100250741B1 (ko) 반도체 소자의 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21873928

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021873928

Country of ref document: EP

Effective date: 20230208

NENP Non-entry into the national phase

Ref country code: DE