WO2022068350A1 - 异质结电池及其制备方法和应用 - Google Patents

异质结电池及其制备方法和应用 Download PDF

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Publication number
WO2022068350A1
WO2022068350A1 PCT/CN2021/108942 CN2021108942W WO2022068350A1 WO 2022068350 A1 WO2022068350 A1 WO 2022068350A1 CN 2021108942 W CN2021108942 W CN 2021108942W WO 2022068350 A1 WO2022068350 A1 WO 2022068350A1
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Prior art keywords
amorphous silicon
transparent conductive
conductive oxide
silicon layer
oxide layer
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English (en)
French (fr)
Inventor
黄强
崔艳峰
谷士斌
蔡涔
任明冲
周学谦
张莹
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Risen Energy Changzhou Co Ltd
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Risen Energy Changzhou Co Ltd
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Priority to AU2021354681A priority Critical patent/AU2021354681B2/en
Priority to EP21874012.4A priority patent/EP4207312A4/en
Publication of WO2022068350A1 publication Critical patent/WO2022068350A1/zh
Priority to US18/127,007 priority patent/US12490545B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/90—Structures for connecting between photovoltaic cells, e.g. interconnections or insulating spacers
    • H10F19/902—Structures for connecting between photovoltaic cells, e.g. interconnections or insulating spacers for series or parallel connection of photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/90—Structures for connecting between photovoltaic cells, e.g. interconnections or insulating spacers
    • H10F19/902—Structures for connecting between photovoltaic cells, e.g. interconnections or insulating spacers for series or parallel connection of photovoltaic cells
    • H10F19/906—Structures for connecting between photovoltaic cells, e.g. interconnections or insulating spacers for series or parallel connection of photovoltaic cells characterised by the materials of the structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/10—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material
    • H10F71/103—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/40—Optical elements or arrangements
    • H10F77/42—Optical elements or arrangements directly associated or integrated with photovoltaic cells, e.g. light-reflecting means or light-concentrating means
    • H10F77/484—Refractive light-concentrating means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/707—Surface textures, e.g. pyramid structures of the substrates or of layers on substrates, e.g. textured ITO layer on a glass substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the technical field of solar cells, in particular to heterojunction cells and their preparation methods and applications.
  • the material for the transparent conductive oxide layer in the heterojunction cell usually includes indium tin oxide (ITO). expensive.
  • ITO indium tin oxide
  • the heterojunction cell When the heterojunction cell is further prepared into a heterojunction cell assembly, since the growth temperature of the heterojunction cell is below 200 °C, the conventional ribbon and stringer cannot be used, and a low-temperature ribbon and a low-temperature stringer are required. , the equipment is expensive, further increasing the production cost.
  • a heterojunction cell includes a substrate and a first intrinsic amorphous silicon layer, an N-type doping layer, and a first intrinsic amorphous silicon layer disposed on one side of the substrate in sequence.
  • the amorphous silicon layer, the first transparent conductive oxide layer and the first dielectric film are sequentially stacked and disposed on the other side of the substrate.
  • the second intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer, the first two transparent conductive oxide layers and a second dielectric film, the heterojunction cell further includes a first metal mesh and a second metal mesh, the first metal mesh penetrates the first dielectric film and is connected to the The first transparent conductive oxide layer is fixedly connected, the second metal mesh penetrates the second dielectric film and is fixedly connected with the second transparent conductive oxide layer, wherein the first metal mesh and the The second metal mesh is composed of several first metal wires and several second metal wires, and the first metal wires are perpendicular to the second metal wires.
  • the first metal mesh and the second metal mesh composed of the first metal wire and the second metal wire are used as metal electrodes, which avoids the use of expensive resin-type low-temperature curing silver paste, and greatly reduces the cost. production cost.
  • the material of the first metal wire and/or the second metal wire includes at least one of copper, silver, gold, tin or aluminum.
  • the diameter of the first metal wire is greater than or equal to the diameter of the second metal wire; the diameter of the first metal wire is 0.1 mm-10 mm, and the diameter of the second metal wire is 0.1mm-10mm.
  • the cross-sectional shape of the first metal wire and/or the second metal wire is a rectangle, a square, a cylinder or a triangle.
  • the first metal mesh and the first transparent conductive oxide layer are fixedly connected through an adhesive layer, and the second metal mesh and the first transparent conductive oxide layer are connected through an adhesive layer Fixed connection.
  • the material of the adhesive layer includes at least one of conductive adhesive, hot melt adhesive, or nanomaterials containing Ag particles.
  • the hot-melt adhesive includes polyethylene hot-melt adhesive or ethylene copolymer hot-melt adhesive hot-melt adhesive.
  • the material of the first transparent conductive oxide layer and/or the second transparent conductive oxide layer includes ITO, IWO, AZO, FTO, In 2 O 3 :ZnO or SnO 2 at least one.
  • the material of the first dielectric film and/or the material of the second dielectric film includes at least one of SiN, SiO x , AlO x , MgF 2 or TiO 2 .
  • the refractive index of the first transparent conductive oxide layer is greater than the refractive index of the first dielectric film, and the refractive index of the second transparent conductive oxide layer is greater than that of the second dielectric film The refractive index of the film.
  • the thickness of the first intrinsic amorphous silicon layer is 1 nm-10 nm; the thickness of the N-type doped amorphous silicon layer is 1 nm-30 nm; the thickness of the first transparent conductive oxide layer The thickness of the first dielectric film is 1 nm-100 nm; the thickness of the first dielectric film is 1 nm-100 nm.
  • the thickness of the second intrinsic amorphous silicon layer is 1 nm-10 nm; the thickness of the P-type doped amorphous silicon layer is 1 nm-30 nm; the thickness of the second transparent conductive oxide layer is 1 nm-100 nm, and the thickness of the second dielectric film is 1 nm-100 nm.
  • a method for preparing a heterojunction battery as described above comprising the following steps:
  • a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer are grown on one side of the texturing substrate, and a second intrinsic amorphous silicon layer is grown on the surface of the texturing substrate away from the first intrinsic amorphous silicon layer.
  • Two intrinsic amorphous silicon layers and P-type doped amorphous silicon layers, the growth temperature is 100 °C-250 °C;
  • a first transparent conductive oxide layer is deposited on the surface of the N-type doped amorphous silicon layer away from the first intrinsic amorphous silicon layer, and a first transparent conductive oxide layer is deposited on the surface of the P-type doped amorphous silicon layer away from the second intrinsic amorphous silicon layer.
  • a second transparent conductive oxide layer is deposited on the surface of the amorphous silicon layer, and the growth temperature is 25°C-250°C;
  • a first metal mesh is fixed on the surface of the first transparent conductive oxide layer away from the N-type doped amorphous silicon layer, and on the surface of the second transparent conductive oxide layer away from the P-type doped amorphous silicon layer securing the second metal mesh;
  • a first dielectric film is deposited on the surface of the first transparent conductive oxide layer away from the N-type doped amorphous silicon layer, and on the surface of the second transparent conductive oxide layer away from the P-type doped amorphous silicon layer
  • a second dielectric film is deposited on the surface to obtain a heterojunction cell, and the growth temperature is 25°C-250°C.
  • the above-mentioned preparation method of the heterojunction battery can realize the simple preparation of the low-cost heterojunction battery, and is suitable for industrial production.
  • the fixing method includes fixing through an adhesive layer.
  • a heterojunction battery assembly includes two or more heterojunction batteries as described above or prepared by the method for preparing a heterojunction battery as described above.
  • Heterojunction cells, the heterojunction cells are connected in series through adhesive conductive materials, and the heterojunction cells have the same conversion efficiency.
  • the heterojunction batteries are connected in series by the conductive material with adhesiveness, and no welding tape is required for welding, which greatly simplifies the preparation process of the heterojunction battery assembly, reduces the preparation cost, and reduces the cost of the process.
  • the reduction also reduces the difficulty of production control, thereby improving the product qualification rate; at the same time, it also eliminates the need for screen printing, sintering furnaces and other equipment, further reducing equipment costs.
  • the adhesive conductive material includes at least one of a conductive tape, a conductive glue, or a nanomaterial containing Ag particles.
  • FIG. 1 is a cross-sectional view of an embodiment of a heterojunction battery of the present application.
  • FIG. 2 is a top view of an embodiment of the first metal mesh of the present application.
  • FIG. 3 is a schematic structural diagram of an embodiment of the provided heterojunction cell assembly of the present application.
  • the heterojunction battery provided by the present application and its preparation method and application will be further described below.
  • FIG. 1 is a cross-sectional view of a heterojunction cell 100 according to an embodiment of the present application.
  • the heterojunction cell 100 includes a substrate 10 and a first intrinsic amorphous layer stacked on one side of the substrate 10 in sequence.
  • the silicon layer 20 , the N-type doped amorphous silicon layer 30 , the first transparent conductive oxide layer 60 and the first dielectric film 901 are sequentially stacked on the second intrinsic amorphous silicon layer 40 disposed on the other side of the substrate 10 , P-type doped amorphous silicon layer 50, second transparent conductive oxide layer 70 and second dielectric film 902,
  • the heterojunction cell 100 further includes a first metal mesh 801 and a second metal mesh 802, the first metal mesh 801 penetrates the first dielectric film 901 and is fixedly connected to the first transparent conductive oxide layer 60 , and the second metal mesh 802 penetrates the second dielectric film 902 and is fixedly connected to the second transparent conductive oxide layer 70 .
  • the stacking arrangement can be achieved by deposition or growth.
  • the doped amorphous silicon layer 50 is stacked by growth, and the first transparent conductive oxide layer 60 , the second transparent conductive oxide layer 70 , the first dielectric film 901 , and the second dielectric film 902 are stacked by deposition.
  • FIG. 2 is a top view of an embodiment of the first metal mesh 801 of the present application. It can be understood that the first metal mesh 801 and the second metal mesh 802 are both composed of several first metal wires 8011 and several second metal wires 8012 Composition, the first metal wire 8011 is perpendicular to the second metal wire 8012 .
  • the substrate 10 includes an N-type silicon substrate or a P-type silicon substrate.
  • the material of the first metal wire 8011 and/or the second metal wire 8012 includes at least one of copper, silver, gold, tin or aluminum.
  • the material of the first metal wire 8011 and the material of the second metal wire 8012 may be the same or different.
  • the size of the first metal wire 8011 is greater than or equal to the size of the second metal wire 8012; the size of the first metal wire 8011 is 0.1 mm-10 mm, optionally, the size of the first metal wire 8011 is 0.1mm-0.2mm, the size of the second metal wire 8012 is 0.1mm-10mm, optionally, the size of the second metal wire 8012 is 0.1mm-0.15mm.
  • a dimension is a diameter specifically.
  • the cross-sectional shape of the first metal wire 8011 and/or the second metal wire 8012 is a rectangle, a square, a cylinder or a triangle, in order to increase the size of the metal mesh 80 and the first transparent conductive oxide layer 60 and the The contact area of the two transparent conductive oxide layers 70 increases the diffuse reflection effect of light, and the cross-sectional shape of the first metal wire 8011 and/or the second metal wire 8012 can be selected as a triangle. It should be noted that the cross-sectional shape is specifically a cross-sectional shape.
  • first metal mesh 801 and the first transparent conductive oxide layer 60 are fixedly connected through an adhesive layer
  • second metal mesh 802 and the first transparent conductive oxide layer 60 are fixedly connected through an adhesive layer
  • the adhesive layer material may or may not have conductivity.
  • the adhesive layer material includes at least one of conductive adhesive, hot melt adhesive, or nanomaterials containing Ag particles. A sort of.
  • the hot melt adhesive comprises polyethylene hot melt adhesive or ethylene copolymer hot melt adhesive.
  • the material of the first transparent conductive oxide layer 60 and/or the second transparent conductive oxide layer 70 includes at least one of ITO, IWO, AZO, FTO, In 2 O 3 :ZnO or SnO 2 kind.
  • the material of the first transparent conductive oxide layer 60 and/or the second transparent conductive oxide layer 70 includes ITO.
  • the thickness of the first transparent conductive oxide layer 60 is 1 nm-100 nm
  • the thickness of the second transparent conductive oxide layer 70 is 1 nm-100 nm.
  • the material of the first dielectric film 901 and/or the material of the second dielectric film 902 includes at least one of SiN, SiO x , AlO x , MgF 2 or TiO 2 .
  • the material of the first dielectric film 901 and/or the material of the second dielectric film 902 includes SiN.
  • the thickness of the first dielectric film 901 is 1 nm-100 nm, and the thickness of the second dielectric film 902 is 1 nm-100 nm; Thickness is 1nm-70nm.
  • the refractive index of the first transparent conductive oxide layer 60 is greater than the refractive index of the first dielectric film 901
  • the refractive index of the second transparent conductive oxide layer 70 is greater than the refractive index of the second dielectric film 902 .
  • the stacking of the dielectric film 90 and the transparent conductive oxide layer in the heterojunction cell 100 of the present application can form an anti-reflection structure, enhance the transmitted light, so that more light enters the heterojunction cell 100 , and the heterojunction cell 100
  • the current density and conversion efficiency are improved, and the thickness of the transparent conductive oxide layer can be reduced, thereby further reducing the production cost of the heterojunction cell 100 .
  • the thickness of the first intrinsic amorphous silicon layer 20 is 1 nm-10 nm; the thickness of the N-type doped amorphous silicon layer 30 is 1 nm-30 nm.
  • the thickness of the second intrinsic amorphous silicon layer 40 is 1 nm-10 nm; the thickness of the P-type doped amorphous silicon layer 50 is 1 nm-30 nm.
  • the above heterojunction cell 100 uses the first metal mesh 801 and the second metal mesh 802 composed of the first metal wire 8011 and the second metal wire 8012 as electrodes, avoiding the use of expensive resin-type low-temperature curing silver paste, Greatly reduces production costs.
  • the preparation method of the heterojunction battery provided by this application includes the following steps:
  • the intrinsic amorphous silicon layer 40 and the P-type doped amorphous silicon layer 50 are both grown at a temperature of 100°C to 250°C;
  • a second transparent conductive oxide layer 70 is deposited on the surface of the crystalline silicon layer 40, and the growth temperature is 25°C-250°C;
  • a second dielectric film 902 is deposited on the surface of the film, and the growth temperature is 25° C.-250° C. to obtain a heterojunction cell.
  • the step S1 includes: using an alkaline solution to perform a texturing treatment on the substrate 10 to obtain a textured substrate.
  • the alkaline solution includes NaOH or KOH.
  • step S2 adopts plasma enhanced chemical vapor deposition equipment.
  • the deposition method of the first transparent conductive oxide layer 60 and the second transparent conductive oxide layer 70 includes magnetron sputtering deposition, reactive plasma deposition or electron beam evaporation deposition.
  • the deposition temperature of the first transparent conductive oxide layer 60 and the second transparent conductive oxide layer 70 can be selected from 25°C to 250°C.
  • the fixing method includes fixing by an adhesive layer, specifically including: coating the material of the adhesive layer on one side of the first metal mesh 801 and the second metal mesh 802, and attaching the first transparent conductive oxide layer 60 One side is fixed with the side of the first metal mesh 801 coated with the material of the adhesive layer, and the side of the second transparent conductive oxide layer 70 is fixed with the side of the second metal mesh 802 coated with the material of the adhesive layer.
  • the deposition method includes plasma-enhanced chemical vapor deposition or atomic layer deposition.
  • the deposition temperature of the first dielectric film 901 and the second dielectric film 902 can be selected from 100°C to 250°C.
  • the contact portion of the first metal mesh 801 and the first transparent conductive oxide layer 60 and the second metal mesh 802 and the The annealing treatment of the contact portion of the second transparent conductive oxide layer 70 increases the surface doping concentration of the first transparent conductive oxide layer 60 and the second transparent conductive oxide layer 70.
  • a certain annealing temperature makes the first metal The bonding force between the mesh 801 and the first transparent conductive oxide layer 60 and the second metal mesh 802 and the second transparent conductive oxide layer is increased, forming a good contact.
  • the preparation method of the heterojunction battery provided by the present application can realize the simple preparation of the low-cost heterojunction battery 100, and is suitable for industrial production.
  • the heterojunction cell assembly 130 provided by the present application includes two or more heterojunction cells 100 as described above or the heterojunction cells 100 prepared by the above-mentioned method for preparing a heterojunction cell, and between the heterojunction cells 100 By connecting the conductive materials 110 with adhesive properties in series, the heterojunction cells 100 have the same conversion efficiency.
  • the conversion efficiency of the heterojunction cell 100 can be tested with a copper test bench.
  • the copper test bench is equipped with a plurality of metal wires on both sides to replace the traditional probe bar, which is usually used to test the battery without the busbar. .
  • the adhesive conductive material 110 includes at least one of conductive tape, conductive glue or nanomaterials containing Ag particles.
  • the heterojunction cells 100 are connected in series through the adhesive conductive material 110, and no welding tape is required for welding, which greatly simplifies the preparation process of the heterojunction cell assembly 130.
  • the preparation cost is reduced, and the reduction of the process also reduces the difficulty of production control, thereby improving the product qualification rate; at the same time, equipment such as screen printing and sintering furnaces are eliminated, further reducing equipment costs.
  • heterojunction battery and its preparation method and application will be further described by the following specific examples.
  • the substrate 10 is subjected to a texturing treatment with a NaOH solution to obtain a textured substrate; wherein, the substrate 10 is an N-type silicon substrate.
  • a first intrinsic amorphous silicon layer 20 with a thickness of 5 nm and an N-type doped amorphous silicon layer 30 with a thickness of 15 nm are grown on the surface of the textured substrate 10 by using a plasma-enhanced chemical vapor deposition (PECVD) device;
  • a second intrinsic amorphous silicon layer 40 with a thickness of 5 nm and a P-type doped amorphous silicon layer 50 with a thickness of 15 nm are grown on the surface of the wool substrate away from the first intrinsic amorphous silicon layer 20.
  • the growth temperature of the N-type doped amorphous silicon layer 30, the second intrinsic amorphous silicon layer 40 and the P-type doped amorphous silicon layer 50 is all 200°C.
  • a first transparent conductive oxide layer 60 with a thickness of 50 nm is deposited on the surface of the N-type doped amorphous silicon layer 30 away from the first intrinsic amorphous silicon layer 20 by the method of reactive plasma deposition.
  • a second transparent conductive oxide layer 70 with a thickness of 50 nm is deposited on the surface of the layer 50 away from the second intrinsic amorphous silicon layer 40, and the growth temperature of the first transparent conductive oxide layer 60 and the second transparent conductive oxide layer 70 are both 100 °C, the materials of the first transparent conductive oxide layer 60 and the second transparent conductive oxide layer 70 are both ITO.
  • a first metal mesh 801 is fixed as an electrode on the surface of the first transparent conductive oxide layer 60 away from the N-type doped amorphous silicon layer 30 by conductive glue, and the second transparent conductive oxide layer 70 is away from the P-type doped amorphous silicon layer.
  • the second metal mesh 802 is fixed on the surface of the layer 50 as an electrode by means of conductive glue.
  • the first metal mesh 801 and the second metal mesh 802 are both composed of a plurality of first metal wires 8011 and a plurality of second metal wires 8012.
  • the second metal wire 8012 is vertical, the diameter of the first metal wire 8011 is 0.2 mm, and the cross-sectional shape is triangular.
  • the diameter of the second metal wire 8012 is 0.15 mm, and the cross-sectional shape is triangular.
  • Plasma-enhanced chemical vapor deposition is used to deposit a first dielectric film 901 with a thickness of 40 nm on the surface of the first transparent conductive oxide layer 60 away from the N-type doped amorphous silicon layer 30, and a first dielectric film 901 with a thickness of 40 nm is deposited on the surface of the second transparent conductive oxide layer 70 away from the N-type doped amorphous silicon layer 30.
  • a second dielectric film 902 with a thickness of 40 nm is deposited on the surface of the P-type doped amorphous silicon layer 50 to obtain the heterojunction cell 100.
  • the growth temperatures of the first dielectric film 901 and the second dielectric film 902 are both 200°C.
  • the materials of the first dielectric film 901 and the second dielectric film 902 include SiN, so that an ITO/SiN laminated anti-reflection structure is formed outside the regions of the first metal mesh 801 and the second metal mesh 802 .
  • the electrical properties of the heterojunction cells 100 are tested and sorted by the wire method used in busbarless cells, and 12 heterojunction cells 100 with the same gear (same conversion efficiency) are selected, and conductive tape is used to bond them on the heterojunction cells.
  • the positive and negative electrodes (that is, the metal mesh 80) of the adjacent two heterojunction cells 100 are connected at the head and tail ends of the battery 100 to form a series connection, and then typesetting is performed, and an ethylene-vinyl acetate copolymer (EVA) film is attached, and then Lamination is performed, glue is applied, and the frame 130 is attached to obtain the heterojunction battery assembly 130 as shown in FIG. 3 .
  • EVA ethylene-vinyl acetate copolymer
  • the substrate 10 is subjected to a texturing treatment with a NaOH solution to obtain a textured substrate; wherein, the substrate 10 is an N-type silicon substrate.
  • a first intrinsic amorphous silicon layer 20 with a thickness of 8 nm and an N-type doped amorphous silicon layer 30 with a thickness of 25 nm are grown on the surface of the textured substrate 10 by using plasma enhanced chemical vapor deposition (PECVD) equipment;
  • a second intrinsic amorphous silicon layer 40 with a thickness of 8 nm and a P-type doped amorphous silicon layer 50 with a thickness of 25 nm are grown on the surface of the wool substrate away from the first intrinsic amorphous silicon layer 20.
  • the first intrinsic amorphous silicon layer is 20.
  • the growth temperature of the N-type doped amorphous silicon layer 30, the second intrinsic amorphous silicon layer 40 and the P-type doped amorphous silicon layer 50 is all 100°C.
  • a first transparent conductive oxide layer 60 with a thickness of 80 nm is deposited on the surface of the N-type doped amorphous silicon layer 30 away from the first intrinsic amorphous silicon layer 20 by using the deposition method of electron beam evaporation.
  • a second transparent conductive oxide layer 70 with a thickness of 80 nm is deposited on the surface of the crystalline silicon layer 50 away from the second intrinsic amorphous silicon layer 40, and the growth temperatures of the first transparent conductive oxide layer 60 and the second transparent conductive oxide layer 70 are the same. At 25° C., the materials of the first transparent conductive oxide layer 60 and the second transparent conductive oxide layer 70 are both ITO.
  • the first metal mesh 801 is fixed as an electrode on the surface of the first transparent conductive oxide layer 60 away from the N-type doped amorphous silicon layer 30 by polyethylene hot melt adhesive, and the second transparent conductive oxide layer 70 is far away from the P-type doping layer.
  • the surface of the amorphous silicon layer 50 is fixed with a second metal mesh 802 as an electrode by polyethylene hot melt adhesive.
  • the first metal mesh 801 and the second metal mesh 802 are both composed of several first metal wires 8011 and several second metal wires 8012
  • the first metal wire 8011 is perpendicular to the second metal wire 8012, the diameter of the first metal wire 8011 is 0.15 mm, and the cross-sectional shape is circular, and the diameter of the second metal wire 8012 is 0.15 mm, and the cross-sectional shape is circular.
  • Atomic layer deposition method is used to deposit a first dielectric film 901 with a thickness of 60 nm on the surface of the first transparent conductive oxide layer 60 away from the N-type doped amorphous silicon layer 30, and on the second transparent conductive oxide layer 70 away from the P-type dopant layer.
  • a second dielectric film 902 with a thickness of 60 nm is deposited on the surface of the hetero-amorphous silicon layer 50 to obtain the heterojunction cell 100.
  • the growth temperature of the first dielectric film 901 and the growth temperature of the second dielectric film 902 is both 150 °C, the material of the first dielectric film 901 and the second dielectric film 902 includes TiO2, so that an ITO/TiO2 laminated anti-reflection structure is formed outside the regions of the first metal mesh 801 and the second metal mesh 802.
  • the electrical properties of the heterojunction cells 100 are tested and sorted by the wire method used in busbarless cells, and 12 heterojunction cells 100 with the same grade (same conversion efficiency) are selected, and nano-silver colloids are used to bond the heterojunction cells 100 to the heterojunction cells.
  • the positive and negative electrodes (ie the metal meshes 80) of two adjacent heterojunction cells 100 are connected to form a series connection, and then typesetting is performed, and an ethylene-vinyl acetate copolymer (EVA) film is attached. Then, lamination is performed, glue is applied, and the frame 130 is installed to obtain the heterojunction battery assembly 130 as shown in FIG. 3 .

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Abstract

一种异质结电池及其制备方法和应用。该异质结电池包括衬底(10)、第一本征非晶硅层(20)、N型掺杂非晶硅层(30)、第一透明导电氧化物层(60)、第二本征非晶硅层(40)、P型掺杂非晶硅层(50)、第二透明导电氧化物层(70)以及介电薄膜(90)，该异质结电池(100)还包括金属网(80)，金属网(80)穿透介电薄膜(90)并分别与第一透明导电氧化物层(60)以及第二透明导电氧化物层(70)固定连接，其中，金属网(80)由若干第一金属丝(8011)和若干第二金属丝(8012)组成，第一金属丝(8011)与第二金属丝(8012)垂直。

Description

异质结电池及其制备方法和应用
相关申请
本申请要求2020年9月29日申请的，申请号为202011053423.1，发明名称为“一种异质结电池及其制备方法和组件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及太阳能电池技术领域，特别是涉及异质结电池及其制备方法和应用。
背景技术
在传统的异质结电池中，通常采用树脂型低温固化银浆作为电极，电阻率高，导电性差，为了提高导电性，需要提高金属电极的宽度或者高度，导致电池的银浆耗量增加，5BB主栅结构的异质结电池银浆耗量在300mg左右，比市场主流的PERC电池高200mg以上。即使采用最新的多主栅技术，银浆耗量仍然在150mg以上。因此异质结电池成本偏高，几乎占到了电池非硅生产成本的一半以上。
另外，异质结电池中透明导电氧化物层的材料通常包括氧化铟锡(ITO)，氧化铟锡中的金属铟In属于稀有金属，地壳含量稀少，进而导致溅射氧化铟锡所用的靶材价格昂贵。
将异质结电池进一步制备成异质结电池组件时，由于异质结电池的生长温度在200℃以下，因此不能采用常规的焊带和串焊机，需要使用低温焊带和低温串焊机，设备价格昂贵，进一步增加生产成本。
发明内容
根据本申请的各种实施例，提供一种异质结电池，该异质结电池包括衬底以及依次层叠设置于所述衬底的一面的第一本征非晶硅层、N型掺杂非晶硅层、第一透明导电氧化物层和第一介电薄膜，依次层叠设置于所述衬底的另一面的第二本征非晶硅层、P型掺杂非晶硅层、第二透明导电氧化物层和第二介电薄膜，所述异质结电池还包括第一金属网和第二金属网，所述第一金属网穿透所述第一介电薄膜并与所述第一透明导电氧化物层固定连接，所述第二金属网穿透所述第二介电薄膜并与所述第二透明导电氧化物层固定连接，其中，所述第一金属网和所述第二金属网均由若干第一金属丝和若干第二金属丝组成，所述第一金属丝与所述第二金属丝垂直。
上述异质结电池中，采用由第一金属丝与第二金属丝组成的第一金属网和第二金属网作为金属电极，避免了价格高昂的树脂型低温固化银浆的使用，极大降低了生产成本。
在其中一个实施例中，所述第一金属丝和/或所述第二金属丝的材质包括铜、银、金、锡或铝中的至少一种。
在其中一个实施例中，所述第一金属丝的直径大于或等于所述第二金属丝的直径；所述第一金属丝的直径为0.1mm-10mm，所述第二金属丝的直径为0.1mm-10mm。
在其中一个实施例中，所述第一金属丝和/或所述第二金属丝的横截面形状为长方形、正方形、圆柱形或三角形。
在其中一个实施例中，所述第一金属网与所述第一透明导电氧化物层通过粘结层固定连接，所述第二金属网与所述第一透明导电氧化物层通过粘结层固 定连接。
在其中一个实施例中，所述粘结层的材料包括导电胶、热熔胶或含有Ag颗粒的纳米材料中的至少一种。
在其中一个实施例中，所述热熔胶包括聚乙烯热熔胶或乙烯共聚物热熔胶热熔胶。
在其中一个实施例中，所述第一透明导电氧化物层和/或所述第二透明导电氧化物层的材料包括ITO、IWO、AZO、FTO、In 2O 3:ZnO或SnO 2中的至少一种。
在其中一个实施例中，所述第一介电薄膜的材料和/或所述第二介电薄膜的材料包括SiN、SiO x、AlO x、MgF 2或TiO 2中的至少一种。
在其中一个实施例中，所述第一透明导电氧化物层的折射率大于所述第一介电薄膜的折射率，所述第二透明导电氧化物层的折射率大于所述第二介电薄膜的折射率。
在其中一个实施例中，所述第一本征非晶硅层的厚度为1nm-10nm；所述N型掺杂非晶硅层的厚度为1nm-30nm；所述第一透明导电氧化物层的厚度为1nm-100nm；所述第一介电薄膜的厚度为1nm-100nm。
在其中一个实施例中，所述第二本征非晶硅层的厚度为1nm-10nm；所述P型掺杂非晶硅层的厚度为1nm-30nm；第二透明导电氧化物层的厚度为1nm-100nm，所述第二介电薄膜的厚度为1nm-100nm。
根据本申请的各种实施例，提供一种如上述的异质结电池的制备方法，该制备方法包括以下步骤：
对衬底进行制绒处理，得到制绒衬底；
在所述制绒衬底的一面生长第一本征非晶硅层和N型掺杂非晶硅层，在所述制绒衬底远离所述第一本征非晶硅层的表面生长第二本征非晶硅层和P型掺 杂非晶硅层，生长温度均为100℃-250℃；
在所述N型掺杂非晶硅层远离所述第一本征非晶硅层的表面沉积第一透明导电氧化物层，在所述P型掺杂非晶硅层远离所述第二本征非晶硅层的表面沉积第二透明导电氧化物层，生长温度均为25℃-250℃；
在所述第一透明导电氧化物层远离所述N型掺杂非晶硅层的表面固定第一金属网，在所述第二透明导电氧化物层远离P型掺杂非晶硅层的表面固定第二金属网；以及
在所述第一透明导电氧化物层远离所述N型掺杂非晶硅层的表面沉积第一介电薄膜，在所述第二透明导电氧化物层远离P型掺杂非晶硅层的表面沉积第二介电薄膜，得到异质结电池，生长温度均为25℃-250℃。
上述异质结电池的制备方法能够实现低成本的异质结电池的简单制备，适用于工业化生产。
在其中一个实施例中，所述固定的方式包括通过粘结层固定。
根据本申请的各种实施例，提供一种异质结电池组件，该异质结电池组件包括两个以上的如上述的异质结电池或者如上述的异质结电池的制备方法制备得到的异质结电池，所述异质结电池之间通过具有粘结性的导电材料串联，所述异质结电池之间具有相同的转换效率。
上述异质结电池组件中，异质结电池之间通过具有粘结性的导电材料串联，无需焊带进行焊接，极大地简化了异质结电池组件的制备流程，降低了制备成本，工序的减少也降低了生产控制的难度，进而提高了产品合格率；同时，还免去了丝网印刷、烧结炉等设备，进一步降低设备成本。
在其中一个实施例中，所述具有粘结性的导电材料包括导电胶带、导电胶或含有Ag颗粒的纳米材料中的至少一种。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为本申请异质结电池的一实施方式的截面图。
图2为本申请第一金属网的一实施方式的俯视图。
图3为提供的本申请异质结电池组件的一实施方式的结构示意图。
图中，10、衬底；20、第一本征非晶硅层；30、N型掺杂非晶硅层；40、第二本征非晶硅层；50、P型掺杂非晶硅层；60、第一透明导电氧化物层；70、第二透明导电氧化物层；80、金属网；801、第一金属网；802、第二金属网；8011、第一金属丝；8012、第二金属丝；90、介电薄膜；901、第一介电薄膜；902、第二介电薄膜；100、异质结电池；110、导电材料；120、边框；130、异质结电池组件。
具体实施方式
以下将对本申请提供的异质结电池及其制备方法和应用作进一步说明。
如图1所示为本申请提供的一实施方式的异质结电池100的截面图，该异质结电池100包括衬底10以及依次层叠设置于衬底10的一面的第一本征非晶硅层20、N型掺杂非晶硅层30、第一透明导电氧化物层60和第一介电薄膜901，依次层叠设置于衬底10的另一面的第二本征非晶硅层40、P型掺杂非晶硅层50、第二透明导电氧化物层70和第二介电薄膜902，异质结电池100还包括第一金 属网801和第二金属网802，第一金属网801穿透第一介电薄膜901并与第一透明导电氧化物层60固定连接，第二金属网802穿透第二介电薄膜902并与第二透明导电氧化物层70固定连接。
可以理解的，层叠设置可以通过沉积或者生长来实现，可选的，第一本征非晶硅层20、N型掺杂非晶硅层30、第二本征非晶硅层40、P型掺杂非晶硅层50通过生长实现层叠设置，第一透明导电氧化物层60、第二透明导电氧化物层70、第一介电薄膜901、第二介电薄膜902通过沉积实现层叠设置。
如图2所示为本申请第一金属网801的一实施方式的俯视图，可以理解的，第一金属网801与第二金属网802均由若干第一金属丝8011和若干第二金属丝8012组成，第一金属丝8011与第二金属丝8012垂直。
具体的，衬底10包括N型硅衬底或P型的硅衬底。
在其中一个实施例中，第一金属丝8011和/或第二金属丝8012的材质包括铜、银、金、锡或铝中的至少一种。第一金属丝8011的材质和第二金属丝8012的材质可以相同，也可以不同。
在其中一个实施例中，第一金属丝8011的尺寸大于或等于第二金属丝8012的尺寸；第一金属丝8011的尺寸为0.1mm-10mm，可选的，第一金属丝8011的尺寸为0.1mm-0.2mm，第二金属丝8012的尺寸为0.1mm-10mm，可选的，第二金属丝8012的尺寸为0.1mm-0.15mm。应予说明的是，尺寸具体为直径。
在其中一个实施例中，第一金属丝8011和/或第二金属丝8012的截面形状为长方形、正方形、圆柱形或三角形，为了增大金属网80与第一透明导电氧化物层60以及第二透明导电氧化物层70的接触面积，同时，增加光的漫反射效果，第一金属丝8011和/或第二金属丝8012的截面形状可选为三角形。应予说明的是，截面形状具体为横截面形状。
在其中一个实施例中，第一金属网801与第一透明导电氧化物层60通过粘结层固定连接，第二金属网802与第一透明导电氧化物层60通过粘结层固定连接。
应予说明的是，粘结层材料可以具有导电性，也可以不具有导电性，在其中一个实施例中，粘结层材料包括导电胶、热熔胶或含有Ag颗粒的纳米材料中的至少一种。
在其中一个实施例中，热熔胶包括聚乙烯热熔胶或乙烯共聚物热熔胶。
在其中一个实施例中，第一透明导电氧化物层60和/或第二透明导电氧化物层70的材料包括ITO、IWO、AZO、FTO、In 2O 3:ZnO或SnO 2中的至少一种。可选的，第一透明导电氧化物层60和/或第二透明导电氧化物层70的材料包括ITO。第一透明导电氧化物层60的厚度为1nm-100nm，第二透明导电氧化物层70的厚度为1nm-100nm。
在其中一个实施例中，第一介电薄膜901的材料和/或第二介电薄膜902的材料包括SiN、SiO x、AlO x、MgF 2或TiO 2中的至少一种。可选的，第一介电薄膜901的材料和/或第二介电薄膜902的材料包括的材料包括SiN。第一介电薄膜901的厚度为1nm-100nm，第二介电薄膜902的厚度为1nm-100nm；可选的，第一介电薄膜901的厚度为1nm-70nm，第二介电薄膜902的厚度为1nm-70nm。
在其中一个实施例中，第一透明导电氧化物层60的折射率大于第一介电薄膜901的折射率，第二透明导电氧化物层70的折射率大于第二介电薄膜902的折射率。
可以理解的，当光纤从低折射率的介质垂直进入到高折射率介质时，会发生干涉相消现象，反射光相消，透射光增强，即所谓的增透现象。本申请异质结电池100中的介电薄膜90和透明导电氧化物层层叠能够形成减反射结构，增 强透射光，使得更多的光进入到异质结电池100中，使异质结电池100的电流密度以及转换效率提高，透明导电氧化物层的厚度可以减小，从而进一步降低异质结电池100的生产成本。
在其中一个实施例中，第一本征非晶硅层20的厚度为1nm-10nm；N型掺杂非晶硅层30的厚度为1nm-30nm。
在其中一个实施例中，第二本征非晶硅层40的厚度为1nm-10nm；P型掺杂非晶硅层50的厚度为1nm-30nm。
上述异质结电池100，采用由第一金属丝8011与第二金属丝8012组成的第一金属网801和第二金属网802作为电极，避免了价格高昂的树脂型低温固化银浆的使用，极大降低了生产成本。
本申请提供的异质结电池的制备方法，包括以下步骤：
S1，对衬底10进行制绒处理，得到制绒衬底；
S2，在制绒衬底的一面生长第一本征非晶硅层20和N型掺杂非晶硅层30，在制绒衬底远离第一本征非晶硅层20的表面生长第二本征非晶硅层40和P型掺杂非晶硅层50，生长温度均为100℃-250℃；
S3，在N型掺杂非晶硅层30远离第一本征非晶硅层20的表面沉积第一透明导电氧化物层60，在P型掺杂非晶硅层50远离第二本征非晶硅层40的表面沉积第二透明导电氧化物层70，生长温度均为25℃-250℃；
S4，在第一透明导电氧化物层60远离N型掺杂非晶硅层30的表面固定第一金属网801，在第二透明导电氧化物层70远离P型掺杂非晶硅层50的表面固定第二金属网802；以及
S5，在第一透明导电氧化物层60远离N型掺杂非晶硅层30的表面沉积第一介电薄膜901，在第二透明导电氧化物层70远离P型掺杂非晶硅层50的表面 沉积第二介电薄膜902，生长温度均为25℃-250℃，得到异质结电池。
在其中一个实施例中，步骤S1包括：利用碱性溶液对衬底10进行制绒处理，得到制绒衬底。在其中一个实施例中，碱性溶液包括NaOH或KOH。
在其中一个实施例中，步骤S2采用等离子体增强化学气相沉积设备。
在步骤S3中，第一透明导电氧化物层60以及第二透明导电氧化物层70沉积的方式包括采用磁控溅射沉积、反应等离子体沉积或电子束蒸发沉积。
在其中一个实施例中，第一透明导电氧化物层60以及第二透明导电氧化物层70的沉积温度可选为25℃-250℃。
在步骤S4中，固定的方式包括通过粘结层固定，具体包括，在第一金属网801以及第二金属网802的一面涂覆粘结层的材料，将第一透明导电氧化物层60的一面与第一金属网801涂覆有粘结层的材料的一面固定，将第二透明导电氧化物层70的一面与第二金属网802涂覆有粘结层的材料的一面固定。
在步骤S5中，沉积的方式包括采用等离子体增强化学气相沉积法或采用原子层沉积法。在其中一个实施例中，第一介电薄膜901以及第二介电薄膜902的沉积温度可选为100℃-250℃。
可以理解的，在形成第一介电薄膜901以及第二介电薄膜902的过程中，实现了对第一金属网801和第一透明导电氧化物层60的接触部分以及第二金属网802和第二透明导电氧化物层70的接触部分的退火处理，使得第一透明导电氧化物层60以及第二透明导电氧化物层70的表面掺杂浓度增加，同时，一定的退火温度使得第一金属网801与第一透明导电氧化物层60以及第二金属网802与第二透明导电氧化物层之间的结合力增加，形成一个良好的接触。
本申请提供的异质结电池的制备方法，能够实现低成本的异质结电池100的简单制备，适用于工业化生产。
本申请提供的异质结电池组件130包括两个以上的如上述的异质结电池100或者如上述的异质结电池的制备方法制备得到的异质结电池100，异质结电池100之间通过具有粘结性的导电材料110串联，异质结电池100之间具有相同的转换效率。
在其中一个实施例中，可选铜测试台测试异质结电池100的转换效率，铜测试台的两边装有多条金属丝线，代替传统的探针排，通常用来测试没有主栅的电池。
在其中一个实施例中，具有粘结性的导电材料110包括导电胶带，导电胶或含有Ag颗粒的纳米材料中的至少一种。
本申请提供的异质结电池组件130中，异质结电池100之间通过具有粘结性的导电材料110串联，无需焊带进行焊接，极大地简化了异质结电池组件130的制备流程，降低了制备成本，工序的减少也降低了生产控制的难度，进而提高了产品合格率；同时，还免去了丝网印刷、烧结炉等设备，进一步降低设备成本。
以下，将通过以下具体实施例对异质结电池及其制备方法和应用做进一步的说明。
实施例1
利用NaOH溶液对衬底10进行制绒处理，得到制绒衬底；其中，衬底10选用N型的硅衬底。
利用等离子体增强型化学气相沉积(PECVD)设备在制绒衬底10的表面生长5nm厚的第一本征非晶硅层20和15nm厚的N型掺杂非晶硅层30；接着在制绒衬底远离第一本征非晶硅层20的表面生长5nm厚的第二本征非晶硅层40和15nm厚的P型掺杂非晶硅层50，第一本征非晶硅层20、N型掺杂非晶硅层 30、第二本征非晶硅层40以及P型掺杂非晶硅层50的生长温度均为200℃。
采用反应等离子体沉积的方法在N型掺杂非晶硅层30远离第一本征非晶硅层20的表面沉积50nm厚的第一透明导电氧化物层60，在P型掺杂非晶硅层50远离第二本征非晶硅层40的表面沉积50nm厚的第二透明导电氧化物层70，第一透明导电氧化物层60以及第二透明导电氧化物层70的生长温度均为100℃，第一透明导电氧化物层60以及第二透明导电氧化物层70的材料均为ITO。
在第一透明导电氧化物层60远离N型掺杂非晶硅层30的表面通过导电胶固定第一金属网801作为电极，在第二透明导电氧化物层70远离P型掺杂非晶硅层50的表面通过导电胶固定第二金属网802作为电极，第一金属网801以及第二金属网802均由若干第一金属丝8011以及若干第二金属丝8012组成，第一金属丝8011与第二金属丝8012垂直，第一金属丝8011的直径为0.2mm，横截面形状为三角形，第二金属丝8012的直径为0.15mm，横截面形状为三角形。
采用等离子体增强化学气相沉积法在第一透明导电氧化物层60远离N型掺杂非晶硅层30的表面沉积40nm厚的第一介电薄膜901，在第二透明导电氧化物层70远离P型掺杂非晶硅层50的表面沉积40nm厚的第二介电薄膜902，得到异质结电池100，第一介电薄膜901以及第二介电薄膜902的生长温度均为200℃，第一介电薄膜901以及第二介电薄膜902的材料包括SiN，从而，在第一金属网801以及第二金属网802的区域外形成ITO/SiN的叠层减反射结构。
采用无主栅电池所用到的丝线方法对异质结电池100进行电性能测试分选，选取12个同档位(相同转化效率)的异质结电池100，采用导电胶带粘结在异质结电池100的首尾两端，将相邻两个异质结电池100的正负电极(即金属网80)相连，形成串联，再进行排版，附上乙烯-醋酸乙烯共聚物(EVA)膜，再进行层压，打胶，装上边框130，得到如图3所示的异质结电池组件130。
实施例2
利用NaOH溶液对衬底10进行制绒处理，得到制绒衬底；其中，衬底10选用N型的硅衬底。
利用等离子体增强型化学气相沉积(PECVD)设备在制绒衬底10的表面生长8nm厚的第一本征非晶硅层20和25nm厚的N型掺杂非晶硅层30；接着在制绒衬底远离第一本征非晶硅层20的表面生长8nm厚的第二本征非晶硅层40和25nm厚的P型掺杂非晶硅层50，第一本征非晶硅层20、N型掺杂非晶硅层30、第二本征非晶硅层40以及P型掺杂非晶硅层50的生长温度均为100℃。
采用电子束蒸发的方法沉积的方法在N型掺杂非晶硅层30远离第一本征非晶硅层20的表面沉积80nm厚的第一透明导电氧化物层60，在P型掺杂非晶硅层50远离第二本征非晶硅层40的表面沉积80nm厚的第二透明导电氧化物层70，第一透明导电氧化物层60以及第二透明导电氧化物层70的生长温度均为25℃，第一透明导电氧化物层60以及第二透明导电氧化物层70的材料均为ITO。
在第一透明导电氧化物层60远离N型掺杂非晶硅层30的表面通过聚乙烯热熔胶固定第一金属网801作为电极，在第二透明导电氧化物层70远离P型掺杂非晶硅层50的表面通过聚乙烯热熔胶固定第二金属网802作为电极，第一金属网801以及第二金属网802均由若干第一金属丝8011以及若干第二金属丝8012组成，第一金属丝8011与第二金属丝8012垂直，第一金属丝8011的直径为0.15mm，横截面形状为圆形，第二金属丝8012的直径为0.15mm，横截面形状为圆形。
采用原子层沉积法在第一透明导电氧化物层60远离N型掺杂非晶硅层30的表面沉积60nm厚的第一介电薄膜901，在第二透明导电氧化物层70远离P型掺杂非晶硅层50的表面沉积60nm厚的第二介电薄膜902，得到异质结电池 100，第一介电薄膜901以及第二介电薄膜902的生长温度均为的生长温度均为150℃，第一介电薄膜901以及第二介电薄膜902的材料包括TiO2，从而，在第一金属网801以及第二金属网802的区域外形成ITO/TiO2的叠层减反射结构。
采用无主栅电池所用到的丝线方法对异质结电池100进行电性能测试分选，选取12个同档位(相同转化效率)的异质结电池100，采用纳米银胶体粘结在异质结电池100的首尾两端，将相邻两个异质结电池100的正负电极(即金属网80)相连，形成串联，再进行排版，附上乙烯-醋酸乙烯共聚物(EVA)膜，再进行层压，打胶，装上边框130，得到如图3所示的异质结电池组件130。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种异质结电池，其特征在于，包括衬底以及依次层叠设置于所述衬底的一面的第一本征非晶硅层、N型掺杂非晶硅层、第一透明导电氧化物层和第一介电薄膜，依次层叠设置于所述衬底的另一面的第二本征非晶硅层、P型掺杂非晶硅层、第二透明导电氧化物层和第二介电薄膜，所述异质结电池还包括第一金属网和第二金属网，所述第一金属网穿透所述第一介电薄膜并与所述第一透明导电氧化物层固定连接，所述第二金属网穿透所述第二介电薄膜并与所述第二透明导电氧化物层固定连接，其中，所述第一金属网和所述第二金属网均由若干第一金属丝和若干第二金属丝组成，所述第一金属丝与所述第二金属丝垂直。
  2. 如权利要求1所述的异质结电池，其中，所述第一金属丝和/或所述第二金属丝的材质包括铜、银、金、锡或铝中的至少一种。
  3. 如权利要求1所述的异质结电池，其中，所述第一金属丝的直径大于或等于所述第二金属丝的直径；所述第一金属丝的直径为0.1mm-10mm，所述第二金属丝的直径为0.1mm-10mm。
  4. 如权利要求1所述的异质结电池，其中，所述第一金属丝和/或所述第二金属丝的横截面形状为长方形、正方形、圆柱形或三角形。
  5. 如权利要求1所述的异质结电池，其中，所述第一金属网与所述第一透明导电氧化物层通过粘结层固定连接，所述第二金属网与所述第一透明导电氧化物层通过粘结层固定连接。
  6. 如权利要求5所述的异质结电池，其中，所述粘结层的材料包括导电胶、热熔胶或含有Ag颗粒的纳米材料中的至少一种。
  7. 如权利要求6所述的异质结电池，其中，所述热熔胶包括聚乙烯热熔胶 或乙烯共聚物热熔胶热熔胶。
  8. 如权利要求1所述的异质结电池，其中，所述第一透明导电氧化物层和/或所述第二透明导电氧化物层的材料包括ITO、IWO、AZO、FTO、In2O3:ZnO或SnO2中的至少一种。
  9. 根据权利要求1所述的异质结电池，其中，所述第一介电薄膜的材料和/或所述第二介电薄膜的材料包括SiN、SiOx、AlOx、MgF2或TiO2中的至少一种。
  10. 如权利要求8或9所述的异质结电池，其中，所述第一透明导电氧化物层的折射率大于所述第一介电薄膜的折射率，所述第二透明导电氧化物层的折射率大于所述第二介电薄膜的折射率。
  11. 如权利要求1-9任一项所述的异质结电池，其中，所述第一本征非晶硅层的厚度为1nm-10nm；所述N型掺杂非晶硅层的厚度为1nm-30nm；所述第一透明导电氧化物层的厚度为1nm-100nm；所述第一介电薄膜的厚度为1nm-100nm。
  12. 如权利要求1-9任一项所述的异质结电池，其中，所述第二本征非晶硅层的厚度为1nm-10nm；所述P型掺杂非晶硅层的厚度为1nm-30nm；第二透明导电氧化物层的厚度为1nm-100nm，所述第二介电薄膜的厚度为1nm-100nm。
  13. 一种如权利要求1-12任一所述的异质结电池的制备方法，其特征在于，包括以下步骤：
    对衬底进行制绒处理，得到制绒衬底；
    在所述制绒衬底的一面生长第一本征非晶硅层和N型掺杂非晶硅层，在所述制绒衬底远离所述第一本征非晶硅层的表面生长第二本征非晶硅层和P 型掺杂非晶硅层，生长温度均为100℃-250℃；
    在所述N型掺杂非晶硅层远离所述第一本征非晶硅层的表面沉积第一透明导电氧化物层，在所述P型掺杂非晶硅层远离所述第二本征非晶硅层的表面沉积第二透明导电氧化物层，生长温度均为25℃-250℃；
    在所述第一透明导电氧化物层远离所述N型掺杂非晶硅层的表面固定第一金属网，在所述第二透明导电氧化物层远离P型掺杂非晶硅层的表面固定第二金属网；以及
    在所述第一透明导电氧化物层远离所述N型掺杂非晶硅层的表面沉积第一介电薄膜，在所述第二透明导电氧化物层远离P型掺杂非晶硅层的表面沉积第二介电薄膜，生长温度均为25℃-250℃，得到异质结电池。
  14. 如权利要求13所述的异质结电池的制备方法，其中，所述固定的方式包括通过粘结层固定。
  15. 一种异质结电池组件，其特征在于，包括两个以上的如权利要求1-12任一项所述的异质结电池或者如权利要求13或14所述的异质结电池的制备方法制备得到的异质结电池，所述异质结电池之间通过具有粘结性的导电材料串联，所述异质结电池之间具有相同的转换效率。
  16. 根据权利要求15所述的异质结电池组件，其中，所述具有粘结性的导电材料包括导电胶带、导电胶或含有Ag颗粒的纳米材料中的至少一种。
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CN114122161A (zh) * 2021-11-12 2022-03-01 东方日升新能源股份有限公司 叠层膜电池及其制备方法
CN114530525A (zh) * 2022-01-27 2022-05-24 江苏日托光伏科技股份有限公司 一种非银金属化结构制备方法及其应用
CN114843373A (zh) * 2022-01-27 2022-08-02 江苏日托光伏科技股份有限公司 一种htj电池的制备方法
CN114639743A (zh) * 2022-02-25 2022-06-17 通威太阳能（合肥）有限公司 异质结电池、光伏组件电池串及其制造方法
CN115101600A (zh) * 2022-07-29 2022-09-23 常州时创能源股份有限公司 一种hjt电池的电流引出结构及其制备方法
CN117423766B (zh) * 2023-10-23 2025-01-14 天合光能股份有限公司 异质结电池及其制作方法、光伏组件及光伏系统
CN117747681A (zh) * 2023-12-08 2024-03-22 天合光能股份有限公司 异质结太阳能电池、光伏组件及光伏系统
CN118039721A (zh) * 2024-03-07 2024-05-14 淮安捷泰新能源科技有限公司 太阳能电池和太阳能电池的制备方法
CN118156351A (zh) * 2024-03-08 2024-06-07 上海电气集团恒羲光伏科技(南通)有限公司 一种异质结太阳能电池及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107482071A (zh) * 2017-07-24 2017-12-15 协鑫集成科技股份有限公司 异质结太阳能电池及其制备方法
US20180254361A1 (en) * 2012-09-25 2018-09-06 International Business Machines Corporation Embedded junction in hetero-structured back-surface field for photovoltaic devices
CN110649104A (zh) * 2019-09-19 2020-01-03 苏州拓升智能装备有限公司 一种高光电转化效率的太阳能电池
CN111403554A (zh) * 2020-03-26 2020-07-10 中国科学院上海微系统与信息技术研究所 一种太阳电池的制备方法以及由此得到的太阳电池
CN112038424A (zh) * 2020-09-29 2020-12-04 东方日升（常州）新能源有限公司 一种异质结电池及其制备方法和组件
CN212625599U (zh) * 2020-09-29 2021-02-26 东方日升（常州）新能源有限公司 一种异质结电池和组件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008135654A (ja) * 2006-11-29 2008-06-12 Sanyo Electric Co Ltd 太陽電池モジュール
CN102214729A (zh) * 2010-04-09 2011-10-12 陕西众森电能科技有限公司 一种太阳电池正面电极结构及其制作方法
US10193007B2 (en) * 2014-03-26 2019-01-29 Kaneka Corporation Solar cell module and method for manufacturing same
CN203932071U (zh) * 2014-04-22 2014-11-05 陕西众森电能科技有限公司 一种hit太阳电池电极
CN104037265B (zh) * 2014-06-18 2016-06-15 陕西众森电能科技有限公司 一种hit太阳电池及其电极制备及串联的方法
CN107078179B (zh) * 2014-09-30 2019-04-26 株式会社钟化 晶体硅太阳能电池的制造方法、及太阳能电池模块的制造方法
CN104576779B (zh) * 2015-01-21 2017-04-19 黄华松 丝网阵列导电膜、太阳能电池及其制备方法
CN105895746B (zh) * 2016-06-29 2017-08-15 中国科学院上海微系统与信息技术研究所 具有叠层减反特性的晶体硅异质太阳电池及其制备方法
JP7183245B2 (ja) * 2018-02-23 2022-12-05 株式会社カネカ 太陽電池の製造方法
CN208655661U (zh) * 2018-08-02 2019-03-26 君泰创新（北京）科技有限公司 一种太阳能电池芯片

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180254361A1 (en) * 2012-09-25 2018-09-06 International Business Machines Corporation Embedded junction in hetero-structured back-surface field for photovoltaic devices
CN107482071A (zh) * 2017-07-24 2017-12-15 协鑫集成科技股份有限公司 异质结太阳能电池及其制备方法
CN110649104A (zh) * 2019-09-19 2020-01-03 苏州拓升智能装备有限公司 一种高光电转化效率的太阳能电池
CN111403554A (zh) * 2020-03-26 2020-07-10 中国科学院上海微系统与信息技术研究所 一种太阳电池的制备方法以及由此得到的太阳电池
CN112038424A (zh) * 2020-09-29 2020-12-04 东方日升（常州）新能源有限公司 一种异质结电池及其制备方法和组件
CN212625599U (zh) * 2020-09-29 2021-02-26 东方日升（常州）新能源有限公司 一种异质结电池和组件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4207312A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024193576A1 (zh) * 2023-03-23 2024-09-26 通威太阳能（成都）有限公司 一种太阳电池及其制备方法

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