WO2022077947A1 - 电容结构及其制作方法 - Google Patents

电容结构及其制作方法 Download PDF

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Publication number
WO2022077947A1
WO2022077947A1 PCT/CN2021/101292 CN2021101292W WO2022077947A1 WO 2022077947 A1 WO2022077947 A1 WO 2022077947A1 CN 2021101292 W CN2021101292 W CN 2021101292W WO 2022077947 A1 WO2022077947 A1 WO 2022077947A1
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Prior art keywords
layer
capacitor
capacitive
substrate
contact layer
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English (en)
French (fr)
Inventor
盛超军
陆勇
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to EP21878997.2A priority Critical patent/EP4199087A4/en
Priority to US17/439,586 priority patent/US11723190B2/en
Publication of WO2022077947A1 publication Critical patent/WO2022077947A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • the present application relates to the technical field of memory fabrication, and in particular, to a capacitor structure and a fabrication method thereof.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • DRAM is a kind of semiconductor memory commonly used in computers.
  • DRAM is usually arranged in a two-dimensional matrix with a capacitor and a transistor as a unit.
  • bit binary bit
  • the capacitors in DRAM are mostly single-sided capacitor structures.
  • the single-sided capacitor structure limits the increase of the capacitance value per unit area.
  • the prior art proposes a double-sided capacitor that can increase the surface area of the electrode layer. structure.
  • the capacitor is arranged on the capacitor contact layer. Since the contact area between the lower electrode plate and the capacitor contact layer is small, and the area of the capacitor is small, the resistance value of the double-sided capacitor structure is large.
  • the present application provides a capacitor structure and a manufacturing method thereof, which increases the area of the capacitor and reduces the resistance of the double-sided capacitor structure.
  • the present application provides a capacitor structure, including:
  • the array is arranged on the substrate;
  • a lower electrode layer surrounding the sidewall of the first capacitive contact layer and extending along the direction of the first capacitive contact layer away from the substrate;
  • capacitor dielectric layer covering the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the first capacitor contact layer;
  • the upper electrode layer covers the surface of the capacitor dielectric layer.
  • the present application provides a method for fabricating a capacitor structure, including:
  • a second electrode layer is deposited overlying the capacitive dielectric layer.
  • the capacitor structure is composed of a substrate, a first capacitor contact layer, a lower electrode layer, a capacitor dielectric layer and an upper electrode layer, the first capacitor contact layer array is arranged on the substrate, and the lower
  • the electrode layer surrounds the sidewall of the first capacitor contact layer and extends along the direction of the first capacitor contact layer away from the substrate.
  • the capacitor dielectric layer covers the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the first capacitor contact layer.
  • the upper electrode layer Covering the surface of the capacitor dielectric layer, since the first capacitor contact layer is arranged on the substrate in an array, and the lower electrode layer surrounds the sidewall of the first capacitor contact layer, that is, the lower electrode layer surrounds the sidewall of the first capacitor contact layer, so it can increase the number of capacitors.
  • the contact area between the lower electrode layer and the first capacitor contact layer is large. Since the capacitor dielectric layer covers the upper surface of the substrate except the first capacitor contact layer arranged in the array, and the upper electrode layer covers the surface of the capacitor dielectric layer, compared with In the existing capacitor structure, the capacitor is arranged on the first capacitor contact layer. In the present application, the capacitor area surrounding the sidewall of the first capacitor contact layer is increased, thereby increasing the area of the capacitor and reducing the resistance of the double-sided capacitor structure. value.
  • FIG. 1 is a schematic diagram of a capacitor structure provided by an embodiment of the present application.
  • FIG. 2 is a top view of a first capacitive contact layer
  • FIG. 3 is a schematic diagram of a capacitor structure provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for fabricating a capacitor structure according to an embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a substrate in a process of forming a capacitor structure according to an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a conductive layer and a capacitor stack layer in a process of forming a capacitor structure provided by an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of at least one capacitor column formed during the formation process of a capacitor structure provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a process of patterning a capacitor stack layer and a conductive layer during the formation of a capacitor structure provided by an embodiment of the present application;
  • FIG. 9 is a schematic structural diagram after depositing a first electrode layer during the formation of a capacitor structure provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a capacitor structure after removing a capacitor column during the formation process of a capacitor structure provided by an embodiment of the present application;
  • FIG. 11 is a schematic structural diagram after removing the first electrode layer on the upper surface of the substrate during the formation process of a capacitor structure provided by an embodiment of the present application;
  • FIG. 12 is a schematic structural diagram of depositing a mask layer and forming a photoresist during the formation process of a capacitor structure provided by an embodiment of the present application;
  • FIG. 13 is a schematic diagram of a process of removing a capacitor column during the formation of a capacitor structure provided by an embodiment of the present application;
  • FIG. 14 is a schematic structural diagram after depositing a capacitor dielectric layer during the formation of a capacitor structure provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram after depositing an upper electrode material layer during the formation of a capacitor structure provided by an embodiment of the present application;
  • FIG. 16 is a schematic structural diagram after depositing an upper electrode filling layer during the formation process of a capacitor structure provided by an embodiment of the present application;
  • FIG. 17 is a schematic flowchart of a method for fabricating a capacitor structure according to an embodiment of the present application.
  • the capacitor is arranged on the capacitor contact layer. Since the contact area between the lower electrode plate and the capacitor contact layer is small, and the area of the capacitor is small, the resistance value of the double-sided capacitor structure is large. In order to solve this problem, the present application provides a capacitor structure.
  • a lower electrode layer at a position around the sidewall of the first capacitor contact layer, that is, the lower electrode layer surrounds the sidewall of the first capacitor contact layer, so it can be Increase the contact area between the lower electrode layer and the first capacitor contact layer, cover the surface of the lower electrode layer with the capacitor dielectric layer, and the capacitor dielectric layer also covers the upper surface of the substrate except the first capacitor contact layer arranged in the array, and the upper electrode Therefore, compared with the existing capacitor structure, the capacitor area surrounding the sidewall of the first capacitor contact layer is increased in this application, thereby increasing the area of the capacitor and reducing the resistance of the double-sided capacitor structure. value.
  • the capacitor structure provided in the present application can be applied to semiconductor memories, for example, dynamic random access memory.
  • the dynamic random access memory includes a plurality of repeated memory cells, and each memory cell can include a capacitor and a transistor, and the gate of the transistor can be The electrode is connected to the word line, the drain electrode of the transistor is connected to the bit line, and the source electrode of the transistor is connected to the capacitor.
  • the capacitor here can use the capacitor structure provided in this application.
  • the capacitor structure provided in the present application can also be applied to other semiconductor devices, which is not limited thereto.
  • FIG. 1 is a schematic diagram of a capacitor structure provided by an embodiment of the present application.
  • the capacitor structure of this embodiment may include: a substrate 101 , a first capacitor contact layer 102 , a lower electrode layer 103 , and a capacitor dielectric layer 104 and the upper electrode layer 105.
  • the material of the substrate 101 may be silicon (Si), germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), silicon-on-insulator or germanium-on-insulator, or other materials.
  • the substrate 101 has active regions and a trench isolation structure for isolating the active regions.
  • a semiconductor device may be formed on the active region of the substrate 101 , and the semiconductor device may be, for example, a transistor.
  • the first capacitor contact layers 102 are arranged in an array on the substrate 101, and the array may be arranged on the substrate 101 at equal intervals, or may not be arranged on the substrate 101 at equal intervals.
  • the cross-section of the contact layer 102 may be circular, square or rectangular. Taking eight capacitors arranged on the substrate 101 as an example, FIG. 2 is a top view of the first capacitor contact layer, as shown in FIG. 2 , the cross section of the first capacitor contact layer 102 shown in FIG.
  • a capacitive contact layer 102 has a certain height, and the first capacitive contact layer 102 may have a cylindrical structure. It can be understood that, the first capacitive contact layer 102 may also be other columnar structures.
  • the material of the first capacitive contact layer 102 may be metal, and the metal may specifically be tungsten (W) or the like.
  • the first capacitive contact layer 102 is electrically connected to the transistor.
  • the lower electrode layer 103 surrounds the sidewall of the first capacitive contact layer 102 and extends along the direction of the first capacitive contact layer 102 away from the substrate 101 , and the lower surface of the lower electrode layer 103 is in direct contact with the substrate 101 .
  • the lower electrode layer 103 has a certain height.
  • the material of the lower electrode layer 103 may be a compound formed by at least one of metal nitride and metal silicide, such as titanium nitride (TiN), titanium silicide (TiSi) or titanium silicon nitride .
  • the capacitor dielectric layer 104 covers the upper surface of the substrate 101 , the surface of the lower electrode layer 103 and the upper surface of the first capacitor contact layer 102 , and the upper electrode layer 105 covers the surface of the capacitor dielectric layer 104 .
  • the material of the capacitor dielectric layer 104 may be a high-K dielectric material to increase the capacitance value of the capacitor per unit area, including one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or the above materials.
  • the material of the capacitor dielectric layer 104 can also be silicon oxide or other insulating materials.
  • the lower electrode layer 103 surrounds the sidewall of the first capacitive contact layer 102 , that is, the lower electrode layer 103 surrounds the side of the first capacitive contact layer 102 . Therefore, the contact area between the lower electrode layer 103 and the first capacitive contact layer 102 can be increased, and since the capacitive dielectric layer 104 covers the upper surface of the substrate 101 except the first capacitive contact layer 102 arranged in the array, the upper electrode The layer 105 covers the surface of the capacitor dielectric layer 104. Therefore, compared with the existing capacitor structure, the capacitor is arranged on the first capacitor contact layer. In the present application, the capacitor area surrounding the sidewall of the first capacitor contact layer 102 is increased, thereby The area of the capacitor is increased, and the resistance value of the double-sided capacitor structure is reduced.
  • the upper electrode layer 105 includes an upper electrode material layer 1051 and an upper electrode filling layer 1052, the upper electrode material layer 1051 covers the surface of the capacitor medium layer 104, and the upper electrode filling layer 1052 is located on the upper electrode material layer 1052.
  • the material of the upper electrode material layer 1051 may be a compound formed by at least one of metal nitride and metal silicide, such as titanium nitride (TiN), titanium silicide (TiSi) or silicon nitride titanium.
  • the material of the upper electrode filling layer 1052 may be polysilicon or silicon germanium.
  • the capacitor structure provided in this embodiment is composed of a substrate, a first capacitor contact layer, a lower electrode layer, a capacitor dielectric layer and an upper electrode layer.
  • the first capacitor contact layer array is arranged on the substrate, and the lower electrode layer surrounds the first capacitor contact layer.
  • the sidewall of the capacitor contact layer extends along the direction of the first capacitor contact layer away from the substrate, the capacitor dielectric layer covers the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the first capacitor contact layer, and the upper electrode layer covers the surface of the capacitor dielectric layer , because the first capacitor contact layer is arranged on the substrate in an array, and the lower electrode layer surrounds the sidewall of the first capacitor contact layer, that is, the lower electrode layer surrounds the sidewall of the first capacitor contact layer, so it can increase the number of The contact area of the first capacitor contact layer, and since the capacitor dielectric layer covers the upper surface of the substrate except the first capacitor contact layer arranged in the array, and the upper electrode layer covers the surface of the capacitor dielectric layer, compared with the existing capacitor In the structure, the capacitor is arranged on the first capacitor contact layer. In the present application, the capacitor area surrounding the sidewall of the first capacitor contact layer is increased, thereby increasing the area of the capacitor and reducing the resistance of the double-sided capacitor structure.
  • FIG. 3 is a schematic diagram of a capacitor structure provided by an embodiment of the present application.
  • the capacitor structure of this embodiment is based on the capacitor structure shown in FIG. 1 , and may further include: a second capacitor contact layer 106, the second capacitive contact layer 106 is located on the upper surface of the first capacitive contact layer 102, the shape of the second capacitive contact layer is the same as the shape of the first capacitive contact layer, for example, if the cross section of the first capacitive contact layer 102 is a circle
  • the capacitor dielectric layer 104 covers the upper surface of the substrate 101 , the surface of the lower electrode layer 103 and the upper surface of the second capacitor contact layer 106 .
  • the material of the second capacitive contact layer 106 may be the same as the material of the lower electrode layer 103 .
  • the material of the second capacitive contact layer 106 may be a compound formed by at least one of metal nitride and metal silicide, such as titanium nitride (TiN), titanium silicide (TiSi) or titanium silicon nitride.
  • the material of the first capacitive contact layer 102 is metal tungsten (W), and the material of the capacitive dielectric layer 104 is oxide In the case of silicon, metal tungsten can be prevented from diffusing into silicon oxide.
  • the second capacitive contact layer 106 can also serve as a lower electrode layer, so the areas of the lower electrode layer and the first capacitive contact layer 102 can be increased, thereby further increasing the capacitance area.
  • FIG. 4 is a schematic flowchart of a manufacturing method of a capacitor structure provided by an embodiment of the present application. As shown in FIG. 4 , the method of this embodiment may include:
  • FIG. 5 is a schematic structural diagram of a substrate in the process of forming a capacitor structure provided by an embodiment of the present application.
  • a substrate 101 is provided first, wherein the material of the substrate 101 may be silicon (Si), germanium ( Ge), silicon germanium (GeSi), or silicon carbide (SiC), or silicon-on-insulator or germanium-on-insulator, or other materials.
  • the substrate 101 has active regions and a trench isolation structure for isolating the active regions.
  • a semiconductor device may be formed on the active region of the substrate 101 , and the semiconductor device may be, for example, a transistor.
  • FIG. 6 is a schematic structural diagram of a conductive layer and a capacitor stack layer in the process of forming a capacitor structure provided by an embodiment of the present application.
  • a conductive layer 201 is formed on the substrate 101 and formed on the conductive layer 201
  • the capacitor stack layer 202 includes a sacrificial layer 2021 and a top support layer 2022 .
  • FIG. 7 is a schematic structural diagram of at least one capacitor column formed in the process of forming a capacitor structure according to an embodiment of the present application.
  • the capacitor stack layer 202 and the conductive layer 201 are patterned to form at least one capacitor column 203 arranged in an array and the first capacitive contact layer 102 corresponding to the capacitor columns 203 one-to-one.
  • FIG. 8 is a schematic diagram of a process of patterning a capacitor stack layer and a conductive layer in the process of forming a capacitor structure provided by an embodiment of the present application.
  • patterning the capacitor stack layer 202 and the conductive layer 201 forming at least one capacitive column 203 arranged in an array and the first capacitive contact layer 102 corresponding to the capacitive column 203 one-to-one, which may be:
  • a mask layer 111 is deposited to cover the top support layer 2022 in the capacitor stack layer 202.
  • the mask layer may be a single-layer structure or a multi-layer structure.
  • the mask layer may include polysilicon, carbon and Silicon oxynitride, then a negative photoresist 112 is formed to cover the mask layer 111, then exposed, developed, etched down along the negative photoresist 112, etched to the mask layer 111, and then etched all the way to the substrate 101 , forming at least one capacitive column 203 arranged in an array and a first capacitive contact layer 102 corresponding to the capacitive column 203 one-to-one.
  • the capacitive column structure of a specific shape (such as a circle) can be directly obtained.
  • two patterning processes can also be used to obtain capacitor columns with specific shapes, and the patterning processes include a self-aligned double patterning process or a reverse self-aligned double patterning process.
  • FIG. 9 is a schematic structural diagram of a capacitor structure after deposition of a first electrode layer in the process of forming a capacitor structure provided by an embodiment of the present application.
  • a first electrode layer 301 is deposited to cover the sidewall of the capacitor column 203 and the first capacitor contact layer.
  • the first electrode layer 301 can be deposited by atomic layer deposition, while also covering the upper surface of the substrate.
  • the deposition process here may be chemical vapor deposition, plasma enhanced chemical vapor deposition, or low pressure chemical vapor deposition, and the like.
  • FIG. 10 is a schematic diagram of the structure after removing the capacitor column during the formation process of a capacitor structure provided by an embodiment of the present application. Please refer to FIG. 10 , the capacitor column 203 is removed, and the first electrode layer 301 and the first capacitor contact layer 102 are retained. , while removing the capacitor column 203, the first electrode layer 301 on the upper surface of the capacitor column 203 and the first electrode layer 301 on the upper surface of the substrate 101 are also removed accordingly.
  • FIG. 11 is a schematic diagram of the structure after removing the first electrode layer on the upper surface of the substrate in the process of forming a capacitor structure provided by the embodiments of the present application. Referring to FIG. 11 , first remove the first electrode layer on the upper surface of the substrate The first electrode layer 301 .
  • the removal of the capacitor column 203 may specifically be: depositing a layer of mask
  • the layer 302 covers the upper surface of the capacitor pillars 203 , and then a photoresist 303 is formed to cover the mask layer 302 , and the photoresist 303 has openings corresponding to the capacitor pillars 203 one-to-one.
  • the deposition process here may be chemical vapor deposition, plasma enhanced chemical vapor deposition, or low pressure chemical vapor deposition, and the like.
  • FIG. 13 is a schematic diagram of a process of removing a capacitor column during the formation of a capacitor structure provided by an embodiment of the present application.
  • the mask layer 302 , the top support layer 2022 and the sacrificial layer 2021 are removed along the opening, as shown in FIG. 10 . shown structure.
  • dry etching may be used to remove the top support layer 2022
  • dry etching and wet etching may be used to remove the sacrificial layer 2021
  • the wet etching may completely remove the sacrificial layer 2021 .
  • the first electrode layer 301 corresponds to the lower electrode layer 103 in FIG. 1 , that is, the lower electrode layer 103 .
  • FIG. 14 is a schematic view of the structure after depositing a capacitor dielectric layer in the formation process of a capacitor structure provided by an embodiment of the present application.
  • the deposition capacitor dielectric layer 104 covers the first An electrode layer 301 .
  • a second electrode layer (ie, corresponding to the upper electrode layer 105 shown in FIG. 1 ) is deposited to cover the capacitive dielectric layer 104 .
  • the second electrode layer 304 includes an upper electrode material layer 3041 and an upper electrode filling layer 3042.
  • FIG. 15 is a schematic diagram of the structure after depositing the upper electrode material layer in the process of forming a capacitor structure provided by an embodiment of the present application. Please refer to FIG. 15, depositing the second electrode layer 304 to cover the capacitor dielectric layer 104, which can be:
  • the upper electrode material layer 3041 is deposited to cover the surface of the capacitor dielectric layer 104.
  • FIG. 16 is a schematic diagram of the structure after depositing the upper electrode filling layer during the formation process of a capacitor structure provided by an embodiment of the present application. Referring to FIG. 16, the upper electrode filling layer is deposited. The layer 3042 covers the upper surface of the upper electrode material layer 3041 . It should be noted that the upper electrode material layer 3041 corresponds to the upper electrode material layer 1051 shown in FIG. 1 , and the upper electrode filling layer 3042 corresponds to the upper electrode material layer 1052 shown in FIG. 1 .
  • the fabricated capacitor structure is composed of a substrate, a first capacitor contact layer, a lower electrode layer, a capacitor dielectric layer and an upper electrode layer, and the first capacitor contact layer array is arranged on the substrate
  • the upper and lower electrode layers surround the sidewall of the first capacitor contact layer and extend along the direction of the first capacitor contact layer away from the substrate, and the capacitor dielectric layer covers the upper surface of the substrate, the surface of the lower electrode layer and the upper surface of the first capacitor contact layer,
  • the upper electrode layer covers the surface of the capacitor dielectric layer.
  • the lower electrode layer surrounds the sidewall of the first capacitor contact layer, that is, the lower electrode layer surrounds the sidewall of the first capacitor contact layer. Therefore, the contact area between the lower electrode layer and the first capacitive contact layer can be increased, and since the capacitive dielectric layer covers the upper surface of the substrate except the first capacitive contact layer arranged in the array, the upper electrode layer covers the surface of the capacitive dielectric layer Therefore, compared with the existing capacitor structure, the capacitor is arranged on the first capacitor contact layer. In this application, the capacitor area surrounding the sidewall of the first capacitor contact layer is increased, thereby increasing the area of the capacitor and reducing the double The resistance value of the surface capacitor structure.
  • the conductive layer includes a first conductive layer and a second conductive layer, and the material of the second conductive layer is the same as that of the first electrode layer.
  • the method may further include: electrically connecting the second conductive layer and the first electrode layer, so that the second conductive layer and the first electrode layer form a lower electrode.
  • the flow shown in FIG. 17 is used as an example for description.
  • FIG. 17 is a schematic flowchart of a method for fabricating a capacitor structure provided by an embodiment of the present application. As shown in FIG. 17 , the method of this embodiment may include:
  • the conductive layer includes a first conductive layer and a second conductive layer, the material of the second conductive layer is the same as that of the first electrode layer, and the second conductive layer is electrically connected to the first electrode layer. connected, so that the conductive layer and the first electrode layer form a lower electrode.
  • the specific process is the same as that shown in FIG. 4 , which is not repeated here, and finally the capacitor structure shown in FIG. 3 is formed.
  • the conductive layer includes a first conductive layer and a second conductive layer
  • the conductive layer ie the second capacitive contact layer 106 in FIG. 3
  • the material of the second conductive layer is the same as the material of the first electrode layer.
  • the second conductive layer is added On the one hand, it can prevent the first capacitive contact layer from diffusing to the capacitive dielectric layer.
  • the material of the first capacitive contact layer is metal tungsten (W)
  • the material of the capacitive dielectric layer is silicon oxide, which can prevent metal tungsten from diffusing to silicon oxide.
  • the second conductive layer can also serve as the lower electrode layer, so the area of the lower electrode layer and the first capacitor contact layer can be increased, and the area of the capacitor can be further increased.
  • Embodiments of the present application further provide a memory, where the memory includes any of the capacitor structures described above.

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Abstract

本申请提供一种电容结构及其制作方法。该电容结构包括：衬底、第一电容接触层、下电极层、电容介质层和上电极层，其中，第一电容接触层阵列排布于衬底上，下电极层围绕第一电容接触层侧壁，并沿第一电容接触层背离衬底的方向延伸，电容介质层覆盖衬底上表面、下电极层表面及第一电容接触层上表面，上电极层覆盖电容介质层表面。本申请提供的电容结构及其制作方法，增加了环绕第一电容接触层侧壁的电容面积，从而增大了电容的面积，降低了双面电容结构的阻值。

Description

电容结构及其制作方法
本申请要求于2020年10月15日提交中国专利局、申请号为202011105560.5、申请名称为“电容结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储器制作技术领域，特别是涉及一种电容结构及其制作方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的一种半导体存储器，DRAM通常以一个电容和一个晶体管为一个单元排成二维矩阵，主要的作用原理是利用电容内存储的电荷量来代表一个二进制比特(bit)是1还是0。随着制程工艺的持续演进，DRAM集成度不断提高，元件尺寸不断缩小，电容存储电荷容量也面临考验。目前，DRAM中的电容多为单面电容结构，单面电容结构限制了单位面积内电容值的提高，为了提高电容的存储电荷容量，现有技术中提出了可以增加电极层表面积的双面电容结构。
现有的双面电容结构中，电容设置在电容接触层之上，由于下电极板和电容接触层的接触面积小，且电容的面积较小，从而造成双面电容结构的阻值较大。
发明内容
本申请提供一种电容结构及其制作方法，增大了电容的面积，降低了双面电容结构的阻值。
第一方面，本申请提供一种电容结构，包括：
衬底；
第一电容接触层，阵列排布于所述衬底上；
下电极层，围绕所述第一电容接触层侧壁，并沿所述第一电容接触层背离所述衬底的方向延伸；
电容介质层，覆盖所述衬底上表面、所述下电极层表面及所述第一电容接触层上表面；
上电极层，覆盖所述电容介质层表面。
第二方面，本申请提供一种电容结构制作方法，包括：
提供衬底；
在所述衬底上形成一导电层，并在所述导电层上形成电容堆叠层；
图形化所述电容堆叠层和所述导电层，形成阵列排布的至少一个电容柱和与所述电容柱一一对应的第一电容接触层；
沉积第一电极层覆盖所述电容柱侧壁和第一电容接触层侧壁；
去除所述电容柱，保留所述第一电极层和所述第一电容接触层；
沉积电容介质层覆盖所述第一电极层；
沉积第二电极层覆盖所述电容介质层。
本申请提供的电容结构及其制作方法，电容结构由衬底、第一电容接触层、下电极层、电容介质层和上电极层构成，第一电容接触层阵列排布于衬底上，下电极层围绕第一电容接触层侧壁，并沿第一电容接触层背离衬底的方向延伸，电容介质层覆盖衬底上表面、下电极层表面及第一电容接触层上表面，上电极层覆盖电容介质层表面，由于第一电容接触层是阵列排布在衬底上，下电极层围绕第一电容接触层侧壁，即下电极层环绕着第一电容接触层侧壁，因此可以增大下电极层与第一电容接触层的接触面积，由于电容介质层覆盖除阵列排布的第一电容接触层之外的衬底上表面，上电极层覆盖在电容介质层表面，因此相比现有的电容结构中电容设置在第一电容接触层之上，本申请中增加了环绕第一电容接触层侧壁的电容面积，从而增大了电容的面积，降低了双面电容结构的阻值。
附图说明
图1为本申请实施例提供的一种电容结构的示意图；
图2为第一电容接触层的俯视图；
图3为本申请实施例提供的一种电容结构的示意图；
图4为本申请实施例提供的一种电容结构的制作方法流程示意图；
图5为本申请实施例提供的一种电容结构的形成过程中衬底的结构示意图；
图6为本申请实施例提供的一种电容结构的形成过程中导电层和电容堆叠层的结构示意图；
图7为本申请实施例提供的一种电容结构的形成过程中所形成的至少一个电容柱的结构示意图；
图8为本申请实施例提供的一种电容结构的形成过程中图形化电容堆叠层和导电层的过程示意图；
图9为本申请实施例提供的一种电容结构的形成过程中沉积第一电极层后的结构示意图；
图10为本申请实施例提供的一种电容结构的形成过程中去除电容柱后的结构示意图；
图11为本申请实施例提供的一种电容结构的形成过程中去除衬底上表面的第一电极层后的结构示意图；
图12为本申请实施例提供的一种电容结构的形成过程中沉积一层掩膜层和形成光阻后的结构示意图；
图13为本申请实施例提供的一种电容结构的形成过程中去除电容柱的过程示意图；
图14为本申请实施例提供的一种电容结构的形成过程中沉积电容介质层后的结构示意图；
图15为本申请实施例提供的一种电容结构的形成过程中沉积上电极材料层后的结构示意图；
图16为本申请实施例提供的一种电容结构的形成过程中沉积上电极填充层后的结构示意图；
图17为本申请实施例提供的一种电容结构的制作方法流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
现有的双面电容结构中，电容设置在电容接触层之上，由于下电极板和电容接触层的接触面积小，且电容的面积较小，从而造成双面电容结构的阻值较大。为解决这一问题，本申请提供一种电容结构，通过在围绕第一电容接触层侧壁一圈的位置也设置下电极层，即下电极层环绕着第一电容接触层侧壁，因此可以增大下电极层与第一电容接触层的接触面积，将电容介质层覆盖在下电极层表面，电容介质层还覆盖除阵列排布的第一电容接触层之外的衬底上表面，上电极层覆盖在电容介质层表面，因此相比现有的电容结构，本申请中增加了环绕第一电容接触层侧壁的电容面积，从而增大了电容的面积，降低了双面电容结构的阻值。下面结合附图通过具体实施例，对本申请提供的电容结构的具体结构进行详细说明。
本申请提供的电容结构可应用于半导体存储器中，例如可应用于动态随机存取存储器中，动态随机存取存储器包括多个重复的存储单元，每个存储单元可以包括电容和晶体管，晶体管的栅极与字线连接，晶体管的漏极与位线连接，晶体管的源极与电容连接，此处的电容可以使用本申请提供的电容结构。本申请提供的电容结构还可应用于其它半导体器件中，不以此为限。
图1为本申请实施例提供的一种电容结构的示意图，如图1所示，本实施例的电容结构可以包括：衬底101、第一电容接触层102、下电极层103、电容介质层104和上电极层105。
其中，衬底101的材料可以为硅(Si)、锗(Ge)、硅锗(GeSi)或碳化硅(SiC)，也可以是绝缘体上硅或绝缘体上锗，也可以是其它的材料。
在一些实施例中，衬底101中具有有源区，以及隔离各有源区的沟槽隔离结构，衬底101的有源区上可以形成半导体器件，半导体器件例如可以为晶体管。
其中，第一电容接触层102阵列排布于衬底101上，阵列排布可以是等间距的排布在衬底101上，也可以不是等间距的排布在衬底101上，第一电容接触层102的截面可以是圆形、正方形或长方形等形状。以衬底101上排布了8个电容为例，图2为第一电容接触层的俯视图，如图2所示，图2中所示的第一电容接触层102的截面为圆形，第一电容接 触层102具有一定的高度，第一电容接触层102可以为圆柱形结构。可以理解的是，第一电容接触层102还可以是其它柱状结构。第一电容接触层102的材料可以是金属，金属具体可以为钨(W)等。
在一些实施例中，若衬底101的有源区上形成有晶体管时，第一电容接触层102与晶体管电连接。
如图1所示，下电极层103围绕第一电容接触层102侧壁，并沿第一电容接触层102背离衬底101的方向延伸，下电极层103的下表面与衬底101直接接触，下电极层103具有一定高度。作为一种可实施的方式，下电极层103的材料可以为金属氮化物和金属硅化物中的至少一种形成的化合物，如氮化钛(TiN)、硅化钛(TiSi)或硅氮化钛。
电容介质层104覆盖衬底101上表面、下电极层103表面及第一电容接触层102上表面，上电极层105覆盖电容介质层104表面。在一些实施例中，电容介质层104的材料可以为高K介电材料，以提高单位面积电容器的电容值，包括ZrOx、HfOx、ZrTiOx、RuOx、SbOx、AlOx中的一种或上述材料所组成群组中的两种以上所形成的叠层。电容介质层104的材料还可以为氧化硅或其它绝缘材料。
本实施例中，由于第一电容接触层102是阵列排布在衬底101上，下电极层103围绕第一电容接触层102侧壁，即下电极层103环绕着第一电容接触层102侧壁，因此可以增大下电极层103与第一电容接触层102的接触面积，且由于电容介质层104覆盖除阵列排布的第一电容接触层102之外的衬底101上表面，上电极层105覆盖在电容介质层104表面，因此相比现有的电容结构中，电容设置在第一电容接触层之上，本申请中增加了环绕第一电容接触层102侧壁的电容面积，从而增大了电容的面积，降低了双面电容结构的阻值。
进一步地，在一种可实施的方式中，上电极层105包括上电极材料层1051和上电极填充层1052，上电极材料层1051覆盖电容介质层104表面，上电极填充层1052位于上电极材料层1051上表面。作为一种可实施的方式，上电极材料层1051的材料可以为金属氮化物和金属硅化物中的至少一种形成的化合物，如氮化钛(TiN)、硅化钛(TiSi)或硅氮化钛。
其中，上电极填充层1052的材料可以为多晶硅或锗化硅。
本实施例提供的电容结构，由衬底、第一电容接触层、下电极层、电容介质层和上电极层构成，第一电容接触层阵列排布于衬底上，下电极层围绕第一电容接触层侧壁，并沿第一电容接触层背离衬底的方向延伸，电容介质层覆盖衬底上表面、下电极层表面及第一电容接触层上表面，上电极层覆盖电容介质层表面，由于第一电容接触层是阵列排布在衬底上，下电极层围绕第一电容接触层侧壁，即下电极层环绕着第一电容接触层侧壁，因此可以增大下电极层与第一电容接触层的接触面积，且由于电容介质层覆盖除阵列排布的第一电容接触层之外的衬底上表面，上电极层覆盖在电容介质层表面，因此相比现有的电容结构中，电容设置在第一电容接触层之上，本申请中增加了环绕第一电容接触层侧壁的电容面积，从而增大了电容的面积，降低了双面电容结构的阻值。
图3为本申请实施例提供的一种电容结构的示意图，如图3所示，本实施例的电容结构在图1所示电容结构的基础上，进一步地，还可以包括：第二电容接触层106，该第二电容接触层106位于第一电容接触层102上表面，第二电容接触层的形状与第一电容接触 层的形状相同，例如，第一电容接触层102的截面若为圆形，则导电层的截面也为圆形，在本实施例中，电容介质层104覆盖衬底101上表面、下电极层103表面及第二电容接触层106上表面。其中，第二电容接触层106的材料可以是与下电极层103的材料相同。例如，第二电容接触层106的材料可以是金属氮化物和金属硅化物中的至少一种形成的化合物，如氮化钛(TiN)、硅化钛(TiSi)或硅氮化钛。通过增加第二电容接触层106，一方面可以防止第一电容接触层102向电容介质层104扩散，例如第一电容接触层102的材料为金属钨(W)，电容介质层104的材料为氧化硅时，可以防止金属钨向氧化硅扩散。另一方面，第二电容接触层106还可以作为下电极层，因此可以增大下电极层和第一电容接触层102的面积，进一步增大了电容面积。
下面结合附图详细说明本申请提供的电容结构的制作方法。
图4为本申请实施例提供的一种电容结构的制作方法流程示意图，如图4所示，本实施例的方法可以包括：
S101、先提供衬底。
图5为本申请实施例提供的一种电容结构的形成过程中衬底的结构示意图，如图5所示，先提供衬底101，其中衬底101的材料可以为硅(Si)、锗(Ge)、硅锗(GeSi)或碳化硅(SiC)，还可以也可以是绝缘体上硅或绝缘体上锗，也可以是其它的材料。
在一些实施例中，衬底101中具有有源区，以及隔离各有源区的沟槽隔离结构，衬底101的有源区上可以形成半导体器件，半导体器件例如可以为晶体管。
S102、在衬底上形成一导电层，并在导电层上形成电容堆叠层。
图6为本申请实施例提供的一种电容结构的形成过程中导电层和电容堆叠层的结构示意图，请参见图6，在衬底101上形成一导电层201，并在导电层201上形成电容堆叠层202，电容堆叠层202包括一牺牲层2021和顶部支撑层2022。
S103、图形化电容堆叠层和导电层，形成阵列排布的至少一个电容柱和与电容柱一一对应的第一电容接触层。
图7为本申请实施例提供的一种电容结构的形成过程中所形成的至少一个电容柱的结构示意图。请参见图6和图7，图形化电容堆叠层202和导电层201，形成阵列排布的至少一个电容柱203和与电容柱203一一对应的第一电容接触层102。
具体地，图8为本申请实施例提供的一种电容结构的形成过程中图形化电容堆叠层和导电层的过程示意图，作为一种可实施的方式，图形化电容堆叠层202和导电层201，形成阵列排布的至少一个电容柱203和与电容柱203一一对应的第一电容接触层102，可以为：
请参见图8，沉积一掩膜层111覆盖电容堆叠层202中的顶部支撑层2022，掩膜层可以为单层结构或多层结构，掩膜层为多层结构时可以包括多晶硅、碳和氮氧化硅，接着形成一负性光阻112覆盖掩膜层111，接着曝光、显影，沿负性光阻112向下刻蚀，刻蚀到掩膜层111，接着一直刻蚀到衬底101，形成阵列排布的至少一个电容柱203和与电容柱203一一对应的第一电容接触层102。利用负性光阻曝光的地方被保留的特性，可以直接得到特定形状(如圆形)的电容柱结构。在其它实施例中，也可以利用两次图形化工艺得到特定形状的电容柱，图形化工艺包括自对准双重图案化工艺或反向自对准双重图案化工艺。
S104、沉积第一电极层覆盖电容柱侧壁和第一电容接触层侧壁。
图9为本申请实施例提供的一种电容结构的形成过程中沉积第一电极层后的结构示意图，请参见图9，沉积第一电极层301覆盖电容柱203侧壁和第一电容接触层102侧壁，可以用原子层沉积方法沉积第一电极层301，同时还覆盖衬底上表面。此处的沉积工艺可以是化学气相沉积、等离子增强化学气相沉积或低压化学气相沉积等。
S105、去除电容柱，保留第一电极层和第一电容接触层。
接着，图10为本申请实施例提供的一种电容结构的形成过程中去除电容柱后的结构示意图，请参见图10，去除电容柱203，保留第一电极层301和第一电容接触层102，在去除电容柱203的同时，位于电容柱203上表面的第一电极层301和衬底101上表面的第一电极层301也相应被去除。
在一些实施例中，图11为本申请实施例提供的一种电容结构的形成过程中去除衬底上表面的第一电极层后的结构示意图，请参见图11，先去除衬底上表面的第一电极层301。
图12为本申请实施例提供的一种电容结构的形成过程中沉积一层掩膜层和形成光阻后的结构示意图，请参见图12，去除电容柱203具体可以为：沉积一层掩膜层302覆盖电容柱203上表面，接着形成一光阻303覆盖掩膜层302，光阻303具有与电容柱203一一对应的开口。此处的沉积工艺可以是化学气相沉积、等离子增强化学气相沉积或低压化学气相沉积等。
图13为本申请实施例提供的一种电容结构的形成过程中去除电容柱的过程示意图，请参见图13，沿开口去除掩膜层302、顶部支撑层2022和牺牲层2021，得到如图10所示的结构。在一些实施例中，去除顶部支撑层2022可以采用干法刻蚀，去除牺牲层2021可以采用干法刻蚀和湿法刻蚀，湿法刻蚀可以完全去除牺牲层2021。需要说明的是，图10所示的结构中，第一电极层301与图1中的下电极层103对应，即为下电极层103。
S106、沉积电容介质层覆盖第一电极层。
得到如图10所示的结构后，接着，图14为本申请实施例提供的一种电容结构的形成过程中沉积电容介质层后的结构示意图，请参见图14，沉积电容介质层104覆盖第一电极层301。
S107、沉积第二电极层覆盖电容介质层。
具体地，沉积第二电极层(即与图1所示的上电极层105对应)覆盖电容介质层104。
具体地，第二电极层304包括上电极材料层3041和上电极填充层3042，图15为本申请实施例提供的一种电容结构的形成过程中沉积上电极材料层后的结构示意图，请参见图15，沉积第二电极层304覆盖电容介质层104，可以为：
沉积上电极材料层3041覆盖电容介质层104表面，图16为本申请实施例提供的一种电容结构的形成过程中沉积上电极填充层后的结构示意图，接着请参见图16，沉积上电极填充层3042覆盖上电极材料层3041上表面。需要说明的是，上电极材料层3041与图1所示的上电极材料层1051对应，上电极填充层3042与图1所示的上电极材料层1052对应。
本实施例提供的电容结构的制作方法，所制作的电容结构由衬底、第一电容接触层、下电极层、电容介质层和上电极层构成，第一电容接触层阵列排布于衬底上，下电极层围绕第一电容接触层侧壁，并沿第一电容接触层背离衬底的方向延伸，电容介质层覆盖衬底 上表面、下电极层表面及第一电容接触层上表面，上电极层覆盖电容介质层表面，由于第一电容接触层是阵列排布在衬底上，下电极层围绕第一电容接触层侧壁，即下电极层环绕着第一电容接触层侧壁，因此可以增大下电极层与第一电容接触层的接触面积，且由于电容介质层覆盖除阵列排布的第一电容接触层之外的衬底上表面，上电极层覆盖在电容介质层表面，因此相比现有的电容结构中，电容设置在第一电容接触层之上，本申请中增加了环绕第一电容接触层侧壁的电容面积，从而增大了电容的面积，降低了双面电容结构的阻值。
进一步地，在上述电容结构的制作过程中，在另一种可实施的方式中，导电层包括第一导电层和第二导电层，第二导电层的材料与第一电极层的材料相同。在衬底上形成一导电层之后，还可以包括：将第二导电层与第一电极层电连接，使得第二导电层与第一电极层组成下电极。具体以图17所示的流程为例进行说明。
图17为本申请实施例提供的一种电容结构的制作方法流程示意图，如图17所示，本实施例的方法可以包括：
S201、先提供衬底。
S202、在衬底上形成一导电层，导电层包括第一导电层和第二导电层，第二导电层的材料与第一电极层的材料相同，将第二导电层与第一电极层电连接，使得导电层与第一电极层组成下电极。
S203、在导电层上形成电容堆叠层。
S204、图形化电容堆叠层和导电层，形成阵列排布的至少一个电容柱和与电容柱一一对应的第一电容接触层。
S205、沉积第一电极层覆盖电容柱侧壁和第一电容接触层侧壁。
S206、去除电容柱，保留第一电极层和第一电容接触层。
S207、沉积电容介质层覆盖第一电极层。
S208、沉积第二电极层覆盖电容介质层。
本实施例中，具体的过程与图4所示的过程相同，此处不再赘述，最终形成如图3所示的电容结构，本实施例中，由于导电层包括第一导电层和第二导电层(即图3中的第二电容接触层106)，第二导电层的材料与第一电极层的材料相同，相比较图4所示的制作方法，本实施例中通过增加第二导电层，一方面可以防止第一电容接触层向电容介质层扩散，例如第一电容接触层的材料为金属钨(W)时，电容介质层的材料为氧化硅，可以防止金属钨向氧化硅扩散。另一方面，第二导电层还可以作为下电极层，因此可以增大下电极层和第一电容接触层的面积，进一步增大了电容面积。
本申请实施例还提供一种存储器，该存储器包括上述任一种电容结构。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (18)

  1. 一种电容结构，包括：
    衬底；
    第一电容接触层，阵列排布于所述衬底上；
    下电极层，围绕所述第一电容接触层侧壁，并沿所述第一电容接触层背离所述衬底的方向延伸；
    电容介质层，覆盖所述衬底上表面、所述下电极层表面及所述第一电容接触层上表面；
    上电极层，覆盖所述电容介质层表面。
  2. 根据权利要求1所述的电容结构，其中，还包括：
    第二电容接触层，位于所述第一电容接触层上表面；
    所述电容介质层覆盖所述衬底上表面、所述下电极层表面及所述第二电容接触层上表面。
  3. 根据权利要求2所述的电容结构，其中，所述第二电容接触层与所述下电极层电连接，所述第二电容接触层与所述下电极层组成下电极。
  4. 根据权利要求1所述的电容结构，其中，所述上电极层包括上电极材料层和上电极填充层，所述上电极材料层覆盖所述电容介质层表面，所述上电极填充层位于所述上电极材料层上表面。
  5. 根据权利要求4所述的电容结构，其中，所述上电极填充层的材料为多晶硅或锗化硅。
  6. 根据权利要求2所述的电容结构，其中，所述第二电容接触层的形状与所述第一电容接触层的形状相同。
  7. 根据权利要求2所述的电容结构，其中，所述第一电容接触层和所述第二电容接触层均为柱状结构。
  8. 根据权利要求1所述的电容结构，其中，所述衬底的有源区上形成有晶体管，所述第一电容接触层与所述晶体管电连接。
  9. 根据权利要求1所述的电容结构，其中，所述电容介质层为高K介电材料或氧化硅。
  10. 根据权利要求4所述的电容结构，其中，所述上电极材料层的材料为金属氮化物和金属硅化物中的至少一种形成的化合物。
  11. 一种电容结构制作方法，包括：
    提供衬底；
    在所述衬底上形成一导电层，并在所述导电层上形成电容堆叠层；
    图形化所述电容堆叠层和所述导电层，形成阵列排布的至少一个电容柱和与所述电容柱一一对应的第一电容接触层；
    沉积第一电极层覆盖所述电容柱侧壁和第一电容接触层侧壁；
    去除所述电容柱，保留所述第一电极层和所述第一电容接触层；
    沉积电容介质层覆盖所述第一电极层；
    沉积第二电极层覆盖所述电容介质层。
  12. 根据权利要求11所述的方法，其中，所述导电层包括第一导电层和第二导电层，所述第二导电层的材料与所述第一电极层的材料相同。
  13. 根据权利要求12所述的方法，其中，所述方法还包括：
    将所述第二导电层与所述第一电极层电连接，使得所述导电层与所述第一电极层 组成下电极。
  14. 根据权利要求11所述的方法，其中，所述电容堆叠层包括一牺牲层和顶部支撑层，所述去除所述电容柱，包括：
    沉积一层掩膜层覆盖所述电容柱上表面，形成一光阻覆盖所述掩膜层，所述光阻具有与所述电容柱一一对应的开口；
    沿所述开口去除所述掩膜层、所述顶部支撑层和所述牺牲层。
  15. 根据权利要求11所述的方法，其中，所述第二电极层包括上电极材料层和上电极填充层，所述沉积第二电极层覆盖所述电容介质层，包括：
    沉积所述上电极材料层覆盖所述电容介质层表面，沉积所述上电极填充层覆盖所述上电极材料层上表面。
  16. 根据权利要求11所述的方法，其中，所述图形化所述电容堆叠层和所述导电层，形成阵列排布的至少一个电容柱和与所述电容柱一一对应的第一电容接触层，包括：
    沉积一掩膜层覆盖所述电容堆叠层中的顶部支撑层；
    形成一负性光阻覆盖所述掩膜层；通过曝光、显影、沿所述负性光阻向下刻蚀到所述衬底，形成阵列排布的至少一个电容柱和与所述电容柱一一对应的第一电容接触层。
  17. 根据权利要求11所述的方法，其中，还包括：
    去除所述电容柱上表面的第一电极层和所述衬底上表面的第一电极层。
  18. 根据权利要求14所述的方法，其中，去除所述顶部支撑层采用干法刻蚀，去除所述牺牲层采用干法刻蚀和湿法刻蚀。
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