WO2022083466A1 - 一种数据处理的方法及装置 - Google Patents

一种数据处理的方法及装置 Download PDF

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Publication number
WO2022083466A1
WO2022083466A1 PCT/CN2021/123049 CN2021123049W WO2022083466A1 WO 2022083466 A1 WO2022083466 A1 WO 2022083466A1 CN 2021123049 W CN2021123049 W CN 2021123049W WO 2022083466 A1 WO2022083466 A1 WO 2022083466A1
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WIPO (PCT)
Prior art keywords
data
pcie
link
host
data processing
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PCT/CN2021/123049
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English (en)
French (fr)
Inventor
赵晨涛
杨鑫
郑振发
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP21881884.7A priority Critical patent/EP4213030A4/en
Publication of WO2022083466A1 publication Critical patent/WO2022083466A1/zh
Priority to US18/301,799 priority patent/US20230259479A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present application relates to the field of computing, and in particular, to a data processing method and apparatus.
  • a bus is a standardized way of exchanging data between computer components, that is, providing data transmission and control logic for each component in a common way.
  • a bus usually transfers bits (bits) between different components in accordance with preset lines. These lines are only responsible for transmitting one bit at a time. Therefore, multiple lines must be used at the same time to send more data, and the size of the data that the bus can transmit at the same time is called width, which is measured in bits. The larger the bus width, the better the transmission performance, and the bandwidth of the bus. (that is, the total data size that can be transmitted per unit time) can be calculated by multiplying the frequency by the width.
  • PCIe Peripheral Component Interconnect Express
  • PCIe controller chip the higher the version corresponding to the PCIe controller chip, the more channel data it corresponds to, and the larger the maximum bandwidth that can be supported, and the better it can meet the real-time transmission of a larger amount of data.
  • the common v3.x version has a single-channel rate of 985MB/s and 16-channel 15.75GB/s; the current latest v5.x version has a single-channel rate of 3.938GB/s and 16-channel 63.01GB/s.
  • the PCIe controller version is restricted by a variety of physical and economic factors; and the number of PCIe channels is also affected by the module selection, computing unit density, and hardware wiring in the computer, especially in the current Computers are becoming more and more thin and light. Therefore, how to effectively expand the bandwidth through the innovation of the transmission model and the link connection method under the condition that the PCIe version and the number of channels are kept constant, so as to make the design of the system scheme more flexible, is an urgent problem to be solved at present.
  • the present application provides a data processing method, device and system, which can be used in the version of the PCIe controller. Increase the rate at which data is transmitted over the PCIe link while keeping the number of lanes unchanged.
  • the present application provides a data processing system, the data processing system includes a host and a PCIe device, the PCIe device includes a first interface and a second interface, the PCIe device establishes a first PCIe link with the host through the first interface , and establish a second PCIe link with the host through the second interface.
  • the host is used to send the first data to the PCIe device through the first PCIe link, and the second data is sent to the PCIe device through the second PCIe link;
  • the PCIe device is used to receive the first data through the first PCIe link and The second data is received through the second PCIe link, wherein both the first PCIe link and the second PCIe link are in an active state during data transmission.
  • the PCIe device itself may have multiple interfaces, only one interface is connected to the host through the PCIe link during operation.
  • the host is connected to at least two interfaces of the PCIe device through at least two independent PCIe links, and can use these PCIe links to send data, and these independent PCIe links All channels are active during data transmission, so as to improve the rate of data transmission through the PCIe link between the host and the PCIe device while the version of the PCIe controller and the number of channels remain unchanged.
  • the host is further configured to determine data to be transmitted that needs to be sent to the PCIe device, and split the data to be transmitted into first data and second data.
  • the host can actively split the data to be transmitted corresponding to the data transmission task into multiple pieces of data when performing a data transmission task, and transmit the multiple pieces of data simultaneously through multiple links respectively,
  • the method of the present application can transmit the data to be transmitted corresponding to a part of the data transmission tasks in the plurality of data transmission tasks through the first link when receiving multiple data transmission tasks, and the other part of the data transmission tasks corresponds to the transmission.
  • the data to be transmitted is transmitted through the second link; or when a data transmission task is received, the data to be transmitted corresponding to the data transmission task can be actively split, and transmitted through different links, so that the Schemes can be used in more scenarios.
  • the PCIe device is further configured to determine data to be transmitted that needs to be requested from the host, divide the data to be transmitted into first data and second data, and send the data to the host respectively.
  • the host requests the first data and the second data.
  • the operation of determining the data to be transmitted, the first data and the second data can be performed by the PCIe device, so that the solution can be used in more scenarios.
  • splitting the data to be transmitted into the first data and the second data is based on the link state of the first PCIe link and the chain of the second PCIe link road status.
  • the link states of the first PCIe link and the second PCIe link include bandwidths or usage rates of the first PCIe link and the second PCIe link.
  • the data to be transmitted may be evenly split into multiple pieces of data, that is, the split first data and second data have the same size.
  • the data splitting method is relatively simple, and usually the attributes of the multiple links of the host and PCIe link are the same. Therefore, the average splitting method can reduce the split data bandwidth. achieves better results in most cases, at the same time as the overhead.
  • the host is further configured to send the first data to the PCIe device through the first link by means of direct memory access, or by means of direct memory access through the first link.
  • the second link sends the second data to the PCIe device.
  • the host is further configured to, before splitting the data to be transmitted into the first data and the second data, determine that the size of the data to be transmitted exceeds a preset value.
  • the data to be transmitted is compared with the preset value, and the split operation is performed only when the size of the data to be transmitted exceeds the preset value. Since the operation of splitting data will bring a certain amount of overhead, the data splitting and transmission operations through different links are only performed for the data to be transmitted that exceeds a certain size, which is beneficial to improve the efficiency of the data processing system.
  • the host is further configured to, when it is determined that both the first data and the second data have been sent to the PCIe device, send a synchronization signal to the PCIe device, the synchronization signal using to indicate that the data transfer is complete.
  • the PCIe device since the PCIe device does not necessarily know the size of the data to be transmitted, nor does it necessarily know the sizes of the first data and the second data, when the host determines that both the first data and the second data have been transmitted When the synchronization signal is sent to the PCIe device, the PCIe device can determine that the data transmission has been completed, thereby increasing the stability of the data processing system.
  • the PCIe device is further configured to, after determining that the first data is written, adjust the pointer to the end of the storage space, where the storage space is stored in the PCIe device and received to the space for the first data.
  • the pointer is the first address of the space used to indicate the next data writing. Therefore, after the first data is written, the pointer can be adjusted to the end of the storage space for storing the first data, so as to indicate that the next received data is to be stored after the storage space.
  • the host is respectively connected to the first interface and the second interface in the PCIe device through a PCIe switch.
  • the PCIe switch increases the number of PCIe devices or interfaces in the PCIe devices that can be connected to the host, thereby increasing the scalability of the data processing system.
  • the data processing system can be applied to a cloud mobile phone scenario, wherein the host is further configured to, before sending the first data to the PCIe device through the first PCIe link, A data processing task sent by the user is received, where the data processing task corresponds to the data to be transmitted including the first data and the second data.
  • the data processing system is applied to the cloud mobile phone scenario, and the cloud mobile phone scenario often requires a host to support dozens of cloud mobile phones to run games or video rendering tasks at the same time, which requires a large number of connections between the host and the PCIe device.
  • Data transmission, and the real-time requirements for data transmission are relatively high. Therefore, by adopting the practice of splitting the data to be transmitted and sending it through different links, it is beneficial to improve the processing efficiency of the data processing task sent by the user in the cloud mobile phone scenario, and thus improve the user experience.
  • the data processing system can be applied to an artificial intelligence scenario, wherein the host is further configured to, before sending the first data to the PCIe device through the first PCIe link, An artificial intelligence task is received, and the artificial intelligence task corresponds to the data to be transmitted including the first data and the second data.
  • the data processing system is applied to an artificial intelligence scenario, and artificial intelligence tasks, including training tasks or inference tasks, involve a large number of data transmissions between hosts and PCIe devices. Therefore, by adopting the practice of splitting the data to be transmitted and sending it through different links, it is beneficial to improve the efficiency of the data processing system performing artificial intelligence tasks in the artificial intelligence scenario.
  • the present application provides a data processing method.
  • the data processing method is applied to a host.
  • a PCIe device establishes a first PCIe link with the host through a first interface, and establishes a second PCIe link with the host through a second interface.
  • the data processing method includes: sending first data to a PCIe device through a first PCIe link, and sending second data to a PCIe device through a second PCIe link, wherein the first PCIe link and the second PCIe link Active during data transmission.
  • the method further includes: the host determines data to be transmitted that needs to be sent to the PCIe device, and splits the data to be transmitted into first data and second data.
  • splitting the data to be transmitted into the first data and the second data includes: according to the link status of the first PCIe link and the second PCIe link The link state splits the data to be transmitted into first data and second data.
  • the link states of the first PCIe link and the second PCIe link include bandwidths or usage rates of the first PCIe link and the second PCIe link.
  • the sizes of the first data and the second data obtained by splitting are the same.
  • sending the first data to the PCIe device through the first PCIe link includes: using direct memory access to send the first data to the PCIe device through the first PCIe link and sending the second data to the PCIe device through the second PCIe link includes: using direct memory access to send the second data to the PCIe device through the second PCIe link.
  • the method before splitting the data to be transmitted into the first data and the second data, the method further includes: the host determines that the size of the data to be transmitted exceeds a preset value .
  • the method further includes: after the host determines that both the first data and the second data have been sent to the PCIe device, sending a synchronization signal to the PCIe device, the synchronization signal Used to indicate that data transfer is complete.
  • the host is respectively connected to the first interface and the second interface through a PCIe switch.
  • the method further includes: receiving a data transmission request from a PCIe device, where the data transmission request is used to instruct the host to transmit the first data and transmitting the second data over the second link.
  • the data processing method is applied to a cloud mobile phone scenario, wherein, before sending the first data to the PCIe device through the first PCIe link, the method further includes: A data processing task sent by the user is received, where the data processing task corresponds to the data to be transmitted including the first data and the second data.
  • the data processing method is applied to an artificial intelligence scenario, wherein, before sending the first data to the PCIe device through the first PCIe link, the method further includes: An artificial intelligence task is received, the artificial intelligence task corresponding to the data to be transmitted including the first data and the second data.
  • the present application provides a data processing apparatus, wherein a PCIe device establishes a first PCIe link with the data processing apparatus through a first interface, and establishes a second PCIe link with the data processing apparatus through a second interface, and the data
  • the processing device includes a transmission module for sending first data to a PCIe device through a first PCIe link, and sending second data to a PCIe device through a second PCIe link, wherein the first PCIe link and the second PCIe link Active during data transmission.
  • the data processing apparatus further includes: a determining module for determining data to be transmitted that needs to be sent to the PCIe device; a splitting module for determining the data to be transmitted Split into first data and second data.
  • the splitting module is configured to split the data to be transmitted into the following links according to the link status of the first PCIe link and the link status of the second PCIe link. first data and second data.
  • the link states of the first PCIe link and the second PCIe link include bandwidths or usage rates of the first PCIe link and the second PCIe link.
  • the sizes of the first data and the second data are the same.
  • the transmission module is configured to send the first data to the PCIe device through the first PCIe link using direct memory access, and use the direct memory access to send the first data to the PCIe device through the second PCIe link
  • the channel sends the second data to the PCIe device.
  • the determining module is further configured to determine that the first data and the second data have been sent to the PCIe device, and send a synchronization signal to the PCIe device.
  • the data processing apparatus is respectively connected to the first interface and the second interface through a PCIe switch.
  • the transmission module is further configured to receive a data transmission request from a PCIe device, wherein the data transmission request instructs the data processing apparatus to transmit the first PCIe link through the first PCIe link. a data and the second data is transmitted over the second PCIe link.
  • the data processing device is applied to a cloud mobile phone scenario, wherein the transmission module is further configured to receive a data processing task sent by a user, and the data corresponding to the data processing task includes: first data and second data.
  • the data processing device is applied to an artificial intelligence scenario, wherein the transmission module is further configured to receive an artificial intelligence task, and the data corresponding to the artificial intelligence task includes the first data and second data.
  • the present application provides a data processing method, the data processing method is applied to a PCIe device, the PCIe device includes a first interface and a second interface, the PCIe device establishes a first PCIe link with a host through the first interface, and establishing a second PCIe link with the host through the second interface, the data processing method includes: receiving first data sent by the host through the first PCIe link, and receiving second data sent by the host through the second PCIe link, wherein , both the first PCIe link and the second PCIe link are in an active state during data transmission.
  • the method further includes: determining data to be transmitted that needs to be requested from the host, and requesting the host for the first data and the second data respectively according to the data to be transmitted.
  • respectively requesting the first data and the second data from the host according to the data to be transmitted includes: according to the data to be transmitted and the link status and the link status of the first PCIe link
  • the link state of the second PCIe link requests the host for the first data and the second data, respectively.
  • the link states of the first PCIe link and the second PCIe link include bandwidths or usage rates of the first PCIe link and the second PCIe link.
  • the sizes of the first data and the second data are the same.
  • receiving the first data sent by the host through the first PCIe link includes: using direct memory access to receive the first data sent by the host through the first PCIe link and receiving the second data sent by the host through the second PCIe link includes: using a memory to directly access the second data sent by the host through the second PCIe link.
  • the method further includes: before respectively requesting the first data and the second data from the host according to the to-be-transmitted data, determining that the size of the to-be-transmitted data exceeds a preset value .
  • the method further includes: receiving a synchronization signal sent by the host, where the synchronization signal indicates that the first data and the second data have been transmitted.
  • the method further includes: after determining that the first data is written, adjusting the pointer to the end of the storage space, where the storage space is stored in the PCIe device Space for the first data.
  • the first interface and the second interface are connected to the host through a PCIe switch.
  • the data processing method is applied to a cloud mobile phone scenario, wherein the first data and the second data correspond to data processing tasks sent by the user to the host.
  • the data processing method is applied to an artificial intelligence scenario, wherein the first data and the second data correspond to the AI tasks received by the host.
  • the present application provides a data processing device, the data processing device includes a first interface and a second interface, the data processing device establishes a first PCIe link with a host through the first interface, and communicates with the host through the second interface. establishing a second PCIe link, where the data processing apparatus includes: a transmission module configured to receive first data sent by the host through the first PCIe link, and receive second data sent by the host through the second PCIe link, wherein the first data Both the one PCIe link and the second PCIe link are in an active state during data transmission.
  • the data processing apparatus further includes: a determination module for determining data to be transmitted that needs to be requested from the host; a request module for respectively requesting the host according to the data to be transmitted first data and second data.
  • the request module is configured to request the host for the first PCIe link according to the data to be transmitted and the link status of the first PCIe link and the link status of the second PCIe link, respectively. first data and second data.
  • the link states of the first PCIe link and the second PCIe link include bandwidths or usage rates of the first PCIe link and the second PCIe link.
  • the sizes of the first data and the second data are the same.
  • the transmission module is configured to receive the first data sent by the host through the first PCIe link using direct memory access.
  • the transmission module is further configured to: receive a synchronization signal sent by the host, where the synchronization signal indicates that the first data and the second data have been transmitted.
  • the data processing apparatus further includes: an adjustment module, configured to adjust the pointer to the end of the storage space after it is determined that the first data is written, wherein the storage The space is the space for storing the first data in the PCIe device.
  • the first interface and the second interface are connected to the host through a PCIe switch.
  • the data processing apparatus is applied to a cloud mobile phone scenario, wherein the first data and the second data correspond to data processing tasks sent by the user to the host.
  • the data processing apparatus is applied to an artificial intelligence scenario, wherein the first data and the second data correspond to artificial intelligence tasks received by the host.
  • the present application provides a computer device, the computer device comprising a processor and a memory, wherein the memory is used for storing a program code, and the processor is used for executing the program code to implement the second aspect or the fourth aspect.
  • the present application provides a computer-readable storage medium, the computer-readable medium comprising instructions, when the instructions are executed on a computer, causing the computer to execute the data processing method provided in the second or fourth aspect.
  • the present application provides a computer program that, when the computer program runs on a computer, causes the computer to execute the data processing method as provided in the second aspect or the fourth aspect.
  • FIG. 1 is an architectural diagram of a data processing system including a PCIe link.
  • FIG. 2 is an architectural diagram of a data processing system provided by the present application.
  • FIG. 3 is a schematic diagram of a flow of a data processing embodiment provided by the present application.
  • FIG. 4 is a schematic diagram of a scheme for splitting data to be transmitted and transmitting them separately.
  • FIG. 5 is a schematic diagram of a mapping relationship between a memory domain and a PCIe bus domain.
  • FIG. 6 is a schematic diagram of a flow of another data processing embodiment provided by the present application.
  • FIG. 7 is a schematic diagram of the architecture of another data processing system provided by the present application.
  • FIG. 8 is a schematic diagram of a flow of another data processing embodiment provided by the present application.
  • FIG. 9 is a schematic diagram of an artificial intelligence application scenario provided by the present application.
  • FIG. 10 is a schematic diagram of a cloud mobile phone application scenario provided by the present application.
  • FIG. 11 is a schematic diagram of a data processing apparatus provided by the present application.
  • FIG. 12 is a schematic diagram of a data processing apparatus provided by the present application.
  • FIG. 13 is a schematic structural diagram of a computer device provided by the present application.
  • Figure 1 shows the architecture diagram of a data processing system that can expand the bandwidth.
  • the system compresses the data to be transmitted at the sending end and transmits the compressed data through the PCIe link. Under the condition that the PCIe version and the number of channels remain unchanged, more data to be transmitted per unit time is transmitted to the receiving end. This actually increases the rate at which data is transmitted.
  • the data processing system includes two computer devices, which are connected through a PCIe bus, and both run software capable of realizing data compression and data decompression functions. These two functions can be realized by two softwares respectively, or can be integrated in one software.
  • the software is first used to compress the data to be transmitted, so as to Reduce the size of subsequent actual transfers of data.
  • the size of the data to be transmitted is 2 gigabytes (Gigabyte, GB)
  • the compressed data to be transmitted is 1 GB
  • the compressed data of the 1 GB size is transmitted to the computer device B through the PCIe bus.
  • the computer device B After receiving the compressed data, the computer device B restores the compressed data to the original data to be transmitted. If the data transfer rate of the PCIe bus between the computer device A and the computer device B is 50 megabytes (Megabyte, MB) per second, the time required to transmit the compressed data of the size of 1 GB is 20 seconds. And these 20 seconds actually transfer 2GB of data from computer device A to computer device B, so it can be considered that a bandwidth of 100MB/s is actually achieved, so that when the PCIe version and the number of channels remain unchanged, the actual increase the rate of data transfer.
  • the data transfer rate of the PCIe bus between the computer device A and the computer device B is 50 megabytes (Megabyte, MB) per second
  • the time required to transmit the compressed data of the size of 1 GB is 20 seconds. And these 20 seconds actually transfer 2GB of data from computer device A to computer device B, so it can be considered that a bandwidth of 100MB/s is actually achieved, so that when the PCIe version and the number of channels remain
  • the present application provides a method and device for improving bandwidth, which can overcome the constraints of the upper limit of physical bandwidth on system design under the condition that the bus version and the number of channels of PCIe are kept constant, and the multi-channel hardware connection method and The collaborative support of the software that realizes the synchronous transmission function can increase the actual data transmission rate, so as to meet the bandwidth requirements of large data stream transmission without bringing too much computational resource overhead and without introducing too much extra cost.
  • FIG. 2 is an architectural diagram of a data processing system provided by the present application.
  • the data processing system includes a host computer and several sub-system devices.
  • the host may be a computer device such as a server or a personal computer (PC).
  • the subsystem device is connected to the host through the PCIe bus, and can transmit data to and from the host.
  • the subsystem device may be an external device connected to the host, or may be an independent computer device.
  • the subsystem device when the subsystem device is an external device connected to the host, it can either be directly inserted into the card slot on the mainboard of the host, or it can be connected to the host through a cable; it can be located inside the host or located in the host Outside the host, this application does not limit the connection mode and positional relationship between the subsystem device and the host.
  • the host 200 includes a processor 210, a root complex (Root Complex, RC) 220, a PCIe switch (switch) 230, and a memory (not shown in the figure) and other components.
  • the processor 210 is used for interpreting computer instructions and processing data in computer software, and the root complex 220 connects the processor 210 and the memory to a PCIe switch fabric composed of one or more switch devices. Similar to a host bridge in a PCI system, root complex 220 generates transaction requests on behalf of processor 210 .
  • the root complex 220 may be a component independent of the processor 210 , or may be integrated in the processor 210 .
  • FIG. 2 shows the root complex 220 alone as a separate component from the processor 210 , but the present application does not limit the actual shape of the root complex 220 .
  • each PCIe link occupies a PCI bus number, and the PCIe bus uses an end-to-end connection method.
  • a PCIe link can only be connected to one device.
  • each PCIe link can only be connected to one PCIe device, PCIe switch, endpoint device (endpoint, EP) or PCIe bridge.
  • endpoint endpoint
  • PCIe switch needs to be used for link expansion.
  • a standard PCIe switch has one upstream port and multiple downstream ports, where the upstream port can be connected to the root complex or the downstream ports of other PCIe switches, and the downstream ports can be connected to EP, PCIe The upstream port of the bridge or downstream PCIe switch is connected.
  • the PCIe switch extends the link through the specified multiple ports. As shown in FIG. 2 , the four ports of the PCIe switch 230 are respectively connected to different PCIe controllers.
  • the four PCIe controllers belong to two different subsystem devices, that is, each subsystem device may include multiple PCIe controllers, such as a primary PCIe controller and a backup PCIe controller.
  • the number and type of PCIe controllers included in the system device are limited. Among them, the PCIe controller is usually a high-speed bus transceiver that is integrated in a processor chip and supports the PCIe protocol, and can be regarded as an interface of a PCIe device.
  • the number of PCIe controllers integrated in the processor chip can be set according to the specifications of the chip. When the processor chip integrates multiple PCIe controllers, each PCIe controller may occupy a pin of the processor chip, and may establish a link with the host through the pin as a main link or an alternate link.
  • each different PCIe controller on the opposite end is identified as an independent device connected through different links, and there is an independent bus between these PCIe controllers number, device number or function number (bus number/device number/function number, BDF), and an independent BDF will cause different PCIe controllers to be assigned different space addresses.
  • the host can still identify the subsystem devices to which these PCIe controllers belong. For example, the host can recognize that both the PCIe controller 241 and the PCIe controller 242 belong to the subsystem device 240, so when data needs to be sent to the subsystem device 240, the host 200 is connected to the PCIe controller 241 through the first PCIe link ( The data is sent by the second PCIe link (hereinafter referred to as the second link) connected between the host 200 and the PCIe controller 242 (hereinafter referred to as the first link).
  • the second link hereinafter referred to as the second link
  • FIG. 3 is a schematic diagram of a flow of a data processing embodiment provided by the present application.
  • the data processing flow is based on the architecture shown in FIG. 2 .
  • the steps in the flow shown in FIG. 3 will be adopted.
  • the present application takes the host sending data to the subsystem device as an example for description, but the method flow shown in FIG. 3 can also be used for the subsystem device sending data to the host, and the present application does not limit the direction of data transmission.
  • the method flow shown in Figure 3 utilizes multiple controllers of each subsystem device to split the data to be transmitted into multiple copies, which are respectively performed through the link between the host and each controller. transmission, thereby increasing the rate of data transmission while keeping the version and number of lanes of the PCIe bus unchanged.
  • S301 Determine whether the size of the data to be transmitted exceeds a split threshold.
  • the data to be transmitted can be divided into multiple parts and transmitted through different links. Before data splitting, it can be judged whether the data to be transmitted exceeds the preset splitting threshold. When the size of the data to be transmitted exceeds the split threshold, the data to be transmitted is divided into multiple parts according to the number of available links between the host and the subsystem device. For example, as shown in Figure 2, when the host and the subsystem device are connected When there is a first link connecting the host and the primary PCIe controller and a second link connecting the host and the standby PCIe controller, the data to be transmitted can be divided into two parts, and the data to be transmitted can be divided into two parts through the first link and the second link respectively. to transmit. When the size of the data to be transmitted does not exceed the split threshold, the unsplit data to be transmitted is directly transmitted through the first link or the second link.
  • the split threshold is set because a certain overhead may be incurred when the host side performs the split operation on the data, or when the subsystem device side confirms whether the separately transmitted data has been transmitted. Therefore, for relatively small data to be transmitted, the benefits brought by the data processing method provided in this embodiment may not make up for the overhead generated. Therefore, a traditional method can be selected to transmit all the data to be transmitted through one link. For relatively large data to be transmitted, the benefits brought by the data processing method provided by this embodiment often exceed the generated overhead, so the data is first split, and then the split data is passed through different data link for transmission.
  • the setting may be performed according to the data transmission attributes of the first link and/or the second link.
  • the data may be encapsulated into a transaction layer packet (transaction layer packet, TLP) and then transmitted.
  • TLP transaction layer packet
  • a complete TLP includes elements such as TLP header (header) and data payload.
  • the maximum value of the data load of a TLP message is 4 kilobytes (Kilobyte, KB), but a PCIe device may not necessarily be able to send a 4KB TLP, and the TLP that can be sent is subject to "Max_Payload_Size_Supported” and "Max_Payload_Size" "The influence of these two parameters, where the "Max_Payload_Size_Supported” parameter is used to indicate the maximum value of the TLP payload in a PCIe device, which is determined by the hardware logic of the PCIe device and cannot be rewritten by the system software; and the "Max_Payload_Size” parameter is used In order to indicate the maximum value of the data load in the TLP actually used by the PCIe device, this parameter is negotiated and determined by the equipment at both ends of the PCIe link, and is the parameter actually used when the PCIe device carries out data transmission.
  • the dividing threshold is set to the size of the "Max_Payload_Size_Supported” parameter or several times the size of the "Max_Payload_Size” parameter, as a dividing line for determining whether to split the data.
  • the size of the split threshold may also be set by the user of the host. Since the overhead and benefits of split data transmission are affected by many factors, if you only set the attributes of the link itself, you may not be able to obtain the best results. Therefore, in actual use, users can select an appropriate split threshold according to the rate of data transmission of different sizes in different ways.
  • the user or the host itself can also choose not to perform the above judgment, and directly split all the data to be transmitted, and transmit them through different links respectively.
  • This application does not pre-execute whether the size of the data to be transmitted exceeds the split. The operation of the threshold is limited.
  • S302 Split the data to be transmitted into first data and second data.
  • FIG. 4 is a schematic diagram of a scheme for splitting data to be transmitted and transmitting them separately.
  • the data to be transmitted is split, and the data to be transmitted is split into the first data transmitted through the first link and the second data transmitted over the second link.
  • the data to be transmitted may be equally divided. For example, if the size of the data to be transmitted is 1MB, and the links available for data transmission are the first link and the second link, the data to be transmitted is divided into two pieces of data with a size of 0.5MB, and the split data is divided into two pieces. The transmission takes place over the first link and the second link, respectively.
  • the splitting manner of the data to be transmitted may also be determined according to the link states of the first link and the second link.
  • the link status refers to attributes of the link related to data transmission, such as link bandwidth, link usage rate, and the like. Because for a transmission task, when the data to be sent corresponding to the transmission task is transmitted through multiple links, the transmission task can be considered to be completed only when the data corresponding to all the links have been transmitted. Only the receiver can use the complete data. Therefore, it is beneficial to increase the efficiency of data transmission by enabling different links to complete data transmission at the same time as much as possible.
  • the data to be transmitted may be allocated proportionally according to the bandwidth of the first link and the bandwidth of the second link. For example, if the size of the data to be transmitted is 3MB, and the bandwidth of the first link is twice the bandwidth of the second link, 2MB of the data to be transmitted is allocated to the first link, and the remaining 1MB is allocated to the first link. size data is allocated to the second link.
  • the link status refers to the link usage rate
  • less data to be transmitted will be allocated to the link with a high current link usage rate, and more data to be transmitted will be allocated to the link with a low current link usage rate. The data.
  • the host can obtain the attribute information of the two links, so as to obtain the two links bandwidth data. For example, the host can obtain the specifications of the slots occupied by the ports of the first link and the second link. For the same PCIe version, it can be considered that the bandwidth of the X4 slot is twice the bandwidth of the X2 slot. Then, when the first link uses the X4 slot and the second link uses the X2 slot, it can be considered that the bandwidth of the first link is twice the bandwidth of the second link.
  • the bandwidth data of the first link and the bandwidth data of the second link may also be obtained by sending a test packet.
  • the host first uses the first link to send a small test packet, and determines the bandwidth of the first link according to the time required for the packet to be transmitted through the first link and the size of the packet;
  • the second link sends the test packet, and the bandwidth of the second link is determined according to the time required for the packet to be transmitted through the second link and the size of the packet. Since the bandwidth of the link often does not change greatly, the data obtained through the test can be used for a long period of time, and it is not necessary to perform the test every time the data is transmitted.
  • the first data transmitted through the first link and the second data transmitted through the second link may also be determined according to an address alignment parameter (address alignment attribute).
  • address alignment parameter address alignment attribute
  • the alignment parameter is related to the PAGE_SIZE (usually 4K, up to 2M) parameter of the host operating system. If the byte length of the transmitted data is not an integer multiple of PAGE_SIZE, the operating system cannot guarantee that the data is allocated to consecutive physical addresses. When data transmission is performed according to consecutive physical addresses, data mistransmission is likely to occur. In this case, it is possible to first ensure that the first data meets the requirements of the address alignment parameter, and then perform a fill-up operation for the second data according to the address alignment parameter.
  • S303 Send the first data and the second data to the subsystem device through the first link and the second link respectively.
  • the first data and the second data are respectively sent to the first PCIe controller and the second PCIe controller in the subsystem device through the first link and the second link.
  • PCIe controller in order to speed up the rate of data transmission, data transmission can be performed by means of direct memory access (Direct Memory Access, DMA).
  • DMA Direct Memory Access
  • DMA is a technique for rapidly transferring data that allows hardware devices of different speeds to communicate without relying on a heavy interrupt load on the processor. Otherwise, the processor needs to copy each slice's data from the sender to a register, and then write the data to the new place. During this time period, the processor cannot perform other operations. However, using DMA to transfer data is to copy data directly from one address space to another address space.
  • the processor initializes the data transfer action, the data transfer action itself is realized and completed by the DMA controller. For example, when a block of memory outside a chip is moved to a storage area inside the chip, the data transmission operation does not occupy the processing capacity of the processor, and the processor can continue to process other services.
  • the DMA controller When implementing DMA transfer, the DMA controller directly controls the bus, so there is a problem of transfer of bus control rights. That is, before the DMA transfer, the processor transfers the bus control right to the DMA controller, and after the DMA transfer ends, the DMA controller transfers the bus control right to the processor.
  • a complete DMA transfer process needs to go through four steps: DMA request, DMA response, DMA transfer and DMA end.
  • the address information corresponding to the first data and the second data respectively is determined.
  • the address information of the first data or the second data may be represented by an address interval formed by a head address and a tail address, or may be represented by the head address and the length information of the data, which is not limited in this application.
  • the host submits different DMA descriptors (Descriptors) to the split first data and second data, and uses different DMA channels for data transmission.
  • the DMA descriptor also known as the DMA descriptor array, is an array of pointers in the form of unsigned long*hw_desc[DESC_NUM], and each pointer (hw_desc[i]) points to a descriptor.
  • This descriptor is defined by hardware, and its data structure is generally defined by datasheet or sdk.
  • DMA descriptors can be divided into hardware descriptions and software descriptors, wherein the hardware descriptors usually include control bits, data packet addresses, data packet lengths, ring tails and ring links.
  • the software descriptor usually includes information such as horizontal intra-packet fragmentation and vertical multi-packet chaining required to maintain the completed data link information for link tracking.
  • the processor in the host can only directly access the memory space of the host, it cannot directly operate the subsystem device. Therefore, the storage space open to the host in the sub-device system needs to be mapped to the memory space, and when the processor needs to access the storage space of the sub-device system, it only needs to access the corresponding memory space.
  • the subsystem device may have several storage spaces that need to be mapped to the memory space. When the subsystem device leaves the factory, the size and attributes of these storage spaces are written in the base address register (BAR).
  • BAR base address register
  • the system software in the host allocates the corresponding system memory space for the storage space in the subsystem device by reading the information in the BAR, and writes the base address of the allocated system memory space into the BAR.
  • the address of the BAR is the address of the PCIe bus domain
  • the processor accesses the address of the memory domain.
  • the address of the bus domain needs to be converted to the address of the memory domain.
  • FIG. 5 is a schematic diagram of a mapping relationship between a memory domain and a PCIe bus domain.
  • the processor system When the PCIe device uses the DMA mechanism to access the address space of the memory domain, the processor system also needs to inversely map the address space of the memory domain to the PCIe bus address space. Assuming that in a processor system, the size of the main memory is 2GB, its address space in the memory domain is 0x0000-0000 ⁇ 0x7FFF-FFFF, and the corresponding "PCIe bus address space" in the PCIe bus domain is 0x8000- 0000 ⁇ 0xFFFF-FFFF.
  • the address of the PCIe bus domain from 0x8000-0000 to 0xFFFF-FFFF must be used, so that the HOST master bridge can claim the PCIe bus transaction and convert the PCIe bus address used by the bus transaction into memory. address, and perform data transfer with the memory area of 0x0000-0000 ⁇ 0x7FFF-FFFF.
  • mapping method between the memory domain and the PCIe bus domain is only an example for the convenience of describing the embodiments of the present application, and does not limit the protection scope of the present application.
  • both the first link and the second link are in an active state.
  • the link is in the active state means that not only the interface between the host and the subsystem device forms a link through a physical connection, but the link itself has completed the preparations for data transmission, and is in the process of transmitting data or ready to transmit data at any time. status of the data.
  • the transmission of the first data through the first link and the transmission of the second data through the second link can be performed in parallel.
  • the subsystem device When the host sends the first data and second data obtained by splitting the data to be transmitted to the subsystem device through the first link and the second link respectively, the subsystem device does not necessarily know the size of the data to be transmitted, nor does it The sizes of the first data and the second data must be known. Therefore, when the host determines that the data transmission of the first link and the data transmission of the second link have been completed, it needs to send a synchronization signal to the sub-device system.
  • the synchronization signal is used to notify the sub-system device that the data to be transmitted has been transmitted. .
  • the subsystem device receives the synchronization signal, it is determined that the data transmission has been completed.
  • the host can send the first synchronization signal to the subsystem device; and when the first data transmitted through the second link has been transmitted After the second data has been transmitted, the host sends a second synchronization signal to the subsystem device.
  • the present application also does not limit the form of the synchronization signal and the method by which the host sends the synchronization signal to the subsystem device.
  • the host and the subsystem device are also connected through a signal link independent of the data link, the signal link is used to transmit data that requires high immediacy, and the host can pass the signal The link transmits the synchronization signal described above.
  • the storage space of the PCIe domain has a destination cache pointer, which is used to indicate the first address of the next write data. Therefore, when it is determined that the data transmission is completed, the destination cache pointer of the storage space of the PCIe domain needs to be updated, and the updated pointer points to the tail address of the data written this time in the storage space as the next write data. 's first address.
  • the subsystem device When the subsystem device receives the data to be transmitted, the data is written into the shared data buffer in the subsystem operating system, and the shared data buffer is a data storage area for the producer to write and the consumer to read.
  • the producer refers to the provider of the data, for example, the process in the subsystem device responsible for receiving the data to be transmitted.
  • the producer generates data, and after the consumer reads the data, writes the data into the shared data buffer.
  • the consumer refers to the user of the data, such as the process of using the data to be transmitted in the subsystem device, and the consumer obtains the data after the producer writes the data to the shared data cache.
  • the producer/consumer model completes data exchange through two status bits, Flag and Status.
  • the Flag status bit is used by the producer to notify the consumer whether the data is written
  • the Status status bit is used by the consumer to notify the producer whether the data has been written. is read out.
  • Table 1 specifically, when the producer has written data into the shared data buffer, the Flag bit is set to 1.
  • the consumer confirms that the producer has written data into the shared data buffer by identifying the Flag bit as 1, and sets the Flag bit to 0 after reading the data.
  • the Status bit is set to 1.
  • the producer confirms that the producer has read the data from the shared data buffer by identifying the Status as 1.
  • the Status bit is set to 0.
  • Flag Status describe 0 0 Idle state, when the shared data buffer is empty 1 0 The producer writes data, but the consumer does not use the data 0 1 Consumers finish using the data 1 1 error state
  • the above-mentioned producer/consumer model is a method for a process on a subsystem device to use data from a host, and this application does not limit how the subsystem device uses the above-mentioned data to be transmitted.
  • FIG. 6 is a schematic diagram of a flow of another data processing embodiment provided by the present application.
  • the data processing method shown in Figure 3 is that the host actively sends the data to be transmitted to the subsystem device.
  • the subsystem device requests data from the host, and the host then sends the data to be transmitted according to the data request of the subsystem device. Sent to the subsystem device.
  • the data processing flow includes the following steps:
  • S601 The subsystem device acquires the information of the data to be transmitted.
  • the sub-system device requests the host for data to be transmitted, and the requested data to be transmitted is stored in the host, therefore, the sub-system device needs to obtain the information of the data to be transmitted first.
  • the host has determined the data to be transmitted that needs to be sent to the subsystem device next according to the business with the subsystem device.
  • the host can send the information of the data to be transmitted to the subsystem device, so that the subsystem device obtains the information of the data to be transmitted.
  • the subsystem device may obtain information about part or all of the data in the host, for example, information about the data related to the subsystem device in the host. In this case, the subsystem device determines the information of the data to be transmitted from the information of the known data in the host according to the needs of the subsequent service.
  • S602 The subsystem device determines whether the size of the data to be transmitted exceeds a split threshold.
  • step S301 after the subsystem device determines the information of the data to be transmitted, it may first determine whether the size of the data to be transmitted exceeds the split threshold.
  • step S603 is executed, that is, the data to be transmitted is divided into multiple copies according to the data of the available link between the subsystem device and the host, and the split data is requested respectively;
  • step S606 is executed, that is, directly requesting the host for unsplit data to be transmitted.
  • S603 The subsystem device splits the data to be transmitted into first data and second data, and sends a first request for the first data and a second request for the second data to the host.
  • step S302 when the subsystem device determines that the size of the data to be transmitted exceeds the splitting threshold, it determines to split the data to be transmitted, and splits the data to be transmitted into the first data transmitted through the first link by a certain method and the second data transmitted over the second link.
  • the data splitting method has already been illustrated in step S302, and will not be repeated here.
  • the operation of splitting the data to be transmitted in step S603 includes the subsystem device sending the information of the first data and the second data to the host, instructing the host to specifically perform the splitting of the data to be transmitted into the first data and the second data. operate.
  • the information of the first data and the second data may include the size of the data, the storage address in the host, the name of the corresponding file, etc., which are not limited in this application. For example, when the data to be transmitted is 10MB in size, the subsystem operation instructs the host to split the to-be-transmitted data into first data of 6MB and second data of 4MB.
  • S604 The subsystem device receives the first data and the second data.
  • the host After receiving the first request and the second request sent by the subsystem device, the host sends the first data and the second data to the subsystem device through the first link and the second link respectively.
  • the host may send the first data and the second data to the subsystem device respectively by means of DMA, and the sending of the first data and the sending of the second data may be performed simultaneously.
  • the subsystem device Since both the first data and the second data are requested by the subsystem device from the host, in this case, the subsystem device has obtained the information of the first data and the second data, for example, the information of the first data and the second data size. Therefore, the subsystem device can judge by itself whether the data to be transmitted has been transmitted, and can also judge whether the first data transmitted through the first link or the second data transmitted through the second link has been transmitted.
  • the host sends a sync signal.
  • step S305 The method for using the data by the subsystem device goes to step S305, which will not be repeated here.
  • FIG. 7 is a schematic diagram of the architecture of another data processing system provided by the present application.
  • the data processing system includes a first device and a second device, wherein the first device and the second device are both electronic devices that can process data, such as a host, a mobile phone, a mobile Internet device ( mobile internet device, MID) wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control (industrial control), unmanned driving (self driving) Wireless terminal, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, smart home (smart home) wireless terminals, etc.
  • both the first device and the second device are hosts; and in another possible implementation manner, the first device is a host, and the second device is an external device.
  • the second device includes at least two interfaces, the first interface and the second interface are respectively connected to the first device through a first link and a second link, wherein the at least two interfaces of the second device are components that can process data , such as a PCIe controller, a network interface card, etc., and the link between the interface and the first device is used to transmit data.
  • the interfaces of the second device are identified as mutually independent devices, the first device can identify that these interfaces belong to the second device. Therefore, when the first device needs to send data to the second device, the data can be sent through the first link connected to the first interface and/or the second link connected to the second interface.
  • the link between the interface of the second device and the first device is a wired link, that is, the interface and the first device have a physical form of cable or card slot through a bus, a network cable, etc. to connect.
  • data is sent between the interface of the second device and the first device through a preset protocol, such as PCIe protocol, compute express link (CXL) protocol, universal serial bus (Universal Serial Bus, USB) protocol, etc.
  • a preset protocol such as PCIe protocol, compute express link (CXL) protocol, universal serial bus (Universal Serial Bus, USB) protocol, etc.
  • CXL compute express link
  • USB Universal Serial Bus
  • FIG. 8 is a schematic diagram of a flow of another data processing embodiment provided by the present application.
  • the data processing flow is based on the architecture shown in FIG. 7 .
  • the steps in the process shown in FIG. 7 will be used.
  • this application takes the example of sending data from the first device to the second device for description.
  • the method flow shown in FIG. 8 may also be used by the second device to send data to the first device, and this application does not limit the direction of data transmission.
  • the process shown in FIG. 8 includes not only the first device actively sending the data to be transmitted to the second device, but also the second device requesting data from the first device, and the first device then sending the data to the second device according to the data request of the second device.
  • the situation in which the data to be transmitted is sent to the second device.
  • S801 Determine whether the size of the data to be transmitted exceeds a split threshold.
  • step S802 when the first device needs to transmit data to the first device, it may first determine whether the size of the data to be transmitted exceeds the split threshold.
  • step S802 is executed, that is, the data to be transmitted is split into the first data and the second data; and when the size of the data to be transmitted does not exceed the split threshold, step S806 is executed, That is, the unsplit data to be transmitted is directly transmitted through the first link or the second link.
  • Step S801 may be performed by the first device or by the second device.
  • the first device when the first device actively sends the data to be transmitted to the second device, the first device performs the above judgment operation; and when the first device sends the data to be transmitted to the second device according to the data request of the second device When there are two devices, the above judgment operation is performed by the second device.
  • S802 Split the data to be transmitted into first data and second data.
  • steps S302 and S603 when it is determined that the size of the data to be transmitted exceeds the split threshold, it is determined that the data to be transmitted is split, and the data to be transmitted is split into the first data and second data transmitted over the second link.
  • the data splitting method has been illustrated in step S302, and will not be repeated here.
  • Step S802 may be that the first device splits the data to be transmitted into the first data and the second data, or that after the second device obtains the information of the data to be transmitted, the first interface and the second interface respectively send the data to the first interface and the second interface.
  • a device requests the first data and the second data, so that the first device splits the data to be transmitted before the data transmission.
  • S803 The first device sends the first data and the second data to the second device through the first link and the second link respectively.
  • the first device sends the first data and the second data to the second device through the first link and the second link, respectively.
  • the first device may send the first data and the second data to the second device respectively by means of DMA, and the sending of the first data and the sending of the second data may be performed simultaneously.
  • steps S304 and S604 in the case where the first device actively sends the data to be transmitted to the second device, since the second device has not obtained information such as the size of the data to be transmitted, it cannot judge by itself whether the data transmission has been completed, usually It is necessary to determine the completion of data transmission by receiving the synchronization signal sent by the first device; and when the first device sends the data to be transmitted to the second device according to the data request of the second device, the second device has obtained the data to be transmitted, the first The information of the data and the second data can be judged by itself whether the transmission of the data to be transmitted has been completed, and it is not necessary for the first device to send a synchronization signal again.
  • S805 The second device uses the received data.
  • steps S305 and S605 when the second device receives the data to be transmitted, the corresponding process in the second device will read and use the data.
  • FIG. 9 is a schematic diagram of an artificial intelligence (Artificial Intelligence, AI) application scenario provided by the present application.
  • AI Artificial Intelligence
  • the inference node includes a host and several inference cards.
  • the reasoning card is used to provide artificial intelligence reasoning capabilities, and usually includes a graphics processor (Graphics Processing Unit, GPU), a network processor (Network Processing Unit, NPU) or a central processing unit (Central Processing Unit, CPU) with certain computing power ) and other processing units.
  • the reasoning card can support high-definition video real-time analysis, image recognition and other artificial intelligence functions, so it is widely used in smart cities, smart transportation, smart finance and other scenarios.
  • the host includes an artificial intelligence inference service (Artificial Intelligence Inference Service) module, which is used for scheduling and management of AI inference tasks.
  • Artificial Intelligence Inference Service Artificial Intelligence Inference Service
  • the AI inference service module can receive AI inference tasks from the client through the network, and allocate the received AI inference tasks to one or several inference cards through a certain scheduling method, and complete the AI in the inference card. After the reasoning task, receive the results from the reasoning card.
  • the host can also instruct the inference card to process AI training tasks, that is, the host provides the model and training data to the inference card, the inference card uses the model to process the training data, and compares the processing results with the real results. In this way, functions such as model tuning can be realized.
  • the host can be connected to multiple interfaces on the inference card through multiple links respectively.
  • the host and the two interfaces of each inference card are connected through different links, but this application does not limit the number of interfaces of each inference card and the number of interfaces between the inference card and the host.
  • FIG. 10 is a schematic diagram of a cloud mobile phone application scenario provided by the present application.
  • the cloud mobile phone system includes a user part, a network part and a data center part.
  • the user's computer device or intelligent terminal equipment is connected with the host of the data center part through the network.
  • the computer device may be a server, a personal computer (PC), a laptop (laptop), a tablet computer and other equipment
  • the intelligent terminal device may be a mobile phone (mobile phone), a smart head-mounted device, a smart watch and other devices, This application does not limit the types of computer devices and intelligent terminal equipment.
  • the host receives the user's service request, and transfers the task corresponding to the service request to the media card connected to the host for processing. After the media card finishes processing the task, it feeds back the processing result of the task to the server, and the server sends the result to the user's computer device or intelligent terminal device.
  • the media card may be a processing unit such as a graphics processor, a network processor, or a central processing unit that usually includes a certain computing power.
  • a host often needs to support dozens of cloud mobile phones to run applications at the same time. For example, when 30 cloud mobile phones run a large game at the same time, a large amount of image rendering data and data that needs to be calculated will often be generated. All or part of these data needs to be interacted between the server and the media card.
  • the user experience has high requirements on the real-time processing tasks of the cloud mobile phone system, and the data transmission and processing need to be completed in the fastest time possible.
  • the host is connected to multiple interfaces on the media card through multiple links, and the data transmission method between the server and the media card can refer to Figure 3, Figure 6 and Figure 2. 8 shows the method flow.
  • the server is respectively connected with multiple interfaces on the media card through multiple links.
  • the sent data can be divided into multiple parts and transmitted simultaneously through different links, so as to increase the data between the server and the media card under the condition that the bus version and the number of channels are kept constant. transmission bandwidth.
  • FIG. 11 is a schematic diagram of a data processing apparatus provided by the present application.
  • the data processing apparatus may be the host in FIG. 2 , FIG. 9 , and FIG. 10 or the first device in FIG. 7 , or may be the host or a part of the first device.
  • the data processing apparatus is connected with the first interface and the second interface in the PCIe device through the first PCIe link and the second PCIe link, respectively.
  • the data processing apparatus 1100 includes a transmission module 1110 , a determination module 1120 and a splitting module 1130 .
  • the functions of each module are as follows:
  • the transmission module 1110 is configured to: send the first data to the PCIe device through the first PCIe link; and send the second data to the PCIe device through the second PCIe link while sending the first data.
  • the determining module 1120 is configured to: determine the data to be transmitted that needs to be sent to the PCIe device.
  • the splitting module 1130 is used for: splitting the data to be transmitted into first data and second data.
  • the transmission module 1110, the determination module 1120 and the splitting module 1130 can also be used to execute the processes shown in FIG. 3 and FIG. 8 .
  • the transmission module 1110 may perform steps 303 and S306 in FIG. 3 and steps S803 and S806 in FIG. 8 ;
  • the determining module 1120 may perform steps S301 and S304 in FIG. 3 and steps S801 and S804 in FIG. 8 ;
  • the splitting module 1130 may perform step S302 in FIG. 3 and step S802 in FIG. 8 . This application will not repeat them here.
  • FIG. 12 is a schematic diagram of a data processing apparatus provided by the present application.
  • the data processing apparatus may be the subsystem device in FIG. 2 , the first device in FIG. 7 , the accelerator card in FIG. 9 , the media card in FIG. 10 , or a part of the above-mentioned devices.
  • the data processing device includes two interfaces, which are respectively connected with the host through a first PCIe link and a second PCIe link.
  • the data processing apparatus 1200 includes a transmission module 1210 , a determination module 1220 , a request module 1230 and an adjustment module 1240 .
  • the functions of each module are as follows:
  • the transmission module 1210 is configured to: receive the first data sent by the host through the first PCIe link, and receive the second data sent by the host through the second PCIe link while receiving the first data.
  • the determining module 1220 is configured to: determine the data to be transmitted that needs to be requested from the host.
  • the requesting module 1230 is used for: requesting the first data and the second data from the host respectively according to the data to be transmitted
  • the adjustment module 1240 is configured to: after determining that the first data is written, adjust the pointer to the end of the storage space, where the storage space is the space in the data processing apparatus 1200 for storing the first data.
  • the transmission module 1210 , the determination module 1220 , the request module 1230 and the adjustment module 1240 may be used to execute the processes shown in FIGS. 6 and 8 .
  • the transmission module 1210 may perform step S604 in FIG. 6 and steps S803 and S806 in FIG. 8 ;
  • the determining module 1220 may perform steps S601 and S602 in FIG. 6 and steps S801 and S804 in FIG. 8 ;
  • the request module 1230 may perform step S603 in FIG. 6 . This application will not repeat them here.
  • FIG. 13 is a schematic structural diagram of a computer apparatus 1300 provided by an embodiment of the present application.
  • the computer apparatus 1100 in this embodiment may be one of the specific implementations of the computer apparatuses in the foregoing embodiments, and may be the host in FIG. 2 , FIG. 9 , and FIG. 10 , the first device in FIG. 7 , or It may be a PCIe device such as the subsystem device 240 in FIG. 2 , the second device in FIG. 7 , the inference card in FIG. 9 , or the media card in FIG. 10 .
  • the computer device 1300 includes a processor 1301 , and the processor 1301 is connected to a memory 1305 .
  • the processor 1301 can be a field programmable gate array (full name in English: Field Programmable Gate Array, abbreviation: FPGA), or a digital signal processor (full name in English: Digital Signal Processor, abbreviation: DSP) and other computing logic or any of the above computing logic. combination.
  • the processor 1101 may also be a single-core processor or a multi-core processor.
  • the memory 1305 can be RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, or any other form of storage medium known in the art, and the memory can be used to store program instructions that, when executed by the processor 1301, process the memory 1305.
  • the controller 1301 executes the methods described in the above embodiments.
  • connection line 1309 is used to transmit information between various components of the communication device, and the connection line 1309 may use a wired connection manner or a wireless connection manner, which is not limited in this application.
  • the connection line 1309 is also connected to the network interface 1304 .
  • the network interface 1304 implements communication with other devices or the network 1311 using connection means such as, but not limited to, cables or twisted wires.
  • the network interface 1304 may also be interconnected with the network 1311 in a wireless manner.
  • Some features of the embodiments of the present application may be implemented/supported by the processor 1301 executing program instructions or software codes in the memory 1305 .
  • the software components loaded on the memory 1305 can be summarized in terms of functions or logic, for example, the transmission module 1110, the determination module 1120 and the splitting module 1130 shown in FIG. 11 or the transmission module 1210, the determination module 1220, the A request module 1230 and an adjustment module 1240.
  • the processor 1301 executes the transaction related to the above-mentioned function/logic module in the memory 1305 .
  • FIG. 13 is only an example of a computer device 1300, and the computer device 1300 may include more or less components than those shown in FIG. 13, or have a different configuration of the components.
  • various components shown in FIG. 13 may be implemented in hardware, software, or a combination of hardware and software.
  • the memory and the processor may be implemented in one module, and the instructions in the memory may be pre-written into the memory, or may be loaded by the subsequent processor during execution, which is not limited in this application.

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Abstract

针对当前主机和PCIe设备的数据传输速率受到PCIe控制器的版本和通道数制约的问题，为了满足业务的需求，本申请提供一种数据处理方法、装置和系统。在本申请中，主机和PCIe设备的不同接口之间通过不同的PCIe链路进行连接，并通过不同的PCIe链路并行进行数据传输，从而提高数据通过PCIe链路进行传输的速率。

Description

一种数据处理的方法及装置 技术领域
本申请涉及计算领域，特别涉及一种数据处理的方法及装置。
背景技术
总线(bus)，是一种计算机组件间规范化的交换数据的方式，即以一种通行的方式为各组件提供数据传输和控制逻辑。总线通常是按照预设的线路，在不同的组件之间传输比特(bit)。这些线路在同一时间都仅能负责传输一个比特。因此，必须同时采用多条线路才能发送更多数据，而总线可同时传输的数据的大小被称为宽度(width)，以比特为单位，总线宽度越大，传输性能就越好，总线的带宽(即单位时间内可以传输的总数据大小)可以通过频率乘以宽度计算得到。
周边设备高速互联(Peripheral Component Interconnect Express，PCIe)是计算机总线的一种，它基于周边设备连接(Peripheral Component Interconnect，PCI)的编程概念和信号标准，构建了更加高速的串行通信系统标准。不同版本以及不同通道数量的PCIe总线，所能支持的最大带宽也不相同。通常来说，PCIe控制器芯片所对应的版本越高，所对应的通道数据越多，能够支持的最大带宽也就越大，也越能满足较大数据量的实时传输。例如，常见的v3.x版本单通道速率985MB/s，16通道15.75GB/s；当前最新v5.x版本单通道速率3.938GB/s，16通道63.01GB/s。
在现实的系统设计方案中，PCIe控制器版本受多种物理因素和经济因素制约；而PCIe通道的数量也受到计算机中模块选型、计算单元密度以及硬件布线等因素的影响，特别是在当前计算机越来越朝着轻薄化方向发展的情况下。因此，如何能在PCIe版本和通道数保持一定的情况下，通过传输模型和链路连接方式的创新有效拓展带宽，使得系统方案的设计更加灵活，是当前亟待解决的问题。
发明内容
针对当前主机和PCIe设备的数据传输速率受到PCIe控制器的版本和通道数的制约的问题，为了满足业务的需要，本申请提供一种数据处理方法、装置和系统，能够在PCIe控制器的版本和通道数保持不变的情况下，提高数据通过PCIe链路进行传输的速率。
第一方面，本申请提供一种数据处理系统，该数据处理系统包括主机和PCIe设备，该PCIe设备包括第一接口和第二接口，该PCIe设备通过第一接口与主机建立第一PCIe链路，通过第二接口与主机建立第二PCIe链路。其中，主机用于通过第一PCIe链路向PCIe设备发送第一数据，，通过第二PCIe链路向PCIe设备发送第二数据；PCIe设备则用于通过第一PCIe链路接收第一数据以及通过第二PCIe链路接收第二数据，其中，第一PCIe链路和第二PCIe链路在数据传输时均处于激活态。
在现有做法中，虽然PCIe设备本身可以存在多个接口，但在操作中只会有一个接口与主机通过PCIe链路进行连接。而在本申请所提供的数据处理系统中，主机通过至少两条独立的PCIe链路分别与PCIe设备的至少两个接口进行连接，并可以利用这些PCIe链路发送数据，且这些独立的PCIe链路在数据传输时均处于激活态，从而实现在PCIe控制器的版本和通道 数保持不变的情况下，提高数据通过主机和PCIe设备之间的PCIe链路进行传输的速率。
根据第一方面，在本申请一种可能的实现方式中，主机还用于确定需要向PCIe设备发送的待传输数据，并将该待传输数据拆分为第一数据和第二数据。
在上述实现方式中，主机可以在执行一次数据传输任务的时候，将该数据传输任务对应的待传输数据主动拆分为多份数据，并将该多份数据分别通过多条链路同时传输，从而使得本申请的方法既可以在接到多个数据传输任务时，将该多个数据传输任务中的一部分数据传输任务对应的待传输数据通过第一链路进行传输，另一部分数据传输任务对应的待传输数据通过第二链路进行传输；也可以在接到一个数据传输任务时，将该数据传输任务对应的待传输数据主动进行拆分，并通过不同的链路进行传输，从而使得本方案可以在更多场景中被使用。
根据第一方面，在本申请另一种可能的实现方式中，PCIe设备还用于确定需要向主机请求的待传输数据，将该待传输数据分为第一数据和第二数据，并分别向主机请求该第一数据和第二数据。
在上述实现方式中，确定待传输数据、第一数据和第二数据的操作可以由PCIe设备来执行，从而使得本方案可以在更多场景中被使用。
根据第一方面，在本申请另一种可能的实现方式中，将待传输数据拆分为第一数据和第二数据是根据第一PCIe链路的链路状态和第二PCIe链路的链路状态进行的。
根据第一方面，在本申请另一种可能的实现方式中，第一PCIe链路和第二PCIe链路的链路状态包括第一PCIe链路和第二PCIe链路的带宽或者使用率。
在上述实现方式中，通过根据不同链路的链路状态确定待传输数据的拆分方式，可以更合理的给不同链路分配不同大小的待传输数据，例如给带宽较大的链路分配较多的待传输数据，从而从整体上提高了数据处理系统的效率。
根据第一方面，在本申请另一种可能的实现方式中，可以将待传输数据平均拆分为多份数据，即拆分后的第一数据和第二数据大小相同。
在上述实现方式中，数据的拆分方式相对简单，且通常情况下主机和PCIe链路的多条链路的属性都是相同的，因此，采用平均拆分的方式可以在减少拆分数据带来的开销的同时，在大多数情况下实现较优的结果。
根据第一方面，在本申请另一种可能的实现方式中，主机还用于利用直接内存访问的方式通过第一链路向PCIe设备发送第一数据，也可以利用直接内存访问的方式通过第二链路向PCIe设备发送第二数据。
在上述实现方式中，由于在使用直接内存访问时，可以在不需要大量占用中央处理器的资源的情况下完成数据传输，使得中央处理器在数据传输时可以执行别的任务。因此，该实现方式可以提高数据处理系统的效率。
根据第一方面，在本申请另一种可能的实现方式中，主机还用于，在将待传输数据拆分为第一数据和第二数据之前，确定待传输数据的大小超过预设值。
在上述实现方式中，在对待传输数据进行拆分之前，先将待传输数据与预设值进行比较，并当待传输数据的大小超过预设值时才执行拆分操作。由于拆分数据的操作会带来一定的开销，因此只对超过一定大小的待传输数据才执行数据拆分以及通过不同的链路进行传输的操作，有利于提高数据处理系统的效率。
根据第一方面，在本申请另一种可能的实现方式中，主机还用于，当确定第一数据和第二数据都已经发送至PCIe设备时，向PCIe设备发送同步信号，该同步信号用于指示数据传 输已完成。
在上述实现方式中，由于PCIe设备不一定已知待传输数据的大小，也不一定已知第一数据和第二数据的大小，因此，当主机确定第一数据和第二数据都已传输完成时，向PCIe设备发送同步信号，使得PCIe设备可以确定数据传输已完成，从而增加数据处理系统的稳定性。
根据第一方面，在本申请另一种可能的实现方式中，PCIe设备还用于，当确定第一数据写入后，将指针调整至存储空间的末尾，该存储空间为PCIe设备中存储接收到的第一数据的空间。
在上述实现方式中，指针是用于指示下一次数据写入的空间的首地址。因此当第一数据写入后，可以将指针调整到用于存储第一数据的存储空间的末尾，从而指示在该存储空间之后继续存储下一次接收的数据。
根据第一方面，在本申请另一种可能的实现方式中，主机通过PCIe交换器分别与PCIe设备中的第一接口和第二接口进行连接。
在上述实现方式中，PCIe交换器增加了主机所能连接的PCIe设备或者PCIe设备中的接口的数量，从而增加了数据处理系统的扩展性。
根据第一方面，在本申请另一种可能的实现方式中，数据处理系统可以应用于云手机场景，其中，主机还用于，在通过第一PCIe链路向PCIe设备发送第一数据之前，接收用户发送的数据处理任务，该数据处理任务对应包括第一数据和第二数据在内的待传输数据。
在上述实现方式中，数据处理系统应用于云手机场景，而云手机场景往往需要一台主机支撑几十台云手机同时运行游戏或者视频渲染任务，而这需要主机和PCIe设备之间有着大量的数据传输，且对数据传输的实时性要求较高。因此，通过采用将待传输数据拆分并通过不同链路的进行发送的做法，有利于在云手机场景下提高对于用户发送的数据处理任务的处理效率，并进而提高用户体验。
根据第一方面，在本申请另一种可能的实现方式中，数据处理系统可以应用于人工智能场景，其中，主机还用于，在通过第一PCIe链路向PCIe设备发送第一数据之前，接收人工智能任务，该人工智能任务对应包括第一数据和第二数据在内的待传输数据。
在上述实现方式中，数据处理系统应用于人工智能场景，而人工智能任务，包括训练任务或者推理任务，涉及大量的主机和PCIe设备之间的数据传输。因此，通过采用将待传输数据拆分并通过不同链路的进行发送的做法，有利于在人工智能场景下提高数据处理系统执行人工智能任务的效率。
第二方面，本申请提供一种数据处理方法，该数据处理方法应用于主机，PCIe设备通过第一接口与该主机建立第一PCIe链路，并通过第二接口与该主机建立第二PCIe链路，该数据处理方法包括：通过第一PCIe链路向PCIe设备发送第一数据，并通过第二PCIe链路向PCIe设备发送第二数据，其中，第一PCIe链路与第二PCIe链路在数据传输时均处于激活态。
根据第二方面，在本申请一种可能的实现方式中，该方法还包括：主机确定需要向PCIe设备发送的待传输数据，并将该待传输数据拆分为第一数据和第二数据。
根据第二方面，在本申请另一种可能的实现方式中，将待传输数据拆分为第一数据和第二数据，包括：根据第一PCIe链路的链路状态和第二PCIe链路的链路状态将待传输数据拆分为第一数据和第二数据。
根据第二方面，在本申请另一种可能的实现方式中，第一PCIe链路和第二PCIe链路的链路状态包括第一PCIe链路和第二PCIe链路的带宽或者使用率。
根据第二方面，在本申请另一种可能的实现方式中，拆分得到的第一数据和第二数据的 大小相同。
根据第二方面，在本申请另一种可能的实现方式中，通过第一PCIe链路向PCIe设备发送第一数据，包括：利用直接内存访问通过第一PCIe链路向PCIe设备发送第一数据；而通过第二PCIe链路向PCIe设备发送第二数据，包括：利用直接内存访问通过第二PCIe链路向PCIe设备发送第二数据。
根据第二方面，在本申请另一种可能的实现方式中，在将待传输数据拆分为第一数据和第二数据之前，该方法还包括：主机确定待传输数据的大小超过预设值。
根据第二方面，在本申请另一种可能的实现方式中，该方法还包括：主机确定第一数据和第二数据都已经发送至PCIe设备后，向该PCIe设备发送同步信号，该同步信号用于指示数据传输已完成。
根据第二方面，在本申请另一种可能的实现方式中，主机通过PCIe交换器分别与第一接口和第二接口进行连接。
根据第二方面，在本申请另一种可能的实现方式中，该方法还包括：接收来自于PCIe设备的数据传输请求，其中，该数据传输请求用于指示主机通过第一链路传输第一数据以及通过第二链路传输第二数据。
根据第二方面，在本申请另一种可能的实现方式中，该数据处理方法应用于云手机场景，其中，在通过第一PCIe链路向PCIe设备发送第一数据之前，该方法还包括：接收用户发送的数据处理任务，该数据处理任务对应于包括第一数据和第二数据在内的待传输数据。
根据第二方面，在本申请另一种可能的实现方式中，该数据处理方法应用于人工智能场景，其中，在通过第一PCIe链路向PCIe设备发送第一数据之前，该方法还包括：接收人工智能任务，该人工智能任务对应于包括第一数据和第二数据在内的待传输数据。
第三方面，本申请提供一种数据处理装置，PCIe设备通过第一接口与该数据处理装置建立第一PCIe链路，并通过第二接口与该数据处理装置建立第二PCIe链路，该数据处理装置包括传输模块，用于通过第一PCIe链路向PCIe设备发送第一数据，以及通过第二PCIe链路向PCIe设备发送第二数据，其中，第一PCIe链路和第二PCIe链路在数据传输时均处于激活态。
根据第三方面，在本申请一种可能的实现方式中，该数据处理装置还包括：确定模块，用于确定需要向PCIe设备发送的待传输数据；拆分模块，用于将该待传输数据拆分为第一数据和第二数据。
根据第三方面，在本申请另一种可能的实现方式中，拆分模块用于，根据第一PCIe链路的链路状态和第二PCIe链路的链路状态将待传输数据拆分为第一数据和第二数据。
根据第三方面，在本申请另一种可能的实现方式中，第一PCIe链路和第二PCIe链路的链路状态包括第一PCIe链路和第二PCIe链路的带宽或者使用率。
根据第三方面，在本申请另一种可能的实现方式中，第一数据和第二数据的大小相同。
根据第三方面，在本申请另一种可能的实现方式中，传输模块用于，利用直接内存访问通过第一PCIe链路向PCIe设备发送第一数据，并利用直接内存访问通过第二PCIe链路向PCIe设备发送第二数据。
根据第三方面，在本申请另一种可能的实现方式中，确定模块还用于，确定第一数据和第二数据已发送至PCIe设备，并向PCIe设备发送同步信号。
根据第三方面，在本申请另一种可能的实现方式中，数据处理装置通过PCIe交换器分别与第一接口和第二接口进行连接。
根据第三方面，在本申请另一种可能的实现方式中，传输模块还用于，接收来自PCIe设备的数据传输请求，其中，该数据传输请求指示数据处理装置通过第一PCIe链路传输第一数据以及通过第二PCIe链路传输第二数据。
根据第三方面，在本申请另一种可能的实现方式中，数据处理装置应用于云手机场景，其中，传输模块还用于，接收用户发送的数据处理任务，该数据处理任务对应的数据包括第一数据和第二数据。
根据第三方面，在本申请另一种可能的实现方式中，数据处理装置应用于人工智能场景，其中，传输模块还用于，接收人工智能任务，该人工智能任务对应的数据包括第一数据和第二数据。
第四方面，本申请提供一种数据处理方法，该数据处理方法应用于PCIe设备，该PCIe设备包括第一接口和第二接口，该PCIe设备通过第一接口与主机建立第一PCIe链路，并通过第二接口与主机建立第二PCIe链路，该数据处理方法包括：通过第一PCIe链路接收主机发送的第一数据，并通过第二PCIe链路接收主机发送的第二数据，其中，第一PCIe链路与第二PCIe链路在数据传输时均处于激活态。
根据第四方面，在本申请一种可能的实现方式中，该方法还包括：确定需要向主机请求的待传输数据，并根据待传输数据分别向主机请求第一数据和第二数据。
根据第四方面，在本申请另一种可能的实现方式中，根据待传输数据分别向主机请求第一数据和第二数据，包括：根据待传输数据以及第一PCIe链路的链路状态和第二PCIe链路的链路状态分别向主机请求第一数据和第二数据。
根据第四方面，在本申请另一种可能的实现方式中，第一PCIe链路和第二PCIe链路的链路状态包括第一PCIe链路和第二PCIe链路的带宽或者使用率。
根据第四方面，在本申请另一种可能的实现方式中，第一数据和第二数据的大小相同。
根据第四方面，在本申请另一种可能的实现方式中，通过第一PCIe链路接收主机发送的第一数据，包括：利用直接内存访问通过第一PCIe链路接收主机发送的第一数据；而通过第二PCIe链路接收主机发送的第二数据，包括：利用内存直接访问通过第二PCIe链路接收主机发送的第二数据。
根据第四方面，在本申请另一种可能的实现方式中，该方法还包括：在根据待传输数据分别向主机请求第一数据和第二数据之前，确定待传输数据的大小超过预设值。
根据第四方面，在本申请另一种可能的实现方式中，该方法还包括：接收主机发送的同步信号，该同步信号指示第一数据和第二数据已经传输完成。
根据第四方面，在本申请另一种可能的实现方式中，该方法还包括：当确定第一数据写入后，将指针调整到存储空间的末尾，其中，该存储空间为PCIe设备中存储第一数据的空间。
根据第四方面，在本申请另一种可能的实现方式中，第一接口和第二接口通过PCIe交换器与主机进行连接。
根据第四方面，在本申请另一种可能的实现方式中，该数据处理方法应用于云手机场景，其中，第一数据和第二数据对应于用户发送给主机的数据处理任务。
根据第四方面，在本申请另一种可能的实现方式中，该数据处理方法应用于人工智能场景，其中，第一数据和第二数据对应于主机接收的AI任务。
第五方面，本申请提供一种数据处理装置，该数据处理装置包括第一接口和第二接口，该数据处理装置通过第一接口与主机建立第一PCIe链路，并通过第二接口与主机建立第二PCIe链路，，该数据处理装置包括：传输模块，用于通过第一PCIe链路接收主机发送的第一 数据，通过第二PCIe链路接收主机发送的第二数据，其中，第一PCIe链路与第二PCIe链路在数据传输时均处于激活态。
根据第五方面，在本申请一种可能的实现方式中，数据处理装置还包括：确定模块，用于确定需要向主机请求的待传输数据；请求模块，用于根据待传输数据分别向主机请求第一数据和第二数据。
根据第五方面，在本申请一种可能的实现方式中，请求模块用于，根据待传输数据以及第一PCIe链路的链路状态和第二PCIe链路的链路状态分别向主机请求第一数据和第二数据。
根据第五方面，在本申请另一种可能的实现方式中，第一PCIe链路和第二PCIe链路的链路状态包括第一PCIe链路和第二PCIe链路的带宽或者使用率。
根据第五方面，在本申请一种可能的实现方式中，第一数据和第二数据的大小相同。
根据第五方面，在本申请一种可能的实现方式中，传输模块用于，利用直接内存访问通过第一PCIe链路接收主机发送的第一数据。
根据第五方面，在本申请一种可能的实现方式中，传输模块还用于：接收主机发送的同步信号，其中，该同步信号指示第一数据和第二数据已传输完成。
根据第五方面，在本申请一种可能的实现方式中，数据处理装置还包括：调整模块，用于，当确定第一数据写入后，将指针调整至存储空间的末尾，其中，该存储空间为PCIe设备中存储第一数据的空间。
根据第五方面，在本申请一种可能的实现方式中，第一接口和所述第二接口通过PCIe交换器与主机进行连接。
根据第五方面，在本申请一种可能的实现方式中，该数据处理装置应用于云手机场景，其中，第一数据和第二数据对应于用户发送给主机的数据处理任务。
根据第五方面，在本申请一种可能的实现方式中，该数据处理装置应用于人工智能场景，其中，第一数据和第二数据对应于主机接收的人工智能任务。
第六方面，本申请提供一种计算机装置，该计算机装置包括处理器和存储器，其中，该存储器用于存储程序代码，该处理器用于执行该程序代码以实现如第二方面或第四方面所提供的数据处理方法。
第七方面，本申请提供一种计算机可读存储介质，该计算机可读介质包括指令，当指令在计算机上运行时，使得计算机执行如第二方面或第四方面所提供的数据处理方法。
第八方面，本申请提供一种计算机程序，当该计算机程序在计算机上运行时，使得计算机执行如第二方面或第四方面所提供的数据处理方法。
附图说明
图1是一种包含PCIe链路的数据处理系统的架构图。
图2是本申请所提供的一种数据处理系统的架构图。
图3是本申请所提供的一种数据处理实施例的流程的示意图。
图4是一种将待传输数据拆分并分别传输的方案的示意图。
图5是一种存储器域和PCIe总线域的映射关系的示意图。
图6是本申请所提供的另一种数据处理实施例的流程的示意图。
图7是本申请提供的另一种数据处理系统的架构的示意图。
图8是本申请所提供的另一种数据处理实施例的流程的示意图。
图9是本申请所提供的一种人工智能应用场景的示意图。
图10是本申请所提供的一种云手机应用场景的示意图。
图11是本申请所提供的一种数据处理装置的示意图。
图12是本申请所提供的一种数据处理装置的示意图。
图13为本申请所提供的计算机装置的结构示意图。
具体实施方式
为了能在PCIe版本和通道数不变的前提下增加数据传输的速率，图1给出了一种能扩展带宽的数据处理系统的架构图。该系统通过在发送端压缩待传输数据，并通过PCIe链路传输压缩后的数据，在PCIe版本和通道数量保持不变的情况下，使得单位时间内更多的待传输数据传输到了接收端，从而实际上增加了传输数据的速率。
具体来说，如图1所示，该数据处理系统包括两个计算机装置，这两个计算机装置通过PCIe总线进行连接，且都运行着可以实现数据压缩功能和数据解压缩功能的软件。这两个功能既可以通过两个软件分别实现，也可以集成在一个软件内，当这两个计算机装置中的计算机装置A向计算机装置B发送数据时，首先利用软件对待传输数据进行压缩，从而减少后续实际传输的数据的大小。例如，待传输数据的大小为2吉字节(Gigabyte，GB)，压缩后的待传输数据为1GB大小，并通过PCIe总线将该1GB大小的压缩数据传输给计算机装置B。而当计算机装置B接收到该压缩数据后，再将该压缩数据还原为原始的待传输数据。如果计算机装置A和计算机装置B之间的PCIe总线的数据传输速率为50兆字节(Megabyte，MB)每秒时，则传输该1GB大小的压缩数据所需要的时间为20秒。而这20秒实际上是将2GB的数据从计算机装置A传输到了计算机装置B，因此可以认为实际上实现了100MB/s的带宽，从而在PCIe版本和通道数都保持不变的情况下，实际上增加了数据传输的速率。
然而，采用如图1所示的数据处理系统进行数据传输时，会带来一些问题。第一，该方案带来的带宽提升能力有限，该带宽能力受限于软件所采用的压缩算法的压缩比、算法负载度以及接收端和发送端的计算能力；第二，由于发送端和接收端分别需要进行数据的压缩和解压缩的操作，这对于发送端和接收端的处理器资源有额外占用，从而对系统算力和功耗都会造成额外的开销；第三，会引入压缩软件的开发和使用成本，而如果选择第三方软件或者开源软件，还可能会造成系统存在质量风险，并使得软件管理变得更加复杂。
基于上述问题，本申请提供一种提高带宽的方法及装置，可以在PCIe的总线版本、通道数量保持一定的情况下，克服物理带宽上限对于系统设计的约束，并通过多通道的硬件连接方式和实现同步传输功能的软件的协同支持，实现数据实际传输速率的增加，从而在不带来过多计算资源的开销以及不引入过多额外成本的情况下，满足大数据流传输对于带宽的要求。
图2是本申请所提供的一种数据处理系统的架构图。如图2所示，该数据处理系统包括主机和若干个子系统设备。主机可以是服务器、个人电脑(personal computer,PC)等计算机装置。子系统设备通过PCIe总线与主机进行连接，并可以与主机之间相互传输数据。其中，子系统设备可以是与主机相连接的外接设备，也可以是独立的计算机装置。其中，当子系统设备为与主机相连接的外接设备时，既可以直接插入主机的主板上的卡槽中，也可以是通过线缆与主机进行连接；既可以位于主机的内部，也可以位于主机的外部，本申请不对子系统设备与主机的连接方式和位置关系进行限定。
如图2所示，主机200包括处理器210、根复合体(Root Complex，RC)220、PCIe交 换器(switch)230以及内存(图中未示出)等部件。其中，处理器210用于解释计算机指令以及处理计算机软件中的数据，根复合体220将处理器210和内存连接到一个或者多个交换设备组成的PCIe交换结构中。类似于PCI系统中的主机桥，根复合体220代表处理器210生成事务请求。其中，根复合体220既可以作为独立于处理器210的部件，也可以被集成在处理器210中。图2单独示出了根复合体220，将其作为独立于处理器210的部件，但本申请不对根复合体220的实际形态进行限定。
从系统软件的角度上看，每一条PCIe链路都占用一个PCI总线号，且PCIe总线使用端到端的连接方式，理论上一条PCIe链路都只能连接一个设备。例如，每一条PCIe链路只能连接有一个PCIe设备、PCIe交换器、端点设备(endpoint，EP)或者PCIe桥片。当一条PCIe链路上需要挂载多个EP时，需要使用PCIe交换器使用链路扩展。一个标准PCIe交换器具有一个上游端口(upstream port)和多个下游端口(downstream port)，其中，上游端口可以与根复合体或者其他PCIe交换器的下游端口相连，而下游端口可以与EP、PCIe桥或者下游PCIe交换器的上游端口相连。
PCIe交换器通过所具体的多个端口进行链路扩展。如图2所示，PCIe交换器230的4个端口分别于不同的PCIe控制器进行连接。其中，该4个PCIe控制器分别属于两个不同的子系统设备，也即每个子系统设备可以包括多个PCIe控制器，例如一个主PCIe控制器和一个备PCIe控制器，本申请不对每个子系统设备包括的PCIe控制器的数量和类型进行限定。其中，PCIe控制器通常为集成在处理器芯片中，支持PCIe协议的高速总线收发器，可以视为PCIe设备的接口。处理器芯片所集成的PCIe控制器的数量可以根据芯片的规格设定。当处理器芯片集成多个PCIe控制器时，每个PCIe控制器可占用处理器芯片的一个引脚，并可以通过引脚与主机建立链路，作为主链路或者备选链路。
对于主机(或者说对于主机中的处理器)来说，对端的每个不同PCIe控制器会被识别为通过不同链路进行连接的独立的设备，并且，这些PCIe控制器之间具有独立的总线号、设备号或者功能号(bus number/device number/function number，BDF)，而独立的BDF会使得不同的PCIe控制器被分配不同的空间地址。
需要指出的是，虽然PCIe控制器本身具有独立的BDF且被主机识别为相互独立的设备，但在本申请中，主机仍然可以识别这些PCIe控制器所隶属的子系统设备。例如，主机可以识别PCIe控制器241和PCIe控制器242都属于子系统设备240，因此会在需要向子系统设备240发送数据时，通过主机200与PCIe控制器241连接的第一PCIe链路(以下简称第一链路)以及主机200与PCIe控制器242连接的第二PCIe链路(以下简称第二链路)发送该数据。
图3为本申请所提供的一种数据处理实施例的流程的示意图。
该数据处理的流程是基于图2所示的架构进行的，当图2中的主机与某一个子系统设备之间传输数据时，将采用如图3所示的流程中的步骤。为了方便说明，本申请以主机向子系统设备发送数据为例进行说明，但子系统设备向主机发送数据也可以使用图3所示的方法流程，本申请不对数据传输的方向进行限定。
总的来说，图3所示的方法流程利用了每个子系统设备所具有的多个控制器，将待传输数据拆分为多份，分别通过主机与每个控制器之间的链路进行传输，从而在保持PCIe总线的版本和通道数量不变的情况下，增加了数据传输的速率。
S301：判断待传输数据的大小是否超过拆分阈值。
由于在本实施例中，可以将待传输数据拆分为多份，通过不同链路进行传输。而在数据 拆分之前，可以先判断待传输的数据是否超过预设的拆分阈值。当待传输数据的大小超过拆分阈值时，将待传输数据根据主机和子系统设备之间可用的链路的数量拆分为多份，例如，如图2所示，当主机和子系统设备之间具有主机和主PCIe控制器连接的第一链路以及主机和备PCIe控制器连接的第二链路时，可以将待传输数据分为2份，并分别通过第一链路和第二链路进行传输。而当待传输数据的大小不超过拆分阈值时，则直接通过第一链路或者第二链路传输未拆分的待传输数据。
之所以设置拆分阈值，是因为在主机侧对数据执行拆分操作时，抑或是在子系统设备侧确认分别传输的数据是否已经传输完毕时，都有可能产生一定的开销。因此，对于比较小的待传输数据，采用本实施例所提供的数据处理方法带来的收益可能会弥补不了产生的开销，因此可以选择传统的方法，将全部待传输数据通过一条链路进行传输；而对于比较大的待传输数据，采用本实施例所提供的数据处理方法带来的收益往往会超过所产生的开销，因此先对数据进行拆分，再将拆分后的数据通过不同的数据链路进行传输。
对于拆分阈值的设定，在本申请一种可能的实现方式中，可以根据第一链路和/或第二链路的数据传输方面的属性进行设定。例如，主机和主PCIe控制器通过第一链路传输数据时，可以将数据封装为事务层报文(transaction layer packet，TLP)再进行传输。一个完整的TLP包括TLP头(header)、数据负载(data payload)等元素。在PCIe总线中，TLP报文的数据负载的最大值为4千字节(Kilobyte，KB)，但是PCIe设备并不一定能发送4KB大小的TLP，而能够发送的TLP受到“Max_Payload_Size_Supported”和“Max_Payload_Size”这两个参数的影响，其中，“Max_Payload_Size_Supported参数用于指示一个PCIe设备中TLP有效负载的最大值，该参数由PCIe设备的硬件逻辑确定，系统软件不能改写该参数；而“Max_Payload_Size”参数用于指示PCIe设备实际使用的TLP中的数据负载的最大值，该参数由PCIe链路两端的设备协商决定，是PCIe设备进行数据传输时实际使用的参数。而在本实施例中，可以将拆分阈值设置为“Max_Payload_Size_Supported”参数大小或者“Max_Payload_Size”参数大小的若干倍，作为确定是否对数据进行拆分的分界线。
而在本申请另一种可能的实现方式中，还可以由主机的用户对拆分阈值的大小进行设定。由于拆分数据发送所产生的开销以及收益均受到很多因素的影响，如果仅仅通过链路本身的属性进行设定，不一定能获取到最佳的效果。因此，可以让用户在实际使用中，根据不同方式传输不同大小的数据的速率，选择合适的拆分阈值。
另外，用户或者主机本身也可以选择不执行上述判断，直接对所有待传输数据都进行拆分，并分别通过不同的链路进行传输，本申请不对是否预先执行判断待传输数据大小是否超过拆分阈值的操作进行限定。
S302：将待传输数据拆分为第一数据和第二数据。
图4是一种将待传输数据拆分并分别传输的方案的示意图。
如图4所示，当确定待传输数据的大小超过拆分阈值时，确定对待传输数据进行拆分，并通过一定的方法将待传输数据拆分为通过第一链路传输的第一数据和通过第二链路传输的第二数据。
数据拆分的方法可以有多种，以下对其中的几种数据拆分方法进行举例说明。需要指出的是，本申请不对数据方法的方式进行限定。
在本申请一种可能的实现方式中，可以对待传输的数据进行均分。例如，待传输数据的大小为1MB，可供数据传输的链路为第一链路和第二链路，则将待传输数据分为2个0.5MB大小的数据，并将拆分后的数据分别通过第一链路和第二链路进行传输。
采用均分待传输数据的方式进行数据拆分，简单易行，且主机和子系统设备间的多条PCIe链路的属性往往是相同或者相近的，因此使用该方法通常也能取得较好的效果。
在本申请另一种可能的实现方式中，还可以根据第一链路和第二链路的链路状态确定待传输数据的拆分方式。其中，链路状态的是指链路与数据传输相关的属性，例如链路带宽、链路使用率等。由于对于一个传输任务来说，当该传输任务对应的待发送数据通过多条链路进行数据传输时，只有当所有链路对应的数据都传输完毕，才能认为该传输任务已经完成，在此基础上接收方才可以对完整的数据进行使用。因此，尽可能地使不同链路同时完成数据传输，有利于增加数据传输的效率。而当链路状态是指链路带宽，且第一链路的带宽和第二链路的带宽不同时，为了使第一链路和第二链路同时或者以较为近似的时间完成数据传输，可以根据第一链路的带宽和第二链路的带宽按比例分配需要传输的数据。例如，待传输数据的大小为3MB，而第一链路的带宽是第二链路带宽的两倍，则将待传输数据中2MB大小的数据分配给第一链路，并将剩下的1MB大小的数据分配给第二链路。类似的，当链路状态是指链路使用率时，会为当前链路使用率已经较高的链路少分配需要传输的数据，为当前链路使用率较低的链路多分配需要传输的数据。
为了分别确定第一链路和第二链路的带宽，或者确定第一链路与第二链路带宽的比，可以由主机获取这两条链路的属性信息，从而获得这两条链路的带宽数据。例如，主机可以获取第一链路和第二链路的端口所占用的插槽的规格。对于同样的PCIe版本，可以认为X4插槽的带宽为X2插槽的带宽的2倍。那么当第一链路使用X4插槽，而第二链路使用X2插槽时，可以认为第一链路的带宽为第二链路的带宽的2倍。
另外，对于第一链路的带宽和第二链路的带宽数据，也可以通过发送测试报文的方式来获取。例如，主机先利用第一链路发送一个较小的测试报文，根据该报文通过第一链路进行传输所需时间以及该报文的大小，确定第一链路的带宽；再利用第二链路发送该测试报文，根据该报文通过第二链路进行传输所需时间以及该报文的大小，确定第二链路的带宽。由于链路的带宽往往不会发生较大的变化，因此，可以在较长的一段时间使用通过测试获取的数据，而不需要每次数据传输的时候都进行测试。
在本申请另一种可能的实现方式中，还可以根据地址对齐参数(address alignment attribute)确定通过第一链路传输的第一数据和通过第二链路传输的第二数据。当主机和子系统设备传输数据时，往往需要按照地址对齐参数，对所传输的数据进行补齐。对齐参数和主机操作系统的PAGE_SIZE(通常是4K，最大可到2M)参数有关。如果传输数据字节长度不是PAGE_SIZE的整数倍，操作系统无法保证数据被分配到连续的物理地址上，当按照连续物理地址进行数据传输时，很可能会发生数据误传。在这种情况下，可以先确保第一数据满足地址对齐参数的要求，再根据地址对齐参数对第二数据进行补齐操作。
S303：将第一数据和第二数据分别通过第一链路和第二链路发送到子系统设备中。
如图4所示，当完成对待传输数据的拆分后，将第一数据和第二数据分别通过第一链路和第二链路发送给子系统设备中的第一PCIe控制器和第二PCIe控制器。其中，为了加快数据传输的速率，可以选择通过直接存储器访问(Direct Memory Access，DMA)的方式进行数据传输。
DMA是一种快速传输数据的技术，它允许不同速度的硬件装置来沟通，而不需要依赖于处理器的大量中断负载。否则，处理器需要从发送端将每一分片的数据复制到寄存器，然后再将这些数据写到新的地方。在这个时间段内，处理器无法进行其他的操作。而利用DMA进行数据传输是将数据从一个地址空间直接复制到另一个地址空间，当处理器初始化数据传 输动作时，该数据传输动作本身是由DMA控制器来实现和完成的。例如当移动一个芯片外部的内存的区块到芯片内部的存储区域时，该数据传输的操作并不会占用处理器的处理能力，处理器可以继续处理其他的业务。
在实现DMA传输时，是由DMA控制器直接控制总线，因此，存在着一个总线控制权转移的问题。即在DMA传输前，处理器将总线控制权交给DMA控制器，而在结束DMA传输后，DMA控制器将总线控制权再交给处理器。一个完整的DMA传输过程需要经过DMA请求、DMA响应、DMA传输和DMA结束等4个步骤。
在本申请中，根据S302中的数据拆分方法以及待传输数据的首地址，确定第一数据和第二数据分别对应的地址信息。其中，第一数据或第二数据的地址信息可以采用首地址和尾地址所构成的地址区间表示，也可以采用首地址以及数据的长度信息来表示，本申请不对此进行限定。
主机将拆分得到的第一数据和第二数据通过提交不同的DMA描述符(Descriptor)，采用不同的DMA通道进行数据传输。其中，DMA描述符，通常又称为DMA描述符数组，是一个形如unsigned long*hw_desc[DESC_NUM]的指针数组，每个指针(hw_desc[i])指向一个描述符。这个描述符是由硬件定义的，其数据结构一般由datasheet或sdk定义。DMA描述符可以分为硬件描述符合软件描述符，其中，硬件描述符通常包括控制位、数据包地址、数据包长度、环尾标和环链结。而软件描述符通常包括维系完成的数据链信息所需要的横向的包内分片和纵向的多包链化等信息以便进行链接跟踪。
由于主机中的处理器只能直接访问主机的内存空间，不能对子系统设备直接操作。因此，子设备系统中开放给主机的存储空间需要被映射到内存空间，当处理器需要访问该子设备系统的存储空间时，只需要访问对应的内存空间。而子系统设备作为一个PCIe设备，可能会有若干个存储空间需要被映射到内存空间。而当子系统设备出厂时，这些存储空间的大小和属性都写在基地址寄存器(base address register，BAR)中。主机中的系统软件通过读取BAR中的信息，分别为子系统设备中的存储空间分配相应的系统内存空间，并将所分配的系统内存空间的基地址写会到BAR中。换句话说，BAR的地址为PCIe总线域的地址，而处理器访问的是存储器域的地址，当处理器访问PCIe设备时，需要把总线域的地址转换为存储器域的地址。
图5是一种存储器域和PCIe总线域的映射关系的示意图。
当PCIe设备使用DMA机制访问存储器域的地址空间时，处理器系统同样需要将存储器域的地址空间反向映射到PCIe总线地址空间。假设在一个处理器系统中，主存储器大小为2GB，其在存储器域的地址空间为0x0000-0000～0x7FFF-FFFF，而这段地址在PCIe总线域中对应的“PCIe总线地址空间”为0x8000-0000～0xFFFF-FFFF。因此，当PCIe设备进行DMA操作时，必须使用0x8000-0000～0xFFFF-FFFF这段PCIe总线域的地址，HOST主桥才能认领这个PCIe总线事务，并将这个总线事务使用的PCIe总线地址转换为存储器地址，并与0x0000-0000～0x7FFF-FFFF这段存储器区域进行数据传递。
需要指出的是，上述存储器域和PCIe总线域之间的映射方式，只是为了便于说明本申请实施例的一种举例，并不对本申请的保护范围进行限定。
在本方案中，当主机进行数据传输时，第一链路和第二链路均处于激活态。其中，链路处于激活(active)态是指，不仅主机和子系统设备的接口之间通过物理上的连接形成链路，链路本身已完成数据传输的准备工作，处于正在传输数据或者随时可以传输数据的状态。
进一步的，为了加快数据传输的速率，在一种可能的实现方式中，第一数据通过第一链 路传输和第二数据通过第二链路传输可以并行进行，通过这种方法，使得同一时间内有多条链路进行数据传输，从而增加了主机和子系统设备之间的带宽。
S304：确定数据传输完成。
当主机分别通过第一链路和第二链路向子系统设备发送待传输数据拆分得到的第一数据和第二数据时，子系统设备并不一定已知待传输数据的大小，也不一定已知第一数据和第二数据的大小。因此，当主机确定第一链路的数据传输和第二链路的数据传输都已完成后，需要向子设备系统发送同步信号，该同步信号用于知会子系统设备待传输数据已经传输完成。当子系统设备接收到同步信号后，确定数据传输已完成。
在本申请另一种可能的实现方式中，也可以当通过第一链路传输的第一数据已传输完成后，主机向子系统设备发送第一同步信号；而当通过第二链路传输的第二数据已传输完成后，主机向子系统设备发送第二同步信号。
本申请也不限定同步信号的形式以及主机将同步信号发送给子系统设备的方法。在本申请一种可能的实现方式中，主机和子系统设备还通过独立于数据链路的信号链路进行连接，该信号链路用于传输对即时性要求较高的数据，主机可以通过该信号链路发送上述同步信号。
另外，每当数据发送至子系统设备时，都需要占用一定的存储空间。PCIe域的存储空间具有目的缓存指针，用于指示下次写入数据的首地址。因此，当确定数据传输完成后，需要将PCIe域的存储空间的目的缓存指针进行更新，而更新后的指针指向本次所写入的数据在存储空间中的尾地址，作为下次写入数据的首地址。
S305：子系统设备使用数据。
当子系统设备接收到待传输数据时，该数据被写入子操作系统中的共享数据缓冲中，该共享数据缓冲是供生产者写入，而消费者读取的数据存储区域。其中，生产者是指数据的提供方，例如子系统设备中负责接收待传输数据的进程。生产者产生数据，并在消费者将数据读出后，再将数据写入共享数据缓冲中。而消费者是指数据的使用方，例如子系统设备中使用待传输数据的进程，消费者在生产者将数据写入共享数据缓存后，再获取数据。
生产者/消费者模型通过Flag和Status两个状态位完成数据的交换，其中，Flag状态位用于生产者通知消费者数据是否写入，而Status状态位用于消费者通知生产者数据是否已经被读出。如表1所示，具体来说，当生产者已经将数据写入共享数据缓冲后，将Flag位置1。消费者通过识别Flag位为1确认生产者已经将数据写入共享数据缓冲中，并在将数据读出后，将Flag位置为0。相应的，当消费者已经将数据从共享数据缓冲中读出后，将Status位置为1。生产者通过识别Status位置为1确认生成者已经将数据从共享数据缓冲中读出。而当生产者后续再向数据缓冲中写入数据后，将Status位置为0。
表1 Flag和Status状态位
Flag Status 描述
0 0 空闲状态，此时共享数据缓冲为空
1 0 生产者写入数据，但消费者没有使用该数据
0 1 消费者使用完毕该数据
1 1 错误状态
上述生产者/消费者模型是子系统设备上的进程使用来自主机的数据的一种方法，本申请不对子系统设备如何使用上述待传输数据的方式进行限定。
图6是本申请所提供的另一种数据处理实施例的流程的示意图。
图3所示的数据处理方法是由主机主动将待传输数据发送给子系统设备，在实际中，也 有可能是子系统设备向主机请求数据，主机再根据子系统设备的数据请求将待传输数据发送给子系统设备。如图6所示，当由子系统设备向主机数据时，数据处理的流程包括下列步骤：
S601：子系统设备获取待传输数据的信息。
由于在本实施例中，是由子系统设备向主机请求待传输数据，而所请求的待传输数据存储于主机之中，因此，子系统设备需要首先获取待传输数据的信息。
在一种可能的实现方式中，主机根据和子系统设备之间的业务，已经确定了接下来需要发送给子系统设备的待传输数据。在这种情况下，主机可以将待传输数据的信息发送给子系统设备，从而使得子系统设备获取该待传输数据的信息。
在另一种可能的实现方式中，子系统设备可以获取主机中部分或全部数据的信息，例如，主机中与子系统设备相关的数据的信息。在这种情况下，子系统设备根据后续业务的需要，从已知的主机中的数据的信息中确定待传输数据的信息。
S602：子系统设备确定待传输数据的大小是否超过拆分阈值。
参考步骤S301，当子系统设备确定了待传输数据的信息后，可以先判断待传输数据的大小是否超过了拆分阈值。当待传输数据大于拆分阈值时，则执行步骤S603，即将待传输数据根据子系统设备和主机之间可用链路的数据拆分为多份，并分别请求拆分后的数据；而当待传输数据的大小不超过拆分阈值时，则执行步骤S606，即直接向主机请求未拆分的待传输数据。
S603：子系统设备将待传输数据拆分为第一数据和第二数据，并向主机发送请求第一数据的第一请求和请求第二数据的第二请求。
参考步骤S302，当子系统设备确定待传输数据的大小超过拆分阈值时，确定对待传输数据进行拆分，并通过一定的方法将待传输数据拆分为通过第一链路传输的第一数据和通过第二链路传输的第二数据。其中，对于数据的拆分方法，已经在步骤S302处进行举例说明，此处不再赘述。
需要指出的是，在步骤S302中，执行拆分待传输数据操作的主机拥有该待传输数据，而在步骤S603中，执行拆分待传输数据操作的子系统设备实际上只有关于待传输数据的信息。因此，步骤S603中的拆分待传输数据的操作包括子系统设备通过发送第一数据和第二数据的信息给主机，指示主机具体执行将待传输数据拆分为第一数据和第二数据的操作。其中，第一数据和第二数据的信息可以包括数据的大小、在主机中的存储地址、所对应的文件的名称等，本申请不对此进行限定。例如，当待传输数据为10MB大小时，子系统操作指示主机将该待传输数据拆分为6MB大小的第一数据和4MB大小的第二数据。
S604：子系统设备接收第一数据和第二数据。
当主机收到子系统设备发送的第一请求和第二请求后，通过第一链路和第二链路分别将第一数据和第二数据发送给子系统设备。其中，参考步骤S303，主机可以通过DMA的方式分别将第一数据和第二数据发送给子系统设备，且发送第一数据和发送第二数据可以同时进行。
由于第一数据和第二数据都是子系统设备向主机请求的，在这种情况下，子系统设备已获取了第一数据和第二数据的信息，例如，第一数据和第二数据的大小。因此，子系统设备可以自行判断待传输数据是否已经传输完毕，也可以分别判断通过第一链路传输的第一数据或者通过第二链路传输的第二数据是否已经传输完毕，而不需要由主机发送同步信号。
S605：子系统设备使用数据。
子系统设备使用数据的方法参加步骤S305，此处不再赘述。
图7是本申请提供的另一种数据处理系统的架构的示意图。
如图7所示，数据处理系统包括第一设备和第二设备，其中，第一设备和第二设备均为可以进行数据处理的电子设备，例如主机、手机(mobile phone)、移动互联网设备(mobile internet device，MID)可穿戴设备、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程手术(remote medical surgery)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等。在一种可能的实现方式中，第一设备和第二设备均为主机；而在另一种可能的实现方式中，第一设备为主机，而第二设备为外接设备。第二设备包括至少两个接口，第一接口和第二接口分别通过第一链路和第二链路与第一设备进行连接，其中，第二设备的至少两个接口是可以处理数据的组件，例如PCIe控制器、网络接口卡等，接口与第一设备之间的链路用于传输数据。而对于第一设备来说，虽然第二设备的各个接口被识别为相互独立的设备，但第一设备可以识别这些接口都隶属于第二设备。因此，当第一设备需要向第二设备发送数据时，可以通过与第一接口连接的第一链路和/或与第二接口连接的第二链路发送该数据。
在本申请一种可能的实现方式中，第二设备的接口与第一设备之间的链路为有线链路，即接口与第一设备通过总线、网线等具有实体形态的线缆或者卡槽进行连接。
在本申请一种可能的实现方式中，第二设备的接口与第一设备之间通过预设的协议发送数据，例如PCIe协议、计算快速互联(compute express link，CXL)协议、通用串行总线(Universal Serial Bus，USB)协议等，本申请不对接口与第一设备之间用于数据传输的协议的种类进行限定。
图8是本申请所提供的另一种数据处理实施例的流程的示意图。
该数据处理的流程是基于图7所示的架构进行的。当图7中的第一设备与第二之间传输数据时，将采用如图7所示的流程中的步骤，为了方便说明，本申请以第一设备向第二设备发送数据为例进行说明，但第二设备向第一设备发送数据也可以使用图8所示的方法流程，本申请不对数据传输的方向进行限定。
另外，图8所示的流程既包括第一设备主动将待传输数据发送给第二设备的情况，也包括第二设备向第一设备请求数据，第一设备再根据第二设备的数据请求将待传输数据发送给第二设备的情况。
S801：判断待传输数据的大小是否超过拆分阈值。
参考步骤S301和S602，当第一设备需要向第一设备传输数据时，可以先判断待传输数据的大小是否超过了拆分阈值。当待传输的数据超过拆分阈值时，则执行步骤S802，即将待传输数据拆分为第一数据和第二数据；而当待传输数据的大小不超过拆分阈值时，则执行步骤S806，即直接通过第一链路或者第二链路传输未拆分的待传输数据。
步骤S801既可以由第一设备执行，也可以由第二设备执行。通常来说，在第一设备主动将待传输数据发送给第二设备的情况下，由第一设备执行上述判断操作；而当第一设备根据第二设备的数据请求将待传输数据发送给第二设备时，由第二设备执行上述判断操作。
S802：将待传输数据拆分为第一数据和第二数据。
参考步骤S302和S603，当确定待传输数据的大小超过拆分阈值时，确定对待传输数据进行拆分，并通过一定的方法将待传输数据拆分为通过第一链路传输的第一数据和通过第二链路传输的第二数据。其中，对于数据的拆分方法，已经在步骤S302处进行举例说明，此处 不再赘述。
步骤S802既可以是第一设备将待传输数据拆分为第一数据和第二数据，也可以是当第二设备获取到待传输数据的信息后，通过第一接口和第二接口分别向第一设备请求第一数据和第二数据，从而使得第一设备在数据传输前对待传输数据进行拆分。
S803：第一设备将第一数据和第二数据分别通过第一链路和第二链路发送到第二设备中。
参考步骤S303和S604，当对待传输数据拆分完成后，第一设备通过第一链路和第二链路分别将第一数据和第二数据发送给第二设备。其中，第一设备可以通过DMA的方式分别将第一数据和第二数据发送给第二设备，且发送第一数据和发送第二数据可以同时进行。
S804：确定数据传输完成。
参考步骤S304和S604，在第一设备主动将待传输数据发送给第二设备的情况下，由于第二设备并没有获取关于待传输数据的大小等信息，无法自行判断数据传输是否已经完成，通常需要通过接收第一设备发送的同步信号来确定数据传输完成；而当第一设备根据第二设备的数据请求将待传输数据发送给第二设备时，第二设备已获取待传输数据、第一数据和第二数据的信息，可以自行判断待传输数据是否已经传输完成，而不需要由第一设备再发送同步信号。
S805：第二设备使用所接收到的数据。
参考步骤S305和S605，当第二设备接收到待传输数据时，第二设备中相应的进程将读取并使用该数据。
图9是本申请所提供的一种人工智能(Artificial Intelligence，AI)应用场景的示意图。
如图9所示，推理节点包括主机以及若干个推理卡。其中，推理卡用于提供人工智能推理能力，通常包括具有一定算力的图形处理器(Graphics Processing Unit，GPU)、网络处理器(Network Processing Unit，NPU)或中央处理器(Central Processing Unit，CPU)等处理单元。推理卡可支持高清视频实时分析、图像识别等人工智能功能，从而被广泛应用于智慧城市、智慧交通、智慧金融等场景。相应的，主机中包括人工智能推理服务(Artificial Intelligence Inference Service)模块，用于AI推理任务的调度和管理。具体来说，AI推理服务模块可以通过网络从客户端处接收AI推理任务，并通过一定的调度方法将接收到的AI推理任务分配给某个或者某几个推理卡，并且在推理卡完成AI推理任务后，接收推理卡得出的结果。在另外一种可能的实现方式中，主机还可以指示推理卡处理AI训练任务，即主机提供模型和训练数据给推理卡，推理卡利用模型处理训练数据，并将处理结果与真实结果进行对比，从而实现模型调优等功能。
由于在推理节点处理AI推理任务或AI训练的过程中，主机中的AI推理服务模块与推理卡存在着大量的数据传递，例如AI推理任务所涉及的特征数据或者AI训练任务所涉及的模型和训练数据，而为了增加该推理节点的工作效率，可以如图9所示，使得主机通过多条链路分别与推理卡上的多个接口进行连接。为了方便说明，图9中主机和每一个推理卡的2个接口通过不同的链路进行连接，但本申请不对每个推理卡接口数量以及推理卡和主机之间的接口数量进行限定。
当主机向推理卡发送数据时，可以参考如图3、图6和图8所示的方法流程，即将所发送的数据切分成多个部分，通过不同的链路同时传输各部分数据，从而在总线版本、通道数量保持一定的情况下，增加主机和推理卡之间数据传输的带宽。
图10是本申请所提供的一种云手机应用场景的示意图。
如图10所示，云手机系统包括用户部分、网络部分和数据中心部分。其中，用户的计算 机装置或者智能终端设备通过网络与数据中心部分的主机进行连接。其中，计算机装置可以是服务器、个人电脑(personal computer，PC)、笔记本电脑(laptop)、平板电脑等设备，智能终端设备可以是手机(mobile phone)、智能头戴式设备、智能手表等设备，本申请不对计算机装置和智能终端设备的类型进行限定。
在数据中心部分，主机接收用户的业务请求，并将该业务请求对应的任务传递给与主机进行连接的媒体卡进行处理。当媒体卡处理完任务后，将任务的处理结果反馈给服务器，再由服务器将该结果发送给用户的计算机装置或者智能终端设备。其中，媒体卡可以是通常包括具有一定算力的图形处理器、网络处理器或中央处理器等处理单元。
由于在云手机系统中，一个主机往往需要支持数十个云手机同时运行应用。例如，当30台云手机同时运行大型游戏时，往往会产生大量的图像渲染的数据和需要运算的数据，这些数据的全部或者部分需要在服务器和媒体卡之间进行交互。且云手机应用场景，用户的使用体验对云手机系统处理任务的实时性的要求较高，需要在尽可能快的时间内完成数据的传输和处理。
因此，在数据中心部分，如图10所示，主机通过多条链路分别与媒体卡上的多个接口进行连接，服务器和媒体卡之间的数据传输方法可以参考图3、图6和图8所示的方法流程。具体来说，服务器通过多条链路分别与媒体卡上的多个接口进行连接。当服务器需要向媒体卡发送数据时，可以将所发送的数据切分成多份，通过不同的链路同时传输，从而在总线版本、通道数量保持一定的情况下，增加服务器和媒体卡之间数据传输的带宽。
图11是本申请所提供的一种数据处理装置的示意图。其中，该数据处理装置可以为图2、图9、图10中的主机或图7中的第一设备，也可以是主机或者第一设备的一部分。该数据处理装置分别通过第一PCIe链路和第二PCIe链路与PCIe设备中的第一接口和第二接口进行连接。
如图11所示，数据处理装置1100包括传输模块1110、确定模块1120和拆分模块1130。其中，各个模块的作用如下：
传输模块1110用于：通过第一PCIe链路向PCIe设备发送第一数据；并在发送第一数据的同时，通过第二PCIe链路向PCIe设备发送第二数据。
确定模块1120用于：确定需要向PCIe设备发送的待传输数据。
拆分模块1130用于：将待传输数据拆分为第一数据和第二数据。
传输模块1110、确定模块1120和拆分模块1130还可以用于执行如图3和图8所示的流程。具体来说，传输模块1110可以执行图3中的步骤303和S306以及图8中的步骤S803和S806；确定模块1120可以执行图3中的步骤S301和S304以及图8中的步骤S801和S804；拆分模块1130可以执行图3中的步骤S302和图8中的步骤S802。本申请在此不再赘述。
图12是本申请所提供的一种数据处理装置的示意图。其中，该数据处理装置可以为图2中的子系统设备、图7中的第一设备、图9中的加速卡、图10中的媒体卡，也可以为上述设备的一部分。该数据处理装置包括两个接口，分别通过第一PCIe链路和第二PCIe链路与主机进行连接。
如图12所示，数据处理装置1200包括传输模块1210、确定模块1220、请求模块1230和调整模块1240。其中，各个模块的作用如下：
传输模块1210用于：通过第一PCIe链路接收主机发送的第一数据，并在接收第一数据的同时，通过第二PCIe链路接收主机发送的第二数据。
确定模块1220用于：确定需要向主机请求的待传输数据。
请求模块1230用于：根据待传输数据分别向主机请求第一数据和第二数据
调整模块1240用于：当确定第一数据写入后，将指针调整至存储空间的末尾，该存储空间为数据处理装置1200中存储第一数据的空间。
传输模块1210、确定模块1220、请求模块1230和调整模块1240可以用于执行如图6和图8所示的流程。具体来说，传输模块1210可以执行图6中的步骤S604以及图8中的步骤S803和S806；确定模块1220可以执行图6中的步骤S601和S602以及图8中的步骤S801和S804；请求模块1230可以执行图6中的步骤S603。本申请在此不再赘述。
图13为本申请的实施例所提供的计算机装置1300的结构示意图。本实施例中的计算机装置1100可以是上述各实施例中的计算机装置的其中一种具体实现方式，既可以为图2、图9、图10中的主机、图7中的第一设备，也可以为图2中的子系统设备240、图7中的第二设备、图9中的推理卡或图10中的媒体卡等PCIe设备。
如图13所示，计算机装置1300包括处理器1301，处理器1301与存储器1305连接。处理器1301可以为现场可编程门阵列(英文全称：Field Programmable Gate Array，缩写：FPGA)，或数字信号处理器(英文全称：Digital Signal Processor，缩写：DSP)等计算逻辑或以上任意计算逻辑的组合。处理器1101也可以为单核处理器或多核处理器。
存储器1305可以是RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器或者本领域熟知的任何其它形式的存储介质，存储器可以用于存储程序指令，该程序指令被处理器1301执行时，处理器1301执行上述实施例中的所述的方法。
连接线1309用于在通信装置的各部件之间传递信息，连接线1309可以使用有线的连接方式或采用无线的连接方式，本申请并不对此进行限定。连接线1309还连接有网络接口1304。
网络接口1304使用例如但不限于电缆或电绞线一类的连接装置，来实现与其他设备或网络1311之间的通信，网络接口1304还可以通过无线的形式与网络1311互连。
本申请实施例的一些特征可以由处理器1301执行存储器1305中的程序指令或者软件代码来完成/支持。存储器1305上在加载的软件组件可以从功能或者逻辑上进行概括，例如，图11所示的传输模块1110、确定模块1120和拆分模块1130或者图12所示的传输模块1210、确定模块1220、请求模块1230和调整模块1240。
在本申请的一个实施例中，当存储器1305加载程序指令后，处理器1301执行存储器1305中的上述功能/逻辑模块相关的事务。
此外，图13仅仅是一个计算机装置1300的例子，计算机装置1300可能包含相比于图13展示的更多或者更少的组件，或者有不同的组件配置方式。同时，图13中展示的各种组件可以用硬件、软件或者硬件与软件的结合方式实施。例如，存储器和处理器可以在一个模块中实现，存储器中的指令可以是预先写入存储器的，也可以是后续处理器在执行的过程中加载的，本申请不对此进行限定。

Claims (34)

  1. 一种数据处理系统，其特征在于，所述数据处理系统包括主机和周边设备高速互联PCIe设备，所述PCIe设备通过第一接口与所述主机建立第一PCIe链路，所述PCIe设备通过第二接口与所述主机建立第二PCIe链路，其中，
    所述主机用于通过所述第一PCIe链路向所述PCIe设备发送第一数据，以及通过所述第二PCIe链路向所述PCIe设备发送第二数据；
    所述PCIe设备用于接收通过所述第一PCIe链路接收所述第一数据，以及通过所述第二PCIe链路接收所述第二数据；
    其中，所述第一PCIe链路与所述第二PCIe链路在数据传输时均处于激活态。
  2. 根据权利要求1所述的数据处理系统，其特征在于，
    所述主机还用于确定需要向所述PCIe设备发送的待传输数据；
    将所述待传输数据拆分为所述第一数据和所述第二数据。
  3. 根据权利要求1所述的数据处理系统，其特征在于，
    所述PCIe设备还用于确定需要向所述主机请求的待传输数据；
    根据所述待传输数据分别向所述主机请求所述第一数据和所述第二数据。
  4. 根据权利要求2所述的数据处理系统，其特征在于，
    所述主机根据所述第一PCIe链路和所述第二PCIe链路的链路状态将待传输数据拆分为所述第一数据和所述第二数据。
  5. 根据权利要求2或3所述的数据处理系统，其特征在于，
    所述第一数据和所述第二数据的大小相同。
  6. 根据权利要求1-5任一项所述的数据处理系统，其特征在于，
    所述主机用于利用直接内存访问DMA通过所述第一PCIe链路向所述PCIe设备发送所述第一数据以及利用DMA通过所述第二PCIe链路向所述PCIe设备发送所述第二数据。
  7. 根据权利要求2和4-6任一项所述的数据处理系统，其特征在于，
    所述主机还用于：在将所述待传输数据拆分为所述第一数据和所述第二数据之前，确定所述待传输数据的大小超过预设值。
  8. 根据权利要求1-7任一项所述的数据处理系统，其特征在于，所述主机还用于：
    确定所述第一数据和所述第二数据已发送至所述PCIe设备；
    向所述PCIe设备发送同步信号。
  9. 根据权利要求1-8任一项所述数据处理系统，其特征在于，
    所述PCIe设备还用于：当确定所述第一数据写入后，将指针调整至存储空间的末尾，其中，所述存储空间为所述PCIe设备中存储所述第一数据的空间。
  10. 根据权利要求1-9任一项所述的数据处理系统，其特征在于，所述数据处理系统应用于云手机场景，其中，
    所述主机还用于：在通过所述第一PCIe链路向所述PCIe设备发送第一数据之前，接收用户发送的数据处理任务，所述数据处理任务对应的数据包括所述第一数据和所述第二数据。
  11. 根据权利要求1-9任一项所述的数据处理系统，其特征在于，所述数据处理系统应用于人工智能AI场景，其中，
    所述主机还用于，在通过所述第一PCIe链路向所述PCIe设备发送第一数据之前，接收AI任务，所述AI任务对应的数据包括所述第一数据和所述第二数据。
  12. 一种数据处理方法，其特征在于，所述数据处理方法应用于主机，周边设备高速互 联PCIe设备通过第一接口与所述主机建立第一PCIe链路，所述PCIe设备通过第二接口与所述主机建立第二PCIe链路，所述数据处理方法包括：
    通过所述第一PCIe链路向所述PCIe设备发送第一数据；
    通过所述第二PCIe链路向所述PCIe设备发送第二数据，其中，所述第一PCIe链路与所述第二PCIe链路在数据传输时均处于激活态。
  13. 根据权利要求12所述的数据处理方法，其特征在于，所述方法还包括：
    确定需要向所述PCIe设备发送的待传输数据；
    将所述待传输数据拆分为所述第一数据和所述第二数据。
  14. 根据权利要求13所述的数据处理方法，其特征在于，
    所述将所述待传输数据拆分为所述第一数据和第二数据，包括：
    根据所述第一PCIe链路的链路状态和所述第二PCIe链路的链路状态将所述待传输数据拆分为所述第一数据和第二数据。
  15. 根据权利要求12-14任一项所述的数据处理方法，其特征在于，在将所述待传输数据拆分为所述第一数据和第二数据之前，所述方法还包括：
    确定所述待传输数据的大小超过预设值。
  16. 根据权利要求12-15任一项所述的数据处理方法，其特征在于，所述数据处理方法应用于云手机场景，其中，在通过所述第一PCIe链路向所述PCIe设备发送第一数据之前，所述方法还包括：
    接收用户发送的数据处理任务，所述数据处理任务对应的数据包括所述第一数据和所述第二数据。
  17. 一种数据处理装置，其特征在于，周边设备高速互联PCIe设备通过第一接口与所述数据处理装置建立第一PCIe链路，所述PCIe设备通过第二接口与所述数据处理装置建立第二PCIe链路，所述数据处理装置包括：
    传输模块，用于：通过所述第一PCIe链路向所述PCIe设备发送第一数据；
    通过所述第二PCIe链路向所述PCIe设备发送第二数据，其中，所述第一PCIe链路与所述第二PCIe链路在数据传输时均处于激活态。
  18. 根据权利要求17所述的数据处理装置，其特征在于，所述数据传输装置还包括：
    确定模块，用于确定需要向所述PCIe设备发送的待传输数据；
    拆分模块，用于将所述待传输数据拆分为所述第一数据和所述第二数据。
  19. 根据权利要求18所述的数据处理装置，其特征在于，
    所述拆分模块用于：根据所述第一PCIe链路的链路状态和所述第二PCIe链路的链路状态将所述待传输数据拆分为所述第一数据和第二数据。
  20. 根据权利要求17-19任一项所述的数据处理装置，其特征在于，
    所述确定模块还用于：确定所述待传输数据的大小超过预设值。
  21. 根据权利要求17-20任一项所述的数据处理装置，其特征在于，所述数据处理装置应用于云手机场景，其中，
    所述传输模块还用于：接收用户发送的数据处理任务，所述数据处理任务对应的数据包括所述第一数据和所述第二数据。
  22. 一种计算机装置，其特征在于，所述计算机装置包括处理器和存储器，其中，所述存储器用于存储程序代码，所述处理器用于执行所述程序代码以实现如权利要求12-16中任一项所述的数据处理方法。
  23. 一种数据处理方法，其特征在于，所述数据处理方法应用于周边设备高速互联PCIe设备，所述PCIe设备通过第一接口与所述主机建立第一PCIe链路，所述PCIe设备通过第二接口与所述主机建立第二PCIe链路所述数据处理方法包括：
    通过所述第一PCIe链路接收所述主机发送的第一数据；
    通过所述第二PCIe链路接收所述主机发送的第二数据，其中，所述第一PCIe链路与所述第二PCIe链路在数据传输时均处于激活态。
  24. 根据权利要求23所述的数据处理方法，其特征在于，所述方法还包括：
    确定需要向所述主机请求的待传输数据；
    根据所述待传输数据分别向所述主机请求所述第一数据和所述第二数据。
  25. 根据权利要求24所述的数据处理方法，其特征在于，所述根据所述待传输数据分别向所述主机请求所述第一数据和所述第二数据，包括：
    根据所述待传输数据以及所述第一PCIe链路的链路状态和所述第二PCIe链路的链路状态分别向所述主机请求所述第一数据和所述第二数据。
  26. 根据权利要求23-25任一项所述的数据处理方法，其特征在于，所述方法还包括：
    在根据所述待传输数据分别向所述主机请求所述第一数据和所述第二数据之前，
    确定所述待传输数据的大小超过预设值。
  27. 根据权利要求23-26任一项所述的数据处理方法，其特征在于，所述方法还包括：
    当确定所述第一数据写入后，将指针调整至存储空间的末尾，其中，所述存储空间为所述PCIe设备中存储所述第一数据的空间。
  28. 根据权利要求23-27任一项所述的数据处理方法，其特征在于，所述数据处理方法应用于云手机场景，其中，所述第一数据和第二数据对应于用户发送给所述主机的数据处理任务。
  29. 一种数据处理装置，其特征在于，所述数据处理装置通过第一接口与主机建立第一周边设备高速互联PCIe链路，所述数据处理装置通过第二接口与所述主机建立第二PCIe链路，所述数据处理装置包括：
    传输模块，用于：通过所述第一PCIe链路接收所述主机发送的第一数据；
    通过所述第二PCIe链路接收所述主机发送的第二数据，其中，所述第一PCIe链路与所述第二PCIe链路在数据传输时均处于激活态。
  30. 根据权利要求29所述的数据处理装置，其特征在于，所述数据处理装置还包括：
    确定模块，用于：确定需要向所述主机请求的待传输数据；
    请求模块，用于：根据所述待传输数据分别向所述主机请求所述第一数据和所述第二数据。
  31. 根据权利要求30所述的数据处理装置，其特征在于，所述请求模块用于：
    根据所述待传输数据以及所述第一PCIe链路的链路状态和所述第二PCIe链路的链路状态分别向所述主机请求所述第一数据和所述第二数据。
  32. 根据权利要求29-31任一项所述的数据处理装置，其特征在于，所述数据处理装置还包括：
    调整模块，用于：当确定所述第一数据写入后，将指针调整至存储空间的末尾，其中，所述存储空间为所述PCIe设备中存储所述第一数据的空间。
  33. 根据权利要求29-32任一项所述的数据处理装置，其特征在于，所述数据处理装置应用于云手机场景，其中，所述第一数据和第二数据对应于用户发送给主机的数据处理任务。
  34. 一种计算机装置，其特征在于，所述计算机装置包括处理器和存储器，其中，所述存储器用于存储程序代码，所述处理器用于执行所述程序代码以实现如权利要求23-28中任一项所述的数据处理方法。
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