WO2022088709A1 - 一种以太网的编码方法及装置 - Google Patents

一种以太网的编码方法及装置 Download PDF

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Publication number
WO2022088709A1
WO2022088709A1 PCT/CN2021/101722 CN2021101722W WO2022088709A1 WO 2022088709 A1 WO2022088709 A1 WO 2022088709A1 CN 2021101722 W CN2021101722 W CN 2021101722W WO 2022088709 A1 WO2022088709 A1 WO 2022088709A1
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Prior art keywords
fec
encoded data
codeword
fec codeword
pma
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English (en)
French (fr)
Inventor
严增超
马会肖
王中风
林军
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP21884450.4A priority Critical patent/EP4228160B1/en
Publication of WO2022088709A1 publication Critical patent/WO2022088709A1/zh
Priority to US18/309,014 priority patent/US12206433B2/en
Anticipated expiration legal-status Critical
Priority to US18/978,204 priority patent/US20250112645A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/251—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with block coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2735—Interleaver using powers of a primitive element, e.g. Galois field [GF] interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the embodiments of the present application relate to the technical field of encoding, and in particular, to an Ethernet encoding method and device.
  • Ethernet Ethernet
  • the IEEE 802.3 Ethernet protocol has defined 100GE, 200GE, and 400GE interfaces. protocol. Big data transmission has a higher demand for high bandwidth, which puts pressure on the data center architecture and the underlying interconnection. Based on this consideration, the standardization work of the next-generation Ethernet 800G has begun to advance.
  • Ethernet 800G can provide higher transmission bandwidth, it will bring about the problem of increased transmission bit errors. How to provide a coding method with higher error correction performance is an urgent problem to be solved.
  • Embodiments of the present application provide an Ethernet encoding method and device, so as to provide an encoding method with higher error correction performance, so as to adapt to the scenario of larger transmission errors caused by high bandwidth.
  • an Ethernet encoding method is provided, and the execution subject of the method may be a sender, or is referred to as an encoding device.
  • the steps of the method include: the transmitting end uses a first FEC codeword to encode the first information to be encoded to obtain first encoded data, and the first FEC codeword is the Reed Solomon forward error correction code RS-FEC, so The transmitting end uses the second FEC codeword to encode the first encoded data to obtain second encoded data.
  • the code length N and information bit length K of the second FEC codeword conform to the following formula:
  • the M1 is the throughput rate of the first encoded data
  • the M2 is the throughput rate of the second encoded data.
  • Ethernet 800G adopts higher baud rate transmission, and the bit error rate before correction is higher.
  • the error correction performance of Ethernet can be improved and the error correction performance of Ethernet 800G can be satisfied. index.
  • constraints It can meet the bandwidth and transmission performance constraints of optical devices. Under the premise of meeting the requirements of next-generation Ethernet technical indicators, it flexibly supports and is compatible with most interface protocols of 100GE, 200GE, and 400GE in the IEEE 802.3 standard.
  • the transmitting end uses the first FEC codeword to perform FEC encoding on the first to-be-encoded information to obtain the first encoded data, which is implemented in the following manner: the transmitting end uses y first FEC codewords Perform FEC encoding on the first to-be-encoded information to obtain y groups of encoded data, where y is an even number greater than or equal to 2; the transmitting end performs first interleaving on the y groups of encoded data to obtain the first Encoded data; the first interleaving conforms to an interleaving matrix whose row and column numbers are L and P respectively, where L and the P are even numbers greater than or equal to 2, and P is the number of PMA channels of the physical medium access sublayer.
  • the coded data after the coding of the first FEC codeword can be more fully interleaved, and the error correction performance can be improved.
  • the interleaving between the first FEC codeword (RS codeword) and the second FEC codeword (Inner-FEC) is to gather the residual errors after Inner-FEC into one RS symbol (10-bit) , so that the Hamming distance at the symbol level between the RS and the Inner-FEC is minimized, and the error correction efficiency of the RS is improved.
  • row elements in a row of the interleaving matrix respectively correspond to data obtained by polling from the y groups of encoded data.
  • Such an interleaving method enables the symbols of different RSs in the PCS layer to be more randomly and uniformly allocated to the second FEC codeword (Inner-FEC) codeword, which can improve the ability of the system to resist Burst Error.
  • Such interleaving can be compatible with the number of RSs in each PCS layer, without distinguishing the symbols of the RS codewords from the PCS layer data stream, and can reduce the operation of identifying RS symbol boundaries.
  • each of the L rows adopts the same polling rule; or, the polling rules of each consecutive y row in the L rows are different.
  • the transmitting end uses the second FEC codeword to encode the first encoded data, which is implemented in the following manner: the transmitting end transmits the first encoded data through P PMA channels; The first encoded data transmitted by the P PMA channels is encoded.
  • the sending end transmits the second encoded data through P PMA channels, and processes the second encoded data transmitted by the P PMA channels.
  • the transmitting end performs the first interleaving on the y groups of encoded data, which is implemented in the following manner: the transmitting end transmits the y groups of encoded data through P PMA channels; The first interleaving is performed on the y groups of encoded data transmitted by the PMA channel.
  • the corresponding sequence numbers of the P PMA channels are 0 to (P-1), and the P columns of the interleaving matrix are in one-to-one correspondence with the encoded data from the P PMA channels;
  • the row elements whose column sequence numbers are odd numbers in a row respectively correspond to the encoded data of the PMA channels whose sequence numbers are 0 to (P/2-1);
  • the row elements whose column sequence numbers are even numbers in a row of the interleaving matrix respectively correspond to the sequence numbers It is the encoded data of PMA channel of P/2 ⁇ P.
  • Such an interleaving method design does not need to identify the boundaries of symbols, so that the PMA layer does not need to know the format of the PCS layer data frame, and directly performs multiplexing and 10-bit granularity distribution on the data stream received by the PMA layer.
  • the 10-bit (10-bits) granularity just matches the size of the symbol of the second FEC codeword, which improves the system's ability to resist burst errors, and the implementation is simple.
  • the value of P may be an integer power of 2, such as 16 or 32.
  • the K also satisfies the following conditions: is a positive integer, and N1 is the code length of the first FEC codeword.
  • the output of the first FEC codeword ie, the input of the second FEC codeword
  • the output of the first FEC codeword can be divided into integer parts, each of which is K, and each input does not need padding bits.
  • the concatenated coding scheme of the first FEC codeword and the second FEC codeword is simpler and easier to implement, and the complexity is lower.
  • the N and the K also satisfy the following conditions: Reference clock *W, W is a positive integer.
  • the Ethernet coding scheme corresponding to the second FEC codeword can make the implementation of Ethernet clock extraction and synchronization simpler.
  • W is an integer, the PLL can be adjusted on a whole grid point, and the clock extraction and synchronization are simple to implement, so that the phase locking of the PLL can be completed more quickly, and it is easy to implement and has low complexity.
  • W may be 4*reference clock multiplication factor RCM.
  • the structure of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, and K is the information The number of bits included in the bit, where m is the order of the Galois field where the second FEC codeword is located;
  • the second FEC codeword includes any of the following codewords, or includes any of the following codewords Spatially coupled codes constructed for sub-codes, or multi-layer codes constructed from any of the following codewords for sub-codes: Hamming (144, 136, 8), Hamming (180, 170, 10), extended Hamming (180, 170) ,9), double-extended Hamming code DE-Hamming(180,170,8), BCH(360,340,10), double-extended BCH code DE-BCH(360,340,9), DE-BCH(576,544,10), or BCH(594,561 , 11), or Hamming (180, 170, 10).
  • the structure of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, and K is the information The number of bits included in the bit, and the m is the order of the Galois field where the FEC codeword is located;
  • the second FEC codeword includes any of the following codewords, or includes any of the following codewords as subcodes
  • the transmitting end performs one or more of the following processing on the second encoded data: transmission through P PMA channels, second interleaving, data modulation, or photoelectric conversion; the P is greater than or an even number equal to 2; the sending end sends the processed data to the receiving device.
  • N x*n
  • K x*k
  • the outer code of the concatenated code follows the original standard RS codeword, and the inner code of the concatenated code uses the original standard RS codeword.
  • the code adopts the second FEC codeword, that is, the Inner-FEC codeword.
  • This encoding method is compatible with 100GE, 200GE, and 400GE Ethernet RS (544, 514, 10) encoding, and the Inner-FEC code is cascaded through RS (544, 514, 10).
  • the encoding method of the word increases the overhead (overhead, OH) of the entire FEC encoding.
  • the OH of the system link FEC code is increased, which improves the error correction performance of the system, which not only meets the performance indicators of the next high-speed Ethernet, but also meets the delay requirements of the next-generation Ethernet with low implementation cost.
  • the encoder part of this Inner-FEC codeword can be placed at the PCS layer or at the PMA layer.
  • the encoder part of the Inner-FEC codeword is placed in the PMA layer, the RS encoding of the PCS layer is decoupled from the Inner-FEC encoding of the PMA layer, and the PMA can be completed in the presence of errors inherent at the C2M optical interface Inner-FEC encoding of the layer.
  • the encoder components of the Inner-FEC codeword are placed concatenated at the PCS layer, the concatenated coding scheme can also be completed.
  • a second aspect provides an Ethernet encoding device, the device having the function of implementing the method described in the first aspect and any possible design of the first aspect.
  • the functions can be implemented by hardware, or can be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the apparatus may include an acquisition module and a processing module.
  • an obtaining module configured to obtain the first information to be encoded
  • a processing module configured to encode the first information to be encoded by using the first forward error correction code (FEC) codeword to obtain first encoded data
  • the first A forward error correction code FEC codeword is Reed Solomon forward error correction code RS-FEC
  • the processing module is further configured to use the second FEC codeword to encode the first encoded data to obtain a second encoded data Data
  • the code length N and the information bit length K of the second FEC codeword conform to the following formula:
  • the M1 is the throughput rate of the first encoded data
  • the M2 is the throughput rate of the second encoded data.
  • the processing module when using the first FEC codeword to perform FEC encoding on the first information to be encoded to obtain the first encoded data, is configured to: use y first FEC codewords to perform the FEC encoding on the first FEC codeword. 1. Perform FEC encoding on the information to be encoded to obtain y groups of encoded data, where y is an even number greater than or equal to 2; perform first interleaving on the y groups of encoded data to obtain the first encoded data; the first interleaving It conforms to the interleaving matrix whose numbers of rows and columns are L and P respectively, where L and P are even numbers greater than or equal to 2, and P is the number of PMA channels of the physical medium access sublayer.
  • row elements in a row of the interleaving matrix respectively correspond to data obtained by polling from the y groups of encoded data.
  • each of the L rows adopts the same polling rule; or, the polling rules of each consecutive y row in the L rows are different.
  • the processing module when using the second FEC codeword to encode the first encoded data, is configured to: transmit the first encoded data through P PMA channels; The first encoded data transmitted by the PMA channel is encoded.
  • the processing module is further configured to: transmit the second encoded data through P PMA channels, and process the second encoded data transmitted by the P PMA channels.
  • the processing module when performing the first interleaving on the y groups of encoded data, is configured to: transmit the y groups of encoded data through P PMA channels; The y groups of encoded data are subjected to the first interleaving.
  • the corresponding sequence numbers of the P PMA channels are 0 to (P-1), and the P columns of the interleaving matrix are in one-to-one correspondence with the encoded data from the P PMA channels;
  • the row elements whose column sequence numbers are odd numbers in a row respectively correspond to the encoded data of the PMA channels whose sequence numbers are 0 to (P/2-1);
  • the row elements whose column sequence numbers are even numbers in a row of the interleaving matrix respectively correspond to the sequence numbers It is the encoded data of PMA channel of P/2 ⁇ P.
  • the value of P includes 16 or 32.
  • the K also satisfies the following conditions: is a positive integer, and N1 is the code length of the first FEC codeword.
  • the N and the K also satisfy the following conditions: Reference clock *W, W is a positive integer.
  • W 4*reference clock multiplication factor RCM.
  • the structure of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, and K is the information The number of bits included in the bit, where m is the order of the Galois field where the second FEC codeword is located;
  • the second FEC codeword includes any of the following codewords, or includes any of the following codewords Spatially coupled codes constructed for sub-codes, or multi-layer codes constructed from any of the following codewords for sub-codes: Hamming (144, 136, 8), Hamming (180, 170, 10), extended Hamming (180, 170) ,9), double-extended Hamming code DE-Hamming(180,170,8), BCH(360,340,10), double-extended BCH code DE-BCH(360,340,9), DE-BCH(576,544,10), or BCH(594,561) , 11), or Hamming (180, 170, 10).
  • the structure of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, and K is the information The number of bits included in the bit, and the m is the order of the Galois field where the FEC codeword is located;
  • the second FEC codeword includes any of the following codewords, or includes any of the following codewords as subcodes
  • the processing module is further configured to: perform one or more of the following processing on the second encoded data: transmission through P PMA channels, second interleaving, data modulation, or photoelectric conversion;
  • the P is an even number greater than or equal to 2;
  • the apparatus further includes a communication module for sending the processed data to the receiving device.
  • N x*n
  • K x*k
  • a third aspect provides an Ethernet encoding device, the device having the function of implementing the method described in the first aspect and any possible design of the first aspect.
  • the functions can be implemented by hardware, or can be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the Ethernet encoding device when part or all of the functions are implemented by hardware, includes: an input interface circuit for acquiring the first information to be encoded; a logic circuit for acquiring the first information to be encoded based on the acquired The first information to be encoded performs the actions described in the first aspect and any possible design of the first aspect, and outputs the interface circuit for outputting the second encoded data.
  • the Ethernet encoding device may be a chip or an integrated circuit.
  • the Ethernet encoding device when part or all of the functions are implemented by software, includes: a memory for storing programs or instructions; a processor for executing all the programs stored in the memory.
  • the program or instruction when the program or instruction is executed, the method described in the first aspect and any possible design of the first aspect is implemented.
  • the above-mentioned memory may be a physically independent unit, or may be integrated with the processor.
  • the Ethernet encoding device when part or all of the functions are implemented by software, includes a processor.
  • a memory for storing a program is located outside the encoding device, and a processor is connected to the memory through a circuit/wire for reading and executing the program stored in the memory.
  • a fourth aspect provides a computer-readable storage medium storing computer-readable instructions, which, when the computer-readable instructions are executed on a computer, cause any one of the possible designs of the first aspect and the first aspect to be executed. A described method is performed.
  • embodiments of the present application provide a computer program product containing instructions, which, when executed on a computer, enable the method described in the first aspect and any possible design of the first aspect to be executed.
  • an embodiment of the present application provides a chip system, where the chip system includes a processor and may also include a memory, for implementing the method described in the first aspect or any possible design of the first aspect .
  • the chip system can be composed of chips, and can also include chips and other discrete devices.
  • FIG. 1a is a schematic structural diagram of a communication system in an embodiment of the application.
  • FIG. 1b is a schematic diagram of an Ethernet architecture in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of RS-FEC encoding of 100GE Ethernet in the embodiment of the application;
  • FIG. 3 is a schematic diagram of RS-FEC encoding of 200GE Ethernet in an embodiment of the application
  • FIG. 4 is a schematic diagram of RS-FEC encoding of 400GE Ethernet in an embodiment of the application
  • FIG. 5 is one of the schematic flowcharts of an Ethernet encoding method in an embodiment of the present application.
  • 6a is a schematic diagram of an Ethernet layer architecture in an embodiment of the present application.
  • 6b is a second schematic diagram of an Ethernet layer architecture in an embodiment of the present application.
  • FIG. 7a is a schematic diagram of a processing process of a data stream corresponding to architecture 1 in an embodiment of the present application
  • FIG. 7b is a schematic diagram of a processing process of a data stream corresponding to architecture 2 in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an 800G Ethernet layer architecture in an embodiment of the application.
  • FIG. 9 is one of the schematic flowcharts of data processing in an embodiment of the application.
  • FIG. 10 is the second schematic flowchart of data processing in the embodiment of the application.
  • FIG. 12 is the second schematic flowchart of the Ethernet encoding method in the embodiment of the application.
  • FIG. 13 is one of the schematic structural diagrams of the Ethernet encoding apparatus in the embodiment of the application.
  • FIG. 14 is the second schematic diagram of the structure of the Ethernet encoding apparatus in the embodiment of the application.
  • FIG. 15 is a third schematic structural diagram of an Ethernet encoding apparatus in an embodiment of the present application.
  • Embodiments of the present application provide an Ethernet encoding method and device, so as to improve the error correction performance of Ethernet encoding.
  • the method and the device are based on the same technical concept. Since the principles of the method and the device to solve the problem are similar, the implementation of the device and the method can be referred to each other, and the repetition will not be repeated.
  • the communication method provided by the embodiments of the present application may be applied to Ethernet, and may also be applied to other networks using gate forward error correction (forward error correction, FEC) encoding.
  • FEC forward error correction
  • the embodiments of the present application may be applicable to application scenarios of large traffic and short delay, such as short-distance interconnection of data centers, cloud storage, cloud computing, and fifth-generation (5th generation, 5G) base station backbone networks.
  • FIG. 1a is a schematic structural diagram of a communication system 100 to which an embodiment of the present application is applied.
  • the communication system includes a transmitter 101 and a receiver 102 .
  • the transmitting end may also be referred to as a transmitting device, and the receiving end may also be referred to as a receiving device.
  • the sending end may also be called a sending device, and the receiving end may also be called a receiving device.
  • the embodiments of the present application are described by taking the sending end and the receiving end as examples. When the embodiments of the present application are applied to the Ethernet, both the sending end and the receiving end support the IEEE802.3 Ethernet protocol.
  • FIG. 1b it is a schematic structural diagram of an Ethernet to which the embodiments of the present application are applied.
  • switches can be connected, and switches and servers can also be connected. It can be understood that FIG. 1 b is a schematic diagram, and an actual Ethernet network may further include more or less switches and more or less servers.
  • the connection mode between switches and switches, and the connection mode between switches and servers are an indication.
  • the sender 101 is a switch, and the receiver 102 is a switch; the sender 101 is a switch, and the receiver 102 is a server; the sender 101 is a server, and the receiver 102 is a switch.
  • the methods provided in the embodiments of the present application may be applicable to multiple fields, for example, augmented reality/virtual reality (AR/VR), artificial intelligence (artificial intelligence, AI), 5G applications, or cloud applications, etc.
  • AR/VR augmented reality/virtual reality
  • AI artificial intelligence
  • 5G applications or cloud applications, etc.
  • Applications in more and more fields will generate more and more throughput, and the explosive growth of throughput requires higher bandwidth. Therefore, the standard work of Ethernet 800G has begun to advance. The growth of Ethernet transmission bandwidth will inevitably bring about an increase in transmission errors.
  • the embodiment of the present application provides an Ethernet encoding method, so as to adapt to a higher Ethernet transmission bandwidth.
  • the coding scheme adopts Reed-Solomon (RS) (544, 514, 10) codewords.
  • Figure 2 shows a schematic flowchart of the coding scheme of the 100GE KP4 Ethernet. Data from medium access control (MAC) and higher-layer clients will go through a reconciliation sublayer, which translates data from MAC and higher-layer clients through 100Gbits per second.
  • MAC medium access control
  • reconciliation sublayer which translates data from MAC and higher-layer clients through 100Gbits per second.
  • the (bit per second, bps, b/s) medium independent interface (100Gb/s media independent interface, CGMII) interface is transmitted to the physical coding sublayer (physical coding sublayer, PCS) layer of 100GBASE-R.
  • the PCS layer performs operations such as transcoding, scrambling, and AM insertion into the data, and then sends it into a Reed-Solomon forward error correction (RS-FEC) codeword for encoding.
  • RS-FEC Reed-Solomon forward error correction
  • the RS-FEC encoding of 100GE Ethernet uses an RS (544, 514, 10) codeword.
  • the encoded codeword will enter the physical medium attachment sublayer (PMA) layer for multiplexing (Mux) and other operations, and the manipulated data stream passes through a four-lane attachment unit interface (four-lane attachment unit interface). interface, CAUI-4)
  • the chip-to-module (C2M) interface is passed to the PMA of the next layer.
  • the PMD modulates and photoelectrically converts the data stream.
  • a medium dependent interface (MDI) interface transmits the modulated and photoelectrically converted optical signal to a receiving end through a medium (medium) such as an optical fiber.
  • the coding scheme of 200GE and 400GE Ethernet also adopts RS (544, 514, 10) code words.
  • FIG. 3 A schematic flowchart of the coding scheme of the 200GE Ethernet is shown in FIG. 3 .
  • the data from the client of the MAC and higher layers will go through the coordination sublayer, and the coordination sublayer will translate the data from the clients of the MAC and higher layers, and send it to the PCS layer of 200GBASE-R through the 200GMII interface.
  • the PCS layer performs operations such as transcoding, scrambling, and inserting AM into the data, and sends it to the RS-FEC module for encoding.
  • the RS-FEC encoding of 200GE Ethernet adopts two RS (544, 514, 10) code words, and the data stream from the PCS layer is sent to the two RS code words by means of 10-bit (bit) polling and distribution.
  • the codewords encoded by the two RS codewords will enter the PMA layer to perform operations such as Mux, and the operated data stream will be transmitted to the next through a 200G four-lane attachment unit interface (CAUI-4) C2M interface.
  • CAUI-4 200G four-lane attachment unit interface
  • One layer of PMA after the data stream passes through the PMA, the PMD modulates and converts the data stream to photoelectric.
  • the MDI interface transmits the modulated and photoelectrically converted optical signals to the receiving end through a medium such as an optical fiber.
  • FIG. 4 A schematic flowchart of the coding scheme of 400GE Ethernet is shown in FIG. 4 .
  • the data from the client of the MAC and higher layers will go through the coordination sublayer, and the coordination sublayer will translate the data from the clients of the MAC and higher layers and send it to the PCS layer of 400GBASE-R through the 400GMII interface.
  • the PCS layer performs operations such as transcoding, scrambling, and inserting AM into the data, and sends it to the RS-FEC module for encoding.
  • the RS-FEC encoding of 400GE Ethernet uses two RS (544, 514, 10) code words, and the data stream from the PCS layer is sent to the two RS code words by means of 10-bit (bit) polling and distribution.
  • the codewords encoded by the two RS codewords are distributed through Mux and 10bit symbols, and then enter the PMA layer.
  • the data stream output by the PMA layer is transmitted to the next layer of PMA through a 400GAUI-4C2M interface.
  • PMD modulates and photoelectrically converts the data stream.
  • the MDI interface transmits the modulated and photoelectrically converted optical signals to the receiving end through a medium such as an optical fiber.
  • the coding schemes of 100GE, 200GE, and 400GE Ethernet all use RS coding at the PCS layer.
  • the RS-coded data flow runs through the end-to-end, and errors caused by noise at the optical link and electrical layer interface are corrected by the RS code.
  • the single-wavelength rate increases from 100Gbps in 400GE to 200Gbps. Due to device constraints, the bit error rate before correction increases. Therefore, an Ethernet encoding method with stronger error correction capability is required, which needs to be compatible with the original solution. The most compatible docking of the data flow.
  • an embodiment of the present application provides an Ethernet encoding method.
  • the specific process of the Ethernet encoding method provided by the embodiment of the present application is as follows.
  • the execution body of the method may be a sending device, a sending end or a sending apparatus.
  • the transmitting end uses the first codeword to encode the first information to be encoded to obtain first encoded data.
  • the first codeword may be a forward error correction code (forward error correction, FEC) codeword, which is denoted as the first FEC codeword.
  • FEC forward error correction
  • the first codeword may be an RS-FEC codeword, and may also be referred to as an RS codeword, or an RS code.
  • the transmitting end uses the second codeword to encode the first encoded data to obtain the second encoded data.
  • the second codeword may be an FEC codeword, denoted as the second FEC codeword.
  • the embodiment of the present application adopts two FEC codeword concatenated coding schemes, which can support the throughput requirements of Ethernet 800G or even higher.
  • Ethernet 800G adopts higher baud rate transmission, and the bit error rate before correction is higher.
  • the error correction performance of Ethernet can be improved and the error correction performance of Ethernet 800G can be satisfied. index.
  • the sending device may also process the second encoded data, and send the processed data to the receiving device.
  • the receiving device receives the processed data.
  • the processing procedure may include: transmission through P PMA channels, second interleaving, data modulation, or photoelectric conversion.
  • the processing procedure may also include some of the above procedures.
  • P is an even number greater than or equal to 2, or P is an integer power of 2, for example, P can be 4, 8, 16, or 32.
  • the structure of the first FEC codeword that is, the RS codeword is (544, 514, 10), where 514 is the information symbol bit length K1 of the first FEC codeword, and 544 is the length of the first FEC codeword.
  • K1 is 514 symbols
  • N1 is 544 symbols
  • the architecture of the Ethernet layer can have the following examples.
  • the first FEC codeword is an RS-FEC codeword
  • the second FEC codeword may be recorded as an Inner-FEC codeword.
  • the architecture of the Ethernet layer may include a MAC layer, a PCS layer, a PMA layer and a PMD layer.
  • the MAC layer and the PCS layer can be considered to be located on the device side
  • the PMA layer and the PMD layer can be considered to be located on the module side.
  • the device refers to the device at the sending end, for example, a switch or a server.
  • a module refers to an optical module used for optical communication.
  • the encoder component of the first FEC codeword is used to complete the encoding of the first FEC codeword
  • the encoder component of the second FEC codeword is used to complete the encoding of the second FEC codeword.
  • the encoder component of the first FEC codeword may also be denoted as the encoder of the first FEC codeword or the encoding module of the first FEC or the RS-FEC encoder or the RS-FEC encoding module.
  • the encoder component of the second FEC codeword may also be denoted as the encoder of the second FEC codeword, the encoding module of the second FEC, the Inner-FEC encoder, and the Inner-FEC encoding module.
  • the encoder component of the second FEC codeword may also be called a Hamming code encoder or a Hamming code encoding module.
  • the second FEC codeword is a BCH code
  • the second FEC codeword is a BCH code.
  • the encoder component of the FEC codeword may also be referred to as either a BCH code encoder, or a BCH code encoding module.
  • BCH codes are (Bose, Ray-Chaudhuri and Hocquenghem) codes.
  • the encoder component of the second FEC codeword may be located at the PCS layer.
  • the encoder component of the Inner-FEC codeword is added to the PCS layer on the device side.
  • the data stream undergoes 64B/66B encoding at the MAC layer and PCS layer, 256B/257B transcoding, scrambling, AM insertion, and 10-bit granularity polling and distribution, and then RS-FEC encoding is performed.
  • 64B/66B encoding It may refer to expanding a 64-bit data block into a 66-bit information block.
  • 256B/257B transcoding may refer to: sorting and splitting 66-bit data blocks, taking 25G services as an example, splitting the data to be sent into multiple 66-bit data blocks, and each 4 66-bit data blocks It is divided into a data block group (data segment), and each data block group is a data block of 257 bits.
  • the RS-FEC encoded data stream enters the encoder part of the Inner-FEC codeword. After the data stream is encoded in the encoder part of the Inner-FEC codeword, it enters the module side through the AUI C2M interface. After completing the operation of PMA and PMD on the module side, use the MDI interface to send the data stream on the module side to the medium layer to complete the data stream transmission.
  • the encoder component of the second FEC codeword may be located at the PMA layer.
  • the data stream undergoes 64B/66B encoding at the MAC layer and PCS layer in sequence, 256B/257B transcoding, scrambling, AM insertion, and 10-bit granularity polling and distribution, and then RS-FEC encoding is performed.
  • 64B/66B encoding and 256B/257B transcoding please refer to the description of Architecture 1.
  • the RS-FEC encoded data stream enters the module side through the AUI C2M interface.
  • the data stream on the module side enters the encoder part of the Inner-FEC codeword.
  • the module-side data stream is sent to the medium using the MDI interface.
  • the layer completes the data stream transmission.
  • the encoder component of the second FEC codeword may also be located in other parts of the Ethernet, and the above-mentioned architectures 1 and 2 are only illustrative examples.
  • the following describes the processing flow of the data stream based on the first and second architectures.
  • the encoder component of the second FEC codeword can be located at the PCS layer, as shown in Fig. 7a, and the processing process of the data stream is as follows.
  • the data output from the MAC layer will pass through the PCS layer, and the encoding of the second FEC codeword, that is, Inner-FEC encoding, will be completed in the PCS layer.
  • the two PCS layer data streams encoded by Inner-FEC are independently distributed to the PMA layer, and then combined into an 800G data stream at the PMA layer.
  • the 800G data stream is sent to the receiver through the communication medium.
  • the processing of the data stream is as follows.
  • the processing procedure of the data stream includes the processing procedure of the data stream of the sender from top to bottom, and the processing procedure of the data stream of the receiver from the bottom to the top.
  • the data stream of the sender is sent to the PCS layer from the MII interface, and the PCS layer is compatible with 100GE, 200GE, and 400GE standard protocols.
  • Encoding and rate matching (encode and rate matching), 256B/257B transcoding (transcode), scramble (scramble), alignment insertion (alignment insertion), distribution before FEC (Pre-FEC distribution) , RS Encode (RS Encode), distribution and interleave (distribution and interleave), PMA layer processing, PMD layer after 10 main operation steps, sent to the receiving end through the communication medium.
  • Encode and rate matching is a 64B/66B module.
  • the TXD ⁇ 63:0> data block translated by the MII interface is encoded in 64B/66B, and the throughput rate is adjusted according to the TXC ⁇ 7:0> of the MII interface.
  • 256B/257B Transcode is 256-bit to 257-bit transcoding. Scramble is a scrambling operation.
  • the alignment insertion is the alignment mark insertion operation.
  • Pre-FEC distribution is a 10-bit polling distribution operation before RS encoding.
  • RS Encode is an RS(544,514,10) encoding operation.
  • distribution and interleave is the symbol distribution and symbol interleaving of 10-bit granularity after RS encoding.
  • the data stream after symbol distribution and symbol interleaving is subjected to the second FEC codeword encoding, that is, the Inner-FEC Encode step operation. After completing the Inner-FEC Encode operation, let the data flow through the PMA and PMD operations.
  • the receiving end receives the data stream from the communication medium, and passes through PMD, PMA, Alignment lock and lane deskew, Inner-FEC Decode, Lane reorder and de-interleave, RS Decode, Post-FEC interleave, Alignment removal, Descramble, The 11 main steps of Reverse Transcode, Decode and rate matching.
  • the 11 steps that the receiver passes through are the solution operations of the corresponding operation steps of the sender.
  • Inner-FEC Decode is the decoding operation of Inner-FEC.
  • the 11 steps that the receiver passes through are the solution operations of the corresponding operation steps of the sender.
  • Inner-FEC Decode is the decoding operation of Inner-FEC.
  • Alignment lock and lane deskew are the alignment mark lock and lane alignment operations.
  • Lane reorder and de-interleave are channel rearrangement and de-interleave operations.
  • RS Decode is the decoding operation of RS(544,514,10).
  • Post-FEC interleave is the inverse operation of Pre-FEC distribution after RS decoding.
  • Alignment remove is the operation of removing the alignment mark added by the coding end.
  • Descramble is a descrambling operation.
  • Reverse Transcode is the inverse operation of 256B/257B transcoding, which inversely converts 257 bits to 256 bits.
  • Decode and rate matching is the inverse operation of 64B/66B and the throughput rate matching operation.
  • the encoder component of the second FEC codeword may be located at the PMA layer, as shown in Fig. 7b, and the processing process of the data stream is as follows.
  • the processing procedure of the data stream includes the processing procedure of the data stream of the sender from top to bottom, and the processing procedure of the data stream of the receiver from the bottom to the top.
  • the data stream of the sender is sent to the PCS layer from the MII interface, and the PCS layer is compatible with 100GE, 200GE, and 400GE standard protocols.
  • Encoding and rate matching (encode and rate matching), 256B/257B transcoding (transcode), scramble (scramble), alignment insertion (alignment insertion), distribution before FEC (Pre-FEC distribution) , RS encoding (RS Encode), distribution and interleaving (distribution and interleave), PMA layer processing, second FEC codeword encoding (Inner-FEC Encode), PMD layer processing After these 10 steps of operation, it is sent to the receiver through the communication medium end.
  • Encode and rate matching is a 64B/66B module.
  • the TXD ⁇ 63:0> data block translated by the MII interface is encoded in 64B/66B, and the throughput rate is adjusted according to the TXC ⁇ 7:0> of the MII interface.
  • 256B/257B Transcode is 256-bit to 257-bit transcoding. Scramble is a scrambling operation. Alignment insertion is the alignment mark insertion operation.
  • Pre-FEC distribution is a 10-bit polling distribution operation before RS encoding.
  • RS Encode is an RS(544,514,10) encoding operation.
  • Distribution and Interleave is the symbol distribution and symbol interleaving of 10-bit granularity after RS encoding.
  • PMA is the next layer after the data stream has been operated through the PCS layer. The data stream will perform the encoding operation of the second FEC codeword at the PMA layer, that is, the Inner-FEC Encode operation.
  • the receiving end receives the data stream from the communication medium, and passes through PMD, Inner-FEC Decode, PMA, Alignment lock and lane deskew, Lane reorder and de-interleave, RS Decode, Post-FEC interleave, Alignment removal, Descramble, The 11 main steps of Reverse Transcode, Decode and rate matching.
  • the 11 steps that the receiver passes through are the solution operations of the corresponding operation steps of the sender.
  • Inner-FEC Decode is the decoding operation of Inner-FEC.
  • Alignment lock and lane deskew are the alignment mark lock and lane alignment operations.
  • Lane reorder and de-interleave are channel rearrangement and de-interleave operations.
  • RS Decode is the decoding operation of RS(544,514,10).
  • Post-FEC interleave is the inverse operation of Pre-FEC distribution after RS decoding.
  • Alignment remove is the operation of removing the alignment mark added by the coding end.
  • Descramble is a descrambling operation.
  • Reverse Transcode is the inverse operation of 256B/257B transcoding, which inversely converts 257 bits to 256 bits.
  • Decode and rate matching is the inverse operation of 64B/66B and the throughput rate matching operation.
  • the outer code of the concatenated code follows the original standard RS codeword, and the level
  • the inner code of the concatenated code adopts the second FEC codeword, that is, the Inner-FEC codeword.
  • This encoding method is compatible with 100GE, 200GE, and 400GE Ethernet RS (544, 514, 10) encoding, and cascades Inner through RS (544, 514, 10).
  • the encoding method of the codeword of FEC increases the overhead (overhead, OH) of the entire FEC encoding.
  • the OH of the system link FEC code is increased, which improves the error correction performance of the system, which not only meets the performance indicators of the next high-speed Ethernet, but also meets the delay requirements of the next-generation Ethernet with low implementation cost.
  • the encoder part of this Inner-FEC codeword can be placed at the PCS layer or at the PMA layer.
  • the encoder part of the Inner-FEC codeword is placed in the PMA layer, the RS encoding of the PCS layer is decoupled from the Inner-FEC encoding of the PMA layer, and the PMA can be completed in the presence of errors inherent at the C2M optical interface Inner-FEC encoding of the layer.
  • the encoder components of the Inner-FEC codeword are placed concatenated at the PCS layer, the concatenated coding scheme can also be completed.
  • the second FEC codeword needs to meet some constraints. In addition, it aims to flexibly support and be compatible with most interface protocols of 100GE, 200GE, and 400GE in the IEEE 802.3 standard based on the premise of meeting the requirements of the next-generation Ethernet technical indicators.
  • the second FEC code word also needs to meet some constraints.
  • the code length of the second FEC codeword is represented by N
  • the information bit length of the second FEC codeword is represented by K.
  • N x*n
  • x is the common factor of N and K.
  • the code length of the first FEC codeword is represented by N1, and the information bit length of the first FEC codeword is represented by K1.
  • the length of the FEC codeword may be relatively long, and when the construction parameters of the codeword are limited, more fine-grained parameters for the construction of the codeword may be limited.
  • N x*n
  • K x*k
  • n and k can be defined.
  • the number of RS codewords used by the PCS layer of the Ethernet for RS-FEC encoding is represented by y.
  • the RS-FEC encoding of the 800G Ethernet can adopt 4 RSs.
  • adopting RS means adopting the encoder component of RS.
  • the structure of the first FEC codeword that is, the RS codeword is (544, 514, 10), where 514 is the information bit length K1 of the first FEC codeword, and 544 is the code length N1 of the first FEC codeword.
  • K1 is 514 symbols
  • N1 is 544 symbols
  • the second FEC codeword satisfies any one or more of the following conditions 1 to 3.
  • Condition 1 The code length N and information bit length K of the second FEC codeword conform to the following formula (1).
  • M1 is the throughput rate of the first encoded data
  • M2 is the throughput rate (throughput) of the second encoded data
  • Equation (1) can have various deformation formulas, for example, For another example,
  • K is the information bit length
  • N is the code length. It can be considered that K is the input before encoding, and N is the output after encoding.
  • M1 is the throughput rate of the first encoded data
  • the throughput rate of the first encoded data is used as the input of the second FEC codeword, and the output of the second FEC codeword cannot exceed M2.
  • M2 is one or more factors based on the limitation of transceiver rate, optical device bandwidth and transmission performance in the Ethernet, and the determined value may be regarded as the throughput rate of the second encoded data. M2 can also be considered as the output data throughput rate of the PMD layer.
  • the unit of M1 and M2 can be Gbps.
  • Ethernet is based on the 156.25MHz reference clock, and uses PLL for clock extraction and clock recovery.
  • the phase-locked synchronization process of the PLL is adjusted based on the reference clock multiplier (RCM) as the grid point.
  • RCM reference clock multiplier
  • the data stream of the MAC layer will be transmitted to the PCS layer through the PCS physical channel with a bit width of 64 bits.
  • the data stream first completes 64B/66B encoding at the PCS layer, and then completes 256B/257B transcoding on the basis of four 64B/66B encodings.
  • the 20 transcoded data blocks are subjected to RS (544,514,10) FEC encoding .
  • the data throughput rate of every 100 Gbps input from the MAC layer to the PCS layer, after 64B/66B encoding, 256B/257B transcoding and RS encoding are completed in the PCS layer, the single lane output data throughput rate in the PCS layer is 106.25Gbps. Limited by the bandwidth and transmission performance of optical devices, the output data throughput rate of the PMD layer cannot exceed M2Gbps. Optionally, M2 114Gbps.
  • K also satisfies the following conditions: is a positive integer, and N1 is the code length of the first FEC codeword.
  • N1 is the code length of the first FEC codeword, which can be regarded as the output of the first FEC codeword.
  • the second FEC codeword is input and encoded in the unit of K. Therefore, by setting N2 to be a positive integer multiple of K, the output of the first FEC codeword (that is, the input of the second FEC codeword) can be equally divided into integers Parts, each of which is K, and no padding bits are required for each part of the input.
  • the concatenated coding scheme of the first FEC codeword and the second FEC codeword is simpler and easier to implement, and the complexity is lower.
  • condition 2 can be transformed into is a positive integer.
  • the number of RS codewords used by the PCS layer of the Ethernet for RS-FEC encoding is y, where the output codeword code length of one RS codeword is N1, and the output codeword code length of y RS codewords is y* N1.
  • the output of the y RS codewords is the input of the second FEC codeword, that is to say, the input of the second FEC codeword is y*N1. If the input of the second FEC codeword needs to be divisible by K, In fact, it is necessary to satisfy that y*N1 can be divisible by K, that is, is a positive integer, or, is a positive integer.
  • y is set to be 1, then is a positive integer.
  • the value of y is 1, that is, when an RS codeword is used for RS-FEC encoding at the PCS layer of the Ethernet, if the output of the RS codeword (that is, the input of the second FEC codeword) can be divisible by K , then when the value of y is 2 or any other integer value, the outputs of the y RS codewords (that is, the input of the second FEC codeword) are all divisible by K. Therefore, in the embodiment of the present application, the value of y is set to 1, and the second constraint condition is obtained is a positive integer.
  • the value of y is set to 1, indicating that the PCS layer divides the data blocks with the granularity of 1 RS (544, 514, 10).
  • the encoder component of the second FEC codeword may be located at the PCS layer, and the second FEC codeword also needs to satisfy the third condition.
  • each 100Gbps data stream will be serial-to-parallel conversion with 156.25MHz RCM as grid adjustment, and the 4-channel data stream will be merged into one channel, which will be serially transmitted in one transmission channel.
  • the Ethernet coding scheme corresponding to the second FEC codeword satisfying the third condition can make the implementation of Ethernet clock extraction and synchronization simpler.
  • W is an integer
  • the PLL can be adjusted on a whole grid point, so that the phase locking of the PLL can be completed more quickly, and it is easy to implement and has low complexity.
  • the second FEC codeword when the encoder component of the second FEC codeword is placed in the PMA layer, the second FEC codeword may satisfy at least one of the first condition and the second condition, and does not need to satisfy the third condition.
  • the second FEC codeword when the encoder component of the second FEC codeword is placed in the PCS layer, the second FEC codeword may satisfy at least one of condition one, condition two, and condition three.
  • the embodiment of the present application further sets condition four for the second FEC codeword.
  • Condition four or or some other variant, for example, which is or,
  • the structure of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, K is the number of bits included in the information bits, and m is the FEC The order of the Galois Field where the codeword is located.
  • the second FEC codeword includes any one of the following codewords, or includes any of the following codewords as subcodes, and includes a spatially coupled code constructed as a subcode, or includes any of the following codewords as a subcode.
  • coding, MLC :
  • OH can be determined on the basis of the determination of the codeword construction parameters N, K, and m.
  • Code word (1) to code word (8) meet condition 1, condition 2, condition 3 and condition 4.
  • the second FEC codeword may also include any one of the following codewords, or include any one of the following codewords that are constructed as subcodes, or include any of the following codewords that are constructed as subcodes.
  • the multi-layer code :
  • Code word 1) to code word 16) meet the first and second conditions.
  • the above codewords are only examples, and there may be more codewords that meet the conditions in practical applications.
  • the error correction performance is increased by increasing the overhead (overhead, OH) of the system FEC coding. If the Ethernet continues to evolve to 1.6 Tbps, the concatenated coding scheme provided in the embodiment of the present application and the above constraints of the inner code under the concatenated scheme still apply.
  • Example 1 As shown in Figure 8, the architecture of two 400GE Ethernet layers can be spliced in parallel to form an 800G Ethernet layer. It can be known from the 400GE Ethernet layer architecture shown in FIG. 4 that the RS-FEC encoding of the 400GE Ethernet PCS layer uses 2 RS codewords, thus, the RS-FEC encoding of the 800GE Ethernet PCS layer uses 4 RS codewords.
  • Example 2 The architecture of four 200GE Ethernet layers can also be spliced into an 800G Ethernet layer in parallel. From the 200GE Ethernet layer architecture shown in Figure 3, it can be known that the RS-FEC encoding of the 200GE Ethernet PCS layer adopts 2 RS codewords, and the RS-FEC encoding of the 800GE Ethernet PCS layer adopts 8 RS codewords.
  • Example 3 The architecture of eight 100GE Ethernet layers can also be spliced into an 800G Ethernet layer in parallel. It can be known from the 100GE Ethernet layer architecture shown in FIG. 2 that the RS-FEC encoding of the 100GE Ethernet PCS layer uses one RS codeword, so that the RS-FEC encoding of the 800GE Ethernet PCS layer uses eight RS codewords.
  • Example 4 The architecture of four 100GE Ethernet layers and the architecture of one 400GE Ethernet layer can also be spliced side by side to form an 800G Ethernet layer. From the 100GE Ethernet layer architecture shown in Figure 2 and the 400GE Ethernet layer architecture shown in Figure 4, it can be known that the RS-FEC encoding of the 100GE Ethernet PCS layer uses one RS codeword, and the RS-FEC encoding of the 400GE Ethernet PCS layer uses one RS codeword. The encoding adopts 2 RS codewords, thus, the RS-FEC encoding of the PCS layer of the 800GE Ethernet adopts 6 RS codewords.
  • Example 5 The architecture of two 200GE Ethernet layers and the architecture of one 400GE Ethernet layer can also be spliced side by side to form an 800G Ethernet layer. From the 200GE Ethernet layer architecture shown in Figure 3 and the 400GE Ethernet layer architecture shown in Figure 4, it can be known that the RS-FEC encoding of the 200GE Ethernet PCS layer uses two RS codewords, and the RS-FEC encoding of the 400GE Ethernet PCS layer uses two RS codewords. The encoding adopts 2 RS codewords, thus, the RS-FEC encoding of the PCS layer of the 800GE Ethernet adopts 6 RS codewords.
  • Example 6 The architecture of six 100GE Ethernet layers and the architecture of one 200GE Ethernet layer can also be spliced into an 800G Ethernet layer in parallel. From the 100GE Ethernet layer architecture shown in Figure 2 and the 400GE Ethernet layer architecture shown in Figure 4, it can be known that the RS-FEC encoding of the 100GE Ethernet PCS layer uses one RS codeword, and the RS-FEC encoding of the 400GE Ethernet PCS layer uses one RS codeword. The encoding adopts 2 RS codewords, thus, the RS-FEC encoding of the PCS layer of the 800GE Ethernet adopts 8 RS codewords.
  • the RS-FEC encoding of the 800GE Ethernet PCS layer adopts the number of RS codewords, which is obtained in the compatible mode of the parallel architecture constituting the Ethernet layer, and the RS codeword in the non-compatible mode is obtained.
  • the number is variable.
  • Example 1 takes Example 1 as an example, and based on the Architecture 1 shown in FIG. 6a and the process shown in FIG. 7a, the processing flow of the data stream is described in further detail.
  • the 800G Ethernet PCS layer is formed by two 400GE PCS layers, and the encoder component of the second FEC codeword (Inner-FEC codeword) can be located in the PCS layer.
  • the 800G data stream is divided into two 400G data streams at the PCS layer. Each 400G data stream is the same as the 400GE PCS layer data stream operation process shown in Figure 7a.
  • the data stream enters the encoder of the Inner-FEC codeword (referred to as the Inner-FEC encoder) for encoding.
  • the data stream is divided into data blocks with a length of K bits, and the data blocks encoded by the Inner-FEC encoder are N bits.
  • the Inner-FEC encoder encodes a block of K bits into N bits.
  • the data stream encoded by the Inner-FEC encoder enters the PMA.
  • the data stream entering the PMA layer will undergo multiplexing and 10bit symbol distribution operations again.
  • the multiplexing and 10bit symbol distribution operations here are 4 RSs (544, 514, 10). Multiplexing of the PMA layer and distribution of 10bit symbols. Interleaving of 2-bit grains is implemented at the PMA layer.
  • the interleaved data stream is distributed to the PMD in bits, and modulation and electro-optical conversion are completed on the PMD.
  • Example 1 takes Example 1 as an example, and based on the second architecture shown in FIG. 6b and the flow shown in FIG. 7b, the processing flow of the data stream is described in further detail.
  • the 800G Ethernet PCS layer is formed by two 400GE PCS layers, and the encoder part of the second FEC codeword can be located in the PMA layer.
  • the 800G data stream is divided into two 400G data streams at the PCS layer. Each 400G data stream is the same as the 400GE PCS layer data stream operation process described in Figure 7b.
  • AM insertion, two-way RS encoding, two RS (544,514,10 ) and 10bit symbol distribution the data stream enters the PMA.
  • the data stream entering the PMA layer will undergo multiplexing and 10bit symbol distribution operations again.
  • the multiplexing and 10bit symbol distribution operations here are 4 RSs (544, 514, 10).
  • the data stream after the multiplexing of the PMA layer and the 10-bit symbol distribution operation enters the encoder of the Inner-FEC codeword (referred to as the Inner-FEC encoder) for encoding.
  • the data stream is divided into data blocks with a length of K bits, and the data block after entering the Inner-FEC encoder is N bits.
  • the Inner-FEC encoder encodes a block of K bits into N bits.
  • 2-bit particle interleaving is performed at the PMA layer.
  • the interleaved data stream is distributed to the PMD in bits, and modulation and electro-optical conversion are completed on the PMD.
  • a scheme of concatenating the first FEC codeword and the second FEC codeword is adopted, wherein the first FEC codeword is an outer code, and the second FEC codeword is an inner code.
  • the transmitting end first uses the first FEC codeword to encode the first information to be encoded, and then encodes the encoded first encoded data using the second FEC codeword.
  • the embodiment of the present application provides a method for adding an interleaving step in the concatenated coding scheme.
  • S501 in the embodiment of FIG. 5 can be described as:
  • the transmitting end uses y first FEC codewords to perform FEC encoding on the first information to be encoded to obtain y groups of encoded data, where y is greater than or an even number equal to 2; the transmitting end performs the first interleaving on the y groups of encoded data to obtain the first encoded data.
  • S501 and S502 in the embodiment of FIG. 5 can be described as:
  • the transmitting end uses the first FEC codeword to encode the first information to be encoded to obtain the first encoded data, including the following Step:
  • the transmitting end uses y first FEC codewords to perform FEC encoding on the first information to be encoded to obtain y groups of first encoded data.
  • the transmitting end uses the second FEC codeword to encode the first encoded data, which actually includes the following steps: the transmitting end performs the first interleaving on the y groups of the first encoded data, and uses the second FEC codeword to perform the first interleaving on the first interleaved data.
  • the first encoded data is encoded.
  • the first interleaving conforms to an interleaving matrix whose number of rows and columns are L and P respectively, that is, the transmitting end uses an interleaving matrix to interleave the y groups of encoded data.
  • the interleaving matrix may also be referred to as an interleaving pattern, which means that the interleaving is performed according to the interleaving matrix or the interleaving pattern in the process of interleaving the y groups of encoded data.
  • L and P are even numbers greater than or equal to 2
  • P is the number of PMA channels.
  • the PMA channel can be a real channel or a virtual channel.
  • the value of P may be an integer power of 2
  • the value of P may be 4, 8, 16, and 32.
  • the processes of encoding, interleaving, and output via the PMA channel can be implemented by the following processes. Several processes have changed the order of encoding, interleaving, and output via the PMA channel.
  • the transmitting end uses the first FEC codeword to encode the first information to be encoded to obtain y groups of encoded data; the transmitting end performs first interleaving on the y groups of encoded data to obtain the first encoded data; the transmitting end uses P PMA channels Transmit the first encoded data; use the second FEC codeword to encode the first encoded data transmitted by the P PMA channels to obtain the second encoded data.
  • the sending end uses the first FEC codeword to encode the first information to be encoded to obtain y groups of encoded data; the sending end transmits the y groups of encoded data through the P PMA channels; interleaving to obtain the first encoded data; the transmitting end uses the second FEC codeword to encode the first encoded data transmitted by the P PMA channels to obtain the second encoded data.
  • the transmitting end uses the first FEC codeword to encode the first information to be encoded to obtain y groups of encoded data; the transmitting end performs the first interleaving on the y groups of encoded data to obtain the first encoded data; The two FEC codewords encode the first encoded data to obtain the second encoded data; the transmitting end transmits the second encoded data through the P PMA channels, and processes the second encoded data transmitted by the P PMA channels. The processed data can also be sent to the receiving end.
  • the interleaver of the first interleaving can be denoted by ⁇ e .
  • the interleaver ⁇ e of the first interleaving may be an interleaver composed of a multiplexer (Mux) and a 10-bit symbol distribution (10-bit symbol distribution).
  • the above-mentioned flow 1 may be applicable to the encoder component of the second FEC codeword located at the PMA layer, and the interleaver ⁇ e of the first interleaving located in the Ethernet architecture of the PCS layer.
  • the second process may be applicable to an Ethernet architecture where the encoder component of the second FEC codeword is located at the PMA layer, and the interleaver ⁇ e of the first interleaving is located at the PMA layer.
  • the third process may be applicable to the encoder component of the second FEC codeword being located at the PCS layer, and the interleaver ⁇ e of the first interleaving being located in the Ethernet architecture of the PCS layer.
  • the row elements in a row of the interleaving matrix from left to right, respectively correspond to data obtained by polling from the y groups of encoded data.
  • y 4
  • the group numbers of the 4 groups of encoded data are a, b, c, and d, respectively
  • the row elements in a row of the interleaving matrix correspond to a, b, c, d, a, Data obtained in b, c, d...
  • Each row of L rows adopts the same polling rule; for example, the row elements in each row of the interleaving matrix, from left to right, correspond to a, b, c, d, a, b, c, d... acquired data.
  • the polling rules are different for each consecutive y row in the L rows.
  • y 4.
  • the polling rule for row 1 of L rows is: row elements in the first row of the interleaving matrix, from left to right, correspond to a, b, c, d, a, b, c, d...
  • the polling rules of the 1st row to the 4th row in the L rows are different for 4 consecutive rows.
  • the polling rules of the fifth row to the eighth row in the L row may be the same as the polling rules of the first row to the fourth row, respectively.
  • the polling rules of every four consecutive rows of the L row are different.
  • the polling rules of the fifth row to the eighth row in the L row are different, and for example, the polling rules of the third row to the sixth row in the L row are also different.
  • the first interleaving in the above process 2 complies with the following rules:
  • the corresponding sequence numbers of the P PMA channels are 0 to (P-1), and the P columns of the interleaving matrix correspond to the encoded data from the P PMA channels one-to-one respectively; the row elements with odd column numbers in a row of the interleaving matrix correspond to The coded data of the PMA channels with the serial numbers 0 to (P/2-1); the row elements whose column serial numbers are even numbers in a row of the interleaving matrix correspond to the coded data of the PMA channels with the serial numbers of P/2 to P, respectively.
  • the row elements whose column numbers are even numbers respectively correspond to the encoded data of the PMA channels whose numbers are 0 to (P/2-1);
  • the row elements respectively correspond to the encoded data of the PMA channels whose serial numbers are P/2 to P.
  • the data processing process is as follows.
  • the two 400Gbps data streams enter the AM Insertion module. After inserting the alignment markers, the data streams are polled and distributed (10-bit round robin distribution) to the RS codeword at a granularity of 10 bits. symbol.
  • codeword A There are four RS codewords in FIG. 9, which are denoted as codeword A, codeword B, codeword C, and codeword D, respectively.
  • the lower 0-bit information symbol (symbol to be encoded) of the codeword A is represented as mA0
  • the lower 1-bit information symbol is represented as mA1
  • the upper 512-bit information symbol is represented as mA512
  • the upper 513-bit information symbol is represented as mA513.
  • the lower 0-bit information symbol of codeword B is represented as mB0
  • the lower 1-bit information symbol is represented as mB1
  • the upper 512-bit information symbol is represented as mB512
  • the upper 513-bit information symbol is represented as mB513.
  • the lower 0-bit information symbol of the codeword C is represented as mC0
  • the lower 1-bit information symbol is represented as mC1
  • the upper 512-bit information symbol is represented as mC512
  • the upper 513-bit information symbol is represented as mC513.
  • the lower 0-bit information symbol of the codeword D is represented as mD0
  • the lower 1-bit information symbol is represented as mD1
  • the upper 512-bit information symbol is represented as mD512
  • the upper 513-bit information symbol is represented as mD513.
  • the encoding process of codeword A, codeword B, codeword C, and codeword D may correspond to the embodiment in FIG. 5 , where the first FEC codeword is used to encode y pieces of information to be encoded to obtain y groups of encoded data. The value of y is 4.
  • the concatenated encoding of the second FEC codeword is completed on the data stream at the PMA layer through the optoelectronic interface C2M or through P PMA channels.
  • the encoded codeword is the second FEC codeword, that is, the Inner-FEC codeword.
  • cA ⁇ 543-8L-j> represents the 543-8L-j symbol bit of the RS codeword A on the left of Figure 9
  • cB ⁇ 543-8L-j> represents the 543-th symbol bit of the RS codeword B on the left of Figure 9 8L-j sign bits
  • cC ⁇ 543-8L-j> represents the 543-8L-j sign bits of the RS code word C on the right side of Figure 9
  • cD ⁇ 543-8L-j> represents the RS code on the right side of Figure 9 543-8L-j sign bits of word D.
  • tx_out represents the output data stream of the interleaver according to the symbol granularity
  • tx_out ⁇ 32L+4j> represents the 32L+4j symbol of the output data stream of the interleaver
  • tx_out ⁇ 32L+4j+1> represents the 32Lth output data stream of the interleaver +4j+1 symbols
  • tx_out ⁇ 32L+4j+2> represents the 32L+4j+2 symbol of the output data stream of the interleaver
  • tx_out ⁇ 32L+4j+3> represents the 32L+4th symbol of the output data stream of the interleaver +2j+3 symbols.
  • the interleaving rule adopted by the interleaver ⁇ e may be, for example, the following interleaving rule 1, interleaving rule 2, interleaving rule 3 and interleaving rule 4.
  • the first interleaving rule is: the 32 symbols in the first row on the 32 PMA channels are distributed in turn by 4 RS code words A, B, C, and D; the 32 symbols in the second row are composed of 4 RS codes. Words D, C, B, A are polled and distributed in turn; the 32 symbols in the third row are polled and distributed in turn by four RS code words B, A, D, and C; the 32 symbols in the fourth row are distributed by four The RS codewords C, D, A, and B are distributed in turn by polling, and each subsequent row is distributed in 10-bit granularity according to this rule.
  • the interleaving rule 1 of the interleaver ⁇ e can be expressed as:
  • the second interleaving rule is:
  • the 32 symbols of the first row on the 32 PMA channels are polled and distributed by 4 RS code words A, B, C, and D in turn; the 32 symbols of the second row are composed of 4 RS code words B, A, and D. D and C are polled and distributed in turn; the 32 symbols in the third row are polled and distributed in turn by 4 RS codewords C, D, A, and B; the 32 symbols in the fourth row are polled and distributed by 4 RS codewords D, C, B, and A are distributed in turn by polling, and each subsequent row is distributed with 10-bit granularity according to this rule.
  • the interleaving rule of the interleaver can be expressed in pseudocode as:
  • the third interleaving rule is: the 32 symbols in the first row on the 32 PMA channels are polled and distributed in turn by 4 RS code words A, B, C, and D; the 32 symbols in the second row are composed of 4 RS codes. Words C, D, A, B are polled and distributed in turn; the 32 symbols in the third row are polled and distributed by four RS code words B, A, D, and C in turn; the 32 symbols in the fourth row are distributed by four The RS codewords D, C, B, and A are distributed in turn by polling, and each subsequent row is distributed in 10-bit granularity according to this rule.
  • the interleaving rule three of the interleaver can be expressed in pseudocode form as:
  • the fourth interleaving rule is: the 32 symbols in the first row on the 32 PMA channels are polled and distributed by 4 RS code words A, B, C, and D in turn; the 32 symbols in the second row are composed of 4 RS codes. Words D, C, B, A are polled and distributed in turn; the 32 symbols in the third row are polled and distributed in turn by four RS code words A, B, C, and D; the 32 symbols in the fourth row are distributed by four The RS codewords D, C, B, and A are distributed in turn by polling, and each subsequent row is distributed in 10-bit granularity according to this rule.
  • the interleaving rule four of the interleaver can be expressed in pseudocode form as:
  • the data stream is sent into the Inner-FEC module through the PMA channel to carry out the inner code encoding operation, and the original data interleaving of the PMA is directly multiplexed after the inner code encoding is completed.
  • Complete data modulation and photoelectric conversion and transmit it to the communication medium through the MDI interface to complete the data transmission.
  • interleaving rule 1 to interleaving rule 4 in the symbol distribution process of each row, codeword A and codeword B are always adjacent, and codeword C and codeword D are always adjacent, so there is no need to distinguish adjacent ones. Codeword A and codeword B do not need to distinguish adjacent codeword C and codeword D, which reduces the complexity.
  • the ⁇ e interleaving depth is increased from the symbol distribution of 2 RSs to the symbol distribution of 4 RSs, and the distribution pattern is changed from the parity distribution pattern in the original standard to the new distribution pattern, but the RS code of each PCS layer is required.
  • the symbols of the words are adjacent, that is, it is ensured that the symbols of the RS codewords A and B in FIG.
  • Such an interleaver design can recognize the boundaries of symbols, and the 10-bit granularity exactly matches the size of the symbols of the RS.
  • Such an interleaver enables the symbols of different RSs to be allocated to the Inner-FEC codewords more randomly and evenly, and is compatible with the number of RSs in each PCS layer without distinguishing the symbols of the RS codewords from the PCS layer data stream. It can reduce the operation of identifying the RS symbol boundary, and can improve the ability of the system to resist Burst Error.
  • the data processing process is as follows.
  • the two 400Gbps data streams enter the AM Insertion module. After inserting the alignment mark, the data stream will be distributed (10-bit round robin distribution) to the information symbols of the RS codeword at a granularity of 10 bits. .
  • codeword A, codeword B, codeword C, and codeword D there are four RS codewords in FIG. 10, which are denoted as codeword A, codeword B, codeword C, and codeword D, respectively.
  • codeword A, codeword B, codeword C, and codeword D For the encoding methods of codeword A, codeword B, codeword C, and codeword D, reference may be made to the description related to FIG. 9 , which will not be repeated here.
  • codeword A, codeword B, codeword C, and codeword D may correspond to the embodiment in FIG. 5 , where the first FEC codeword is used to encode y pieces of information to be encoded to obtain y groups of encoded data.
  • the value of y is 4.
  • the two groups of encoded data after codeword A and codeword B are interleaved by the interleaver of Mux and 10-bit symbol distribution, which can be recorded as the third interleaving.
  • the two groups of encoded data after encoding by codeword C and codeword D are interleaved.
  • Mux performs third interleaving with an interleaver of 10-bit symbol distribution.
  • j represents the number of symbols for each RS contained in one row of each PMA lane, and L represents how many rows there are in the PMA lane.
  • cA ⁇ 543-8L-j> represents the 543-8L-j symbol bit of the RS codeword A on the left of Figure 10
  • cB ⁇ 543-8L-j> represents the 543-th symbol bit of the RS codeword B on the left of Figure 10 8L-j sign bits
  • cC ⁇ 543-8L-j> represents the 543-8L-j sign bit of the RS code word C on the right side of Figure 10
  • cD ⁇ 543-8L-j> represents the RS code on the right side of Figure 10 543-8L-j sign bits of word D.
  • the data streams output from the 32 PMA channels enter the interleaver ⁇ e for interleaving, and the data streams after interleaving by the interleaver ⁇ e complete the concatenated encoding of the second FEC codeword at the PMA layer.
  • the encoded codeword is the second FEC codeword, that is, the Inner-FEC codeword.
  • the interleaver ⁇ e is equivalent to performing a secondary Mux and 10-bit symbol distribution on the data output through the 32 PMA channels, and completes a more adequate interleaving of the data streams of the two 400G PCS layers at the PMA layer.
  • the data stream is transmitted to the PMA layer through the optoelectronic interface C2M, so the bit errors caused at the optoelectronic interface are before the interleaver ⁇ e , and it is impossible to know which symbols belong to which RS codewords at this time, unless the deinterleaving is done at the PMA layer, which will require greater cost.
  • the interleaving rule adopted by the interleaver ⁇ e may be, for example, the following interleaving rule 5.
  • the five interleaving rules are:
  • tx_out represents the output data stream of the interleaver at symbol granularity.
  • the corresponding serial numbers of the 32 PMA channels are 0 to (32-1), and the 32 columns of the interleaving matrix correspond to the encoded data from the 32 PMA channels one-to-one.
  • the row elements whose column numbers are even numbers respectively correspond to the encoded data of the PMA channels whose numbers are 0 to (32/2-1);
  • the row elements respectively correspond to the encoded data of the PMA channels whose serial numbers are 32/2 to 32.
  • the interleaving rule 5 of the interleaver ⁇ e can be expressed in pseudocode as:
  • Such an interleaving method design does not need to identify the boundaries of symbols, so that the PMA layer does not need to know the format of the PCS layer data frame, and directly performs multiplexing and 10-bit granularity distribution on the data stream received by the PMA layer.
  • the 10-bit (10-bits) granularity just matches the size of the symbol of the second FEC codeword, which improves the system's ability to resist burst errors, and the implementation is simple.
  • the data processing process is as follows.
  • the process shown in FIG. 11 can refer to the process shown in FIG. 9 .
  • the difference is that in FIG. 9 , after the 4 groups of coded data are interleaved by the interleaver ⁇ e , the first coded data obtained is transmitted through 32 PMA channels, and the first coded data is transmitted through 32 PMA channels.
  • the two FEC codewords encode the first encoded data transmitted by the 32 PMA channels to obtain the second encoded data.
  • FIG. 11 shows that after the 4 groups of coded data are interleaved with the interleaver ⁇ e , the first coded data is obtained, the second FEC codeword is used to encode the first coded data, and the second coded data is obtained, and the second coded data is obtained through 32 PMA channels.
  • the second encoded data is transmitted, and the second encoded data transmitted by the 32 PMA channels is processed.
  • FIG. 11 the difference between FIG. 11 and FIG. 9 is that the position of the second FEC encoding is different.
  • the details of each step can refer to the description of the embodiment of FIG. 9 .
  • Figures 9 to 11 are described by taking Example 1 shown in Figure 8 as an example, that is, the parallel splicing of two 400GE Ethernet layers to form an 800G Ethernet layer.
  • Example 2 the parallel splicing of four 200GE Ethernet layers to form an 800GE Ethernet layer as an example to describe the data processing flow.
  • the data stream is coded in cascade at the PMA layer through the optical and electrical interface C2M.
  • the encoded codeword is Inner-FEC.
  • cA ⁇ 543-4L-j> represents the 543-4L-j symbol bit of RS codeword A
  • cB ⁇ 543-4L-j> represents the 543-4L-jth symbol bit of RS codeword B
  • cC ⁇ 543-4L-j> represents the 543-4L-jth sign bit of RS codeword C
  • cD ⁇ 543-4L-j> represents the 543-4L-jth sign bit of RS codeword D
  • cE ⁇ 543 -4L-j> represents the 543-4L-jth sign bit of the RS codeword E
  • cF ⁇ 543-4L-j> represents the 543-4L-jth sign bit of the RS codeword F
  • cG ⁇ 543-4L -j> represents the 543-4L-jth sign bit of the RS codeword G
  • cH ⁇ 543-4L-j> represents the 543-4L-jth sign bit of the RS codeword H.
  • tx_out represents the output data stream of the interleaver according to the symbol granularity
  • tx_out ⁇ 32L+8j> represents the 32L+8j symbol of the output data stream of the interleaver
  • tx_out ⁇ 32L+8j+1> represents the 32Lth output data stream of the interleaver +8j+1 symbols
  • tx_out ⁇ 32L+8j+2> represents the 32L+8j+2 symbol of the output data stream of the interleaver
  • tx_out ⁇ 32L+8j+3> represents the 32k+8jth output data stream of the interleaver +3 symbols
  • tx_out ⁇ 32k+8j+4> represents the 32L+8j+4 symbol of the output data stream of the interleaver
  • tx_out ⁇ 32L+8j+5> represents the 32L+8j+5th symbol of the output data stream of the interleaver symbols
  • the interleaving rule adopted by the interleaver ⁇ e may be the interleaving rule six.
  • the sixth interleaving rule is: 32 symbols in the first row on the 32 PMA channels are polled and distributed by 8 RS codewords A, B, C, D, E, F, G, and H in turn; 32 symbols in the second row symbols, which are distributed in turn by 8 RS code words C, D, E, F, G, H, A, B; the 32 symbols in the third row are composed of 8 RS code words E, F, G, H , A, B, C, and D are polled and distributed in turn; the 32 symbols in the fourth row are polled and distributed in turn by 8 RS codewords G, H, A, B, C, D, E, and F; 32 symbols are polled and distributed in turn by 8 RS code words H, G, F, E, D, C, B, A; the 32 symbols in the sixth row are composed of 8 RS code words B, A, H, G, F, E, D, C are distributed in turn by polling; the 32 symbols in the seventh row are polled and distributed in turn by
  • the interleaving rule six of the interleaver ⁇ e can be expressed in pseudocode form as:
  • the symbol distribution method can increase the ⁇ e interleaving depth from the symbol distribution of 2 RSs to the symbol distribution of 8 RSs, and the distribution pattern is changed from the odd-even distribution pattern in the original standard to the new distribution pattern, but each path PCS is required.
  • the symbols of the RS codewords of the layers are adjacent, that is, the symbols of the RS codewords A and B are adjacent, the symbols of C and D are adjacent, the symbols of E and F are adjacent, and the symbols of G and H are adjacent.
  • the data stream is sent to the Inner-FEC module through the PMA channel to perform the inner code encoding operation.
  • the original data interleaving of the PMA is directly multiplexed for ⁇ O interleaving, and the final data is completed in the PMD.
  • the conversion is transmitted to the communication medium through the MDI interface to complete the data transmission.
  • FIG. 12 a schematic flowchart of the Ethernet encoding method provided by the embodiment of the present application may be as shown in FIG. 12 .
  • the main process includes that the data stream to be encoded is encoded by the RS encoder, interleaved by the interleaver ⁇ e , encoded by the Inner-FEC encoder, and interleaved by the interleaver ⁇ o .
  • ⁇ e can use the original polling distribution, or other distribution or interleaving methods.
  • the sequence of the various steps can be changed, and for details, reference may be made to the description of the various embodiments above, and FIG. 12 is a schematic diagram of one way.
  • the PCS layer coding and the PMA layer coding are decoupled.
  • Each layer of coding is responsible for different error types and error distributions.
  • the system as a whole has an optimal coding benefit with the lowest implementation complexity.
  • the delay and resource consumption level are both an optimal solution.
  • the method provided by the embodiment of the present application solves the problem that the error type and error distribution do not match the error correction efficiency of the designed Inner-FEC codeword.
  • the interleaving between the first FEC codeword (RS codeword) and the second FEC codeword (Inner-FEC) is to gather the residual errors after Inner-FEC into one RS symbol (10-bit) , so that the Hamming distance at the symbol level between the RS and the Inner-FEC is minimized, and the error correction efficiency of the RS is improved; while the interleaving between the channel and the Inner-FEC reduces the Burst Error of the channel to a certain extent, making the Burst
  • the error length is within the correctable range of Inner-FEC, which improves the error correction efficiency of Inner-FEC.
  • the solutions provided by the embodiments of the present application can achieve a comprehensive optimal effect on various technical indicators such as delay, computational complexity, resource consumption, and system compatibility under the premise of meeting the performance indicators of the next-generation Ethernet.
  • an embodiment of the present application further provides an Ethernet encoding apparatus 1300 , and the apparatus 1300 has the function of implementing the foregoing Ethernet encoding method.
  • the functions can be implemented by hardware, or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the apparatus 1300 may include an acquisition module 1301 and a processing module 1302 .
  • the obtaining module 1301 is used to obtain the first information to be encoded; the processing module 1302 is used to encode the first information to be encoded by using the first forward error correction code (FEC) code word to obtain the first encoded data.
  • the error code FEC codeword is Reed Solomon forward error correction code RS-FEC; the processing module 1302 is further configured to use the second FEC codeword to encode the first encoded data to obtain the second encoded data; the second FEC codeword
  • the code length N and information bit length K conform to the following formulas: Wherein, M1 is the throughput rate of the first encoded data, and M2 is the throughput rate of the second encoded data.
  • the processing module 1302 is configured to: use y first FEC codewords to perform FEC on the first information to be encoded. Coding to obtain y groups of coded data, where y is an even number greater than or equal to 2; perform first interleaving on y groups of coded data to obtain first coded data; the first interleaving conforms to an interleaving matrix whose number of rows and columns are L and P respectively, L and P is an even number greater than or equal to 2, and P is the number of PMA channels in the physical medium access sublayer.
  • the row elements in a row of the interleaving matrix respectively correspond to the data obtained by polling from the y groups of encoded data.
  • each of the L lines adopts the same polling rule; or, the polling rule of each consecutive y line in the L line is different.
  • the processing module 1302 when using the second FEC codeword to encode the first encoded data, is configured to: transmit the first encoded data through the P PMA channels; encode the first encoded data transmitted by the P PMA channels. .
  • the processing module 1302 is further configured to: transmit the second encoded data through the P PMA channels, and process the second encoded data transmitted by the P PMA channels.
  • the processing module 1302 when performing the first interleaving on the y groups of coded data, is configured to: transmit the y groups of coded data through the P PMA channels; and perform the first interleaving on the y groups of coded data transmitted by the P PMA channels.
  • the corresponding sequence numbers of the P PMA channels are 0 to (P-1), and the P columns of the interleaving matrix are in one-to-one correspondence with the encoded data from the P PMA channels; row elements with odd-numbered column numbers in a row of the interleaving matrix , which correspond to the encoded data of the PMA channels with serial numbers 0 to (P/2-1), respectively; the row elements whose column serial numbers are even in a row of the interleaving matrix correspond to the encoding of the PMA channels with serial numbers P/2 to P, respectively. data.
  • the value of P includes 16 or 32.
  • K also satisfies the following conditions: is a positive integer, and N1 is the code length of the first FEC codeword.
  • N and K also satisfy the following conditions: Reference clock *W, W is a positive integer.
  • W 4*reference clock multiplication factor RCM.
  • M1 106.25Gbps
  • M2 114Gbps.
  • the structure of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, and K is the number of bits included in the information bits,
  • the m is the order of the Galois field where the second FEC codeword is located;
  • the second FEC codeword includes any one of the following codewords, or includes a space where any of the following codewords is constructed as a subcode Coupling code, or a multi-layer code consisting of any of the following code words as subcodes: Hamming (144, 136, 8), Hamming (180, 170, 10), extended Hamming code eHamming (180, 170, 9), double-extended Hamming Clear code DE-Hamming(180,170,8), BCH(360,340,10), double extended BCH code DE-BCH(360,340,9), DE-BCH(576,544,10), or BCH(594,561,11), or Hamming( 180
  • the structure of the second FEC codeword is (N, K, m), where N is the number of bits included in the code length of the second FEC codeword, and K is the number of bits included in the information bits.
  • the number of bits, the m is the order of the Galois field where the FEC codeword is located; the second FEC codeword includes any of the following codewords, or includes any of the following codewords for subcodes.
  • Spatially coupled code or a multi-layer code consisting of any of the following codewords as subcodes: Hamming(126,119,7), Hamming(127,119,8), Hamming(145,136,9), Hamming(179,170,9), eHamming(127,119,7), eHamming(145,136,8), eHamming(179,170,8), eHamming(181,170,10), BCH(290,272,9), BCH(358,340,9), BCH(574,544,10), extended BCH codes eBCH(291,272,9), eBCH(359,340,9), eBCH(361,340,10), eBCH(575,544,10), or DE-BCH(362,340,10).
  • the processing module 1302 is further configured to: perform one or more of the following processing on the second encoded data: transmission through P PMA channels, second interleaving, data modulation, or photoelectric conversion; P is greater than or equal to 2 an even number; the apparatus further includes a communication module 1303, configured to send the processed data to the receiving device.
  • N x*n
  • K x*k
  • x, n and k are positive integers.
  • an Ethernet encoding apparatus 1400 is further provided in this embodiment of the present application, and the Ethernet encoding apparatus 1400 can be used to execute the foregoing Ethernet encoding method.
  • Part or all of the above-mentioned Ethernet encoding method can be implemented by hardware or software.
  • the Ethernet encoding device 1400 includes: an input interface circuit 1401 for obtaining the first information to be encoded.
  • the logic circuit 1402 is used for executing the above-mentioned Ethernet encoding method.
  • the output interface circuit 1403 is used for outputting the second encoded data.
  • the Ethernet encoding apparatus 1400 may be a chip or an integrated circuit during specific implementation.
  • the Ethernet encoding apparatus 1400 includes: a memory 1501 for storing a program; a processor 1502 , is used to execute the program stored in the memory 1501 , and when the program is executed, the Ethernet encoding apparatus 900 can implement the Ethernet encoding method provided by the foregoing embodiments.
  • the above-mentioned memory 1501 may be a physically independent unit, or the memory 1501 and the processor 1502 may be integrated together.
  • the Ethernet encoding apparatus 1400 may also only include the processor 1502.
  • the memory 1501 for storing programs is located outside the encoding device 1400 of the Ethernet, and the processor 1502 is connected to the memory 1501 through circuits/wires for reading and executing the programs stored in the memory 1501 .
  • the processor 1502 may be a central processing unit (CPU), a network processor (NP), or a combination of CPU and NP.
  • CPU central processing unit
  • NP network processor
  • the processor 1502 may further include hardware chips.
  • the above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof.
  • the above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.
  • the memory 1501 may include volatile memory (volatile memory), such as random-access memory (RAM); the memory 1501 may also include non-volatile memory (non-volatile memory), such as flash memory (flash memory) memory), hard disk drive (HDD) or solid-state drive (solid-state drive, SSD); the memory 1501 may also include a combination of the above-mentioned types of memory.
  • volatile memory volatile memory
  • non-volatile memory non-volatile memory
  • flash memory flash memory
  • HDD hard disk drive
  • solid-state drive solid-state drive
  • the Ethernet encoding device 1400 may also be a chip, an integrated circuit or a chip system.
  • Embodiments of the present application may further provide a chip, including a processor, for supporting the Ethernet encoding apparatus 1400 to implement the functions involved in the foregoing method embodiments.
  • the chip is connected to a memory or the chip includes a memory for storing necessary program instructions and data of the Ethernet encoding device 1400 .
  • An embodiment of the present application provides a computer-readable storage medium storing a computer program, where the computer program includes instructions for executing the foregoing method embodiments.
  • the embodiments of the present application provide a computer program product containing instructions, which, when executed on a computer, enable the above method embodiments to be implemented.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

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Abstract

本申请公开了一种以太网的编码方法及装置，以期适应高带宽带来的更大的传输误码的场景。该方法为：发送端采用第一前向纠错码FEC码字对第一待编码信息进行编码，获得第一编码数据，所述第一前向纠错码FEC码字为里德所罗门前向纠错码RS-FEC；所述发送端采用第二FEC码字对所述第一编码数据进行编码，获得第二编码数据；所述第二FEC码字的码长N和信息位长度K符合以下公式：(I) 其中，所述M1为所述第一编码数据的吞吐率，所述M2为所述第二编码数据的吞吐率。

Description

一种以太网的编码方法及装置
本申请要求于2020年10月29日提交中国国家知识产权局、申请号为202011183088.7、申请名称为“一种以太网的编码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及编码技术领域，尤其涉及一种以太网的编码方法及装置。
背景技术
随着网络业务吞吐率的高速增长，通讯设备的业务带宽也快速增长，国际标准组织定义了IEEE802.3以太网(ethernet)协议，IEEE 802.3以太网协议中已经定义了100GE、200GE、400GE的接口协议。大数据传输对高带宽有更高的需求，这给数据中心架构和底层互连带来了压力。基于此考虑，下一代以太网800G的标准化工作已开始推进。
以太网800G虽然能够提供更高的传输带宽，但是会带来传输误码增大的问题。如何提供一种更高纠错性能的编码方法是亟需解决的问题。
发明内容
本申请实施例提供一种以太网的编码方法及装置，以期提供一种更高纠错性能的编码方法，以适应高带宽带来的更大的传输误码的场景。
第一方面，提供一种以太网的编码方法，该方法的执行主体可以是发送端，或者称为编码设备。该方法的步骤包括：发送端采用第一FEC码字对第一待编码信息进行编码，获得第一编码数据，所述第一FEC码字为里德所罗门前向纠错码RS-FEC，所述发送端采用第二FEC码字对所述第一编码数据进行编码，获得第二编码数据。所述第二FEC码字的码长N和信息位长度K符合以下公式：
Figure PCTCN2021101722-appb-000001
其中，所述M1为所述第一编码数据的吞吐率，所述M2为所述第二编码数据的吞吐率。可以看出，通过采用两种FEC码字级联的编码方案，能够支持以太网800G甚至更高的吞吐率需求，通过第二FEC码字的设计，通过提高系统FEC编码的开销(overhead，OH)方式增加纠错性能。以太网800G采用更高的波特率传输，纠前误码率更高，通过采用两种FEC码字级联的编码方案，能够提高以太网的纠错性能，满足以太网800G的纠错性能指标。通过设置约束条件
Figure PCTCN2021101722-appb-000002
能够满足光器件带宽和传输性能限制。在满足下一代以太网技术指标需求的前提下，灵活支持和兼容IEEE 802.3标准中100GE、200GE、400GE的大多接口协议。
在一个可能的设计中，所述发送端采用第一FEC码字对第一待编码信息进行FEC编码，获得第一编码数据，通过以下方式实现：所述发送端采用y个第一FEC码字对所述第一待编码信息进行FEC编码，获得y组编码数据，所述y为大于或等于2的偶数；所述发送端对所述y组编码数据进行第一交织，获得所述第一编码数据；所述第一交织符合行列数分别为L和P的交织矩阵，所述L和所述P为大于等于2的偶数，所述P为物理介质接入子层PMA通道的数目。能够使得第一FEC码字编码之后的编码数据交织的更加充分，提高纠错性能。在第一FEC码字(RS码字)与第二FEC码字(Inner-FEC)之间的交织，是将Inner-FEC之后残余的误码能够聚集到一个RS的符号(10-bit)中，使得RS与Inner-FEC 之间符号水平的汉明Hamming距离最小，提高RS的纠错效率。
在一个可能的设计中，所述交织矩阵的一行中的行元素，分别对应于从所述y组编码数据中轮询获取的数据。这样的交织方式使得PCS层的不同RS的符号，可以更加随机均匀的分配到第二FEC码字(Inner-FEC)码字上，可以提升系统抗Burst Error的能力。这样的交织可以兼容每路PCS层的RS的个数，不用区别从PCS层数据流中RS码字的符号，可以减少识别RS符号边界的操作。
在一个可能的设计中，所述L行的每一行采取相同的轮询规则；或者，所述L行中每连续y行的轮询规则均不相同。
在一个可能的设计中，所述发送端采用第二FEC码字对所述第一编码数据进行编码，通过以下方式实现：所述发送端通过P个PMA通道传输所述第一编码数据；对所述P个PMA通道传输的所述第一编码数据进行编码。
在一个可能的设计中，所述发送端通过P个PMA通道传输所述第二编码数据，对所述P个PMA通道传输的所述第二编码数据进行处理。
在一个可能的设计中，所述发送端对所述y组编码数据进行第一交织，通过以下方式实现：所述发送端通过P个PMA通道传输所述y组编码数据；对所述P个PMA通道传输的所述y组编码数据进行所述第一交织。
在一个可能的设计中，所述P个PMA通道对应序号为0～(P-1)，所述交织矩阵的P列分别与来自P个PMA通道的编码数据一一对应；所述交织矩阵的一行中列序号为奇数的行元素，分别对应于序号为0～(P/2-1)的PMA通道的编码数据；所述交织矩阵的一行中列序号为偶数的行元素，分别对应于序号为P/2～P的PMA通道的编码数据。这样的交织方法设计可以不用识别符号(symbol)的边界，使得PMA层不必知道PCS层数据帧的格式，直接在PMA层接收到的数据流上进行复用和10bit颗粒度的分发。10比特(10-bits)颗粒度正好匹配第二FEC码字的符号的大小，提升了系统抗突发误差(burst error)能力，实现方式简单。
在一个可能的设计中，所述P的取值可以是2的整数次幂，例如可以是16或32。
在一个可能的设计中，所述K还满足以下条件：
Figure PCTCN2021101722-appb-000003
为正整数，N1为所述第一FEC码字的码长。这样，可以将第一FEC码字的输出(即第二FEC码字的输入)等分为整数份，每份为K，并且，每份输入不需要填充比特。使得第一FEC码字和第二FEC码字的级联编码方案更加简单易实现，复杂度较低。
在一个可能的设计中，所述N和所述K还满足以下条件：
Figure PCTCN2021101722-appb-000004
参考时钟*W，W为正整数。第二FEC码字对应的以太网编码的方案，能够使得以太网时钟提取和同步的实现更加简单。W为整数时，PLL才可以整格点地调整，时钟提取和同步实现简单，这样可以更快速地完成PLL的相位锁定，且易于实现，复杂度较低。
其中，W可以为4*参考时钟倍频因子RCM。
在一个可能的设计中，所述M1＝106.25Gbps，所述M2＝114Gbps。
在一个可能的设计中，
Figure PCTCN2021101722-appb-000005
在一个可能的设计中，第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为所述第二FEC码字所在伽罗华域的阶数；所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：汉明码Hamming(144,136,8)、Hamming(180,170,10)、扩展汉明码eHamming(180,170,9)、 双扩展汉明码DE-Hamming(180,170,8)、BCH(360,340,10)、双扩展BCH码DE-BCH(360,340,9)、DE-BCH(576,544,10)、或BCH(594,561,11)、或Hamming(180,170,10)。
在一个可能的设计中，第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为该FEC码字所在伽罗华域的阶数；所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：Hamming(126,119,7)、Hamming(127,119,8)、Hamming(145,136,9)、Hamming(179,170,9)、eHamming(127,119,7)、eHamming(145,136,8)、eHamming(179,170,8)、eHamming(181,170,10)、BCH(290,272,9)、BCH(358,340,9)、BCH(574,544,10)、扩展BCH码eBCH(291,272,9)、eBCH(359,340,9)、eBCH(361,340,10)、eBCH(575,544,10)、或DE-BCH(362,340,10)。
在一个可能的设计中，所述发送端对所述第二编码数据进行以下一项或多项处理：通过P个PMA通道传输、第二交织、数据调制、或光电转换；所述P为大于或等于2的偶数；所述发送端向接收设备发送处理后的数据。
在一个可能的设计中，N＝x*n，K＝x*k，其中，x、n和k为正整数。
本申请实施例提供的以太网的编码方法，通过第一FEC码字和第二FEC码字的级联编码方案，级联码的外码沿用原有标准的RS码字，级联码的内码采用第二FEC码字，即Inner-FEC码字，该编码方法能够兼容100GE、200GE、400GE以太网RS(544,514,10)编码，并通过RS(544,514,10)级联Inner-FEC的码字的编码方法增加了整个FEC编码的开销(overhead，OH)。系统链路FEC编码的OH增大，提高了系统的纠错性能，既满足下一高速以太网的性能指标，又满足下一代以太网的时延要求且实现代价小。
此Inner-FEC码字的编码器部件可以置于PCS层，也可以置于PMA层。当Inner-FEC码字的编码器部件置于PMA层时，将PCS层的RS编码与PMA层的Inner-FEC编码解耦，可以在包含有C2M光电接口处固有的误码的情况下完成PMA层的Inner-FEC编码。当Inner-FEC码字的编码器部件置于级联在PCS层，同样可以完成级联编码方案。
第二方面，提供一种以太网的编码装置，该装置具有实现上述第一方面和第一方面的任一种可能的设计中所述的方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。一种设计中，该装置可以包括获取模块和处理模块。示例性地：获取模块，用于获取第一待编码信息；处理模块，用于采用第一前向纠错码FEC码字对第一待编码信息进行编码，获得第一编码数据，所述第一前向纠错码FEC码字为里德所罗门前向纠错码RS-FEC；所述处理模块，还用于采用第二FEC码字对所述第一编码数据进行编码，获得第二编码数据；所述第二FEC码字的码长N和信息位长度K符合以下公式：
Figure PCTCN2021101722-appb-000006
其中，所述M1为所述第一编码数据的吞吐率，所述M2为所述第二编码数据的吞吐率。
在一个可能的设计中，在采用第一FEC码字对第一待编码信息进行FEC编码，获得第一编码数据时，所述处理模块用于：采用y个第一FEC码字对所述第一待编码信息进行FEC编码，获得y组编码数据，所述y为大于或等于2的偶数；对所述y组编码数据进行第一交织，获得所述第一编码数据；所述第一交织符合行列数分别为L和P的交织矩阵，所述L和所述P为大于等于2的偶数，所述P为物理介质接入子层PMA通道的数目。
在一个可能的设计中，所述交织矩阵的一行中的行元素，分别对应于从所述y组编码数据中轮询获取的数据。
在一个可能的设计中，所述L行的每一行采取相同的轮询规则；或者，所述L行中每连续y行的轮询规则均不相同。
在一个可能的设计中，在采用第二FEC码字对所述第一编码数据进行编码时，所述处理模块用于：通过P个PMA通道传输所述第一编码数据；对所述P个PMA通道传输的所述第一编码数据进行编码。
在一个可能的设计中，所述处理模块还用于：通过P个PMA通道传输所述第二编码数据，对所述P个PMA通道传输的所述第二编码数据进行处理。
在一个可能的设计中，在对所述y组编码数据进行第一交织时，所述处理模块用于：通过P个PMA通道传输所述y组编码数据；对所述P个PMA通道传输的所述y组编码数据进行所述第一交织。
在一个可能的设计中，所述P个PMA通道对应序号为0～(P-1)，所述交织矩阵的P列分别与来自P个PMA通道的编码数据一一对应；所述交织矩阵的一行中列序号为奇数的行元素，分别对应于序号为0～(P/2-1)的PMA通道的编码数据；所述交织矩阵的一行中列序号为偶数的行元素，分别对应于序号为P/2～P的PMA通道的编码数据。
在一个可能的设计中，所述P的取值包括16或32。
在一个可能的设计中，所述K还满足以下条件：
Figure PCTCN2021101722-appb-000007
为正整数，N1为所述第一FEC码字的码长。
在一个可能的设计中，所述N和所述K还满足以下条件：
Figure PCTCN2021101722-appb-000008
参考时钟*W，W为正整数。
在一个可能的设计中，W＝4*参考时钟倍频因子RCM。
在一个可能的设计中，所述M1＝106.25Gbps，所述M2＝114Gbps。
在一个可能的设计中，
Figure PCTCN2021101722-appb-000009
在一个可能的设计中，第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为所述第二FEC码字所在伽罗华域的阶数；所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：汉明码Hamming(144,136,8)、Hamming(180,170,10)、扩展汉明码eHamming(180,170,9)、双扩展汉明码DE-Hamming(180,170,8)、BCH(360,340,10)、双扩展BCH码DE-BCH(360,340,9)、DE-BCH(576,544,10)、或BCH(594,561,11)、或Hamming(180,170,10)。
在一个可能的设计中，第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为该FEC码字所在伽罗华域的阶数；所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：Hamming(126,119,7)、Hamming(127,119,8)、Hamming(145,136,9)、Hamming(179,170,9)、eHamming(127,119,7)、eHamming(145,136,8)、eHamming(179,170,8)、eHamming(181,170,10)、BCH(290,272,9)、BCH(358,340,9)、BCH(574,544,10)、扩展BCH码eBCH(291,272,9)、eBCH(359,340,9)、eBCH(361,340,10)、eBCH(575,544,10)、或DE-BCH(362,340,10)。
在一个可能的设计中，所述处理模块还用于：对所述第二编码数据进行以下一项或多项处理：通过P个PMA通道传输、第二交织、数据调制、或光电转换；所述P为大于或等于2的偶数；所述装置还包括，通信模块，用于向接收设备发送处理后的数据。
在一个可能的设计中N＝x*n，K＝x*k，其中，x、n和k为正整数。
第二方面的有益效果可以参见第一方面的相应描述，在此不再赘述。
第三方面，提供一种以太网的编码装置，该装置具有实现上述第一方面和第一方面的任一种可能的设计中所述的方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述以太网的编码装置包括：输入接口电路，用于获取第一待编码信息；逻辑电路，用于基于获取的第一待编码信息执行上述第一方面和第一方面的任一种可能的设计中所述的行为，输出接口电路，用于输出第二编码数据。
可选的，所述以太网的编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述以太网的编码装置包括：存储器，用于存储程序或指令；处理器，用于执行所述存储器存储的所述程序或指令，当所述程序或指令被执行时，上述第一方面和第一方面的任一种可能的设计中所述的方法被实现。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述以太网的编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第四方面，提供了一种计算机可读存储介质，存储有计算机可读指令，当所述计算机可读指令在计算机上运行时，使得如第一方面和第一方面的任一可能设计中任一种所述的方法被执行。
第五方面，本申请实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得上述第一方面和第一方面的任一可能设计所述的方法被执行。
第六方面，本申请实施例提供了一种芯片系统，该芯片系统包括处理器，还可以包括存储器，用于实现上述第一方面或第一方面中任一种可能的设计中所述的方法。该芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。
附图说明
图1a为本申请实施例中通信系统的结构示意图；
图1b为本申请实施例中以太网架构示意图；
图2为本申请实施例中100GE以太网的RS-FEC编码示意图；
图3为本申请实施例中200GE以太网的RS-FEC编码示意图；
图4为本申请实施例中400GE以太网的RS-FEC编码示意图；
图5为本申请实施例中以太网的编码方法的流程示意图之一；
图6a为本申请实施例中以太网层架构一示意图；
图6b为本申请实施例中以太网层架构二示意图；
图7a为本申请实施例中架构一对应的数据流的处理过程示意图；
图7b为本申请实施例中架构二对应的数据流的处理过程示意图；
图8为本申请实施例中800G以太网层架构示意图；
图9为本申请实施例中数据处理的流程示意图之一；
图10为本申请实施例中数据处理的流程示意图之二；
图11为本申请实施例中数据处理的流程示意图之三；
图12为本申请实施例中以太网的编码方法的流程示意图之二；
图13为本申请实施例中以太网的编码装置结构示意图之一；
图14为本申请实施例中以太网的编码装置结构示意图之二；
图15为本申请实施例中以太网的编码装置结构示意图之三。
具体实施方式
本申请实施例提供一种以太网的编码方法及装置，以期提高以太网编码的纠错性能。其中，方法和装置是基于同一技术构思的，由于方法及装置解决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。
本申请实施例的描述中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。本申请中所涉及的多个是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
本申请实施例提供的通信方法可以应用于以太网，也可以应用到其它采用门前向纠错码(forward error correction，FEC)编码的网络中。本申请实施例可以适用于数据中心的短距互联、云存储、云计算、第五代(5th generation，5G)基站骨干网等大流量、短时延的应用场景。
下面将结合附图，对本申请实施例进行详细描述。
图1a为本申请实施例所适用的一种通信系统100的结构示意图。通信系统中包括发送端101和接收端102。其中，发送端也可以称为发送设备，接收端也可以称为接收设备。发送端还可以称为发送装置，接收端还可以称为接收装置。本申请实施例以发送端和接收端为例进行描述。当本申请实施例应用于以太网中时，发送端和接收端均支持IEEE802.3以太网协议。如图1b所示，为本申请实施例所适用的一种以太网的架构示意图。包括数据中心的交换机和服务器，交换机之间可以相连，交换机与服务器之间也可以相连。可以理解的是图1b是示意图，实际以太网的网络中还可以包括更多或者更少的交换机，更多或更少的服务器。交换机与交换机之间的连接方式、交换机与服务器之间的连接方式，是一种示意。
在以太网中，发送端101为交换机，接收端102为交换机；发送端101为交换机，接收端102为服务器；发送端101为服务器，接收端102为交换机。
本申请实施例提供的方法可以适用于多个领域，例如，增强现实/虚拟现实(augmented reality/virtual reality，AR/VR)、人工智能(artificial intelligence，AI)、5G应用或者云应用等。越来越多领域的应用都会产生越来越多的吞吐率，吞吐率的爆炸性增长需要更高的带宽。因此，以太网800G的标准工作已开始推进。以太网传输带宽的增长，势必带来传输误码的增大。本申请实施例提供一种以太网的编码方法，以期适应更高的以太网传输带宽。
为了更好的理解本申请实施例提供的方案，以下先对IEEE 802.3标准中100GE、200GE、400GE的编码方案，以及一些涉及的概念和术语进行介绍。
1、100GE
在100GE以太网4通道物理介质关联层(physical media dependent，PMD)即KP4应用场景下，编码方案采用里德所罗门(Reed-Solomon，RS)(544,514,10)码字。RS码字的码长n RS＝544，信息符号位长度k RS＝514，伽罗华域为GF(2 10)。100GE KP4以太网的编码方案的流程示意图如图2所示。来自媒体接入控制(medium access control，MAC)和更高层的客户端的数据会经过协调(reconciliation)子层，调协子层将来自MAC和更高层的客户端的数据进行翻译，通过100G比特每秒(bit per second，bps，b/s)介质独立接口(100Gb/s media independent interface，CGMII)接口发送到100GBASE-R的物理编码子层(physical coding sublayer，PCS)层。PCS层将数据进行转码、扰码、插入AM等操作，送入里德所罗门前向纠错码(Reed-Solomon forward error correction，RS-FEC)码字进行编码。100GE以太网的RS-FEC编码采用一个RS(544,514,10)码字。编码后的码字会进入物理介质接入子层(physical medium attachment sublayer，PMA)层进行复用(Mux)等a操作，操作后的数据流通过一个四通道连接单元接口(four-lane attachment unit interface，CAUI-4)芯片到模块(chip-to-module，C2M)接口传递到下一层的PMA，数据流通过PMA后，PMD将数据流进行调制和光电转换。媒介依赖接口(medium dependent interface，MDI)接口将调制和光电转换后的光信号通过光纤等媒介(medium)传送到接收端。
2、200GE、400GE
200GE、400GE以太网的编码方案，也采用RS(544,514,10)码字。RS码字的码长n RS＝544，信息符号位长度k RS＝514，伽罗华域为GF(2 10)。
200GE以太网的编码方案的流程示意图如图3所示。来自MAC和更高层的客户端的数据会经过调协子层，调协子层将来自MAC和更高层的客户端的数据进行翻译，通过200GMII接口发送到200GBASE-R的PCS层。PCS层将数据进行转码、扰码、插入AM等操作，送入RS-FEC模块进行编码。200GE以太网的RS-FEC编码采用两个RS(544,514,10)码字，来自PCS层的数据流通过10比特(bit)轮询分发的方式发送到两个RS码字上。两个RS码字分别编码后的码字会进入PMA层进行Mux等操作，操作后的数据流通过一个200G四通道连接单元接口(four-lane attachment unit interface，CAUI-4)C2M接口传递到下一层的PMA，数据流通过PMA后，PMD将数据流进行调制和光电转换。MDI接口将调制和光电转换后的光信号通过光纤等媒介(medium)传送到接收端。
400GE以太网的编码方案的流程示意图如图4所示。来自MAC和更高层的客户端的数据会经过调协子层，调协子层将来自MAC和更高层的客户端的数据进行翻译，通过400GMII接口发送到400GBASE-R的PCS层。PCS层将数据进行转码、扰码、插入AM等操作，送入RS-FEC模块进行编码。400GE以太网的RS-FEC编码采用两个RS(544,514,10)码字，来自PCS层的数据流通过10比特(bit)轮询分发的方式发送到两个RS码字上。两个RS码字分别编码后的码字，再通过Mux和10bit符号分发，进入PMA层，PMA层输出的数据流通过一个400GAUI-4C2M接口传递到下一层的PMA，数据流通过PMA后，PMD将数据流进行调制和光电转换。MDI接口将调制和光电转换后的光信号通过光纤等媒介(medium)传送到接收端。
100GE、200GE和400GE以太网的编码方案均采用在PCS层做RS编码，RS编码后的数据流贯穿端到端，光链路与电层接口噪声引起的错误，都是由RS码进行纠正。然而当以太网演进到800G，单波长速率由400GE的100Gbps增加到200Gbps，受器件约束使 得纠前误码率水平增加，因此需要纠错能力更强的以太网的编码方法，需要与原有方案的数据流最大程度的兼容对接。
基于此，本申请实施例提供一种以太网的编码方法。如图5所示，本申请实施例提供的以太网的编码方法的具体流程如下所述。该方法的执行主体可以是发送设备、发送端或发送装置。
S501、发送端采用第一码字对第一待编码信息进行编码，获得第一编码数据。
其中，第一码字可以是前向纠错码(forward error correction，FEC)码字，记为第一FEC码字。例如，第一码字可以为RS-FEC码字，还可以称为RS码字，或RS码。
S502、发送端采用第二码字对第一编码数据进行编码，获得第二编码数据。
第二码字可以是FEC码字，记为第二FEC码字。
可以看出，本申请实施例采用两种FEC码字级联的编码方案，能够支持以太网800G甚至更高的吞吐率需求。以太网800G采用更高的波特率传输，纠前误码率更高，通过采用两种FEC码字级联的编码方案，能够提高以太网的纠错性能，满足以太网800G的纠错性能指标。
发送设备还可以对第二编码数据进行处理，并向接收设备发送处理后的数据。对应地，接收设备接收处理后的数据。
其中，处理过程可以包括：通过P个PMA通道传输、第二交织、数据调制、或光电转换。处理过程也可以包括以上的部分过程。其中，P为大于或等于2的偶数，或者P为2的整数次幂，例如P可以取值为4、8、16、32。
结合以上描述，下面对本申请实施例的一些可选的实现方式进行说明。
本申请实施例中，可以假设第一FEC码字即RS码字的构造为(544,514,10)，其中，514为第一FEC码字的信息符号位长度K1，544为第一FEC码字的码长N1。K1为514个符号，N1为544个符号，10表示一个符号为10个比特。即N1＝5440比特，K1＝5140比特。
当以太网采用两种FEC码字级联的编码方案时，以太网层的架构可以有以下几种示例。几种示例的以太网层的架构可以适用于以太网800G甚至更高带宽的网络。第一FEC码字为RS-FEC码字，第二FEC码字可以记为Inner-FEC码字。以太网层的架构可以包括MAC层、PCS层、PMA层和PMD层。其中，MAC层和PCS层可以认为是位于设备侧，PMA层和PMD层可以认为是位于模块侧。设备是指发送端的设备，例如可以是交换机，或者服务器。模块是指用于光通信的光模块。本申请实施例中，第一FEC码字的编码器部件用于完成第一FEC码字的编码，第二FEC码字的编码器部件用于完成第二FEC码字的编码。第一FEC码字的编码器部件也可以记为第一FEC码字的编码器或者第一FEC的编码模块或者RS-FEC编码器或者RS-FEC编码模块。第二FEC码字的编码器部件也可以记为第二FEC码字的编码器、第二FEC的编码模块、Inner-FEC编码器、Inner-FEC编码模块。当第二FEC码字为汉明码(Hamming)时，第二FEC码字的编码器部件也可以称为汉明码编码器或者汉明码编码模块，当第二FEC码字为BCH码时，第二FEC码字的编码器部件也可以称为或者BCH码编码器、或者BCH码编码模块。BCH码是(Bose、Ray-Chaudhuri与Hocquenghem)码。
架构一：
如图6a所示，第二FEC码字的编码器部件可以位于PCS层。
在设备侧的PCS层增加了Inner-FEC码字的编码器部件。数据流在设备侧依次经过MAC层、PCS层的64B/66B编码，256B/257B转码、扰码，插入AM以及10bit颗粒度轮询分发后，进行RS-FEC编码，其中，64B/66B编码可以是指将64比特的数据块扩展为66比特的信息块。256B/257B转码可以是指：对66比特的数据块进行排序和拆分，以25G的业务为例，将待发送数据拆分为多个66比特的数据块，每4个66比特数据块划分为一个数据块组(数据段)，每一个数据块组为257比特的数据块。
RS-FEC编码后的数据流进入Inner-FEC码字的编码器部件。数据流在Inner-FEC码字的编码器部件进行编码之后，通过AUI C2M接口进入模块侧。在模块侧完成PMA与PMD的操作后，用MDI接口将模块侧数据流传送到介质层完成数据流发送。
架构二：
如图6b所示，第二FEC码字的编码器部件可以位于PMA层。
在模块侧增添了Inner-FEC码字的编码器部件。数据流在设备侧依次经过MAC层、PCS层的64B/66B编码，256B/257B转码、扰码，插入AM以及10bit颗粒度轮询分发后，进行RS-FEC编码。64B/66B编码，256B/257B转码的过程可以参考架构一的描述。
RS-FEC编码后的数据流通过AUI C2M接口进入模块侧。在模块侧数据流进入Inner-FEC码字的编码器部件，数据流在Inner-FEC码字的编码器部件进行编码之后，进行PMA与PMD操作后，用MDI接口将模块侧数据流传送到介质层完成数据流发送。
可以理解的是，第二FEC码字的编码器部件还可以位于以太网的其它部位，上述架构一和架构二仅是一种示意性的举例。
下面基于架构一和架构二，描述数据流的处理流程。
在图6a所示的架构一的基础上，第二FEC码字的编码器部件可以位于PCS层，如图7a所示，数据流的处理过程如下所述。从MAC层输出的数据会经过PCS层，并且会在PCS层完成第二FEC码字的编码即Inner-FEC编码。Inner-FEC编码后的两路PCS层数据流独立分发到PMA层，在PMA层再合为800G的数据流。800G的数据流通过通信媒介，发送到接收端。
数据流的处理过程如下所述。数据流的处理过程包括从上向下的发送端数据流的处理过程，以及从下到上方向的接收端数据流的处理过程。
发送端数据流从MII接口处送达PCS层，PCS层兼容100GE、200GE、400GE标准协议。在发送端依次经过编码和速率匹配(encode and rate matching)、256B/257B转码(transcode)、扰码(scramble)、对齐标记插入(alignment insertion)、在FEC之前的分发(Pre-FEC distribution)、RS编码(RS Encode)、分发和交织(distribution and interleave)、PMA层处理、PMD层这10步主要操作步骤后，通过通信媒介发送到接收端。
其中，Encode and rate matching是64B/66B模块，将MII接口翻译后的TXD<63:0>数据块完成64B/66B编码，同时根据MII接口的TXC<7:0>进行吞吐率速率调整。256B/257B Transcode为256比特到257比特的转码。Scramble为扰码操作。alignment insertion为对齐标记插入操作。Pre-FEC distribution为RS编码前的10-比特的轮询分发操作。RS Encode为RS(544,514,10)编码操作。distribution and interleave为RS编码后的10比特颗粒度的符号分发和符号交织。符号分发和符号交织后的数据流进行第二FEC码字编码即Inner-FEC Encode步骤操作。完成Inner-FEC Encode操作后让数据流经过PMA和PMD的操作。
接收端从通信媒介接收到数据流，在接收端依次经过PMD、PMA、Alignment lock and lane deskew、Inner-FEC Decode、Lane reorder and de-interleave、RS Decode、Post-FEC interleave、Alignment removal、Descramble、Reverse Transcode、Decode and rate matching这11个主要步骤。接收端这经过的11个步骤，是发送端相应操作步骤的解操作。Inner-FEC Decode为Inner-FEC的解码操作。接收端这经过的11个步骤，是发送端相应操作步骤的解操作。Inner-FEC Decode为Inner-FEC的解码操作。Alignment lock and lane deskew为对齐标记锁定和通道对齐操作。Lane reorder and de-interleave为通道重排和解交织操作。RS Decode为RS(544,514,10)的解码操作。Post-FEC interleave为RS解码后Pre-FEC distribution的逆操作。Alignment removal为去除编码端添加的对齐标记的操作。Descramble为解扰码操作。Reverse Transcode为256B/257B转码的逆操作，将257比特逆转换为256比特。Decode and rate matching为64B/66B的逆操作以及吞吐率速率匹配操作。
在图6b所示的架构二的基础上，第二FEC码字的编码器部件可以位于PMA层，如图7b所示，数据流的处理过程如下所述。数据流的处理过程包括从上向下的发送端数据流的处理过程，以及从下到上方向的接收端数据流的处理过程。
发送端数据流从MII接口处送达PCS层，PCS层兼容100GE、200GE、400GE标准协议。在发送端依次经过编码和速率匹配(encode and rate matching)、256B/257B转码(transcode)、扰码(scramble)、对齐标记插入(alignment insertion)、在FEC之前的分发(Pre-FEC distribution)、RS编码(RS Encode)、分发和交织(distribution and interleave)、PMA层处理、第二FEC码字编码(Inner-FEC Encode)、PMD层处理这10步操作步骤后，通过通信媒介发送到接收端。
其中，Encode and rate matching是64B/66B模块，将MII接口翻译后的TXD<63:0>数据块完成64B/66B编码，同时根据MII接口的TXC<7:0>进行吞吐率速率调整。256B/257B Transcode为256比特到257比特的转码。Scramble为扰码操作。Alignment insertion为对齐标记插入操作。Pre-FEC distribution为RS编码前的10-比特的轮询分发操作。RS Encode为RS(544,514,10)编码操作。Distribution and Interleave为RS编码后的10比特颗粒度的符号分发和符号交织。PMA是在数据流经过PCS层操作后的下一层。数据流在PMA层会进行第二FEC码字的编码操作，即Inner-FEC Encode操作。
接收端从通信媒介接收到数据流，在接收端依次经过PMD、Inner-FEC Decode、PMA、Alignment lock and lane deskew、Lane reorder and de-interleave、RS Decode、Post-FEC interleave、Alignment removal、Descramble、Reverse Transcode、Decode and rate matching这11个主要步骤。接收端这经过的11个步骤，是发送端相应操作步骤的解操作。Inner-FEC Decode为Inner-FEC的解码操作。Alignment lock and lane deskew为对齐标记锁定和通道对齐操作。Lane reorder and de-interleave为通道重排和解交织操作。RS Decode为RS(544,514,10)的解码操作。Post-FEC interleave为RS解码后Pre-FEC distribution的逆操作。Alignment removal为去除编码端添加的对齐标记的操作。Descramble为解扰码操作。Reverse Transcode为256B/257B转码的逆操作，将257比特逆转换为256比特。Decode and rate matching为64B/66B的逆操作以及吞吐率速率匹配操作。
可以看出，本申请实施例提供的以太网的编码方法，通过第一FEC码字和第二FEC码字的级联编码方案，级联码的外码沿用原有标准的RS码字，级联码的内码采用第二FEC 码字，即Inner-FEC码字，该编码方法能够兼容100GE、200GE、400GE以太网RS(544,514,10)编码，并通过RS(544,514,10)级联Inner-FEC的码字的编码方法增加了整个FEC编码的开销(overhead，OH)。系统链路FEC编码的OH增大，提高了系统的纠错性能，既满足下一高速以太网的性能指标，又满足下一代以太网的时延要求且实现代价小。
此Inner-FEC码字的编码器部件可以置于PCS层，也可以置于PMA层。当Inner-FEC码字的编码器部件置于PMA层时，将PCS层的RS编码与PMA层的Inner-FEC编码解耦，可以在包含有C2M光电接口处固有的误码的情况下完成PMA层的Inner-FEC编码。当Inner-FEC码字的编码器部件置于级联在PCS层，同样可以完成级联编码方案。
在器件传输速率和系统链路预算的限制下，第二FEC码字需要符合一些约束条件。另外，旨在基于满足下一代以太网技术指标需求的前提下，灵活支持和兼容IEEE 802.3标准中100GE、200GE、400GE的大多接口协议，第二FEC码字也需要符合一些约束条件。本申请实施例中，第二FEC码字的码长用N表示，第二FEC码字的信息位长度用K表示。其中，N＝x*n，K＝x*k，其中，x、n和k为正整数，x为N和K的公因子。第一FEC码字的码长用N1表示，第一FEC码字的信息位长度用K1表示。在一种可能的实现中，FEC码字的长度可能比较长，在对码字的构造参数进行限定时，可以对码字构造的更细粒度的参数进行限定。例如，N＝x*n，K＝x*k，在对第二FEC码字的参数N、K进行限定时，可以通过限定n和k。以太网的PCS层进行RS-FEC编码采用的RS码字的个数用y表示。例如，图2所示的100GE以太网的RS-FEC编码采用1个RS，即y＝1。例如，图3所示的200GE以太网的RS-FEC编码采用2个RS，即y＝2。例如，图4所示的400GE以太网的RS-FEC编码采用2个RS，即y＝2。800G以太网的RS-FEC编码可以采用4个RS。
其中，采用RS的意思是采用RS的编码器部件。
假设第一FEC码字即RS码字的构造为(544,514,10)，其中，514为第一FEC码字的信息比特位长度K1，544为第一FEC码字的码长N1。K1为514个符号，N1为544个符号，10表示一个符号为10个比特。即N1＝5440比特，K1＝5140比特。
下面对第二FEC码字相关的一些实现形式进行说明。
第二FEC码字符合以下条件一～条件三中的任意一种或多种条件。
条件一：第二FEC码字的码长N和信息位长度K符合以下公式(1)。
Figure PCTCN2021101722-appb-000010
其中，M1为第一编码数据的吞吐率，M2为第二编码数据的吞吐率(throughput)。
公式(1)可以有多种变形的公式，例如，
Figure PCTCN2021101722-appb-000011
又例如，
Figure PCTCN2021101722-appb-000012
K为信息位长度，N为码长，可以认为K为编码前的输入，N为编码后的输出。K长的信息位经过第二FEC码字编码后，得到N长的编码后数据。M1为第一编码数据的吞吐率，第一编码数据的吞吐率作为第二FEC码字的输入，第二FEC码字的输出不能超过M2。
M2是基于以太网中的收发器速率、光器件带宽和传输性能的限制中的一种或多种因素，所确定的值，可以认为是第二编码数据的吞吐率。M2也可以认为是PMD层的输出数据吞吐率。
M1和M2的单位可以是Gbps。M1和M2取值可以为：M1＝106.25Gbps，M2＝114Gbps。即公式(1)变为
Figure PCTCN2021101722-appb-000013
其中，106.25Gbps是PCS层的单通道(lane)输出数据流吞吐率。
以太网以156.25MHz的参考时钟为基准，使用PLL进行时钟提取与时钟恢复，PLL 的锁相同步过程，是以参考时钟倍频因子(reference clock multiplier，RCM)为格点进行调整。MAC层的数据流会以64比特的位宽，通过PCS物理通道传输到PCS层。数据流在PCS层首先完成64B/66B的编码，再在4个64B/66B编码的基础上完成256B/257B的转码，20个转码后的数据块进行RS(544,514,10)的FEC编码。MAC层输入给PCS层的每100Gbps的数据吞吐率，在PCS层完成64B/66B编码、256B/257B转码以及RS编码后，在PCS层的单lane输出数据吞吐率为106.25Gbps。受光器件带宽和传输性能限制，PMD层输出数据吞吐率不能超过M2Gbps。可选的，M2＝114Gbps。
条件二：K还满足以下条件：
Figure PCTCN2021101722-appb-000014
为正整数，N1为第一FEC码字的码长。
通过图5实施例的级联编码方案可以看出，第一FEC码字的输出，作为第二FEC码字的输入。N1为第一FEC码字的码长，可以认为是第一FEC码字的输出。第二FEC码字是以K为单位进行输入并编码的，因此，设置N2为正整数倍的K，可以将第一FEC码字的输出(即第二FEC码字的输入)等分为整数份，每份为K，并且，每份输入不需要填充比特。使得第一FEC码字和第二FEC码字的级联编码方案更加简单易实现，复杂度较低。
N1＝5440比特时，条件二可以变换为
Figure PCTCN2021101722-appb-000015
为正整数。
代入K＝x*k，得到
Figure PCTCN2021101722-appb-000016
为正整数，N1＝5440比特时，变换为
Figure PCTCN2021101722-appb-000017
为正整数。
以太网的PCS层进行RS-FEC编码采用的RS码字的个数为y，其中，一个RS码字的输出码字码长N1，则y个RS码字的输出码字码长为y*N1。实际上，y个RS码字的输出即为第二FEC码字的输入，也就是说第二FEC码字的输入为y*N1，若需要满足第二FEC码字的输入能够被K整除，实际上需要满足y*N1能被K整除，即
Figure PCTCN2021101722-appb-000018
为正整数，或者，
Figure PCTCN2021101722-appb-000019
为正整数。
若将y取值为1，则
Figure PCTCN2021101722-appb-000020
为正整数。在y取值为1时，也就是在以太网的PCS层进行RS-FEC编码采用一个RS码字时，若能够满足RS码字的输出(即第二FEC码字的输入)能够被K整除，那么当y取值为2或者其他任意整数值时，y个RS码字的输出(即第二FEC码字的输入)都能够被K整除。因此，本申请实施例中，将y取值为1，得到约束条件二
Figure PCTCN2021101722-appb-000021
为正整数。
将y取值1，表示PCS层以1个RS(544,514,10)的颗粒度进行数据块的划分。Inner-FEC的信息位长度能整除1个RS(544,514,10)码字，则RS的个数无论有几个，均是1个RS(544,514,10)长度的整数倍。由于100GE的PCS层RS个数为1，200GE和400GE的PCS层RS个数为2，为100Gbps颗粒度的以太网PCS层，在码字约束中将y值取1。下一代800G以太网，y值可取y＝4。
条件三：N和K还满足以下条件：
Figure PCTCN2021101722-appb-000022
参考时钟*L，L为正整数。例如，L＝4*RCM。
当以太网的架构为架构一时，第二FEC码字的编码器部件可以位于PCS层，第二FEC码字还需要满足条件三。
例如，传输每100Gbps的数据流过程中，每个100Gbps的数据流会以156.25MHz的RCM为格点调整进行串并转换，由4路的数据流合并成一路，以串行方式在一个传输通道进行数据流的传输。因此第二FEC码字即Inner-FEC码字需要满足：
Figure PCTCN2021101722-appb-000023
W为正整数。或者满足：
Figure PCTCN2021101722-appb-000024
W为正整数。
满足条件三的第二FEC码字对应的以太网编码的方案，能够使得以太网时钟提取和同步的实现更加简单。W为整数时，PLL才可以整格点地调整，这样可以更快速地完成PLL的相位锁定，且易于实现，复杂度较低。
可选的，当第二FEC码字的编码器部件置于PMA层时，第二FEC码字可以满足条件一和条件二中的至少一种，不需要满足条件三也可以。当第二FEC码字的编码器部件置于PCS层时，第二FEC码字可以满足条件一、条件二和条件三中的至少一种。
在一个可能的设计中，本申请实施例还对第二FEC码字设置了条件四。
条件四：
Figure PCTCN2021101722-appb-000025
或者
Figure PCTCN2021101722-appb-000026
或者一些其他的变型，例如，
Figure PCTCN2021101722-appb-000027
即
Figure PCTCN2021101722-appb-000028
或者，
Figure PCTCN2021101722-appb-000029
以下给出一些可能的具体的第二FEC码字。
第二FEC码字的构造为(N，K，m)，N为所述第二FEC码字的码长所包含的比特数，K为所述信息位所包含的比特数，m为该FEC码字所在伽罗华域的阶数。
在符合条件四时，
Figure PCTCN2021101722-appb-000030
第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码(multilevel coding，MLC)：
(1)码字为汉明码(Hamming)(144,136,8)。其中，x＝8，N＝144，K＝136，OH＝5.88％。
(2)码字为Hamming(180,170,10)。其中，x＝10，N＝180，K＝170，OH＝5.88％。
(3)码字为扩展Hamming码(extended Hamming，eHamming)(180,170,9)。其中，x＝10，N＝180，K＝170，OH＝5.88％。
(4)码字为双扩展Hamming码(Double Extended Hamming，DE-Hamming)(180,170,8)。其中，x＝10，N＝180，K＝170，OH＝5.88％。
(5)码字为BCH(360,340,10)。其中，x＝20，N＝360，K＝340，OH＝5.88％。
(6)码字为DE-BCH(360,340,9)。其中，x＝20，N＝360，K＝340，OH＝5.88％。
(7)码字为DE-BCH(576,544,10)。其中，x＝32，N＝576，K＝544，OH＝5.88％。
(8)码字为BCH(594,561,11)。其中，x＝33，N＝594，K＝561，OH＝5.88％。
其中，在码字构造参数N，K，m确定的基础上，OH即可以确定出来。
码字(1)～码字(8)符合条件一、条件二、条件三和条件四。
可选的，第二FEC码字还可以包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：
1)Hamming(126,119,7)。其中，x＝7,OH＝5.88％，N＝126，K＝119。
2)Hamming(127,119,8)。其中，x＝7，OH＝6.72％，N＝127，K＝119。
3)Hamming(145,136,9)。其中，x＝8，OH＝6.62％，N＝144，K＝136。
4)Hamming(179,170,9)。其中，x＝10，OH＝5.29％，N＝179，K＝170。
5)eHamming(127,119,7)。其中，x＝7，OH＝6.72％，N＝127，K＝119。
6)eHamming(145,136,8)。其中，x＝8，OH＝6.62％，N＝145，K＝136。
7)eHamming(179,170,8)。其中，x＝10，OH＝5.29％，N＝179，K＝170。
8)eHamming(181,170,10)。其中，x＝10，OH＝6.47％，N＝181，K＝170。
9)BCH(290,272,9)。其中，x＝16，OH＝6.62％，N＝290，K＝272。
10)BCH(358,340,9)。其中，x＝20，OH＝5.29％，N＝358，K＝340。
11)BCH(574,544,10)。其中，x＝32，OH＝5.51％，N＝574，K＝544。
12)扩展BCH码eBCH(291,272,9)。其中，x＝16，OH＝6.99％，N＝291，K＝272。
13)eBCH(359,340,9)。其中，x＝20，OH＝5.59％，N＝359，K＝340。
14)eBCH(361,340,10)。其中，x＝20，OH＝6.18％，N＝361，K＝340。
15)eBCH(575,544,10)。其中，x＝32，OH＝5.70％，N＝575，K＝544。
16)DE-BCH(362,340,10)。其中，x＝20，OH＝6.47％，N＝362，K＝340。
码字1)～码字16)符合条件一和条件二。
上述各个码字仅仅是举例，实际应用中还可以存在更多符合条件的码字。通过第二FEC码字的设计，通过提高系统FEC编码的开销(overhead，OH)方式增加纠错性能。若以太网继续演进到1.6Tbps，本申请实施例提供的级联编码方案、以及级联方案下内码的上述各个约束条件依然适用。
结合图2、图3和图4分别给出的100GE、200GE和400GE的以太网层架构，以下给出几种可能的800G(或800GE)的以太网层架构的示例。
示例一：如图8所示，可以由2个400GE以太网层的架构并列拼接成800G以太网层。由图4所示的400GE以太网层架构可知，400GE以太网PCS层的RS-FEC编码采用2个RS码字，这样，800GE以太网PCS层的RS-FEC编码采用4个RS码字。
示例二：也可以由4个200GE以太网层的架构并列拼接成800G以太网层。由图3所示的200GE以太网层架构可知，200GE以太网PCS层的RS-FEC编码采用2个RS码字，800GE以太网PCS层的RS-FEC编码采用8个RS码字。
示例三：也可以由8个100GE以太网层的架构并列拼接成800G以太网层。由图2所示的100GE以太网层架构可知，100GE以太网PCS层的RS-FEC编码采用1个RS码字，这样，800GE以太网PCS层的RS-FEC编码采用8个RS码字。
示例四：也可以由4个100GE以太网层的架构和1个400GE以太网层的架构并列拼接成800G以太网层。由图2所示的100GE以太网层架构和图4所示的400GE以太网层架构可知，100GE以太网PCS层的RS-FEC编码采用1个RS码字，400GE以太网PCS层的RS-FEC编码采用2个RS码字，这样，800GE以太网PCS层的RS-FEC编码采用6个RS码字。
示例五：也可以由2个200GE以太网层的架构和1个400GE以太网层的架构并列拼接成800G以太网层。由图3所示的200GE以太网层架构和图4所示的400GE以太网层架构可知，200GE以太网PCS层的RS-FEC编码采用2个RS码字，400GE以太网PCS层的RS-FEC编码采用2个RS码字，这样，800GE以太网PCS层的RS-FEC编码采用6个RS码字。
示例六：也可以由6个100GE以太网层的架构和1个200GE以太网层的架构并列拼接成800G以太网层。由图2所示的100GE以太网层架构和图4所示的400GE以太网层架构可知，100GE以太网PCS层的RS-FEC编码采用1个RS码字，400GE以太网PCS层的RS-FEC编码采用2个RS码字，这样，800GE以太网PCS层的RS-FEC编码采用8个RS码字。
上述示例一～示例六，800GE以太网PCS层的RS-FEC编码采用RS码字的个数，是在构成以太网层的并列架构兼容的模式下得出的，非兼容的模式下RS码字的个数是可变的。
示例二～示例六并列架构组成800GE以太网的示意图可以参照示例一类比得出。
可以理解的是，随着系统的演进，本申请实施例的方案还可以适用于由1个800G的以太网层的架构组成，而非多个架构并列拼接而成。
下面以示例一为例，基于图6a所示的架构一和图7a所示的流程，对数据流的处理流程进行进一步详细描述。
800G以太网PCS层通过两个400GE的PCS层构成，第二FEC码字(Inner-FEC码字)的编码器部件可以位于PCS层。800G的数据流在PCS层分成两路400G数据流，每路400G数据流与图7a所示的400GE PCS层数据流操作流程一样，完成AM插入、两路RS编码、两个RS(544,514,10)的复用和10bit符号分发后数据流进入Inner-FEC码字的编码器(简称 Inner-FEC编码器)进行编码。数据流被分成长度为K比特的数据块，进入Inner-FEC编码器编码后的数据块为N比特。Inner-FEC编码器将K比特的数据块编码为N比特。完成Inner-FEC编码器编码后的数据流进入PMA。进入到PMA层的数据流会再进行一次复用和10bit符号分发操作，此处的复用和10bit符号分发操作为4个RS(544,514,10)。PMA层的复用和10bit符号分发。在PMA层实施2比特颗粒的交织。交织后的数据流按比特分发给PMD，在PMD上完成调制和电光转换。
下面以示例一为例，基于图6b所示的架构二和图7b所示的流程，对数据流的处理流程进行进一步详细描述。
800G以太网PCS层通过两个400GE的PCS层构成，第二FEC码字的编码器部件可以位于PMA层。800G的数据流在PCS层分成两路400G数据流，每路400G数据流与图7b所描述的400GE PCS层数据流操作流程一样，完成AM插入、两路RS编码、两个RS(544,514,10)的复用和10bit符号分发后，数据流进入PMA。进入到PMA层的数据流会再进行一次复用和10bit符号分发操作，此处的复用和10bit符号分发操作为4个RS(544,514,10)。PMA层的复用和10bit符号分发操作后的数据流进入Inner-FEC码字的编码器(简称Inner-FEC编码器)进行编码。数据流被分成长度为K比特的数据块，进入Inner-FEC编码器后的数据块为N比特。Inner-FEC编码器将K比特的数据块编码为N比特。完成Inner-FEC编码器编码后的数据流，在PMA层进行2比特颗粒的交织。交织后的数据流按比特分发给PMD，在PMD上完成调制和电光转换。
本申请实施例中，采用第一FEC码字和第二FEC码字级联编码的方案，其中，第一FEC码字为外码，第二FEC码字为内码。如图5实施例所述，发送端先采用第一FEC码字对第一待编码信息进行编码，再将编码后的第一编码数据采用第二FEC码字进行编码。考虑到输入第二FEC码字的数据的充分混合，本申请实施例提供一种方法，在级联编码的方案中增加交织的步骤。
在增加交织的步骤后，图5实施例中的S501可以描述为：S501中，发送端采用y个第一FEC码字对第一待编码信息进行FEC编码，获得y组编码数据，y为大于或等于2的偶数；发送端对y组编码数据进行第一交织，获得第一编码数据。
或者，在增加交织的步骤后，图5实施例中的S501和S502可以描述为：S501中，发送端采用第一FEC码字对第一待编码信息进行编码，获得第一编码数据，包括以下步骤：发送端采用y个第一FEC码字对第一待编码信息进行FEC编码，获得y组第一编码数据。S502中，发送端采用第二FEC码字对第一编码数据进行编码，实际上包括以下步骤：发送端对y组第一编码数据进行第一交织，采用第二FEC码字对第一交织后的第一编码数据进行编码。
增加交织后对S501和S502的描述，实际上操作的过程是一样的，只是文字表述不同而已。
其中，第一交织符合行列数分别为L和P的交织矩阵，即发送端对y组编码数据使用交织矩阵进行交织。交织矩阵也可以称为交织图样，是指，在对y组编码数据进行交织的过程中按照交织矩阵或者交织图样进行交织。其中，L和P为大于等于2的偶数，P为PMA通道的数目。PMA通道可以是真实的通道，也可以是虚拟的通道。例如，P的取值可以是2的整数次幂，例如P可以取值为4、8、16、32。
经过第一FEC码字进行编码之后，需要经过PMA通道输出，进入第二FEC码字的编 码器进行编码。在增加交织操作之后，编码、交织以及经过PMA通道输出的流程可以由以下几种流程来实现。几种流程从编码、交织以及经过PMA通道输出的顺序上做了改变。
流程一：
发送端采用第一FEC码字对第一待编码信息进行编码，获得y组编码数据；发送端对所述y组编码数据进行第一交织，获得第一编码数据；发送端通过P个PMA通道传输第一编码数据；采用第二FEC码字对P个PMA通道传输的第一编码数据进行编码，获得第二编码数据。
流程二：
发送端采用第一FEC码字对第一待编码信息进行编码，获得y组编码数据；发送端通过P个PMA通道传输y组编码数据；对P个PMA通道传输的y组编码数据进行第一交织，获得第一编码数据；发送端采用第二FEC码字对P个PMA通道传输的第一编码数据进行编码，获得第二编码数据。
流程三：发送端采用第一FEC码字对第一待编码信息进行编码，获得y组编码数据；发送端对所述y组编码数据进行第一交织，获得第一编码数据；发送端采用第二FEC码字对第一编码数据进行编码，获得第二编码数据；发送端通过P个PMA通道传输第二编码数据，对P个PMA通道传输的第二编码数据进行处理。还可以向接收端发送处理后的数据。
第一交织的交织器可以用π e表示。第一交织的交织器π e可以是复用器(Mux)与10比特符号分发(10-bit symbol distribution)组成的交织器。
上述流程一可以适用于第二FEC码字的编码器部件位于PMA层、第一交织的交织器π e位于PCS层的以太网架构中。流程二可以适用于第二FEC码字的编码器部件位于PMA层、第一交织的交织器π e位于PMA层的以太网架构中。流程三可以适用于第二FEC码字的编码器部件位于PCS层、第一交织的交织器π e位于PCS层的以太网架构中。
上述流程一和流程三中第一交织符合以下规则：
交织矩阵的一行中的行元素，从左到右分别对应于从y组编码数据中轮询获取的数据。例如，y＝4,4组编码数据的组号分别为a、b、c、d，交织矩阵的一行中的行元素，从左到右分别对应于从a、b、c、d、a、b、c、d……中获取的数据。
L行的每一行采取相同的轮询规则；例如，交织矩阵的每一行中的行元素，从左到右分别对应于从a、b、c、d、a、b、c、d……中获取的数据。
或者，L行中每连续y行的轮询规则均不相同。假设y＝4。例如，L行中的第1行的轮询规则为：交织矩阵的第一行中的行元素，从左到右分别对应于从a、b、c、d、a、b、c、d……中获取的数据；L行中的第2行的轮询规则为：交织矩阵的第二行中的行元素，从左到右分别对应于从d、c、b、a、d、c、b、a……中获取的数据；L行中的第3行的轮询规则为：交织矩阵的第三行中的行元素，从左到右分别对应于从b、a、d、c、b、a、d、c、……中获取的数据；L行中的第4行的轮询规则为：交织矩阵的第四行中的行元素，从左到右分别对应于从c、d、a、b、c、d、a、b、……中获取的数据。那么，L行中的第1行～第4行连续4行的轮询规则均不相同。L行中的第5行～第8行的轮询规则可以分别与第1行～第4行的轮询规则相同，那么，L行的每连续4行的轮询规则均不相同。例如，L行中的第5行～第8行的轮询规则不相同，又例如，L行中的第3行～第6行的轮询规则也不相同。
上述流程二中第一交织符合以下规则：
P个PMA通道对应序号为0～(P-1)，交织矩阵的P列分别与来自P个PMA通道的编码数据一一对应；交织矩阵的一行中列序号为奇数的行元素，分别对应于序号为0～(P/2-1)的PMA通道的编码数据；交织矩阵的一行中列序号为偶数的行元素，分别对应于序号为P/2～P的PMA通道的编码数据。当然，也可以是，交织矩阵的一行中列序号为偶数的行元素，分别对应于序号为0～(P/2-1)的PMA通道的编码数据；交织矩阵的一行中列序号为奇数的行元素，分别对应于序号为P/2～P的PMA通道的编码数据。
为了更好地理解上述流程一、流程二和流程三，以及更好地理解各个流程符合的交织规则，下面以图8所示的示例一为例，即由2个400GE以太网层的架构并列拼接成800G以太网层为例，对上述流程一～流程三以及交织规则进行详细的描述。
结合流程一的描述，如图9所示，数据处理的流程如下所述。
两路400Gbps的数据流进入对齐标记插入(AM Insertion)模块，数据流在插入对齐标记之后，以10bit的颗粒度轮询分发(10-bit round robin distribution)给RS码字(RS codeword)的信息符号。在图9中有四个RS码字，分别记为码字A、码字B、码字C和码字D。码字A的低0位信息符号(待编码符号)表示为mA0，低1位信息符号表示为mA1，高512位信息符号表示为mA512，高513位信息符号表示为mA513。同样的，码字B的低0位信息符号表示为mB0，低1位信息符号表示为mB1，高512位信息符号表示为mB512，高513位信息符号表示为mB513。码字C的低0位信息符号表示为mC0，低1位信息符号表示为mC1，高512位信息符号表示为mC512，高513位信息符号表示为mC513。码字D的低0位信息符号表示为mD0，低1位信息符号表示为mD1，高512位信息符号表示为mD512，高513位信息符号表示为mD513。码字A、B、C、D的信息符号完成分发后分别送入对应的编码器RS编码器A、RS编码器B、RS编码器C、RS编码器D。码字A完成编码后的低0位表示为cA0，cA0也是校验符号位pA0，即cA0＝pA0。码字A完成编码后的低1位表示为cA1，cA1也是校验符号位pA1，即cA1＝pA1。码字A完成编码后的低29位表示为cA29，cA29也是校验符号位pA29，即cA29＝pA29。码字A完成编码后的低30位表示为cA30，cA30也是信息符号位mA0，即cA30＝mA0。码字A完成编码后的低31位表示为cA31，cA31也是信息符号位mA1，即cA31＝mA1。码字A完成编码后的高543位表示为cA543，cA543也是信息符号位mA513，即cA543＝mA513。码字B完成编码后的低0位表示为cB0，cB0也是校验符号位pB0，即cB0＝pB0。码字B完成编码后的低1位表示为cB1，cB1也是校验符号位pB1，即cB1＝pB1。码字B完成编码后的低29位表示为cB29，cB29也是校验符号位pB29，即cB29＝pB29。码字B完成编码后的低30位表示为cB30，cB30也是信息符号位mB0，即cB30＝mB0。码字B完成编码后的低31位表示为cB31，cB31也是信息符号位mB1，即cB31＝mB1。码字B完成编码后的高543位表示为cB543，cB543也是信息符号位mB513，即cB543＝mB513。码字C完成编码后的低0位表示为cC0，cC0也是校验符号位pC0，即cC0＝pC0。码字C完成编码后的低1位表示为cC1，cC1也是校验符号位pC1，即cC1＝pC1。码字C完成编码后的低29位表示为cC29，cC29也是校验符号位pC29，即cC29＝pC29。码字C完成编码后的低30位表示为cC30，cC30也是信息符号位mC0，即cC30＝mC0。码字C完成编码后的低31位表示为cC31，cC31也是信息符号位mC1，即cC31＝mC1。码字C完成编码后的高543位表示为cC543，cC543也是信息符号位mC513，即cC543＝mC513。码字D完成编码后的低0位表示为cD0， cD0也是校验符号位pD0，即cD0＝pD0。码字D完成编码后的低1位表示为cD1，cD1也是校验符号位pD1，即cD1＝pD1。码字D完成编码后的低29位表示为cD29，cD29也是校验符号位pD29，即cD29＝pD29。码字D完成编码后的低30位表示为cD30，cD30也是信息符号位mD0，即cD30＝mD0。码字D完成编码后的低31位表示为cD31，cD31也是信息符号位mD1，即cD31＝mD1。码字D完成编码后的高543位表示为cD543，cD543也是信息符号位mD513，即cD543＝mD513。码字A、码字B、码字C和码字D的编码流程可以对应于图5实施例中，采用第一FEC码字对y个待编码信息进行编码，获得y组编码数据。y的取值为4。
在PCS层对4组编码数据采用交织器π e进行交织之后，通过光电接口C2M或通过P个PMA通道，将数据流在PMA层完成第二FEC码字的级联编码。编码码字为第二FEC码字即Inner-FEC码字。
图9所示架构下有P个PMA通道(PMA Lane)，P＝32，即32列PMA Lane，j表示每个PMA lane一行中含有的每个RS的符号数，L表示PMA Lane有多少行。其中cA<543-8L-j>代表图9左边的RS码字A的第543-8L-j个符号位，cB<543-8L-j>代表图9左边的RS码字B的第543-8L-j个符号位，cC<543-8L-j>代表图9右边的RS码字C的第543-8L-j个符号位，cD<543-8L-j>代表图9右边的RS码字D的第543-8L-j个符号位。tx_out代表交织器按symbol颗粒度的输出数据流，tx_out<32L+4j>表示交织器输出数据流的第32L+4j个符号，tx_out<32L+4j+1>表示交织器输出数据流的第32L+4j+1个符号，tx_out<32L+4j+2>表示交织器输出数据流的第32L+4j+2个符号，tx_out<32L+4j+3>表示交织器输出数据流的第32L+4+2j+3个符号。
交织器π e采用的交织规则例如可以是下述交织规则一、交织规则二、交织规则三和交织规则四。
交织规则一为：32个PMA通道上的第一行的32个符号，由4个RS码字A、B、C、D依次轮询分发；第二行的32个符号，由4个RS码字D、C、B、A依次轮询分发；第三行的32个符号，由4个RS码字B、A、D、C依次轮询分发；第四行的32个符号，由4个RS码字C、D、A、B依次轮询分发，之后的每一行都依此规则进行10bit颗粒度的分发。
交织器π e的交织规则一用伪代码形式可表示为：
For all k＝0to 67
For all j＝0to 7
if(k％4＝＝0)
tx_out<32k+4j>＝cA<543-8k-j>
tx_out<32k+4j+1>＝cB<543-8k-j>
tx_out<32k+4j+2>＝cC<543-8k-j>
tx_out<32k+4j+3>＝cD<543-8k-j>
else if(k％4＝＝1)
tx_out<32k+4j>＝cD<543-8k-j>
tx_out<32k+4j+1>＝cC<543-8k-j>
tx_out<32k+4j+2>＝cB<543-8k-j>
tx_out<32k+4j+3>＝cA<543-8k-j>
else if(k％4＝＝2)
tx_out<32k+4j>＝cB<543-8k-j>
tx_out<32k+4j+1>＝cA<543-8k-j>
tx_out<32k+4j+2>＝cD<543-8k-j>
tx_out<32k+4j+3>＝cC<543-8k-j>
else
tx_out<32k+4j>＝cC<543-8k-j>
tx_out<32k+4j+1>＝cD<543-8k-j>
tx_out<32k+4j+2>＝cA<543-8k-j>
tx_out<32k+4j+3>＝cB<543-8k-j>
交织规则二为：
32个PMA通道上的第一行的32个符号，由4个RS码字A、B、C、D依次轮询分发；第二行的32个符号，由4个RS码字B、A、D、C依次轮询分发；第三行的32个符号，由4个RS码字C、D、A、B依次轮询分发；第四行的32个符号，由4个RS码字D、C、B、A依次轮询分发，之后的每一行都依此规则进行10bit颗粒度的分发。交织器的交织规则用伪代码形式可表示为：
For all k＝0to 67
For all j＝0to 7
if(k％4＝＝0)
tx_out<32k+4j>＝cA<543-8k-j>
tx_out<32k+4j+1>＝cB<543-8k-j>
tx_out<32k+4j+2>＝cC<543-8k-j>
tx_out<32k+4j+3>＝cD<543-8k-j>
else if(k％4＝＝1)
tx_out<32k+4j>＝cB<543-8k-j>
tx_out<32k+4j+1>＝cA<543-8k-j>
tx_out<32k+4j+2>＝cD<543-8k-j>
tx_out<32k+4j+3>＝cC<543-8k-j>
else if(k％4＝＝2)
tx_out<32k+4j>＝cC<543-8k-j>
tx_out<32k+4j+1>＝cD<543-8k-j>
tx_out<32k+4j+2>＝cA<543-8k-j>
tx_out<32k+4j+3>＝cB<543-8k-j>
else
tx_out<32k+4j>＝cD<543-8k-j>
tx_out<32k+4j+1>＝cC<543-8k-j>
tx_out<32k+4j+2>＝cB<543-8k-j>
tx_out<32k+4j+3>＝cA<543-8k-j>
交织规则三为：32个PMA通道上的第一行的32个符号，由4个RS码字A、B、C、D依次轮询分发；第二行的32个符号，由4个RS码字C、D、A、B依次轮询分发；第三 行的32个符号，由4个RS码字B、A、D、C依次轮询分发；第四行的32个符号，由4个RS码字D、C、B、A依次轮询分发，之后的每一行都依此规则进行10bit颗粒度的分发。
交织器的交织规则三用伪代码形式可表示为：
For all k＝0to 67
For all j＝0to 7
if(k％4＝＝0)
tx_out<32k+4j>＝cA<543-8k-j>
tx_out<32k+4j+1>＝cB<543-8k-j>
tx_out<32k+4j+2>＝cC<543-8k-j>
tx_out<32k+4j+3>＝cD<543-8k-j>
else if(k％4＝＝1)
tx_out<32k+4j>＝cC<543-8k-j>
tx_out<32k+4j+1>＝cD<543-8k-j>
tx_out<32k+4j+2>＝cA<543-8k-j>
tx_out<32k+4j+3>＝cB<543-8k-j>
else if(k％4＝＝2)
tx_out<32k+4j>＝cB<543-8k-j>
tx_out<32k+4j+1>＝cA<543-8k-j>
tx_out<32k+4j+2>＝cD<543-8k-j>
tx_out<32k+4j+3>＝cC<543-8k-j>
else
tx_out<32k+4j>＝cD<543-8k-j>
tx_out<32k+4j+1>＝cC<543-8k-j>
tx_out<32k+4j+2>＝cB<543-8k-j>
tx_out<32k+4j+3>＝cA<543-8k-j>
交织规则四为：32个PMA通道上的第一行的32个符号，由4个RS码字A、B、C、D依次轮询分发；第二行的32个符号，由4个RS码字D、C、B、A依次轮询分发；第三行的32个符号，由4个RS码字A、B、C、D依次轮询分发；第四行的32个符号，由4个RS码字D、C、B、A依次轮询分发，之后的每一行都依此规则进行10bit颗粒度的分发。
交织器的交织规则四用伪代码形式可表示为：
For all k＝0to 67
For all j＝0to 7
if even(k)
tx_out<32k+4j>＝cA<543-8k-j>
tx_out<32k+4j+1>＝cB<543-8k-j>
tx_out<32k+4j+2>＝cC<543-8k-j>
tx_out<32k+4j+3>＝cD<543-8k-j>
else
tx_out<32k+4j>＝cD<543-8k-j>
tx_out<32k+4j+1>＝cC<543-8k-j>
tx_out<32k+4j+2>＝cB<543-8k-j>
tx_out<32k+4j+3>＝cA<543-8k-j>
上述交织器π e的交织完成后，数据流通过PMA通道送入Inner-FEC模块进行内码编码操作，内码编码完成后直接复用PMA原有的数据交织进行π O交织，最终数据在PMD完成数据调制和光电转换，通过MDI接口传送到通信介质完成数据发送。
交织规则一～交织规则四中，每一行的符号分发过程中，码字A和码字B总是相邻的，码字C和码字D总是相邻的，因此不需要区分相邻的码字A和码字B，不需要区分相邻的码字C和码字D，降低复杂度。使得π e交织深度由2个RS的符号分发增加到4个RS的符号分发，且分发图样由原有标准中的奇偶分发图样改变为到新的分发图样，但是需要每一路PCS层的RS码字的符号相邻近，即保证图9中的RS码字A和B的符号相邻，C和D的符号相邻。这样的交织器设计可以识别符号(symbol)的边界，10-bits颗粒度正好匹配RS的符号的大小。这样的交织器使得不同RS的符号，可以更加随机均匀的分配到Inner-FEC码字上，可以兼容每路PCS层的RS的个数，不用区别从PCS层数据流中RS码字的符号，可以减少识别RS符号边界的操作，可以提升系统抗Burst Error的能力。
结合流程二的描述，如图10所示，数据处理的流程如下所述。
两路400Gbps的数据流进入对齐标记插入(AM Insertion)模块数据流在插入对齐标记之后，以10bit的颗粒度轮询分发(10-bit round robin distribution)给RS码字(RS codeword)的信息符号。在图10中有四个RS码字，分别记为码字A、码字B、码字C和码字D。码字A、码字B、码字C和码字D的编码方法可以参考图9相关的描述，在此不再赘述。
码字A、码字B、码字C和码字D的编码流程可以对应于图5实施例中，采用第一FEC码字对y个待编码信息进行编码，获得y组编码数据。y的取值为4。
码字A和码字B编码之后的两组编码数据经过Mux与10-bit symbol distribution的交织器进行交织，可以记为第三交织，码字C和码字D编码之后的两组编码数据经过Mux与10-bit symbol distribution的交织器进行第三交织。
分别经过Mux与10-bit symbol distribution的交织器进行交织的4组编码数据，输入P个PMA通道(PMA Lane)，P＝32，即32列PMA Lane。j表示每个PMA lane一行中含有的每个RS的符号数，L表示PMA Lane有多少行。其中cA<543-8L-j>代表图10左边的RS码字A的第543-8L-j个符号位，cB<543-8L-j>代表图10左边的RS码字B的第543-8L-j个符号位，cC<543-8L-j>代表图10右边的RS码字C的第543-8L-j个符号位，cD<543-8L-j>代表图10右边的RS码字D的第543-8L-j个符号位。
从32个PMA通道输出的数据流进入交织器π e进行交织，交织器π e进行交织后的数据流在PMA层完成第二FEC码字的级联编码。编码码字为第二FEC码字即Inner-FEC码字。
交织器π e相当于对经过32个PMA通道输出的数据进行二次Mux与10-bit symbol distribution，将两路400G PCS层的数据流在PMA层完成一个更加充分的交织。数据流通过光电接口C2M传送到PMA层，因此光电接口处引起的误码在交织器π e之前，此时也无法知晓哪些符号属于哪个RS码字，除非在PMA层完成解交织，这样会需要较大的代价。因此若交织器π e放置于PMA层，采用blind模式设计交织器π e，交织器设计与PMA Lane相关即可。交织器π e采用的交织规则例如可以是下述交织规则五。
交织规则五为：
32条PMA Lane，从左到右第j条PMA Lane输出的符号(symbol)为S<j>，j＝1，2，…，31,32。符号大小为10bit。tx_out代表交织器按symbol颗粒度的输出数据流。
32个PMA通道对应序号为0～(32-1)，交织矩阵的32列分别与来自32个PMA通道的编码数据一一对应；交织矩阵的一行中列序号为奇数的行元素，分别对应于序号为0～(32/2-1)的PMA通道的编码数据；交织矩阵的一行中列序号为偶数的行元素，分别对应于序号为32/2～32的PMA通道的编码数据。当然，也可以是，交织矩阵的一行中列序号为偶数的行元素，分别对应于序号为0～(32/2-1)的PMA通道的编码数据；交织矩阵的一行中列序号为奇数的行元素，分别对应于序号为32/2～32的PMA通道的编码数据。
交织器π e的交织规则五用伪代码形式可表示为：
For all k＝0to 67
For all j＝0to 16
     If even(j)
tx_out<32k+j>＝S<j>
     else
tx_out<32k+j>＝S<16+j>
这样的交织方法设计可以不用识别符号(symbol)的边界，使得PMA层不必知道PCS层数据帧的格式，直接在PMA层接收到的数据流上进行复用和10bit颗粒度的分发。10比特(10-bits)颗粒度正好匹配第二FEC码字的符号的大小，提升了系统抗突发误差(burst error)能力，实现方式简单。
结合流程三的描述，如图11所示，数据处理的流程如下所述。
图11的流程可以参考图9所示的流程，不同的是，图9在对4组编码数据采用交织器π e进行交织之后，获得的第一编码数据，通过32个PMA通道传输，采用第二FEC码字对32个PMA通道传输的第一编码数据进行编码，获得第二编码数据。而图11是在对4组编码数据采用交织器π e进行交织之后，获得第一编码数据，采用第二FEC码字对第一编码数据进行编码，获得第二编码数据，通过32个PMA通道传输第二编码数据，对32个PMA通道传输的第二编码数据进行处理。
可见图11和图9的区别在于第二FEC编码的位置不同，除此之外，每个步骤的细节都可以参考图9实施例的描述。交织规则也可以参考图9的描述，在此不再赘述。
可以理解的是，图9～图11是以图8所示示例一为例，即由2个400GE以太网层的架构并列拼接成800G以太网层为例进行描述的，当以太网的架构是其它组成方式时，数据处理的流程是类似的，下面以示例二为例，即由4个200GE以太网层的架构并列拼接成800G以太网层为例，对数据处理流程进行描述。
四路200Gbps的数据流进入对齐标记插入(AM Insertion)模块，数据流在插入对齐标记之后，以10bit的颗粒度轮询分发(10-bit round robin distribution)给以10bit的颗粒度轮询分发(10-bit round robin distribution)。会有八个RS码字，分别记为码字A、码字B、码字C、码字D、码字E、码字F、码字G、和码字H。各个码字的RS编码方式可以参考图9实施例相关的描述。
在PCS层对4组编码数据采用交织器π e进行交织之后，通过光电接口C2M将数据流在PMA层完成级联编码。编码码字为Inner-FEC。
有P个PMA通道(PMA Lane)，P＝32，即32列PMA Lane，j表示每个PMA lane一行中含有的每个RS的符号数，L表示PMA Lane有多少行。
其中cA<543-4L-j>代表RS码字A的第543-4L-j个符号位，cB<543-4L-j>代表RS码字B的第543-4L-j个符号位，cC<543-4L-j>代表RS码字C的第543-4L-j个符号位，cD<543-4L-j>代表RS码字D的第543-4L-j个符号位，cE<543-4L-j>代表RS码字E的第543-4L-j个符号位，cF<543-4L-j>代表RS码字F的第543-4L-j个符号位，cG<543-4L-j>代表RS码字G的第543-4L-j个符号位，cH<543-4L-j>代表RS码字H的第543-4L-j个符号位。tx_out代表交织器按symbol颗粒度的输出数据流，tx_out<32L+8j>表示交织器输出数据流的第32L+8j个符号，tx_out<32L+8j+1>表示交织器输出数据流的第32L+8j+1个符号，tx_out<32L+8j+2>表示交织器输出数据流的第32L+8j+2个符号，tx_out<32L+8j+3>表示交织器输出数据流的第32k+8j+3个符号，tx_out<32k+8j+4>表示交织器输出数据流的第32L+8j+4个符号，tx_out<32L+8j+5>表示交织器输出数据流的第32L+8j+5个符号，tx_out<32L+8j+6>表示交织器输出数据流的第32L+8j+6个符号，tx_out<32L+8j+7>表示交织器输出数据流的第32L+8j+7个符号。
交织器π e采用的交织规则可以是交织规则六。
交织规则六为：32个PMA通道上的第一行的32个符号，由8个RS码字A、B、C、D、E、F、G、H依次轮询分发；第二行的32个符号，由8个RS码字C、D、E、F、G、H、A、B依次轮询分发；第三行的32个符号，由8个RS码字E、F、G、H、A、B、C、D依次轮询分发；第四行的32个符号，由8个RS码字G、H、A、B、C、D、E、F依次轮询分发；第五行的32个符号，由8个RS码字H、G、F、E、D、C、B、A依次轮询分发；第六行的32个符号，由8个RS码字B、A、H、G、F、E、D、C、依次轮询分发；第七行的32个符号，由8个RS码字D、C、B、A、H、G、F、E依次轮询分发；第八行的32个符号，由8个RS码字F、E、D、C、B、A、H、G依次轮询分发，之后的每一行都依此规则进行10bit颗粒度的分发。实际上，只要保证每连续8行的轮询规则均不相同即可，规则六的轮询规则是个举例。
交织器π e的交织规则六用伪代码形式可表示为：
For all k＝0to 67
For all j＝0to 4
if(k％8＝＝0)
tx_out<32k+8j>＝cA<543-4k-j>
tx_out<32k+8j+1>＝cB<543-4k-j>
tx_out<32k+8j+2>＝cC<543-4k-j>
tx_out<32k+8j+3>＝cD<543-4k-j>
tx_out<32k+8j+4>＝cE<543-4k-j>
tx_out<32k+8j+5>＝cF<543-4k-j>
tx_out<32k+8j+6>＝cG<543-4k-j>
tx_out<32k+8j+7>＝cH<543-4k-j>
else if(k％8＝＝1)
tx_out<32k+8j>＝cC<543-4k-j>
tx_out<32k+8j+1>＝cD<543-4k-j>
tx_out<32k+8j+2>＝cE<543-4k-j>
tx_out<32k+8j+3>＝cF<543-4k-j>
tx_out<32k+8j+4>＝cG<543-4k-j>
tx_out<32k+8j+5>＝cH<543-4k-j>
tx_out<32k+8j+6>＝cA<543-4k-j>
tx_out<32k+8j+7>＝cB<543-4k-j>
else if (k％8＝＝2)
tx_out<32k+8j>＝cE<543-4k-j>
tx_out<32k+8j+1>＝cF<543-4k-j>
tx_out<32k+8j+2>＝cG<543-4k-j>
tx_out<32k+8j+3>＝cH<543-4k-j>
tx_out<32k+8j+4>＝cA<543-4k-j>
tx_out<32k+8j+5>＝cB<543-4k-j>
tx_out<32k+8j+6>＝cC<543-4k-j>
tx_out<32k+8j+7>＝cD<543-4k-j>
else if (k％8＝＝3)
tx_out<32k+8j>＝cG<543-4k-j>
tx_out<32k+8j+1>＝cH<543-4k-j>
tx_out<32k+8j+2>＝cA<543-4k-j>
tx_out<32k+8j+3>＝cB<543-4k-j>
tx_out<32k+8j+4>＝cC<543-4k-j>
tx_out<32k+8j+5>＝cD<543-4k-j>
tx_out<32k+8j+6>＝cE<543-4k-j>
tx_out<32k+8j+7>＝cF<543-4k-j>
if(k％8＝＝4)
tx_out<32k+8j>＝cH<543-4k-j>
tx_out<32k+8j+1>＝cG<543-4k-j>
tx_out<32k+8j+2>＝cF<543-4k-j>
tx_out<32k+8j+3>＝cE<543-4k-j>
tx_out<32k+8j+4>＝cD<543-4k-j>
tx_out<32k+8j+5>＝cC<543-4k-j>
tx_out<32k+8j+6>＝cB<543-4k-j>
tx_out<32k+8j+7>＝cA<543-4k-j>
else if (k％8＝＝5)
tx_out<32k+8j>＝cB<543-4k-j>
tx_out<32k+8j+1>＝cA<543-4k-j>
tx_out<32k+8j+2>＝cH<543-4k-j>
tx_out<32k+8j+3>＝cG<543-4k-j>
tx_out<32k+8j+4>＝cF<543-4k-j>
tx_out<32k+8j+5>＝cE<543-4k-j>
tx_out<32k+8j+6>＝cD<543-4k-j>
tx_out<32k+8j+7>＝cC<543-4k-j>
else if(k％8＝＝6)
tx_out<32k+8j>＝cD<543-4k-j>
tx_out<32k+8j+1>＝cC<543-4k-j>
tx_out<32k+8j+2>＝cB<543-4k-j>
tx_out<32k+8j+3>＝cA<543-4k-j>
tx_out<32k+8j+4>＝cH<543-4k-j>
tx_out<32k+8j+5>＝cG<543-4k-j>
tx_out<32k+8j+6>＝cF<543-4k-j>
tx_out<32k+8j+7>＝cE<543-4k-j>
else if(k％8＝＝7)
tx_out<32k+8j>＝cF<543-4k-j>
tx_out<32k+8j+1>＝cE<543-4k-j>
tx_out<32k+8j+2>＝cD<543-4k-j>
tx_out<32k+8j+3>＝cC<543-4k-j>
tx_out<32k+8j+4>＝cB<543-4k-j>
tx_out<32k+8j+5>＝cA<543-4k-j>
tx_out<32k+8j+6>＝cH<543-4k-j>
tx_out<32k+8j+7>＝cG<543-4k-j>
符号分发方式可以使得π e交织深度由2个RS的符号分发增加到8个RS的符号分发，且分发图样由原有标准中的奇偶分发图样改变为到新的分发图样，但是需要每一路PCS层的RS码字的符号相邻近，即保证RS码字A和B的符号相邻，C和D的符号相邻，E和F的符号相邻，G和H的符号相邻。
上述交织完成后，数据流通过PMA通道送入Inner-FEC模块进行内码编码操作，内码编码完成后直接复用PMA原有的数据交织进行π O交织，最终数据在PMD完成数据调制和光电转换，通过MDI接口传送到通信介质完成数据发送。
基于上述描述，一种可能的设计中，本申请实施例提供的以太网的编码方法的流程示意图可以如图12所示。主要流程包括，待编码数据流经过RS编码器进行编码、交织器π e进行交织、Inner-FEC编码器进行编码、以及交织器π o进行交织。π e可以采用原有的轮询分发，也可以采用其他分发或交织方式。当然，各个步骤之间的顺序可以改变，具体可以参考上文对各个实施例的描述，图12为一种方式的示意图。
综上所述，由于100GE、200GE、400GE以太网技术中的RS码字纠错性能有限，即使将200GE、400GE以太网的10-bit的RS符号分发技术应用到下一代以太网编码方案中，这个符号分发实质上为一个弱交织器，性能上还是无法达到下一代以太网BER性能技术指标的要求，必须采用增加系统的OH的办法来提高纠错性能。本申请实施例通过设计了一 种级联Inner-FEC码字，在兼容了IEEE 802.3bj、IEEE802.3bs大部分协议层的基础上，增加了系统的OH。通过架构与编码的联合优化设计，将PCS层编码与PMA层编码解耦，各层编码负责不同的错误类型及错误分布，在系统整体上有一个最优的编码收益，且实现的复杂度最低，时延和资源消耗水平均是一个最优方案。
另外，本申请实施例提供的方法解决了误码类型及误码分布与设计的Inner-FEC码字纠错效率不匹配的问题。在第一FEC码字(RS码字)与第二FEC码字(Inner-FEC)之间的交织，是将Inner-FEC之后残余的误码能够聚集到一个RS的符号(10-bit)中，使得RS与Inner-FEC之间符号水平的Hamming距离最小，提高RS的纠错效率；而在信道与Inner-FEC之间的交织则是将信道的Burst Error做一定程度的减小，使得Burst Error长度在Inner-FEC可纠范围之内，提高Inner-FEC的纠错效率。
从而，本申请实施例提供的方案能够达到满足下一代以太网性能指标前提下，时延、计算复杂度、资源消耗以及系统兼容性等各项技术指标能够达到一个综合最优效果。
基于与上述以太网的编码方法相同的技术构思，如图13所示，本申请实施例还提供了一种以太网的编码装置1300，该装置1300具有实现上述以太网的编码方法的功能。功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的模块。一种设计中，该装置1300可以包括获取模块1301和处理模块1302。
示例性地：
获取模块1301，用于获取第一待编码信息；处理模块1302，用于采用第一前向纠错码FEC码字对第一待编码信息进行编码，获得第一编码数据，第一前向纠错码FEC码字为里德所罗门前向纠错码RS-FEC；处理模块1302，还用于采用第二FEC码字对第一编码数据进行编码，获得第二编码数据；第二FEC码字的码长N和信息位长度K符合以下公式：
Figure PCTCN2021101722-appb-000031
其中，M1为第一编码数据的吞吐率，M2为第二编码数据的吞吐率。
可选的，在采用第一FEC码字对第一待编码信息进行FEC编码，获得第一编码数据时，处理模块1302用于：采用y个第一FEC码字对第一待编码信息进行FEC编码，获得y组编码数据，y为大于或等于2的偶数；对y组编码数据进行第一交织，获得第一编码数据；第一交织符合行列数分别为L和P的交织矩阵，L和P为大于等于2的偶数，P为物理介质接入子层PMA通道的数目。
可选的，交织矩阵的一行中的行元素，分别对应于从y组编码数据中轮询获取的数据。
可选的，L行的每一行采取相同的轮询规则；或者，L行中每连续y行的轮询规则均不相同。
可选的，在采用第二FEC码字对第一编码数据进行编码时，处理模块1302用于：通过P个PMA通道传输第一编码数据；对P个PMA通道传输的第一编码数据进行编码。
可选的，处理模块1302还用于：通过P个PMA通道传输第二编码数据，对P个PMA通道传输的第二编码数据进行处理。
可选的，在对y组编码数据进行第一交织时，处理模块1302用于：通过P个PMA通道传输y组编码数据；对P个PMA通道传输的y组编码数据进行第一交织。
可选的，P个PMA通道对应序号为0～(P-1)，交织矩阵的P列分别与来自P个PMA通道的编码数据一一对应；交织矩阵的一行中列序号为奇数的行元素，分别对应于序号为0～(P/2-1)的PMA通道的编码数据；交织矩阵的一行中列序号为偶数的行元素，分别对 应于序号为P/2～P的PMA通道的编码数据。
可选的，P的取值包括16或32。
可选的，K还满足以下条件：
Figure PCTCN2021101722-appb-000032
为正整数，N1为第一FEC码字的码长。
可选的，N和K还满足以下条件：
Figure PCTCN2021101722-appb-000033
参考时钟*W，W为正整数。
可选的，W＝4*参考时钟倍频因子RCM。
可选的，M1＝106.25Gbps，M2＝114Gbps。
可选的，
Figure PCTCN2021101722-appb-000034
第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为所述第二FEC码字所在伽罗华域的阶数；所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：汉明码Hamming(144,136,8)、Hamming(180,170,10)、扩展汉明码eHamming(180,170,9)、双扩展汉明码DE-Hamming(180,170,8)、BCH(360,340,10)、双扩展BCH码DE-BCH(360,340,9)、DE-BCH(576,544,10)、或BCH(594,561,11)、或Hamming(180,170,10)。
可选的，第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为该FEC码字所在伽罗华域的阶数；所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：Hamming(126,119,7)、Hamming(127,119,8)、Hamming(145,136,9)、Hamming(179,170,9)、eHamming(127,119,7)、eHamming(145,136,8)、eHamming(179,170,8)、eHamming(181,170,10)、BCH(290,272,9)、BCH(358,340,9)、BCH(574,544,10)、扩展BCH码eBCH(291,272,9)、eBCH(359,340,9)、eBCH(361,340,10)、eBCH(575,544,10)、或DE-BCH(362,340,10)。
可选的，处理模块1302还用于：对第二编码数据进行以下一项或多项处理：通过P个PMA通道传输、第二交织、数据调制、或光电转换；P为大于或等于2的偶数；装置还包括，通信模块1303，用于向接收设备发送处理后的数据。
可选的，N＝x*n，K＝x*k，其中，x、n和k为正整数。
如图14所示，本申请实施例中还提供一种以太网的编码装置1400，该以太网的编码装置1400可以用于执行上述以太网的编码方法。上述以太网的编码方法中的部分或全部可以通过硬件来实现也可以通过软件来实现，当通过硬件实现时，以太网的编码装置1400包括：输入接口电路1401，用于获取第一待编码信息；逻辑电路1402，用于执行上述以太网的编码方法，具体请见前面方法实施例中的描述，此处不再赘述；输出接口电路1403，用于输出第二编码数据。
可选的，以太网的编码装置1400在具体实现时可以是芯片或者集成电路。
可选的，当上述实施例的以太网的编码方法中的部分或全部通过软件来实现时，如图15所示，以太网的编码装置1400包括：存储器1501，用于存储程序；处理器1502，用于执行存储器1501存储的程序，当程序被执行时，使得以太网的编码装置900可以实现上述实施例提供的以太网的编码方法。
可选的，上述存储器1501可以是物理上独立的单元，也可以存储器1501与处理器1502集成在一起。
可选的，当上述以太网的编码方法中的部分或全部通过软件实现时，以太网的编码装 置1400也可以只包括处理器1502。用于存储程序的存储器1501位于以太网的编码装置1400之外，处理器1502通过电路/电线与存储器1501连接，用于读取并执行存储器1501中存储的程序。
处理器1502可以是中央处理器(central processing unit，CPU)，网络处理器(network processor，NP)或者CPU和NP的组合。
处理器1502还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic,GAL)或其任意组合。
存储器1501可以包括易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；存储器1501也可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器1501还可以包括上述种类的存储器的组合。
以太网的编码装置1400还可以是芯片、集成电路或者芯片系统。
本申请实施例还可提供一种芯片，包括处理器，用于支持该以太网的编码装置1400实现上述方法实施例中所涉及的功能。在一种可能的设计中，该芯片与存储器连接或者该芯片包括存储器，该存储器用于保存该以太网的编码装置1400必要的程序指令和数据。
本申请实施例提供了一种计算机可读存储介质，存储有计算机程序，该计算机程序包括用于执行上述方法实施例的指令。
本申请实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得上述方法实施例被实现。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他 可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (39)

  1. 一种以太网的编码方法，其特征在于，包括：
    发送端采用第一前向纠错码FEC码字对第一待编码信息进行编码，获得第一编码数据，所述第一FEC码字为里德所罗门前向纠错码RS-FEC；
    所述发送端采用第二FEC码字对所述第一编码数据进行编码，获得第二编码数据；所述第二FEC码字的码长N和信息位长度K符合以下公式：
    Figure PCTCN2021101722-appb-100001
    其中，所述M1为所述第一编码数据的吞吐率，所述M2为所述第二编码数据的吞吐率。
  2. 如权利要求1所述的方法，其特征在于，所述发送端采用第一FEC码字对第一待编码信息进行FEC编码，获得第一编码数据，包括：
    所述发送端采用y个第一FEC码字对所述第一待编码信息进行FEC编码，获得y组编码数据，所述y为大于或等于2的偶数；
    所述发送端对所述y组编码数据进行第一交织，获得所述第一编码数据；所述第一交织符合行列数分别为L和P的交织矩阵，所述L和所述P为大于等于2的偶数，所述P为物理介质接入子层PMA通道的数目。
  3. 如权利要求2所述的方法，其特征在于，所述交织矩阵的一行中的行元素，分别对应于从所述y组编码数据中轮询获取的数据。
  4. 如权利要求3所述的方法，其特征在于，所述L行的每一行采取相同的轮询规则；或者，所述L行中每连续y行的轮询规则均不相同。
  5. 如权利要求2～4任一项所述的方法，其特征在于，所述发送端采用第二FEC码字对所述第一编码数据进行编码，包括：
    所述发送端通过P个PMA通道传输所述第一编码数据；
    对所述P个PMA通道传输的所述第一编码数据进行编码。
  6. 如权利要求2～4任一项所述的方法，其特征在于，所述方法还包括：
    所述发送端通过P个PMA通道传输所述第二编码数据，对所述P个PMA通道传输的所述第二编码数据进行处理。
  7. 如权利要求2所述的方法，其特征在于，所述发送端对所述y组编码数据进行第一交织，包括：
    所述发送端通过P个PMA通道传输所述y组编码数据；
    对所述P个PMA通道传输的所述y组编码数据进行所述第一交织。
  8. 如权利要求7所述的方法，其特征在于，所述P个PMA通道对应序号为0～(P-1)，所述交织矩阵的P列分别与来自P个PMA通道的编码数据一一对应；所述交织矩阵的一行中列序号为奇数的行元素，分别对应于序号为0～(P/2-1)的PMA通道的编码数据；所述交织矩阵的一行中列序号为偶数的行元素，分别对应于序号为P/2～P的PMA通道的编码数据。
  9. 如权利要求2～8任一项所述的方法，其特征在于，所述P的取值包括16或32。
  10. 如权利要求1～9任一项所述的方法，其特征在于，所述K还满足以下条件：
    Figure PCTCN2021101722-appb-100002
    为正整数，N1为所述第一FEC码字的码长。
  11. 如权利要求1～10任一项所述的方法，其特征在于，所述N和所述K还满足以下条件：
    Figure PCTCN2021101722-appb-100003
    W为正整数。
  12. 如权利要求1～11任一项所述的方法，其特征在于，所述M1＝106.25Gbps，所述 M2＝114Gbps。
  13. 如权利要求1～12任一项所述的方法，其特征在于，
    Figure PCTCN2021101722-appb-100004
  14. 如权利要求1～13任一项所述的方法，其特征在于，第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为所述第二FEC码字所在伽罗华域的阶数；
    所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：汉明码Hamming(144,136,8)、Hamming(180,170,10)、扩展汉明码eHamming(180,170,9)、双扩展汉明码DE-Hamming(180,170,8)、BCH(360,340,10)、双扩展BCH码DE-BCH(360,340,9)、DE-BCH(576,544,10)、或BCH(594,561,11)、或Hamming(180,170,10)。
  15. 如权利要求1～12任一项所述的方法，其特征在于，第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为该FEC码字所在伽罗华域的阶数；
    所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：Hamming(126,119,7)、Hamming(127,119,8)、Hamming(145,136,9)、Hamming(179,170,9)、eHamming(127,119,7)、eHamming(145,136,8)、eHamming(179,170,8)、eHamming(181,170,10)、BCH(290,272,9)、BCH(358,340,9)、BCH(574,544,10)、扩展BCH码eBCH(291,272,9)、eBCH(359,340,9)、eBCH(361,340,10)、eBCH(575,544,10)、或DE-BCH(362,340,10)。
  16. 如权利要求1～15任一项所述的方法，其特征在于，所述方法还包括：
    所述发送端对所述第二编码数据进行以下一项或多项处理：通过P个PMA通道传输、第二交织、数据调制、或光电转换；所述P为大于或等于2的偶数；
    所述发送端向接收设备发送处理后的数据。
  17. 如权利要求1～16任一项所述的方法，其特征在于，N＝x*n，K＝x*k，其中，x、n和k为正整数。
  18. 一种以太网的编码装置，其特征在于，包括：
    获取模块，用于获取第一待编码信息；
    处理模块，用于采用第一前向纠错码FEC码字对第一待编码信息进行编码，获得第一编码数据，所述第一前向纠错码FEC码字为里德所罗门前向纠错码RS-FEC；
    所述处理模块，还用于采用第二FEC码字对所述第一编码数据进行编码，获得第二编码数据；所述第二FEC码字的码长N和信息位长度K符合以下公式：
    Figure PCTCN2021101722-appb-100005
    其中，所述M1为所述第一编码数据的吞吐率，所述M2为所述第二编码数据的吞吐率。
  19. 如权利要求18所述的装置，其特征在于，在采用第一FEC码字对第一待编码信息进行FEC编码，获得第一编码数据时，所述处理模块用于：
    采用y个第一FEC码字对所述第一待编码信息进行FEC编码，获得y组编码数据，所述y为大于或等于2的偶数；
    对所述y组编码数据进行第一交织，获得所述第一编码数据；所述第一交织符合行列数分别为L和P的交织矩阵，所述L和所述P为大于等于2的偶数，所述P为物理介质接入子层PMA通道的数目。
  20. 如权利要求19所述的装置，其特征在于，所述交织矩阵的一行中的行元素，分别 对应于从所述y组编码数据中轮询获取的数据。
  21. 如权利要求20所述的装置，其特征在于，所述L行的每一行采取相同的轮询规则；或者，所述L行中每连续y行的轮询规则均不相同。
  22. 如权利要求19～21任一项所述的装置，其特征在于，在采用第二FEC码字对所述第一编码数据进行编码时，所述处理模块用于：
    通过P个PMA通道传输所述第一编码数据；
    对所述P个PMA通道传输的所述第一编码数据进行编码。
  23. 如权利要求19～21任一项所述的装置，其特征在于，所述处理模块还用于：
    通过P个PMA通道传输所述第二编码数据，对所述P个PMA通道传输的所述第二编码数据进行处理。
  24. 如权利要求19所述的装置，其特征在于，在对所述y组编码数据进行第一交织时，所述处理模块用于：
    通过P个PMA通道传输所述y组编码数据；
    对所述P个PMA通道传输的所述y组编码数据进行所述第一交织。
  25. 如权利要求24所述的装置，其特征在于，所述P个PMA通道对应序号为0～(P-1)，所述交织矩阵的P列分别与来自P个PMA通道的编码数据一一对应；所述交织矩阵的一行中列序号为奇数的行元素，分别对应于序号为0～(P/2-1)的PMA通道的编码数据；所述交织矩阵的一行中列序号为偶数的行元素，分别对应于序号为P/2～P的PMA通道的编码数据。
  26. 如权利要求19～24任一项所述的装置，其特征在于，所述P的取值包括16或32。
  27. 如权利要求18～26任一项所述的装置，其特征在于，所述K还满足以下条件：
    Figure PCTCN2021101722-appb-100006
    为正整数，N1为所述第一FEC码字的码长。
  28. 如权利要求18～27任一项所述的装置，其特征在于，所述N和所述K还满足以下条件：
    Figure PCTCN2021101722-appb-100007
    W为正整数。
  29. 如权利要求18～28任一项所述的装置，其特征在于，所述M1＝106.25Gbps，所述M2＝114Gbps。
  30. 如权利要求18～29任一项所述的装置，其特征在于，
    Figure PCTCN2021101722-appb-100008
  31. 如权利要求18～30任一项所述的装置，其特征在于，第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为所述第二FEC码字所在伽罗华域的阶数；
    所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：汉明码Hamming(144,136,8)、Hamming(180,170,10)、扩展汉明码eHamming(180,170,9)、双扩展汉明码DE-Hamming(180,170,8)、BCH(360,340,10)、双扩展BCH码DE-BCH(360,340,9)、DE-BCH(576,544,10)、或BCH(594,561,11)、或Hamming(180,170,10)。
  32. 如权利要求18～29任一项所述的装置，其特征在于，第二FEC码字的构造为(N，K，m)，所述N为所述第二FEC码字的码长所包含的比特数，所述K为所述信息位所包含的比特数，所述m为该FEC码字所在伽罗华域的阶数；
    所述第二FEC码字包括以下任意一种码字，或者包括以下任意一种码字为子码而构造的空间耦合码，或者包括以下任意一种码字为子码而构造的多层码：Hamming(126,119,7)、 Hamming(127,119,8)、Hamming(145,136,9)、Hamming(179,170,9)、eHamming(127,119,7)、eHamming(145,136,8)、eHamming(179,170,8)、eHamming(181,170,10)、BCH(290,272,9)、BCH(358,340,9)、BCH(574,544,10)、扩展BCH码eBCH(291,272,9)、eBCH(359,340,9)、eBCH(361,340,10)、eBCH(575,544,10)、或DE-BCH(362,340,10)。
  33. 如权利要求18～32任一项所述的装置，其特征在于，所述处理模块还用于：
    对所述第二编码数据进行以下一项或多项处理：通过P个PMA通道传输、第二交织、数据调制、或光电转换；所述P为大于或等于2的偶数；
    所述装置还包括，通信模块，用于向接收设备发送处理后的数据。
  34. 如权利要求18～33任一项所述的装置，其特征在于，N＝x*n，K＝x*k，其中，x、n和k为正整数。
  35. 一种以太网的编码装置，其特征在于，包括：
    输入接口电路，用于获取第一待编码信息；
    逻辑电路，用于基于获取的第一待编码信息执行所述权利要求1～17任一项所述的方法，得到第二编码数据；
    输出接口电路，用于输出第二编码数据。
  36. 一种以太网的编码装置，其特征在于，包括：
    存储器，用于存储程序或指令；
    处理器，用于执行所述存储器存储的所述程序或指令，以使得如权利要求1～17任一项所述的方法被执行。
  37. 如权利要求36所述的装置，其特征在于，所述处理器包括所述存储器，或者，所述处理器与所述存储器耦合。
  38. 如权利要求36或37所述的装置，其特征在于，所述以太网的编码装置为芯片或集成电路。
  39. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机可读指令，当所述计算机可读指令在以太网的编码装置上运行时，使得所述以太网的编码装置执行权利要求1～17任一项所述的方法。
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