WO2022088876A1 - 通信数据的处理方法、装置、设备及存储介质 - Google Patents

通信数据的处理方法、装置、设备及存储介质 Download PDF

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WO2022088876A1
WO2022088876A1 PCT/CN2021/114111 CN2021114111W WO2022088876A1 WO 2022088876 A1 WO2022088876 A1 WO 2022088876A1 CN 2021114111 W CN2021114111 W CN 2021114111W WO 2022088876 A1 WO2022088876 A1 WO 2022088876A1
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bit
address
code length
weight
check
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French (fr)
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张斌
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ZTE Corp
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ZTE Corp
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Priority to EP21884608.7A priority patent/EP4236129A4/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a method, apparatus, device, and storage medium for processing communication data.
  • the row weight is the number of 1s in each row of the G matrix.
  • the traditional method is to count the number of 1s in the G matrix and store them in advance.
  • When calculating the polar coding comparison line weight read out the pre-stored line weight for comparison. This approach requires pre-stored row weight information.
  • the traditional method of rate matching is to implement the order of sub-block interleaving, bit selection, and bit interleaving. Between bit selection and sub-block interleaving, ram needs to be used to store the bit-selected data. This approach uses more ram, and parallel implementation is not flexible enough.
  • An embodiment of the present application provides a method for processing communication data, including: determining a bit pattern according to a coding parameter; mapping the bit pattern according to the communication data to be encoded and the check bit to obtain an initial bit sequence; respectively perform operations with a preset matrix to obtain a target bit sequence; generate a bit index based on the transmission rate, and select bit data from the target bit sequence for transmission according to the bit index.
  • An embodiment of the present application provides a communication data processing device, including: a bit pattern determination module, configured to determine a bit pattern according to coding parameters; an initial bit sequence acquisition module, used to map the bit pattern according to the communication data to be encoded and the check bits , to obtain the initial bit sequence; the target bit sequence acquisition module is used to obtain the target bit sequence by operating multiple subsequences in the initial bit sequence with the preset matrix respectively; the data selection module is used to generate the bit index based on the transmission rate, according to the bit The index selects bit data from the target bit sequence for transmission.
  • Embodiments of the present application provide a computer device, including a memory, a processor, and a computer program stored in the memory and running on the processor.
  • the processor executes the program, the method for processing communication data according to the embodiments of the present application is implemented.
  • the embodiments of the present application provide a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, implements the method for processing communication data according to the embodiments of the present application.
  • FIG. 1 is a diagram showing the relationship between the front and rear stages of polar coding and rate matching in uplink UCI information processing provided according to an embodiment of the present application;
  • FIG. 2 is a flowchart of a method for processing communication data provided according to an embodiment of the present application
  • FIG. 3 is an example diagram of a G matrix element provided according to an embodiment of the present application.
  • FIG. 4 is an example diagram of a matrix addition operation provided according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an apparatus for processing communication data provided according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a computer device provided according to an embodiment of the present application.
  • Polar coding is an encoding method for uplink control information (Uplink Control Information, UCI information) introduced in the 5G protocol.
  • UCI information Uplink Control Information
  • the row weight is the number of 1s in each row of the G matrix.
  • the traditional method is to count the number of 1s in the G matrix and store them in advance.
  • the polar coding comparison line weight read out the pre-stored line weight for comparison. This approach requires pre-stored row weight information.
  • the traditional method of rate matching is to implement the order of sub-block interleaving, bit selection, and bit interleaving. Between bit selection and sub-block interleaving, ram needs to be used to store the bit-selected data. This approach uses more ram, and parallel implementation is not flexible enough.
  • Embodiments of the present application provide a communication data processing method, apparatus, device, and storage medium, so as to realize polar coding and rate matching of communication data, and can improve the processing rate of communication data.
  • inventions of this application protect the process of polar coding and rate matching in UCI information processing in the 3GPP 5G NR physical layer protocol.
  • Figure 1 shows the relationship between polar coding and rate matching in UCI information processing.
  • FIG. 2 is a flowchart of a method for processing communication data provided by an embodiment of the present application.
  • the method may be applicable to the case of processing communication data, wherein the communication data may be physical uplink control information UCI.
  • the method can be executed by the interrupt processing device of the data. As shown in FIG. 2, the method includes S110-S140.
  • the encoding parameters may include the first code length and the address weight.
  • the first code length can be understood as the code length of the sequence after polar coding, that is, the code length of the target bit sequence; the address weight can be obtained from the weight table.
  • the bit pattern can be understood as a bit sequence, and it can be determined whether to add the communication data to be encoded or the check bit to be added to the bit by each bit value and bit index in the bit sequence.
  • the manner of determining the bit pattern according to the encoding parameter may be: determining the address segment according to the first code length, and obtaining the address weight of each address in the address segment; for each address, de-sub-blocking the address weight Interleaving operation to determine whether the address is a punching position or a shortening position; if so, set the bit value of the address to 0; otherwise, set the bit value of the address to 1, and add 1 to the number of valid bits; when there is a check bit, according to The line weight and/or number of valid bits of the address determines whether the address is a check bit; if so, the address weight is recorded as the check index.
  • the first code length N may be determined according to coding requirements, and may be 32, 64, 128, 256, 512, and 1024.
  • the address segment and the address weight Q of each address in the address segment may be determined by looking up a table. Table 1 shows the correspondence between the first code length and the address segment.
  • a plurality of address weights are extracted from the protocol table according to the first code length N, and the address weights are sequentially stored in the ROM address range shown in Table 1 according to the order from small to large.
  • performing a desubblock interleaving operation on the address weight to determine whether the address is a punching position or a shortening position may be: converting the address weight into a ten-digit binary code; The number of digits is intercepted to obtain the first value; the second value is obtained by looking up the table according to the first value; the third value is obtained by calculating according to the second value and the first code length; Accumulate to obtain a fourth value; according to the fourth value, determine whether the address is a punching position or a shortening position.
  • the ten-digit binary code is truncated according to the manner in Table 2.
  • the ten-digit binary code is j_n
  • the truncated first value is p_i.
  • j_n[9:1] indicates that the values of the 1st to 9th bits in j_n are reserved.
  • the first code length is 1024
  • the ten-digit binary code j_n is 0100010101
  • the binary code of the first value is 01000
  • the first value is 16.
  • the second value obtained by looking up the table according to the first value may be obtained according to Table 3.
  • the address is a punching position or a shortening position according to the protocol.
  • the encoding parameter further includes a second code length, and the second code length is the code length of the communication data to be encoded; the process of determining whether the address is a check bit according to the line weight and/or the number of valid bits of the address may be: If there is a set check bit, when the number of valid bits is less than or equal to the second code length, determine whether the line weight of the address is the smallest among the recorded line weights, and if so, record the address weight as the first check index ; When the number of valid bits is the second code length plus 2, the address weight is recorded as the second check index; When the number of valid bits is the second code length plus 3, the address weight is recorded as the third check index; If There is no set check bit.
  • the address weight is recorded as the first check index; when the number of valid bits is the second code length plus 2, the address weight is recorded as The second check index; when the number of valid bits is the second code length plus 3, the address weight is recorded as the third check index.
  • the row weight of an address can be represented by the number of 1s included in the address index.
  • the advantage of doing this is that there is no need to count the number of 1s in the G matrix to determine the row weight, which can greatly reduce the amount of computation.
  • the set check bit may be pcwm bit. Specifically, when there is a pcwm bit, when the number of valid bits is less than or equal to the second code length K, compare the line weight W corresponding to the address with the recorded line weight W_min, if W is less than W_min, then register the address weight Q in pc_bit_index0 . When the number of effective bits is K+2 and K+3, the Q value is stored in pc_bit_index1 and pc_bit_index2 respectively.
  • S120 Obtain an initial bit sequence according to the communication data to be encoded and the check bit mapping bit pattern.
  • the communication data to be encoded or the check index is selected from the data to be encoded or the check index.
  • the selected bit data is added to the corresponding address.
  • the process of obtaining the initial bit sequence may be: sequentially extracting bits in each address from the bit pattern, and if the weight value corresponding to the address is the check index, then The selected check bit is added to the address; if the bit value is 1 and the weight value corresponding to the address is not the check index, select bit data from the communication data to be encoded in order and add it to the address.
  • S130 Perform operations on multiple subsequences in the initial bit sequence with a preset matrix, respectively, to obtain a target bit sequence.
  • the number of bits included in each subsequence may be preset, such as 16 bits, 32 bits, and 64 bits. Taking the subsequence containing 32 bits as an example, Table 5 shows the relationship between the first code length N and the number of subsequences.
  • N 32 64 128 256 512 1024 number of subsequences 1 2 4 8 16 32
  • the preset matrix may be a G matrix.
  • the manner of performing operations on the multiple subsequences in the initial bit sequence and the preset matrix respectively may be: dividing the initial bit sequence into multiple subsequences, and multiplying the multiple subsequences with the preset matrix respectively; The multiple subsequences of , perform multi-stage addition operations according to the set method.
  • FIG. 3 is an example diagram of G matrix elements in an embodiment of the present application. As shown in Figure 3, the matrix is a 32*32 matrix. Multiply each subsequence with this G matrix.
  • the process of performing a multi-stage addition operation on the multiplied subsequences according to a set manner may be: for each stage of the addition operation, divide the multiple subsequences obtained by the addition operation in the previous stage into two groups. , and establish a one-to-one correspondence between the subsequences between the two groups; add the subsequences with the one-to-one correspondence, and use the sequence obtained after the addition as one of the new subsequences; the subsequence of the other group constant.
  • FIG. 4 is an example diagram of performing matrix addition operation in an embodiment of the present application.
  • the addition operation is divided into 5 stages.
  • the subsequences are divided into black groups and white groups, and the one-to-one correspondence between the subsequences in the black group and the white group is established according to the numbering order of the subsequences.
  • the Mth subsequence of the black group establishes a one-to-one correspondence with the Mth subsequence of the white group.
  • add the subsequences with one-to-one correspondence and replace the subsequence of the black group with the sequence obtained after the addition, and keep the subsequence of the white group unchanged.
  • S140 Generate a bit index based on the transmission rate, and select bit data from the target bit sequence according to the bit index for transmission.
  • the manner of generating the bit index based on the transmission rate may be: performing de-bit interleaving, de-bit selection and de-sub-block interleaving based on the transmission rate to obtain the bit index.
  • the process of de-interleaving can be understood as calculating the bit index before interleaving for each bit index after interleaving according to the bit index relationship before and after interleaving.
  • the number of parallel computing bit indices can be flexibly set according to the parallelism requirement.
  • the process of performing the debit selection processing based on the transmission rate may be: determining a rate matching mode according to the transmission rate and the first code length; and performing the debit selection processing according to the rate matching mode.
  • the input data for debit selection is the index bit_sel_index after bit selection
  • the output data for debit selection is the index pre_bit_sel_index before bit selection
  • the data length after rate matching is Er .
  • pre_bit_sel_index is shown in Table 7:
  • first determine the bit pattern according to the encoding parameters then map the communication data to be encoded into polar encoded input data and add check bits according to the bit pattern to obtain an initial bit sequence, and then divide the bit sequence into For multiple subsequences, matrix multiplication and addition are performed on the multiple subsequences to obtain a target bit sequence, and finally a bit index is generated based on the transmission rate, and bit data is selected from the target bit sequence according to the bit index for transmission.
  • the communication data to be encoded is mapped into polar encoded input data according to the bit pattern and check bits are added to obtain an initial bit sequence, which can improve the efficiency of polar encoding, and the bit sequence is divided into Multiple subsequences, perform matrix multiplication and addition operations on multiple subsequences to obtain the target bit sequence, instead of performing matrix multiplication and addition operations on the entire bit sequence, which can improve the speed of the operation; select bit data from the target bit sequence according to the bit index To achieve rate matching, instead of directly performing rate matching on the target bit sequence, the efficiency of rate matching is improved.
  • FIG. 5 is a schematic structural diagram of an apparatus for processing communication data according to an embodiment of the present application.
  • the apparatus includes: a bit pattern determination module 210 , an initial bit sequence acquisition module 220 , a target bit sequence acquisition module 230 and a data selection module 240 .
  • the bit pattern determination module 210 is configured to determine the bit pattern according to the encoding parameter.
  • the initial bit sequence obtaining module 220 is configured to map the bit pattern according to the communication data to be encoded and the check bits to obtain the initial bit sequence.
  • the target bit sequence acquisition module 230 is configured to perform operations on multiple subsequences in the initial bit sequence with a preset matrix to obtain a target bit sequence.
  • the data selection module 240 is configured to generate a bit index based on the transmission rate, and select bit data from the target bit sequence for transmission according to the bit index.
  • the encoding parameters include a first code length and an address weight; the first code length is the code length of the target bit sequence; the bit pattern determination module 210 is further configured to: determine the address segment according to the first code length, and obtain The address weight of each address in the address segment; for each address, the de-subblock interleaving operation is performed on the address weight to determine whether the address is a punching position or a shortening position; if so, set the bit value of the address to 0; otherwise, set the address The bit value of the address is set to 1, and the number of valid bits is accumulated by 1; when there is a check bit, determine whether the address is a check bit according to the line weight and/or the number of valid bits of the address; if so, record the address weight as the check index .
  • the bit pattern determination module 210 is further configured to: convert the address weight into a ten-digit binary code; perform digit truncation on the ten-digit binary code according to the first code length to obtain a first value; according to the first value Look up the table to obtain the second value; calculate and obtain the third value according to the second value and the first code length; accumulate the third value and the value truncated in the ten-digit binary code to obtain the fourth value; judge the address according to the fourth value Whether it is a punching position or a shortening position.
  • the encoding parameter further includes a second code length, and the second code length is the code length of the communication data to be encoded;
  • the root bit pattern determination module 210 is further configured to: if there is a set check bit, when the valid bit When the number is less than or equal to the second code length, judge whether the line weight of the address is the smallest among the recorded line weights, and if so, record the address weight as the first check index; when the number of valid bits is the second code length plus 2, record the address weight as the second check index; when the number of valid bits is the second code length plus 3, record the address weight as the third check index; if there is no set check bit, when the valid bit When the number is the second code length plus 1, the address weight is recorded as the first check index; when the number of valid bits is the second code length plus 2, the address weight is recorded as the second check index; when the number of valid bits is When the second code length is increased by 3, the address weight is recorded as the third check index.
  • the initial bit sequence obtaining module 220 is further configured to: sequentially extract the bits in each address from the bit pattern, and if the weight value corresponding to the address is a check index, add the selected check bit to the In the address; if the bit value is 1 and the weight value corresponding to the address is not a check index, select bit data from the communication data to be encoded in order and add it to the address.
  • the target bit sequence obtaining module 230 is further configured to: divide the initial bit sequence into multiple subsequences; multiply the multiple subsequences with a preset matrix respectively; multiply the multiple subsequences according to the setting way to perform multi-stage addition operations.
  • the target bit sequence obtaining module 230 is further configured to: for each stage of addition operation, divide the multiple subsequences obtained by the addition operation in the previous stage into two groups, and establish the subsequence between the two groups. One-to-one correspondence; add the subsequences with one-to-one correspondence, and use the sequence obtained after the addition as one of the new subsequences; the subsequences of the other group remain unchanged.
  • the data selection module 240 is further configured to: perform de-bit interleaving, de-bit selection and de-sub-block interleaving processing based on the transmission rate to obtain a bit index.
  • the data selection module 240 is further configured to: determine a rate matching mode according to the transmission rate and the first code length; and perform debit selection processing according to the rate matching mode.
  • FIG. 6 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • the device provided by this application includes: a processor 310 and a memory 320 .
  • the number of processors 310 in the device may be one or more, and one processor 310 is taken as an example in FIG. 6 .
  • the number of memories 320 in the device may be one or more, and one memory 320 is taken as an example in FIG. 6 .
  • the processor 310 and the memory 320 of the device may be connected through a bus or in other ways, and the connection through a bus is taken as an example in FIG. 6 .
  • the device is a computer device.
  • the memory 320 may be configured to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the device in any embodiment of the present application (for example, the coding module and the coding module in the data transmission device). the first sending module).
  • the memory 320 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the device, and the like.
  • memory 320 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device.
  • memory 320 may further include memory located remotely from processor 310, which may be connected to the device through a network.
  • networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the device provided above can be configured to execute the processing method applied to communication data provided by any of the above embodiments, and has corresponding functions and effects.
  • the program stored in the corresponding memory 320 may be a program instruction/module corresponding to the interrupt processing method provided by the embodiment of the present application.
  • One or more functional applications and data processing that is, to implement the associated query method applied to data in the above method embodiments. It can be understood that, when the above-mentioned device is the receiving end, it can execute the interrupt processing method provided by any embodiment of the present application, and has corresponding functions and effects.
  • Embodiments of the present application further provide a storage medium containing computer-executable instructions, where the computer-executable instructions are used to execute a communication data processing method when executed by a computer processor, the method comprising: determining a bit pattern according to an encoding parameter; According to the bit pattern, the communication data to be encoded is mapped to polar encoded input data and check bits are added to obtain the initial bit sequence; the initial bit sequence is divided into multiple subsequences, and matrix multiplication and addition are performed on the multiple subsequences to obtain the target bits sequence; generate a bit index based on the transmission rate, and select bit data from the target bit sequence for transmission according to the bit index.
  • user equipment encompasses any suitable type of wireless user equipment such as a mobile telephone, portable data processing device, portable web browser or vehicle mounted mobile station.
  • the various embodiments of the present application may be implemented in hardware or special purpose circuits, software, logic, or any combination thereof.
  • some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
  • Embodiments of the present application may be implemented by the execution of computer program instructions by a data processor of a mobile device, eg in a processor entity, or by hardware, or by a combination of software and hardware.
  • Computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or written in any combination of one or more programming languages source or object code.
  • ISA Instruction Set Architecture
  • the block diagrams of any logic flow in the figures of the present application may represent program steps, or may represent interconnected logic circuits, modules and functions, or may represent a combination of program steps and logic circuits, modules and functions.
  • Computer programs can be stored on memory.
  • the memory may be of any type suitable for the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, Read-Only Memory (ROM), Random Access Memory (RAM), optical Memory devices and systems (Digital Video Disc (DVD) or Compact Disk (CD)), etc.
  • Computer-readable media may include non-transitory storage media.
  • the data processor may be of any type suitable for the local technical environment, such as, but not limited to, a general purpose computer, a special purpose computer, a microprocessor, a Digital Signal Processing (DSP), an Application Specific Integrated Circuit (ASIC) ), programmable logic devices (Field-Programmable Gate Array, FGPA) and processors based on multi-core processor architecture.
  • DSP Digital Signal Processing
  • ASIC Application Specific Integrated Circuit
  • FGPA programmable logic devices
  • processors based on multi-core processor architecture.
  • Embodiments of the present application may be implemented by the execution of computer program instructions by a data processor of a mobile device, eg in a processor entity, or by hardware, or by a combination of software and hardware.
  • the computer program instructions may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or source code written in any combination of one or more programming languages or destination code.
  • ISA instruction set architecture

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Abstract

本申请实施例公开一种通信数据的处理方法、装置、设备及存储介质。该方法包括：根据编码参数确定比特模式；根据待编码通信数据和校验比特映射比特模式，获得初始比特序列；将初始比特序列中的多个子序列分别与预设矩阵进行运算，获得目标比特序列；基于传输速率生成比特索引，根据比特索引从目标比特序列中选取比特数据进行传输。

Description

通信数据的处理方法、装置、设备及存储介质
交叉引用
本申请基于申请号为“202011156922.3”、申请日为2020年10月26日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及通信技术领域，尤其涉及一种通信数据的处理方法、装置、设备及存储介质。
背景技术
polar编码时需要比较行重，行重即G矩阵的每一行中1的个数。传统的做法是把G矩阵中1的个数统计出来并预先存好。在计算polar编码比较行重时，读出预先存好的行重进行比较。这种做法需要预先存储行重信息。速率匹配传统的做法是按照子块交织、比特选择、比特交织的顺序实现，比特选择和子块交织之间需要使用ram存储比特选择后的数据。这种做法使用的ram较多，并且并行实现不够灵活。
发明内容
本申请实施例提供了一种通信数据的处理方法，包括：根据编码参数确定比特模式；根据待编码通信数据和校验比特映射比特模式，获得初始比特序列；将初始比特序列中的多个子序列分别与预设矩阵进行运算，获得目标比特序列；基于传输速率生成比特索引，根据比特索引从目标比特序列中选取比特数据进行传输。
本申请实施例提供了一种通信数据的处理装置，包括：比特模式确定模块，用于根据编码参数确定比特模式；初始比特序列获取模块，用于根据待编码通信数据和校验比特映射比特模式，获得初始比特序列；目标比特序列获取模块，用于将初始比特序列中的多个子序列分别与预设矩阵进行运算获得目标比特序列；数据选取模块，用于基于传输速率生成比特索引，根据比特索引从目标比特序列中选取比特数据进行传输。
本申请实施例提供了一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，处理器执行程序时实现如本申请实施例的通信数据的处理方法。
本申请实施例提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现如本申请实施例的通信数据的处理方法。
附图说明
图1是根据本申请实施例提供的polar编码和速率匹配在上行UCI信息处理中的前后级关系图；
图2是根据本申请实施例提供的一种通信数据的处理方法的流程图；
图3是根据本申请实施例提供的G矩阵元素示例图；
图4是根据本申请实施例提供的矩阵加法运算的示例图；
图5是根据本申请实施例提供的一种通信数据的处理装置的结构示意图；
图6是根据本申请实施例提供的一种计算机设备的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
在后续的描述中，使用用于表示元件的诸如“模块”、“部件”或“单元”的后缀仅为了有利于本申请的说明，其本身没有特有的意义。因此，“模块”、“部件”或“单元”可以混合地使用。
polar编码是5G协议中引入的对上行控制信息(UplinkControlInformation，UCI信息)的编码方式。polar编码时需要比较行重，行重即G矩阵的每一行中1的个数。传统的做法是把G矩阵中1的个数统计出来并预先存好。在计算polar编码比较行重时，读出预先存好的行重进行比较。这种做法需要预先存储行重信息。速率匹配传统的做法是按照子块交织、比特选择、比特交织的顺序实现，比特选择和子块交织之间需要使用ram存储比特选择后的数据。这种做法使用的ram较多，并且并行实现不够灵活。
本申请实施例提供了一种通信数据的处理方法、装置、设备及存储介质，以实现对通信数据的polar编码及速率匹配，可以提高通信数据的处理速率。
本申请实施例保护3GPP 5G NR物理层协议中对UCI信息处理中polar编码和速率匹配的过程。图1为polar编码和速率匹配在UCI信息处理中的前后级关系。
在一个实施例中，图2为本申请实施例提供的一种通信数据的处理方法的流程图。该方法可以适用对通信数据进行处理的情况，其中，通信数据可以是物理上行控制信息UCI。该方法可以由数据的中断处理装置了执行。如图2所示，该方法包括S110-S140。
S110，根据编码参数确定比特模式。
其中，编码参数可以包括第一码长和地址权重。第一码长可以理解为polar编码后的序列码长即目标比特序列的码长；地址权重可以由权重表获得。比特模式可以理解为一比特序列，通过比特序列中的各比特值及比特索引可以确定该比特位上添加待编码通信数据还是添加校验比特。
在一个实施例中，根据编码参数确定比特模式的方式可以是：根据第一码长确定地址段，并获取地址段中每个地址的地址权重；对于每个地址，对地址权重进行解子块交织运算以判断地址是否为打孔位置或者缩短位置；若是，则将地址的比特值置0；否则将地址的比特值置1，且将有效比特数累加1；当存在校验比特时，根据地址的行重和/或有效比特数确定地址是否为检验位；若是，则将地址权重记录为校验索引。
其中，第一码长N可以根据编码需求确定，可以是32、64、128、256、512及1024。本实施例中可以通过查表的方式确定地址段及地址段中每个地址的地址权重Q。表1为第一码长与地址段的对应关系。
表1
N ROM地址
1024 0～1023
512 1024～1535
256 1536～1791
128 1792～1919
64 1920～1983
32 1984～2015
本实施例中，根据第一码长N从协议表格中抽取多个地址权重，按照由小到大的顺序，把地址权重依次存储在表1所示的ROM地址范围内。
可选的，对地址权重进行解子块交织运算以判断地址是否为打孔位置或者缩短位置的方式可以是：将地址权重转化为十位二进制码；根据第一码长对十位二进制码进行位数截取，获得第一值；根据第一值查表获得第二值；根据第二值和第一码长计算获得第三值；将第三值与十位二进制码中截取掉的值进行累加，获得第四值；根据第四值判断地址是否为打孔位置或者缩短位置。
具体的，根据第一码长对十位二进制码进行位数截取按照表2的方式进行截取。
表2
N/32 1 2 4 8 16 32
p_i j_n j_n[9:1] j_n[9:2] j_n[9:3] j_n[9:4] j_n[9:5]
如表2所示，十位二进制码为j_n，截取后的第一值为p_i。其中，j_n[9:1]表示保留j_n中第1位到第9位的值。示例性的，假设第一码长为1024，十位二进制码j_n为0100010101，那么p_i＝j_i[9:5],即保留第5位到第9位的值，则第一值的二进制码为01000，第一值为16。
具体的，根据第一值查表获得第二值可以根据表3获得。
表3
p_i i
0,1,2 p_i
3 4
4 3
5,6,7,8 p_i
9 10
10 12
11 14
12 16
13 18
14 20
15 22
16 9
17 11
18 13
19 15
20 17
21 19
22 21
23,24,25,26 p_i
27 28
28 27
29,30,31 p_i
由表3可以获得，第一值p_i和第二值i具有对应关系。假设第一值为16，那么第二值为9。
具体的，根据第二值和第一码长计算获得第三值可由如下公式计算：d＝i*N/32，其中，d为第三值，i为第二值，N为第一码长。假设第二值为9，那么第三值为9*32。
具体的，将第三值与十位二进制码中截取掉的值进行累加获得第四值可以通过表4实现。如表4所示，假设第一码长为1024，十位二进制码j_n为0100010101，那么截取掉的值为j_i[4:0]＝10101,转化为十进制为21，那么第四值为9*32+21。
表4
N/32 1 2 4 8 16 32
n n’ n’+j_n[0] n’+j_n[1:0] n’+j_n[2:0] n’+j_n[3:0] n’+j_n[4:0]
本实施例中，在获得第四值后，可以根据协议规定确定该地址是否为打孔位置或者缩短位置。
在一个实施例中，编码参数还包括第二码长，第二码长为待编码通信数据的码长；根据地址的行重和/或有效比特数确定地址是否为检验位的过程可以是：若存在设定校验比特，当有效比特数小于或者等于第二码长时，判断地址的行重是否是已记录的行重中最小的，若是，则将地址权重记录为第一校验索引；当有效比特数为第二码长加2时，将地址权重记录为第二校验索引；当有效比特数为第二码长加3时，将地址权重记录为第三校验索引；若不存在设定校验比特，当有效比特数为第二码长加1时，将地址权重记录为第一校验索引；当有效比特数为第二码长加2时，将地址权重记录为第二校验索引；当有效比特数为第二码长加3时，将地址权重记录为第三校验索引。
本实施例中，地址的行重可以由地址索引中包含的1的个数来表征。这样的做的好处是无需统计G矩阵中1的个数统来确定行重，可以极大的减小运算量。
其中，设定校验比特可以是pcwm bit。具体的，有pcwm bit时，有效比特数小于等于第二码长K时，比较该地址对应的行重W和已记录的行重W_min，如果W小于W_min，则把地址权重Q寄存到pc_bit_index0中。当有效比特数为K+2和K+3时，把Q值分别存入pc_bit_index1、pc_bit_index2。无pcwm bit时，有效比特数为K+1、K+2和K+3时，把Q值分别存入pc_bit_index0、pc_bit_index1、pc_bit_index2。最终bit_pattern中为1的位置，即为可以映射待编码通信数据的位置；pc_bit_index0、pc_bit_index1、pc_bit_index2为映射校验比特的位置。
S120，根据待编码通信数据和校验比特映射比特模式，获得初始比特序列。
具体的，按照索引从小到大的顺序，每次从比特模式中取4个比特，根据取出的比特值是否为1以及比特地址的权重值是否等于校验索引，从待编码通信数据或校验比特中选取比特数据添加至对应的地址中。
具体的，根据待编码通信数据和校验比特映射比特模式，获得初始比特序列的过程可以是：从比特模式中依次提取各地址中的比特，若地址对应的权重值为校验索引，则将选择的校验比特添加至该地址中；若比特值为1且地址对应的权重值不是校验索引，则按照顺序从待编码通信数据中选择比特数据添加至该地址。
S130，将初始比特序列中的多个子序列分别与预设矩阵进行运算，获得目标比特序列。
其中，每个子序列中包含的比特数可以预先设定，如可以是16比特、32比特及64比特等。以子序列包含32比特为例，表5为第一码长N与子序列数量的关系。
表5
N 32 64 128 256 512 1024
子序列数量 1 2 4 8 16 32
在进行矩阵乘法及加法时，以子序列为单位进行乘法和加法运算。
其中，预设矩阵可以是G矩阵。具体的，将初始比特序列中的多个子序列分别与预设矩阵进行运算的方式可以是：将初始比特序列划分为多个子序列，将多个子序列分别与预设矩阵相乘；将相乘后的多个子序列按照设定方式进行多阶段的加法运算。
建立子序列的编号，表6示出了编号与原始比特序列的对应关系。
表6
编号 U0 U1 U2 …… U31
初始比特序列 u[31:0] U[63:32] U[95:64] …… U[1023:992]
图3为本申请实施例中的G矩阵元素示例图。如图3所示，该矩阵为32*32的矩阵。将每个子序列与该G矩阵进行相乘。
具体的，将相乘后的多个子序列按照设定方式进行多阶段的加法运算的过程可以是：对于每一阶段的加法运算，将上一阶段加法运算获得的多个子序列均分为两组，并建立两组间子序列的一一对应关系；将具有一一对应关系的子序列进行加法运算，并将加法运算后获得的序列作为其中一组新的子序列；另一组的子序列保持不变。
示例性的，图4为本申请实施例进行矩阵加法运算的示例图。如图4所示，加法运算分为5个阶段，每个阶段将子序列分为黑色组和白色组，并按照子序列的编号顺序建立黑色组和白色组中子序列的一一对应关系，例如：黑色组的第M个子序列与白色组的第M个子序列建立一一对应关系。然后将具有一一对应关系的子序列进行加法运算，并将加法运算后获得的序列替换黑色组的子序列，白色组的子序列保持不变。
S140，基于传输速率生成比特索引，根据比特索引从目标比特序列中选取比特数据进行传输。
基于传输速率生成比特索引的方式可以是：基于传输速率进行解比特交织、解比特选择和解子块交织处理，获得比特索引。
其中，解比特交织的过程可以理解为根据交织前后的比特索引关系，针对每一个交织后的比特索引，计算其交织前的比特索引。本申请实施例中，可以根据并行度需求，灵活设置并行计算比特索引的个数。
基于传输速率进行解比特选择处理的过程可以是：根据传输速率及第一码长确定速率匹配模式；根据速率匹配模式进行解比特选择处理。
具体的，解比特选择的输入数据为比特选择后的索引bit_sel_index，解比特选择的输出数据为比特选择前的索引pre_bit_sel_index，记第一码长为N＝2^m，速率匹配后数据长度为Er。pre_bit_sel_index和bit_sel_index的关系如表7所示：
表7
Figure PCTCN2021114111-appb-000001
本申请实施例的技术方案，首先根据编码参数确定比特模式，然后根据比特模式将待编码通信数据映射为polar编码的输入数据及添加校验比特，获得初始比特序列，再然后将比特序列划分为多个子序列，对多个子序列进行矩阵乘法及加法运算，获得目标比特序列，最后基于传输速率生成比特索引，根据比特索引从目标比特序列中选取比特数据进行传输。本申请实施例提供的通信数据的处理方法，根据比特模式将待编码通信数据映射为polar编码的输入数据及添加校验比特，获得初始比特序列，可以提高polar编码的效率，将比特序列划分为多个子序列，对多个子序列进行矩阵乘法及加法运算，获得目标比特序列，不是对整个比特序列进行矩阵乘法及加法运算，可以提高运算的速率；根据比特索引从目标比特序列中选取比特数据进行传输，以实现速率匹配，不是直接对目标比特序列进行速率匹配，提高速率匹配的效率。
在一个实施例中，图5为本申请实施例中的一种通信数据的处理装置的结构示意图。如图5所示，该装置包括：比特模式确定模块210，初始比特序列获取模块220，目标比特序列获取模块230和数据选取模块240。
比特模式确定模块210，用于根据编码参数确定比特模式。
初始比特序列获取模块220，用于根据待编码通信数据和校验比特映射比特模式，获得初始比特序列。
目标比特序列获取模块230，用于将初始比特序列中的多个子序列分别与预设矩阵进行运算，获得目标比特序列。
数据选取模块240，用于基于传输速率生成比特索引，根据比特索引从目标比特序列中选取比特数据进行传输。
在一个实施例中，编码参数包括第一码长和地址权重；第一码长为目标比特序列的码长；比特模式确定模块210，还用于：根据第一码长确定地址段，并获取地址段中每个地址的地址权重；对于每个地址，对地址权重进行解子块交织运算以判断地址是否为打孔位置或者缩短位置；若是，则将地址的比特值置0；否则将地址的比特值置1，且将有效比特数累加1；当存在校验比特时，根据地址的行重和/或有效比特数确定地址是否为检验位；若是，则将地址权重记录为校验索引。
在一个实施例中，比特模式确定模块210，还用于：将地址权重转化为十位二进制码；根据第一码长对十位二进制码进行位数截取，获得第一值；根据第一值查表获得第二值；根 据第二值和第一码长计算获得第三值；将第三值与十位二进制码中截取掉的值进行累加，获得第四值；根据第四值判断地址是否为打孔位置或者缩短位置。
在一个实施例中，编码参数还包括第二码长，第二码长为待编码通信数据的码长；根比特模式确定模块210，还用于：若存在设定校验比特，当有效比特数小于或者等于第二码长时，判断地址的行重是否是已记录的行重中最小的，若是，则将地址权重记录为第一校验索引；当有效比特数为第二码长加2时，将地址权重记录为第二校验索引；当有效比特数为第二码长加3时，将地址权重记录为第三校验索引；若不存在设定校验比特，当有效比特数为第二码长加1时，将地址权重记录为第一校验索引；当有效比特数为第二码长加2时，将地址权重记录为第二校验索引；当有效比特数为第二码长加3时，将地址权重记录为第三校验索引。
在一个实施例中，初始比特序列获取模块220，还用于：从比特模式中依次提取各地址中的比特，若地址对应的权重值为校验索引，则将选择的校验比特添加至该地址中；若比特值为1且地址对应的权重值不是校验索引，则按照顺序从待编码通信数据中选择比特数据添加至该地址。
在一个实施例中，目标比特序列获取模块230，还用于：将初始比特序列划分为多个子序列；将多个子序列分别与预设矩阵相乘；将相乘后的多个子序列按照设定方式进行多阶段的加法运算。
在一个实施例中，目标比特序列获取模块230，还用于：对于每一阶段的加法运算，将上一阶段加法运算获得的多个子序列均分为两组，并建立两组间子序列的一一对应关系；将具有一一对应关系的子序列进行加法运算，并将加法运算后获得的序列作为其中一组新的子序列；另一组的子序列保持不变。
在一个实施例中，数据选取模块240，还用于：基于传输速率进行解比特交织、解比特选择和解子块交织处理，获得比特索引。
在一个实施例中，数据选取模块240，还用于：根据传输速率及第一码长确定速率匹配模式；根据速率匹配模式进行解比特选择处理。
在一个实施例中，图6是本申请实施例提供的一种计算机设备的结构示意图。如图6所示，本申请提供的设备，包括：处理器310以及存储器320。该设备中处理器310的数量可以是一个或者多个，图6中以一个处理器310为例。该设备中存储器320的数量可以是一个或者多个，图6中以一个存储器320为例。该设备的处理器310以及存储器320可以通过总线或者其他方式连接，图6中以通过总线连接为例。实施例中，该设备为计算机设备。
存储器320作为一种计算机可读存储介质，可设置为存储软件程序、计算机可执行程序以及模块，如本申请任意实施例的设备对应的程序指令/模块(例如，数据传输装置中的编码模块和第一发送模块)。存储器320可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据设备的使用所创建的数据等。此外，存储器320可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实例中，存储器320可进一步包括相对于处理器310远程设置的存储器，这些远程存储器可以通过网络连接至设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
上述提供的设备可设置为执行上述任意实施例提供的应用于通信数据的处理方法，具备相应的功能和效果。
对应存储器320中存储的程序可以是本申请实施例所提供应用于中断处理方法对应的程序指令/模块，处理器310通过运行存储在存储器320中的软件程序、指令以及模块，从而执行计算机设备的一种或多种功能应用以及数据处理，即实现上述方法实施例中应用于数据的关联查询方法。可以理解的是，上述设备为接收端时，可执行本申请任意实施例所提供的应用于中断处理方法，且具备相应的功能和效果。
本申请实施例还提供一种包含计算机可执行指令的存储介质，计算机可执行指令在由计算机处理器执行时用于执行一种通信数据的处理方法，该方法包括：根据编码参数确定比特模式；根据比特模式将待编码通信数据映射为polar编码的输入数据及添加校验比特，获得初始比特序列；将初始比特序列划分为多个子序列，对多个子序列进行矩阵乘法及加法运算，获得目标比特序列；基于传输速率生成比特索引，根据比特索引从目标比特序列中选取比特数据进行传输。
本领域内的技术人员应明白，术语用户设备涵盖任何适合类型的无线用户设备，例如移动电话、便携数据处理装置、便携网络浏览器或车载移动台。
一般来说，本申请的多种实施例可以在硬件或专用电路、软件、逻辑或其任何组合中实现。例如，一些方面可以被实现在硬件中，而其它方面可以被实现在可以被控制器、微处理器或其它计算装置执行的固件或软件中，尽管本申请不限于此。
本申请的实施例可以通过移动装置的数据处理器执行计算机程序指令来实现，例如在处理器实体中，或者通过硬件，或者通过软件和硬件的组合。计算机程序指令可以是汇编指令、指令集架构(Instruction Set Architecture，ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码。
本申请附图中的任何逻辑流程的框图可以表示程序步骤，或者可以表示相互连接的逻辑电路、模块和功能，或者可以表示程序步骤与逻辑电路、模块和功能的组合。计算机程序可以存储在存储器上。存储器可以具有任何适合于本地技术环境的类型并且可以使用任何适合的数据存储技术实现，例如但不限于只读存储器(Read-Only Memory，ROM)、随机访问存储器(Random Access Memory，RAM)、光存储器装置和系统(数码多功能光碟(Digital Video Disc，DVD)或光盘(Compact Disk，CD))等。计算机可读介质可以包括非瞬时性存储介质。数据处理器可以是任何适合于本地技术环境的类型，例如但不限于通用计算机、专用计算机、微处理器、数字信号处理器(Digital Signal Processing，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、可编程逻辑器件(Field-Programmable Gate Array，FGPA)以及基于多核处理器架构的处理器。
以上，仅为本申请的示例性实施例而已，并非用于限定本申请的保护范围。
本申请的实施例可以通过移动装置的数据处理器执行计算机程序指令来实现，例如在处理器实体中，或者通过硬件，或者通过软件和硬件的组合。计算机程序指令可以是汇编指令、指令集架构(ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目的代码。
通过示范性和非限制性的示例，上文已提供了对本申请的示范实施例的详细描述。但结 合附图和权利要求来考虑，对以上实施例的多种修改和调整对本领域技术人员来说是显而易见的，但不偏离本申请的范围。因此，本申请的恰当范围将根据权利要求确定。

Claims (12)

  1. 一种通信数据的处理方法，包括：
    根据编码参数确定比特模式；
    根据待编码通信数据和校验比特映射所述比特模式，获得初始比特序列；
    将所述初始比特序列中的多个子序列分别与预设矩阵进行运算，获得目标比特序列；
    基于传输速率生成比特索引，根据所述比特索引从所述目标比特序列中选取比特数据进行传输。
  2. 根据权利要求1所述的方法，其中，所述编码参数包括第一码长和地址权重；第一码长为目标比特序列的码长；根据编码参数确定比特模式，包括：
    根据所述第一码长确定地址段，并获取所述地址段中每个地址的地址权重；
    对于每个地址，对所述地址权重进行解子块交织运算以判断所述地址是否为打孔位置或者缩短位置；
    若是，则将所述地址的比特值置0；若否，则将所述地址的比特值置1，且将有效比特数累加1；
    当存在校验比特时，根据所述地址的行重和/或有效比特数确定所述地址是否为检验位；
    若是，则将所述地址权重记录为校验索引。
  3. 根据权利要求2所述的方法，其中，对所述地址权重进行解子块交织运算以判断所述地址是否为打孔位置或者缩短位置，包括：
    将所述地址权重转化为十位二进制码；
    根据所述第一码长对所述十位二进制码进行位数截取，获得第一值；
    根据所述第一值查表获得第二值；
    根据所述第二值和所述第一码长计算获得第三值；
    将所述第三值与所述十位二进制码中截取掉的值进行累加，获得第四值；
    根据所述第四值判断所述地址是否为打孔位置或者缩短位置。
  4. 根据权利要求2所述的方法，其中，所述编码参数还包括第二码长，所述第二码长为待编码通信数据的码长；根据所述地址的行重和/或有效比特数确定所述地址是否为检验位，包括：
    若存在设定校验比特，当有效比特数小于或者等于所述第二码长时，判断所述地址的行重是否是已记录的行重中最小的，若是，则将所述地址权重记录为第一校验索引；
    当有效比特数为第二码长加2时，将所述地址权重记录为第二校验索引；当有效比特数为第二码长加3时，将所述地址权重记录为第三校验索引；
    若不存在设定校验比特，当有效比特数为第二码长加1时，将所述地址权重记录为第一校验索引；当有效比特数为第二码长加2时，将所述地址权重记录为第二校验索引；当有效比特数为第二码长加3时，将所述地址权重记录为第三校验索引。
  5. 根据权利要求2所述的方法，其中，根据待编码通信数据和校验比特映射所述比特模式，包括：
    从所述比特模式中依次提取各地址中的比特，若地址对应的权重值为校验索引，则将选择的校验比特添加至该地址中；
    若比特值为1且地址对应的权重值不是校验索引，则按照顺序从待编码通信数据中选择比特数据添加至该地址。
  6. 根据权利要求1-5中任一所述的方法，其中，将所述初始比特序列中的多个子序列分别与预设矩阵进行运算，包括：
    将所述初始比特序列划分为多个子序列；
    将所述多个子序列分别与预设矩阵相乘；
    将相乘后的多个子序列按照设定方式进行多阶段的加法运算。
  7. 根据权利要求6所述的方法，其中，将相乘后的多个子序列按照设定方式进行多阶段的加法运算，包括：
    对于每一阶段的加法运算，将上一阶段加法运算获得的多个子序列均分为两组，并建立两组间子序列的一一对应关系；
    将具有所述一一对应关系的子序列进行加法运算，并将加法运算后获得的序列作为其中一组新的子序列；另一组的子序列保持不变。
  8. 根据权利要求1-7中任一所述的方法，其中，基于传输速率生成比特索引，包括：
    基于传输速率进行解比特交织、解比特选择和解子块交织处理，获得比特索引。
  9. 根据权利要求8所述的方法，其中，基于传输速率进行解比特选择处理，包括：
    根据传输速率及所述第一码长确定速率匹配模式；
    根据所述速率匹配模式进行解比特选择处理。
  10. 一种通信数据的处理装置，包括：
    比特模式确定模块，用于根据编码参数确定比特模式；
    初始比特序列获取模块，用于根据待编码通信数据和校验比特映射所述比特模式，获得初始比特序列；
    目标比特序列获取模块，用于将所述初始比特序列中的多个子序列分别与预设矩阵进行运算，获得目标比特序列；
    数据选取模块，用于基于传输速率生成比特索引，根据所述比特索引从所述目标比特序 列中选取比特数据进行传输。
  11. 一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现如权利要求1-9中任一所述的通信数据的处理方法。
  12. 一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现如权利要求1-9中任一所述的通信数据的处理方法。
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