WO2022089505A1 - 一种错误检测方法及相关装置 - Google Patents

一种错误检测方法及相关装置 Download PDF

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Publication number
WO2022089505A1
WO2022089505A1 PCT/CN2021/126873 CN2021126873W WO2022089505A1 WO 2022089505 A1 WO2022089505 A1 WO 2022089505A1 CN 2021126873 W CN2021126873 W CN 2021126873W WO 2022089505 A1 WO2022089505 A1 WO 2022089505A1
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WO
WIPO (PCT)
Prior art keywords
test mode
mapping relationship
instruction
terminal
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/126873
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English (en)
French (fr)
Inventor
陶喆
沈戈
曹建龙
王明
方锐
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP21885232.5A priority Critical patent/EP4227809A4/en
Publication of WO2022089505A1 publication Critical patent/WO2022089505A1/zh
Priority to US18/308,405 priority patent/US12174254B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3668—Testing of software
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Definitions

  • the present application relates to the field of computer technology, and in particular, to an error detection method and related apparatus.
  • random hardware failures can occur in data processing devices, such as permanent failures caused by shorts or opens in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle strikes .
  • the processor can be provided with error detection mechanisms to detect hardware errors and ensure that in the event of a hardware error Perform safe operations.
  • test pattern a test pattern
  • STL Software Test Library
  • the present application provides an error detection method and a related device.
  • a schedule table of a target task is determined to execute a test mode included in the schedule table. Since the schedule table only includes test modes for detecting the target logic circuit, which is used to execute the target task, detecting errors based on the schedule table can avoid executing all test modes in the software testing library, thereby reducing The load of the processor is reduced, and the working efficiency of the processor is effectively improved.
  • a first aspect of the present application provides an error detection method, which is applied to a terminal in a field with safety requirements, such as a vehicle-mounted terminal or a control terminal in aerospace.
  • the method includes: the terminal acquires a schedule table of a target task, where the schedule table may be preset in the terminal or pre-generated by the terminal, and the target task may be, for example, a process or a thread.
  • the schedule table includes at least one test pattern based on which errors of the target logic circuit upon which the target task depends can be detected.
  • the terminal executes at least one test mode according to the schedule table, so as to realize error detection of the target logic circuit.
  • the terminal executes the test mode included in the scheduling table by determining the scheduling table of the target task. Since the schedule table only includes test modes for detecting the target logic circuit, which is used to execute the target task, detecting errors based on the schedule table can avoid executing all test modes in the software testing library, thereby reducing The load of the processor is reduced, and the working efficiency of the processor is effectively improved.
  • the target task is a running task.
  • the terminal runs the target task, if there is an error in the logic circuit that needs to be used during the execution of the target task, the terminal may run the target task due to the error of the logic circuit, resulting in a security risk. Therefore, executing the test mode based on the schedule table of the target task can realize error detection of the logic circuit that needs to be used, and avoid the occurrence of security risks. For other logic circuits, since the current terminal does not perform corresponding tasks, that is, no other logic circuits are required, even if errors occur in this part of the logic circuits, there will be no security risk.
  • the terminal may pre-generate a schedule table corresponding to the task to be run.
  • the method may further include: the terminal obtains the machine instruction code set of the target task. Since the target task may be a process or a thread, for example, the corresponding machine instruction code set may be obtained based on the executable file of the target task.
  • a code set includes a plurality of machine instruction codes (also referred to as machine codes).
  • the terminal determines at least one instruction type corresponding to the machine instruction code set according to a preset second mapping relationship, where the second mapping relationship includes the mapping relationship between the machine instruction code and the instruction type.
  • one machine instruction code is unique Corresponds to an instruction type.
  • the terminal determines at least one test mode corresponding to at least one instruction type according to a preset first mapping relationship, and the at least one test mode is used to detect errors in the logic circuit corresponding to at least one instruction type.
  • the first mapping relationship includes the instruction type and the test mode. The mapping relationship between them, and in this mapping relationship, one instruction type can correspond to one or more test modes.
  • the terminal then generates a schedule table according to at least one test pattern.
  • the terminal determines the instruction type corresponding to the machine instruction code set based on the preset second mapping relationship, and determines the test mode corresponding to the instruction type based on the first mapping relationship, thereby Get the test mode corresponding to the target task.
  • the terminal can generate the scheduling table corresponding to the task to be executed based on the preset mapping relationship, which can ensure that the terminal can generate the scheduling table corresponding to the task when it acquires a new task, which ensures the feasibility of the solution. .
  • the method may further include: the terminal determining the execution times of the instruction type in at least one instruction type according to the instruction types corresponding to the multiple machine instruction codes respectively.
  • the terminal can count the number of machine instruction codes corresponding to each instruction type, and determine the number of machine instruction codes corresponding to the instruction type as the execution times of the instruction type.
  • the terminal may determine the execution order of the test modes in the at least one test mode, so as to generate a schedule table that further includes the execution order of the test modes. That is, the terminal can sort the test modes in descending order based on the execution times. The greater the execution times of the instruction type corresponding to the test mode, the higher the execution order of the test mode. Smaller, the later the execution order of the test pattern is.
  • the execution order of the test mode in the schedule table is determined based on the execution times of the instruction type corresponding to the machine instruction code of the target task, so that the terminal can determine the detection logic circuit based on the probability of an error in the logic circuit Logic circuits with higher error probability are detected first, thereby shortening the error detection time and improving the efficiency of error detection.
  • the terminal determines the execution order of the test mode based on the execution times of the instruction type corresponding to the task, which can shorten the error detection time and improve the efficiency of error detection.
  • the scheduling table may be preset in the terminal or pre-generated by the terminal, and at least one test mode in the scheduling table is determined based on a first mapping relationship and at least one instruction type.
  • the first mapping The relationship includes the mapping relationship between the instruction type and the test mode, at least one instruction type is determined based on the second mapping relationship and the machine instruction code set of the target task, and the second mapping relationship includes the mapping relationship between the machine instruction code and the instruction type.
  • the machine instruction code set includes multiple machine instruction codes.
  • the schedule table further indicates an execution order of at least one test mode, and the execution order is determined based on the execution times of at least one instruction type corresponding to the machine instruction code set of the target task.
  • the terminal when there are many tasks to be executed in the terminal, the terminal may generate a large number of scheduling tables. Therefore, the method may further include: the terminal generates a third mapping relationship, where the third mapping relationship includes the mapping relationship between the target task and the schedule table.
  • the scheduling table can be determined according to the target task and the third mapping relationship, which ensures that the terminal can quickly determine the scheduling table corresponding to the target task in the process of performing error detection, and improves the efficiency of performing error detection.
  • the schedule table is stored in a shared memory
  • the shared memory is configured to store schedule tables corresponding to one or more tasks
  • the shared memory can be accessed by multiple processors.
  • the terminal provides a configuration area for the scheduling table by reserving a shared memory
  • multiple processors in the terminal can access the scheduling table in the shared memory.
  • each of the multiple processors in the terminal can individually perform corresponding error detection based on the tasks performed by each.
  • shared memory By reserving shared memory to provide a configuration area for the scheduling table, it is avoided to provide a configuration area for the scheduling table separately for each processor, and the overhead of storage resources is saved.
  • the execution of the at least one test mode by the terminal according to the scheduling table may specifically include: the terminal writes the at least one test mode into the sorting register according to the execution order; executes the test mode according to the execution order in the sorting register, and Writes the execution result of the test mode to the status register.
  • a second aspect of the present application provides a terminal, the terminal includes: a processing unit and an acquisition unit; the acquisition unit is used to acquire a schedule table of a target task, the schedule table is used to indicate at least one test mode, and the at least one test mode is used to detect the target
  • the error of the logic circuit the target logic circuit is a logic circuit for executing the target task; the processing unit is used for executing at least one test mode according to the schedule table to detect the error of the target logic circuit.
  • the target task is a running task.
  • At least one test mode in the scheduling table is determined based on a first mapping relationship and at least one instruction type
  • the first mapping relationship includes a mapping relationship between instruction types and test modes
  • at least one instruction type is determined based on a second mapping relationship and a machine instruction code set of the target task
  • the second mapping relationship includes a mapping relationship between machine instruction codes and instruction types
  • the machine instruction code set includes multiple machine instruction codes.
  • the schedule table further indicates an execution order of at least one test mode, and the execution order is determined based on the execution times of at least one instruction type corresponding to the machine instruction code set of the target task.
  • the terminal further includes: an acquisition unit; the acquisition unit is configured to acquire a machine instruction code set of the target task, where the machine instruction code set includes multiple machine instruction codes; the processing unit is further configured to: according to the first Two mapping relationships determine at least one instruction type corresponding to the machine instruction code set, and the second mapping relationship includes the mapping relationship between machine instruction codes and instruction types; at least one test mode corresponding to at least one instruction type is determined according to the first mapping relationship, and the second mapping relationship includes the mapping relationship between machine instruction codes and instruction types.
  • a mapping relationship includes a mapping relationship between instruction types and test modes, at least one test mode is used to detect errors in logic circuits corresponding to at least one instruction type; a scheduling table is generated according to the at least one test mode.
  • the processing unit is further configured to: determine the execution times of the instruction type in at least one instruction type according to the instruction types corresponding to the multiple machine instruction codes respectively; determine the test mode in the at least one test mode according to the execution times The execution sequence of ; generate a schedule table according to at least one test pattern and execution sequence.
  • the processing unit is further configured to: generate a third mapping relationship, where the third mapping relationship includes a mapping relationship between the target task and the scheduling table; and determine the scheduling table according to the target task and the third mapping relationship.
  • the schedule table is stored in shared memory, the shared memory is configured to store the schedule table of one or more tasks, and the shared memory can be accessed by multiple processors.
  • the processing unit is further configured to: write at least one test mode into the sorting register according to the execution order; execute the test mode according to the execution order in the sorting register, and write the execution result of the test mode into the status register .
  • target tasks include processes or threads.
  • a third aspect of the present application provides a terminal, the terminal includes: a processor; the processor reads a computer-readable instruction in a memory, so that the terminal implements the method according to any one of the implementation manners of the first aspect.
  • a fourth aspect of the present application provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, which, when executed on a computer, causes the computer to execute the method according to any one of the implementations of the first aspect.
  • a fifth aspect of the present application provides a computer program product, which, when run on a computer, causes the computer to execute the method according to any one of the implementations of the first aspect.
  • a sixth aspect of the present application provides a chip including one or more processors. Part or all of the processor is used to read and execute the computer program stored in the memory to execute the method in any possible implementation of any of the above aspects.
  • the chip includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used for receiving data and/or information to be processed, the processor obtains the data and/or information from the communication interface, processes the data and/or information, and outputs the processing result through the communication interface.
  • the communication interface may be an input-output interface.
  • the method provided by the present application may be implemented by one chip, or may be implemented by multiple chips cooperatively.
  • FIG. 1a is a schematic diagram of a FETI and an FHTI provided by an embodiment of the present application
  • FIG. 1b is a schematic structural diagram of a terminal 101 according to an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of an error detection method 200 provided by an embodiment of the present application.
  • 3a is a schematic flowchart of a method 300 for generating a schedule table according to an embodiment of the present application
  • 3b is a schematic flowchart of another scheduling table generation provided by an embodiment of the present application.
  • FIG. 3c is a schematic flowchart of another scheduling table generation provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a sorting register and a status register provided by an embodiment of the present application
  • FIG. 5 is a comparative schematic diagram of performing error detection provided by an embodiment of the present application.
  • Fig. 6 is the comparative schematic diagram of FDTI in different schemes provided by the embodiment of the present application.
  • FIG. 7(a) is a schematic diagram of the comparison of FDTI in different schemes when there is an error provided by the embodiment of the present application;
  • FIG. 7(b) is a schematic diagram of the total time-consuming comparison of error detection in different schemes provided by the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a terminal 800 according to an embodiment of the present application.
  • random hardware failures can occur in data processing devices, such as permanent failures caused by shorts or opens in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle strikes .
  • Functional safety refers to the absence of unacceptable risks due to electronic system failures, and its ultimate goal is to prevent human casualties or huge property damage due to electronic system failures.
  • FIG. 1a is a schematic diagram of an FDTI and a FHTI provided by an embodiment of the present application.
  • the system To avoid danger, the system must reach a safe state within a certain period of time after a system error, ie the sum of FDTI and FHTI must be less than or equal to a certain time threshold. Therefore, in order to ensure that the FHTI can be long enough to handle the error to ensure that the error can be handled smoothly, it is crucial to shorten the FDTI as much as possible.
  • DCLS Dual-core Lockstep
  • the implementation method of DCLS is: two processors run the same program, and input the output results of the two processors into a comparison logic to compare whether the output results of the two processors are the same. If the output of the two processors is the same, it can be determined that no error has occurred; if the output of the two processors is not the same, it can be determined that an error has occurred in the processor.
  • this method of error detection can effectively detect errors, it requires two processors to run the same program, which has the disadvantages of high cost and poor flexibility.
  • the error detection method is to detect the error of the logic circuit by periodically executing the test mode in the STL by the processor. Compared with the DCLS, the error detection method has lower cost and higher flexibility. However, since there are often more logic circuits in the system, in order to realize error detection of all logic circuits, more test modes are usually included in the STL. Therefore, the processor periodically executes the test mode in the STL, which results in a heavy load on the processor, that is, the processor needs to spend more time to detect errors, thereby affecting the working efficiency of the processor.
  • an embodiment of the present application provides an error detection method, and the error detection method can be applied to a terminal.
  • the terminal executes the test mode included in the scheduling table by determining the scheduling table corresponding to the currently running task. Since the schedule table only includes the test mode corresponding to the machine instruction code of the task, the terminal detects errors based on the schedule table, which can avoid executing all test modes in the software testing library, thereby reducing the load on the processor. Effectively improve the working efficiency of the processor.
  • the terminal involved in the embodiments of the present application may be a device used for data processing in a field with security requirements.
  • some examples of terminals are: vehicle-mounted terminals in transportation, control terminals in aerospace, wireless terminals in industrial control, wireless terminals in self-driving, remote medical wireless terminal in surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home Wait.
  • FIG. 1b is a schematic structural diagram of a terminal 101 according to an embodiment of the present application.
  • the terminal 101 includes a processor 103 , and the processor 103 is coupled to a system bus 105 .
  • the processor 103 may be one or more processors, each of which may include one or more processor cores.
  • a video adapter 107 which can drive a display 109, is coupled to the system bus 105.
  • the system bus 105 is coupled to an input-output (I/O) bus through a bus bridge 111 .
  • I/O interface 115 is coupled to the I/O bus.
  • the I/O interface 115 communicates with various I/O devices, such as an input device 117 (eg, a touch screen, etc.), a media tray 121, (eg, a compact disc read-only memory, CD- ROM), multimedia interface, etc.).
  • Transceiver 123 which can transmit and/or receive radio communication signals
  • camera 155 which can capture still and moving digital video images
  • external USB port 125 external USB port 125 .
  • the interface connected to the I/O interface 115 may be a USB interface.
  • the processor 103 may be any conventional processor, including a reduced instruction set computing (reduced instruction set computing, RISC) processor, a complex instruction set computing (complex instruction set computing, CISC) processor or a combination of the above.
  • the processor may be a special purpose device such as an ASIC.
  • Terminal 101 may communicate with software deployment server 149 through network interface 129 .
  • network interface 129 is a hardware network interface, such as a network card.
  • the network 127 may be an external network, such as the Internet, or an internal network, such as an Ethernet network or a virtual private network (VPN).
  • the network 127 may also be a wireless network, such as a WiFi network, a cellular network, and the like.
  • the hard drive interface 131 is coupled to the system bus 105 .
  • the hardware driver interface is connected to the hard disk drive 133 .
  • System memory 135 is coupled to system bus 105 .
  • the data running in the system memory 135 may include the operating system (OS) 137 of the terminal 101 , the application programs 143 and the schedule.
  • OS operating system
  • the operating system includes a Shell 139 and a kernel 141 .
  • Shell 139 is an interface between the user and the operating system's kernel.
  • the shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system: waiting for user input, interpreting user input to the operating system, and processing various operating system output.
  • Kernel 141 consists of those parts of the operating system that manage memory, files, peripherals, and system resources.
  • the kernel 141 directly interacts with the hardware, and the operating system kernel usually runs processes, provides inter-process communication, provides CPU time slice management, interrupts, memory management, IO management, and the like.
  • the application program 143 includes a program related to controlling car driving, for example, a program for managing the interaction between the self-driving car and road obstacles, a program for controlling the route or speed of the self-driving car, A program that controls the interaction of a self-driving car with other self-driving cars on the road.
  • the terminal 101 may download the application 143 from the software deployment server 149 when the application 143 needs to be executed. In one embodiment, when the terminal 101 downloads the application 143 from the software deployment server 149 , the terminal 101 may also download the schedule corresponding to the application 143 from the software deployment server 149 .
  • the sensor 153 is associated with the terminal 101 .
  • the sensor 153 is used to detect the environment around the terminal 101 .
  • the sensor 153 can detect animals, cars, obstacles and pedestrian crossings, etc.
  • the sensor 153 can also detect the environment around the above-mentioned animals, cars, obstacles and pedestrian crossings, such as: the environment around animals, for example, around animals Other animals present, weather conditions, ambient light levels, etc.
  • the sensor may be a radar system or the like.
  • FIG. 2 is a schematic flowchart of an error detection method 200 provided by an embodiment of the present application. As shown in FIG. 2, the error detection method 200 includes the following steps.
  • Step 201 Obtain a schedule table of the target task, where the schedule table is used to indicate at least one test mode, and the at least one test mode is used to detect errors in the target logic circuit, which is a logic circuit for executing the target task.
  • the terminal may execute the error detection method 200 periodically, for example, execute the error detection method 200 every 30 milliseconds or 50 milliseconds, so as to ensure that the occurrence of the error can be detected in time. mistake.
  • the target task may be a task running in the terminal, such as a process or thread running in the terminal.
  • the terminal determines the target task by obtaining the identifier (identifier, ID) of the currently running task or determining the target task based on the data structure corresponding to the currently running task. For example, based on the thread ID, the currently running task is specifically determined. which thread.
  • the target task when the target task is a process, the target task may be, for example, a process of vehicle video inspection, a vehicle speed calculation process, a radar detection process, a vehicle anti-lock braking process, or a tire pressure detection process.
  • any task that can be run in the terminal may have a corresponding schedule table.
  • These schedules may be preset in the terminal, for example, or may be generated by the terminal's task-based machine script. Therefore, the terminal may determine the schedule table corresponding to the target task from multiple schedule tables. For example, in the case that the target task is a process, the terminal may determine the schedule table corresponding to the target task based on the process ID.
  • the schedule table corresponding to the target task may include at least one test mode, the at least one test mode corresponds to the machine instruction code of the target task, and the at least one test mode is used to detect errors in the target logic circuit.
  • that the at least one test mode corresponds to the machine instruction code of the target task means that based on the at least one test mode, error detection of the target logic circuit on which the machine instruction code of the target task depends can be implemented.
  • the terminal executes the machine instruction code, it needs to rely on the logic circuit in the terminal, that is, the machine instruction code is executed based on the logic circuit. Therefore, when at least one test mode corresponding to the machine instruction code of the target task is determined, the logic circuit used by the terminal to execute the machine instruction code of the target task can be based on the at least one test mode. detection.
  • At least one test mode in the scheduling table is determined based on a first mapping relationship and at least one instruction type
  • the first mapping relationship includes a mapping relationship between instruction types and test modes
  • at least one instruction type is determined based on a second mapping relationship and a machine instruction code set of the target task
  • the second mapping relationship includes a mapping relationship between machine instruction codes and instruction types
  • the machine instruction code set includes multiple machine instruction codes.
  • the schedule table corresponding to the target task may further indicate an execution order of at least one test mode, where the execution order is determined based on the execution times of the instruction type corresponding to the machine instruction code of the target task.
  • a task usually includes multiple machine instruction codes, and different machine instruction codes may belong to different instruction types, or may belong to the same instruction type.
  • Machine instruction codes with the same instruction type usually rely on the same logic circuit to execute, and machine instruction codes with different instruction types rely on different logic circuits to execute.
  • the terminal needs to use the logic circuit corresponding to the instruction type multiple times during the process of executing the target task. That is to say, every use of the logic circuit may lead to an error in the logic circuit, and the probability of the error of the logic circuit is the same, the more times the logic circuit is used, the higher the probability of the error of the logic circuit.
  • the execution order of the test mode in the scheduling table can be determined based on the execution times of the instruction type corresponding to the machine instruction code of the target task. That is, the more times an instruction type is executed, the higher the execution order of the test mode corresponding to the instruction type, so that the terminal can determine the order of detecting logic circuits based on the probability of errors in the logic circuits, thereby shortening the error detection time and improving Efficiency of error detection.
  • the target task includes 6 machine instruction codes
  • the 6 machine instruction codes there are 3 machine instruction codes belonging to instruction type 1, 2 machine instruction codes belonging to instruction type 0, and 1 machine instruction code belonging to instruction type 2. machine script.
  • the execution times of instruction type 0, instruction type 1, and instruction type 2 are 2, 3, and 1, respectively.
  • the schedule table corresponding to the target task includes test mode A, test mode B and test mode C corresponding to instruction type 0, instruction type 1 and instruction type 2 respectively, and the schedule table may also include the above three test modes.
  • Execution sequence The execution sequence of the test mode is determined based on the execution times of the instruction type corresponding to the test mode. That is, the execution sequence of the test mode is: test mode B-test mode A-test mode C. In this way, in the process of performing the error detection, the terminal may sequentially execute the test mode B, the test mode A and the test mode C based on the execution order.
  • Step 202 execute at least one test mode to detect errors in the target logic circuit.
  • the terminal After acquiring the schedule, the terminal executes one or more test modes indicated by the schedule in sequence. Moreover, after the test mode indicated by the schedule table is completed, the terminal may determine that the current period for performing error detection ends, and the terminal may execute the error detection method 200 again after a certain interval. In addition, when the schedule table further includes the execution order of the test mode, the terminal may also execute one or more test modes in the schedule table in sequence based on the execution order indicated by the schedule table.
  • the terminal executes the test mode included in the scheduling table by acquiring the scheduling table of the target task. Since the schedule table only includes the test mode for detecting the target logic circuit, the terminal detects errors based on the schedule table, which can avoid executing all test modes in the software test library, thereby reducing the load of the processor and effectively improving the the efficiency of the processor.
  • the schedule table further includes the execution order of the test mode determined based on the execution times of the instruction type, the terminal executes the test mode based on the execution order, so that the order of detecting the logic circuit can be determined based on the probability of an error occurring in the logic circuit , thereby shortening the error detection time and improving the efficiency of error detection.
  • the above describes the process that the terminal executes the corresponding test mode based on the schedule table corresponding to the target task to implement error detection.
  • the following will describe the process of generating the schedule table by the terminal in detail.
  • FIG. 3a is a schematic flowchart of a method 300 for generating a schedule table according to an embodiment of the present application. As shown in Fig. 3a, the schedule generation method 300 includes the following steps.
  • Step 301 Obtain a machine instruction code set of the target task, where the machine instruction code set includes multiple machine instruction codes.
  • the terminal may pre-generate the schedule table corresponding to the task to be executed in the terminal, so that the terminal can obtain the schedule table corresponding to the target task during the error detection process.
  • the above-mentioned target task is a task to be executed in the terminal, and the terminal can obtain the machine instruction code set of the target task by obtaining the executable file of the target task.
  • the target task is an application program
  • the application program is installed in the terminal, and the executable file of the application program can be, for example, ".exe format file”, “.sys format file”, “.com format file” and other types of files
  • the terminal can obtain the machine instruction code set corresponding to the application program based on the executable file of the application program.
  • the executable file of the target task usually includes multiple machine instruction codes, that is, the machine instruction code set includes multiple machine instruction codes, and the terminal implements the implementation by executing the multiple machine instruction codes.
  • the execution of the target task usually includes multiple machine instruction codes, that is, the machine instruction code set includes multiple machine instruction codes, and the terminal implements the implementation by executing the multiple machine instruction codes. The execution of the target task.
  • Step 302 Determine at least one instruction type corresponding to the machine instruction code set according to a second mapping relationship, where the second mapping relationship includes a mapping relationship between machine instruction codes and instruction types.
  • any machine instruction code there is a corresponding instruction type, that is, any machine instruction code can be classified as a certain instruction type.
  • the instruction type may include, for example, a data transfer instruction, a fixed-point arithmetic operation instruction, a bitwise operation instruction, and a program control instruction. Since different machine instruction codes may correspond to the same instruction type, or may correspond to different instruction types, at least one instruction type may be determined based on each machine instruction code in the set of machine instruction codes.
  • a second mapping relationship may be preset in the terminal, where the second mapping relationship includes a mapping relationship between machine instruction codes and instruction types, and each machine instruction code in the machine instruction code set may be determined based on the second mapping relationship The corresponding command type.
  • Table 1 a possible example of the second mapping relationship is shown in Table 1:
  • the number of instruction types determined by the terminal based on the machine instruction code set is equal to or smaller than the number of machine instruction codes in the machine instruction code set.
  • the number of instruction types is less than the number of machine instruction codes, there are multiple machine instruction codes corresponding to the same instruction type, that is, the number of execution times of an instruction type is the number of corresponding machine instruction codes.
  • the second mapping relationship may be established based on an instruction set manual corresponding to the processor in the terminal.
  • an instruction instructing computer hardware to perform a certain operation or processing function
  • the expression of the instruction can be the above-mentioned machine instruction code.
  • the instruction is the smallest functional unit that the computer runs, and the function of the hardware is to complete the function specified by each instruction.
  • the set of all commands on the terminal is the command set of the terminal, which is the embodiment of all the functions on the terminal.
  • the instruction set on a terminal reflects all the functions of the terminal. Different types of terminals may have different instruction sets and thus different functions.
  • the setting of the instruction set is closely related to the hardware circuit of the terminal, and the instruction set manual can indicate the instruction set that the terminal can execute and the relationship between the instruction set and the hardware circuit in the terminal. Based on the instruction set manual, the relationship between the instruction and the hardware circuit can be determined, and the instruction type to which each instruction in the instruction set belongs, so as to establish the mapping relationship between the machine instruction code and the instruction type.
  • Step 303 Determine at least one test mode corresponding to at least one instruction type according to the first mapping relationship, the first mapping relationship includes the mapping relationship between the instruction type and the test mode, and the at least one test mode is used to detect the logic corresponding to the at least one instruction type circuit error.
  • each type of instruction can be executed in a certain logic circuit, and the logic circuit corresponding to each type of instruction is fixed. Therefore, it can be considered that after the instruction type corresponding to a certain machine instruction code is determined, the logic circuit for executing the machine instruction code can be uniquely determined. Then, after at least one instruction type corresponding to the machine instruction code set is determined, by determining the test mode corresponding to the at least one instruction type, the detection of the logic circuit used in the target task can be realized based on the determined test mode.
  • a first mapping relationship may be preset in the terminal, where the first mapping relationship includes a mapping relationship between instruction types and test modes, and a test mode corresponding to each instruction type can be obtained based on the first mapping relationship.
  • the first mapping relationship includes a mapping relationship between instruction types and test modes, and a test mode corresponding to each instruction type can be obtained based on the first mapping relationship.
  • Table 2 a possible example of the first mapping relationship is shown in Table 2:
  • each test mode group can include one or more test modes, that is, any instruction type has one or more corresponding test modes. test mode. Also, each test mode is used to test a specific logic circuit. Therefore, after the terminal determines the instruction type to which the machine instruction code belongs, the test mode to be executed may be determined based on the instruction type.
  • the first mapping relationship may be obtained based on an STL design document.
  • relevant information of all test modes included in the STL may be determined, for example, the logic circuits detected by the test modes may be determined.
  • a first mapping relationship can be established to establish a mapping relationship between the same instruction type of the logic circuit and the test mode.
  • Step 304 generating a schedule table according to at least one test mode.
  • the terminal may generate the schedule table only based on the determined at least one test mode, that is, the obtained schedule table only includes the at least one test mode without specifying the execution order between the test modes.
  • the terminal may further determine an execution order of the at least one test mode, and generate a scheduling table based on the execution order, so that the scheduling table may further include the execution order between the test modes.
  • the terminal may determine the instruction type of each instruction type in the at least one instruction type according to the instruction types corresponding to the multiple machine instruction codes respectively. number of executions. In short, the terminal can count the number of machine instruction codes corresponding to each instruction type, and determine the number of machine instruction codes corresponding to the instruction type as the execution times of the instruction type. According to the execution times, the terminal may determine the execution sequence of the test modes in the at least one test mode. Since each test mode has a unique corresponding instruction type, and each instruction type has its corresponding execution times, the terminal can determine the execution order of the test modes based on the execution times of the instruction types corresponding to the test mode.
  • the terminal can sort the test modes in descending order based on the execution times.
  • the terminal may generate a schedule table including the execution sequence of the test modes according to the at least one test mode and the execution sequence, so that the terminal can execute the test modes in sequence based on the execution sequence indicated in the schedule table when performing error detection.
  • the above steps 301-304 describe the process that the terminal generates the corresponding schedule table based on the target task.
  • the terminal may determine the corresponding tasks of the multiple tasks based on a similar process after acquiring the multiple tasks to be executed. so that the terminal can save the schedule table corresponding to each task. In this way, when the terminal executes any task, it can search and obtain the scheduling table corresponding to the task, so as to realize the error detection corresponding to the task.
  • the terminal when there are many tasks to be executed in the terminal, the terminal can generate a large number of scheduling tables. Therefore, in order to enable the terminal to quickly determine the scheduling table corresponding to the target task during the error detection process, after generating the scheduling table corresponding to each task, the terminal may also establish a mapping relationship between the tasks and the scheduling table. Exemplarily, the terminal may generate a third mapping relationship, where the third mapping relationship includes a mapping relationship between the task to be run and the schedule table. After the terminal newly generates any scheduling table, the terminal can update the third mapping relationship to increase the mapping relationship between the newly generated scheduling table and the task, so that the third mapping relationship generated by the terminal can include each in the terminal. The mapping relationship between a task to be run and its corresponding schedule table.
  • the terminal may assign a unique ID to each newly generated schedule table, and establish a mapping relationship between the task ID and the schedule table ID to obtain a third mapping relationship .
  • the terminal can quickly determine the corresponding scheduling table ID based on the task ID and the third mapping relationship, and obtain the corresponding scheduling table by searching based on the scheduling table ID.
  • Table 3 a possible example of the third mapping relationship is shown in Table 3:
  • the terminal may also allocate a corresponding address space for the newly generated schedule table after the schedule table is newly generated, so as to obtain an address space for storing the schedule table.
  • the terminal can establish the mapping relationship between the task ID and the address space of the scheduling table to obtain the third mapping relationship. That is, the terminal can quickly determine the address space of the corresponding scheduling table based on the task ID and the third mapping relationship, so that the corresponding scheduling table can be obtained by searching in the address space.
  • FIG. 3b is a schematic flowchart of another scheduling table generation provided by an embodiment of the present application.
  • the terminal can obtain N tasks such as task 1, task 2, ... task N, etc. located in the terminal; then, the terminal performs machine instruction code scanning on these tasks respectively to determine the machine instruction code corresponding to each task .
  • the terminal can pick the test patterns corresponding to the machine instruction code of each task in the STL, and sort these picked test patterns, so as to obtain the scheduling table of each task, that is, the task Schedule 1 of 1, Schedule 2 of Task 2... Schedule N of Task N.
  • FIG. 3c is a schematic flowchart of another scheduling table generation provided by this embodiment of the present application.
  • Figure 3c introduces the process of generating the schedule table by taking the processing chip as Hi1951Taishan as an example.
  • Hi1951Taishan is a processing chip of Huawei, which can include multiple processors and can perform different tasks in parallel.
  • the mapping relationship between machine instruction codes and instruction types can be determined based on the processor architecture instruction set of Hi1951Taishan, and the mapping table A can be obtained; The mapping relationship between the test modes is obtained, and the mapping table B is obtained.
  • the instruction scanner can determine the instruction type corresponding to each machine instruction code in the executable file, thereby obtaining all instruction types corresponding to the executable file.
  • the test modes corresponding to these instruction types can be determined based on the mapping table B, and these test modes are sorted according to the execution times of the instruction types. That is, pick and sort test patterns in STL to get the schedule table corresponding to the target task.
  • the above describes the process of generating the scheduling table by the terminal based on the machine instruction code set of the task.
  • the following will describe in detail the process of how the terminal configures the scheduling table after the scheduling table is generated.
  • the terminal may provide a configuration area for the scheduling table by reserving shared memory.
  • the terminal may reserve a part of the memory space as shared memory through a device tree binary (device tree binary, DTB) configuration, and obtain a reference handle of the shared memory, where the reference handle includes the address, size, and access authority of the shared memory. and other configuration information.
  • the terminal may allocate an address space in the shared memory for the scheduling table, and store the scheduling table in the address space in the shared memory.
  • the terminal may also generate configuration information of the schedule table based on the address space, for example, generate a mapping relationship between the index of the address space and the schedule table ID, so that the terminal can determine the address space based on the schedule table ID when performing error detection , so that the dispatch table can be found in this address space.
  • the terminal When the terminal provides a configuration area for the scheduling table by reserving a shared memory, multiple processors in the terminal can access the scheduling table in the shared memory. In this way, each of the multiple processors in the terminal can individually perform corresponding error detection based on the tasks performed by each. By reserving shared memory to provide a configuration area for the scheduling table, it is avoided to provide a configuration area for the scheduling table separately for each processor, and the overhead of storage resources is saved.
  • the terminal may implement the scheduling of the scheduling table by means of hardware.
  • two registers for scheduling the schedule table may be pre-designed in the processor of the terminal, namely, a sorting register and a status register.
  • the terminal can orderly write the test patterns in the schedule table into the sorting register according to the execution order of the test patterns in the schedule table. Then, the terminal can execute the test mode according to the execution order in the sorting register, and write the execution result of the test mode into the status register.
  • FIG. 4 is a schematic structural diagram of a sorting register and a status register provided by an embodiment of the present application.
  • the sorting register and the status register are both 64-bit (bit) registers.
  • 64 bits are divided into 16 4 bits, and each 4 bits can be used to represent the ID of a group of test patterns.
  • the terminal can orderly write the test patterns in the scheduling table into the sorting register according to the execution order of the test patterns in the scheduling table, and when performing error detection, execute the test patterns in order according to the execution order in the sorting register.
  • bit[2:0] indicates the test status, when its value is 0, it indicates that the test has not been started; when its value is 1, it indicates that the test is completed; when its value is 2, it indicates that the test is in progress.
  • Bit[4:3] represents the test result, when its value is 0, it means the test passes; when its value is 1, it means the test fails.
  • Bit[30:5] represents reserved bits, which are used to reserve a certain number of bits for subsequent expansion.
  • Bit[47:31] represents the test mode ID, which is used to represent the ID of the currently executing test mode.
  • Bit[54:48] represents the hardware module detected in the current test mode, for example, it can indicate a logic circuit.
  • the STL in the terminal includes 20 test modes, which are respectively test mode 1-test mode 20.
  • the terminal also includes two tasks to be run, task A and task B, and based on the error detection method provided in this embodiment, it is determined that the test mode corresponding to task A is test mode 1-test mode 12, and the test mode corresponding to task B is For test mode 10-test 20.
  • FIG. 5 is a comparative schematic diagram of performing error detection according to an embodiment of the present application.
  • the process of performing error detection in the related art is specifically: during the normal operation of the terminal, the terminal performs task A first, and then performs task B. After the terminal starts to execute the task A for a certain time interval, the terminal starts to execute the 20 test modes included in the STL, that is, test mode 1-test mode 20. After executing the 20 test patterns, the terminal continues to execute task A until task A is executed, and continues to execute task B. During the execution of task B by the terminal, after a certain time interval from the last execution of the test mode, the terminal continues to execute the 20 test modes. That is to say, no matter what task is currently being executed by the terminal, the terminal needs to periodically execute 20 test modes, and it takes an excessively long time for the processor to execute the test modes.
  • the process of performing error detection in this solution is as follows: during the normal operation of the terminal, the terminal also executes task A first, and then executes task B. After the terminal starts to execute task A for a certain time interval, the terminal starts to execute 12 test modes corresponding to task A, namely test mode 1-test mode 12. After executing the 12 test modes, the terminal continues to execute task A until task A is executed, and continues to execute task B. During the process of executing task B by the terminal, after a certain time interval from the last execution of the test mode, the terminal executes 10 test modes corresponding to task B, namely test mode 10-test 20. That is to say, the terminal can select the test mode to be executed according to the currently executing task, instead of executing all the test modes in the STL, thereby shortening the time for the terminal to execute the test mode each time.
  • the terminal executes task A
  • the logic circuit in which the error occurs is a logic circuit that is frequently used when the terminal executes task A
  • the test mode for detecting the logic circuit is test mode 12 .
  • the terminal executes the test modes in sequence based on the order of test modes 1-20, and a total of 12 test modes (ie, test modes 1-12) are executed before the logic circuit in which the error occurs can be detected, and the error detection time is relatively short. long.
  • the logic circuit corresponding to the test mode 12 is the logic circuit that is used more frequently in task A
  • the execution order of the test mode 12 is relatively high, and the terminal can quickly detect based on the adjusted execution order.
  • FIG. 6 is a schematic diagram of a comparison of FDTI in different solutions provided in this embodiment of the present application. It can be seen from FIG. 6 that, compared with the related art, in this solution, the test mode is executed based on the adjusted execution order, which can effectively shorten the error detection time.
  • FIG. 7( a ) is a schematic diagram of the comparison of FDTI in different schemes when there is an error provided by the embodiment of the present application. It can be seen from Figure 7(a) that in the case of errors in the logic circuit, it takes nearly 0.7 milliseconds to detect errors by using the related technology, while it takes less than 0.4 milliseconds to detect errors using this scheme, which effectively shortens the error detection time. Referring to FIG. 7(b), FIG.
  • FIG. 7(b) is a schematic diagram comparing the total time consumption of error detection in different solutions provided by the embodiments of the present application.
  • the total time-consuming of detecting errors using related technologies is close to 4.5 milliseconds, while the total time-consuming of detecting errors using this scheme is less than 3.5 milliseconds, which can effectively shorten the time. Error detection time reduces processor load.
  • FIG. 8 is a schematic structural diagram of a terminal 800 according to an embodiment of the present application.
  • the terminal 800 includes a processing unit 801 and an obtaining unit 802 .
  • the obtaining unit 802 is configured to obtain a schedule table of the target task, where the schedule table is used to indicate at least one test mode, the at least one test mode is used to detect errors of the target logic circuit, and the target logic circuit is a logic circuit for executing the target task; the The processing unit 801 is configured to execute at least one test mode according to the schedule table to detect errors of the target logic circuit.
  • the target task is a running task.
  • At least one test mode in the scheduling table is determined based on a first mapping relationship and at least one instruction type
  • the first mapping relationship includes a mapping relationship between instruction types and test modes
  • at least one instruction type is determined based on a second mapping relationship and a machine instruction code set of the target task
  • the second mapping relationship includes a mapping relationship between machine instruction codes and instruction types
  • the machine instruction code set includes multiple machine instruction codes.
  • the schedule table further indicates an execution order of at least one test mode, and the execution order is determined based on the execution times of at least one instruction type corresponding to the machine instruction code set of the target task.
  • the terminal further includes: an obtaining unit 802; the obtaining unit 802 is configured to obtain a machine instruction code set of the target task, where the machine instruction code set includes multiple machine instruction codes; the processing unit 801 is further configured to : determine at least one instruction type corresponding to the machine instruction code set according to the second mapping relationship, where the second mapping relationship includes the mapping relationship between the machine instruction code and the instruction type; determine at least one test corresponding to the at least one instruction type according to the first mapping relationship mode, the first mapping relationship includes a mapping relationship between instruction types and test modes, at least one test mode is used to detect errors in logic circuits corresponding to at least one instruction type; a scheduling table is generated according to the at least one test mode.
  • the processing unit 801 is further configured to: determine the execution times of the instruction type in at least one instruction type according to the instruction types corresponding to the multiple machine instruction codes respectively; The execution order of the pattern; the schedule table is generated according to at least one test pattern and the execution order.
  • the processing unit 801 is further configured to: generate a third mapping relationship, where the third mapping relationship includes the mapping relationship between the target task and the schedule; and determine the schedule according to the target task and the third mapping relationship.
  • the schedule table is stored in shared memory, the shared memory is configured to store the schedule table of one or more tasks, and the shared memory can be accessed by multiple processors.
  • the processing unit 801 is further configured to: write at least one test mode into the sorting register according to the execution order; execute the test mode according to the execution order in the sorting register, and write the execution result of the test mode into the state register.
  • target tasks include processes or threads.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: a U disk, a removable hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk and other media that can store program codes.

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Abstract

本申请实施例公开了一种错误检测方法，涉及计算机技术领域。本申请实施例方法包括：获取目标任务的调度表，所述调度表用于指示至少一个测试模式，所述至少一个测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述目标任务的逻辑电路；根据所述调度表，执行所述至少一个测试模式，以检测所述目标逻辑电路的错误。通过确定目标任务的调度表，来执行该调度表中所包括的测试模式，能够避免执行软件测试库中的所有测试模式，从而降低了处理器的负载，有效地提高处理器的工作效率。

Description

一种错误检测方法及相关装置
本申请要求于2020年10月29日提交中国专利局、申请号为202011180288.7、发明名称为“一种错误检测方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种错误检测方法及相关装置。
背景技术
在计算机领域，数据处理装置可能会发生随机性的硬件故障，例如由集成电路中的短路或断路引起的永久性故障，或由暴露于自然辐射或粒子撞击引起的诸如位翻转之类的临时故障。
在某些安全性要求较高的应用领域中，例如安全性至关重要的汽车领域，为了确保功能安全，可以为处理器提供错误检测机制，以检测硬件错误并确保在发生硬件错误的情况下执行安全操作。
目前，相关技术中通过由处理器周期性的执行软件测试库(Software Test Library，STL)中的测试模式(test pattern)来检测逻辑电路的错误。然而，由于STL中包括有较多的测试模式，处理器周期性地执行STL中的测试模式会导致处理器的负载较大，即处理器需要花费较多的时间来检测错误，从而影响了处理器的工作效率。
发明内容
本申请提供了一种错误检测方法及相关装置，在执行错误检测的过程中，通过确定目标任务的调度表，来执行该调度表中所包括的测试模式。由于该调度表中仅包括用于检测目标逻辑电路的测试模式，该目标逻辑电路用于执行目标任务，因此基于该调度表来检测错误，能够避免执行软件测试库中的所有测试模式，从而降低了处理器的负载，有效地提高了处理器的工作效率。
本申请第一方面提供一种错误检测方法，应用于具有安全性要求领域中的终端，例如车载终端或航空航天中的控制终端。该方法包括：终端获取目标任务的调度表，该调度表可以是预置于终端中的或者由终端预先生成的，该目标任务例如可以为进程或者线程。该调度表包括至少一个测试模式，基于该至少一个测试模式，可以检测在执行目标任务时所依赖的目标逻辑电路的错误。最后，终端根据调度表，执行至少一个测试模式，以实现目标逻辑电路的错误检测。
本方案中，终端在执行错误检测的过程中，通过确定目标任务的调度表，来执行该调度表中所包括的测试模式。由于该调度表中仅包括用于检测目标逻辑电路的测试模式，该目标逻辑电路用于执行目标任务，因此基于该调度表来检测错误，能够避免执行软件测试库中的所有测试模式，从而降低了处理器的负载，有效地提高了处理器的工作效率。
在一些可能的实现方式中，该目标任务为运行中的任务。由于在终端运行目标任务的过程中，如果目标任务运行过程中需要使用到的逻辑电路发生了错误，那么终端运行该目 标任务时可能会由于逻辑电路的错误而产生安全风险。因此，基于该目标任务的调度表来执行测试模式，可以实现需要使用到的逻辑电路的错误检测，避免安全风险的产生。对于其他的逻辑电路，由于当前终端并没有执行相应的任务，即不需要使用到其他的逻辑电路，即便这部分逻辑电路发生了错误，也不会产生安全风险。这样，基于当前正在运行的任务的调度表来检测错误，能够在每次执行错误检测时只是检测单个任务的调度表中的测试模式，避免执行软件测试库中的所有测试模式，从而降低了处理器的负载，有效地提高了处理器的工作效率。在一些可能的实现方式中，终端可以在执行错误检测之前，可以预先生成待运行的任务对应的调度表。具体地，该方法还可以包括：终端获取目标任务的机器指令码集合，由于目标任务可以为进程或者线程，因此例如可以基于目标任务的可执行文件来获取相应的机器指令码集合，该机器指令码集合包括多个机器指令码(也称为机器码)。终端根据预置的第二映射关系确定机器指令码集合对应的至少一个指令类型，该第二映射关系包括机器指令码与指令类型之间的映射关系，在该映射关系中，一个机器指令码唯一对应一个指令类型。终端根据预置的第一映射关系确定至少一个指令类型对应的至少一个测试模式，该至少一个测试模式用于检测至少一个指令类型对应的逻辑电路的错误该第一映射关系包括指令类型与测试模式之间的映射关系，且在该映射关系中，一个指令类型可以对应一个或多个测试模式。终端再根据至少一个测试模式生成调度表。
也就是说，终端在获取到目标任务的机器指令码集合之后，基于预置的第二映射关系确定机器指令码集合对应的指令类型，以及基于第一映射关系确定指令类型对应的测试模式，从而得到目标任务对应的测试模式。
本方案中，终端基于预置的映射关系可以生成待运行任务对应的调度表，可以确保终端在获取到新的任务的情况下，能够生成该任务对应的调度表，保证了方案的可实现性。
在一些可能的实现方式中，该方法还可以包括：终端根据多个机器指令码分别对应的指令类型，确定至少一个指令类型中指令类型的执行次数。简单来说，终端可以统计每个指令类型所对应的机器指令码的个数，并将指令类型对应的机器指令码的个数确定为该指令类型的执行次数。根据该执行次数，终端可以确定至少一个测试模式中测试模式的执行顺序，以生成还包括有测试模式的执行顺序的调度表。即终端可以基于执行次数对测试模式进行降序排列，测试模式所对应的指令类型的执行次数越大，则该测试模式的执行顺序越靠前；反之，测试模式所对应的指令类型的执行次数越小，则该测试模式的执行顺序越靠后。
由于每次使用逻辑电路都可能导致逻辑电路发生错误，那么逻辑电路发生错误的几率相同的情况下，逻辑电路的使用次数越多，则逻辑电路发生错误的几率越高。即，同一指令类型的执行次数越多，逻辑电路的使用次数也越多，则逻辑电路发生错误的几率越高。因此，本实施例中基于目标任务的机器指令码所对应的指令类型的执行次数，来确定调度表中的测试模式的执行顺序，可以使得终端能够基于逻辑电路发生错误的几率来确定检测逻辑电路的顺序，即先检测发生错误几率更高的逻辑电路，从而缩短错误检测时间，提高错误检测的效率。
本方案中，终端通过在生成任务对应的调度表的过程中，基于任务对应的指令类型的 执行次数来确定测试模式的执行顺序，能够缩短错误检测时间，提高错误检测的效率。
在一些可能的实现方式中，该调度表可以是预置于终端中或终端预先生成的，该调度表中的至少一个测试模式是基于第一映射关系和至少一个指令类型确定的，第一映射关系包括指令类型与测试模式之间的映射关系，至少一个指令类型是基于第二映射关系和目标任务的机器指令码集合确定的，第二映射关系包括机器指令码与指令类型之间的映射关系，机器指令码集合包括多个机器指令码。
在一些可能的实现方式中，调度表还指示了至少一个测试模式的执行顺序，执行顺序是基于目标任务的机器指令码集合对应的至少一个指令类型的执行次数确定的。
在一些可能的实现方式中，在终端中存在有较多待运行的任务时，终端可以生成大量的调度表。因此，该方法还可以包括：终端生成第三映射关系，第三映射关系包括目标任务与调度表之间的映射关系。这样，在终端执行错误检测时，可以根据目标任务与第三映射关系确定调度表，保证了终端能够在执行错误检测的过程中快速确定目标任务所对应的调度表，提高执行错误检测的效率。
在一些可能的实现方式中，该调度表存储于共享内存中，共享内存被配置为存储一个或多个任务对应的调度表，且该共享内存可被多个处理器访问。在终端通过预留共享内存的方式为调度表提供配置区域的情况下，终端中的多个处理器均可以访问该共享内存中的调度表。这样，终端中的多个处理器均可以基于各自所执行的任务，单独地执行相应的错误检测。通过预留共享内存来为调度表提供配置区域，避免了为每个处理器单独提供调度表的配置区域，节省了存储资源的开销。
在一些可能的实现方式中，终端根据调度表，执行至少一个测试模式具体可以包括：终端根据该执行顺序，将至少一个测试模式写入排序寄存器；根据排序寄存器中的执行顺序执行测试模式，并将测试模式的执行结果写入状态寄存器。通过以硬件的方式来实现调度表中的测试模式的有序调度，可以提高测试模式调度的效率。
本申请第二方面提供一种终端，该终端包括：处理单元和获取单元；该获取单元用于获取目标任务的调度表，调度表用于指示至少一个测试模式，至少一个测试模式用于检测目标逻辑电路的错误，目标逻辑电路为用于执行目标任务的逻辑电路；该处理单元用于根据调度表，执行至少一个测试模式，以检测目标逻辑电路的错误。
在一些可能的实现方式中，目标任务为运行中的任务。
在一些可能的实现方式中，调度表中的至少一个测试模式是基于第一映射关系和至少一个指令类型确定的，第一映射关系包括指令类型与测试模式之间的映射关系，至少一个指令类型是基于第二映射关系和目标任务的机器指令码集合确定的，第二映射关系包括机器指令码与指令类型之间的映射关系，机器指令码集合包括多个机器指令码。
在一些可能的实现方式中，调度表还指示了至少一个测试模式的执行顺序，执行顺序是基于目标任务的机器指令码集合对应的至少一个指令类型的执行次数确定的。
在一些可能的实现方式中，该终端还包括：获取单元；该获取单元，用于获取目标任务的机器指令码集合，机器指令码集合包括多个机器指令码；处理单元还用于：根据第二映射关系确定机器指令码集合对应的至少一个指令类型，第二映射关系包括机器指令码与 指令类型之间的映射关系；根据第一映射关系确定至少一个指令类型对应的至少一个测试模式，第一映射关系包括指令类型与测试模式之间的映射关系，至少一个测试模式用于检测至少一个指令类型对应的逻辑电路的错误；根据至少一个测试模式生成调度表。
在一些可能的实现方式中，处理单元还用于：根据多个机器指令码分别对应的指令类型，确定至少一个指令类型中指令类型的执行次数；根据执行次数，确定至少一个测试模式中测试模式的执行顺序；根据至少一个测试模式以及执行顺序，生成调度表。
在一些可能的实现方式中，处理单元还用于：生成第三映射关系，第三映射关系包括目标任务与调度表之间的映射关系；根据目标任务与第三映射关系，确定调度表。
在一些可能的实现方式中，调度表存储于共享内存中，共享内存被配置为存储一个或多个任务的调度表，且共享内存可被多个处理器访问。
在一些可能的实现方式中，处理单元还用于：根据执行顺序，将至少一个测试模式写入排序寄存器；根据排序寄存器中的执行顺序执行测试模式，并将测试模式的执行结果写入状态寄存器。
在一些可能的实现方式中，目标任务包括进程或线程。
本申请第三方面提供一种终端，该终端包括：处理器；该处理器读取存储器中的计算机可读指令以使终端实现如第一方面任意一种实现方式的方法。
本申请第四方面提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序，当其在计算机上运行时，使得计算机执行如第一方面任意一种实现方式的方法。
本申请第五方面提供一种计算机程序产品，当其在计算机上运行时，使得计算机执行如第一方面任意一种实现方式的方法。
本申请第六方面提供一种芯片，包括一个或多个处理器。处理器中的部分或全部用于读取并执行存储器中存储的计算机程序，以执行上述任一方面任意可能的实现方式中的方法。可选地，该芯片该包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收需要处理的数据和/或信息，处理器从该通信接口获取该数据和/或信息，并对该数据和/或信息进行处理，并通过该通信接口输出处理结果。该通信接口可以是输入输出接口。本申请提供的方法可以由一个芯片实现，也可以由多个芯片协同实现。
附图说明
图1a为本申请实施例提供的一种FETI和FHTI的示意图；
图1b为本申请实施例提供的一种终端101的结构示意图；
图2为本申请实施例提供的一种错误检测方法200的流程示意图；
图3a为本申请实施例提供的一种调度表生成方法300的流程示意图；
图3b为本申请实施例提供的另一种调度表生成的流程示意图；
图3c为本申请实施例提供的另一种调度表生成的流程示意图；
图4为本申请实施例提供的一种排序寄存器和状态寄存器的结构示意图；
图5为本申请实施例提供的执行错误检测的对比示意图；
图6为本申请实施例提供的不同方案中FDTI的对比示意图；
图7(a)为本申请实施例提供的存在错误时不同方案中FDTI对比示意图；
图7(b)为本申请实施例提供的不同方案中错误检测的总耗时对比示意图；
图8为本申请实施例提供的一种终端800的结构示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或模块的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或模块，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或模块。在本申请中出现的对步骤进行的命名或者编号，并不意味着必须按照命名或者编号所指示的时间/逻辑先后顺序执行方法流程中的步骤，已经命名或者编号的流程步骤可以根据要实现的技术目的变更执行次序，只要能达到相同或者相类似的技术效果即可。
在计算机领域，数据处理装置可能会发生随机性的硬件故障，例如由集成电路中的短路或断路引起的永久性故障，或由暴露于自然辐射或粒子撞击引起的诸如位翻转之类的临时故障。
随着数据处理装置在大量的领域中广泛应用，为避免由于数据处理装置所发生的硬件故障而带来的损失，人们提出了“功能安全”的概念。功能安全是指不存在由于电子系统故障引起的不可接受的风险，其最终目标是防止由于电子系统故障而造成人员伤亡或带来巨大的财产损失。
在安全性要求较高的领域中，例如航空航天、交通运输以及医疗等领域，为满足功能安全的要求，均具有相应的安全机制。这些安全机制都必须保证系统在检测到错误后达到安全状态，以防止造成危害。例如，在汽车领域中，典型的安全风险通常是由防抱死系统或动力转向系统的电子控制单元发生错误而引起的。在防抱死系统或动力转向系统的电子控制单元发生错误的情况下，可能会导致汽车发生致命的碰撞。为保证系统能够达到安全状态以防止安全风险事件的发生，需要及时检测到已发生的错误并处理这些错误。
简单来说，当系统发生错误时，安全机制必须检测到系统所发生的错误并及时处理该错误，确保系统能够在产生危险之前达到安全状态。通常，从错误发生到检测到错误的时间间隔称为错误检测时间(Fault Detection Time Interval，FDTI)；从检测到错误到系统达到安全状态的间隔则称为错误处理时间(Fault Handle Time Interval，FHTI)。示例性地，可以参阅图1a，图1a为本申请实施例提供的一种FDTI和FHTI的示意图。为避免产生危险，在系统发生错误之后，系统必须在一定的期限内达到安全状态，即FDTI和FHTI之和 必须小于或等于某一时间阈值。因此，为了保证能够有足够长的FHTI来处理错误，以确保能够顺利地处理错误，尽可能地缩短FDTI则显得至关重要。
目前，相关技术中实现错误检测的一种方法为双核锁步(Dual-core Lockstep,DCLS)。DCLS的实现方法是：两个处理器运行同样的程序，并将两个处理器的输出结果输入至一个比较逻辑中，以比较两个处理器的输出结果是否相同。如果两个处理器的输出结果相同，则可以确定没有发生错误；如果两个处理器的输出结果不相同，则可以确定处理器发生了错误。这种错误检测的方式虽然能够有效地检测到错误，但是需要用到两个处理器来运行相同的程序，具有成本高和灵活性差的缺点。
因此，相关技术中提供了另一种基于软件的错误检测方法。该错误检测方法为通过由处理器周期性执行STL中的测试模式来检测逻辑电路的错误，相比于DCLS，该错误检测方法的成本较低且灵活性较高。然而，由于系统中往往具有较多的逻辑电路，为实现所有逻辑电路的错误检测，STL中通常包括有较多的测试模式。因此，处理器周期性地执行STL中的测试模式会导致处理器的负载较大，即处理器需要花费较多的时间来检测错误，从而影响了处理器的工作效率。
有鉴于此，本申请实施例提供了一种错误检测方法，该错误检测方法可以应用于终端中。终端在执行错误检测的过程中，通过确定当前运行的任务所对应的调度表，来执行该调度表中所包括的测试模式。由于该调度表中仅包括与该任务的机器指令码所对应的测试模式，因此终端基于该调度表来检测错误，能够避免执行软件测试库中的所有测试模式，从而降低了处理器的负载，有效地提高了处理器的工作效率。
本申请实施例所涉及的终端可以为具有安全性要求的领域中用于数据处理的设备。目前，一些终端的举例为：交通运输中的车载终端、航空航天中的控制终端、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程手术(remote medical surgery)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等。
可以参阅图1b，图1b为本申请实施例提供的一种终端101的结构示意图。
如图1b所示，终端101包括处理器103，处理器103和系统总线105耦合。处理器103可以是一个或者多个处理器，其中每个处理器都可以包括一个或多个处理器核。显示适配器(video adapter)107，显示适配器可以驱动显示器109，显示器109和系统总线105耦合。系统总线105通过总线桥111和输入输出(I/O)总线耦合。I/O接口115和I/O总线耦合。I/O接口115和多种I/O设备进行通信，比如输入设备117(如：触摸屏等)，多媒体盘(media tray)121,(例如，只读光盘(compact disc read-only memory，CD-ROM)，多媒体接口等)。收发器123(可以发送和/或接收无线电通信信号)，摄像头155(可以捕捉静态和动态数字视频图像)和外部USB端口125。其中，可选地，和I/O接口115相连接的接口可以是USB接口。
其中，处理器103可以是任何传统处理器，包括精简指令集计算(reduced instruction set Computing，RISC)处理器、复杂指令集计算(complex instruction set computing，CISC)处理 器或上述的组合。可选地，处理器可以是诸如ASIC的专用装置。
终端101可以通过网络接口129和软件部署服务器149通信。示例性的，网络接口129是硬件网络接口，比如，网卡。网络127可以是外部网络，比如因特网，也可以是内部网络，比如以太网或者虚拟私人网络(virtual private network，VPN)。可选地，网络127还可以是无线网络，比如WiFi网络，蜂窝网络等。
硬盘驱动器接口131和系统总线105耦合。硬件驱动接口和硬盘驱动器133相连接。系统内存135和系统总线105耦合。运行在系统内存135的数据可以包括终端101的操作系统(OS)137、应用程序143和调度表。
操作系统包括Shell 139和内核(kernel)141。Shell 139是介于使用者和操作系统的内核间的一个接口。shell是操作系统最外面的一层。shell管理使用者与操作系统之间的交互：等待使用者的输入，向操作系统解释使用者的输入，并且处理各种各样的操作系统的输出结果。
内核141由操作系统中用于管理存储器、文件、外设和系统资源的那些部分组成。内核141直接与硬件交互，操作系统内核通常运行进程，并提供进程间的通信，提供CPU时间片管理、中断、内存管理和IO管理等等。
示例性地，在终端101为车载终端的情况下，应用程序143包括控制汽车驾驶相关的程序，比如，管理自动驾驶的汽车和路上障碍物交互的程序，控制自动驾驶汽车路线或者速度的程序，控制自动驾驶汽车和路上其他自动驾驶汽车交互的程序。在一个实施例中，在需要执行应用程序143时，终端101可以从软件部署服务器149下载应用程序143。在一个实施例中，在终端101从软件部署服务器149下载应用程序143时，终端101也可以从软件部署服务器149下载与该应用程序143对应的调度表。
传感器153和终端101关联。传感器153用于探测终端101周围的环境。举例来说，传感器153可以探测动物，汽车，障碍物和人行横道等，进一步传感器153还可以探测上述动物，汽车，障碍物和人行横道等物体周围的环境，比如：动物周围的环境，例如，动物周围出现的其他动物，天气条件，周围环境的光亮度等。可选地，如果终端101位于自动驾驶的汽车上，传感器可以是雷达系统等。
以上介绍了本申请实施例所提供的错误检测方法的应用场景，以下将详细介绍该错误检测方法的执行过程。
可以参阅图2，图2为本申请实施例提供的一种错误检测方法200的流程示意图。如图2所示，该错误检测方法200包括以下的步骤。
步骤201，获取目标任务的调度表，调度表用于指示至少一个测试模式，至少一个测试模式用于检测目标逻辑电路的错误，目标逻辑电路为用于执行目标任务的逻辑电路。
本实施例中，在终端正常运行的过程中，终端可以周期性地执行该错误检测方法200，例如每隔30毫秒或50毫秒执行一次该错误检测方法200，以确保能够及时检测到已发生的错误。
在一个可能的实施例中，该目标任务可以为终端中正在运行的任务，例如可以为终端 中正在运行的进程或线程。终端确定目标任务的方式可以是通过获取当前正在运行的任务的标识(identifier，ID)或者基于当前正在运行的任务对应的数据结构来确定目标任务，例如基于线程ID确定当前正在运行的任务具体是哪一个线程。示例性地，在目标任务为进程的情况下，该目标任务例如可以为车辆视频检查进程、车速计算进程、雷达检测进程、车辆防抱死进程或胎压检测进程等进程。
本实施例中，对于终端中可运行的任意一个任务，均可以具有对应的调度表。这些调度表例如可以是预置于终端中的，也可以是由终端基于任务的机器指令码所生成的。因此，终端可以在多个调度表中确定目标任务所对应的调度表，例如在目标任务为进程的情况下，终端可以基于进程ID确定与其对应的调度表。
在目标任务所对应的调度表中，可以包括有至少一个测试模式，该至少一个测试模式与目标任务的机器指令码对应，该至少一个测试模式用于检测目标逻辑电路的错误。其中，该至少一个测试模式与目标任务的机器指令码对应是指基于该至少一个测试模式，可以实现执行目标任务的机器指令码时所依赖的目标逻辑电路的错误检测。
简单来说，终端在执行机器指令码时，需要依赖于终端中的逻辑电路，即基于逻辑电路来执行机器指令码。因此，在确定了目标任务的机器指令码对应的至少一个测试模式的情况下，对于终端执行该目标任务的机器指令码时所使用到的逻辑电路，均可以基于该至少一个测试模式来实现错误的检测。
可以理解的是，在终端运行目标任务的过程中，如果目标任务运行过程中需要使用到的逻辑电路发生了错误，那么终端运行该目标任务时可能会由于逻辑电路的错误而产生安全风险。因此，基于该目标任务对应的调度表来执行测试模式，可以实现需要使用到的逻辑电路的错误检测，避免安全风险的产生。对于其他的逻辑电路，由于当前终端并没有执行相应的任务，即不需要使用到其他的逻辑电路，因此即便这部分逻辑电路发生了错误，也不会产生安全风险。
在一个可能的实施例中，调度表中的至少一个测试模式是基于第一映射关系和至少一个指令类型确定的，第一映射关系包括指令类型与测试模式之间的映射关系，至少一个指令类型是基于第二映射关系和目标任务的机器指令码集合确定的，第二映射关系包括机器指令码与指令类型之间的映射关系，机器指令码集合包括多个机器指令码。
在一个可能的实施例中，目标任务对应的调度表还可以指示至少一个测试模式的执行顺序，该执行顺序是基于目标任务的机器指令码所对应的指令类型的执行次数确定的。
一个任务通常包括有多个机器指令码，不同的机器指令码可能属于不同的指令类型，也可能属于相同的指令类型。指令类型相同的机器指令码通常依赖于相同的逻辑电路来执行，指令类型不同的机器指令码则依赖于不同的逻辑电路来执行。那么，在目标任务包括有指令类型相同的多个机器指令码的情况下，终端在执行该目标任务的过程中，需要使用到多次该指令类型所对应的逻辑电路。也就是说，在每次使用逻辑电路都可能导致逻辑电路发生错误，且逻辑电路发生错误的几率相同的情况下，逻辑电路的使用次数越多，则逻辑电路发生错误的几率越高。换句话说，同一指令类型的执行次数越多，逻辑电路的使用次数也越多，则逻辑电路发生错误的几率越高。因此，本实施例中可以基于目标任务的机 器指令码所对应的指令类型的执行次数，来确定调度表中的测试模式的执行顺序。即指令类型的执行次数越多，那么该指令类型对应的测试模式的执行顺序越靠前，以便于终端能够基于逻辑电路发生错误的几率来确定检测逻辑电路的顺序，从而缩短错误检测时间，提高错误检测的效率。
例如，假设目标任务包括6个机器指令码，该6个机器指令码中分别有3个属于指令类型1的机器指令码、2个属于指令类型0的机器指令码以及1个属于指令类型2的机器指令码。那么，指令类型0、指令类型1以及指令类型2的执行次数分别为2、3、1。其中，目标任务对应的调度表包括有分别与指令类型0、指令类型1和指令类型2对应的测试模式A、测试模式B以及测试模式C，该调度表还可以包括有上述三个测试模式的执行顺序，该测试模式的执行顺序是基于测试模式对应的指令类型的执行次数确定的。即测试模式的执行顺序为：测试模式B-测试模式A-测试模式C。这样，终端在执行错误检测的过程中，可以基于该执行顺序依次执行测试模式B、测试模式A和测试模式C。
步骤202，根据调度表，执行至少一个测试模式，以检测目标逻辑电路的错误。
在获取到调度表之后，终端依次执行调度表所指示的一个或多个测试模式。并且，在执行完毕调度表所指示的测试模式后，终端可以确定当前执行错误检测的周期结束，终端可以在间隔一定的时间之后再次执行该错误检测方法200。此外，在调度表还包括测试模式的执行顺序的情况下，终端还可以是基于调度表所指示的执行顺序依次执行调度表中的一个或多个测试模式。
本实施例中，终端在执行错误检测的过程中，通过获取目标任务的调度表，来执行该调度表中所包括的测试模式。由于该调度表中仅包括用于检测目标逻辑电路的测试模式，因此终端基于该调度表来检测错误，能够避免执行软件测试库中的所有测试模式，从而降低了处理器的负载，有效地提高了处理器的工作效率。此外，在调度表还包括有基于指令类型的执行次数所确定的测试模式的执行顺序时，终端基于该执行顺序来执行测试模式，能够实现基于逻辑电路发生错误的几率来确定检测逻辑电路的顺序，从而缩短错误检测时间，提高错误检测的效率。
以上介绍了终端基于目标任务对应的调度表执行相应的测试模式，以实现错误检测的过程，以下将详细介绍终端生成调度表的过程。
可以参阅图3a，图3a为本申请实施例提供的一种调度表生成方法300的流程示意图。如图3a所示，该调度表生成方法300包括以下的步骤。
步骤301，获取目标任务的机器指令码集合，机器指令码集合包括多个机器指令码。
本实施例中，终端在执行错误检测之前，可以预先生成终端中待运行的任务所对应的调度表，以便于终端在执行错误检测的过程中能够获取到目标任务所对应的调度表。
应理解，在终端执行错误检测之前，上述的目标任务为终端中的一个待运行的任务，终端可以通过获取目标任务的可执行文件来获取目标任务的机器指令码集合。示例性地，在目标任务为应用程序时，终端中安装有该应用程序，该应用程序的可执行文件例如可以为“.exe格式文件”、“.sys格式文件”、“.com格式文件”等类型文件，终端基于该应用程序的 可执行文件可以获得该应用程序对应的机器指令码集合。
一般来说，对于目标任务而言，该目标任务的可执行文件通常包括多个机器指令码，即该机器指令码集合中包括多个机器指令码，终端通过执行该多个机器指令码来实现目标任务的运行。
步骤302，根据第二映射关系确定机器指令码集合对应的至少一个指令类型，该第二映射关系包括机器指令码与指令类型之间的映射关系。
可以理解的是，对于任意一个机器指令码，均有对应的指令类型，即可以将任一个机器指令码归类为某一指令类型。其中，指令类型例如可以包括数据传送类指令、定点算术运算类指令、按位运算类指令、程序控制类指令等类型。由于不同的机器指令码可以对应于同一个指令类型，也可以是对应于不同的指令类型，因此基于机器指令码集合中的每个机器指令码可以确定至少一个指令类型。
在终端中可以预置有第二映射关系，该第二映射关系包括了机器指令码与指令类型之间的映射关系，基于该第二映射关系可以确定机器指令码集合中的每个机器指令码所对应的指令类型。具体地，该第二映射关系的一种可能的示例如表1所示：
表1
机器指令码0 指令类型0
机器指令码1、机器指令码2 指令类型1
… …
机器指令码M 指令类型N
由表1可知，对于任意一个机器指令码，均有唯一对应的一个指令类型；而对于一个指令类型，则可以对应有一个或多个机器指令码。这样，终端基于机器指令码集合所确定的指令类型的个数等于或者小于机器指令码集合中机器指令码的个数。在指令类型的个数小于机器指令码的个数的情况下，存在有多个机器指令码对应于相同的指令类型，即指令类型的执行次数则为其对应的机器指令码的个数。
具体地，该第二映射关系可以是基于终端中的处理器对应的指令集手册来建立的。一般来说，在计算机领域中，指示计算机硬件执行某种运算、处理功能的命令称为指令，该指令的表现方式可以为上述的机器指令码。指令是计算机运行的最小的功能单位，而硬件的作用是完成每条指令规定的功能。终端上全部指令的集合即为该终端的指令集，是终端上全部功能的体现。通常，一个终端上的指令集反映了该终端的全部功能，终端的类型不同，其指令集也可能是不相同的，因而功能也不同。指令集的设置和终端的硬件电路密切相关，而指令集手册则可以指示终端能够执行的指令集，以及指令集与终端中的硬件电路之间的关系。基于指令集手册，可以确定指令与硬件电路之间的关系，以及确定指令集中的每个指令所属的指令类型，从而建立机器指令码与指令类型之间的映射关系。
步骤303，根据第一映射关系确定至少一个指令类型对应的至少一个测试模式，第一映射关系包括指令类型与测试模式之间的映射关系，至少一个测试模式用于检测至少一个指令类型对应的逻辑电路的错误。
由于每种类型的指令都可以执行在某一个逻辑电路中，且每种类型的指令所对应的逻辑电路是固定的。因此，可以认为在确定了某一个机器指令码对应的指令类型之后，即可 唯一确定用于执行该机器指令码的逻辑电路。那么，在确定了机器指令码集合对应的至少一个指令类型之后，通过确定该至少一个指令类型对应的测试模式，即可基于所确定的测试模式实现目标任务所使用到的逻辑电路的检测。
在终端中可以预置有第一映射关系，该第一映射关系包括了指令类型与测试模式之间的映射关系，基于该第一映射关系可以每个指令类型所对应的测试模式。具体地，该第一映射关系的一种可能的示例如表2所示：
表2
指令类型0 测试模式组0
指令类型1 测试模式组1
… …
指令类型N 测试模式组N
由表2可知，对于任意一种指令类型，均有对应的测试模式组，每个测试模式组中可以包括有一个或多个测试模式，即任意一种指令类型均有对应的一个或多个测试模式。并且，每种测试模式均是用于检测特定的逻辑电路。因此，在终端确定了机器指令码所属的指令类型之后，则可以基于指令类型确定需要执行的测试模式。
具体地，该第一映射关系可以是基于STL的设计文档得到的。示例性地，基于STL的设计文档，可以确定STL中所包括的所有测试模式的相关信息，例如确定测试模式所检测的逻辑电路。这样，在确定了测试模式所检测的逻辑电路以及指令类型需要使用到的逻辑电路的情况下，则可以建立第一映射关系，以建立逻辑电路相同的指令类型与测试模式之间的映射关系。
步骤304，根据至少一个测试模式生成调度表。
在一个可能的实施例中，终端可以是只基于确定得到的至少一个测试模式生成该调度表，即得到的调度表中只包括该至少一个测试模式，而没有指定测试模式之间的执行顺序。
在另一个可能的实施例中，终端还可以确定该至少一个测试模式的执行顺序，并基于该执行顺序生成调度表，以使得调度表中还可以包括测试模式之间的执行顺序。
示例性地，在根据第二映射关系确定了多个机器指令码对应的指令类型之后，终端可以根据多个机器指令码分别对应的指令类型，确定该至少一个指令类型中的每个指令类型的执行次数。简单来说，终端可以统计每个指令类型所对应的机器指令码的个数，并将指令类型对应的机器指令码的个数确定为该指令类型的执行次数。根据执行次数，终端可以确定该至少一个测试模式中测试模式的执行顺序。由于每个测试模式均有唯一对应的指令类型，且每个指令类型均有其对应的执行次数，则终端可以基于测试模式对应的指令类型的执行次数来确定测试模式的执行顺序。即终端可以基于执行次数对测试模式进行降序排列，测试模式所对应的指令类型的执行次数越大，则该测试模式的执行顺序越靠前；反之，测试模式所对应的指令类型的执行次数越小，则该测试模式的执行顺序越靠后。最后，终端可以根据该至少一个测试模式以及执行顺序，生成包括有测试模式的执行顺序的调度表，以使得终端在执行错误检测时，能够基于调度表中所指示的执行顺序依次执行测试模式。
以上步骤301-304描述了终端基于目标任务生成对应的调度表的过程，在实际应用中， 终端可以是在获取到待运行的多个任务之后，基于类似的流程，分别确定该多个任务对应的调度表，从而使得终端中可以保存有每个任务对应的调度表。这样一来，终端在执行任意一个任务时，均可以查找得到该任务所对应的调度表，以实现该任务对应的错误检测。
可以理解的是，在终端中存在有较多待运行的任务时，终端可以生成大量的调度表。因此，为了使得终端能够在执行错误检测的过程中快速确定目标任务所对应的调度表，终端在生成每个任务对应的调度表之后，还可以建立任务与调度表之间的映射关系。示例性地，终端可以生成第三映射关系，该第三映射关系包括待运行的任务与调度表之间的映射关系。终端在新生成任意一个调度表之后，终端可以更新该第三映射关系，以增加新生成的调度表与任务之间的映射关系，从而使得终端所生成的第三映射关系能够包括终端中的每个待运行任务与其对应的调度表之间的映射关系。
在一个可能的实施例中，终端可以在生成调度表之后，为每个新生成的调度表分配一个唯一的ID，并且建立任务ID与调度表ID之间的映射关系，以得到第三映射关系。这样一来，终端可以基于任务ID以及第三映射关系，快速确定对应的调度表ID，并基于该调度表ID查找得到对应的调度表。具体地，该第三映射关系的一种可能的示例如表3所示：
表3
任务0 调度表0
任务1 调度表1
… …
任务N 调度表N
此外，终端也可以是在新生成调度表之后，为该新生成的调度表分配相应的地址空间，以得到存储该调度表的地址空间。这样，终端可以建立任务ID与调度表的地址空间之间的映射关系，以得到第三映射关系。也就是说，终端可以基于任务ID与该第三映射关系，快速确定与之对应的调度表的地址空间，从而能够在该地址空间查找得到对应的调度表。
可以参阅图3b，图3b为本申请实施例提供的另一种调度表生成的流程示意图。如图3b所示，终端可以获取到位于终端中的任务1、任务2…任务N等N个任务；然后，终端分别对这些任务执行机器指令码扫描，以确定每个任务对应的机器指令码。基于每个任务的机器指令码，终端可以在STL中挑拣与每个任务的机器指令码对应的测试模式，并且对这些挑拣得到的测试模式进行排序，从而得到每个任务的调度表，即任务1的调度表1、任务2的调度表2…任务N的调度表N。
可以参阅图3c，图3c为本申请实施例提供的另一种调度表生成的流程示意图。如图3c所示，图3c以处理芯片为Hi1951Taishan为例，对生成调度表的过程进行介绍。其中，Hi1951Taishan为华为公司的一种处理芯片，该处理芯片中可以包括多个处理器，能够并行地执行不同的任务。如图3c所示，首先，可以基于Hi1951Taishan的处理器架构指令集，确定机器指令码与指令类型之间的映射关系，得到映射表A；以及，基于Hi1951Taishan的测试模式设计方案，确定指令类型与测试模式之间的映射关系，得到映射表B。然后，基于映射表A和目标任务的可执行文件，指令扫描器可以确定得到可执行文件中每个机器指令码对应的指令类型，从而得到可执行文件对应的所有指令类型。在得到可执行文件对应的所有指令类型之后，可以基于映射表B确定这些指令类型分别对应的测试模式，并且 根据指令类型的执行次数给这些测试模式进行排序。即在STL中挑拣并排序测试模式，以得到目标任务对应的调度表。
以上介绍了终端基于任务的机器指令码集合生成调度表的过程，以下将详细介绍在生成调度表之后，终端如何配置调度表的过程。
在一个可能的实施例中，终端可以通过预留共享内存的方式，为调度表提供配置区域。
示例性地，终端可以通过设备树二进制(device tree binary，DTB)配置预留部分内存空间作为共享内存，并得到该共享内存的引用句柄，该引用句柄包括该共享内存的地址、大小以及访问权限等配置信息。终端在生成调度表之后，终端可以为该调度表在该共享内存中分配一个地址空间，并将调度表存储至该共享内存中的地址空间。此外，终端还可以基于该地址空间生成该调度表的配置信息，例如生成地址空间的索引与调度表ID之间的映射关系，以使得终端在执行错误检测时，能够基于调度表ID确定地址空间的索引，从而在该地址空间查找到该调度表。
在终端通过预留共享内存的方式为调度表提供配置区域的情况下，终端中的多个处理器均可以访问该共享内存中的调度表。这样，终端中的多个处理器均可以基于各自所执行的任务，单独地执行相应的错误检测。通过预留共享内存来为调度表提供配置区域，避免了为每个处理器单独提供调度表的配置区域，节省了存储资源的开销。
在另一个可能的实施例中，终端可以通过硬件的方式来实现调度表的调度。
示例性地，在终端的处理器中可以预先设计有两个用于调度调度表的寄存器，分别为排序寄存器和状态寄存器。在终端执行错误检测的过程中，终端确定目标任务对应的调度表之后，终端可以根据该调度表中的测试模式的执行顺序，将调度表中的测试模式有序地写入排序寄存器。然后，终端可以根据排序寄存器中的执行顺序执行测试模式，并将测试模式的执行结果写入状态寄存器。
示例性地，可以参阅图4，图4为本申请实施例提供的一种排序寄存器和状态寄存器的结构示意图。如图4所示，排序寄存器和状态寄存器均为64比特(bit)的寄存器。在排序寄存器中，64bit分成为16个4bit，每4bit可以用于表示一组测试模式的ID。终端可以根据调度表中的测试模式的执行顺序，将调度表中的测试模式有序地写入排序寄存器中，并且在执行错误检测时，根据排序寄存器中的执行顺序有序地执行测试模式。
在状态寄存器中，状态寄存器的64bit被分为多个部分。其中，bit[2:0]表示测试状态，其值为0时表示未开始测试；其值为1时表示完成测试；其值为2时表示测试进行中。Bit[4:3]表示测试结果，其值为0时表示测试通过；其值为1时表示测试失败。Bit[30:5]表示预留位，用于预留一定的位数，以便于后续拓展。Bit[47:31]表示测试模式ID，用于表示当前正在执行的测试模式的ID。Bit[54:48]表示当前测试模式所检测的硬件模块，例如可以指示某一逻辑电路。
以上介绍了终端如何执行错误检测的过程，为便于理解，以下将结合例子详细介绍终端执行上述的错误检测方法所带来的有益效果。
假设，终端中的STL包括有20个测试模式，分别为测试模式1-测试模式20。终端中还包括有任务A和任务B两个待运行的任务，并且基于本实施例所提供的错误检测方法确定任务A对应的测试模式为测试模式1-测试模式12，任务B对应的测试模式为测试模式10-测试20。
可以参阅图5，图5为本申请实施例提供的执行错误检测的对比示意图。如图5中(a)所示，相关技术中执行错误检测的过程具体为：在终端正常运行的过程中，终端先执行任务A，然后再执行任务B。在间隔终端开始执行任务A一定时间间隔之后，终端开始执行STL所包括的20个测试模式，即测试模式1-测试模式20。在执行完该20个测试模式之后，终端继续执行任务A，直至任务A执行完毕，并继续执行任务B。在终端执行任务B的过程中，距离上一次执行测试模式一定时间间隔之后，终端继续执行该20个测试模式。也就是说，无论当前终端正在执行的是什么任务，终端都需要周期性地执行完20个测试模式，需要占用处理器过长的时间来执行测试模式。
如图5中(b)所示，本方案中执行错误检测的过程具体为：在终端正常运行的过程中，终端同样是先执行任务A，然后再执行任务B。在间隔终端开始执行任务A一定时间间隔之后，终端开始执行任务A所对应的12个测试模式，即测试模式1-测试模式12。在执行完该12个测试模式之后，终端继续执行任务A，直至任务A执行完毕，并继续执行任务B。在终端执行任务B的过程中，距离上一次执行测试模式一定时间间隔之后，终端则执行任务B对应的10个测试模式，即测试模式10-测试20。也就是说，终端可以根据当前正在执行的任务来选择需要执行的测试模式，而并非是执行STL中所有的测试模式，从而缩短了终端每次执行测试模式的时间。
此外，假设终端在执行任务A的过程中发生了错误，且发生错误的逻辑电路为终端执行任务A时使用次数较多的逻辑电路，用于检测该逻辑电路的测试模式为测试模式12。那么，在相关技术中，终端基于测试模式1-20的顺序依次执行测试模式，一共执行了12个测试模式(即测试模式1-12)才能够检测到发生错误的逻辑电路，错误检测时间较长。然而，在本方案中，由于测试模式12对应的逻辑电路为任务A中使用次数较多的逻辑电路，因此，测试模式12的执行顺序比较靠前，终端基于调整后的执行顺序，能够快速检测到发生错误的逻辑电路。具体地，可以参阅图6，图6为本申请实施例提供的不同方案中FDTI的对比示意图。由图6可知，相对于相关技术，本方案中基于调整后的执行顺序来执行测试模式，能够有效地缩短错误检测时间。
此外，本实施例还提供了在逻辑电路存在错误的情况下，采用相关技术和本方案进行错误检测时的FDTI对比；以及在逻辑电路不存在错误的情况下，采用相关技术和本方案进行错误检测时的总耗时对比。可以参阅图7(a)，图7(a)为本申请实施例提供的存在错误时不同方案中FDTI对比示意图。由图7(a)可知，在逻辑电路存在错误的情况下，采用相关技术检测错误耗时接近0.7毫秒，而采用本方案检测错误耗时则不到0.4毫秒，有效地缩短了错误检测时间。可以参阅图7(b)，图7(b)为本申请实施例提供的不同方案中错误检测的总耗时对比示意图。由图7(b)可知，在逻辑电路不存在错误的情况下，采用相关技术检测错误总耗时接近4.5毫秒，而采用本方案检测错误总耗时则不到3.5毫秒， 能够有效地缩短了错误检测时间，降低了处理器的负载。
在图1至图7(b)所对应的实施例的基础上，为了更好的实施本申请实施例的上述方案，下面还提供用于实施上述方案的相关设备。具体可以参阅图8，图8为本申请实施例提供的一种终端800的结构示意图，该终端800包括：处理单元801和获取单元802。该获取单元802用于获取目标任务的调度表，调度表用于指示至少一个测试模式，至少一个测试模式用于检测目标逻辑电路的错误，目标逻辑电路为用于执行目标任务的逻辑电路；该处理单元801用于根据调度表，执行至少一个测试模式，以检测目标逻辑电路的错误。
在一些可能的实现方式中，目标任务为运行中的任务。
在一些可能的实现方式中，调度表中的至少一个测试模式是基于第一映射关系和至少一个指令类型确定的，第一映射关系包括指令类型与测试模式之间的映射关系，至少一个指令类型是基于第二映射关系和目标任务的机器指令码集合确定的，第二映射关系包括机器指令码与指令类型之间的映射关系，机器指令码集合包括多个机器指令码。
在一些可能的实现方式中，调度表还指示了至少一个测试模式的执行顺序，执行顺序是基于目标任务的机器指令码集合对应的至少一个指令类型的执行次数确定的。在一些可能的实现方式中，该终端还包括：获取单元802；该获取单元802，用于获取目标任务的机器指令码集合，机器指令码集合包括多个机器指令码；处理单元801还用于：根据第二映射关系确定机器指令码集合对应的至少一个指令类型，第二映射关系包括机器指令码与指令类型之间的映射关系；根据第一映射关系确定至少一个指令类型对应的至少一个测试模式，第一映射关系包括指令类型与测试模式之间的映射关系，至少一个测试模式用于检测至少一个指令类型对应的逻辑电路的错误；根据至少一个测试模式生成调度表。
在一些可能的实现方式中，处理单元801还用于：根据多个机器指令码分别对应的指令类型，确定至少一个指令类型中指令类型的执行次数；根据执行次数，确定至少一个测试模式中测试模式的执行顺序；根据至少一个测试模式以及执行顺序，生成调度表。
在一些可能的实现方式中，处理单元801还用于：生成第三映射关系，第三映射关系包括目标任务与调度表之间的映射关系；根据目标任务与第三映射关系，确定调度表。
在一些可能的实现方式中，调度表存储于共享内存中，共享内存被配置为存储一个或多个任务的调度表，且共享内存可被多个处理器访问。
在一些可能的实现方式中，处理单元801还用于：根据执行顺序，将至少一个测试模式写入排序寄存器；根据排序寄存器中的执行顺序执行测试模式，并将测试模式的执行结果写入状态寄存器。
在一些可能的实现方式中，目标任务包括进程或线程。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组 件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器、随机存取存储器、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (20)

  1. 一种错误检测方法，其特征在于，包括：
    获取目标任务的调度表，所述调度表用于指示至少一个测试模式，所述至少一个测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述目标任务的逻辑电路；
    根据所述调度表，执行所述至少一个测试模式，以检测所述目标逻辑电路的错误。
  2. 根据权利要求1所述的错误检测方法，其特征在于，所述目标任务为运行中的任务。
  3. 根据权利要求1或2所述的错误检测方法，其特征在于，所述调度表中的所述至少一个测试模式是基于第一映射关系和至少一个指令类型确定的，所述第一映射关系包括指令类型与测试模式之间的映射关系，所述至少一个指令类型是基于第二映射关系和所述目标任务的机器指令码集合确定的，所述第二映射关系包括机器指令码与指令类型之间的映射关系，所述机器指令码集合包括多个机器指令码。
  4. 根据权利要求1至3任意一项所述的错误检测方法，其特征在于，所述调度表还指示了所述至少一个测试模式的执行顺序，所述执行顺序是基于所述目标任务的机器指令码集合对应的至少一个指令类型的执行次数确定的。
  5. 根据权利要求1或2所述的错误检测方法，其特征在于，所述方法还包括：
    获取所述目标任务的机器指令码集合，所述机器指令码集合包括多个机器指令码；
    根据第二映射关系确定所述机器指令码集合对应的至少一个指令类型，所述第二映射关系包括机器指令码与指令类型之间的映射关系；
    根据第一映射关系确定所述至少一个指令类型对应的至少一个测试模式，所述第一映射关系包括指令类型与测试模式之间的映射关系，所述至少一个测试模式用于检测所述至少一个指令类型对应的逻辑电路的错误；
    根据所述至少一个测试模式生成所述调度表。
  6. 根据权利要求5所述的错误检测方法，其特征在于，所述方法还包括：
    根据所述多个机器指令码分别对应的指令类型，确定所述至少一个指令类型中指令类型的执行次数；
    根据所述执行次数，确定所述至少一个测试模式中测试模式的执行顺序；
    所述根据所述至少一个测试模式生成所述调度表，包括：
    根据所述至少一个测试模式以及所述执行顺序，生成所述调度表。
  7. 根据权利要求1至6任意一项所述的错误检测方法，其特征在于，所述调度表存储于共享内存中，所述共享内存被配置为存储一个或多个任务的调度表，且所述共享内存可 被多个处理器访问。
  8. 根据权利要求4或6所述的错误检测方法，其特征在于，所述根据所述调度表，执行所述至少一个测试模式，包括：
    根据所述执行顺序，将所述至少一个测试模式写入排序寄存器；
    根据所述排序寄存器中的执行顺序执行测试模式，并将测试模式的执行结果写入状态寄存器。
  9. 根据权利要求1至8任意一项所述的错误检测方法，其特征在于，所述目标任务包括进程或线程。
  10. 一种终端，其特征在于，包括处理器；所述处理器用于：
    获取目标任务的调度表，所述调度表用于指示至少一个测试模式，所述至少一个测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述目标任务的逻辑电路；
    根据所述调度表，执行所述至少一个测试模式，以检测所述目标逻辑电路的错误。
  11. 根据权利要求10所述的终端，其特征在于，所述目标任务为运行中的任务。
  12. 根据权利要求10或11所述的终端，其特征在于，所述调度表中的所述至少一个测试模式是基于第一映射关系和至少一个指令类型确定的，所述第一映射关系包括指令类型与测试模式之间的映射关系，所述至少一个指令类型是基于第二映射关系和所述目标任务的机器指令码集合确定的，所述第二映射关系包括机器指令码与指令类型之间的映射关系，所述机器指令码集合包括多个机器指令码。
  13. 根据权利要求10至12任意一项所述的终端，其特征在于，所述调度表还指示了所述至少一个测试模式的执行顺序，所述执行顺序是基于所述目标任务的机器指令码集合对应的至少一个指令类型的执行次数确定的。
  14. 根据权利要求10或11所述的终端，其特征在于，所述处理器还用于：
    获取所述目标任务的机器指令码集合，所述机器指令码集合包括多个机器指令码；
    根据第二映射关系确定所述机器指令码集合对应的至少一个指令类型，所述第二映射关系包括机器指令码与指令类型之间的映射关系；
    根据第一映射关系确定所述至少一个指令类型对应的至少一个测试模式，所述第一映射关系包括指令类型与测试模式之间的映射关系，所述至少一个测试模式用于检测所述至少一个指令类型对应的逻辑电路的错误；
    根据所述至少一个测试模式生成所述调度表。
  15. 根据权利要求14所述的终端，其特征在于，所述处理器还用于：
    根据所述多个机器指令码分别对应的指令类型，确定所述至少一个指令类型中指令类型的执行次数；
    根据所述执行次数，确定所述至少一个测试模式中测试模式的执行顺序；
    根据所述至少一个测试模式以及所述执行顺序，生成所述调度表。
  16. 根据权利要求10至15任意一项所述的终端，其特征在于，所述调度表存储于共享内存中，所述共享内存被配置为存储一个或多个任务的调度表，且所述共享内存可被多个处理器访问。
  17. 根据权利要求13或15所述的终端，其特征在于，所述处理器还用于：
    根据所述执行顺序，将所述至少一个测试模式写入排序寄存器；
    根据所述排序寄存器中的执行顺序执行测试模式，并将测试模式的执行结果写入状态寄存器。
  18. 根据权利要求10至17任意一项所述的终端，其特征在于，所述目标任务包括进程或线程。
  19. 一种计算机可读存储介质，其特征在于，包括计算机可读指令，当所述计算机可读指令在计算机上运行时，使得所述计算机执行如权利要求1至9中任一项所述的方法。
  20. 一种计算机程序产品，其特征在于，包括计算机可读指令，当所述包括计算机可读指令，在计算机上运行时，使得所述计算机执行如权利要求1至9任一项所述的方法。
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