WO2022095874A1 - 电路板 - Google Patents

电路板 Download PDF

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Publication number
WO2022095874A1
WO2022095874A1 PCT/CN2021/128318 CN2021128318W WO2022095874A1 WO 2022095874 A1 WO2022095874 A1 WO 2022095874A1 CN 2021128318 W CN2021128318 W CN 2021128318W WO 2022095874 A1 WO2022095874 A1 WO 2022095874A1
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WO
WIPO (PCT)
Prior art keywords
signal
holes
circuit board
hole
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/128318
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English (en)
French (fr)
Inventor
赵丽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing ZTE New Software Co Ltd
Original Assignee
Nanjing ZTE New Software Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing ZTE New Software Co Ltd filed Critical Nanjing ZTE New Software Co Ltd
Priority to US18/033,585 priority Critical patent/US12289832B2/en
Priority to JP2023525595A priority patent/JP7668354B2/ja
Priority to EP21888571.3A priority patent/EP4236638B1/en
Publication of WO2022095874A1 publication Critical patent/WO2022095874A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09645—Patterning on via walls; Plural lands around one hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0207—Partly drilling through substrate until a controlled depth, e.g. with end-point detection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Definitions

  • the embodiments of the present disclosure relate to the technical field of circuits, and in particular, to circuit boards.
  • Connectors are one of the core basic components necessary for the electrical connection of circuit systems, and are widely used in industrial, automotive, communications and other products. With the development of technology, especially 5G technology, connectors are also developing in the direction of high speed, high frequency and high density. With the development of connectors, more and more signals need to be introduced into the internal circuits of the connector.
  • the circuit board connected to the connector can only ensure that the signal of the connector can be introduced into the internal circuit of the circuit board by increasing the number of trace layers. , but the more layers of the board, the higher the cost of the board.
  • An embodiment of the present disclosure provides a circuit board, which includes a signal hole array matched with a terminal array of a connector, and at least some of the signal holes in the signal hole array are first signal holes;
  • the first signal hole is a blind hole, which is connected to a part of the wiring layer of the circuit board, and is connected to the auxiliary conductive structure through the auxiliary line located in the auxiliary wiring layer;
  • the auxiliary conductive structure is at least connected to the auxiliary wiring layer and the wiring layer that is not connected to the first signal hole, and is connected to the signal lead wire located in the main wiring layer;
  • the signal lead lines extend out of the area where the signal hole array is located.
  • FIG. 1 is a schematic diagram of the layout of a signal lead-out line in the related art
  • FIG. 2 is a schematic structural diagram of a circuit board in the related art
  • FIG. 3 is a schematic structural diagram of a circuit board according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of a circuit board provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a relationship between hole and line distances of a circuit board according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of fabrication of an auxiliary conductive structure of a circuit board according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure may be described with reference to plan views and/or cross-sectional views with the aid of idealized schematic illustrations of the present disclosure. Accordingly, example illustrations may be modified according to manufacturing techniques and/or tolerances.
  • Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes.
  • the regions illustrated in the figures have schematic properties and the shapes of regions illustrated in the figures are illustrative of the specific shapes of regions of elements and are not intended to be limiting.
  • the pins (also called pins) of the connector may be referred to as signal pins (terminals), and there are signal holes on the circuit board corresponding to the signal pins of the connector, and the signal pins can be inserted into the circuit board with the corresponding signal pins.
  • the corresponding signal hole, the signal hole corresponding to the signal pin on the circuit board is connected to the internal circuit of the circuit board (that is, the circuit in the circuit board that processes the signal from the signal pin of the connector) through the signal lead-out line, that is, the signal pin
  • the signal can be introduced into the internal circuit of the circuit board by connecting with the internal circuit of the circuit board through the corresponding signal hole on the circuit board and the signal lead wire of the signal hole.
  • the signal hole 11 in the figure and the signal The holes 12 are the signal holes corresponding to the signal pins of the connector, the two signal holes 11 are a pair of differential signal holes (that is, the signals introduced by the signal pins corresponding to the two holes are a pair of differential signals), and the two signal holes 12 are
  • the signal lead-out line 01 is the signal lead-out line of the signal hole 11
  • the signal lead-out line 02 is the signal lead-out line of the signal hole 12
  • the signal lead-out line 01 and the signal lead-out line 02 have the same outgoing direction.
  • the signal lead lines corresponding to the paired differential signal holes must be laid out on the same wiring layer of the circuit board, so when two signal holes can be arranged at most three signal lead lines are arranged.
  • the pitch (spacing) between the two signal holes is 1.46mm (mm)
  • the paired signal leads must be laid out on the same wiring layer of the circuit board, so in each layer of the wiring layer, two lines Only two signal pinout lines can actually be arranged between the signal holes.
  • the two signal lead-out lines 01 corresponding to the two signal holes 11 obviously cannot be connected with the two signal holes.
  • the two signal lead lines 02 corresponding to 12 are laid out on the same layer of the circuit board, and can only be laid out on different wiring layers of the circuit board.
  • the increase in the number of layers of the wiring layer of the circuit board will not only increase the cost of the circuit board, but also increase the thickness of the circuit board, which will affect the soldering of the circuit board and reduce the soldering reliability of the circuit board.
  • the number of signal lead-out lines is reduced, and at the same time, more signal lead-out lines can be laid out on the same layer of circuit board to reduce the wiring layer of the circuit board. the number of layers.
  • most of the signal lead-out lines cannot be optimized or easily changed in direction, so that the effect of reducing the number of layers of the wiring layer of the circuit board by this method is not obvious.
  • an embodiment of the present disclosure provides a circuit board, which specifically includes a signal hole array matched with a terminal array of a connector, and at least part of the signal holes in the signal hole array are first signal holes 20 , and the first signal holes 20 It is a blind hole, which is connected to a part of the wiring layer of the circuit board, and is connected to the corresponding auxiliary conductive structure 30 through the auxiliary line 03 located in the auxiliary wiring layer.
  • the auxiliary conductive structure 30 at least connects the auxiliary wiring layer and the first signal hole 20.
  • the unconnected main wiring layer is connected to the signal lead line 04 located on the main wiring layer, and the signal lead line 04 extends out of the area where the signal hole array is located.
  • the terminal array of the connector refers to the array composed of multiple signal pins of the connector, and the array composed of the signal holes corresponding to the signal pins forming the terminal array on the circuit board is the signal hole array of the circuit board.
  • the signal hole corresponding to the pin refers to the signal hole which is located relative to the signal pin and can be inserted into the signal pin when the connector is connected to the circuit board.
  • the first signal hole 20 is specifically a blind hole, which is connected to part of the wiring layer of the circuit board, and passes through the auxiliary line located in one of the connected wiring layers (that is, the auxiliary wiring layer) 03 (for more clarity, only one auxiliary line 03 is marked in FIG. 3 , but the lines connecting the first signal hole 20 and the auxiliary conductive structure 30 in FIG. 3 are all auxiliary lines 03 ) to connect the auxiliary conductive structure 30 .
  • Different first signal holes 20 are connected to different auxiliary conductive structures 30, and different first signal holes 20 can be connected to different wiring layers of the circuit board, so the auxiliary wiring layers corresponding to different first signal holes 20 can also be different. Yes, that is to say, the first signal hole 20 , the auxiliary line 03 and the auxiliary conductive structure 30 are all corresponding.
  • the auxiliary conductive structure 30 corresponding to a first signal hole 20 is connected to at least the auxiliary wiring layer that is connected to the first signal hole 20 and the wiring layer that is not connected to the first signal hole 20 , and is connected to the first signal hole 20
  • the signal lead-out line 04 of the main wiring layer that is not connected (for the sake of clarity, only one signal lead-out line 04 is marked in FIG. 3, but the lines connecting the auxiliary conductive structure 30 and extending outward in FIG. 3 are all signal lead-out lines 04 ), through the signal lead-out line, the auxiliary conductive structure 30 is connected to the internal circuit for processing the signal in the circuit board located outside the area where the signal hole array is located.
  • the signal hole array of the circuit board in the embodiment of the present disclosure may also include a second signal hole, and the second signal hole may specifically be a through hole (such as the signal hole 11 and the signal hole 12 in FIG. 2). , which is directly connected to the internal circuit of the circuit board by connecting the signal pinout.
  • the signal lead-out line of the second signal hole and the signal lead-out line 04 corresponding to the first signal hole 20 may be jointly laid out on the main wiring layer.
  • the through holes, the first signal holes, and the auxiliary conductive structures of the circuit board according to the embodiment of the present disclosure can be combined with the design of large and small holes in the related art, the back drilling process, etc., as shown in part of FIG. 4 .
  • a signal hole 20 and all the auxiliary conductive structures 30 adopt the back-drilling process, and conduct electricity only in part of the layers.
  • the corresponding part of the layer between the layers is conductive to avoid shunting, circulation and other phenomena caused by too many conductive parts, that is, the stub effect (residual effect), and improve the integrity of the signal.
  • the process of introducing the signal of the signal pin of the connector into the internal circuit of the circuit board by the circuit board in the embodiment of the present disclosure may specifically be: when the signal pin of the connector corresponding to the first signal hole 20 is inserted into the first signal hole 20, The signal of the signal pin is introduced into the first signal hole 20, and then introduced into the auxiliary conductive structure 30 corresponding to the first signal hole 20 through the auxiliary line 03, and is introduced into the interior of the circuit board through the signal lead-out line 04 connected to the auxiliary conductive structure 30 circuit.
  • the first signal hole 20 is a blind hole, it is not connected to the wiring layer where the signal lead-out line 04 connected to the auxiliary conductive structure 30 is located, that is to say, the signal of the first signal hole 20 is introduced through the auxiliary conductive structure 30
  • the first signal hole 20 does not have a connected main wiring layer, so the signal lead-out line 04 connected to the auxiliary conductive structure 30 can be laid out at the position where the orthographic projection of the corresponding first signal hole 20 is located.
  • the layout space of the signal lead lines 04 is increased.
  • the trace layer where the signal lead lines 04 connected to the auxiliary conductive structure 30 of the circuit board in the embodiment of the present disclosure are located can be laid out with more signal lead lines 04, thereby reducing the circuit board traces.
  • the thickness of the circuit board will also be reduced, and the soldering reliability of large-size BGAs has been improved.
  • the connector corresponding to the circuit board in the embodiment of the present disclosure may be any device that needs to be connected to the circuit board through a signal hole, such as the output/connector of other devices.
  • the circuit board in the embodiment of the present disclosure may be a PCB (Printed Circuit Board, printed circuit board), and may specifically be a base station type communication circuit board.
  • PCB design of PCB is generally based on the schematic diagram, using drawing software to perform automatic layout under certain design rules, and then manually adjust to complete the final design. Restricted by PCB processing and PCB assembly capabilities, the final designed PCB must meet the requirements of producibility, reliability and low cost in addition to realizing functions.
  • PCB is developing towards high speed, high frequency, high density and multi-function.
  • PCB design also needs to develop towards high speed, high frequency, high density and multi-function.
  • BGA Bit Grid Array, ball grid array package
  • first-order laser holes, second-order/third-order laser holes, etc. are used to make BGA outlet lines. The space is fully utilized and the outlet density of the BGA is improved.
  • the BGA outlet space and device layout space are sufficient, but because the connectors cannot use the HDI (High Density Interconnector, high-density interconnect) process, often only by adding circuit boards.
  • the number of layers of the routing layer increases the layout space of the signal lead-out lines of the signal holes corresponding to the signal pins of the connector, which increases the cost.
  • the signals of the first signal holes 20 are introduced into the first signal holes by designing the first signal holes 20 as blind holes and designing corresponding auxiliary conductive structures 30 for the first signal holes 20 .
  • 20 does not have a connected wiring layer, which increases the layout space of signal lead-out lines and reduces the number of layers of circuit board wiring layers, which can significantly reduce the cost of base station communication circuit boards.
  • the connector corresponding to the circuit board in the embodiment of the present disclosure may be a high-speed connector. That is, the circuit board connected to the high-speed connector may specifically be the circuit board of the embodiment of the present disclosure.
  • the high-speed connector has a high density of pins (or signal pins), and it is more likely that the space for the signal lead-out lines of the layout signal holes cannot meet the requirements. It is necessary to "increase" the layout signal by increasing the number of layers of the wiring layer of the circuit board. The case of the space for the signal pinout of the hole. At the same time, the length of the pins (or signal pins) of the high-speed connector is generally shortened, so the depth of the signal holes of the corresponding circuit boards is also shortened, which further reduces the space available for the signal lead-out lines of the signal holes.
  • the circuit board connected to the high-speed connector is the circuit board of the embodiment of the disclosure, the number of layers of the wiring layers of the circuit board can be significantly reduced, and the cost of the circuit board can be reduced.
  • the orthographic projection of at least part of the signal lead-out line 04 overlaps with the orthographic projection of the first signal hole 20 .
  • the signal lead-out line 04 of the circuit board connected to the auxiliary conductive structure 30 in the embodiment of the present disclosure can pass through the position corresponding to the orthographic projection of the first signal hole 20 corresponding to the signal lead-out line 04 in the wiring layer. 20 is not connected to the wiring layer where the signal pinout 04 is located, so even if the signal pinout 04 is laid out at the position corresponding to the orthographic projection of the first signal hole 20 in the wiring layer, it will not be connected to the first signal hole 20. It will affect the normal operation of the circuit board.
  • the layout space of the signal lead lines 04 in the embodiment of the present disclosure is obviously larger.
  • first signal holes 20 there may be a plurality of first signal holes 20 in the signal hole array of the circuit board, and different first signal holes 20 may be connected to different wiring layers.
  • the position may be arranged with other first signal holes 20 or through holes connected to the layer, and the signal lead lines 04 connected to the auxiliary conductive structure 30 are arranged at positions other than the positions corresponding to the orthographic projection of the corresponding first signal holes 20 , obviously it is necessary to consider whether it will be connected to other first signal holes 20 or through holes, and to leave a safe distance with other first signal holes 20 or through holes, etc., and increase the signal lead-out line connected to the auxiliary conductive structure 30 04 layout difficulty.
  • the ultimate purpose of the signal lead-out line 04 connected to the auxiliary conductive structure 30 is to lead the signal introduced into the first signal hole 20 out of the area where the signal hole array is located, and to arrange the signal lead-out line 04 connected to the auxiliary conductive structure 30 in the first signal hole 20.
  • the positions corresponding to the orthographic projection of the signal holes 20 can avoid problems such as confusion in the layout of the signal lead lines 04 caused by crossing between the signal lead lines 04 corresponding to different first signal holes 20 , and make the layout of the signal lead lines 04 more reasonable.
  • the first signal holes 20 are arranged in a plurality of rows parallel to the first direction, each row includes a plurality of first signal holes 20; the first signal holes 20 are divided into multiple groups, each group Including two adjacent rows of first signal holes 20; a plurality of auxiliary conductive structures 30 corresponding to each row of first signal holes 20 are located in a direction perpendicular to the first direction, and are located far from the same group of first signal holes 20 in the row.
  • One side of a row of first signal holes 20 ; the signal lead line 04 includes a first portion extending into the group of the first signal hole 20 corresponding to the signal lead line 04 , and a second portion along the first direction.
  • the plurality of first signal holes 20 in the signal hole array are arranged in multiple rows parallel to a certain direction (ie, the first direction, as shown in FIG. 3 , the horizontal direction).
  • Each of the first signal holes 20 is a row), there is at least one first signal hole 20, and every two rows of the first signal holes 20 are a group (as shown in FIG. 3, the middle two rows in the longitudinal direction are a group).
  • the auxiliary conductive structures 30 corresponding to the first signal holes 20 of each group are located “outside” the first signal holes 20 of the group along the direction perpendicular to the first direction. Specifically, the auxiliary conductive structures corresponding to each first signal hole 20 The structure 30 is located on the "outer side” closer to itself, and the corresponding signal lead-out line 04 connected to the auxiliary conductive structure 30 includes two parts, respectively extending into the group of the group (ie the "inner side” opposite to the "outer side") and a second portion parallel to the first direction and leading the signal out of the area where the signal hole array is located.
  • a plurality of first signal holes 20 are arranged in multiple rows in the horizontal direction, and the first signal holes 20 in the middle two rows (the second row and the third row) are a group of first signal holes 20 ,
  • the auxiliary conductive structures 30 corresponding to each of the first signal holes 20 in the group are respectively located on the "outside" of the first signal holes 20 of the group closer to themselves along the direction perpendicular to the horizontal direction, and the first signal holes 20 in the second row correspond to
  • the auxiliary conductive structures 30 are located between the first signal holes 20 in the first row and the first signal holes 20 in the second row, and the auxiliary conductive structures 30 corresponding to the first signal holes 20 in the third row are located between the first signal holes 20 in the third row.
  • the signal lead lines 04 connected to the auxiliary conductive structure 30 include signals from the auxiliary conductive structure 30 to the inside of the group (that is, the first signal holes 20 in the second row and the first signal holes in the third row). A first portion extending between the holes 20 ) and a second portion extending outward in the horizontal direction (outside the area where the signal hole array is located).
  • At least part of the first signal vias 20 are differential signal vias.
  • Each group of the first signal holes 20 includes a plurality of pairs of the first signal holes 20 .
  • the first signal holes 20 in a column in the second row of the first signal holes 20 and the third row of the first signal holes 20 are a pair Differential signal hole.
  • Differential signals are commonly used signals in various fields, and are also signals that often need to be introduced into the internal circuit of the circuit board through the signal pins of the connector. Since the differential signals appear in pairs, the corresponding signal leads must also be laid out in pairs on the same routing layer, which leads to the existence of the routing layer space where three signal leads can be laid out, but only two signals can actually be laid out. Therefore, the layout of the signal lead-out lines for introducing differential signals into the internal circuit of the circuit board is often more complicated.
  • the circuit board includes a first sub-board and a second sub-board; the first signal hole 20 is connected to all the wiring layers of the first sub-board, and the auxiliary conductive structure 30 is at least connected to the auxiliary wiring layer and located in the second sub-board.
  • the main trace layer of the daughter board is not limited to.
  • the circuit board in the embodiment of the present disclosure can be realized by a secondary pressing process, that is, two sub-boards are pressed together to form a circuit board, and each sub-board is a sub-part of the circuit board.
  • a secondary pressing process can be used to press together two daughter boards with a thickness of 1.8 mm to form the circuit board.
  • the first signal hole 20 is connected to all the trace layers of the first sub-board, that is to say, from the perspective of the first sub-board, the first signal hole 20 is a through hole, so the first signal hole 20 can pass through a sub-board. This is achieved by making a through hole (that is, the first sub-board) and without any processing on the part of the other sub-board (that is, the second sub-board) that corresponds to the through hole.
  • the first signal hole 20 is obtained through such a process, which simplifies the fabrication process of the first signal hole 20 .
  • the first signal hole 20 can also be obtained by the deep blind hole processing technology.
  • all the signal holes of the signal hole array are the first signal holes 20 .
  • all the signal holes in the signal hole array are the first signal holes 20 , that is, all the signal holes in the signal hole array are blind holes, which are connected to part of the wiring layer of the circuit board, and are connected to The auxiliary line 03 of one of the wiring layers (that is, the auxiliary wiring layer) is connected to the auxiliary conductive structure 30 .
  • the signal lead lines 04 corresponding to the first signal holes 20 obviously require fewer wiring layers than the signal lead lines 04 corresponding to the through holes.
  • the wiring layers of the circuit board can be minimized, and the cost of the circuit board can be reduced.
  • the auxiliary conductive structures 30 are holes.
  • the auxiliary conductive structures are vias.
  • the auxiliary conductive structure may specifically be a hole such as a circular hole, an oval hole, or a long slotted hole.
  • a hole is a common shape in a circuit board, and its manufacturing process is relatively mature.
  • the auxiliary conductive structure 30 is a hole, which can realize the function of leading signals out of the area where the signal hole array is located, and is also convenient for fabrication.
  • the auxiliary conductive structure 30 is a through hole, which not only facilitates the connection between the first signal hole 20 and the auxiliary conductive structure 30, but also increases the optional routing layer for the signal lead-out line. Simpler.
  • the auxiliary conductive structure 30 is formed by dividing the metallized via into electrically independent multiple sections, each section being an auxiliary conductive structure 30 .
  • dividing the metallized via into electrically separate portions includes dividing the metallized via into electrically separate portions by removing portions of a hole wall of the metallized via.
  • the auxiliary conductive structures 30 can be obtained by dividing the metallized through holes. As shown in FIG. 3 , the auxiliary conductive structures 30 corresponding to the first signal holes 20 in the first row and the auxiliary conductive structures 30 corresponding to the first signal holes 20 in the second row It is obtained by dividing a metallized through hole into two electrically independent parts; similarly, the auxiliary conductive structure 30 corresponding to the first signal hole 20 in the third row and the auxiliary conductive structure corresponding to the first signal hole 20 in the fourth row Structure 30 is also obtained by dividing a metallized via into two electrically independent parts
  • the segmentation of metallized through holes can be performed by using related techniques, such as referring to FIG. 6(1) and FIG. 6(2), drilling one or more non-metallized slot holes 40 on the metallized through holes, or referring to FIG. 6(3) ), drill two non-metallized holes 40 on the metallized through hole; or refer to FIG. 6(4), use an etching method to directly remove a part of the hole wall of the metallized through hole.
  • the multiplexing of the holes is realized, the number of the auxiliary conductive structures 30 is also reduced, and the layout space of the signal lead-out lines is further increased.
  • the safety distance between the lines and the holes of the circuit board is C
  • the value of C is related to the number of layers and thickness of the circuit board, and is generally 0.228mm, that is, 9mil (micro-inch)
  • the safety distance between lines can be 0.102mm, or 4mil
  • the width of the line can be 0.102mm, or 4mil.
  • the first signal hole 20 is a differential signal hole
  • its diameter is 0.34mm
  • the corresponding hole diameter is 0.40mm.
  • Each pair of first signal holes 20 (such as the first signal holes 20 and The center-to-center spacing of the first signal holes 20) in the third row is 1.46 mm.
  • the auxiliary conductive structure 30 (the auxiliary conductive structure 30 in FIG.
  • the metallized through hole is obtained by dividing the metallized through hole.
  • the diameter of the metallized through hole is 0.55mm, and the corresponding drilling hole diameter is 0.6mm.
  • the metallized through hole is divided into As the two parts are electrically independent, the obtained non-metallized slot width of the auxiliary conductive structure 30 is 0.3 mm.
  • the part of the signal lead-out line that can be laid out is only a, and the length of a is 1.46mm-(0.4mm+0.4mm)/2, that is, 1.06mm, which can take three signal lead-out lines (three signals The length occupied by the pinout is 0.228mm*2+0.102mm*5, that is, 0.966mm, and the remaining 0.094mm is not enough to take a signal pinout). Since the signal lead-out lines of a pair of differential signals must be laid out on the same routing layer, only two signal lead-out lines can be routed on one routing layer.
  • the area where the signal lead lines can be laid out on the wiring layer of the second sub-board is b, and the length thereof is 1.46mm ⁇ 2-0.6mm/2-0.6mm/2, that is, 2.32mm , referring to the above calculation, it can take 10 signal lead lines, that is, 5 pairs of differential signal signal lead lines.

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Abstract

提供了一种电路板，电路板包括与连接器的端子阵列匹配的信号孔阵列，信号孔阵列中至少有部分信号孔为第一信号孔（20）；第一信号孔（20）为盲孔，其连通至电路板的部分走线层,并通过位于辅助走线层的辅助线（03）连接辅助导电结构（30）；辅助导电结构（30）至少连通辅助走线层和第一信号孔（20）未连通的走线层,并与位于主走线层的信号引出线（04）连接；信号引出线（04）延伸出信号孔阵列所在区域。

Description

电路板
相关申请的交叉引用
本申请要求于2020年11月3日提交的中国专利申请NO.202011208923.8的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本公开实施例涉及电路技术领域，特别涉及电路板。
背景技术
连接器是电路系统电气连接必需的核心基础元件之一，在工业、汽车、通讯等产品中广泛应用。随着技术，尤其是5G技术的发展，连接器也在向着高速、高频、高密度的方向发展。随着连接器的发展，有越来越多的信号需要引入连接器的内部电路。
由于连接器无法使用HDI(High Density Interconnector，高密度互连)工艺，因此与连接器连接的电路板只能通过增加走线层的层数，保证连接器的信号可以被引入电路板的内部电路，但电路板层数越多，电路板的成本就越高。
公开内容
本公开实施例提供一种电路板，其包括与连接器的端子阵列匹配的信号孔阵列，所述信号孔阵列中至少有部分信号孔为第一信号孔；
所述第一信号孔为盲孔，其连通至所述电路板的部分走线层,并通过位于辅助走线层的辅助线连接辅助导电结构；
所述辅助导电结构至少连通辅助走线层和所述第一信号孔未连通的走线层,并与位于所述主走线层的信号引出线连接；
所述信号引出线延伸出所述信号孔阵列所在区域。
附图说明
在本公开实施例的附图中：
图1为相关技术中一种信号引出线的布局示意图；
图2为相关技术中一种电路板的结构示意图；
图3为本公开实施例提供的一种电路板的结构示意图；
图4为本公开实施例提供的一种电路板的剖面结构示意图；
图5为本公开实施例提供的一种电路板的孔线距离关系示意图；以及
图6为本公开实施例提供的一种电路板的辅助导电结构的制作示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开实施例的技术方案，下面结合附图对本公开实施例提供的电路板进行详细描述。
在下文中将参考附图更充分地描述本公开实施例，但是所示的实施例可以以不同形式来体现，且不应当被解释为限于本公开阐述的实施例。提供这些实施例的目的在于使本公开更加透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施例的附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其他特征和优点对本领域技术人员将变得更加清楚。
本公开实施例可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。
在不冲突的情况下，本公开各实施例及实施例中的各特征可相互组合。
本公开所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本公开所使用的术语“和/或”包括一个或多个相关列举条目的任何和所有组合。如本公开所使用的单数形式“一个”和“该” 也意欲包括复数形式，除非上下文另外清楚指出。如本公开所使用的术语“包括”、“由……制成”指定存在特定特征、整体、步骤、操作、元件和/或组件，但不排除存在或可添加一个或多个其他特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本公开所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如在那些常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本公开明确如此限定。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是旨在限制性的。
在一些相关技术中，连接器的引脚(也称为pin脚)可称为信号脚(端子)，电路板上存在与连接器的信号脚对应的信号孔，信号脚可插入电路板上与其对应的信号孔，电路板上与信号脚对应的信号孔通过信号引出线与电路板的内部电路(即电路板内处理来自连接器的信号脚的信号的电路)连接，也就是说，信号脚可以通过电路板上与其对应的信号孔、以及该信号孔的信号引出线与电路板的内部电路连接，将信号引入电路板的内部电路。
随着连接器的发展，越来越多的信号需要通过信号脚引入电路板的内部电路，连接器的信号脚也就越来越多，因此电路板上与信号脚对应的信号孔也越来越多，信号孔与信号孔之间的空间也越来越小，即可用于布局信号引出线的空间越来越小。因此，可以增加电路板的走线层的层数，使得不同信号孔的信号引出线可以布局在电路板的不同走线层，“增加”信号引出线的布局空间，进一步保证所有信号可以被引入电路板的内部电路。
如参照图1(图中仅示出了信号孔和信号引出线的空间位置)和图2(图中仅示出了信号孔和信号引出线的投影关系),图中的信号 孔11和信号孔12都是连接器的信号脚对应的信号孔，两个信号孔11为一对差分信号孔(即两个孔对应的信号脚引入的信号为一对差分信号)，两个信号孔12为另一对差分信号孔，信号引出线01为信号孔11的信号引出线，信号引出线02为信号孔12的信号引出线，信号引出线01与信号引出线02的出线方向相同。
进一步的，当信号孔为差分信号孔时，成对的差分信号孔对应的信号引出线必须布局在电路板的同一走线层，故当两个信号孔之间最多可布局三条信号引出线时，如两个信号孔之间的pitch(间距)为1.46mm(毫米)时，由于成对的信号引出线必须布局在电路板的同一走线层，因此在每一层走线层，两行信号孔之间实际只能布局两条信号引出线。
可见，当同一走线层中，两行差分信号孔之间的airgap(空隙)不足以布局四条信号引出线时，两个信号孔11对应的两条信号引出线01显然不能和两个信号孔12对应的两条信号引出线02布局在电路板的同一层，只能布局在电路板的不同走线层。
而电路板的走线层的层数的增多，不仅会增加电路板的成本，同时也使电路板厚度增加，进而会对电路板的焊接造成影响，使得电路板的焊接可靠性降低。
在另一些相关技术中，通过优化信号扇出方式以及信号引出线的方向，减少信号引出线的数量，同时使同一层电路板可以布局更多的信号引出线，来减少电路板的走线层的层数。但由于信号完整性的制约，大部分的信号引出线并不能被优化掉或轻易更改方向，导致该方法的减少电路板的走线层的层数的效果并不明显。
参照图3，本公开实施例提供一种电路板，其具体包括与连接器的端子阵列匹配的信号孔阵列，信号孔阵列中至少有部分信号孔为第一信号孔20，第一信号孔20为盲孔，其连通至电路板的部分走线层,并通过位于辅助走线层的辅助线03连接对应的辅助导电结构30，辅助导电结构30至少连通辅助走线层和第一信号孔20未连通的主走线层,并与位于主走线层的信号引出线04连接，信号引出线04延伸出 信号孔阵列所在区域。
连接器的端子阵列是指连接器的多个信号脚所组成的阵列，电路板上与组成端子阵列的信号脚对应的信号孔组成的阵列就是电路板的信号孔阵列，端子阵列中每个信号脚对应的信号孔是指与该信号脚处于相对位置，在连接器与电路板连接时该信号脚可以插入的信号孔。
参照图3(图中仅示出了第一信号孔20、辅助导电结构30、辅助线03、信号引出线04的投影关系)，在组成信号孔阵列的所有信号孔中至少有部分信号孔为第一信号孔20，第一信号孔20具体为盲孔，其连通电路板的部分走线层，并通过位于其连通的走线层中其中一层(也就是辅助走线层)的辅助线03(为了更加清楚，图3中只标出一条辅助线03，但图3中连接第一信号孔20与辅助导电结构30的线都是辅助线03)连接辅助导电结构30。
不同的第一信号孔20连接不同的辅助导电结构30，不同的第一信号孔20可连通电路板的不同走线层，因此不同的第一信号孔20对应的辅助走线层也可以是不同的，也就是说，第一信号孔20、辅助线03以及辅助导电结构30都是对应的。
与一个第一信号孔20对应的辅助导电结构30至少连通该第一信号孔20连通的辅助走线层、以及该第一信号孔20未连通的走线层，并连接位于第一信号孔20未连通的主走线层的信号引出线04(为了更加清楚，图3中只标出一条信号引出线04，但图3中连接辅助导电结构30并向外延伸的线都是信号引出线04)，通过该信号引出线，辅助导电结构30与位于信号孔阵列所在区域外的电路板内处理信号的内部电路连接。
本公开实施例的电路板的信号孔阵列除了第一信号孔20之外，也可以包括第二信号孔，第二信号孔具体可以是通孔(如图2中信号孔11和信号孔12)，其直接通过连接信号引出线连接电路板的内部电路。具体的，第二信号孔的信号引出线可以和第一信号孔20对应的信号引出线04共同布局在主走线层。
具体的，参照图4，本公开实施例的电路板的通孔、第一信号孔、 以及辅助导电结构可以和相关技术中的大小孔设计、背钻工艺等结合，如图4中的部分第一信号孔20和所有辅助导电结构30就采用了背钻工艺，只在部分层导电，如辅助导电结构30可以只在辅助走线层和信号引出线04所在的走线层(即主走线层)之间层对应的部分导电，以避免由于导电部分过多而引起的分流、环流等现象，即stub效应(残留效应)，提升信号的完整性。
本公开实施例的电路板将连接器的信号脚的信号引入电路板的内部电路的过程具体可以是：当与第一信号孔20对应的连接器的信号脚插入该第一信号孔20时，信号脚的信号被引入第一信号孔20，然后通过辅助线03被引入与第一信号孔20对应的辅助导电结构30，并通过连接辅助导电结构30的信号引出线04被引入电路板的内部电路。
由于第一信号孔20为盲孔，其并没有连通与辅助导电结构30连接的信号引出线04所在的走线层，也就是说，通过辅助导电结构30将第一信号孔20的信号引入了第一信号孔20并没有连通的主走线层，因此与辅助导电结构30连接的信号引出线04可以布局在其对应的第一信号孔20的正投影所在的位置，这样在布局的时候不用考虑保持与第一信号孔的安全距离，而只用考虑与其他信号引出线04之间的安全距离，增大了信号引出线04的布局空间。在走线层大小相同的情况下，本公开实施例的电路板的与辅助导电结构30连接的信号引出线04所在的走线层可以布局更多的信号引出线04，进而减少了电路板走线层的层数，同时由于走线层数降低，电路板厚度也会降低，大尺寸BGA的焊接可靠性得到了提升。
本公开实施例的电路板对应的连接器可以是任何需要通过信号孔与电路板连接的器件，例如其它设备的输出/接头等。具体的，本公开实施例的电路板可以是PCB(Printed Circuit Board，印制电路板)，具体可以是基站类通信电路板。
PCB的设计一般是根据原理图，使用画图软件在一定的设计规则下进行自动布局，然后再进行人工调整，完成最终设计。受PCB加工、PCB组装能力的制约，最终设计的PCB，除了要实现功能外，也要满 足可生产性、可靠性、低成本的需求。
随着技术发展，PCB向着高速、高频、高密度、多功能发展，PCB的设计作为PCB工艺的重要组成部分，也需要向着高速、高频、高密度、多功能发展。
在一般的PCB设计中，BGA(Ball Grid Array,球栅阵列封装)的出线设计是优化重点，在一些相关技术中,会采用一阶激光孔、二阶/三阶激光孔等使BGA的出线空间得到充分利用,提升BGA的出线密度。
但是，一些电路板,尤其是基站类通信电路板，BGA的出线空间以及器件布局空间足够,反而由于连接器无法使用HDI(High Density Interconnector,高密度互连)工艺，往往只能通过增加电路板的走线层的层数,来增加与连接器的信号脚对应的信号孔的信号引出线的布局空间，增加了成本。
而本公开实施例的电路板则通过将第一信号孔20设计为盲孔，以及为第一信号孔20设计对应的辅助导电结构30，将第一信号孔20的信号引入了第一信号孔20并没有连通的走线层，增大了信号引出线的布局空间进而减少了电路板走线层的层数，可以明显降低基站类通信电路板的成本。
具体的，本公开实施例的电路板对应的连接器可以是高速连接器。也就是说，与高速连接器连接的电路板具体可以是本公开实施例的电路板。
高速连接器的引脚(或者说信号脚)密度大，更容易出现布局信号孔的信号引出线的空间无法满足要求，需要通过增加电路板的走线层的层数来“增大”布局信号孔的信号引出线的空间的情况。同时，高速连接器的引脚(或者说信号脚)的长度普遍变短，因此与其对应的电路板的信号孔的深度也变短，使得可用于布局信号孔的信号引出线的空间进一步减少。当与高速连接器连接的电路板为本公开实施例的电路板时，可以明显降低电路板的走线层的层数，降低电路板的成本。
参照图3，在一些实施方式中，在平行于电路板的平面中，至少部分信号引出线04的正投影与第一信号孔20的正投影有重叠。
本公开实施例的电路板的与辅助导电结构30连接的信号引出线04，可以经过走线层中该信号引出线04对应的第一信号孔20的正投影对应的位置，由于第一信号孔20并没有连通信号引出线04所在的走线层，因此信号引出线04即使布局在走线层中第一信号孔20的正投影对应的位置，也并不会和第一信号孔20导通而对电路板的正常工作造成影响。
相比于在第一信号孔20连通的走线层布局信号引出线04(不能在第一信号孔20对应的位置布局信号引出线04，同时必须在信号引出线04和第一信号孔20之间留出安全距离)，本公开实施例的信号引出线04的可布局空间显然更大。
电路板的信号孔阵列中可能有多个第一信号孔20，不同的第一信号孔20可能连通不同的走线层，与辅助导电结构30连接的信号引出线04所在的走线层的其他位置可能布局了连通至该层的其他第一信号孔20或通孔，在除对应的第一信号孔20的正投影对应的位置之外的位置布局与辅助导电结构30连接的信号引出线04，显然要考虑是否会与其他第一信号孔20或通孔连通，以及与其他的第一信号孔20或通孔留出安全距离等问题，增大了与辅助导电结构30连接的信号引出线04的布局难度。
同时，与辅助导电结构30连接的信号引出线04的最终目的是将被引入第一信号孔20的信号引出信号孔阵列所在区域，将与辅助导电结构30连接的信号引出线04布局在第一信号孔20的正投影对应的位置，可以避免不同的第一信号孔20对应的信号引出线04之间交叉造成信号引出线04布局混乱等问题，使信号引出线04的布局更加合理。
参照图3，在一些实施方式中，第一信号孔20排成多个平行于第一方向的行，每行包括多个第一信号孔20；第一信号孔20分为多组，每组包括相邻的两行第一信号孔20；与每行第一信号孔20对应 的多个辅助导电结构30沿与第一方向垂直的方向，位于该行第一信号孔20的远离同组另一行第一信号孔20的一侧；信号引出线04包括向与该信号引出线04对应的第一信号孔20所在组的组内延伸的第一部分、以及沿第一方向的第二部分。
参照图3，信号孔阵列中的多个第一信号孔20排成了平行于一定方向(即第一方向，如图3中为横向)的多行，每行(如图3中横向的多个第一信号孔20为一行)中都有至少有一个第一信号孔20，每两行第一信号孔20为一组(如图3中沿纵向的中间两行为一组)。
每一组的第一信号孔20对应的辅助导电结构30沿垂直于第一方向的方向位于该组第一信号孔20的“外侧”，具体的，每一个第一信号孔20对应的辅助导电结构30位于更靠近自己的“外侧”，对应的与辅助导电结构30连接的信号引出线04包括两个部分，分别为向所在组的组内(即与“外侧”相对的“内侧”)延伸的第一部分、和与第一方向平行且将信号引出信号孔阵列所在区域的第二部分。
具体的，参照图3，多个第一信号孔20排成了水平方向的多行，中间两行(第二行和第三行)的第一信号孔20为一组第一信号孔20，该组中每个第一信号孔20对应的辅助导电结构30沿垂直于水平方向的方向分别位于该组第一信号孔20的更接近自己的“外侧”，第二行第一信号孔20对应的辅助导电结构30位于第一行第一信号孔20和第二行第一信号孔20之间，第三行第一信号孔20对应的辅助导电结构30位于第三行第一信号孔20和第四行第一信号孔20之间，与辅助导电结构30连接的信号引出线04包括了从辅助导电结构30向组内(也就是第二行第一信号孔20和第三行第一信号孔20之间)延伸的第一部分以及沿水平方向向外(信号孔阵列所在区域外)延伸的第二部分。
在一些实施方式中，至少部分第一信号孔20为差分信号孔。
每组第一信号孔20包括多对第一信号孔20，如参照图3，第二行第一信号孔20和第三行第一信号孔20中在一列的第一信号孔20为一对差分信号孔。
差分信号为多种领域的常用信号，也是常需要通过连接器的信号脚引入电路板的内部电路的信号。由于差分信号是成对出现，对应的信号引出线也必须成对布局在同一个走线层，这就导致了存在走线层空间可以布局三条信号引出线，但实际却只能布局两条信号引出线的情况，所以将差分信号引入电路板的内部电路的信号引出线的布局往往更加复杂。
在一些实施方式中，电路板包括第一子板和第二子板；第一信号孔20连通至第一子板的所有走线层，辅助导电结构30至少连通辅助走线层以及位于第二子板的主走线层。
本公开实施例的电路板可以采用二次压合工艺实现，即将两个子板压合在一起组成一个电路板，每一个子板就是电路板的一个子部分，如假设电路板的厚度为3.6mm，则可以采用二次压合工艺，将两个厚度为1.8mm的子板压合在一起形成该电路板。
第一信号孔20连接第一子板的所有走线层，也就是说，从第一子板来看，第一信号孔20是一个通孔，因此第一信号孔20可以通过在一个子板(也就是第一子板)制作一个通孔、在另一个子板(也就是第二子板)与该通孔对应的部分不作任何处理来实现。
由于通孔的实现工艺比盲孔的实现工艺要更加简单，通过这样的处理得到第一信号孔20，使得第一信号孔20的制作工艺得到了简化。当不采用二次压合工艺时，第一信号孔20也可以通过深盲孔加工技术获得。
在一些实施方式中，信号孔阵列的所有信号孔都为第一信号孔20。
参照图3，信号孔阵列的所有信号孔都是第一信号孔20，也就是说，信号孔阵列中的所有信号孔都是盲孔，连通电路板的部分走线层，并通过位于其连通的走线层中其中一层(也就是辅助走线层)的辅助线03连接辅助导电结构30。
本公开实施例的电路板中，在信号引出线04的数量相同的情况 下，第一信号孔20对应的信号引出线04显然比通孔对应的信号引出线04需要的走线层更少，当信号孔阵列的所有信号孔都为第一信号孔20时，可以最大程度地减少电路板的走线层，降低电路板的成本。
在一些实施方式中，辅助导电结构30为孔。
在一些实施方式中，辅助导电结构为通孔。
辅助导电结构具体可以是如圆孔、椭圆孔、长槽孔的孔。
孔是电路板中的常用形状，其制作工艺比较成熟，辅助导电结构30为孔既可以实现将信号引出信号孔阵列所在区域的功能，也便于制作。
辅助导电结构30为通孔既方便了第一信号孔20与辅助导电结构30的连接，又增加了信号引出线可选择的走线层，同时，相比于盲孔，通孔的制作工艺也更加简单。
在一些实施方式中，辅助导电结构30通过以下方式形成：将金属化通孔分割为电气独立的多个部分，每个部分为一个辅助导电结构30。
在一些实施方式中，将金属化通孔分割为电气独立的多个部分包括：通过将金属化通孔的孔壁的部分去除，将金属化通孔分割为电气独立的多个部分。
辅助导电结构30可以通过将金属化通孔分割得到，如图3中，第一行的第一信号孔20对应的辅助导电结构30和第二行的第一信号孔20对应的辅助导电结构30就是通过将一个金属化通孔分割为电气独立的两部分得到的；同样的，第三行的第一信号孔20对应的辅助导电结构30和第四行的第一信号孔20对应的辅助导电结构30也是通过将一个金属化通孔分割为电气独立的两部分得到的
金属化通孔的分割可以采用相关技术，如参照图6(1)和图6(2)，在金属化通孔上钻一个或多个非金属化的槽孔40，或者参照图6(3)，在金属化通孔上钻两个非金属化的孔40；或者参照图6(4)，采用采用蚀刻方式，直接将金属化通孔的孔壁去除一部分。
通过将一个金属化通孔分割为电气独立的多个部分，实现孔的复用，也减少了辅助导电结构30的数量，进一步增大了信号引出线布局的空间。
具体的，参照图3和图5，电路板的线与孔之间的安全距离为C，C的取值和电路板的层数、厚度等相关，一般为0.228mm，即9mil(微英寸)，线与线之间的安全距离可以为0.102mm，即4mil，线的宽度可以为0.102mm，即4mil。假设第一信号孔20为差分信号孔，其孔径为0.34mm，其对应的钻孔的孔径为0.40mm，每对第一信号孔20(如图3中第二行的第一信号孔20和第三行的第一信号孔20)的中心间距为1.46mm。辅助导电结构30(如图3中辅助导电结构30)为通过金属化通孔分割得到的，金属化通孔的孔径为0.55mm，对应的钻孔孔径为0.6mm，将该金属化通孔分割为电气独立的两部分，得到的辅助导电结构30的非金属化槽孔宽度为0.3mm。
参照图3，在常规设计下，信号引出线可布局的部分只有a，a的长度为1.46mm-(0.4mm+0.4mm)/2，即1.06mm，其可以走三条信号引出线(三条信号引出线需要占用的长度为0.228mm*2+0.102mm*5，即0.966mm，而剩余的0.094mm，并不足以走一条信号引出线)。由于一对差分信号的信号引出线必须布局在同一个走线层，因此一个走线层只能走两条信号引出线。
而本公开实施例的电路板中，其第二子板的走线层可布局信号引出线的区域为b，其长度为1.46mm×2-0.6mm/2-0.6mm/2，即2.32mm，参考上述的计算，其可以走10条信号引出线，即5对差分信号的信号引出线。
本公开已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则与特定实施例相结合描述的特征、特性和/或元素可单独使用，或可与结合其他实施例描述的特征、特性和/或元件组合使用。 因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (10)

  1. 一种电路板，其包括与连接器的端子阵列匹配的信号孔阵列，所述信号孔阵列中至少有部分信号孔为第一信号孔，其中，
    所述第一信号孔为盲孔，其连通至所述电路板的部分走线层,并通过位于辅助走线层的辅助线连接对应的辅助导电结构；
    所述辅助导电结构至少连通辅助走线层和所述第一信号孔未连通的主走线层,并与位于所述主走线层的信号引出线连接；以及
    所述信号引出线延伸出所述信号孔阵列所在区域。
  2. 根据权利要求1所述的电路板，其中，在平行于所述电路板的平面中，至少部分所述信号引出线的正投影与所述第一信号孔的正投影有重叠。
  3. 根据权利要求1所述的电路板，其中，所述第一信号孔排成平行于第一方向的多行，每行包括多个第一信号孔；所述第一信号孔分为多组，每组包括相邻的两行第一信号孔；
    与每行第一信号孔对应的多个辅助导电结构，沿与第一方向垂直的方向，位于该行第一信号孔的远离同组另一行第一信号孔的一侧；
    所述信号引出线包括向与该信号引出线对应的第一信号孔所在组的组内延伸的第一部分、以及沿第一方向的第二部分。
  4. 根据权利要求1所述的电路板，其中，所述辅助导电结构为孔。
  5. 根据权利要求4所述的电路板，其中，所述辅助导电结构为通孔。
  6. 根据权利要求1所述的电路板，其中，所述辅助导电结构通过以下方式形成：将金属化通孔分割为电气独立的多个部分，每个部 分为一个辅助导电结构。
  7. 根据权利要求1所述的电路板，其中，至少部分所述第一信号孔为差分信号孔。
  8. 根据权利要求1所述的电路板，其中，所述电路板包括第一子板和第二子板；
    所述第一信号孔连通至所述第一子板的所有走线层，所述辅助导电结构至少连通辅助走线层以及位于所述第二子板的主走线层。
  9. 根据权利要求1所述的电路板，其中，所述信号孔阵列的所有信号孔都为第一信号孔。
  10. 根据权利要求1所述的电路板，其中，所述信号孔阵列有部分信号孔为第二信号孔，所述第二信号孔为通孔。
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