WO2022110055A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2022110055A1
WO2022110055A1 PCT/CN2020/132413 CN2020132413W WO2022110055A1 WO 2022110055 A1 WO2022110055 A1 WO 2022110055A1 CN 2020132413 W CN2020132413 W CN 2020132413W WO 2022110055 A1 WO2022110055 A1 WO 2022110055A1
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WIPO (PCT)
Prior art keywords
anode
area
anodes
display
display area
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2020/132413
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English (en)
French (fr)
Inventor
杜丽丽
龙跃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2020/132413 priority Critical patent/WO2022110055A1/zh
Priority to US18/250,598 priority patent/US20230403897A1/en
Priority to KR1020237014728A priority patent/KR20230109622A/ko
Priority to CN202080003036.9A priority patent/CN114830349B/zh
Priority to EP20962945.0A priority patent/EP4220726A4/en
Priority to JP2023524804A priority patent/JP7664384B2/ja
Publication of WO2022110055A1 publication Critical patent/WO2022110055A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80517—Multilayers, e.g. transparent multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • an embodiment of the present disclosure provides a display substrate, including:
  • a base substrate having a display area and a frame area surrounding the display area
  • the display area includes: a first display area and a second display area located at least on one side of the first display area; wherein the first display area The transmittance of the display area is greater than the transmittance of the second display area;
  • the driving circuit layer is located on the base substrate; the driving circuit layer includes a plurality of first pixel circuits and a plurality of second pixel circuits, and the orthographic projection of the first pixel circuits on the base substrate is the same as the The orthographic projections of the first display area on the base substrate do not overlap, and the second pixel circuit is located in the second display area;
  • a light-emitting device layer located on the side of the driving circuit layer away from the base substrate, the light-emitting device layer includes a plurality of first light-emitting devices and a plurality of second light-emitting devices, the first light-emitting devices are located on the first light-emitting device a display area, the second light-emitting devices are located in the second display area, each of the first light-emitting devices includes an independently arranged first anode, and each of the second light-emitting devices includes an independently arranged second anode; Each of the plurality of first anodes is respectively electrically connected to each of the plurality of first pixel circuits, and each of the plurality of second anodes is respectively connected to the plurality of second pixel circuits Each of the corresponding electrical connections; wherein the density of the plurality of first light-emitting devices in the first display area is the same as the density of the plurality of second light-emitting devices in the second display area;
  • At least one transparent conductive layer is located between the driving circuit layer and the light-emitting device layer; each layer of the at least one transparent conductive layer includes a plurality of first anodes electrically connected to the first anodes wiring; the first anode wiring at least includes a first part extending in a column direction and a second part extending in a row direction, and the second parts of a plurality of first anode wirings electrically connected to the first anodes in the same row It is located between the first anodes in different adjacent rows, and the second part is led out to the outside of the first display area along the row direction.
  • the at least one transparent conductive layer includes a first transparent conductive layer and a second transparent conductive layer that are stacked and insulated from each other;
  • one row of the first anode traces corresponding to the first anodes is located in the first transparent conductive layer, and the other row of the first anode traces corresponding to the first anodes is located in the first transparent conductive layer on the second transparent conductive layer.
  • the patterns of the first transparent conductive layer and the second transparent conductive layer are the same.
  • the number of first anode wirings between two adjacent rows of first anodes corresponding to each transparent conductive layer is not greater than the first number, and each The number of first anode wirings between two adjacent columns of first anodes corresponding to the transparent conductive layer is not greater than a second number, and the first number is greater than the second number.
  • At least one row of the first anodes is divided into adjacent first regions, second regions and third regions, and the first anodes corresponding to the first regions
  • the traces are located between the first anodes in the same two adjacent rows
  • the first anode traces corresponding to the second area are located between the first anodes in the same two adjacent rows
  • the first anode traces corresponding to the third area The first anode wires corresponding to the first area, the second area and the third area are located between the first anodes in the same two adjacent rows
  • the first anode wirings corresponding to the first area, the second area and the third area are located between the first anodes in different adjacent rows.
  • the first area is close to the second display area, and the second area is located on a side of the first area away from the second display area, the third area is located on the side of the second area away from the second display area;
  • the number of first anode wirings corresponding to the first region is not greater than half of the first number, and the numbers of first anode wirings corresponding to the second region and the third region are both the first quantity.
  • At least one row of the first anodes is divided into adjacent fourth, fifth and sixth regions, and the fourth region corresponds to the first anode
  • the wiring is located between the same two adjacent rows of first anodes
  • the first anode wiring corresponding to the fifth region is located between the same two adjacent rows of first anodes
  • the first anode wiring corresponding to the sixth region are located between two different adjacent rows of first anodes
  • the first anode traces corresponding to the fourth region, the fifth region and the sixth region are located between two different adjacent rows of first anodes .
  • the fourth area is close to the second display area, and the fifth area is located on a side of the fourth area away from the second display area, the sixth area is located on the side of the fifth area away from the second display area;
  • the number of the first anode wirings corresponding to the fourth region is the first number
  • the number of the first anode wirings corresponding to the fifth region is the first number
  • the number of the first anode wirings corresponding to the sixth region is the first number.
  • the number of an anode wiring is not more than half of the first number.
  • the first number is 11-15, and the second number is 2-6.
  • the plurality of first anode wirings included in each of the transparent conductive layers do not overlap with each other, and the plurality of first anode wires included in the different transparent conductive layers are different.
  • Orthographic projections of an anode trace on the base substrate are interlaced with each other.
  • an insulating layer is provided between the first anode and the transparent conductive layer, and the insulating layer has an insulating layer for electrically connecting the first anode and the transparent conductive layer.
  • a plurality of via holes of the first anode wiring, the orthographic projection of the first anode wiring on the base substrate and the orthographic projection of the via holes on the base substrate do not overlap.
  • the plurality of first pixel circuits are located in the frame area adjacent to the first display area.
  • the second display area has a seventh area and an eighth area adjacent to the first display area, the seventh area and the eighth area Relatively arranged, the area occupied by the second pixel circuits in the seventh area and the eighth area is smaller than the area occupied by the second pixel circuits in the other second display areas, and the plurality of first pixel circuits located in the seventh area and the eighth area.
  • the shape of the first display area is a circle, an ellipse, a rectangle or a polygon.
  • the first display area is divided into four equal parts along the center line of the row direction and the column direction, and the first anode of each equal part is divided into four equal parts.
  • the wiring adopts the arrangement of the first anode wiring in the display substrate according to any one of claims 1-13.
  • the four equal parts include a first equal part, a second equal part, a third equal part and a fourth equal part arranged in a clockwise direction, the The first equal portion and the second equal portion are arranged symmetrically with respect to the center line in the column direction, the second equal portion and the third equal portion are symmetrically arranged with respect to the center line in the row direction, and the third The equal parts and the fourth equal parts are arranged symmetrically with respect to the center line in the column direction, and the fourth equal parts and the first equal parts are symmetrically arranged with respect to the center line in the row direction.
  • the first anode in the first equal portion closest to the fourth equal portion is the first anode in the first row
  • the fourth equal portion is closest to the first anode.
  • the first equal portion is the first anode in the second row
  • the first gap between the first anode in the first row and the first anode in the second row is the first gap
  • the first anode in the first row is close to the first anode in the first row.
  • the first anode traces corresponding to the first area of the second display area and the first anode traces corresponding to the first area of the second row of first anodes near the second display area are located in the first within the gap.
  • an embodiment of the present disclosure further provides a display panel including the above-mentioned display substrate.
  • an embodiment of the present disclosure further provides a display device, including: a photosensitive device, and the above-mentioned display panel; the photosensitive device is disposed in a first display area of the display substrate.
  • FIG. 1 is a schematic top view of a display substrate in the related art
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • Fig. 3 is the enlarged schematic diagram of the first display area in Fig. 2;
  • FIG. 4 is an enlarged schematic diagram of the wiring of the first display area in FIG. 2;
  • Fig. 5 is the enlarged schematic diagram of the upper left part in Fig. 4;
  • FIG. 6 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic top-view structure diagram of a transparent conductive layer provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional structure diagram of a transparent conductive layer provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the wiring arrangement of the first display area in FIG. 2 .
  • the under-screen camera technology generally sets a first display area AA1 and a second display area AA2 in the display area AA, wherein the second display area AA2 occupies most of the display screen, and the first display area AA2 AA1 occupies the remaining part, and the first display area AA1 is where the camera under the screen is placed.
  • the off-screen camera means that the front camera is located below the screen but does not affect the screen display function. When the front camera is not used, the screen above the camera can still display images normally. So from the appearance point of view, the under-screen camera will not have any camera hole, which truly achieves the full-screen display effect.
  • the display brightness of the first display area AA1 is at least twice as low as the display brightness of the second display area AA2, which is an urgent problem to be solved.
  • FIG. 2 is a schematic diagram of the overall structure of the display substrate
  • FIG. 3 is the first display area in FIG. 2
  • FIG. 4 is a schematic diagram showing the detailed structure of the quarter area where the dotted frame in FIG. 3 is located
  • FIG. 5 is an enlarged schematic diagram of the structure of the quarter area where the dotted line frame is located in FIG. 4
  • the display substrate includes:
  • the base substrate 10 has a display area AA and a frame area BB surrounding the display area.
  • the display area AA includes: a first display area AA1 and a second display area AA2 located at least on one side of the first display area AA1;
  • the transmittance of the area AA1 is greater than the transmittance of the second display area AA2;
  • the driving circuit layer is located on the base substrate 10; the driving circuit layer includes a plurality of first pixel circuits D1 and a plurality of second pixel circuits D2, and the orthographic projection of the first pixel circuits D1 on the base substrate 10 is the same as that of the first display
  • the orthographic projections of the area AA1 on the base substrate 10 do not overlap, and the second pixel circuit D2 is located in the second display area AA2; only part of the first pixel circuit D1 and the second pixel circuit D2 are shown in FIG. 1 ;
  • the light-emitting device layer is located on the side of the driving circuit layer away from the base substrate 10, the light-emitting device layer includes a plurality of first light-emitting devices and a plurality of second light-emitting devices, the first light-emitting devices are located in the first display area AA1, and the second light-emitting devices Located in the second display area AA2, each of the first light-emitting devices includes an independently arranged first anode 11, and each of the second light-emitting devices includes an independently arranged second anode 12; each of the plurality of first anodes 11 is connected to a plurality of Each of the plurality of first pixel circuits D1 is electrically connected to each other, and each of the plurality of second anodes 12 is respectively electrically connected to each of the plurality of second pixel circuits D2; wherein the plurality of first light-emitting devices are The density (ie pixel resolution) of the first display area AA1 is the same as the density of the plurality of second light
  • At least one transparent conductive layer is located between the driving circuit layer and the light emitting device layer; each layer of the at least one transparent conductive layer includes a plurality of first anode wirings 101 electrically connected to the first anode 11; the first anode
  • the traces 101 at least include a first portion 01 extending in the column direction Y and a second portion 02 extending in the row direction X, and the second portions 02 of the plurality of first anode traces 101 electrically connected to the first anodes 11 in the same row are located in different positions. Between two adjacent rows of the first anodes 11, and the second portion 02 is drawn out along the row direction X to the outside of the first display area AA1.
  • the second pixel circuit D2 and the corresponding second light-emitting device are arranged in the second display area AA2, and the first pixel circuit corresponding to the first display area AA1 with higher light transmittance D1 is not arranged in the first display area AA1, and the density (ie pixel resolution) of the plurality of first light-emitting devices in the first display area AA1 is the same as the density of the plurality of second light-emitting devices in the second display area AA2, so as to achieve
  • the under-screen camera display area ie the first display area AA1 can display images with the same pixel resolution, which can improve the luminous brightness of the under-screen camera display area and reduce the main display area (ie the second display area AA2) and the under-screen camera display.
  • the diameter of the hole in the display area of the camera under the screen can be enlarged, so as to achieve a better full-screen display effect and user experience.
  • the wiring between the first anode and the first anode is electrically connected through a via hole penetrating the insulating layer between them, and the space between the first anodes in two adjacent rows does not strictly refer to the space between the first anodes in the adjacent two rows.
  • the orthographic projection of the second portion of the first anode trace on the base substrate may overlap with the orthographic projection of the first anode on the base substrate, so in the embodiment of the present disclosure, the first anode in the adjacent two rows is between the first anodes.
  • the interval refers to the gap between two adjacent rows of first anodes and the adjacent two rows of via holes connected to the corresponding transparent conductive layer, that is, between two adjacent rows of first anodes refers to the two adjacent rows of via holes V in FIG. 5 . between.
  • the shape of the first display area AA1 may be a circle as shown in FIG. 2 , or may be other shapes such as an ellipse, a rectangle, or a polygon, which can be designed according to actual needs. Do limit.
  • the second display area AA2 may surround the periphery of the first display area AA1 as shown in FIG. 2; it may also surround a part of the first display area AA1, for example, surrounding the left side, the lower side and the right side of the first display area AA1, while the first display area AA1 is surrounded by the first display area AA1.
  • the upper boundary of the display area AA1 coincides with the upper boundary of the second display area AA2.
  • the first light emitting device and the second light emitting device refer to pixels actually used for displaying light emission, and the first pixel circuit and the second pixel circuit are circuits for connecting the light emitting pixels.
  • a plurality of first pixel circuits D1 are located in a frame adjacent to the first display area AA1 In the area BB, FIG. 2 specifically shows that a plurality of first pixel circuits D1 are located in the upper border area.
  • the transparency between the first pixel circuit D1 and the first light-emitting device can be effectively reduced.
  • the length of the trace is reduced, thereby reducing the resistance of the transparent trace and improving the long-range uniformity of the driving signal.
  • the second display area AA2 has a seventh area A1 and an eighth area A2 adjacent to the first display area AA1, and the seventh area A1 and The eighth area A2 is arranged oppositely, and the area occupied by the second pixel circuits D2 in the seventh area A1 and the eighth area A2 is smaller than the area occupied by the second pixel circuits D2 in the other second display areas AA2, and a plurality of first pixels
  • the circuit D1 is located in the seventh area A1 and the eighth area A2.
  • the present disclosure arranges a plurality of first pixel circuits D1 corresponding to the first display area AA1 in the seventh area A1 and the eighth area by reducing the area of the second pixel circuits D2 in the seventh area A1 and the eighth area A2 A2, this can also realize that the under-screen camera display area (ie the first display area AA1) can display images with the same pixel resolution, improve the luminous brightness of the under-screen camera display area, and reduce the main display area (ie the second display area AA2). ) and the brightness difference between the camera display area under the screen (ie, the first display area AA1).
  • each area in FIG. 6 only illustrates part of the pixel circuit structure.
  • At least one transparent conductive layer includes a first transparent conductive layer and a second transparent conductive layer that are stacked and insulated from each other;
  • the first anode wiring 101 corresponding to one row (eg, the last row) of the first anodes 11 is located in the first transparent conductive layer
  • the first anode wiring 101 corresponding to the first anode 11 in another row (for example, the penultimate row) is located in the second transparent conductive layer.
  • the first anode wiring 101 corresponding to the row of the first anode 11 is located in the second transparent conductive layer.
  • first anode wirings 101 corresponding to the first anodes 11 in the odd-numbered rows are illustrated in the embodiments of the present disclosure, and the wiring modes of the first anode wirings 101 corresponding to the first anodes 11 in the even-numbered rows are shown.
  • the routing method of the first anode wirings 101 corresponding to the first anodes 11 in the odd-numbered rows is the same, and the difference between the odd-numbered rows and the even-numbered rows is only that the corresponding cathode wirings are located in different conductive layers.
  • FIG. 7 is a schematic top-view structural diagram of the first transparent conductive layer 20 and the second transparent conductive layer 30 , and each transparent conductive layer contains The multiple first anode traces do not overlap each other, for example, the multiple first anode traces 101 contained in the first transparent conductive layer 20 do not overlap each other, and the multiple first anode traces contained in the second transparent conductive layer 30 The traces 101 do not overlap each other; the orthographic projections of the multiple first anode traces contained in different transparent conductive layers on the substrate are interlaced with each other, for example, the multiple first anode traces contained in the first transparent conductive layer 20
  • the orthographic projection of 101 on the base substrate 10 and the orthographic projection of the plurality of first anode wires 101 included in the second transparent conductive layer 30 on the base substrate 10 are interlaced with each other.
  • the first transparent conductive layer 20 and the second transparent conductive layer 30 are alternately routed in the gap between each other, so as to reduce the overlap between the two layers as much as possible, thereby reducing the distance between the first anode wirings 101 loading.
  • an insulating layer 40 is provided between the first anode 11 and the transparent conductive layer (eg, the first transparent conductive layer 20 ).
  • the layer 40 has a plurality of vias V for electrically connecting the first anode 11 and the first anode wiring 101 , the orthographic projection of the first anode wiring 101 on the base substrate 10 and the vias V on the base substrate 10 The orthographic projections do not overlap.
  • the patterns of the first transparent conductive layer and the second transparent conductive layer are the same. Specifically, when the odd-numbered rows of the first anode traces 101 in FIG. 5 are arranged on the first transparent conductive layer, the even-numbered rows of the first anode traces 101 in FIG. 5 are arranged on the second transparent conductive layer, and FIG. 5 only shows the odd-numbered rows
  • the routing mode of the first anode traces 101, the routing mode of the first anode traces 101 in the even rows is the same as the routing mode of the odd routing wires, the difference is that the orthographic projections of the odd routing wires and the even routing wires are staggered.
  • the first anode wirings between two adjacent rows of first anodes 11 corresponding to each transparent conductive layer (for example, in FIG. 5 )
  • the number of first anode traces 101) between the first anodes 11 in the last row and the first anodes 11 in the penultimate row is not greater than the first number.
  • each transparent conductive layer is provided with anode traces, due to pixel resolution and other requirements, the number of wirings between two adjacent rows of first anodes 11 in each transparent conductive layer is generally 11-15, for example, the first number may be 13, the present disclosure includes two transparent conductive layers as For example, in the overall structure of the two transparent conductive layers, the total number of wires between the first anodes 11 in two adjacent rows generally does not exceed 26; the first anodes 11 in the adjacent two adjacent rows corresponding to each transparent conductive layer The number of the first anode traces in between (for example, the first anode traces 101 between the first anode 11 in the first column and the first anode 11 in the second column in the right number in FIG.
  • each transparent conductive layer is provided with anode wiring.
  • the number of wirings between the first anodes 11 in two adjacent columns of each transparent conductive layer is generally 2-6, for example, the second The number can be 4.
  • the present disclosure takes two transparent conductive layers as an example. In the overall structure of the two transparent conductive layers, the total number of wires between the first anodes 11 in two adjacent rows generally does not exceed 8. ; so the first quantity is greater than the second quantity.
  • the number of wirings between the first anodes in two adjacent rows is 7 as an example for illustration in FIG. 5 .
  • the wiring between the first anode and the first anode is electrically connected through a via hole penetrating the insulating layer between them, and the distance between the first anodes in two adjacent columns does not strictly refer to the distance between the first anodes in the adjacent two columns.
  • the orthographic projection of the first portion of the first anode trace on the base substrate may overlap with the orthographic projection of the first anode on the base substrate, so in this embodiment of the present disclosure, between two adjacent rows of first anodes Refers to the gap between the adjacent two rows of first anodes and the corresponding transparent conductive layers connected to the adjacent two rows of via holes, that is, between the adjacent two rows of first anodes refers to the gap between the two adjacent rows of via holes V in FIG. 5 . between.
  • At least one row of the first anodes is divided into adjacent first regions, second regions and third regions, for example, the last row in FIG. 5 .
  • the first anode is divided into adjacent first regions B1, second regions B2 and third regions B3, and the first anode wiring 101 corresponding to the first region B1 is located in the gap ( Between the last row and the first row that is mirror-symmetrical with FIG.
  • the first anode traces 101 corresponding to the second region B2 are located in the gap between the first anodes 11 in the same two adjacent rows (the last row and the penultimate row between), the first anode traces 101 corresponding to the third region B3 are located in the gap between the first anodes 11 in the same two adjacent rows (between the penultimate row and the penultimate third row).
  • the first anode wirings 101 corresponding to the second region B2 and the third region B3 are located in the gaps between the first anodes 11 in two adjacent rows.
  • FIG. 9 is a complete anode wiring structure of odd rows of pixels in the first display area AA1
  • FIG. 5 is a schematic diagram of a quarter area of the upper left part in FIG. 9
  • FIG. 9 The lower left part of the AA1 also has another quarter area of the first display area AA1, and the space between the first anode 11 in the last row of FIG. 5 and the first anode 11 in the first row of the quarter area in the lower left part in FIG.
  • the two are equally divided, so there are three first anode wirings on the left side of the last row of FIG. 5 . 101 and the three first anode traces 101 on the left side of the first row of the first row of the lower left quarter area in FIG. Between the first anodes 11 in the first row. Taking seven first anode traces 101 corresponding to the second area B2 and the third area B3 as an example, the seven first anode traces 101 corresponding to the second area B2 are all arranged in the last row of the first anode in FIG. 5 .
  • the first pixel circuit D1 is electrically connected.
  • the first area B1 is close to the second display area AA2
  • the second area B2 is located in the first area B1 away from the second display area
  • the third area B3 is located on the side of the second area B2 away from the second display area AA2;
  • the number of the first anode wirings 101 corresponding to the first region B1 is not more than half of the first number (for example, the first number is 7, and the number of the first anode wirings 101 in the first region B1 in FIG. 5 is 3).
  • the numbers of the first anode wirings 101 corresponding to the second region B2 and the third region B3 are both the first number (for example, the numbers of the first anode wirings 101 corresponding to the second region B2 and the third region B3 are both 7).
  • At least one row of the first anodes is divided into adjacent fourth, fifth and sixth regions, for example, the penultimate area in FIG. 5 .
  • the three rows of first anodes are divided into adjacent fourth regions B4, fifth regions B5 and sixth regions B6.
  • the first anode wirings 101 corresponding to the fourth region B4 are located between the same two adjacent rows of first anodes 11.
  • the first anode traces 101 corresponding to the three areas can only be located on the upper side thereof. Between the first anodes 11 in two adjacent rows, and the number of wirings in the fourth area B4 and the fifth area B5 are both 7, then 7 fourth areas B4 are arranged between the penultimate third row and the penultimate fourth row Corresponding to the first anode wiring 101, seven first anode wirings 101 corresponding to the fifth region B5 are arranged between the fourth-to-last row and the fifth-to-last row, then the third-to-last row of pixels corresponding to the sixth region B6 corresponds to three An anode wiring 101 can only be vertically routed in the column direction, and then go between two adjacent rows of the first anodes 11 with less than 7 wirings and lead to the second display area AA2 in the row direction.
  • the fourth area B4 is close to the second display area AA2
  • the fifth area B5 is located in the fourth area B4 away from the second display area
  • the sixth area B6 is located on the side of the fifth area B5 away from the second display area AA2;
  • the number of the first anode traces 101 corresponding to the fourth area B4 is the first number (for example, the number of the first anode traces 101 corresponding to the fourth area B4 is 7), and the first anode traces corresponding to the fifth area B5
  • the number of 101 is the first number (for example, the number of the first anode wirings 101 corresponding to the fifth region B5 is equal to 7), and the number of the first anode wirings 101 corresponding to the sixth region B6 is not more than half of the first number (for example, The number of the first anode traces 101 corresponding to the sixth region B6 is less than or equal to 3).
  • the first anode traces 101 in the upper left part of the first display area AA1 shown in FIG. 4 is described in detail, as shown in FIG. row, fifth from last, seventh from last, ninth from last, eleventh from last, thirteenth from last and fifteenth from last), the first from last row is divided into three areas: B1, B2 and B3, B2 and B3 correspond to 7 first anode traces 101, and the first anode traces 101 corresponding to the B2 area extend along the column direction to between the first anode 11 in the penultimate row and the first anode 11 in the penultimate row, along the row The direction extends and leads to the second display area AA2, and the three first anode traces 101 corresponding to B1 extend downward and then extend to the left to lead to the second display area AA2.
  • the first anode traces 101 corresponding to the seven first anodes 11 on the left are arranged between the first anodes 11 of the third to last row and the first anodes 11 of the fourth to last row.
  • the first anode traces 101 corresponding to the seven first anodes 11 are arranged between the first anodes 11 in the fourth-to-last row and the first anodes 11 in the fifth-to-last row, and three first anodes 11 remain on the right side of the third-to-last row. .
  • the first anode traces 101 corresponding to the seven first anodes 11 on the left are arranged between the first anodes 11 in the fifth-to-last row and the first anodes 11 in the sixth-to-last row.
  • the first anode wiring 101 corresponding to the first anode 11 is disposed between the first anode 11 in the sixth from last row and the first anode 11 in the seventh from last row, and there are three first anodes 11 left on the right side of the fifth from last row.
  • the first anode traces 101 corresponding to the seven first anodes 11 on the left are arranged between the first anodes 11 of the seventh-to-last row and the first anodes 11 of the eighth-to-last row.
  • the first anode traces 101 corresponding to the five first anodes 11 are arranged between the first anode 11 in the eighth-to-last row and the first anode 11 in the ninth-to-last row.
  • first anode wiring 101 corresponding to the left first anode among the three first anodes 11 on the right can be routed upward to the edge between the first anode 11 in the eighth-to-last row and the first anode 11 in the ninth-to-last row. Lead out in the row direction.
  • the first anode traces 101 corresponding to the seven first anodes 11 on the left are arranged between the first anodes 11 in the ninth-to-last row and the first anodes 11 in the tenth-to-last row.
  • the first anode traces 101 corresponding to the six first anodes 11 are arranged between the tenth-to-last row of the first anodes 11 and the tenth-to-last row of the first anodes 11.
  • There are only six first anode traces 101 between the first anodes 11 in one row so the first anode corresponding to the first anode on the left of the three first anodes 11 on the right side of the first anode 11 in the seventh-to-last row is routed.
  • the line 101 can be routed upward, and is led out in the row direction between the first anode 11 in the tenth last row and the first anode 11 in the eleventh last row.
  • the first anode traces 101 corresponding to the seven first anodes 11 on the left are arranged between the first anodes 11 in the eleventh row from the bottom and the first anodes 11 in the twelfth row from the bottom.
  • the first anode traces 101 corresponding to the four first anodes 11 in total are arranged between the first anode 11 in the twelfth last row and the first anode 11 in the twelfth last row.
  • the first anode wiring 101 corresponding to the first anode in the middle can be routed upwards and lead out in the row direction between the first anode 11 in the twelfth last row and the first anode 11 in the thirteenth last row.
  • the first anode traces 101 corresponding to the seven first anodes 11 on the left are arranged between the first anodes 11 in the thirteenth row from the bottom and the first anodes 11 in the fourteenth row from the bottom. 10.
  • the first anode traces 101 corresponding to a total of three first anodes 11 are arranged between the first anode 11 in the fourteenth last row and the first anode 11 in the fifteenth last row.
  • the anode wiring 101 can be routed upwards, and is led out along the row direction between the first anode 11 of the fourteenth from the bottom row and the first anode 11 of the fifteenth from the bottom row, the fifth from the bottom row, the seventh from the bottom row and the ninth from the bottom row.
  • the first anode wiring 101 corresponding to the rightmost first anode 11 among the three first anodes 11 on the right side of an anode 11 can be routed upward to the first anode 11 in the fourteenth last row and the first anode 11 in the last fifteenth row.
  • An anode 11 is drawn out along the row direction.
  • the first anode traces 101 corresponding to the seven first anodes 11 are arranged between the first anodes 11 in the fifteenth row from the bottom and the first anodes 11 in the sixteenth row from the bottom.
  • the first anode wiring 101 corresponding to the rightmost first anode among the three first anodes 11 on the right side of the first anodes 11 in the thirteen rows can be routed upward to the upper edge of the first anode 11 in the sixteenth row from the bottom.
  • first anodes 11 on the right side of the first anode 11 in the penultimate row and the two first anode traces 101 corresponding to the rightmost first anode 11 can be routed upward to the penultimate row. Sixteen rows of first anodes 11 are drawn from the upper side along the row direction.
  • FIG. 5 takes an example of accommodating up to seven first anode wirings 101 between two adjacent rows of first anodes. In practical application, wiring is performed according to the wiring method of the present disclosure.
  • the first display area AA1 is divided into four equal parts (M1, M2, M3) along the center lines of the row direction X and the column direction Y. and M4), each equal portion of the first anode wiring adopts the arrangement of the first anode wiring 101 in the display substrate shown in FIG. 5 .
  • the four equal parts include a first equal part M1, a second equal part M2, a third equal part M3 and The fourth equal portion M4, the first equal portion M1 and the second equal portion M2 are arranged symmetrically with respect to the center line of the column direction Y, the second equal portion M2 and the third equal portion M3 are symmetrically arranged with respect to the center line of the row direction X, and the third The equal parts M3 and the fourth equal parts M4 are arranged symmetrically about the center line of the column direction Y, and the fourth equal parts M4 and the first equal parts M1 are symmetrically arranged about the center line of the row direction X.
  • the one closest to the fourth equal portion M4 is the first anode H1 in the first row
  • the fourth equal portion M4 is the first anode H1 in the first row.
  • the one closest to the first equal portion M1 is the first anode H2 of the second row
  • the first gap d1 is between the first anode H1 of the first row and the first anode H2 of the second row
  • the first anode H1 of the first row is close to the first anode H1 of the first row.
  • the first anode traces 101 corresponding to the first area B1 of the second display area AA2 and the first anode traces 101 corresponding to the first area B1 of the second row of the first anodes H2 near the second display area AA2 are located in the within a gap.
  • the transparent conductive layers in the embodiments of the present disclosure are two layers.
  • only one transparent conductive layer is shown in FIG. 5 and FIG. 9 .
  • the arrangement of the first anode traces of the odd-numbered rows corresponds to the other transparent conductive layer is the same as that of the odd-numbered rows, but the orthographic projection of the two-layer traces Staggered settings.
  • the transparent conductive layer can also be only one layer, then the first anode in each row of the first display area adopts the same transparent conductive layer to set the first anode wiring to be electrically connected to the second pixel circuit; the transparent conductive layer
  • the layers can also be three layers, then the first transparent conductive layer is provided with 1, 4, 7, etc. rows of first anode wirings, and the second transparent conductive layer is provided with 2, 5, 8, etc. rows of first anode wirings Lines, 3, 6, 9, etc. rows of first anode wirings are arranged on the third transparent conductive layer, and so on for other multi-layer transparent conductive layers.
  • the material of the transparent conductive layer may be ITO.
  • the first display area AA1 is configured to install a photosensitive device, such as a camera module.
  • a larger area of light transmission area can be provided, which is helpful for adapting to a larger size camera module.
  • an embodiment of the present disclosure further provides a display panel including the above-mentioned display substrate.
  • an embodiment of the present disclosure further provides a display device, including: a photosensitive device (eg, a camera module), and the above-mentioned display panel; wherein, the photosensitive device is disposed in the first display area AA1 of the display substrate.
  • the photosensitive device may be a camera module.
  • the display device can be: mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, smart watch, fitness wristband, personal digital assistant, and any other product or component with display function.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present invention.
  • the implementation of the display device can refer to the embodiment of the above-mentioned display panel, and the repetition will not be repeated.
  • Embodiments of the present disclosure provide a display substrate, a display panel, and a display device, wherein a second pixel circuit and a corresponding second light-emitting device are arranged in a second display area, and a first display area corresponding to a higher light transmittance
  • the pixel circuit is not arranged in the first display area, and the density (ie pixel resolution) of the plurality of first light-emitting devices in the first display area is the same as the density of the plurality of second light-emitting devices in the second display area, so as to achieve the under-screen
  • the camera display area ie the first display area

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Abstract

一种显示基板、显示面板及显示装置，显示基板包括：衬底基板（10），具有显示区（AA）和包围显示区（AA）的边框区（BB），显示区（AA）包括：第一显示区（AA1）和至少位于第一显示区（AA1）一侧的第二显示区（AA2）；多个第一发光器件在第一显示区（AA1）的密度与多个第二发光器件在第二显示区（AA2）的密度相同；至少一层透明导电层，位于驱动电路层和发光器件层之间；至少一层透明导电层中的每一层包括与第一阳极（11）电连接的多条第一阳极走线（101）；第一阳极走线（101）至少包括沿列方向（Y）延伸的第一部分（01）和沿行方向（X）延伸的第二部分（02），同一行第一阳极（11）电连接的多条第一阳极走线（101）的第二部分（02）位于不同的相邻两行第一阳极（11）之间，且第二部分（02）沿行方向（X）引出至第一显示区（AA1）外侧。

Description

显示基板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示基板、显示面板及显示装置。
背景技术
随着智能手机的高速发展，不仅要求手机的外形美观，还需兼顾给手机使用者带来更出色的视觉体验。各大厂商开始在智能手机上提高屏占比，使得全面屏成为智能手机的一个新竞争点。随着全面屏的发展，在性能和功能上的提升需求也与日俱增，屏下摄像头在不影响高屏占比的前提下，在一定程度上可以带来视觉和使用体验上的冲击感。
发明内容
一方面，本公开实施例提供了一种显示基板，包括：
衬底基板，具有显示区和包围所述显示区的边框区，所述显示区包括：第一显示区和至少位于所述第一显示区一侧的第二显示区；其中，所述第一显示区的透光率大于所述第二显示区的透光率；
驱动电路层，位于所述衬底基板之上；所述驱动电路层包括多个第一像素电路和多个第二像素电路，所述第一像素电路在所述衬底基板上的正投影与所述第一显示区在所述衬底基板上的正投影不交叠，所述第二像素电路位于所述第二显示区；
发光器件层，位于所述驱动电路层背离所述衬底基板的一侧，所述发光器件层包括多个第一发光器件和多个第二发光器件，所述第一发光器件位于所述第一显示区，所述第二发光器件位于所述第二显示区，各所述第一发光器件均包括独立设置的第一阳极，各所述第二发光器件均包括独立设置的第 二阳极；多个所述第一阳极中的每个分别与所述多个第一像素电路中的每个对应电连接，多个所述第二阳极中的每个分别与所述多个第二像素电路中的每个对应电连接；其中，所述多个第一发光器件在所述第一显示区的密度与所述多个第二发光器件在所述第二显示区的密度相同；
至少一层透明导电层，位于所述驱动电路层和所述发光器件层之间；所述至少一层透明导电层中的每一层包括与所述第一阳极电连接的多条第一阳极走线；所述第一阳极走线至少包括沿列方向延伸的第一部分和沿行方向延伸的第二部分，同一行所述第一阳极电连接的多条第一阳极走线的第二部分位于不同的相邻两行第一阳极之间，且所述第二部分沿所述行方向引出至所述第一显示区外侧。
可选地，在本公开实施例提供的上述显示基板中，所述至少一层透明导电层包括层叠设置且相互绝缘的第一透明导电层和第二透明导电层；
在每相邻两行所述第一阳极中，其中一行所述第一阳极对应的第一阳极走线位于所述第一透明导电层，另一行所述第一阳极对应的第一阳极走线位于所述第二透明导电层。
可选地，在本公开实施例提供的上述显示基板中，所述第一透明导电层和所述第二透明导电层的图形相同。
可选地，在本公开实施例提供的上述显示基板中，每一所述透明导电层对应的相邻两行第一阳极之间的第一阳极走线的数量不大于第一数量，每一所述透明导电层对应的相邻两列第一阳极之间的第一阳极走线的数量不大于第二数量，所述第一数量大于所述第二数量。
可选地，在本公开实施例提供的上述显示基板中，至少一行所述第一阳极分为相邻的第一区域、第二区域和第三区域，所述第一区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第二区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第三区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第一区域、所述第二区域和所述第三区域对应的第一阳极走线位于不同的相邻两行第一阳极之间。
可选地，在本公开实施例提供的上述显示基板中，所述第一区域靠近所述第二显示区，所述第二区域位于所述第一区域远离所述第二显示区一侧，所述第三区域位于所述第二区域远离所述第二显示区一侧；
所述第一区域对应的第一阳极走线的数量不大于所述第一数量的一半，所述第二区域和所述第三区域对应的第一阳极走线的数量均为所述第一数量。
可选地，在本公开实施例提供的上述显示基板中，至少一行所述第一阳极分为相邻的第四区域、第五区域和第六区域，所述第四区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第五区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第六区域对应的第一阳极走线位于不同的相邻两行第一阳极之间，且所述第四区域、所述第五区域和所述第六区域对应的第一阳极走线位于不同的相邻两行第一阳极之间。
可选地，在本公开实施例提供的上述显示基板中，所述第四区域靠近所述第二显示区，所述第五区域位于所述第四区域远离所述第二显示区一侧，所述第六区域位于所述第五区域远离所述第二显示区一侧；
所述第四区域对应的第一阳极走线的数量为所述第一数量，所述第五区域对应的第一阳极走线的数量为所述第一数量，所述第六区域对应的第一阳极走线的数量不大于所述第一数量的一半。
可选地，在本公开实施例提供的上述显示基板中，所述第一数量为11-15，所述第二数量为2-6。
可选地，在本公开实施例提供的上述显示基板中，每一所述透明导电层所含的多条第一阳极走线互不交叠，不同所述透明导电层所含的多条第一阳极走线在所述衬底基板上的正投影相互交错。
可选地，在本公开实施例提供的上述显示基板中，所述第一阳极和所述透明导电层之间具有绝缘层，所述绝缘层具有用于电连接所述第一阳极和所述第一阳极走线的多个过孔，所述第一阳极走线在所述衬底基板上的正投影与所述过孔在所述衬底基板上的正投影不交叠。
可选地，在本公开实施例提供的上述显示基板中，所述多个第一像素电 路位于与所述第一显示区邻近的所述边框区域。
可选地，在本公开实施例提供的上述显示基板中，所述第二显示区具有邻近所述第一显示区的第七区域和第八区域，所述第七区域和所述第八区域相对设置，所述第七区域和所述第八区域中的第二像素电路所占的面积小于其它所述第二显示区的第二像素电路所占的面积，所述多个第一像素电路位于所述第七区域和所述第八区域。
可选地，在本公开实施例提供的上述显示基板中，所述第一显示区的形状为圆形、椭圆形、矩形或多边形。
可选地，在本公开实施例提供的上述显示基板中，所述第一显示区被沿所述行方向和所述列方向的中心线划分为四等份，每一等份的第一阳极走线均采用权利要求1-13任一项所述的显示基板中第一阳极走线的排布方式。
可选地，在本公开实施例提供的上述显示基板中，所述四等份包括沿顺时针方向排列的第一等份、第二等份、第三等份和第四等份，所述第一等份和所述第二等份关于所述列方向的中心线对称设置，所述第二等份和所述第三等份关于所述行方向的中心线对称设置，所述第三等份和所述第四等份关于所述列方向的中心线对称设置，所述第四等份和所述第一等份关于所述行方向的中心线对称设置。
可选地，在本公开实施例提供的上述显示基板中，所述第一等份中最靠近所述第四等份的为第一行第一阳极，所述第四等份中最靠近所述第一等份的为第二行第一阳极，所述第一行第一阳极和所述第二行第一阳极之间为第一间隙，所述第一行第一阳极中靠近所述第二显示区的第一区域对应的第一阳极走线、以及所述第二行第一阳极中靠近所述第二显示区的第一区域对应的第一阳极走线均位于所述第一间隙内。
另一方面，本公开实施例还提供了一种显示面板，包括上述显示基板。
另一方面，本公开实施例还提供了一种显示装置，包括：感光器件，以及上述显示面板；所述感光器件被设置在所述显示基板的第一显示区。
附图说明
图1为相关技术中显示基板的俯视结构示意图；
图2为本公开实施例提供的一种显示基板的结构示意图；
图3为图2中第一显示区的放大示意图；
图4为图2中第一显示区走线的放大示意图；
图5为图4中左上部分的放大示意图；
图6为本公开实施例提供的又一种显示基板的结构示意图；
图7为本公开实施例提供的透明导电层的俯视结构示意图；
图8为本公开实施例提供的透明导电层的剖面结构示意图；
图9为图2中第一显示区走线的排布示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是 示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
相关技术中，如图1所示，屏下摄像头技术一般在显示区AA内设置第一显示区AA1和第二显示区AA2，其中第二显示区AA2占显示屏幕绝大部分，第一显示区AA1占据剩余部分，第一显示区AA1是屏下摄像头放置的位置。屏下摄像头就是指前置摄像头位于屏幕下方但并不影响屏幕显示功能，不使用前置摄像头的时候，摄像头上方的屏幕仍可以正常显示图像。所以从外观上看，屏下摄像头不会有任何相机孔，真正的达到了全面屏显示效果。但是，在目前有屏下摄像头设计的OLED显示装置中，第一显示区AA1的显示亮度比第二显示区AA2的显示亮度低至少一倍，是一个亟待解决的问题。
针对相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图2-图5所示，图2为显示基板的整体结构示意图，图3为图2中第一显示区AA1的结构示意图，图4为示意出图3中虚线框所在四分之一区域的详细结构示意图，图5为图4中虚线框所在四分之一区域的放大结构示意图，该显示基板包括：
衬底基板10，具有显示区AA和包围显示区的边框区BB，显示区AA包括：第一显示区AA1和至少位于第一显示区AA1一侧的第二显示区AA2；其中，第一显示区AA1的透光率大于第二显示区AA2的透光率；
驱动电路层，位于衬底基板10之上；驱动电路层包括多个第一像素电路D1和多个第二像素电路D2，第一像素电路D1在衬底基板10上的正投影与第一显示区AA1在衬底基板10上的正投影不交叠，第二像素电路D2位于第二显示区AA2；图1中仅示意出部分第一像素电路D1和第二像素电路D2；
发光器件层，位于驱动电路层背离衬底基板10的一侧，发光器件层包括多个第一发光器件和多个第二发光器件，第一发光器件位于第一显示区AA1，第二发光器件位于第二显示区AA2，各第一发光器件均包括独立设置的第一阳极11，各第二发光器件均包括独立设置的第二阳极12；多个第一阳极11中的每个分别与多个第一像素电路D1中的每个对应电连接，多个第二阳极 12中的每个分别与多个第二像素电路D2中的每个对应电连接；其中，多个第一发光器件在第一显示区AA1的密度(即像素分辨率)与多个第二发光器件在第二显示区AA2的密度相同；
至少一层透明导电层，位于驱动电路层和发光器件层之间；至少一层透明导电层中的每一层包括与第一阳极11电连接的多条第一阳极走线101；第一阳极走线101至少包括沿列方向Y延伸的第一部分01和沿行方X向延伸的第二部分02，同一行第一阳极11电连接的多条第一阳极走线101的第二部分02位于不同的相邻两行第一阳极11之间，且第二部分02沿行方向X引出至第一显示区AA1外侧。
在本公开实施例提供的上述显示基板中，第二显示区AA2内设置了第二像素电路D2和对应的第二发光器件，透光率较高的第一显示区AA1对应的第一像素电路D1不设置在第一显示区AA1，且多个第一发光器件在第一显示区AA1的密度(即像素分辨率)与多个第二发光器件在第二显示区AA2的密度相同，从而达到屏下摄像头显示区(即第一显示区AA1)既可以显示同样像素分辨率的图像，可以提升屏下摄像头显示区发光亮度，降低主要显示区(即第二显示区AA2)和屏下摄像头显示区(即第一显示区AA1)的亮度差异，同时可以扩大屏下摄像头显示区孔的直径，从而实现更优的全屏显示效果和用户体验。
需要说明的是，第一阳极和第一阳极走线通过贯穿二者之间绝缘层的过孔电连接，相邻两行第一阳极之间不是严格指相邻两行第一阳极之间的间隙处，第一阳极走线的第二部分在衬底基板的正投影可以与第一阳极在衬底基板的正投影有交叠，因此本公开实施例中的相邻两行第一阳极之间是指相邻两行第一阳极与对应透明导电层连接的相邻两行过孔之间的间隙，即相邻两行第一阳极之间是指图5中相邻两行过孔V之间。
需要说明的是，在本公开中第一显示区AA1的形状可以为图2所示的圆形，也可以为椭圆形、矩形或多边形等其他形状，具体可根据实际需要进行设计，在此不做限定。第二显示区AA2可以如图2所示环绕第一显示区AA1 的周边；也可以包围部分第一显示区AA1，例如包围第一显示区AA1的左侧、下侧和右侧，而第一显示区AA1的上侧边界与第二显示区AA2的上侧边界重合。另外，在本公开中第一发光器件和第二发光器件是指实际用于显示发光的像素，第一像素电路和第二像素电路是用于连接发光像素的电路。
可选地，为了提高第一显示区的透光率，在本公开实施例提供的上述显示基板中，如图2所示，多个第一像素电路D1位于与第一显示区AA1邻近的边框区域BB，图2具体示出了多个第一像素电路D1位于上边框区域。另外，通过将多个第一像素电路D1设置在多个第一发光器件和多个第二发光器件共同邻近的边框区域BB，可以有效减小第一像素电路D1与第一发光器件之间透明走线的长度，进而减小该透明走线电阻，提高驱动信号的长程均一性。
可选地，在本公开实施例提供的上述显示基板中，如图6所示，第二显示区AA2具有邻近第一显示区AA1的第七区域A1和第八区域A2，第七区域A1和第八区域A2相对设置，第七区域A1和第八区域A2中的第二像素电路D2所占的面积小于其它第二显示区AA2的第二像素电路D2所占的面积，多个第一像素电路D1位于第七区域A1和第八区域A2。即本公开通过减少第七区域A1和第八区域A2内第二像素电路D2的面积，把与第一显示区AA1相对应的多个第一像素电路D1设置在第七区域A1和第八区域A2，这样也可以实现屏下摄像头显示区(即第一显示区AA1)既可以显示同样像素分辨率的图像，可以提升屏下摄像头显示区发光亮度，降低主要显示区(即第二显示区AA2)和屏下摄像头显示区(即第一显示区AA1)的亮度差异。
需要说明的是，图6中各个区域仅示意出部分像素电路结构。
可选地，在本公开实施例提供的上述显示基板中，如图5所示，至少一层透明导电层包括层叠设置且相互绝缘的第一透明导电层和第二透明导电层；
在每相邻两行第一阳极11中，例如图5中最后一行和倒数第二行，其中一行(例如最后一行)第一阳极11对应的第一阳极走线101位于第一透明导电层，另一行(例如倒数第二行)第一阳极11对应的第一阳极走线101位于 第二透明导电层。
具体地，假设图5中从最后一行向上依次为第一行、第二行、第三行……，则奇数行第一阳极11对应的第一阳极走线101位于第一透明导电层，偶数行第一阳极11对应的第一阳极走线101位于第二透明导电层。
需要说明的是，本公开实施例图4和图5中仅示意奇数行第一阳极11对应的第一阳极走线101，偶数行第一阳极11对应的第一阳极走线101的走线方式与奇数行第一阳极11对应的第一阳极走线101的走线方式相同，奇数行和偶数行的区别仅在于各自对应的阴极走线位于不同的导电层。
可选地，在本公开实施例提供的上述显示基板中，如图7所示，图7为第一透明导电层20和第二透明导电层30的俯视结构示意图，每一透明导电层所含的多条第一阳极走线互不交叠，例如第一透明导电层20所含的多条第一阳极走线101互不交叠，第二透明导电层30所含的多条第一阳极走线101互不交叠；不同透明导电层所含的多条第一阳极走线在衬底基板上的正投影相互交错，例如第一透明导电层20所含的多条第一阳极走线101在衬底基板10上的正投影与第二透明导电层30所含的多条第一阳极走线101在衬底基板10上的正投影相互交错。即在采用两层透明导电层时，第一透明导电层20和第二透明导电层30交替在对方间隙走线，尽量减少两层之间交叠，从而减小第一阳极走线101之间的loading(负载)。
可选地，在本公开实施例提供的上述显示基板中，如图6和图8所示，第一阳极11和透明导电层(例如第一透明导电层20)之间具有绝缘层40，绝缘层40具有用于电连接第一阳极11和第一阳极走线101的多个过孔V，第一阳极走线101在衬底基板10上的正投影与过孔V在衬底基板10上的正投影不交叠。
可选地，在本公开实施例提供的上述显示基板中，第一透明导电层和第二透明导电层的图形相同。具体地，当第一透明导电层上排布图5中奇数行第一阳极走线101时，第二透明导电层排布图5中偶数行第一阳极走线101，图5仅示意奇数行第一阳极走线101的走线方式，偶数行第一阳极走线101 的走线方式与奇数行走线方式相同，区别在于奇数行走线和偶数行走线的正投影交错设置。
可选地，在本公开实施例提供的上述显示基板中，如图5所示，每一透明导电层对应的相邻两行第一阳极11之间的第一阳极走线(例如图5中最后一行第一阳极11和倒数第二行第一阳极11之间的第一阳极走线101)的数量不大于第一数量，由于每一透明导电层均设置阳极走线，目前由于像素分辨率等要求，每一层透明导电层的相邻两行第一阳极11之间的走线数量一般为11-15条，例如第一数量可以为13条，本公开以包括两层透明导电层为例，则在两层透明导电层的整体结构中，相邻两行第一阳极11之间的走线总数量一般不超过26条；每一透明导电层对应的相邻两列第一阳极11之间内的第一阳极走线(例如图5中右数第一列第一阳极11和第二列第一阳极11之间的第一阳极走线101)的数量不大于第二数量，由于每一透明导电层均设置阳极走线，目前由于像素分辨率等要求，每一层透明导电层的相邻两列第一阳极11之间的走线数量一般为2-6条，例如第二数量可以为4条，本公开以包括两层透明导电层为例，则在两层透明导电层的整体结构中，相邻两列第一阳极11之间的走线总数量一般不超过8条；因此第一数量大于第二数量。
需要说明的是，为了清楚的示意第一显示区AA1的第一阳极走线101的布线方式，图5中以相邻两行第一阳极之间走线数量为7条为例进行说明。
需要说明的是，第一阳极和第一阳极走线通过贯穿二者之间绝缘层的过孔电连接，相邻两列第一阳极之间不是严格指相邻两列第一阳极之间的间隙处，第一阳极走线的第一部分在衬底基板的正投影可以与第一阳极在衬底基板的正投影有交叠，因此本公开实施例中的相邻两列第一阳极之间是指相邻两列第一阳极与对应透明导电层连接的相邻两列过孔之间的间隙，即相邻两列第一阳极之间是指图5中相邻两列过孔V之间。
可选地，在本公开实施例提供的上述显示基板中，如图5所示，至少一行第一阳极分为相邻的第一区域、第二区域和第三区域，例如图5中最后一行第一阳极分为相邻的第一区域B1、第二区域B2和第三区域B3，第一区域 B1对应的第一阳极走线101位于同一相邻两行第一阳极11之间的间隙(最后一行和与图5镜像对称的第一行之间)，第二区域B2对应的第一阳极走线101位于同一相邻两行第一阳极11之间的间隙(最后一行和倒数第二行之间)，第三区域B3对应的第一阳极走线101位于同一相邻两行第一阳极11之间的间隙(倒数第二行和倒数第三行之间)，第一区域B1、第二区域B2和第三区域B3对应的第一阳极走线101位于不同的相邻两行第一阳极11之间的间隙。
具体地，如图5和图9所示，图9为第一显示区AA1的奇数行像素的完整阳极走线布线结构，图5为图9中左上部分四分之一区域的示意图，图9的左下部分还具有另外第一显示区AA1的四分之一区域，图5的最后一行第一阳极11和图9中左下部分四分之一区域的第一行第一阳极11之间可以作为该两行第一区域B1的阳极走线布线区域，由于相邻两行第一阳极之间可以设置7条走线，二者均分，因此图5最后一行的左侧三条第一阳极走线101和图9中左下部分四分之一区域的第一行左侧三条第一阳极走线101，分别分布在图5的最后一行第一阳极11和图9中左下部分四分之一区域的第一行第一阳极11之间。以第二区域B2和第三区域B3对应的第一阳极走线101均为7条为例，第二区域B2对应的7条第一阳极走线101均设置在图5中最后一行第一阳极11和倒数第二行第一阳极11之间，且各第一阳极走线101先向列方向Y延伸，然后再向行方向X延伸引出至第一显示区AA1，之后和图2或图6的第一像素电路D1电连接。
可选地，在本公开实施例提供的上述显示基板中，如图2和图5所示，第一区域B1靠近第二显示区AA2，第二区域B2位于第一区域B1远离第二显示区AA2一侧，第三区域B3位于第二区域B2远离第二显示区AA2一侧；
第一区域B1对应的第一阳极走线101的数量不大于第一数量的一半(例如第一数量为7，图5中第一区域B1的第一阳极走线101的数量为3)，第二区域B2和第三区域B3对应的第一阳极走线101的数量均为第一数量(例如第二区域B2和第三区域B3对应的第一阳极走线101的数量均为7)。
可选地，在本公开实施例提供的上述显示基板中，如图5所示，至少一 行第一阳极分为相邻的第四区域、第五区域和第六区域，例如图5中倒数第三行第一阳极分为相邻的第四区域B4、第五区域B5和第六区域B6，第四区域B4对应的第一阳极走线101位于同一相邻两行第一阳极11之间的间隙(倒数第三行和倒数第四行之间)，第五区域B5对应的第一阳极走线101位于同一相邻两行第一阳极11之间的间隙(倒数第四行和倒数第五行之间)，第六区域B6对应的第一阳极走线101位于不同的相邻两行第一阳极11之间的间隙，且第四区域B4、第五区域B5和第六区域B6对应的第一阳极走线101位于不同的相邻两行第一阳极11之间的间隙。
具体地，如图5所示，由于第四区域B4、第五区域B5和第六区域B6是倒数第三行像素，该三个区域对应的第一阳极走线101只能在其上侧的相邻两行第一阳极11之间设置，第四区域B4和第五区域B5中的走线数量均为7条，则倒数第三行和倒数第四行之间设置7条第四区域B4对应的第一阳极走线101，倒数第四行和倒数第五行之间设置7条第五区域B5对应的第一阳极走线101，那么倒数第三行像素中第六区域B6对应的三条第一阳极走线101只能先沿列方向竖直走线，走到不足7条走线的相邻两行第一阳极11之间沿行方向引出至第二显示区AA2。
可选地，在本公开实施例提供的上述显示基板中，如图2和图5所示，第四区域B4靠近第二显示区AA2，第五区域B5位于第四区域B4远离第二显示区AA2一侧，第六区域B6位于第五区域B5远离第二显示区AA2一侧；
第四区域B4对应的第一阳极走线101的数量为第一数量(例如第四区域B4对应的第一阳极走线101的数量均为7)，第五区域B5对应的第一阳极走线101的数量为第一数量(例如第五区域B5对应的第一阳极走线101的数量等于7)，第六区域B6对应的第一阳极走线101的数量不大于第一数量的一半(例如第六区域B6对应的第一阳极走线101的数量小于等于3)。
具体地，对图4所示的第一显示区AA1左上部分的第一阳极走线101的排布方式进行详细说明，如图5所示，奇数行像素中(倒数第一行、倒数第三行、倒数第五行、倒数第七行、倒数第九行、倒数第十一行、倒数第十三 行和倒数第十五行)，倒数第一行分为B1、B2和B3三个区域，B2和B3均对应7条第一阳极走线101，B2区域对应的第一阳极走线101沿列方向延伸至倒数第一行第一阳极11和倒数第二行第一阳极11之间，沿行方向延伸引出至第二显示区AA2，B1对应的三条第一阳极走线101向下延伸后向左延伸引出至第二显示区AA2。
倒数第三行，左侧7个第一阳极11对应的第一阳极走线101设置在倒数第三行第一阳极11和倒数第四行第一阳极11之间，左侧第8-14共7个第一阳极11对应的第一阳极走线101设置在倒数第四行第一阳极11和倒数第五行第一阳极11之间，该倒数第三行右侧还剩余3个第一阳极11。
倒数第五行，左侧7个第一阳极11对应的第一阳极走线101设置在倒数第五行第一阳极11和倒数第六行第一阳极11之间，左侧第8-14共7个第一阳极11对应的第一阳极走线101设置在倒数第六行第一阳极11和倒数第七行第一阳极11之间，该倒数第五行右侧还剩余3个第一阳极11。
倒数第7行，左侧7个第一阳极11对应的第一阳极走线101设置在倒数第七行第一阳极11和倒数第八行第一阳极11之间，左侧第8-12共5个第一阳极11对应的第一阳极走线101设置在倒数第八行第一阳极11和倒数第九行第一阳极11之间，由于倒数第八行第一阳极11和倒数第九行第一阳极11之间仅走了5条第一阳极走线101，因此倒数第三行第一阳极11右侧三个第一阳极11中的左侧第一阳极与倒数第五行第一阳极11右侧三个第一阳极11中的左侧第一阳极对应的第一阳极走线101可以向上走线，走到倒数第八行第一阳极11和倒数第九行第一阳极11之间沿行方向引出。
倒数第9行，左侧7个第一阳极11对应的第一阳极走线101设置在倒数第九行第一阳极11和倒数第十行第一阳极11之间，左侧第8-13共6个第一阳极11对应的第一阳极走线101设置在倒数第十行第一阳极11和倒数第十一行第一阳极11之间，由于倒数第十行第一阳极11和倒数第十一行第一阳极11之间仅走了6条第一阳极走线101，因此倒数第七行第一阳极11右侧三个第一阳极11中的左侧第一阳极对应的第一阳极走线101可以向上走线，走 到倒数第十行第一阳极11和倒数第十一行第一阳极11之间沿行方向引出。
倒数第11行，左侧7个第一阳极11对应的第一阳极走线101设置在倒数第十一行第一阳极11和倒数第十二行第一阳极11之间，左侧第8-11共4个第一阳极11对应的第一阳极走线101设置在倒数第十二行第一阳极11和倒数第十三行第一阳极11之间，由于倒数第十二行第一阳极11和倒数第十三行第一阳极11之间仅走了4条第一阳极走线101，因此倒数第五行、倒数第七行和倒数第九行第一阳极11右侧三个第一阳极11中的中间第一阳极对应的第一阳极走线101可以向上走线，走到倒数第十二行第一阳极11和倒数第十三行第一阳极11之间沿行方向引出。
倒数第13行，左侧7个第一阳极11对应的第一阳极走线101设置在倒数第十三行第一阳极11和倒数第十四行第一阳极11之间，左侧第8-10共3个第一阳极11对应的第一阳极走线101设置在倒数第十四行第一阳极11和倒数第十五行第一阳极11之间，由于倒数第十四行第一阳极11和倒数第十五行第一阳极11之间仅走了3条第一阳极走线101，因此倒数第十一行第一阳极11右侧三个第一阳极11中的中间第一阳极对应的第一阳极走线101可以向上走线，走到倒数第十四行第一阳极11和倒数第十五行第一阳极11之间沿行方向引出，倒数第五行、倒数第七行和倒数第九行第一阳极11右侧三个第一阳极11中的最右侧第一阳极11对应的第一阳极走线101可以向上走线，走到倒数第十四行第一阳极11和倒数第十五行第一阳极11之间沿行方向引出。
倒数第15行，7个第一阳极11对应的第一阳极走线101设置在倒数第十五行第一阳极11和倒数第十六行第一阳极11之间，倒数第十一行和倒数十三行第一阳极11右侧三个第一阳极11中的最右侧第一阳极对应的第一阳极走线101可以向上走线，走到倒数第十六行第一阳极11上侧沿行方向引出，倒数第三行第一阳极11右侧三个第一阳极11中的中间和最右侧第一阳极11对应的两条第一阳极走线101可以向上走线，走到倒数第十六行第一阳极11上侧沿行方向引出。
需要说明的是，图5是以相邻两行第一阳极之间最多容纳7条第一阳极走线101为例进行说明的，实际应用时，根据实际情况按照本公开的布线方式进行布线。
可选地，在本公开实施例提供的上述显示基板中，如图9所示，第一显示区AA1被沿行方向X和列方向Y的中心线划分为四等份(M1、M2、M3和M4)，每一等份的第一阳极走线均采用图5所示的显示基板中第一阳极走线101的排布方式。
可选地，在本公开实施例提供的上述显示基板中，如图9所示，四等份包括沿顺时针方向排列的第一等份M1、第二等份M2、第三等份M3和第四等份M4，第一等份M1和第二等份M2关于列方向Y的中心线对称设置，第二等份M2和第三等份M3关于行方向X的中心线对称设置，第三等份M3和第四等份M4关于列方向Y的中心线对称设置，第四等份M4和第一等份M1关于行方向X的中心线对称设置。
可选地，在本公开实施例提供的上述显示基板中，如图9所示，第一等份M1中最靠近第四等份M4的为第一行第一阳极H1，第四等份M4中最靠近第一等份M1的为第二行第一阳极H2，第一行第一阳极H1和第二行第一阳极H2之间为第一间隙d1，第一行第一阳极H1中靠近第二显示区AA2的第一区域B1对应的第一阳极走线101、以及第二行第一阳极H2中靠近第二显示区AA2的第一区域B1对应的第一阳极走线101均位于第一间隙内。
需要说明的是，本公开实施例中的透明导电层为两层，为清楚的示意每一透明导电层的阳极走线排布方式，图5和图9中仅示意其中一层透明导电层上对应奇数行第一阳极走线的排布方式，另一层透明导电层上对应的偶数行第一阳极走线的排布方式与奇数行的排布方式相同，但是两层走线的正投影交错设置。
当然，在具体实施时，透明导电层也可以仅为一层，则第一显示区每一行第一阳极均采用同一层透明导电层设置第一阳极走线与第二像素电路电连接；透明导电层也可以为三层，则第一透明导电层上设置1、4、7……等行第 一阳极走线，第二透明导电层上设置2、5、8……等行第一阳极走线，第三透明导电层上设置3、6、9……等行第一阳极走线，其他多层透明导电层的以此类推。
可选地，在本公开实施例提供的上述显示基板中，透明导电层的材料可以为ITO。
可选地，在本公开实施例提供的上述显示基板中，如图2所示，第一显示区AA1被配置为安装感光器件，例如摄像头模组。
由于在本公开中第一显示区AA1内仅存在第一发光器件，因此能够提供更大面积的透光区域，有助于适配更大尺寸的摄像头模组。
另一方面，本公开实施例还提供了一种显示面板，包括上述显示基板。
另一方面，本公开实施例还提供了一种显示装置，包括：感光器件(例如摄像头模组)，以及上述显示面板；其中，感光器件被设置在显示基板的第一显示区AA1。可选地，感光器件可以为摄像头模组。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。另外，由于该显示装置解决问题的原理与上述显示面板解决问题的原理相似，因此，该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本公开实施例提供的一种显示基板、显示面板及显示装置，第二显示区内设置了第二像素电路和对应的第二发光器件，透光率较高的第一显示区对应的第一像素电路不设置在第一显示区，且多个第一发光器件在第一显示区的密度(即像素分辨率)与多个第二发光器件在第二显示区的密度相同，从而达到屏下摄像头显示区(即第一显示区)既可以显示同样像素分辨率的图像，可以提升屏下摄像头显示区发光亮度，降低主要显示区(即第二显示区)和屏下摄像头显示区(即第一显示区)的亮度差异，同时可以扩大屏下摄像 头显示区孔的直径，从而实现更优的全屏显示效果和用户体验。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (19)

  1. 一种显示基板，其中，包括：
    衬底基板，具有显示区和包围所述显示区的边框区，所述显示区包括：第一显示区和至少位于所述第一显示区一侧的第二显示区；其中，所述第一显示区的透光率大于所述第二显示区的透光率；
    驱动电路层，位于所述衬底基板之上；所述驱动电路层包括多个第一像素电路和多个第二像素电路，所述第一像素电路在所述衬底基板上的正投影与所述第一显示区在所述衬底基板上的正投影不交叠，所述第二像素电路位于所述第二显示区；
    发光器件层，位于所述驱动电路层背离所述衬底基板的一侧，所述发光器件层包括多个第一发光器件和多个第二发光器件，所述第一发光器件位于所述第一显示区，所述第二发光器件位于所述第二显示区，各所述第一发光器件均包括独立设置的第一阳极，各所述第二发光器件均包括独立设置的第二阳极；多个所述第一阳极中的每个分别与所述多个第一像素电路中的每个对应电连接，多个所述第二阳极中的每个分别与所述多个第二像素电路中的每个对应电连接；其中，所述多个第一发光器件在所述第一显示区的密度与所述多个第二发光器件在所述第二显示区的密度相同；
    至少一层透明导电层，位于所述驱动电路层和所述发光器件层之间；所述至少一层透明导电层中的每一层包括与所述第一阳极电连接的多条第一阳极走线；所述第一阳极走线至少包括沿列方向延伸的第一部分和沿行方向延伸的第二部分，同一行所述第一阳极电连接的多条第一阳极走线的第二部分位于不同的相邻两行第一阳极之间，且所述第二部分沿所述行方向引出至所述第一显示区外侧。
  2. 如权利要求1所述的显示基板，其中，所述至少一层透明导电层包括层叠设置且相互绝缘的第一透明导电层和第二透明导电层；
    在每相邻两行所述第一阳极中，其中一行所述第一阳极对应的第一阳极 走线位于所述第一透明导电层，另一行所述第一阳极对应的第一阳极走线位于所述第二透明导电层。
  3. 如权利要求2所述的显示基板，其中，所述第一透明导电层和所述第二透明导电层的图形相同。
  4. 如权利要求1所述的显示基板，其中，每一所述透明导电层对应的相邻两行第一阳极之间的第一阳极走线的数量不大于第一数量，每一所述透明导电层对应的相邻两列第一阳极之间的第一阳极走线的数量不大于第二数量，所述第一数量大于所述第二数量。
  5. 如权利要求4所述的显示基板，其中，至少一行所述第一阳极分为相邻的第一区域、第二区域和第三区域，所述第一区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第二区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第三区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第一区域、所述第二区域和所述第三区域对应的第一阳极走线位于不同的相邻两行第一阳极之间。
  6. 如权利要求5所述的显示基板，其中，所述第一区域靠近所述第二显示区，所述第二区域位于所述第一区域远离所述第二显示区一侧，所述第三区域位于所述第二区域远离所述第二显示区一侧；
    所述第一区域对应的第一阳极走线的数量不大于所述第一数量的一半，所述第二区域和所述第三区域对应的第一阳极走线的数量均为所述第一数量。
  7. 如权利要求4所述的显示基板，其中，至少一行所述第一阳极分为相邻的第四区域、第五区域和第六区域，所述第四区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第五区域对应的第一阳极走线位于同一相邻两行第一阳极之间，所述第六区域对应的第一阳极走线位于不同的相邻两行第一阳极之间，且所述第四区域、所述第五区域和所述第六区域对应的第一阳极走线位于不同的相邻两行第一阳极之间。
  8. 如权利要求7所述的显示基板，其中，所述第四区域靠近所述第二显示区，所述第五区域位于所述第四区域远离所述第二显示区一侧，所述第六 区域位于所述第五区域远离所述第二显示区一侧；
    所述第四区域对应的第一阳极走线的数量为所述第一数量，所述第五区域对应的第一阳极走线的数量为所述第一数量，所述第六区域对应的第一阳极走线的数量不大于所述第一数量的一半。
  9. 如权利要求4所述的显示基板，其中，所述第一数量为11-15，所述第二数量为2-6。
  10. 如权利要求1所述的显示基板，其中，每一所述透明导电层所含的多条第一阳极走线互不交叠，不同所述透明导电层所含的多条第一阳极走线在所述衬底基板上的正投影相互交错。
  11. 如权利要求1所述的显示基板，其中，所述第一阳极和所述透明导电层之间具有绝缘层，所述绝缘层具有用于电连接所述第一阳极和所述第一阳极走线的多个过孔，所述第一阳极走线在所述衬底基板上的正投影与所述过孔在所述衬底基板上的正投影不交叠。
  12. 如权利要求1所述的显示基板，其中，所述多个第一像素电路位于与所述第一显示区邻近的所述边框区域。
  13. 如权利要求1所述的显示基板，其中，所述第二显示区具有邻近所述第一显示区的第七区域和第八区域，所述第七区域和所述第八区域相对设置，所述第七区域和所述第八区域中的第二像素电路所占的面积小于其它所述第二显示区的第二像素电路所占的面积，所述多个第一像素电路位于所述第七区域和所述第八区域。
  14. 如权利要求1所述的显示基板，其中，所述第一显示区的形状为圆形、椭圆形、矩形或多边形。
  15. 如权利要求14所述的显示基板，其中，所述第一显示区被沿所述行方向和所述列方向的中心线划分为四等份，每一等份的第一阳极走线均采用权利要求1-13任一项所述的显示基板中第一阳极走线的排布方式。
  16. 如权利要求15所述的显示基板，其中，所述四等份包括沿顺时针方向排列的第一等份、第二等份、第三等份和第四等份，所述第一等份和所述 第二等份关于所述列方向的中心线对称设置，所述第二等份和所述第三等份关于所述行方向的中心线对称设置，所述第三等份和所述第四等份关于所述列方向的中心线对称设置，所述第四等份和所述第一等份关于所述行方向的中心线对称设置。
  17. 如权利要求16所述的显示基板，其中，所述第一等份中最靠近所述第四等份的为第一行第一阳极，所述第四等份中最靠近所述第一等份的为第二行第一阳极，所述第一行第一阳极和所述第二行第一阳极之间为第一间隙，所述第一行第一阳极中靠近所述第二显示区的第一区域对应的第一阳极走线、以及所述第二行第一阳极中靠近所述第二显示区的第一区域对应的第一阳极走线均位于所述第一间隙内。
  18. 一种显示面板，其中，包括如权利要求1-17任一项所述的显示基板。
  19. 一种显示装置，其中，包括：感光器件，以及如权利要求18所述的显示面板；其中，所述感光器件被设置在所述显示基板的第一显示区。
PCT/CN2020/132413 2020-11-27 2020-11-27 显示基板、显示面板及显示装置 Ceased WO2022110055A1 (zh)

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US18/250,598 US20230403897A1 (en) 2020-11-27 2020-11-27 Display substrate, display panel, and display apparatus
KR1020237014728A KR20230109622A (ko) 2020-11-27 2020-11-27 표시 기판, 표시 패널 및 표시 장치
CN202080003036.9A CN114830349B (zh) 2020-11-27 2020-11-27 显示基板、显示面板及显示装置
EP20962945.0A EP4220726A4 (en) 2020-11-27 2020-11-27 DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS
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