WO2022143344A1 - 像素电路、图像传感器、摄像模组和电子设备 - Google Patents

像素电路、图像传感器、摄像模组和电子设备 Download PDF

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Publication number
WO2022143344A1
WO2022143344A1 PCT/CN2021/140515 CN2021140515W WO2022143344A1 WO 2022143344 A1 WO2022143344 A1 WO 2022143344A1 CN 2021140515 W CN2021140515 W CN 2021140515W WO 2022143344 A1 WO2022143344 A1 WO 2022143344A1
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Prior art keywords
transistor
charge
control signal
pixel circuit
pixel
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PCT/CN2021/140515
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English (en)
French (fr)
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罗轶
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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Priority to ES21914081T priority Critical patent/ES3010579T3/es
Priority to JP2023534043A priority patent/JP7697008B2/ja
Priority to EP21914081.1A priority patent/EP4270921B1/en
Priority to KR1020237023006A priority patent/KR102872218B1/ko
Publication of WO2022143344A1 publication Critical patent/WO2022143344A1/zh
Priority to US18/318,109 priority patent/US12256165B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H04N25/581—Control of the dynamic range involving two or more exposures acquired simultaneously
    • H04N25/585—Control of the dynamic range involving two or more exposures acquired simultaneously with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/55—Optical parts specially adapted for electronic image sensors; Mounting thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/53—Control of the integration time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/779—Circuitry for scanning or addressing the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present application relates to the technical field of image processing, and in particular, to a pixel circuit, an image sensor, a camera module and an electronic device.
  • CMOS complementary metal-oxide-semiconductor
  • the dynamic range is generally adjusted by changing the exposure time of all pixels and the gain of the pixel signal.
  • HDR High Dynamic Range
  • WDR Wide Dynamic Range
  • all pixels use the same exposure time.
  • the modulation effect of HDR is changed by the length of exposure time and the adjustment of output signal gain. Since the exposure time of each pixel in the related HDR technology is the same, the use of HDR results in local overexposure or underexposure of some pixels in some scenes.
  • the pixels in the overexposed area are individually encoded pixel by pixel to control the exposure time, which can realize pixel-level dynamic range modulation and avoid overexposure or exposure. underexposure problem.
  • a complex optical coding exposure control system needs to be used. This system is not only bulky, but also requires precise calibration between different devices. It is suitable for practical use on mobile devices such as mobile phones.
  • the pixel circuit When using On-Chip (on-chip) technology to practice the pixel-by-pixel HDR modulation method, the pixel circuit needs to have two or more exposure control signal storage units to control two or more charge memories, which is not conducive to the pixel's Miniaturization will reduce the performance of the pixel, such as the fill factor of the pixel (Fill Factor).
  • the fill factor of the pixel Fill Factor
  • using multiple exposure control signal storage units will have a certain probability to make the output exposure control signals all the same, for example, all output high-level signals, This results in the simultaneous flow of charge generated by the photoelectric conversion device to multiple charge storage regions and ultimately failure of the encoded exposure.
  • the embodiments of the present application provide a pixel circuit, an image sensor, a camera module and an electronic device, which can simplify the pixel structure and effectively reduce the volume of the pixel, thereby avoiding the problem of complex and bulky pixel circuit structure.
  • an embodiment of the present application provides a pixel circuit, including:
  • Photoelectric conversion devices for responding to incident light and generating charges according to the photoelectric effect
  • the charge storage device is connected to the photoelectric conversion device, and the charge storage device is used to store the charge generated after the photoelectric conversion device is exposed;
  • a first transfer transistor connected to the photoelectric conversion device and the charge storage, the first transfer transistor is used to transfer the charge to the charge storage;
  • the second transfer transistor is connected to the photoelectric conversion device, and the second transfer transistor is used for transferring the electric charge to the preset node to destroy the electric charge;
  • the exposure control signal memory is connected to the first transmission transistor and the second transmission transistor, and the control signal memory is used for generating a charge control signal according to the exposure control signal to control the conduction state of the first transmission transistor and the second transmission transistor.
  • an image sensor including:
  • a pixel circuit as provided in the first aspect is a pixel circuit as provided in the first aspect.
  • an embodiment of the present application provides a camera module, including:
  • the image sensor is electrically connected to the circuit board
  • the lens is arranged on the side of the image sensor away from the circuit board.
  • an electronic device including:
  • the pixel circuit includes a photoelectric conversion device, which is used to respond to incident light and generate charges according to the photoelectric effect; a charge memory, which is connected to the photoelectric conversion device, and is used to expose the charge generated by the photoelectric conversion device. storage; the first transfer transistor is connected to the photoelectric conversion device and the charge storage, the first transfer transistor is used to transfer the charge to the charge storage; the second transfer transistor is connected to the photoelectric conversion device, and the second transfer transistor is used to transfer the charge to the pre- A node is set to destroy the charge; an exposure control signal memory is connected to the first transfer transistor and the second transfer transistor, and the control signal memory is used to generate a charge control signal according to the exposure control signal to control the first transfer transistor and the second transfer transistor.
  • FIG. 1 shows one of the schematic diagrams of a pixel circuit according to an embodiment of the present application
  • FIG. 2 shows the second schematic diagram of a pixel circuit according to another embodiment of the present application
  • FIG. 3 shows a third schematic diagram of a pixel circuit according to still another embodiment of the present application.
  • FIG. 4 shows a fourth schematic diagram of a pixel circuit according to still another embodiment of the present application.
  • FIG. 5 shows a block diagram of a hardware structure of an electronic device according to an embodiment of the present application.
  • the receiving device, 110 reads the circuit.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • a pixel circuit 100 provided by an embodiment of the present application includes: a photoelectric conversion device 102 for responding to incident light and generating charges according to the photoelectric effect;
  • the memory 104, the charge memory 104 is connected to the photoelectric conversion device 102, and the charge memory 104 is used to store the charges generated after the photoelectric conversion device 102 is exposed;
  • the first transfer transistor 1062 is connected to the photoelectric conversion device 102 and the charge memory 104, the first The transfer transistor 1062 is used to transfer the charge to the charge storage 104;
  • the second transfer transistor 1064 is connected to the photoelectric conversion device 102, and the second transfer transistor 1064 is used to transfer the charge to a preset node to destroy the charge;
  • the first transfer transistor 1062 and the second transfer transistor 1064 are connected, and the control signal memory is used to generate a charge control signal according to the exposure control signal to control the conduction states of the first transfer transistor
  • the pixel circuit 100 includes an exposure control signal memory 108 (unit), a photoelectric conversion region based on the photoelectric conversion device 102 , the first transfer transistor 1062 and the second transfer transistor 1064 , and the charge memory 104 .
  • the charge in the charge memory 104 can be read out by the readout circuit 110 to output an image, and another part of the charge flows into the preset node through the second transfer transistor 1064 to destroy this part of the charge. Therefore, the effective exposure duration of each pixel can be changed by updating the exposure control signal, that is, only the charges generated and stored when the pixels are commanded to be exposed will be read, realizing the pixel-by-pixel HDR modulation function of the image sensor.
  • the pixel-by-pixel HDR modulation function of the image sensor can be realized without adopting a complex optical coding exposure control system, which avoids the problems of volume and power consumption when the Off-Chip technology implements the pixel-by-pixel HDR modulation method.
  • the structure of the pixel circuit 100 is simplified, and the volume of the pixel is effectively reduced, which is beneficial to the miniaturization of the pixel, improves the performance of the pixel, and avoids the The disorder of the charge flow caused by the same exposure control signals of the multiple exposure control signal memories 108 is avoided, and the stability and gain effect of the pixel-by-pixel HDR modulation are ensured.
  • the preset node may be a memory, and the internal charge is deleted by resetting the memory, and the preset node may also be a voltage source, which directly receives the charge.
  • FIG. 2 is a schematic diagram of a pixel circuit provided by another embodiment of the present application.
  • the preset node is a voltage source V DD3 .
  • the pixel circuit 100 is provided with a charge memory C1.
  • the first transfer transistor 1062 is turned off and the second transfer transistor 1064 is turned on, the charges generated by the photoelectric conversion device 102 flow directly to the voltage source V DD3 for destruction. Therefore, when two charge storages are provided, one of the charge storages stores the charge first and then destroys it, which further simplifies the pixel circuit.
  • the photoelectric conversion device 102 is a photodiode, and the transistor is capable of controlling the output current based on the input voltage, including a bipolar transistor (BJT) and a field effect transistor (FET), wherein the field effect transistor
  • BJT bipolar transistor
  • FET field effect transistor
  • the transistor may be a metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • the charge storage 104 may be a capacitive charge storage, or may be other types of charge storage, such as an operational transconductance amplifier.
  • the exposure control signal is obtained by analyzing the overexposure or underexposure of the pixels in the image within the exposure time, and each pixel can receive one or more binary exposure control signals.
  • the sequence of these exposure control signals can be the same signal, eg, all 1 (high level) or all 0 (low level), or different signals, eg, 100101100 . . .
  • the exposure control signal sequence received by each pixel within the exposure time of one pixel frame can be the same or different.
  • the effective exposure of each pixel in each pixel frame The time may be different or the same, and the effective exposure may be continuous or intermittent.
  • first transfer transistor 1062 and the second transfer transistor 1064 are turned on alternately, that is, the first transfer transistor 1062 and the second transfer transistor 1064 are not turned on at the same time, so as to prevent the charge from flowing to the plurality of charge memories 104 at the same time and finally make the Encoded exposure failed.
  • the first transfer transistor 1062 is turned on and the first transfer transistor 1062 is turned on and the The two pass transistors 1064 are switched on and off to power off.
  • the second pass transistor 1064 is turned on for two predetermined periods of time, and finally the first pass transistor 1062 is turned on and off for a predetermined period of time.
  • the first transfer transistor 1062 when the first transfer transistor 1062 is turned on, the charges generated when the photoelectric conversion device 102 is exposed are transferred to the charge memory 104 for storage, and when the second transfer transistor 1064 is turned on, the charges generated when the photoelectric conversion device 102 is exposed are transferred. to the preset node to destroy the charge. In this way, the effective exposure duration of each pixel is individually modulated.
  • the output image can be prevented from having abrupt edges in the area, which can not only make up for the problem of overexposure or underexposure, but also simplifies the pixel structure and can effectively The volume of downscaled pixels.
  • the exposure control signal memory 108 is a unit-bit static random access memory or a unit-bit dynamic random access memory.
  • the Static Random Access Memory is a storage device with a static access function, which can save the data stored in its internal storage without a refresh circuit, which can improve the reading and writing speed and reduce the power consumption. consumption, and the SRAM process can be widely used in the cache modules of various processor chips, reducing the manufacturing difficulty.
  • Dynamic Random Access Memory DRAM
  • DRAM Dynamic Random Access Memory
  • DRAM has the characteristics of large storage capacity and low cost, and the circuit structure is simpler than that of static random access memory, which can further reduce the size of pixels.
  • dynamic random access memory technology can be widely used. Applied to mainstream memory chips, it is easy to manufacture.
  • the unit-bit SRAM and the unit-bit DRAM both use 1 bit of information, so that even if the exposure control signal memory 108 receives a plurality of exposure control signals, it only stores 1-bit binary signals in sequence. It avoids generating different charge control signals at the same time, preventing the charge generated by the photoelectric conversion device 102 from flowing to different devices at the same time, and ultimately causing the encoding exposure to fail, so that only one exposure control signal memory 108 can realize pixel-by-pixel HDR modulation, which not only simplifies
  • the pixel architecture also guarantees the stability and gain of pixel-by-pixel HDR modulation.
  • FIG. 3 is a schematic diagram of a pixel circuit provided by another embodiment of the present application.
  • the unit-bit SRAM includes: a signal receiving device 1084 for receiving exposure control according to a control command of the control terminal of the unit-bit SRAM Signal; the signal processing device 1082 is connected to the signal receiving device 1084, and the signal processing device 1082 is used for generating a charge control signal according to the exposure control signal.
  • the signal receiving device 1084 includes: a first transistor M1 and a second transistor M2, the drains of the first transistor M1 and the second transistor M2 are connected to the output end of the exposure control signal, the first transistor M1 and the second transistor M2 The gate is connected to the control terminal of the unit-bit SRAM.
  • the signal processing device 1082 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6, the sources of the third transistor M3 and the fourth transistor M4 are connected to the first voltage source VDD1 of the pixel circuit 100,
  • the gate of the third transistor M3 is connected to the gate of the fifth transistor M5, the drain of the fourth transistor M4, the drain of the sixth transistor M6, the source of the first transistor M1 and the first transfer transistor 1062, respectively.
  • the gate of the transistor M4 is respectively connected to the gate of the sixth transistor M6, the drain of the third transistor M3, the drain of the fifth transistor M5, the source of the second transistor M2 and the second pass transistor 1064, and the fifth transistor M5 and the source of the sixth transistor M6 is grounded.
  • the control terminal of the unit-bit SRAM can output the receiving control command rs to control the conduction state of the first transistor M1 and the second transistor M2, and then control the signal receiving device 1084 to receive the exposure control signal res.
  • the first transistor M1 and the second transistor M2 are respectively configured to receive the opposite exposure control signal res, that is, the exposure control signal res received by the second transistor M2 is the inverse signal of the exposure control signal res received by the first transistor M1.
  • Each bit is stored in two cross-coupled inverters composed of the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6, that is, the output of the first inverter is connected to the second The input of one inverter, the output of the second inverter is connected to the input of the first inverter, and the output of the two inverters is completed, that is, the storage of one bit is completed.
  • the first voltage source VDD1 may be a variable voltage source.
  • FIG. 4 is a schematic diagram of a pixel circuit provided by another embodiment of the present application.
  • the unit-bit dynamic random access memory includes: a seventh transistor M7, the drain of the seventh transistor M7 is connected to the output end of the exposure control signal, The gate of the seventh transistor M7 is connected to the control terminal of the unit-bit DRAM, and the seventh transistor M7 is used for receiving the exposure control signal res according to the control command rs of the control terminal; the first capacitor C3 and the first terminals of the first capacitor C3 are respectively Connected to the source of the seventh transistor M7 and the first transfer transistor 1062, the second end of the first capacitor C3 is grounded; the inverter P, the first end of the inverter P is connected to the first end of the first capacitor C3, The second end of the inverter P is connected to the second pass transistor 1064, and the phase of the input signal is inverted by 180 degrees through the inverter P.
  • the exposure control signal res reaches the first capacitor C3 through the seventh transistor M7 and is directly used as the charge control signal Q of the first transfer transistor 1062 .
  • the charge control signal Q passes through an inverter P (not gate) to generate the charge control signal Q' of the second transfer transistor 1064.
  • the first capacitor of DRAM has an unavoidable leakage effect.
  • the DRAM exposure control signal memory needs to be refreshed with a timing signal.
  • the first capacitor C3 may be a parasitic capacitor of a node, a poly capacitor, an MIM (metal isolator metal) capacitor, a MOM (metal oxide metal) capacitor, or a MOS (metal oxide semiconductor) capacitor.
  • MIM metal isolator metal
  • MOM metal oxide metal
  • MOS metal oxide semiconductor
  • the pixel circuit 100 further includes: a reading circuit 110 connected to the charge storage 104 , and the reading circuit 110 is configured to read the charge in the charge storage 104 , and output the exposure image.
  • the readout circuit 110 can read the charges in the modulated charge memory 104 through the column data lines, and output the exposed image.
  • the charge storage further includes: a first charge storage 1042, which is connected to the first transfer transistor 1062, and the first charge storage 1042 is used for reading the circuit according to the The read command of 110 outputs electric charge; the second charge memory 1044 is connected to the second transfer transistor 1064 , and the second charge memory 1044 is used for resetting according to the read command of the read circuit 110 .
  • the number of charge stores is one or more, and the plurality of charge stores includes a first charge store 1042 and a second charge store 1044 .
  • the first charge storage 1042 is connected to the first transfer transistor 1062. When a pixel is instructed to be exposed, the charge can be stored in the first charge storage 1042 through the first transfer transistor 1062. After the exposure, the reading circuit 110 The charge in the first charge storage 1042 can be read and an exposure image can be generated.
  • the second charge storage 1044 is connected to the second transfer transistor 1064. When a pixel is commanded not to be exposed, the charge can be stored in the second charge storage 1044 through the second transfer transistor 1064, and the read circuit 110 can read the The charge in the second charge storage 1044 is then discarded.
  • the second charge storage 1044 is reset to delete the stored charge, and it is guaranteed that there is enough space to store the charge generated by the next exposure, or the charge in the second charge storage 1044 is not read, and the second charge is directly stored.
  • Memory 1044 is reset. Therefore, two kinds of pixel output signals are output through the first charge memory 1042 and the second charge memory 1044 , only one of them will be used for outputting an image, and the other will be ignored and reset eventually.
  • the processor can read the pixel output signals generated by the charges to be destroyed, so as to analyze the HDR modulation of the image.
  • the number of charge memories is N, and N is a multiple of 2
  • the number of exposure control signal memories 108 is N/2 to ensure that each exposure control signal memory 108 can control two charge memories.
  • the first charge storage 1042 or the second charge storage 1044 includes: a second capacitor (capacitor C1 , C2 ), which is connected to the photoelectric conversion device 102 ; storage transistors (transistors M8, M9), connected with the second capacitor and the read circuit 110, the storage transistor is used to transfer the charge in the second capacitor to the read circuit 110.
  • a second capacitor capacitor C1 , C2
  • storage transistors transistors M8, M9
  • the charges generated by the photoelectric conversion device 102 during exposure can flow into the corresponding second capacitors respectively through the first transfer transistor 1062 and the second transfer transistor 1064 in the closed power-on state.
  • the charge in the second capacitor is read out by the reading circuit 110 through the corresponding storage transistor.
  • the charge in the second capacitor C1 reaches the floating diffusion node FD1 through the closed and powered storage transistor M8 to be read out by the readout circuit 110 to output the exposure image.
  • the charge in the second capacitor C2 reaches the floating diffusion node FD2 by closing the energized storage transistor M9 to be read out by the read circuit 110 to be ignored and reset.
  • the pixel circuit 100 further includes: floating diffusion nodes ( FD1 , FD2 ) located at the storage transistors (transistors M8 , M9 ) and the reading circuit 110 between the reset transistors (RST1, RST2), connected between the second voltage source V DD2 and the floating diffusion point, the reset transistors (RST1, RST2) are used to reset the floating diffusion node voltage according to the reset control signal; source follower transistors (SF1, SF2), the gate of the source follower transistor is connected to the floating diffusion node, the drain of the source follower transistor SF is connected to the second voltage source V DD2 ; the row select transistors (RS1, RS2), the drain of the row select transistor The electrode is connected to the source of the source follower transistor, and the source and gate of the row select transistor are connected to the read circuit 110 .
  • the floating diffusion node is coupled to a second capacitor in charge storage 104 during a charge accumulation period to receive the stored value of the second capacitor
  • the charge is also coupled to the second voltage source V DD2 during the reset period to reset the floating diffusion node voltage.
  • the voltage signal of the floating diffusion node is amplified and output to the column data line by the source follower transistor and the row select transistor.
  • the row select transistors RS1 and RS2 are turned on, the reset transistors RST1 and RST2 are turned on, and the floating diffusion points FD1 and FD2 are reset to the second voltage source V DD2 voltage, the charges stored in the second capacitors C1 and C2 are transferred to the floating diffusion points FD1 and FD2 respectively, and the charges are read through SF1, RS1 and SF2, RS2.
  • an image sensor which includes the pixel circuit provided in any of the foregoing embodiments. Therefore, the image sensor also includes all the beneficial effects of the pixel circuit in any of the above-mentioned embodiments, which will not be repeated here.
  • the image sensor is a complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS) with a high dynamic range (HDR) mode.
  • CMOS Image Sensor CIS
  • HDR high dynamic range
  • the CMOS image sensor has the advantages of simple process, easy integration with other devices, small size, light weight, and power consumption. Due to its advantages of small size and low cost, it can be widely used in different electronic devices, such as digital cameras, camera phones, digital video cameras, medical imaging devices (gastroscopes), and automotive imaging devices.
  • a camera module including: a circuit board; the image sensor provided in the above embodiment, the image sensor is electrically connected to the circuit board; a lens, the image sensor is disposed on the image sensor away from the circuit board side. Therefore, the camera module also includes all the beneficial effects of the image sensor in any of the above embodiments, which will not be repeated here.
  • an electronic device including: the camera module provided by the above embodiment. Therefore, the electronic device also includes all the beneficial effects of the camera module in the above-mentioned embodiments, which will not be repeated here.
  • the electronic device in this embodiment of the present application may be an apparatus, or may be a component, an integrated circuit, or a chip in a terminal.
  • the apparatus may be a mobile electronic device or a non-mobile electronic device.
  • the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (personal digital assistant).
  • UMPC ultra-mobile personal computer
  • PDA personal digital assistant
  • non-mobile electronic devices can be servers, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (television, TV), teller machine or self-service machine, etc., this application Examples are not specifically limited.
  • the electronic device in this embodiment of the present application may be an apparatus having an operating system.
  • the operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.
  • FIG. 5 is a block diagram of a hardware structure of an electronic device provided by an embodiment of the present application.
  • the electronic device 500 includes but is not limited to: a radio frequency unit 502 , a network module 504 , an audio output unit 506 , an input unit 508 , a sensor 510 , a display unit 512 , a user input unit 514 , an interface unit 516 , and a memory 518 , the processor 520 and other components.
  • the electronic device 500 may also include a power source (such as a battery) for supplying power to various components, and the power source may be logically connected to the processor 520 through a power management system, so that the power management system can manage charging, discharging, and power management. consumption management and other functions.
  • a power source such as a battery
  • the structure of the electronic device shown in FIG. 5 does not constitute a limitation on the electronic device, and the electronic device may include more or less components than those shown, or combine some components, or arrange different components.
  • electronic devices include, but are not limited to, mobile terminals, tablet computers, notebook computers, handheld computers, vehicle-mounted electronic devices, wearable devices, and pedometers.
  • the radio frequency unit 502 may be used to send and receive information or send and receive signals during a call, and specifically, receive downlink data from the base station or send uplink data to the base station.
  • the radio frequency unit 502 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like.
  • the network module 504 provides the user with wireless broadband Internet access, such as helping the user to send and receive emails, browse the web, access streaming media, and the like.
  • the audio output unit 506 may convert audio data received by the radio frequency unit 502 or the network module 504 or stored in the memory 518 into audio signals and output as sound. Moreover, the audio output unit 506 may also provide audio output related to a particular function performed by the electronic device 500 (e.g., call signal reception sound, message reception sound, etc.).
  • the audio output unit 506 includes a speaker, a buzzer, a receiver, and the like.
  • the input unit 508 is used to receive audio or video signals.
  • the input unit 508 may include a graphics processor (Graphics Processing Unit, GPU) 5082 and a microphone 5084, and the graphics processor 5082 is used for still pictures or video images obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode.
  • data is processed.
  • the processed image frames may be displayed on the display unit 512, or stored in the memory 518 (or other storage medium), or transmitted via the radio frequency unit 502 or the network module 504.
  • the microphone 5084 can receive sound, and can process the sound into audio data, and the processed audio data can be converted into a format output that can be transmitted to a mobile communication base station via the radio frequency unit 502 in the case of a telephone call mode.
  • the electronic device 500 also includes at least one sensor 510, such as a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, a light sensor, a motion sensor, and other sensors.
  • a sensor 510 such as a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, a light sensor, a motion sensor, and other sensors.
  • the display unit 512 is used to display information input by the user or information provided to the user.
  • the display unit 512 may include a display panel 5122, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the user input unit 514 may be used to receive input numerical or character information, and generate key signal input related to user settings and function control of the electronic device.
  • the user input unit 514 includes a touch panel 5142 and other input devices 5144 .
  • the touch panel 5142 also referred to as a touch screen, collects the user's touch operations on or near it.
  • the touch panel 5142 may include two parts, a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and then sends it to the touch controller.
  • Other input devices 5144 may include, but are not limited to, physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which are not described herein again.
  • the touch panel 5142 may be covered on the display panel 5122.
  • the touch panel 5142 detects a touch operation on or near it, the touch panel 5142 transmits it to the processor 520 to determine the type of the touch event, and then the processor 520 determines the type of the touch event according to the touch
  • the type of event provides corresponding visual output on display panel 5122.
  • the touch panel 5142 and the display panel 5122 can be used as two independent components, or can be integrated into one component.
  • the interface unit 516 is an interface for connecting an external device to the electronic device 500 .
  • external devices may include wired or wireless headset ports, external power (or battery charger) ports, wired or wireless data ports, memory card ports, ports for connecting devices with identification modules, audio input/output (I/O) ports, video I/O ports, headphone ports, and more.
  • the interface unit 516 may be used to receive input (eg, data information, power, etc.) from external devices and transmit the received input to one or more elements within the electronic device 500 or may be used between the electronic device 500 and external Transfer data between devices.
  • Memory 518 may be used to store application programs as well as various data.
  • the memory 518 may mainly include a stored program area and a stored data area, wherein the stored program area may store an operating system, an application program required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; Data (such as audio data, phone book, etc.) created by the use of the mobile terminal, etc.
  • memory 518 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
  • the processor 520 executes various functions of the electronic device 500 and processes data by running or executing the application programs and/or modules stored in the memory 518 and calling the data stored in the memory 518, so as to perform the overall operation of the electronic device 500. monitor.
  • the processor 520 may include one or more processing units; the processor 520 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes Operations that handle image processing.

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Abstract

本申请实施例提供了一种像素电路、图像传感器、摄像模组和电子设备，属于图像处理技术领域。其中，像素电路包括：光电转换器件、电荷存储器、第一传输晶体管、第二传输晶体管、曝光控制信号存储器。

Description

像素电路、图像传感器、摄像模组和电子设备 技术领域
本申请主张2020年12月28日在中国提交的中国专利申请号202011587897.4的优先权，其全部内容通过引用包含于此。
技术领域
本申请涉及图像处理技术领域，具体而言，涉及一种像素电路、图像传感器、摄像模组和电子设备。
背景技术
在互补金属氧化半导体图像传感器(Complemerntary metal-oxide semiconductor，CMOS)中，动态范围一般通过改变所有像素曝光时间和像素信号进行增益调整。在高动态范围(High Dynamic Range，HDR)或广动态范围(Wide Dynamic Range，WDR)技术中，无论是多帧、行交织、还是双增益方案，都是所有像素采用相同的曝光时间。通过曝光时间的长短以及输出信号增益调整来改变HDR的调制效果。由于相关HDR技术中每个像素的曝光时间相同，导致HDR的使用在某些场景部分像素局域过曝或者部分像素欠曝。
相关技术中，通过逐像素(Pixel-Wise或Per-Pixel)曝光时间控制技术对过曝区域的像素进行逐像素单独的编码进行曝光时间控制，可以实现像素级的动态范围调制，避免过曝或欠曝问题。但在使用Off-Chip(非芯片)技术实践逐像素HDR调制方法时，需要采用复杂的光学编码曝光控制系统，此系统不仅体积庞大，而且需要不同器件间的精密校准，功耗较高，不适合在手机等移动端设备上实践使用。在使用On-Chip(芯片上)技术实践逐像素HDR调制方法时，像素电路需要有两个或两个以上的曝光控制 信号存储单元来控制两个或两个以上的电荷存储器，不利于像素的小型化且会降低像素的性能，例如像素的填充因子(Fill Factor)，同时，使用多个曝光控制信号存储单元会有一定概率让输出的曝光控制信号全部相同，例如全部输出高电平信号，导致光电转换器件产生的电荷同时流向多个电荷存储区域并最终使编码曝光失败。
发明内容
本申请实施例提供了一种像素电路、图像传感器、摄像模组和电子设备，能够简化像素架构并可以有效的缩小像素的体积，避免了像素电路结构复杂庞大的问题。
第一方面，本申请实施例提供了一种像素电路，包括：
光电转换器件，用于响应入射光并根据光电效应产生电荷；
电荷存储器，电荷存储器与光电转换器件连接，电荷存储器用于将光电转换器件曝光后产生的电荷进行存储；
第一传输晶体管，与光电转换器件和电荷存储器连接，第一传输晶体管用于转移电荷至电荷存储器；
第二传输晶体管，与光电转换器件连接，第二传输晶体管用于转移电荷至预设节点，以销毁电荷；
曝光控制信号存储器，与第一传输晶体管和第二传输晶体管连接，控制信号存储器用于根据曝光控制信号生成电荷控制信号，以控制第一传输晶体管和第二传输晶体管的导通状态。
第二方面，本申请实施例提供了一种图像传感器，包括：
如第一方面提供的像素电路。
第三方面，本申请实施例提供了一种摄像模组，包括：
电路板；
如第二方面提供的图像传感器，与电路板电连接；
镜头，设置于图像传感器的背离电路板的一侧。
第四方面，本申请实施例提供了一种电子设备，包括：
如第三方面提供的摄像模组。
在本申请实施例中，像素电路包括光电转换器件，用于响应入射光并根据光电效应产生电荷；电荷存储器，电荷存储器与光电转换器件连接，电荷存储器用于将光电转换器件曝光后产生的电荷进行存储；第一传输晶体管，与光电转换器件和电荷存储器连接，第一传输晶体管用于转移电荷至电荷存储器；第二传输晶体管，与光电转换器件连接，第二传输晶体管用于转移电荷至预设节点，以销毁电荷；曝光控制信号存储器，与第一传输晶体管和第二传输晶体管连接，控制信号存储器用于根据曝光控制信号生成电荷控制信号，以控制第一传输晶体管和第二传输晶体管的导通状态。从而在曝光过程中，只需要一个二进制信号(1或者0)的曝光控制信号存储器，通过在一帧的曝光时间内不断的改变和更新每一个像素的曝光控制信号，来控制第一传输晶体管和第二传输晶体管，当一个像素被命令需要曝光时，则产生的电荷流向电荷存储器；当一个像素被命令不需要曝光时，产生的电荷流向预设节点并被销毁，从而能够将每个像素的有效曝光时间被预先编写好的曝光控制信号所编排，实现图像传感器的逐像素HDR调制功能。一方面，无需采用复杂的光学编码曝光控制系统，避免了Off-Chip技术实践逐像素HDR调制方法时体积和功耗问题。另一方面，On-Chip技术实践逐像素HDR调制方法时，通过减少用于接收、分析曝光控制信号的曝光控制信号存储器的数量，在简化像素电路结构的同时，有效的缩小像素的体积，有利于像素的小型化，提高像素的性能，并且避免了因多个曝光控制信号存储器的曝光控制信号相同所导致的电荷流向混乱，保证逐像素HDR调制的稳定性和增益效果。
附图说明
图1示出了根据本申请的一个实施例的像素电路的示意图之一；
图2示出了根据本申请的另一实施例的像素电路的示意图之二；
图3示出了根据本申请的再一实施例的像素电路的示意图之三；
图4示出了根据本申请的再一实施例的像素电路的示意图之四；
图5示出了根据本申请的一个实施例的电子设备的硬件结构框图。
附图标记：
100像素电路，102光电转换器件，104电荷存储器，1042第一电荷存储器，1044第二电荷存储器，1062第一传输晶体管，1064第二传输晶体管，108曝光控制信号存储器，1082信号处理器件，1084信号接收器件，110读取电路。
具体实施方式
下面将详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“左”、“右”、等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术 语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
下面参照图1至图5描述本申请实施例提供的像素电路、图像传感器、摄像模组和电子设备。
图1是本申请实施例提供的像素电路的示意图，如图1所示，本申请实施例提供的像素电路100，包括：光电转换器件102，用于响应入射光并根据光电效应产生电荷；电荷存储器104，电荷存储器104与光电转换器件102连接，电荷存储器104用于将光电转换器件102曝光后产生的电荷进行存储；第一传输晶体管1062，与光电转换器件102和电荷存储器104连接，第一传输晶体管1062用于转移电荷至电荷存储器104；第二传输晶体管1064，与光电转换器件102连接，第二传输晶体管1064用于转移电荷至预设节点，以销毁电荷；曝光控制信号存储器108，与第一传输晶体管1062和第二传输晶体管1064连接，控制信号存储器用于根据曝光控制信号生成电荷控制信号，以控制第一传输晶体管1062和第二传输晶体管1064的导通状态。
具体地，像素电路100架构内包含一个曝光控制信号存储器108(单元)，一个基于光电转换器件102、第一传输晶体管1062和第二传输晶体管1064的光电转换区域，以及电荷存储器104。在曝光过程中，二进制的曝光控制信号(1或0)进入曝光控制信号存储器108并产生电荷控制信号Q和Q’，其中，Q’与Q相反，也即Q’＝Q×(-1)，以分别控制第一传输晶体管1062和第二传输晶体管1064的导通状态，使得光电转换区域在曝光时产生的电荷能够按照曝光控制信号，部分经过第一传输晶体管1062流入相应的电荷存储器104，实现像素的有效曝光。曝光结束后，电荷存储器104内的电荷能够被读取电路110读出以输出图像，另一部分经过第二传输晶 体管1064流入预设节点，以销毁这部分电荷。从而能够通过更新曝光控制信号改变每一个像素的有效曝光时长，也即，只有那些像素被命令需要曝光时产生并存储的电荷会被读取，实现图像传感器的逐像素HDR调制功能。
在该实施例中，无需采用复杂的光学编码曝光控制系统，即可实现图像传感器的逐像素HDR调制功能，避免了Off-Chip技术实践逐像素HDR调制方法时体积和功耗问题。而且通过减少用于接收、分析曝光控制信号的曝光控制信号存储器108的数量，在简化像素电路100结构的同时，有效的缩小像素的体积，有利于像素的小型化，提高像素的性能，并且避免了由于多个曝光控制信号存储器108的曝光控制信号相同导致的电荷流向混乱，保证逐像素HDR调制的稳定性和增益效果。
其中，预设节点可以是存储器，通过重置存储器删除内部电荷，预设节点也可以是电压源，直接接收电荷。
具体举例来说，图2是本申请另一实施例提供的像素电路的示意图，如图2所示，预设节点为电压源V DD3。像素电路100设置一个电荷存储器C1。当第一传输晶体管1062断开而第二传输晶体管1064闭合时，光电转换器件102产生的电荷直接流向电压源V DD3进行销毁。从而避免设置两个电荷存储器时，其中一个电荷存储器先存储电荷再进行销毁，进一步简化了像素电路。在具体应用中，光电转换器件102为光电二极管，晶体管为能够基于输入电压控制输出电流，包括双极性晶体管(bipolar transistor，BJT)、场效应晶体管(field effect transistor，FET)，其中，场效应晶体管可以为金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor，MOSFET)。电荷存储器104可以为电容式电荷存储器，也可以是其他类型的电荷存储器，例如，运算跨导放大器。
需要说明的是，在一像素帧的曝光时间中，曝光控制信号根据曝光时间内图像中像素的过曝或欠曝情况分析得到，每个像素可以接收到1个或多个二进制的曝光控制信号。这些曝光控制信号的序列可以是相同信号， 例如全部是1(高平电)或者全部是0(低平电)，也可以是不同信号，例如100101100...。
另外，在一个图像传感器上，每个像素在一像素帧的曝光时间内接收到的曝光控制信号序列可以是相同的也可以是不同的，同样的，每个像素在每一像素帧的有效曝光时间可能不同也可能相同，有效曝光可以是持续的也可能是间断的。
进一步地，第一传输晶体管1062和第二传输晶体管1064交替导通，也即第一传输晶体管1062和第二传输晶体管1064不会同时导通，以防止电荷同时流向多个电荷存储器104并最终使编码曝光失败。
具体举例来说，一个像素的曝光控制信号的序列为全部是1，输出电荷控制信号为Q＝1，Q’＝0，则一像素帧的曝光时间内，第一传输晶体管1062闭合通电且第二传输晶体管1064开合断电。一个像素的曝光控制信号的序列为1001，输出第一个电荷控制信号为Q＝1，Q’＝0，第二、三个电荷控制信号为Q＝0，Q’＝1，第四个电荷控制信号为Q＝1，Q’＝0，则先闭合导通第一传输晶体管1062并开合断开第二传输晶体管1064预设时长，然后再开合断开第一传输晶体管1062并闭合导通第二传输晶体管1064两段预设时长，最后恢复闭合导通第一传输晶体管1062并开合断开第二传输晶体管1064预设时长。其中，在第一传输晶体管1062导通时，光电转换器件102曝光时产生的电荷被输送至电荷存储器104保存，在第二传输晶体管1064导通时，光电转换器件102曝光时产生的电荷被输送至预设节点，以将电荷销毁。从而对每个像素的有效曝光时长进行单独调制，在实现像素级别的HDR调制时，避免输出的图像存在区域边缘突兀感，不仅能够弥补过曝或欠曝问题，还简化了像素架构并可以有效的缩小像素的体积。
在本申请的一个实施例中，进一步地，曝光控制信号存储器108为单位比特静态随机存储器或单位比特动态随机存储器。
在该实施例中，静态随机存储器(Static Random Access Memory，SRAM)是一种具有静止存取功能的存储器件，不需要刷新电路即可保存 其内部存储的数据，能够提高读写速度且降低功耗，且静态随机存储器工艺可广泛应用于各类处理器芯片的缓存模块，降低制造难度。动态随机存储器(Dynamic Random Access Memory，DRAM)具有存储容量大、成本低的特点，且相比于静态随机存储器的电路结构更加简单，能够进一步降低像素大小尺寸，同样的，动态随机存储器工艺能够广泛应用于主流内存芯片，便于生产制造。
另外，单位比特SRAM和单位比特DRAM均采用1比特(bit)的信息量，使得曝光控制信号存储器108即使接收到多个曝光控制信号，也只按顺序存储1比特的二进制信号。避免在同一时间生成不同的电荷控制信号，避免光电转换器件102产生的电荷同时流向不同器件，并最终使编码曝光失败，从而只需一个曝光控制信号存储器108即可实现逐像素HDR调制，不仅简化了像素架构，还保证逐像素HDR调制的稳定性和增益效果。
图3是本申请再一实施例提供的像素电路的示意图，如图3所示，单位比特静态随机存储器包括：信号接收器件1084，用于根据单位比特静态随机存储器的控制端的控制指令接收曝光控制信号；信号处理器件1082，与信号接收器件1084连接，信号处理器件1082用于根据曝光控制信号生成电荷控制信号。
具体地，信号接收器件1084包括：第一晶体管M1和第二晶体管M2，第一晶体管M1和第二晶体管M2的漏极与曝光控制信号的输出端连接，第一晶体管M1和第二晶体管M2的栅极与单位比特静态随机存储器的控制端连接。
信号处理器件1082包括：第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6，第三晶体管M3和第四晶体管M4的源极与像素电路100的第一电压源VDD1连接，第三晶体管M3的栅极分别与第五晶体管M5的栅极、第四晶体管M4的漏极、第六晶体管M6的漏极、第一晶体管M1的源极和第一传输晶体管1062连接，第四晶体管M4的栅极分别与第六晶体管M6的栅极、第三晶体管M3的漏极、第五晶体管M5的漏 极、第二晶体管M2的源极和第二传输晶体管1064连接，第五晶体管M5和第六晶体管M6的源极接地。
在该实施例中，单位比特静态随机存储器的控制端能够输出接收控制指令rs，以控制第一晶体管M1和第二晶体管M2的导通状态，进而控制信号接收器件1084接收曝光控制信号res。其中，第一晶体管M1和第二晶体管M2分别用于接收相反的曝光控制信号res，也即第二晶体管M2接收的曝光控制信号res为第一晶体管M1接收的曝光控制信号res的反相信号。每一个比特储存在由第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6构成的两个交叉耦合的反向器中，也即第一个反向器的输出连接第二个反向器的键入，第二个反向器的输出连接第一个反向器的键入，完成两个反向器的输出，即完成了一个比特的储存。
在具体应用中，第一电压源VDD1可以为可变电压源。
图4是本申请再一实施例提供的像素电路的示意图，如图4所示，单位比特动态随机存储器包括：第七晶体管M7，第七晶体管M7的漏极与曝光控制信号的输出端连接，第七晶体管M7的栅极与单位比特动态随机存储器的控制端连接，第七晶体管M7用于根据控制端的控制指令rs接收曝光控制信号res；第一电容C3，第一电容C3的第一端分别与第七晶体管M7的源极和第一传输晶体管1062连接，第一电容C3的第二端接地；反向器P，反向器P的第一端与第一电容C3的第一端连接，反向器P的第二端与第二传输晶体管1064连接，通过反向器P将输入信号的相位翻转180度。
在该实施例中，在一像素帧的曝光时间内，曝光控制信号res通过第七晶体管M7到达第一电容C3，并直接作为第一传输晶体管1062的电荷控制信号Q。同时电荷控制信号Q经过一个反向器P(非门)生成第二传输晶体管1064的电荷控制信号Q’。
需要说明的是，由于半导体特性，DRAM的第一电容具有无法避免的漏电效应，为了保持曝光控制信号能持续有效地在DRAM曝光控制信号存 储器内存储，DRAM曝光控制信号存储器需要进行定时信号刷新。
在具体应用中，第一电容C3可为节点的寄生电容、Poly电容、MIM(metal isolator metal)电容、MOM(metal oxide metal)电容或MOS(metal oxide semiconductor)电容。
如图1所示，在本申请的一个实施例中，进一步地，像素电路100还包括：读取电路110，与电荷存储器104连接，读取电路110用于读取电荷存储器104中的电荷，并输出曝光图像。
在该实施例中，在曝光结束后，读取电路110可通过列数据线读取调制后电荷存储器104中的电荷，并输出曝光后的图像。
如图3和图4所示，在本申请的一个实施例中，进一步地，电荷存储器包括：第一电荷存储器1042，与第一传输晶体管1062连接，第一电荷存储器1042用于根据读取电路110的读取指令输出电荷；第二电荷存储器1044，与第二传输晶体管1064连接，第二电荷存储器1044用于根据读取电路110的读取指令进行重置。
在该实施例中，电荷存储器的数量为一个或多个，多个电荷存储器包括第一电荷存储器1042和第二电荷存储器1044。其中，第一电荷存储器1042与第一传输晶体管1062连接，当一个像素被命令需要曝光时，电荷可通过第一传输晶体管1062被储存于第一电荷存储器1042中，曝光结束后，读取电路110可读取第一电荷存储器1042中的电荷并生成曝光图像。第二电荷存储器1044与第二传输晶体管1064连接，当一个像素被命令不需要曝光时，电荷可通过第二传输晶体管1064被储存于第二电荷存储器1044中，读取电路110可在读取到第二电荷存储器1044中的电荷后丢弃。同时，第二电荷存储器1044进行重置，删除已经存储的电荷，已保证拥有足够的空间来存储下一次曝光产生的电荷，或不读取第二电荷存储器1044中的电荷，直接对第二电荷存储器1044进行重置。从而通过第一电荷存储器1042和第二电荷存储器1044输出两种像素输出信号，只有其中一个会被利用于输出图像，而另一个则会最终忽略并重置。而且由于想销毁的电 荷先被保存在第二电荷存储器1044中，使得处理器能够读取到想销毁的电荷产生的像素输出信号，以便于对图像HDR调制进行分析。
需要说明的是，电荷存储器的数量为N个，N为2的倍数，则曝光控制信号存储器108的个数为N/2个，以保证每一个曝光控制信号存储器108能够控制2个电荷存储器。
如图3和图4所示，在本申请的一个实施例中，进一步地，第一电荷存储器1042或第二电荷存储器1044包括：第二电容(电容C1、C2)，与光电转换器件102连接；存储晶体管(晶体管M8、M9)，与第二电容和读取电路110连接，存储晶体管用于转移第二电容中的电荷至读取电路110。
在该实施例中，光电转换器件102在曝光时产生的电荷，可以经过处于闭合通电状态的第一传输晶体管1062和第二传输晶体管1064分别流入对应的第二电容。曝光结束后，在像素的信号读取阶段，第二电容内的电荷通过对应的存储晶体管被读取电路110读出。
具体举例来说，曝光结束后，第二电容C1内的电荷通过闭合通电的存储晶体管M8到达浮动扩散节点FD1被读取电路110读出，以输出曝光图像。第二电容C2内的电荷通过闭合通电的存储晶体管M9到达浮动扩散节点FD2被读取电路110读出，以忽略并重置。
如图2至图4所示，在本申请的一个实施例中，进一步地，像素电路100还包括：浮动扩散节点(FD1、FD2)，位于存储晶体管(晶体管M8、M9)和读取电路110之间；复位晶体管(RST1、RST2)，接入第二电压源V DD2和浮动扩散点之间，复位晶体管(RST1、RST2)用于根据复位控制信号重置浮动扩散节点电压；源跟随器晶体管(SF1、SF2)，源跟随器晶体管的栅极与浮动扩散节点连接，源跟随器晶体管SF的漏极与第二电压源V DD2连接；行选择晶体管(RS1、RS2)，行选择晶体管的漏极与源跟随器晶体管的源极连接，行选择晶体管的源极和栅极与读取电路110连接。
在该实施例中，通过复位晶体管和电荷存储器104中的存储晶体管的 导通状态，来决定浮动扩散节点是在电荷累计周期期间耦合至电荷存储器104中第二电容，以接收第二电容所存储的电荷，还是在复位周期期间耦合至第二电压源V DD2，以重置浮动扩散节点电压。通过源跟随器晶体管和行选择晶体管对浮动扩散节点的电压信号放大输出至列数据线。
具体举例来说，如图3和图4所示，在读取阶段，行选择晶体管RS1和RS2闭合通电，复位晶体管RST1和RST2导通，浮动扩散点FD1和FD2复位至第二电压源V DD2的电压，保存在第二电容C1和C2中的电荷分别转移至浮动扩散点FD1和FD2，并通过SF1、RS1以及SF2、RS2读取该电荷。
在本申请的一个实施例中，提供了一种图像传感器，包括上述任一实施例提供的像素电路。因此，该图像传感器同时也包括如上述任一实施例中的像素电路的全部有益效果，在此不再赘述。
进一步地，图像传感器为具有高动态范围(HDR)模式的互补金属氧化半导体图像传感器(CMOS Image Sensor，CIS)，CMOS图像传感器具有工艺简单、易与其他器件集成、体积小、重量轻、功耗小、成本低等优点，可广泛应用于不同电子设备，例如，数码相机、照相手机、数码摄像机、医疗用摄像装置(胃镜)、车用摄像装置等。
在本申请的一个实施例中，提供了一种摄像模组，包括：电路板；上述实施例提供的图像传感器，图像传感器与电路板电连接；镜头，图像传感器设置于图像传感器背离电路板的一侧。因此，该摄像模组同时也包括如上述任一实施例中的图像传感器的全部有益效果，在此不再赘述。
在本申请的一个实施例中，提供了一种电子设备，包括：上述实施例提供的摄像模组。因此，该电子设备同时也包括如上述实施例中的摄像模组的全部有益效果，在此不再赘述。
本申请实施例中的电子设备可以是装置，也可以是终端中的部件、集成电路、或芯片。该装置可以是移动电子设备，也可以为非移动电子设备。示例性的，移动电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、 车载电子设备、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，非移动电子设备可以为服务器、网络附属存储器(Network Attached Storage，NAS)、个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
本申请实施例中的电子设备可以为具有操作系统的装置。该操作系统可以为安卓(Android)操作系统，可以为ios操作系统，还可以为其他可能的操作系统，本申请实施例不作具体限定。
图5为本申请实施例提供的电子设备的硬件结构框图。如图5所示，该电子设备500包括但不限于：射频单元502、网络模块504、音频输出单元506、输入单元508、传感器510、显示单元512、用户输入单元514、接口单元516、存储器518、处理器520等部件。
本领域技术人员可以理解，电子设备500还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器520逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图5中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本申请实施例中，电子设备包括但不限于移动终端、平板电脑、笔记本电脑、掌上电脑、车载电子设备、可穿戴设备、以及计步器等。
应理解的是，本申请实施例中，射频单元502可用于收发信息或收发通话过程中的信号，具体的，接收基站的下行数据或向基站发送上行数据。射频单元502包括但不限于天线、至少一个放大器、收发信机、耦合器、低噪声放大器、双工器等。
网络模块504为用户提供了无线的宽带互联网访问，如帮助用户收发电子邮件、浏览网页和访问流式媒体等。
音频输出单元506可以将射频单元502或网络模块504接收的或者在存储器518中存储的音频数据转换成音频信号并且输出为声音。而且，音 频输出单元506还可以提供与电子设备500执行的特定功能相关的音频输出(例如，呼叫信号接收声音、消息接收声音等等)。音频输出单元506包括扬声器、蜂鸣器以及受话器等。
输入单元508用于接收音频或视频信号。输入单元508可以包括图形处理器(Graphics Processing Unit，GPU)5082和麦克风5084，图形处理器5082对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。处理后的图像帧可以显示在显示单元512上，或者存储在存储器518(或其它存储介质)中，或者经由射频单元502或网络模块504发送。麦克风5084可以接收声音，并且能够将声音处理为音频数据，处理后的音频数据可以在电话通话模式的情况下转换为可经由射频单元502发送到移动通信基站的格式输出。
电子设备500还包括至少一种传感器510，比如指纹传感器、压力传感器、虹膜传感器、分子传感器、陀螺仪、气压计、湿度计、温度计、红外线传感器、光传感器、运动传感器以及其他传感器。
显示单元512用于显示由用户输入的信息或提供给用户的信息。显示单元512可包括显示面板5122，可以采用液晶显示器、有机发光二极管等形式来配置显示面板5122。
用户输入单元514可用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。具体地，用户输入单元514包括触控面板5142以及其他输入设备5144。触控面板5142也称为触摸屏，可收集用户在其上或附近的触摸操作。触控面板5142可包括触摸检测装置和触摸控制器两个部分。其中，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给处理器520，接收处理器520发来的命令并加以执行。其他输入设备5144可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
进一步的，触控面板5142可覆盖在显示面板5122上，当触控面板5142检测到在其上或附近的触摸操作后，传送给处理器520以确定触摸事件的类型，随后处理器520根据触摸事件的类型在显示面板5122上提供相应的视觉输出。触控面板5142与显示面板5122可作为两个独立的部件，也可以集成为一个部件。
接口单元516为外部装置与电子设备500连接的接口。例如，外部装置可以包括有线或无线头戴式耳机端口、外部电源(或电池充电器)端口、有线或无线数据端口、存储卡端口、用于连接具有识别模块的装置的端口、音频输入/输出(I/O)端口、视频I/O端口、耳机端口等等。接口单元516可以用于接收来自外部装置的输入(例如，数据信息、电力等等)并且将接收到的输入传输到电子设备500内的一个或多个元件或者可以用于在电子设备500和外部装置之间传输数据。
存储器518可用于存储应用程序程序以及各种数据。存储器518可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据移动终端的使用所创建的数据(比如音频数据、电话本等)等。此外，存储器518可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
处理器520通过运行或执行存储在存储器518内的应用程序程序和/或模块，以及调用存储在存储器518内的数据，执行电子设备500的各种功能和处理数据，从而对电子设备500进行整体监控。处理器520可包括一个或多个处理单元；处理器520可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理图像处理的操作。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示意性实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施 例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。
以上仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (12)

  1. 一种像素电路，包括：
    光电转换器件，用于响应入射光并根据光电效应产生电荷；
    电荷存储器，所述电荷存储器与所述光电转换器件连接，所述电荷存储器用于将所述光电转换器件产生的所述电荷进行存储；
    第一传输晶体管，与所述光电转换器件和电荷存储器连接，所述第一传输晶体管用于转移所述电荷至所述电荷存储器；
    第二传输晶体管，与所述光电转换器件连接，所述第二传输晶体管用于转移所述电荷至预设节点，以销毁所述电荷；
    曝光控制信号存储器，与所述第一传输晶体管和所述第二传输晶体管连接，所述控制信号存储器用于根据曝光控制信号生成电荷控制信号，以控制所述第一传输晶体管和所述第二传输晶体管的导通状态。
  2. 根据权利要求1所述的像素电路，其中，所述曝光控制信号存储器为单位比特静态随机存储器或单位比特动态随机存储器。
  3. 根据权利要求1所述的像素电路，其中，所述单位比特静态随机存储器包括：
    信号接收器件，用于根据所述单位比特静态随机存储器的控制端的控制指令接收所述曝光控制信号；
    信号处理器件，与所述信号接收器件连接，所述信号处理器件用于根据曝光控制信号生成所述电荷控制信号；
    所述信号接收器件包括：第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管的漏极与所述曝光控制信号的输出端连接，所述第一晶体管和所述第二晶体管的栅极与所述单位比特静态随机存储器的控制端连接；
    所述信号处理器件包括：第三晶体管、第四晶体管、第五晶体管和第六晶体管，所述第三晶体管和第四晶体管的源极与所述像素电路的第一电 压源连接，所述第三晶体管的栅极分别与所述第五晶体管的栅极、所述第四晶体管的漏极、所述第六晶体管的漏极、所述第一晶体管的源极和所述第一传输晶体管连接，所述第四晶体管的栅极分别与所述第六晶体管的栅极、所述第三晶体管的漏极、所述第五晶体管的漏极、所述第二晶体管的源极和所述第二传输晶体管连接，所述第五晶体管和所述六晶体管的源极接地。
  4. 根据权利要求3所述的像素电路，其中，所述单位比特动态随机存储器包括：
    第七晶体管，所述第七晶体管的漏极与所述曝光控制信号的输出端连接，所述第七晶体管的栅极与所述单位比特动态随机存储器的控制端连接，所述第七晶体管用于根据所述控制端的控制指令接收所述曝光控制信号；
    第一电容，所述第一电容的第一端分别与所述第七晶体管的源极和所述第一传输晶体管连接，所述第一电容的第二端接地；
    反向器，所述反向器的第一端与所述存储电容的第一端连接，所述反向器的第二端与所述第二传输晶体管连接。
  5. 根据权利要求1至4中任一项所述的像素电路，还包括：
    读取电路，与所述电荷存储器连接，所述读取电路用于读取所述电荷存储器中的所述电荷，并输出曝光图像。
  6. 根据权利要求5所述的像素电路，其中，所述电荷存储器包括：
    第一电荷存储器，与所述第一传输晶体管连接，所述第一电荷存储器用于根据所述读取电路的读取指令输出所述电荷；
    第二电荷存储器，与所述第二传输晶体管连接，所述第二电荷存储器用于根据所述读取电路的读取指令进行重置。
  7. 根据权利要求6所述的像素电路，其中，所述第一电荷存储器或所述第二电荷存储器包括：
    第二电容，与所述光电转换器件连接；
    存储晶体管，与所述第二电容和所述读取电路连接，所述存储晶体管 用于转移所述第二电容中的电荷至所述读取电路。
  8. 根据权利要求7所述的像素电路，还包括：
    浮动扩散节点，位于所述存储晶体管和所述读取电路之间；
    复位晶体管，接入第二电压源和所述浮动扩散点之间，所述复位晶体管用于根据复位控制信号重置所述浮动扩散节点电压；
    源跟随器晶体管，所述源跟随器晶体管的栅极与所述浮动扩散节点连接，所述源跟随器晶体管的漏极与所述第二电压源连接；
    行选择晶体管，所述行选择晶体管的漏极与所述源跟随器晶体管的源极连接，所述行选择晶体管的源极和栅极与所述读取电路连接。
  9. 根据权利要求1至4中任一项所述的像素电路，其中，所述第一传输晶体管和所述第二传输晶体管交替导通。
  10. 一种图像传感器，包括：
    根据权利要求1至9中任一项所述的像素电路。
  11. 一种摄像模组，包括：
    电路板；
    根据权利要求10所述的图像传感器，所述图像传感器与所述电路板电连接；
    镜头，设置于所述图像传感器的背离所述电路板的一侧。
  12. 一种电子设备，包括：
    根据权利要求11所述的摄像模组。
PCT/CN2021/140515 2020-12-28 2021-12-22 像素电路、图像传感器、摄像模组和电子设备 Ceased WO2022143344A1 (zh)

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112615995B (zh) * 2020-12-28 2022-07-01 维沃移动通信有限公司 像素电路、图像传感器、摄像模组和电子设备
CN113286092B (zh) * 2021-04-16 2023-05-02 维沃移动通信（杭州）有限公司 像素处理电路、方法、装置及电子设备
CN113676651B (zh) * 2021-08-25 2023-05-26 维沃移动通信有限公司 图像传感器、控制方法、控制装置、电子设备和存储介质
CN116132827A (zh) * 2021-11-11 2023-05-16 思特威(上海)电子科技股份有限公司 像素电路、cmos图像传感器及其提高动态范围的方法
CN114302078B (zh) * 2021-12-28 2023-04-07 锐芯微电子股份有限公司 像素结构控制方法及设备、计算机可读存储介质
CN119603570B (zh) * 2024-11-28 2025-10-28 维沃移动通信有限公司 像素电路、图像传感器、摄像头模组、设备及控制方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739854A (en) * 1991-04-22 1998-04-14 Canon Kabushiki Kaisha Image pickup apparatus
CN103595922A (zh) * 2013-11-04 2014-02-19 西北核技术研究所 一种基于电子快门曝光编码的成像方法
CN104485342A (zh) * 2014-12-11 2015-04-01 北京思比科微电子技术股份有限公司 一种图像传感器像素结构及其操作方法
CN206977570U (zh) * 2016-06-06 2018-02-06 半导体元件工业有限责任公司 图像传感器像素及图像传感器
CN111885316A (zh) * 2020-07-09 2020-11-03 深圳奥辰光电科技有限公司 一种图像传感器像素电路、图像传感器及深度相机
CN112615995A (zh) * 2020-12-28 2021-04-06 维沃移动通信有限公司 像素电路、图像传感器、摄像模组和电子设备

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7825973B2 (en) * 2004-07-16 2010-11-02 Micron Technology, Inc. Exposure control for image sensors
US8730382B2 (en) * 2008-06-04 2014-05-20 Honda Motor Co., Ltd. Charge accumulating and splitting imaging device
JP5458582B2 (ja) * 2009-01-28 2014-04-02 ソニー株式会社 固体撮像装置、固体撮像装置の駆動方法および電子機器
CN107924927B (zh) * 2015-08-04 2022-04-19 新唐科技日本株式会社 固体摄像装置
KR102314905B1 (ko) * 2015-09-30 2021-10-19 가부시키가이샤 니콘 촬상 소자 및 전자 카메라
US10044948B2 (en) * 2015-11-12 2018-08-07 Omnivision Technologies, Inc. Image sensor global shutter supply circuit with variable bandwidth
US10484628B2 (en) * 2016-10-21 2019-11-19 The Johns Hopkins University Flexible pixel-wise exposure control and readout
US10110840B2 (en) * 2016-10-25 2018-10-23 Semiconductor Components Industries, Llc Image sensor pixels with overflow capabilities
JP2018186398A (ja) * 2017-04-26 2018-11-22 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、および電子機器
KR102479014B1 (ko) * 2017-04-28 2022-12-16 더 가버닝 카운슬 오브 더 유니버시티 오브 토론토 픽셀 단위 이미징을 위한 방법 및 시스템
WO2018201219A1 (en) * 2017-05-02 2018-11-08 The University Of British Columbia Cmos image sensors with pixel-wise programmable exposure encoding and methods for use of same
CN108282626B (zh) * 2018-03-01 2021-04-23 思特威(上海)电子科技股份有限公司 Tof图像传感器像素结构及tof成像系统
CN110412607B (zh) * 2018-04-28 2021-12-03 思特威(上海)电子科技股份有限公司 具有高动态范围的tof像素电路及测距系统
JP7242262B2 (ja) * 2018-11-14 2023-03-20 キヤノン株式会社 光電変換装置及び撮像システム
JP7339290B2 (ja) * 2019-02-15 2023-09-05 ヌヴォトンテクノロジージャパン株式会社 撮像装置及び距離情報算出方法
CN109686318B (zh) * 2019-02-27 2021-03-16 深圳吉迪思电子科技有限公司 像素驱动电路及驱动方法
US11317042B2 (en) * 2020-08-25 2022-04-26 Pixart Imaging Inc. Image sensor apparatus and processing circuit capable of preventing sampled reset/exposure charges from light illumination as well as achieving lower circuit costs

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739854A (en) * 1991-04-22 1998-04-14 Canon Kabushiki Kaisha Image pickup apparatus
CN103595922A (zh) * 2013-11-04 2014-02-19 西北核技术研究所 一种基于电子快门曝光编码的成像方法
CN104485342A (zh) * 2014-12-11 2015-04-01 北京思比科微电子技术股份有限公司 一种图像传感器像素结构及其操作方法
CN206977570U (zh) * 2016-06-06 2018-02-06 半导体元件工业有限责任公司 图像传感器像素及图像传感器
CN111885316A (zh) * 2020-07-09 2020-11-03 深圳奥辰光电科技有限公司 一种图像传感器像素电路、图像传感器及深度相机
CN112615995A (zh) * 2020-12-28 2021-04-06 维沃移动通信有限公司 像素电路、图像传感器、摄像模组和电子设备

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4270921A4 *

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