WO2022160631A1 - 刷新电路及存储器 - Google Patents

刷新电路及存储器 Download PDF

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Publication number
WO2022160631A1
WO2022160631A1 PCT/CN2021/109273 CN2021109273W WO2022160631A1 WO 2022160631 A1 WO2022160631 A1 WO 2022160631A1 CN 2021109273 W CN2021109273 W CN 2021109273W WO 2022160631 A1 WO2022160631 A1 WO 2022160631A1
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Prior art keywords
refresh
signal
temperature
gate
output
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PCT/CN2021/109273
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English (en)
French (fr)
Inventor
谷银川
刘格言
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to EP21867904.1A priority Critical patent/EP4060668A4/en
Priority to US17/456,635 priority patent/US11862222B2/en
Publication of WO2022160631A1 publication Critical patent/WO2022160631A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a refresh circuit and a memory.
  • the data retention time of volatile memory is related to the chip temperature. At high temperature, the data retention time is shorter, and at low temperature, the data retention time is longer.
  • the traditional technology will meet the medium and high temperature as the standard. According to the data retention time in the medium and high temperature environment, refresh commands at corresponding time intervals are sent, and a fixed number of rows are refreshed under each refresh command. Therefore, under normal temperature or low temperature, all row addresses will be refreshed in advance in the corresponding longer data retention time, but the refresh command will also be sent at a fixed time interval. At this time, the refresh will start from row 0, but in During the data retention time, this part is redundant refresh, wasting current.
  • Embodiments of the present application provide a refresh circuit and a memory, which are beneficial to reduce consumption of refresh current.
  • an embodiment of the present application provides a refresh circuit, including: a refresh control module, configured to receive a refresh command to output a row address refresh signal, and output a preset number of times of the refresh command every time the refresh command is received.
  • a row address refresh signal also used for receiving a temperature signal to adjust the preset value, the higher the temperature represented by the temperature signal, the larger the adjusted preset value; the row addresser is used to receive all the preset values.
  • a row address refresh signal is described, and a single row address to be refreshed is output; an array refresh device is used to perform a single row refresh operation according to the single row address, and output a single row refresh end signal after the single row refresh is completed.
  • an embodiment of the present application further provides a memory including the refresh circuit described in any one of the above.
  • the preset value is adjusted according to the temperature signal, so that the number of refresh lines corresponding to each refresh command under high temperature conditions is larger, and the number of refresh lines corresponding to each refresh command under low temperature conditions is smaller; Under the condition that the time interval is constant, in a high temperature environment, in a short data retention time, the number of rows refreshed under each refresh command is more, which is beneficial to ensure that the refresh of all row addresses is completed; in a low temperature environment, in a relatively low temperature environment. In a long data retention time, the number of rows refreshed under each refresh command is small, which is beneficial to avoid the refresh of all rows in advance and repeated refreshes, thereby reducing the waste of refresh current and reducing the refresh rate corresponding to each refresh command. current.
  • FIG. 1 and FIG. 2 are schematic structural diagrams of a refresh circuit provided by an embodiment of the application
  • FIG. 3 is a timing diagram of signal generation of a refresh circuit provided by an embodiment of the present application.
  • the refresh circuit includes: a refresh control module 20 for receiving a refresh command 11 to output a row address refresh signal 12, each time receiving a refresh command 11, outputting a row address refresh signal 12 of a preset number of times; Receive the temperature signal 10a to adjust the preset value, the higher the temperature represented by the temperature signal 10a, the larger the adjusted preset value; the row addresser 30 is used to receive the row address refresh signal 12, and output a single row to be refreshed Address 13; the array refresh device 40 is configured to perform a single-row refresh operation according to the single-row address 13, and output a single-row refresh end signal 14 after the single-row refresh is completed.
  • the address information contained in the address 13 is incremented by 1, that is, the sequence of the 0th row, the 1st row, and the 2nd row is successively incremented until all row addresses are sent; Refreshing row by row, when row addresser 30 sends all row addresses, array refresh device 40 completes the refresh of all rows accordingly. It should be noted that after the row addresser 30 has sent all the row addresses, if it continues to receive the row address refresh signal 12, it will re-send all the row addresses in the order of row 0, row 1, row 2 . . .
  • the refresh control module 20 includes: a control unit 22 for receiving the row address refresh signal 12, outputting the reset signal 15, and for counting the row address refresh signal 12, when the count value is equal to the adjusted preset value When the value is set, the reset signal 15 is output; the refresh signal generation unit 21 is used to receive the refresh command 11, the reset signal 15 and the single-line refresh end signal 14, and output the row address refresh signal 12; When receiving the refresh command 11, output Row address refresh signal 12; when the single row refresh end signal 14 is received, the reset signal 15 is detected. If the reset signal 15 is not received, the row address refresh signal 12 is output. If the reset signal 15 is received, the output of the row address is stopped. Refresh signal 12.
  • control unit 22 includes: a counting subunit 23 for receiving the row address refresh signal 12, for counting the received row address refresh signal 12, and outputting a count value 16; an adjustment subunit 24 for receiving the temperature signal 10a and count value 16, output excitation signal 17, and used to adjust the preset value according to temperature signal 10a, when the count value 16 is equal to the adjusted preset value, output excitation signal 17; automatic pulse generator 25, used to receive The excitation signal 17 and the reset signal 15 are output.
  • the counting subunit 23 includes an asynchronous binary addition counter composed of a plurality of D flip-flops in series
  • the adjustment subunit 24 includes an OR gate and a plurality of AND gates, and at least one input of the AND gate is The terminal is connected to the input terminal of the asynchronous binary addition counter, the output terminal of the AND gate is connected to the input terminal of the OR gate, the output terminal of the OR gate is used as the output terminal of the adjustment subunit 24, and all the input terminals of at least one AND gate are connected to the asynchronous binary addition counter.
  • At least one AND gate When the level of the counting terminal represents the default value, at least one AND gate outputs a high level; at least one input terminal of another AND gate receives the temperature signal 10a, and when the level of the counting terminal represents the first value, at least another AND gate receives the temperature signal 10a.
  • An AND gate outputs a high level, and the first value is less than the default value.
  • the number of D flip-flops constituting the asynchronous binary addition counter is related to the maximum number of refresh lines corresponding to a single refresh command 11.
  • the number of devices is less.
  • the maximum count value of n D flip-flops is 2 n -1, and the maximum count value needs to be greater than or equal to the maximum number of refresh rows. For example, when the maximum number of refresh rows is 7, the number of D flip-flops is at least 3.
  • the D flip-flop has a data input terminal D, a clock input terminal CK, a first data output terminal Q, a second data output terminal QB and a reset terminal RST, wherein the first data output terminal Q and the second data output terminal QB are complementary.
  • the following takes 3 D flip-flops as an example to describe the working principle and connection method of the asynchronous binary addition counter in detail:
  • Asynchronous binary addition counter (hereinafter referred to as "counter”) includes a first D flip-flop 231 as a low bit, a second D flip-flop 232 as a second high bit, and a third D flip-flop 233 as a high bit.
  • the two data output terminals QB are connected to the data input terminal D, and are also connected to the clock input terminal CK of the next stage D flip-flop.
  • the first data output terminal Q of each D flip-flop is used as a counting terminal, and the reset terminal RST receives After setting the signal 15, the level is reset, that is, it represents 0.
  • the clock input terminal CK of the first D flip-flop 231 is used to receive the row address refresh signal 12, the first D flip-flop 231 has a first count terminal Q1; the second D flip-flop 232 has a second count terminal Q2; The D flip-flop 233 has a third count terminal Q3.
  • the D flip-flop When the D flip-flop characterizes 1, the corresponding count terminal is at a high level. When the data recorded by the relatively low-order D flip-flop reaches 2, the next-level relatively high-order D flip-flop needs to be carried. The D flip-flop is reset, representing 0, and the relatively high-order D flip-flop is carried, representing 1, which constitutes a binary full of 2 into 1.
  • the count value is incremented, that is, the count value Q3Q2Q1 is in accordance with 000, 001, The order of 010, 011, 100, 101, 110, 111 is incremented, and the above count value Q3Q2Q1 is converted into decimal to represent 0, 1, 2, 3, 4, 5, 6, 7 respectively; when the counter receives the reset signal, the count The value Q3Q2Q1 is reset to the initial state of 000.
  • n temperature signals 10a correspond to n adjusted preset values.
  • each adjusted preset value corresponds to an AND gate, n+1 AND gates are required for n temperature signals, and at least two AND gates are required.
  • the number of input terminals of the AND gate is less than or equal to the number of D flip-flops in the counting subunit 23 . Since the number of D flip-flops determines the maximum count value of the counting subunit 23, the optional range of preset values under different temperature conditions can be expanded by increasing the number of D flip-flops, so that under extreme temperature conditions, all Timely refresh of row addresses, as well as reducing the waste of refresh current.
  • the adjustment subunit 24 is configured to receive the first temperature signal T1, the second temperature signal T2 and the third temperature signal T3, the first temperature signal T1 represents that the current temperature is less than or equal to the first temperature and greater than the second temperature, The second temperature signal T2 represents that the current temperature is less than or equal to the second temperature and greater than the third temperature, and the third temperature signal T3 represents that the current temperature is less than or equal to the third temperature.
  • each refresh command 11 when the current temperature is greater than the first temperature, the number of refresh lines corresponding to each refresh command 11 is 7 lines, that is, the default value is 7; within the temperature range represented by the first temperature signal T1, each refresh command 11 corresponds to The number of refresh lines is 6 lines; in the temperature range represented by the second temperature signal T2, the number of refresh lines corresponding to each refresh command 11 is 5 lines; in the temperature range represented by the third temperature signal T3, each refresh command The number of refresh lines corresponding to 11 is 3 lines.
  • the adjustment subunit 24 provided in the embodiment of the present application includes four AND gates, and the number of the input terminals of the AND gate is equal to the number of D flip-flops. specifically:
  • the adjustment subunit 24 includes a first AND gate 241 , a second AND gate 242 , a third AND gate 243 , a fourth AND gate 244 and an OR gate 245 , a first input terminal 241 a of the first AND gate 241 and a first counting terminal Q1 connection, the second input terminal 241b is connected to the second counting terminal Q2, the third input terminal 241c is connected to the third counting terminal Q3; the first input terminal 242a of the second AND gate 242 is used to receive the first temperature signal T1, the second The input terminal 242b is connected to the second counting terminal Q2, the third input terminal 242c is connected to the third counting terminal Q3; the first input terminal 243a of the third AND gate 243 is connected to the first counting terminal Q1, and the second input terminal 243b is used for Receiving the second temperature signal T2, the third counting terminal 243c is connected to the third counting terminal Q3; the first input terminal 244a of the fourth AND gate 244 is connected to the first counting terminal Q1, and the second input terminal 244
  • the adjustment subunit 24 does not receive the temperature signal 10a
  • the first input terminal 242a of the second AND gate 242, the second input terminal 243b of the third AND gate 243, and the third input terminal 244c of the fourth AND gate 244 are always in the state of Low level
  • the output terminals of the second AND gate 242, the third AND gate 243 and the fourth AND gate 244 are always at a low level, at this time, only the first counting terminal Q1, the second counting terminal Q2 and the third counting terminal are The level of Q3 is all high, that is, when the count value 16 of the counting subunit 23 is 7, the first input end 241a, the second input end 241b and the third input end 241c of the first AND gate 241 can all receive High level, the first AND gate 241 can output a high level signal, and the OR gate 245 can output a high level signal as the excitation signal 17 of the automatic pulse generator 25 .
  • the automatic pulse generator 25 generates a reset signal 15 after receiving the excitation signal 17.
  • the adjustment sub-unit 24 when the adjustment sub-unit 24 receives the first temperature signal T1, the first input terminal 242a of the second AND gate 242 is at a high level.
  • the average is high level, that is, when the count value 16 of the counting subunit 23 is 6, the second AND gate 242 can output a high level signal, so that the OR gate 245 sends an active high level signal to the automatic pulse generator 25.
  • the OR gate 245 sends the excitation signal 17 to the automatic pulse generator 25; when the third input terminal 244c of the fourth AND gate 244 receives the third temperature signal T3, and the first count terminal Q1 and The level of the second counting terminal Q2 is all high, that is, when the count value 16 of the counting subunit 23 is 3, the OR gate 245 sends the excitation signal 17 to the automatic pulse generator 25 .
  • the counting subunit 23 counts the row address refresh signal 12, and when the count value reaches the preset value corresponding to the temperature signal 10a, the automatic pulse generator 25 generates the reset signal 15, so that the refresh signal is generated
  • the unit 21 stops outputting the row address refresh signal 12 . Because the lower the temperature, the smaller the preset value, therefore, as the temperature decreases, the number of row address refresh signals 12 output under each refresh command 11 is less, and the number of refresh rows corresponding to a single refresh command 11 is smaller. In this way, the total number of refresh rows in a relatively long data retention time can be reduced, and the waste of refresh current can be reduced.
  • the first temperature signal T1 represents that the current temperature is less than or equal to 85°C and greater than 45°C
  • the second temperature signal T2 represents that the current temperature is less than or equal to 45°C and greater than 0°C
  • the third temperature signal T3 represents that the current temperature is less than or equal to 0 °C.
  • a temperature signal may be set at every other fixed temperature interval, that is, the temperature interval range represented by the first temperature signal T1 is equal to the temperature interval range represented by the second temperature signal T2.
  • the temperature range range represented by the first temperature signal T1 may be 20°C to 50°C, for example, 30°C, 35°C, 40°C or 45°C. In this way, it is beneficial to ensure that there is a certain difference in the data holding time corresponding to different temperature signals, to the extent that the preset value needs to be added or subtracted by one; This ensures that all row addresses can be refreshed within the data retention time and avoids wasting refresh current.
  • the difference between the preset values corresponding to adjacent temperature signals may be 1 to 3 lines, for example, 2 lines. By limiting the difference within a small range, it is beneficial to more precisely adjust the preset values of the refresh command 11 under different temperature conditions, and reduce the waste of refresh current.
  • the application does not specifically limit the effective manner of the specific signal between different functional structures, and the specific signal can be either high-level active or low-level active, and can also be active on a rising edge or active on a falling edge.
  • the refresh command 11 is a high-level active pulse signal
  • the single-line refresh end signal 14 is a high-level active pulse signal
  • the reset signal 15 is a high-level active pulse signal.
  • the refresh signal generating unit 21 includes: a first NOR gate 21a for receiving the refresh command 11 and the single-line refresh end signal 14; and a refresh window generation unit 21b for receiving the refresh command 11 and the single-line refresh end signal 14 and reset signal 15, output refresh window signal 18; when receiving refresh command 11, output refresh window signal 18; used to detect reset signal 15 when receiving single-line refresh end signal 14, if no reset is received Signal 15, continuously output the refresh window signal 18, if receiving the reset signal 15, stop outputting the refresh window signal 18; the second NOR gate 21c is used to receive the output signal of the first NOR gate 21a and the refresh window signal 18, A row address refresh signal 12 is output.
  • the refresh window signal 18 is a window signal whose low level is active, and the duration of the refresh window signal 18 is used to represent the time length corresponding to each refresh command 11 that can be used to send the row address refresh signal 12 .
  • the refresh circuit further includes: a switch unit 50, when the switch unit 50 is turned on, the adjustment subunit 24 in the refresh control module 20 can adjust the preset value according to the temperature signal 10a, and when the switch unit 50 is turned off, the AND gate The input terminal of the middle receiving temperature signal 10a is at a low level, the AND gate outputs a low level, and the preset value is the default value.
  • the size of the default value depends on the number of input terminals of the first AND gate 241, the number of D flip-flops included in the counter, and the connection relationship between the first AND gate 241 and the counter.
  • the default value is 7; in addition, the switch unit 50 includes a fuse unit, and the refresh control module 20 can receive the temperature signal 10a through the fuse unit.
  • the refresh circuit further includes a temperature sensor 10 for detecting the temperature of the target chip and outputting a temperature signal 10a. That is to say, the refresh circuit adjusts the number of refresh rows corresponding to each refresh command 11 according to the temperature of the target chip.
  • the first signal generation process when receiving the refresh command 11 with an active high level, the output terminal of the first NOR gate 21a becomes a low level, and the refresh window generating unit 21b outputs the refresh window signal 18 with an active low level, and the second The output terminal of the NOR gate 21c becomes a high level, that is, the refresh signal generating unit 21 outputs the row address refresh signal 12 that is active at a high level;
  • the second signal generation process the row addresser 30 and the counting sub-unit 23 receive the row address refresh signal 12 respectively, the count value 16 output by the counting sub-unit 23 is 1, and the row addresser 30 stores the first single row address to be refreshed. 13 is sent to the array refresh device 40, and the array refresh device 40 performs a refresh operation according to the single row address 13.
  • the refresh operation includes a row activation window and a precharge window.
  • the row activation window is a high-level active window signal.
  • the occurrence of the row activation window signal indicates the start of a single row refresh operation.
  • the duration of the row activation window needs to be greater than the row addressing time to ensure that the row seeks.
  • the address can be completed effectively, the precharge window is a high-level active window signal, and the end of the precharge window represents the end of the single-line refresh.
  • the duration of the precharge window needs to be longer than the precharge time to ensure that the precharge is effectively completed.
  • the third signal generation process after the array refresh device 40 completes the single-row refresh operation of the single-row address 13, it outputs the single-row refresh end signal 14.
  • the refresh window generation unit 21b detects the reset signal 15 after receiving the single-line refresh end signal 14. Since the count value 16 is 1 at this time and has not yet reached 3, the reset signal 15 has not been issued yet, and the refresh window generation unit 21b continues to output At the same time, since the single-line refresh end signal 14 is an active high-level pulse signal, the first NOR gate 21a outputs a low level when receiving the single-line refresh end signal 14 . In this way, the second NOR gate 21c can output the second row address refresh signal 12, and repeat the second signal generating process. At this time, the count value 16 changes from 1 to 2.
  • the fourth signal generation process after the refresh signal generation unit 21 outputs the third row address refresh signal 12, the count value 16 changes from 2 to 3, the three input terminals of the fourth AND gate 244 are all high, and the fourth The AND gate 244 outputs a high level, and the OR gate 245 outputs the excitation signal 17; the automatic pulse generator 25 generates the reset signal 15 under the excitation of the excitation signal 17, and the reset terminal RST of each D flip-flop receives the reset signal 15, The level is reset to a low level, representing a value of 0. At this time, the count value 16 is reset from 3 to 0; at the same time, the refresh window generation unit 21b receives the reset signal 15 .
  • the fifth signal generation process after the array refresh device 40 completes the single-row refresh action according to the single-row address 13 corresponding to the third row address refresh signal 12, it outputs the third single-row refresh end signal 14; the refresh window generation unit 21b receives the single-row refresh. After the end signal 14, the reset signal 15 is detected. Since the automatic pulse generator 25 has sent the reset signal 15 at this time, the refresh window signal 18 of the refresh window generation unit 21b is stopped, and the output terminal level of the refresh window generation unit 21b is refreshed. From low level to high level, the output terminal of the second NOR gate 21c changes to low level, that is, the output of the row address refresh signal 12 is stopped, so that the number of refresh rows corresponding to each refresh command 11 is 3.
  • the duration of the reset signal 15 output by the automatic pulse generator 25 should be longer than the row addressing time of the row addresser 30 and the single-row refresh time of the array refresh device 40 to ensure that the refresh window generation unit 21b receives At the third single-row refresh end signal 14 , the reset signal 15 is still continued, thereby effectively suspending the output of the row address refresh signal 12 .
  • the above timing diagram only takes one refresh command 11 as an example.
  • the refresh window generation unit 21b receives the refresh command 11 again, it can output the refresh window signal 18 again, and the refresh circuit repeats the above signal generation process.
  • the adjustment sub-unit 24 receives other temperature signals 10a or no longer receives other temperature signals 10a during the refresh period corresponding to the refresh command 11, the preset value of the number of refresh lines corresponding to the refresh command 11 is caused. Increase, at this time, as long as the automatic pulse generator 25 has not generated the reset signal 15, the refresh circuit refreshes the row address according to the increased preset value; If the preset value of the corresponding number of refreshed rows decreases, then see if the current count value 16 is greater than or equal to the reduced preset value. If it is greater than or equal to, then stop outputting the row address refresh signal 12. The default value for single-line address refresh.
  • the preset value is adjusted according to the temperature signal, so that the number of refresh lines corresponding to each refresh command under high temperature conditions is larger, and the number of refresh lines corresponding to each refresh command under low temperature conditions is smaller; Under the condition that the time interval is constant, in a high temperature environment, in a short data retention time, the number of rows refreshed under each refresh command is more, which is beneficial to ensure that the refresh of all row addresses is completed; in a low temperature environment, in a relatively low temperature environment. In a long data retention time, the number of rows refreshed under each refresh command is small, which is beneficial to avoid the refresh of all rows in advance and repeated refreshes, thereby reducing the waste of refresh current and reducing the refresh rate corresponding to each refresh command. current.
  • an embodiment of the present application further provides a memory including any one of the above refresh circuits. In this way, it is beneficial to reduce the current waste during the memory refresh process.

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Abstract

本申请实施例提供一种刷新电路及存储器，刷新电路包括：刷新控制模块，用于接收刷新命令，以输出行地址刷新信号，每接收一所述刷新命令，输出预设值次数的所述行地址刷新信号；还用于接收温度信号，以调整所述预设值，所述温度信号表征的温度越高，调整后的所述预设值越大；行寻址器，用于接收所述行地址刷新信号，并输出待刷新的单行地址；阵列刷新装置，用于根据所述单行地址进行单行刷新操作，且在单行刷新结束后输出单行刷新结束信号。本申请实施例有利于减少刷新电流的消耗。

Description

刷新电路及存储器
交叉引用
本申请基于申请号为202110128762.X、申请日为2021年01月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及半导体领域，特别涉及一种刷新电路及存储器。
背景技术
为了保存易失性存储器中的数据，需要定期对易失性存储器进行刷新操作，刷新操作需要在数据保持时间内完成所有行的刷新。易失性存储器的数据保持时间与芯片温度有关，高温下，数据保持时间较短，低温下，数据保持时间较长。
传统技术会以满足中高温为标准，根据中高温环境下的数据保持时间，发送相应时间间隔的刷新命令，每个刷新命令下刷新固定的行数。因此，在常温或低温下，对应的较长的数据保持时间内所有行地址会提前刷完，但是刷新命令还会按照固定的时间间隔发送，此时会再从第0行开始刷新，但是在数据保持时间内，这部分就是多余的刷新，浪费了电流。
发明内容
本申请实施例提供一种刷新电路及存储器，有利于减少刷新电流的消耗。
为解决上述问题，本申请实施例提供一种刷新电路，包括：刷新控 制模块，用于接收刷新命令，以输出行地址刷新信号，每接收一所述刷新命令，输出预设值次数的所述行地址刷新信号；还用于接收温度信号，以调整所述预设值，所述温度信号表征的温度越高，调整后的所述预设值越大；行寻址器，用于接收所述行地址刷新信号，并输出待刷新的单行地址；阵列刷新装置，用于根据所述单行地址进行单行刷新操作，且在单行刷新结束后输出单行刷新结束信号。
相应地，本申请实施例还提供一种存储器，包括上述任一项所述的刷新电路。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
上述技术方案中，根据温度信号调整预设值，使得高温条件下的每一刷新命令对应的刷新行数较多，低温条件下每一刷新命令对应的刷新行数较少；在相邻刷新命令的时间间隔不变的情况下，高温环境中，在较短的数据保持时间内，每个刷新命令下刷新的行数较多，有利于保证完成所有行地址的刷新；低温环境中，在较长的数据保持时间内，每个刷新命令下刷新的行数较少，有利于避免提前完成所有行的刷新而进行重复刷新，从而减少刷新电流的浪费，以及减小每一刷新命令对应的刷新电流。
另外，通过将相邻温度信号对应的刷新行数的差值限定在较小范围内，有利于更为精密地调整刷新命令在不同温度条件下对应的刷新行数，减少刷新电流的浪费。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明， 这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1和图2为本申请实施例提供的刷新电路的结构示意图；
图3为本申请实施例提供的刷新电路的信号发生时序图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
参考图1，刷新电路包括：刷新控制模块20，用于接收刷新命令11，以输出行地址刷新信号12，每接收一刷新命令11，输出预设值次数的行地址刷新信号12；还用于接收温度信号10a，以调整预设值，温度信号10a表征的温度越高，调整后的预设值越大；行寻址器30，用于接收行地址刷新信号12，并输出待刷新的单行地址13；阵列刷新装置40，用于根据单行地址13进行单行刷新操作，且在单行刷新结束后输出单行刷新结束信号14。
行寻址器30每接收到一个行地址刷新信号12，输出一个待刷新的单行地址13，单行地址13对应到阵列刷新装置40里的阵列的每一行，每接收一个行地址刷新信号12，单行地址13包含的地址信息递增1，即按照第0行、第1行、第2行的顺序进行逐次递增，直至发送完所有 行地址；相应地，阵列刷新装置40根据接收到的单行地址13进行逐行刷新，当行寻址器30发送完所有行地址，阵列刷新装置40相应地完成所有行的刷新。需要说明的是，在行寻址器30发送完所有行地址之后，若继续接收到行地址刷新信号12，则重新按照第0行、第1行、第2行…的顺序发送所有行地址。
本实施例中，刷新控制模块20包括：控制单元22，用于接收行地址刷新信号12，输出重置信号15，还用于对行地址刷新信号12进行计数，当计数值等于调整后的预设值时，输出重置信号15；刷新信号生成单元21，用于接收刷新命令11、重置信号15以及单行刷新结束信号14，输出行地址刷新信号12；当接收到刷新命令11时，输出行地址刷新信号12；在接收到单行刷新结束信号14时，检测重置信号15，若未接收到重置信号15，输出行地址刷新信号12，若接收到重置信号15，中止输出行地址刷新信号12。
进一步地，控制单元22包括：计数子单元23，用于接收行地址刷新信号12，并对接收到的行地址刷新信号12进行计数，输出计数值16；调节子单元24，用于接收温度信号10a和计数值16，输出激励信号17，且用于根据温度信号10a调整预设值，当计数值16等于调整后的预设值时，输出激励信号17；自动脉冲生成器25，用于接收激励信号17并输出重置信号15。
参考图1和图2，本实施例中，计数子单元23包括由多个D触发器串联组成的异步二进制加法计数器，调节子单元24包括或门和多个与门，与门的至少一输入端连接异步二进制加法计数器的输入端，与门的 输出端连接到或门的输入端，或门的输出端作为调节子单元24的输出端，至少一与门的所有输入端连接异步二进制加法计数器的计数端，当计数端的电平表征默认数值时，至少一与门输出高电平；至少另一与门的一个输入端接收温度信号10a，且计数端的电平表征第一数值时，至少另一与门输出高电平，第一数值小于默认数值。
其中，构成异步二进制加法计数器的D触发器的数量与单一刷新命令11对应的最大刷新行数有关，最大刷新行数越大，D触发器的数量越多，最大刷新行数越小，D触发器的数量越少。具体地，n个D触发器的最大计数值为2 n-1，最大计数值需要大于等于最大刷新行数。例如最大刷新行数为7时，D触发器的数量最少为3个。
D触发器具有数据输入端D、时钟输入端CK、第一数据输出端Q、第二数据输出端QB以及复位端RST，其中，第一数据输出端Q与第二数据输出端QB互补。以下以3个D触发器为例，详细说明异步二进制加法计数器的工作原理和连接方式：
异步二进制加法计数器(以下简称“计数器”)包括作为低位的第一D触发器231、作为次高位的第二D触发器232和作为高位的第三D触发器233，每一D触发器的第二数据输出端QB与数据输入端D连接，且与下一级D触发器的时钟输入端CK连接，每一D触发器的第一数据输出端Q作为计数端，复位端RST在接收到重置信号15之后复位电平，即表征0。其中，第一D触发器231的时钟输入端CK用于接收行地址刷新信号12，第一D触发器231具有第一计数端Q1；第二D触发器232具有第二计数端Q2；第三D触发器233具有第三计数端Q3。
当D触发器表征1时，相应的计数端呈高电平，当相对低位的D触发器记录的数据达到2时，需要向下一级相对高位的D触发器进位，此时，相对低位的D触发器复位，表征0，相对高位的D触发器进位，表征1，即构成二进制的满2进1。
具体地，当计数器未接收第一行地址刷新信号12时，处于初始状态，计数值Q3Q2Q1＝000，每接收到一个行地址刷新信号12，计数值递增一次，即计数值Q3Q2Q1按照000、001、010、011、100、101、110、111的顺序进行递增，上述计数值Q3Q2Q1换算为十进制分别代表0、1、2、3、4、5、6、7；当计数器受到重置信号之后，计数值Q3Q2Q1复位到000的初始状态。
此外，与门的数量与接收的温度信号10a的个数有关。由于不同温度信号10a表征的温度区间不同，调节子单元24根据温度信号10a调整得到的刷新行数预设值也不同，因此，n个温度信号10a对应n个调整后的预设值。本实施例中，每一调整后的预设值对应一与门，n个温度信号需要n+1个与门，与门最少为2个。
本实施例中，与门的输入端的数量小于等于计数子单元23中D触发器的数量。由于D触发器的数量决定计数子单元23的最大计数值，因此，可通过增加D触发器的数量，扩大不同温度条件下的预设值的可选范围，从而在极端温度条件下，实现所有行地址的及时刷新，以及减少刷新电流的浪费。
以下将通过具体示例举例说明调节子单元24的结构以及调节子单元24与计数子单元23的连接关系。在该具体示例中，调节子单元24 用于接收第一温度信号T1、第二温度信号T2以及第三温度信号T3，第一温度信号T1表征当前温度小于等于第一温度且大于第二温度，第二温度信号T2表征当前温度小于等于第二温度且大于第三温度，第三温度信号T3表征当前温度小于等于第三温度。
相应地，在当前温度大于第一温度时，每一刷新命令11对应的刷新行数为7行，即默认数值为7；在第一温度信号T1表征的温度区间内，每一刷新命令11对应的刷新行数为6行；在第二温度信号T2表征的温度区间内，每一刷新命令11对应的刷新行数为5行；在第三温度信号T3表征的温度区间内，每一刷新命令11对应的刷新行数为3行。
为实现上述具体示例，本申请实施例提供的调节子单元24包括四个与门，与门的输入端的数量等于D触发器的数量。具体地：
调节子单元24包括第一与门241、第二与门242、第三与门243、第四与门244以及或门245，第一与门241的第一输入端241a与第一计数端Q1连接，第二输入端241b与第二计数端Q2连接，第三输入端241c与第三计数端Q3连接；第二与门242的第一输入端242a用于接收第一温度信号T1，第二输入端242b与第二计数端Q2连接，第三输入端242c与第三计数端Q3连接；第三与门243的第一输入端243a与第一计数端Q1连接，第二输入端243b用于接收第二温度信号T2，第三计数端243c与第三计数端Q3连接；第四与门244的第一输入端244a与第一计数端Q1连接，第二输入端244b与第二计数端Q2连接，第三输入端244c用于接收第三温度信号T3。
当调节子单元24没有接收到温度信号10a时，第二与门242的第 一输入端242a、第三与门243的第二输入端243b以及第四与门244的第三输入端244c始终呈低电平，第二与门242、第三与门243以及第四与门244的输出端始终呈低电平，此时，只有第一计数端Q1、第二计数端Q2以及第三计数端Q3的电平都呈高电平，即计数子单元23的计数值16为7时，第一与门241的第一输入端241a、第二输入端241b以及第三输入端241c才能都接收到高电平，第一与门241才能输出高电平信号，或门245才能输出高电平信号，作为自动脉冲生成器25的激励信号17。自动脉冲生成器25在接收到激励信号17之后生成重置信号15，重置信号15一方面使得计数器恢复到初始状态，即Q3Q2Q1＝000，另一方面使得刷新信号生成单元21中止输出行地址刷新信号12。
相应地，当调节子单元24接收到第一温度信号T1时，第二与门242的第一输入端242a呈高电平，此时，当第二计数端Q2和第三计数端Q3的电平都呈高电平，即计数子单元23的计数值16为6时，第二与门242就可以输出高电平信号，以使或门245向自动脉冲生成器25发送高电平有效的激励信号17。
同理地，当第三与门243的第二输入端243b接收到第二温度信号T2，且第一计数端Q1和第三计数端Q3的电平都呈高电平，即计数子单元23的计数值16为5时，或门245就向自动脉冲生成器25发送激励信号17；当第四与门244的第三输入端244c接收到第三温度信号T3，且第一计数端Q1和第二计数端Q2的电平都呈高电平，即计数子单元23的计数值16为3时，或门245就向自动脉冲生成器25发送激励信号17。
总的来说，计数子单元23对行地址刷新信号12进行计数，当计数 值达到与温度信号10a对应的预设值后，自动脉冲生成器25就产生重置信号15，以使得刷新信号生成单元21中止输出行地址刷新信号12。由于温度越低预设值越小，因此随着温度降低，每一个刷新命令11下输出的行地址刷新信号12越少，单一刷新命令11对应的刷新行数越少。如此，可减少相对较长的数据保持时间内的总刷新行数，减少刷新电流的浪费。
本实施例中，第一温度信号T1表征当前温度小于等于85℃且大于45℃，第二温度信号T2表征当前温度小于等于45℃且大于0℃，第三温度信号T3表征当前温度小于等于0℃。
本实施例中，可每隔一个固定的温度区间设置一个温度信号，即第一温度信号T1表征的温度区间极差与第二温度信号T2表征的温度区间极差相等。
其中，第一温度信号T1表征的温度区间极差可以为20℃～50℃，例如为30℃、35℃、40℃或45℃。如此，有利于保证不同温度信号对应的数据保持时间存在一定差别，达到需要对预设值进行加一或减一的程度；另外，有利于避免不同温度信号对应的数据保持时间差值过大，从而保证所有行地址都能在数据保持时间内完成刷新，以及避免浪费刷新电流。
此外，相邻温度信号对应的预设值的差值可以为1～3行，例如2行。通过将差值限定在较小范围内，有利于更为精密地调整刷新命令11在不同温度条件下对应的预设值，减少刷新电流的浪费。
关于不同功能结构之间的特定信号的有效方式，本申请并不进行特 别限定，特定信号既可以是高电平有效或低电平有效，也可以是上升沿有效或下降沿有效。本实施例中，刷新命令11为高电平有效的脉冲信号，单行刷新结束信号14为高电平有效的脉冲信号，重置信号15为高电平有效的脉冲信号。
本实施例中，刷新信号生成单元21包括：第一或非门21a，用于接收刷新命令11和单行刷新结束信号14；刷新窗口生成单元21b，用于接收刷新命令11、单行刷新结束信号14以及重置信号15，输出刷新窗口信号18；当接收到刷新命令11时，输出刷新窗口信号18；用于在接收到单行刷新结束信号14时，检测重置信号15，若未接收到重置信号15，持续输出刷新窗口信号18，若接收到重置信号15，中止输出刷新窗口信号18；第二或非门21c，用于接收第一或非门21a的输出信号和刷新窗口信号18，输出行地址刷新信号12。
其中，刷新窗口信号18低电平有效的窗口信号，刷新窗口信号18的持续时长用于表征每一刷新命令11对应的可用于发送行地址刷新信号12的时长。
本实施例中，刷新电路还包括：开关单元50，开关单元50导通时，刷新控制模块20中的调节子单元24可根据温度信号10a调整预设值，开关单元50断开时，与门中接收温度信号10a的输入端处于低电平，与门输出低电平，预设值为默认数值。默认数值的大小取决于第一与门241的输入端数量、计数器包含的D触发器的数量、以及第一与门241和计数器的连接关系。
具体地，本实施例中，默认数值为7；此外，开关单元50包括熔丝 单元，刷新控制模块20可通过熔丝单元接收温度信号10a。
进一步地，刷新电路还包括温度传感器10，用于检测目标芯片的温度并输出温度信号10a。也就是说，刷新电路根据目标芯片的温度调整每一刷新命令11对应的刷新行数。
以下将以调节子单元24接收到第三温度信号T3，调整后的预设值为3作为示例，结合图3提供的刷新电路的信号发生时序图说明刷新电路的运行原理。需要说明的是，图3中带有箭头的虚线指的是信号发生的因果关系，箭头起点为因，终点为果。具体地：
第一信号发生过程：接收到高电平有效的刷新命令11时，第一或非门21a输出端变为低电平，刷新窗口生成单元21b输出低电平有效的刷新窗口信号18，第二或非门21c输出端变为高电平，即刷新信号生成单元21输出高电平有效的行地址刷新信号12；
第二信号发生过程：行寻址器30和计数子单元23分别接收行地址刷新信号12，计数子单元23输出的计数值16为1，行寻址器30将第一个待刷新的单行地址13发送给阵列刷新装置40，阵列刷新装置40根据单行地址13进行刷新操作。刷新操作包括行激活窗口和预充电窗口，行激活窗口为高电平有效的窗口信号，行激活窗口信号出现代表单行刷新操作开始，行激活窗口的持续时长需要大于行寻址时间，保证行寻址可有效完成，预充电窗口为高电平有效的窗口信号，预充电窗口结束代表单行刷新结束，预充电窗口的时长需要大于预充电时间，保证预充电有效完成。
第三信号发生过程：阵列刷新装置40完成单行地址13的单行刷新 操作之后，输出单行刷新结束信号14。刷新窗口生成单元21b在接收到单行刷新结束信号14之后，检测重置信号15，由于此时计数值16为1，还未到达3，因此重置信号15尚未发出，刷新窗口生成单元21b继续输出低电平有效的刷新窗口信号18；同时，由于单行刷新结束信号14为高电平有效的脉冲信号，因此第一或非门21a在接收到单行刷新结束信号14时输出低电平。如此，第二或非门21c可输出第二个行地址刷新信号12，重复第二信号发生过程，此时，计数值16由1变为2。
第四信号发生过程：在刷新信号生成单元21输出第三个行地址刷新信号12之后，计数值16由2变为3，第四与门244的三个输入端都为高电平，第四与门244输出高电平，或门245输出激励信号17；自动脉冲生成器25在激励信号17的激励作用下生成重置信号15，每一D触发器的复位端RST接收重置信号15，电平复位至低电平，表征数值0，此时，计数值16由3复位为0；同时，刷新窗口生成单元21b接收到重置信号15。
第五信号发生过程：阵列刷新装置40根据第三个行地址刷新信号12对应的单行地址13完成单行刷新动作之后，输出第三个单行刷新结束信号14；刷新窗口生成单元21b在接收到单行刷新结束信号14之后，检测重置信号15，由于此时自动脉冲生成器25已发送重置信号15，因此，刷新窗口生成单元21b的刷新窗口信号18中止，刷新窗口生成单元21b的输出端电平由低电平变为高电平，第二或非门21c输出端变为低电平，即中止输出行地址刷新信号12，从而实现每一刷新命令11对应的刷新行数为3。
需要说明的是，自动脉冲生成器25输出的重置信号15的持续时长应当大于行寻址器30的行寻址时间以及阵列刷新装置40的单行刷新时间，保证刷新窗口生成单元21b在接收到第三个单行刷新结束信号14时，重置信号15依旧持续，从而有效中止行地址刷新信号12的输出。
上述时序图仅以一个刷新命令11作为示例，当刷新窗口生成单元21b再次接收到刷新命令11时，可再次输出刷新窗口信号18，刷新电路重复上述信号发生过程。
需要补充的是，如果在刷新命令11对应的刷新期间内，调节子单元24接收到了其他温度信号10a或者不再接收到其他温度信号10a，从而导致刷新命令11对应的刷新行数的预设值增加，此时，只要自动脉冲生成器25还未生成重置信号15，刷新电路根据增加后的预设值进行行地址刷新；相反的，如果在刷新命令11对应的刷新期间内，刷新命令11对应的刷新行数的预设值减小，则看当前计数值16是否大于等于减小后的预设值，若大于等于，则中止输出行地址刷新信号12，若小于，则根据减小后的预设值进行单行地址刷新。
本实施例中，根据温度信号调整预设值，使得高温条件下的每一刷新命令对应的刷新行数较多，低温条件下每一刷新命令对应的刷新行数较少；在相邻刷新命令的时间间隔不变的情况下，高温环境中，在较短的数据保持时间内，每个刷新命令下刷新的行数较多，有利于保证完成所有行地址的刷新；低温环境中，在较长的数据保持时间内，每个刷新命令下刷新的行数较少，有利于避免提前完成所有行的刷新而进行重复刷新，从而减少刷新电流的浪费，以及减小每一刷新命令对应的刷新电 流。
相应地，本申请实施例还提供一种存储器，包含上述任一项刷新电路。如此，有利于降低存储器刷新过程中的电流浪费。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种刷新电路，包括：
    刷新控制模块，用于接收刷新命令，以输出行地址刷新信号，每接收一所述刷新命令，输出预设值次数的所述行地址刷新信号；还用于接收温度信号，以调整所述预设值，所述温度信号表征的温度越高，调整后的所述预设值越大；
    行寻址器，用于接收所述行地址刷新信号，并输出待刷新的单行地址；
    阵列刷新装置，用于根据所述单行地址进行单行刷新操作，且在单行刷新结束后输出单行刷新结束信号。
  2. 根据权利要求1所述的刷新电路，其中，所述刷新控制模块包括：
    控制单元，用于接收所述行地址刷新信号，输出重置信号；还用于对所述行地址刷新信号进行计数，当计数值等于调整后的所述预设值时，输出所述重置信号；
    刷新信号生成单元，用于接收所述刷新命令、所述重置信号以及所述单行刷新结束信号，输出所述行地址刷新信号；当接收到所述刷新命令时，输出所述行地址刷新信号；在接收到所述单行刷新结束信号时，检测所述重置信号，若未接收到所述重置信号，输出所述行地址刷新信号，若接收到所述重置信号，中止输出所述行地址刷新信号。
  3. 根据权利要求2所述的刷新电路，其中，所述控制单元包括：
    计数子单元，用于接收所述行地址刷新信号，并对接收到的所述行地址刷新信号进行计数，输出所述计数值；
    调节子单元，用于接收所述温度信号和所述计数值，输出激励信号；用于根据所述温度信号调整所述预设值，当所述计数值等于调整后的所述预设值时，输出所述激励信号；
    自动脉冲生成器，用于接收所述激励信号并输出所述重置信号。
  4. 根据权利要求3所述的刷新电路，其中，所述计数子单元包括由多个D触发器串联组成的异步二进制加法计数器，所述调节子单元包括或门和多个与门，所述与门的至少一输入端连接所述异步二进制加法计 数器的计数端，所述与门的输出端连接所述或门的输入端，所述或门的输出端作为所述调节子单元的输出端；
    至少一所述与门的所有输入端连接所述计数端，当所述计数端的电平表征默认数值时，至少一所述与门输出高电平；
    至少另一所述与门的一个输入端接收所述温度信号，且所述计数端的电平表征第一数值时，至少另一所述与门输出高电平，所述第一数值小于所述默认数值。
  5. 根据权利要求4所述的刷新电路，其中，所述异步二进制加法计数器包括作为低位的第一计数端、作为次高位的第二计数端以及作为高位的第三计数端；所述调节子单元包括第一与门、第二与门、第三与门以及第四与门；
    所述第一与门的第一输入端与所述第一计数端连接，第二输入端与所述第二计数端连接，第三输入端与所述第三计数端连接；
    所述第二与门的第一输入端用于接收第一温度信号，第二输入端与所述第二计数端连接，第三输入端与所述第三计数端连接；
    所述第三与门的第一输入端与所述第一计数端连接，第二输入端用于接收第二温度信号，第三输入端与所述第三计数端连接；
    所述第四与门的第一输入端与所述第一计数端连接，第二输入端与所述第二计数端连接，第三输入端用于接收第三温度信号；
    其中，所述第三温度信号表征当前温度小于等于第三温度，所述第二温度信号表征当前温度小于等于第二温度且大于所述第三温度，所述第一温度信号表征当前温度小于等于第一温度且大于所述第二温度。
  6. 根据权利要求5所述的刷新电路，其中，所述第一温度信号表征的温度区间极差与所述第二温度信号表征的温度区间极差相等。
  7. 根据权利要求6所述的刷新电路，其中，所述第一温度信号表征的温度区间极差为20℃～50℃。
  8. 根据权利要求5所述的刷新电路，其中，相邻所述温度信号对应的所述预设值不同，差值为1～3行。
  9. 根据权利要求2所述的刷新电路，其中，所述刷新信号生成单元包括：
    第一或非门，用于接收所述刷新命令和所述单行刷新结束信号；
    刷新窗口生成单元，用于接收所述刷新命令、所述单行刷新结束信号以及所述重置信号，输出刷新窗口信号；当接收到所述刷新命令时，输出所述刷新窗口信号；用于在接收到所述单行刷新结束信号时，检测所述重置信号，若未接收到所述重置信号，输出所述刷新窗口信号，若接收到所述重置信号，中止输出所述刷新窗口信号；
    第二或非门，用于接收所述第一或非门的输出信号和所述刷新窗口信号，输出所述行地址刷新信号。
  10. 根据权利要求2所述的刷新电路，其中，所述刷新命令为高电平有效的脉冲信号，所述单行刷新结束信号为高电平有效的脉冲信号；所述刷新窗口信号为低电平有效的窗口信号。
  11. 根据权利要求10所述的刷新电路，其中，所述重置信号为高电平有效的脉冲信号。
  12. 根据权利要求1所述的刷新电路，其中，还包括：开关单元，所述开关单元导通时，所述刷新控制模块可根据所述温度信号调整所述预设值，所述开关单元断开时，所述预设值为默认数值。
  13. 根据权利要求12所述的刷新电路，其中，所述开关单元包括熔丝单元，所述刷新控制模块通过所述熔丝单元接收所述温度信号。
  14. 根据权利要求1所述的刷新电路，其中，还包括：温度传感器，用于检测目标芯片的温度并输出所述温度信号。
  15. 一种存储器，包含权利要求1至14中任一项所述的刷新电路。
PCT/CN2021/109273 2021-01-29 2021-07-29 刷新电路及存储器 Ceased WO2022160631A1 (zh)

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