WO2022160885A1 - 薄膜晶体管、存储器及制作方法、电子设备 - Google Patents

薄膜晶体管、存储器及制作方法、电子设备 Download PDF

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Publication number
WO2022160885A1
WO2022160885A1 PCT/CN2021/131913 CN2021131913W WO2022160885A1 WO 2022160885 A1 WO2022160885 A1 WO 2022160885A1 CN 2021131913 W CN2021131913 W CN 2021131913W WO 2022160885 A1 WO2022160885 A1 WO 2022160885A1
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Prior art keywords
electrode
thin film
film transistor
gate
dielectric layer
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PCT/CN2021/131913
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English (en)
French (fr)
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景蔚亮
黄凯亮
冯君校
王正波
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to KR1020237026616A priority Critical patent/KR102813663B1/ko
Priority to JP2023544700A priority patent/JP7639152B2/ja
Priority to KR1020257016876A priority patent/KR20250079053A/ko
Priority to EP21922475.5A priority patent/EP4261907A4/en
Publication of WO2022160885A1 publication Critical patent/WO2022160885A1/zh
Priority to US18/358,434 priority patent/US20230371229A1/en
Anticipated expiration legal-status Critical
Priority to JP2025024781A priority patent/JP2025083352A/ja
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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    • H10D64/00—Electrodes of devices having potential barriers
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
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Definitions

  • the present application relates to the technical field of memory, and in particular, to a thin film transistor, a memory, a manufacturing method, and an electronic device.
  • TFTs thin film transistors
  • TFTs have the advantages of low leakage current, low growth temperature, and high mobility
  • thin film transistors have been widely used in various devices such as memories.
  • the structure of the existing thin film transistor is shown in FIG. 1 .
  • the thin film transistor 10 includes a semiconductor layer (also referred to as an active layer) 102 disposed on a substrate 101 , a semiconductor layer 102 disposed on the semiconductor layer 102 and in contact with the semiconductor layer 102 .
  • the semiconductor layer 102 of the existing thin film transistor 10 is spread along a plane parallel to the gate electrode 106 , and the source electrode 103 and the drain electrode 104 are located on the same layer, the size of the thin film transistor 10 is large and the area utilization rate is low.
  • the source electrode 103 and the drain electrode 104 are located on the same layer, the signal line electrically connected to the source electrode 103 and the signal line electrically connected to the drain electrode 104 are prone to short circuit during wiring, which is not conducive to wiring and increases the difficulty of the process .
  • Embodiments of the present application provide a thin film transistor, a memory, a manufacturing method, and an electronic device, which can reduce the size of the thin film transistor, improve area utilization, and reduce wiring difficulty.
  • a thin film transistor in a first aspect, includes a gate electrode, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer.
  • the gate comprises a gate substrate located at the top and a gate column extending from the gate substrate to the bottom; the first pole is located at the bottom; the second pole is located between the first pole and the gate substrate; the first dielectric layer is arranged on the second pole Between the first electrode and the first electrode, the first dielectric layer is used to separate the first electrode and the second electrode; the semiconductor layer is arranged along the side surface of the gate column, and the second dielectric layer separates the semiconductor layer from the gate electrode.
  • the first electrode and the second electrode are electrically connected to the semiconductor layer, respectively.
  • the semiconductor layer is disposed along a plane parallel to the gate electrode (the gate electrode in the prior art is equivalent to the gate substrate in the embodiment of the present application), and the second electrode and the first electrode are placed in the same layer.
  • the semiconductor layer is arranged along the side surface of the gate column, the first electrode is located at the bottom, the second electrode is located between the first electrode and the gate substrate, and the first electrode and the second electrode are respectively electrically connected to the semiconductor layer. Therefore, the thin film transistor provided by the embodiment of the present application has a smaller size on a plane parallel to the gate substrate, so the embodiment of the present application reduces the size of the thin film transistor and improves the area utilization rate.
  • the second electrode and the first electrode of the thin film transistor in the embodiments of the present application are located at different layers, it is possible to avoid short circuit between the signal line electrically connected to the second electrode and the signal line electrically connected to the first electrode during wiring , reducing the difficulty of the process.
  • the second pole is arranged close to the gate substrate. In this way, it can be avoided that the first pole and the second pole are directly conductive when the first pole and the second pole are fabricated.
  • the boundary of the projection of the gate pillar on the gate substrate is located within the boundary of the gate substrate.
  • the gate pillar is disposed in the middle region of the gate substrate.
  • the boundary of the projection of the gate pillar on the gate substrate partially overlaps the boundary of the gate substrate.
  • the gate pillars are disposed at the edge region of the gate substrate.
  • the gate pillar is a hollow structure; the outer boundary of the projection of the gate pillar on the gate substrate overlaps with the boundary of the gate substrate. Since the gate column is a hollow structure, the second dielectric layer, the semiconductor layer, the second electrode, the first dielectric layer and the like can be arranged in the hollow structure.
  • the semiconductor layer further includes an extension extending along the surface of the gate substrate. In this way, the area of the semiconductor layer can be increased, thereby increasing the area where the semiconductor layer is electrically connected to the second electrode, thereby improving the switching rate of the thin film transistor.
  • the semiconductor layer further includes an extension between the gate pillar and the first electrode. In this way, the area of the semiconductor layer can be increased, thereby increasing the area where the semiconductor layer is electrically connected to the first electrode, thereby improving the switching rate of the thin film transistor.
  • the semiconductor layer is arranged in a circle around the side surface of the gate pillar. In this way, the area of the semiconductor layer can be increased, and the switching rate of the thin film transistor can be improved.
  • the semiconductor layer surrounds the entire side surface of the gate pillar.
  • the second pole is arranged on a side of the semiconductor layer away from the second dielectric layer.
  • the second pole is arranged between the semiconductor layer and the second dielectric layer.
  • the material of the second dielectric layer is a ferroelectric material; the thin film transistor further includes: a third dielectric layer disposed between the semiconductor layer and the second dielectric layer.
  • the gate electrode, the second dielectric layer and the third dielectric layer can form a compound gate structure.
  • the thin film transistor can achieve the performance of a negative capacitance transistor, and the gate control capability of the thin film transistor can be improved by using the negative capacitance.
  • the performance of the memory can be improved.
  • the thin film transistor further includes: a first conductive layer disposed between the second dielectric layer and the third dielectric layer.
  • the compound gate structure composed of the gate electrode, the second dielectric layer, the first conductive layer and the third dielectric layer can make the thin film transistor realize the performance of a negative capacitance transistor, and the gate control capability of the thin film transistor can be improved by using the negative capacitance.
  • the performance of the memory can be improved.
  • the thin film transistor further includes: a fourth dielectric layer disposed between the second electrode and the semiconductor layer; and/or a fifth dielectric layer disposed between the first electrode and the semiconductor layer.
  • a fourth dielectric layer disposed between the second pole and the semiconductor layer
  • a fifth dielectric layer disposed between the first electrode and the semiconductor layer. Disposing the fourth dielectric layer between the second pole and the semiconductor layer can avoid the problem of diffusion of the second pole in the contact area with the semiconductor layer, and reduce the problem of Fermi level pinning in the contact between the second pole and the semiconductor layer.
  • Disposing the fifth dielectric layer between the first electrode and the semiconductor layer can avoid the diffusion problem of the first electrode in the contact area with the semiconductor layer, and reduce the Fermi level pinning problem in the contact between the first electrode and the semiconductor layer.
  • the thicknesses of the fourth dielectric layer and the fifth dielectric layer are both in the range of 0.1 nm ⁇ 2 nm. In this way, it can be ensured that when a voltage is provided on the gate, the second electrode and the first electrode can be conducted through the semiconductor layer, and the performance of the thin film transistor will not be affected.
  • the thin film transistor further includes: a modulation gate electrode disposed between the first electrode and the second electrode, and the modulation gate electrode is disposed on a side of the semiconductor layer away from the gate column, and the modulation gate electrode is formed by The first dielectric layer surrounds and is spaced apart from the first pole, the second pole and the semiconductor layer.
  • the threshold voltage of the thin film transistor can be adjusted by modulating the gate electrode.
  • the first electrode is the drain electrode and the second electrode is the source electrode; or, the first electrode is the source electrode and the second electrode is the drain electrode.
  • a memory in a second aspect, includes at least one layer of memory arrays disposed on a substrate; each layer of memory arrays includes a plurality of memory cells, write word lines, write bit lines, read word lines and read bits distributed in the array
  • the memory unit includes a second thin film transistor and a first thin film transistor arranged in layers; the gate of the second thin film transistor is electrically connected to the write word line, and the second pole is electrically connected to the write bit line; the second pole of the first thin film transistor and the The first electrode is electrically connected to the read word line and the read bit line respectively; the second thin film transistor and the first thin film transistor are the above-mentioned thin film transistors; wherein, the first electrode of the second thin film transistor is close to the gate of the first thin film transistor, and The first electrode of the second thin film transistor is electrically connected to the gate electrode of the first thin film transistor. Since the second thin film transistor and the first thin film transistor in the memory are the above-mentioned thin film transistors, the second thin film transistor and the first thin
  • the memory unit further includes a connection electrode disposed between the first thin film transistor and the second thin film transistor; the gate electrode of the first thin film transistor and the first electrode of the second thin film transistor are electrically connected through the connection electrode. connected.
  • the gates of the second thin film transistors in the plurality of memory cells arranged in sequence along the first direction in each layer of the memory array are electrically connected to the same write word line;
  • the second electrodes of the second thin film transistors in the plurality of memory cells arranged in sequence are electrically connected to the same write bit line; wherein the first direction and the second direction intersect. Since the gates of the second thin film transistors in the plurality of memory cells arranged in sequence along the first direction in each layer of the memory array are electrically connected to the same write word line, the second thin film transistors in the plurality of memory cells arranged in sequence along the second direction are electrically connected to the same write word line.
  • the second pole of the transistor is electrically connected to the same writing bit line, so during the writing operation, the first switching signal can be provided to multiple writing word lines row by row, so that the second thin film transistors of multiple rows are turned on row by row.
  • the write word line of the row provides the first switch signal
  • the logic information is simultaneously written to the plurality of memory cells electrically connected to the write word line of the current row through the plurality of write bit lines, so that the logic information can be written to the memory cells row by row. , in order to realize the fast writing of multiple storage units in the storage array.
  • the second electrodes of the first thin film transistors in the plurality of memory cells arranged in sequence along the first direction in each layer of the memory array are electrically connected to the same read bit line;
  • the first electrodes of the first thin film transistors in the plurality of memory cells arranged in sequence in the second direction are electrically connected to the same read word line;
  • the second pole of a thin film transistor is electrically connected to the same read word line;
  • the first pole of the first thin film transistor in the plurality of memory cells arranged in sequence along the second direction in each layer of the memory array is electrically connected to the same read bit line
  • the second poles of the first thin film transistors in the plurality of memory cells arranged in sequence along the second direction in each layer of the storage array are electrically connected to the same read bit line;
  • the first electrodes of the first thin film transistors in the plurality of memory cells are electrically connected to the same read word line;
  • the electrode is electrically connected to the same read word line;
  • a third level signal can be provided to a plurality of read word lines row by row.
  • the read word line of the current row provides the third level signal, by detecting the current on each read bit line, so that The logical information stored in the multiple memory cells electrically connected to the read word line of the current row can be read out at the same time, so that the logical information stored in the memory cells can be read row by row, so that the multiple memory cells in the storage array can be read out. Fast read.
  • the first direction and the second direction are orthogonal.
  • the first thin film transistor further includes a first modulation gate electrode disposed between the first electrode and the second electrode, and the first modulation gate electrode is disposed on a side of the semiconductor layer away from the gate column , the first modulation gate electrode is surrounded by the first dielectric layer of the first thin film transistor, so as to be spaced apart from the second electrode, the first electrode and the semiconductor layer; the first modulation gate electrodes of a plurality of first thin film transistors located in the same layer and/or, the second thin film transistor further includes a second modulation gate electrode disposed between the first electrode and the second electrode, and the second modulation gate electrode is disposed on the side of the semiconductor layer away from the gate column , the second modulation gate electrode is surrounded by the first dielectric layer of the second thin film transistor, so as to be spaced apart from the second electrode, the first electrode and the semiconductor layer; the second modulation gate electrodes of a plurality of second thin film transistors located in the same layer electrically connected together.
  • the threshold voltage of the first thin film transistor can be adjusted through the first modulation gate electrode.
  • the first modulation gate electrodes of the plurality of first thin film transistors are electrically connected together to realize common modulation of the plurality of first thin film transistors.
  • the second thin film transistor includes the second modulation gate electrode, the threshold voltage of the second thin film transistor can be adjusted through the second modulation gate electrode.
  • the second modulation gate electrodes of the plurality of second thin film transistors are electrically connected together to realize common modulation of the plurality of second thin film transistors. Based on this, the storage performance of the memory can be adjusted more flexibly.
  • the memory further includes an integrated circuit; the storage array is arranged on the integrated circuit.
  • the memory is on-chip memory.
  • the memory cells are electrically connected to the integrated circuit. This allows the memory cells to be controlled by the integrated circuit.
  • an electronic device in a third aspect, includes a circuit board and a memory electrically connected to the circuit board, where the memory is the above-mentioned memory.
  • the electronic device has the same technical effects as the foregoing embodiments, which will not be repeated here.
  • a method for fabricating a thin film transistor includes: first, forming a first electrode, a first dielectric layer, a second electrode and a semiconductor layer on a substrate; wherein the first electrode, The first dielectric layer and the second electrode are stacked in sequence, and the first dielectric layer separates the first electrode and the second electrode; the semiconductor layer is formed on the side of the first dielectric layer; the second electrode and the first electrode are electrically connected to the semiconductor layer.
  • the gate includes a gate substrate at the top and a gate pillar extending from the gate substrate to the bottom, and the second dielectric layer connects the gate with the semiconductor layer, the first electrode and the gate Diodes are separated.
  • the fabrication method of the thin film transistor has the same technical effect as the foregoing embodiment, and details are not described herein again.
  • the first electrode is formed as the drain electrode, and the second electrode is formed as the source electrode; or, the first electrode is formed as the source electrode, and the second electrode is formed as the drain electrode.
  • forming the first electrode, the first dielectric layer, the second electrode and the semiconductor layer on the substrate includes: first, forming a stacked first conductive film and a first dielectric film on the substrate in sequence and the second conductive film; then, pattern the first conductive film, the first dielectric film and the second conductive film to form the first pole, the first dielectric layer and the second pole stacked in sequence; and a side surface of the second pole to form a semiconductor layer.
  • forming the first electrode, the first dielectric layer, the second electrode and the semiconductor layer on the substrate includes: first, forming a first conductive film and a third dielectric layer stacked in sequence on the substrate film; next, a modulation gate electrode is formed on the third dielectric film; next, a fourth dielectric film is formed; wherein, the fourth dielectric film surrounds the modulation gate electrode; next, a second conductive film is formed on the fourth dielectric film film; next, the first conductive film is patterned to form the first pole, the fourth dielectric film and the third dielectric film are patterned to form the first dielectric layer, and the second conductive film is patterned to form the second pole; The side surfaces of the first dielectric layer and the second pole form a semiconductor layer.
  • the threshold voltage of the thin film transistor can be adjusted by modulating the gate electrode.
  • forming the first electrode, the first dielectric layer, the second electrode and the semiconductor layer on the substrate includes: first, forming a first conductive film and a first dielectric film stacked in sequence on the substrate ; Next, pattern the first conductive film and the first dielectric film to form a first electrode and a first dielectric layer stacked in sequence; Next, a semiconductor layer is formed on the side of the first dielectric layer; A second pole is formed on the dielectric layer.
  • the material of the second dielectric layer is a ferroelectric material; after forming the semiconductor layer and before forming the second dielectric layer, the above-mentioned manufacturing method further includes: forming a third dielectric layer; the third dielectric layer formed on the side of the first dielectric layer.
  • the third dielectric layer has the same technical effect as the above-mentioned embodiment, which is not repeated here.
  • the above-mentioned manufacturing method further includes: forming a first conductive layer; the first conductive layer is formed on the side surface of the first dielectric layer.
  • the first conductive layer has the same technical effect as the above-mentioned embodiment, which is not repeated here.
  • the above-mentioned manufacturing method further includes: forming a fifth dielectric layer; wherein, the fifth dielectric layer is in contact with the first pole and the semiconductor layer, respectively.
  • the diffusion problem of the first electrode in the contact area with the semiconductor layer can be avoided, and the Fermi level pinning problem in the contact between the first electrode and the semiconductor layer can be reduced.
  • the above-mentioned manufacturing method further includes: forming a fourth dielectric layer; wherein, The fourth dielectric layer is in contact with the second electrode and the semiconductor layer, respectively.
  • a method for fabricating a memory includes forming at least one layer of a storage array on a substrate.
  • a method for fabricating a memory array of any layer comprising: first, forming a plurality of first signal lines arranged in parallel on the substrate; next, forming a plurality of first thin films distributed in an array on the plurality of first signal lines A transistor and a plurality of second signal lines arranged in parallel; the first thin film transistor is manufactured by using the above-mentioned manufacturing method of a thin film transistor; wherein, the first pole of the first thin film transistor is electrically connected to the first signal line, and the first thin film transistor is electrically connected to the first signal line.
  • the second pole is electrically connected to the second signal line; the first signal line is one of the read bit line and the read word line, and the second signal line is the other of the read bit line and the read word line; next , a plurality of second thin film transistors distributed in an array and a plurality of write bit lines arranged in parallel are formed on the first thin film transistor; the second pole of the second thin film transistor is electrically connected to the write bit line; the second thin film transistor adopts the above-mentioned thin film
  • the manufacturing method of the transistor is obtained; wherein, one second thin film transistor corresponds to one first thin film transistor, and the first electrode of the second thin film transistor is electrically connected to the gate of the corresponding first thin film transistor; next, in the second thin film transistor A plurality of writing word lines arranged in parallel are formed on the thin film transistor; the gate electrode of the second thin film transistor is electrically connected to the writing word line. Since both the first thin film transistor and the second thin film transistor in the memory are manufactured by the above-mentioned manufacturing method of the thin
  • the manufacturing method of the memory array in any one layer further includes: forming a plurality of connection electrodes distributed in the array; The first electrodes of the second thin film transistors are electrically connected together by connecting electrodes.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by the prior art
  • Fig. 2a is the structural representation of a storage unit in the memory of 2TOC structure
  • 2b is a schematic structural diagram of a second thin film transistor and a first thin film transistor in a memory cell
  • 2c is a schematic structural diagram of a second thin film transistor and a first thin film transistor in another memory cell
  • FIG. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a memory according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a storage array according to an embodiment of the present application.
  • FIG. 6a is a schematic structural diagram of a storage array according to another embodiment of the present application.
  • FIG. 6b is a schematic cross-sectional view in the first direction in FIG. 6a;
  • FIG. 6c is a schematic cross-sectional view in the second direction in FIG. 6a;
  • Figure 6d is a schematic cross-sectional view taken along the AA direction in Figure 6b or Figure 6c;
  • Figure 6e is another schematic cross-sectional view of Figure 6b or Figure 6c in the direction AA;
  • FIG. 7 is a schematic structural diagram of a memory according to another embodiment of the present application.
  • FIG. 8a is a schematic structural diagram of a thin film transistor provided by an embodiment of the present application.
  • Fig. 8b is a schematic cross-sectional view of Fig. 8a in the direction of BB;
  • Fig. 8c is another schematic cross-sectional view of Fig. 8a in the direction of BB;
  • FIG. 9 is a schematic structural diagram of a thin film transistor according to another embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a thin film transistor according to another embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a thin film transistor according to still another embodiment of the present application.
  • 12a is a schematic structural diagram of a thin film transistor according to another embodiment of the present application.
  • 12b is a schematic structural diagram of a thin film transistor according to another embodiment of the present application.
  • 12c is a schematic structural diagram of a thin film transistor according to still another embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a thin film transistor according to another embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a thin film transistor according to another embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a thin film transistor according to still another embodiment of the present application.
  • 16 is a schematic structural diagram of a thin film transistor according to another embodiment of the present application.
  • FIG. 17a is a schematic structural diagram of a storage array according to another embodiment of the present application.
  • Figure 17b is a schematic cross-sectional view taken along the CC direction in Figure 17a;
  • Figure 17c is another schematic cross-sectional view taken along the CC direction in Figure 17a;
  • FIG. 18 is a schematic flowchart of a method for fabricating a thin film transistor provided by an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of a preparation process of a thin film transistor provided by an embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of another manufacturing process of a thin film transistor provided by an embodiment of the present application.
  • 21 is a schematic structural diagram of another thin film transistor fabrication process provided by an embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of another thin film transistor fabrication process provided by an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of another thin film transistor fabrication process provided by an embodiment of the present application.
  • FIG. 24 is a schematic structural diagram of another thin film transistor fabrication process provided by an embodiment of the present application.
  • FIG. 25 is a schematic structural diagram of another thin film transistor fabrication process provided by an embodiment of the present application.
  • FIG. 26 is a schematic structural diagram of another thin film transistor fabrication process provided by an embodiment of the present application.
  • FIG. 27 is a schematic structural diagram of another thin film transistor fabrication process provided by an embodiment of the present application.
  • FIG. 28 is a schematic structural diagram of another thin film transistor fabrication process provided by an embodiment of the present application.
  • FIG. 29 is a schematic structural diagram of another thin film transistor fabrication process provided by an embodiment of the present application.
  • FIG. 30 is a schematic flowchart of a method for manufacturing a memory according to an embodiment of the present application.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated; It can also be indirectly connected through an intermediary.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • coupled can mean that two or more components are in direct physical or electrical contact, or it can mean that two or more components are not in direct contact with each other, but are electrically connected or interacted through an intermediary .
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • gain cell memories are widely used, and their main target application scenarios are high-speed and high-density memories.
  • the gain cell memory with 2TOC structure can achieve nanosecond read and write speed and millisecond storage time.
  • the storage time refers to the time that the information stored in the memory is kept, that is, the time from writing to the correct reading of the stored information.
  • the gain cell memory of the 2T0C structure needs to be constantly refreshed in practical applications, which brings about a large dynamic power consumption.
  • the gain cell memory of the 2T0C structure can be prepared based on TFT at present.
  • the advantage of ultra-low leakage of TFT can be used to greatly improve the retention time of the memory of 2TOC structure and reduce the dynamic power consumption; , three-dimensional) memory integration to improve storage density.
  • FIG. 2a is a schematic structural diagram of a memory cell in a memory with a 2TOC structure
  • the memory cell includes a first thin film transistor Tr0 and a second thin film transistor Tr1
  • the gate of the second thin film transistor Tr1 is electrically connected to the write word line WWL
  • the source The electrode is electrically connected to the write bit line WBL
  • the drain is electrically connected to the gate of the first thin film transistor Tr0
  • the source of the first thin film transistor Tr0 is electrically connected to the read word line RWL
  • the drain is electrically connected to the read bit line RBL.
  • FIG. 2b and 2c are respectively a schematic structural diagram of a first thin film transistor Tr0 and a second thin film transistor Tr1 in a memory cell of a memory with a TFT-based 2TOC structure.
  • the first thin film transistor Tr0 and the second thin film transistor Tr1 each include a semiconductor layer 102 disposed on a substrate 101, a source electrode 103 and a drain electrode 103 disposed on the semiconductor layer 102 and in contact with the semiconductor layer 102
  • the signal lines are electrically connected to the corresponding electrodes through vias, for example, the read word line RWL is connected to the first through vias.
  • the source electrode 103 of the thin film transistor Tr0 is electrically connected.
  • the semiconductor layers 102 in the first thin film transistor Tr0 and the second thin film transistor Tr1 shown in FIG. 2b and FIG. 2c are both spread along the plane parallel to the gate electrode 106, and the source electrode 103 and the drain electrode 104 are arranged in the same As a result, the sizes of the first thin film transistor Tr0 and the second thin film transistor Tr1 are large, and the area utilization rate of the first thin film transistor Tr0 and the second thin film transistor Tr1 is low.
  • the source electrode 103 and the drain electrode 104 are located on the same layer, the signal line electrically connected to the source electrode 103 and the signal line electrically connected to the drain electrode 104 are prone to short circuit, which is not conducive to wiring and increases the difficulty of the process.
  • an embodiment of the present application provides a memory, which can be applied to an electronic device.
  • the electronic device may be a cell phone, tablet computer, desktop computer, laptop computer, handheld computer, notebook computer, ultra-mobile personal computer (UMPC), netbook, as well as cellular phones, personal digital assistants (personal digital assistants) digital assistant (PDA), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, wearable devices, in-vehicle devices, smart home devices and/or Smart city equipment, the embodiments of the present application do not specifically limit the specific type of the electronic equipment.
  • FIG. 3 shows a schematic structural diagram of an electronic device.
  • the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2 , mobile communication module 150, wireless communication module 160, audio module 170, sensor module 180, key 190, motor 191, indicator 192, camera 193, display screen 194, and user identification module (subscriber identification module, SIM) card interface 195 Wait.
  • SIM subscriber identification module
  • the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 100 .
  • the electronic device 100 may include more or less components than shown, or combine some components, or separate some components, or arrange different components.
  • the illustrated components may be implemented in hardware, software, or a combination of software and hardware.
  • the processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (neural-network processing unit, NPU), etc. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • application processor application processor, AP
  • modem processor graphics processor
  • ISP image signal processor
  • controller video codec
  • digital signal processor digital signal processor
  • baseband processor baseband processor
  • neural-network processing unit neural-network processing unit
  • the controller can generate an operation control signal according to the instruction operation code and timing signal, and complete the control of fetching and executing instructions.
  • a memory may also be provided in the processor 110 for storing instructions and data.
  • the memory in processor 110 is cache memory.
  • the memory may hold instructions or data that have just been used or recycled by the processor 110 . If the processor 110 needs to use the instruction or data again, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby increasing the efficiency of the system.
  • the processor 110 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transceiver (universal asynchronous transmitter) receiver/transmitter, UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, and / or universal serial bus (universal serial bus, USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART universal asynchronous transceiver
  • MIPI mobile industry processor interface
  • GPIO general-purpose input/output
  • SIM subscriber identity module
  • USB universal serial bus
  • the I2C interface is a bidirectional synchronous serial bus that includes a serial data line (SDA) and a serial clock line (SCL).
  • SDA serial data line
  • SCL serial clock line
  • the I2S interface can be used for audio communication.
  • the PCM interface can also be used for audio communications, sampling, quantizing and encoding analog signals.
  • the UART interface is a universal serial data bus used for asynchronous communication.
  • the bus may be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication.
  • the MIPI interface can be used to connect the processor 110 with peripheral devices such as the display screen 194 and the camera 193 .
  • MIPI interfaces include camera serial interface (CSI), display serial interface (DSI), etc.
  • the GPIO interface can be configured by software.
  • the GPIO interface can be configured as a control signal or as a data signal.
  • the GPIO interface can also be configured as I2C interface, I2S interface, UART interface, MIPI interface, etc.
  • the USB interface 130 is an interface that conforms to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, and the like.
  • the USB interface 130 can be used to connect a charger to charge the electronic device 100, and can also be used to transmit data between the electronic device 100 and peripheral devices. It can also be used to connect headphones, play audio through headphones, etc.
  • the interface connection relationship between the modules illustrated in the embodiment of the present invention is only a schematic illustration, and does not constitute a structural limitation of the electronic device 100 .
  • the electronic device 100 may also adopt different interface connection manners in the foregoing embodiments, or a combination of multiple interface connection manners.
  • the charging management module 140 is used to receive charging input from the charger.
  • the charger may be a wireless charger or a wired charger.
  • the power management module 141 is used for connecting the battery 142 , the charging management module 140 and the processor 110 .
  • the power management module 141 receives input from the battery 142 and/or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160.
  • the power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle times, battery health status (leakage, impedance).
  • the power management module 141 may also be provided in the processor 110 .
  • the power management module 141 and the charging management module 140 may also be provided in the same device.
  • the wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modulation and demodulation processor, the baseband processor, and the like.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in electronic device 100 may be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization.
  • the antenna 1 can be multiplexed as a diversity antenna of the wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.
  • the mobile communication module 150 may provide wireless communication solutions including 2G/3G/4G/5G etc. applied on the electronic device 100 .
  • the mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), and the like.
  • the mobile communication module 150 can receive electromagnetic waves from the antenna 1, filter and amplify the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation.
  • the mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and then turn it into an electromagnetic wave for radiation through the antenna 1 .
  • the modem processor may include a modulator and a demodulator.
  • the modulator is used to modulate the low frequency baseband signal to be sent into a medium and high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low frequency baseband signal. Then the demodulator transmits the demodulated low-frequency baseband signal to the baseband processor for processing.
  • the low frequency baseband signal is processed by the baseband processor and passed to the application processor.
  • the application processor outputs sound signals through audio devices (not limited to speakers, receivers, etc.), or displays images or videos through the display screen 194 .
  • the wireless communication module 160 can provide applications on the electronic device 100 including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), global navigation satellites Wireless communication solutions such as global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared technology (IR).
  • WLAN wireless local area networks
  • BT Bluetooth
  • GNSS global navigation satellite system
  • FM frequency modulation
  • NFC near field communication
  • IR infrared technology
  • the wireless communication module 160 may be one or more devices integrating at least one communication processing module.
  • the wireless communication module 160 receives electromagnetic waves via the antenna 2 , frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110 .
  • the wireless communication module 160 can also receive the signal to be sent from the processor 110 , perform frequency modulation on it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2 .
  • the antenna 1 of the electronic device 100 is electrically connected to the mobile communication module 150, and the antenna 2 is electrically connected to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology can include global system for mobile communications (GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA) and the like.
  • the electronic device 100 implements a display function through a GPU, a display screen 194, an application processor, and the like.
  • the GPU is a microprocessor for image processing, and is connected to the display screen 194 and the application processor.
  • the GPU is used to perform mathematical and geometric calculations for graphics rendering.
  • Processor 110 may include one or more GPUs that execute program instructions to generate or alter display information.
  • Display screen 194 is used to display images, videos, and the like.
  • the electronic device 100 may include one or N display screens 194 , where N is a positive integer greater than one.
  • the electronic device 100 may implement a shooting function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, an application processor, and the like.
  • the ISP is used to process the data fed back by the camera 193 .
  • Camera 193 is used to capture still images or video.
  • the electronic device 100 may include 1 or N cameras 193 , where N is a positive integer greater than 1.
  • the external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100 .
  • the external memory card communicates with the processor 110 through the external memory interface 120 to realize the data storage function. For example to save files like music, video etc in external memory card.
  • Internal memory 121 may be used to store computer executable program code, which includes instructions.
  • the internal memory 121 may include a storage program area and a storage data area.
  • the storage program area can store an operating system, an application program required for at least one function (such as a sound playback function, an image playback function, etc.), and the like.
  • the storage data area may store data (such as audio data, phone book, etc.) created during the use of the electronic device 100 and the like.
  • the internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, universal flash storage (UFS), and the like.
  • the processor 110 executes various functional applications and data processing of the electronic device 100 by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.
  • the electronic device 100 may implement the audio function through the audio module 170 and the application processor and the like. Such as music playback, recording, etc.
  • the audio module 170 is used for converting digital audio information into analog audio signal output, and also for converting analog audio input into digital audio signal. Audio module 170 may also be used to encode and decode audio signals.
  • the keys 190 include a power-on key, a volume key, and the like. Keys 190 may be mechanical keys. It can also be a touch key.
  • the electronic device 100 may receive key inputs and generate key signal inputs related to user settings and function control of the electronic device 100 .
  • Motor 191 can generate vibrating cues.
  • the motor 191 can be used for vibrating alerts for incoming calls, and can also be used for touch vibration feedback.
  • the indicator 192 can be an indicator light, which can be used to indicate the charging state, the change of the power, and can also be used to indicate a message, a missed call, a notification, and the like.
  • the SIM card interface 195 is used to connect a SIM card.
  • the SIM card can be contacted and separated from the electronic device 100 by inserting into the SIM card interface 195 or pulling out from the SIM card interface 195 .
  • the electronic device 100 may support 1 or N SIM card interfaces, where N is a positive integer greater than 1.
  • the aforementioned electronic device 100 may further include a circuit board, such as a printed circuit board (printed circuit board, PCB).
  • a circuit board such as a printed circuit board (printed circuit board, PCB).
  • the above-mentioned processor 110, internal memory 121, etc. can be provided on the circuit board, and the processor 110, the internal memory 121, etc. are electrically connected to the circuit board.
  • the memory provided in this embodiment of the present application may be used as the internal memory 121 in the electronic device 100 described above, and may also be used as the memory in the processor 110 of the electronic device 100 described above.
  • the memory provided by the embodiments of the present application may be an off-chip memory or an on-chip memory (also referred to as an embedded memory).
  • the memory provided by the embodiment of the present application may be a memory prepared based on a BEOL (back end of line, back end) process.
  • BEOL back end of line, back end
  • the memory 200 includes at least one layer of memory array 201 disposed on the substrate 101 .
  • FIG. 4 takes the memory 200 including the two-layer memory array 201 as an example for illustration.
  • the memory arrays 201 may be sequentially stacked in a vertical direction.
  • the memory 200 may also be referred to as a three-dimensional integrated memory.
  • the number of layers of the storage arrays 201 can be stacked as required, and the more layers of the stacked storage arrays 201 are, the higher the storage density of the memory 200 is.
  • the memory 200 includes a multi-layer storage array 201
  • the memory 200 further includes a sixth medium layer 202 disposed between two adjacent layers of storage arrays 201, and the two adjacent layers of storage The arrays 201 are separated by a sixth dielectric layer 202 .
  • the material of the sixth dielectric layer 202 may be SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2 (hafnium dioxide), ZrO 2 (zirconia), TiO 2 (titanium dioxide), Y One or more of insulating materials such as 2 O 3 (yttrium trioxide) and Si 3 N 4 (silicon nitride).
  • the sixth dielectric layer 202 may have a single-layer structure or a multi-layer stack structure.
  • the material of the single-layer structure and the material of each layer in the multi-layer stack structure may be SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , Si 3 N 4 one or more of.
  • each layer of memory array 201 includes a plurality of memory cells 201A distributed in the array, a write word line WWL (write word line), a write bit line WBL (write bit line), and a read word line RWL (read word line) And the read bit line RBL (read bit line).
  • WWL write word line
  • WBL write bit line
  • RWL read word line
  • the memory cell 201A includes a first thin film transistor Tr0 and a second thin film transistor Tr1 which are provided in layers.
  • the first thin film transistor Tr0 includes a gate electrode 106a including a gate substrate 1061a at the top and a gate pillar 1062a extending from the gate substrate 1061a to the bottom.
  • the first thin film transistor Tr0 further includes a first electrode 109a, a second electrode 108a, a first dielectric layer 113a, a second dielectric layer 112a and a semiconductor layer 102a, the first electrode 109a is located at the bottom, and the second electrode 108a is located at the first electrode 109a and the semiconductor layer 102a.
  • the first dielectric layer 113a is disposed between the second electrode 108a and the first electrode 109a, and the first dielectric layer 113a is used to separate the first electrode 109a and the second electrode 108a; the semiconductor layer 102a is along the gate The side of the pole 1062a is disposed, and the second dielectric layer 112a separates the semiconductor layer 102a from the gate 106a; wherein, the first pole 109a and the second pole 108a are respectively electrically connected to the semiconductor layer 102a.
  • the second dielectric layer 112a covers the surface of the gate substrate 1061a and the surface of the gate pillar 1062a; further, the second dielectric layer 112a surrounds the first electrode 109a on the Outside the gate pillar 1062a, the semiconductor layer 102a surrounds the outside of the second dielectric layer 112a, and the second electrode 108a is disposed outside the semiconductor layer 102a and is electrically connected to the semiconductor layer 102a, the second electrode 108a is on the first electrode 109a and two They are separated by a first dielectric layer 113a, and the first electrode 109a is electrically connected to the semiconductor layer 102a.
  • the second thin film transistor Tr1 includes a gate electrode 106b including a gate substrate 1061b at the top and a gate pillar 1062b extending from the gate substrate 1061b to the bottom.
  • the second thin film transistor Tr1 further includes a first electrode 109b, a second electrode 108b, a first dielectric layer 113b, a second dielectric layer 112b and a semiconductor layer 102b; the first electrode 109b is located at the bottom, and the second electrode 108b is located at the first electrode 109a and Between the gate substrates 1061a; the first dielectric layer 113b is disposed between the second electrode 108b and the first electrode 109b, and the first dielectric layer 113b is used to separate the first electrode 109b and the second electrode 108b; the second dielectric layer 112b Cover the surface of the gate substrate 1061b and the surface of the gate pillar 1062b; the semiconductor layer 102b is disposed along the side of the gate pillar 1062b, and the second dielectric layer 112b
  • the second dielectric layer 112b surrounds the gate pillar 1062b on the first electrode 109b
  • the semiconductor layer 102b surrounds the second dielectric layer 112b
  • the second electrode 108b is disposed on the outside of the semiconductor layer 102b and is electrically connected to the semiconductor layer 102b.
  • the second electrode 108b is on the first electrode 109b and is separated by a first dielectric layer 113b.
  • the first electrode 109b is electrically connected to the semiconductor layer 102b.
  • the gate 106b (gate, G) of the second thin film transistor Tr1 is electrically connected to the write word line WWL, the second electrode 108b is electrically connected to the write bit line WBL; the first electrode 109a and the second electrode 108a of the first thin film transistor Tr0 They are respectively electrically connected to the read word line RWL and the read bit line RBL; the first electrode 109b of the second thin film transistor Tr1 is close to the gate 106a of the first thin film transistor Tr0, and the first electrode 109b of the second thin film transistor Tr1 is connected to the first thin film transistor Tr1.
  • the gate 106a of the transistor Tr0 is electrically connected.
  • FIG. 6b is a schematic cross-sectional view of the first direction X in FIG. 6a
  • FIG. 6c is a cross-sectional schematic view of the second direction Y in FIG. 6a
  • the memory 200 provided by the embodiment of the present application is a memory of a gain cell structure based on a 2TOC structure.
  • the first electrode 109b of the second thin film transistor Tr1 is in direct contact with the gate electrode 106a of the first thin film transistor Tr0.
  • the first electrode 109b of the second thin film transistor Tr1 and the gate electrode 106a of the first thin film transistor Tr0 are both in contact with the connection electrode 111, and the second thin film transistor Tr1
  • the first electrode 109b and the gate electrode 106a of the first thin film transistor Tr0 are electrically connected together through the connection electrode 111 .
  • the above-mentioned second thin film transistor Tr1 is a writing transistor
  • the first thin film transistor Tr0 is a reading transistor
  • the structures of the second thin film transistor Tr1 and the first thin film transistor Tr0 may be the same or different. It should be understood that, in some embodiments, the projection of the second thin film transistor Tr1 on the substrate overlaps the projection of the first thin film transistor Tr0 on the substrate.
  • the write word line WWL can be fabricated in synchronization with the gate electrode 106b of the second thin film transistor Tr1, and the write bit line WBL can be fabricated in synchronization with the second electrode 108b of the second thin film transistor Tr1.
  • the second electrode 108a of the first thin film transistor Tr0 may be electrically connected to the read word line RWL, and the first electrode 109a may be electrically connected to the read bit line RBL, in this case, the second electrode 108a of the first thin film transistor Tr0 And the read word line RWL can be fabricated synchronously, the first pole 109a of the first thin film transistor Tr0 and the read bit line RBL can be fabricated simultaneously; it can also be that the second pole 108a of the first thin film transistor Tr0 is electrically connected to the read bit line RBL, the first One pole 109a is electrically connected to the read word line RWL. In this case, the second pole 108a of the first thin film transistor Tr0 and the read bit line RBL can be fabricated simultaneously. The first pole 109a of the first thin film transistor Tr0 is connected to the read word line RWL. Can be made synchronously.
  • the second electrode 108a may be the source electrode (source, S) 103, the first electrode 109a may be the drain electrode (drain, D) 104, or the second electrode 108a may be the source electrode (source, S) 103
  • the electrode 108 a is the drain electrode 104
  • the first electrode 109 a is the source electrode 103
  • the second electrode 108b may be the source electrode 103
  • the first electrode 109b may be the drain electrode 104
  • the second electrode 108b may be the drain electrode 104
  • the first electrode 109b may be the source electrode 103.
  • first thin film transistor Tr0 and second thin film transistor Tr1 may be both N-type transistors or P-type transistors.
  • one of the first thin film transistor Tr0 and the second thin film transistor Tr1 may be N-type pipe, the other is P-type pipe.
  • the plurality of first thin film transistors Tr0 included in each layer of the memory array 201 may be fabricated simultaneously; and/or, the plurality of second thin film transistors Tr1 included in each layer of the memory array 201 may be fabricated simultaneously.
  • a write operation process and a read operation process of the memory 200 are described below by taking a storage unit 201A as an example.
  • the write operation process During the write operation, the voltages of the read word line RWL and the read bit line RBL are 0, and the first thin film transistor Tr0 does not work; the write word line WWL provides a first switch signal, and the first switch signal controls the second thin film transistor Tr1 is turned on.
  • the first logic information for example, the first logic information is "0"
  • the write bit line WBL provides a first level signal, and the first level signal is written into the node N through the second thin film transistor Tr1;
  • the level signal can control the first thin film transistor Tr0 to be turned on.
  • the write bit line WBL provides a second level signal, and the second level signal is written into the node N through the second thin film transistor Tr1;
  • the level signal can control the first thin film transistor Tr0 to be turned off.
  • the write word line WWL provides a second switch signal, and the second switch signal controls the second thin film transistor Tr1 is turned off, at this time, the potential stored in the node N is not affected by the outside world.
  • the read operation process the write word line WWL provides a second switch signal, and the second switch signal controls the second thin film transistor Tr1 to turn off; the read word line RWL provides a third level signal, and the memory cell 201A is determined according to the level of the current on the read bit line RBL The stored logical information.
  • the node N stores the first level signal, since the first level signal can control the first thin film transistor Tr0 to be turned on, when the read word line RWL provides the third level signal, the read word line RWL passes through the first thin film The transistor Tr0 charges the read bit line RBL, and the voltage on the read bit line RBL increases.
  • the memory cell 201A stores the logic information "" 0".
  • the second level signal is stored in the node N, since the second level signal can control the first thin film transistor Tr0 to be turned off, when the read word line RWL provides the third level signal, the read word line RWL will not pass through the third level signal.
  • a thin film transistor Tr0 charges the read bit line RBL, and the read bit line RBL maintains a voltage of 0V. In this way, when it is detected that the current on the read bit line RBL is small, it can be read that the logic information stored in the memory cell 201A is "1". .
  • the second thin film transistors in the plurality of memory cells 201A sequentially arranged along the first direction X in each layer of the memory array 201
  • the gate 106b of Tr1 is electrically connected to the same write word line WWL; with reference to FIG. 5 , FIG. 6 a and FIG. 6 c , the second thin film transistors Tr1 in the plurality of memory cells 201A arranged in sequence along the second direction Y in each layer of the memory array 201A
  • the second pole 108b is electrically connected to the same write bit line WBL; wherein, the first direction X and the second direction Y intersect.
  • first direction X and the second direction Y are orthogonal.
  • first direction X is taken as the row direction
  • second direction Y is taken as the column direction as an example.
  • the plurality of The second pole 108b of the second thin film transistor Tr1 in the memory cell 201A is electrically connected to the same write bit line WBL, so during the write operation, the first switch signal can be provided to the plurality of write word lines WWL row by row, so that the The second thin film transistor Tr1 of the row is turned on row by row, and when the write word line WWL of the current row provides the first switching signal, the plurality of memory cells 201A electrically connected to the write word line WWL of the current row are provided through the plurality of write bit lines WBL.
  • the logic information is written at the same time, so that the logic information can be written to the storage unit 201A row by row, so as to realize the fast writing of the multiple storage units 201A in the storage array 201 .
  • the plurality of first thin film transistors Tr0 can be connected in the following four ways by way of example.
  • first electrode 109a of the first thin film transistor Tr0 is electrically connected to the read bit line RBL
  • second electrode 108a is electrically connected to the read word line RWL
  • the second pole 108a of the first thin film transistor Tr0 in the plurality of memory cells 201A arranged in sequence along the first direction X in the memory array 201 of each layer is the same as the second pole 108a of the first thin film transistor Tr0.
  • the word line RWL is electrically connected; with reference to FIG. 5, FIG. 6a and FIG. 6c, the first pole 109a of the first thin film transistor Tr0 in the plurality of memory cells 201A arranged in sequence along the second direction Y in the memory array 201 of each layer is the same as the first pole 109a of the first thin film transistor Tr0.
  • the read bit line RBL is electrically connected; wherein the first direction X and the second direction Y intersect.
  • the second electrodes 108a of the first thin film transistors Tr0 in the plurality of memory cells 201A arranged in sequence along the first direction X in each layer of the memory array 201 are electrically connected to the same read word line RWL, the second electrodes 108a arranged in sequence along the second direction Y
  • the first poles 109a of the first thin film transistors Tr0 in the plurality of memory cells 201A are electrically connected to the same read bit line RBL, so during the read operation, a third level signal can be provided to the plurality of read word lines RWL row by row, Under the condition that the read word line RWL of the current row provides the third level signal, by detecting the current on each read bit line RBL, a plurality of storage devices electrically connected to the read word line RWL of the current row can be simultaneously read out.
  • the logical information stored in the unit 201A can be read row by row, so that the multiple storage units 201A in the storage array 201 can be quickly read.
  • the first electrodes 109a of the first thin film transistors Tr0 in the plurality of memory cells 201A arranged in sequence along the first direction X in 201 are electrically connected to the same read bit line RBL; wherein the first direction X and the second direction Y intersect.
  • the following third or fourth method may be used.
  • the second pole 108a of the first thin film transistor Tr0 in the plurality of memory cells 201A arranged in sequence along the first direction X in each layer of the memory array 201 is electrically connected to the same read bit line RWL; each layer of the memory array
  • the first electrodes 109a of the first thin film transistors Tr0 in the plurality of memory cells 201A arranged in sequence along the second direction Y in 201 are electrically connected to the same read word line RWL; wherein the first direction X and the second direction Y intersect.
  • the second pole 108a of the first thin film transistor Tr0 in the plurality of memory cells 201A arranged in sequence along the second direction Y in each layer of the memory array 201 is electrically connected to the same read bit line RWL; each layer of the memory array
  • the first electrodes 109a of the first thin film transistors Tr0 in the plurality of memory cells 201A arranged in sequence along the first direction X in 201 are electrically connected to the same read word line RWL; wherein the first direction X and the second direction Y intersect.
  • the number of storage cells 201A can be increased along the first direction X and/or the second direction Y to realize a larger-scale storage array.
  • the memory 200 further includes an integrated circuit 203 ; the memory array 201 is disposed on the integrated circuit 203 .
  • the memory 200 is an on-chip memory.
  • the substrate in memory 200 is integrated circuit 203 .
  • the substrate of the integrated circuit 203 may be a silicon substrate, that is, the integrated circuit 203 may be an integrated circuit of a silicon substrate.
  • the above-mentioned integrated circuit 203 may be a control circuit of the memory array 201, or may be other functional circuits.
  • the memory array 201 can be integrated in the back-end of the integrated circuit 203 . Furthermore, stacking of multi-layered memory arrays 201 can be implemented on integrated circuits 203 to enable 3D system integration.
  • memory cells 201A in memory array 201 may be electrically connected to integrated circuit 203 .
  • the memory cells 201A in the memory array 201 may be connected to the underlying integrated circuit 203 through interconnect lines.
  • the embodiment of the present application further provides a thin film transistor 10, which can be used as the above-mentioned first thin film transistor Tr0 and can also be used as the above-mentioned second thin film transistor Tr1.
  • the structure of the thin film transistor 10 will be described in detail below.
  • the thin film transistor 10 includes a gate electrode 106 , a first electrode 109 , a second electrode 108 , a first dielectric layer 113 , a second dielectric layer 112 and a semiconductor layer 102 .
  • the gate 106 includes a gate substrate 1061 located at the top and a gate pillar 1062 extending from the gate substrate 1061 to the bottom; the first electrode 109 is located at the bottom; the second electrode 108 is located between the first electrode 109 and the gate substrate 1061; A dielectric layer 113 is disposed between the second pole 108 and the first pole 109, and the first dielectric layer 113 is used to separate the first pole 109 and the second pole 108; the second dielectric layer 112 covers the surface of the gate substrate 1061 and the The surface of the gate pillar 1062 ; the semiconductor layer 102 is disposed along the side surface of the gate pillar 1062 , and the second dielectric layer 112 separates the semiconductor layer 102 from the gate electrode 106 .
  • the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102, respectively.
  • FIG. 8b is a schematic cross-sectional view along the BB direction in FIG. 8a;
  • FIG. 8c is another schematic cross-sectional view along the BB direction in FIG. 8a.
  • the second dielectric layer 112 surrounds the gate pillar 1062 on the first electrode 109
  • the semiconductor layer 102 surrounds the second dielectric layer 112
  • the second electrode 108 is disposed outside the semiconductor layer 102 , and is electrically connected to the semiconductor layer 102
  • the second electrode 108 is on the first electrode 109 and separated by the first dielectric layer 113
  • the first electrode 109 is electrically connected to the semiconductor layer 102 .
  • the gate pillar 1062 includes a surface in contact with the gate substrate 1061, a surface away from the gate substrate 1061, and a side surface. The surface in contact with the gate substrate 1061 and the surface away from the gate substrate 1061 are disposed opposite to each other.
  • the gate pillar 1062 and the gate substrate 1061 are integrally formed. In other embodiments, the gate pillar 1062 and the gate substrate 1061 are separately fabricated.
  • the gate pillars 1062 are disposed perpendicular to the gate substrate 1061 .
  • the first electrode 109 forms an ohmic contact with the semiconductor layer 102
  • the second electrode 108 forms an ohmic contact with the semiconductor layer 102
  • the first electrode 109 is electrically connected to the semiconductor layer 102, which may be in direct contact with the semiconductor layer 102, or the first electrode 109 and the semiconductor layer 102 are not in direct contact, but are electrically connected through other media.
  • the second electrode 108 is electrically connected to the semiconductor layer 102, which may be in direct contact with the semiconductor layer 102, or the second electrode 108 is not in direct contact with the semiconductor layer 102, but is electrically connected through other media.
  • first electrode 109 in the thin film transistor 10 may be the drain electrode and the second electrode 108 may be the source electrode, or the first electrode 109 in the thin film transistor 10 may be the source electrode and the second electrode 108 may be the drain electrode pole.
  • the thin film transistor 10 may be an N-type transistor or a P-type transistor.
  • the second dielectric layer 112 covers the surface of the gate substrate 1061a and the surface of the gate pillar 1062, as shown in FIG. 8a, the second dielectric layer 112 includes a first dielectric part 1121 and a second dielectric part 1122, the first dielectric The portion 1121 covers the surface of the gate substrate 1061 , and the second dielectric portion 1122 covers the surface of the gate pillar 1062 .
  • the first media portion 1121 and the second media portion 1122 are fabricated simultaneously. In other embodiments, the first medium portion 1121 and the second medium portion 1122 may be separately fabricated.
  • the second electrode 108 is disposed close to the gate substrate 1061 .
  • the above-mentioned materials of the gate electrode 106 , the first electrode 109 and the second electrode 108 are all conductive materials, such as metal materials.
  • the materials of the gate electrode 106, the first electrode 109 and the second electrode 108 may be TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti -
  • conductive materials such as O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).
  • first dielectric layer 113 and the material of the second dielectric layer 112 For the material of the first dielectric layer 113 and the material of the second dielectric layer 112, reference may be made to the material of the sixth dielectric layer 202, which will not be repeated here.
  • the first dielectric layer 113 and the second dielectric layer 112 may have a single-layer structure or a multi-layer stack structure.
  • the material of the semiconductor layer 102 can be Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc)
  • semiconductor materials such as oxide) multicomponent compounds, ZnO (zinc oxide), ITO, TiO 2 (titanium dioxide), MoS 2 (molybdenum disulfide) and the like.
  • An embodiment of the present application provides a thin film transistor 10.
  • the gate electrode 106 of the thin film transistor 10 includes a gate substrate 1061 at the top and a gate pillar 1062 extending from the gate substrate 1061 to the bottom. Since the semiconductor layer 102 is along the side of the gate pillar 1062 is arranged, and the first electrode 109 is located at the bottom, the second electrode 108 is located between the first electrode 109 and the gate substrate 1061, and the first electrode 109 and the second electrode 108 are respectively electrically connected to the semiconductor layer 102.
  • the semiconductor layer 102 is arranged along a plane parallel to the gate 106 (the gate 106 in the prior art is equivalent to the gate substrate 1061 in the embodiment of the present application), and the second electrode 108 and the first electrode 109 are arranged in the same layer.
  • the thin film transistor 10 provided by the embodiment of the application has a smaller size on a plane parallel to the gate substrate 1061 , so the embodiment of the present application reduces the size of the thin film transistor 10 and improves the area utilization rate.
  • the second electrode 108 and the first electrode 109 of the thin film transistor 10 in the embodiment of the present application are located in different layers, the signal line electrically connected to the second electrode 108 and the signal line electrically connected to the first electrode 109 can be avoided A short circuit occurs during wiring, which reduces the difficulty of the process.
  • the size of the first thin film transistor Tr0 and the second thin film transistor Tr1 in the memory 200 can be reduced, and the area utilization rate can be improved.
  • the first type As shown in FIG. 8a, FIG. 9, FIG. 10, and FIG. 11, the boundary of the projection of the gate pillar 1062 on the gate substrate 1061 is located within the boundary of the gate substrate 1061, that is, the gate pillar 1062 is arranged on the gate substrate 1061. the middle area.
  • the second type As shown in FIGS. 12 a and 12 c , the boundary of the projection of the gate pillar 1062 on the gate substrate 1061 partially overlaps with the boundary of the gate substrate 1061 , that is, the gate pillar 1062 is disposed in the edge region of the gate substrate 1061 .
  • the third type as shown in FIG. 12 b , the gate pillar 1062 is a hollow structure; the outer boundary of the projection of the gate pillar 1062 on the gate substrate 1061 overlaps with the boundary of the gate substrate 11061 .
  • the projection of the gate pillar 1062 on the gate substrate 1061 includes two boundaries, namely an outer boundary and an inner boundary.
  • the boundary near the center of the gate substrate 1061 is called an inner boundary, and the boundary far from the center of the gate substrate 10161 is called an outer boundary.
  • the gate pillar 1062 is a hollow structure, and the outer boundary of the projection of the gate pillar 1062 on the gate substrate 1061 overlaps with the boundary of the gate substrate 11061, at least part of the second dielectric layer 112 is located in the hollow structure, and the semiconductor At least a partial area of the layer 102 is located within the hollow structure, the second pole 108 is located within the hollow structure, and at least a partial area of the first dielectric layer 113 is located within the hollow structure.
  • the gate 106 regulates the current in the semiconductor layer 102 from the outside of the semiconductor layer 102 .
  • the first type as shown in FIG. 8 a , the semiconductor layer 102 is only disposed along the side surface of the gate pillar 1062 .
  • the semiconductor layer 102 only surrounds the side surface of the gate pillar 1062 and is disposed on the first electrode 109 .
  • the second electrode 108 , the first electrode 109 and the semiconductor layer 102 are terminally connected or in contact with each other.
  • the second type As shown in FIG. 12 c , the semiconductor layer 102 is disposed along the side surface of the gate pillar 1062 , and the semiconductor layer 102 further includes an extension extending along the surface of the gate substrate 1061 .
  • the second dielectric layer 112 separates the semiconductor layer 102 from the gate 106 .
  • the semiconductor layer 102 is disposed on the side surfaces of the first dielectric layer 113 and the second pole 108 and covers the top surface of the second pole 108 .
  • the semiconductor layer 102 is also provided on the side of the first pole 109 .
  • the semiconductor layer 102 is disposed along the side of the gate pillar 1062 , and the semiconductor layer 102 extends from the side of the gate pillar 1062 to the side of the gate pillar 1062 away from the gate substrate 1061 , that is, located at the gate Between the electrode pillar 1062 and the first electrode 109 , that is, the semiconductor layer 102 further includes an extension portion located between the gate pillar 1062 and the first electrode 109 .
  • the semiconductor layer 102 covers the surfaces of the side and bottom of the second dielectric layer 112 .
  • the semiconductor layer 102 is disposed on the first pole 109 .
  • the semiconductor layer 102 is disposed along the side surface of the gate pillar 1062 , and the semiconductor layer 102 further includes an extension extending along the surface of the gate substrate 1061 and an extension located in the gate column 1061 .
  • the semiconductor layer 102 has a "Z" shape. It can also be said that, as shown in FIG. 10 , FIG. 12 a and FIG. 12 b , the semiconductor layer 102 covers the side surface, the bottom surface and the top surface of the second dielectric layer 112 . Alternatively, as shown in FIG. 11 , the semiconductor layer 102 covers the side surfaces and the bottom surface of the second dielectric layer 112 and also covers the bottom surface of the second pole 108 .
  • the semiconductor layer 102 is disposed on the first pole 109 .
  • the semiconductor layer 102 is disposed in a circle around the side of the gate pillar 1062 .
  • the semiconductor layer 102 may surround the entire side surface of the gate pillar 1062 ; it may also be a part of the side surface of the gate pillar 1062 surrounded by the semiconductor layer 102 .
  • the semiconductor layer 102 is arranged around the side surface of the gate pillar 1062, the area of the semiconductor layer 102 can be increased, and the mobility of carriers can be improved.
  • the second pole 108 is disposed on the semiconductor layer 102 away from the second dielectric layer 112. side.
  • the second electrode 108 is disposed on the side of the semiconductor layer 102 away from the second dielectric layer 112, as shown in FIGS. 10 and 12a. As shown in FIG. 12 b , the second electrode 108 is not in contact with the second dielectric layer 112 , and is separated by the semiconductor layer 102 therebetween. In the case where the semiconductor layer 102 is provided along the side surface of the gate pillar 1062, and the semiconductor layer 102 does not include an extension extending along the surface of the gate substrate 1061, as shown in FIG. 8a and FIG. 9, the second electrode 108 is provided on the semiconductor layer When the 102 is away from the side of the second dielectric layer 112 , the second pole 108 is in contact with the second dielectric layer 112 .
  • the second electrode 108 is disposed on the side of the semiconductor layer 102 close to the second dielectric layer 112 . In this case, the second electrode 108 is located between the second dielectric layer 112 and the semiconductor layer 102 .
  • the second electrode 108 can be arranged around the side of the gate pillar 1062 in a circle, and the second electrode 108 can also be arranged around the side of the gate pillar 1062, but not a complete circle.
  • the first electrode 109 is located at the bottom, that is, the first electrode 109 is disposed on the side of the second electrode 108 away from the gate substrate 1061.
  • the first electrode 109 may be as shown in FIG. 8a, FIG. 9, and FIG. 10. 11 , 12 a and 12 b , the first electrode 109 is disposed on the side of the gate pillar 1062 away from the gate substrate 1061 .
  • the semiconductor layer 102 is provided on the first pole 109 .
  • the first electrode 109 is disposed on the side of the gate pillar 1062 .
  • the semiconductor layer 102 may also extend along the side surface of the first pole 109 .
  • the above-mentioned thin film transistor 10 further includes: a fourth dielectric layer 114 disposed between the second electrode 108 and the semiconductor layer 102 ; and/or a fourth dielectric layer 114 disposed between the first electrode 109 and the semiconductor layer 102 ; Fifth dielectric layer 115 between layers 102 .
  • the fourth dielectric layer 114 and the material of the fifth dielectric layer 115 may have a single-layer structure or a multi-layer stack structure.
  • the fourth dielectric layer 114 is disposed between the second electrode 108 and the semiconductor layer 102 , and the second electrode 108 and the semiconductor layer 102 may or may not be in contact.
  • the fifth dielectric layer 115 is disposed between the first electrode 109 and the semiconductor layer 102, and the first electrode 109 and the semiconductor layer 102 may or may not be in contact.
  • the fourth dielectric layer 114 and the fifth dielectric layer 115 The thickness ranges from 0.1 nm to 2 nm.
  • the thicknesses of the fourth dielectric layer 114 and the fifth dielectric layer 115 may be 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, and the like.
  • the thicknesses of the fourth dielectric layer 114 and the fifth dielectric layer 115 are relatively small, and the thickness ranges from 0.1 nm to 2 nm, even if the fourth dielectric layer 114 is disposed between the second electrode 108 and the semiconductor layer 102, and/or the first The five dielectric layers 115 are disposed between the first electrode 109 and the semiconductor layer 102.
  • the first electrode 109 and the second electrode 108 can still be conducted through the semiconductor layer 102 without affecting the thin film transistor. 10 performance.
  • disposing the fourth dielectric layer 114 between the second electrode 108 and the semiconductor layer 102 can avoid the diffusion problem of the second electrode 108 in the contact area with the semiconductor layer 102 and reduce the Fermi contact between the second electrode 108 and the semiconductor layer 102 Energy level pinning problem.
  • Disposing the fifth dielectric layer 115 between the first electrode 109 and the semiconductor layer 102 can avoid the diffusion problem of the first electrode 109 in the contact area with the semiconductor layer 102 and reduce the Fermi level of the contact between the first electrode 109 and the semiconductor layer 102 pinning problem.
  • the material of the second dielectric layer 112 is a ferroelectric material; in this case, as shown in FIG. 14 , the thin film transistor 10 further includes: disposed between the semiconductor layer 102 and the second dielectric layer 112 the third dielectric layer 116 .
  • the third dielectric layer 116 may have a single-layer structure or a multi-layer stack structure.
  • the gate 106 , the second dielectric layer 112 and the third dielectric layer 116 form a composite gate structure, through which the thin film transistor 10
  • the performance of the negative capacitance transistor can be achieved, and the gate control capability of the thin film transistor 10 can be improved by using the negative capacitance.
  • the performance of the memory 200 can be improved.
  • the materials of the first dielectric layer 113 , the second dielectric layer 112 , the third dielectric layer 116 , the fourth dielectric layer 114 and the fifth dielectric layer 115 may be the same or different.
  • the thin film transistor 10 when the material of the second dielectric layer 112 is a ferroelectric material and the thin film transistor 10 includes the third dielectric layer 116 , as shown in FIG. 15 , the thin film transistor 10 further includes: and the first conductive layer 117 between the third dielectric layer 116 .
  • the materials of the first conductive layer 117 may refer to the above-mentioned materials of the gate 106 , the first electrode 109 and the second electrode 108 , which will not be repeated here.
  • the compound gate structure formed by the gate 106 , the second dielectric layer 112 , the first conductive layer 117 and the third dielectric layer 116 can make the thin film transistor 10 realize the performance of a negative capacitance transistor, and the negative capacitance can improve the performance of the thin film transistor 10 gate control capability.
  • the performance of the memory 200 can be improved.
  • the above-mentioned thin film transistor 10 further includes: a modulation gate electrode 118 disposed between the first electrode 109 and the second electrode 108 , and the modulation gate electrode 118 is surrounded by the first dielectric layer 113 .
  • the material of the modulation gate electrode 118 reference may be made to the above-mentioned materials of the gate electrode 106, the first electrode 109 and the second electrode 108, which will not be repeated here.
  • the modulation gate electrode 118 is surrounded by the first dielectric layer 113 so as to be spaced apart from the first electrode 109 , the second electrode 108 and the semiconductor layer 102 , that is, the modulation gate electrode 118 is connected to the first electrode through the first dielectric layer 113 109, the second electrode 108 and the semiconductor layer 102 are electrically isolated.
  • the threshold voltage of the thin film transistor 10 can be adjusted by the modulation gate electrode 118 .
  • the first thin film transistor Tr0 further includes setting The first modulation gate electrode 118a between the first electrode 109a and the second electrode 108a, and the first modulation gate electrode 118a is disposed on the side of the semiconductor layer 102a away from the gate pillar 1062a, and the first modulation gate electrode 118a is formed by the first modulation gate electrode 118a.
  • the dielectric layer 113a is surrounded so as to be spaced apart from the first electrode 109a, the second electrode 108a and the semiconductor layer 102a; the first modulation gate electrodes 118a of the plurality of first thin film transistors Tr0 located in the same layer are electrically connected together; and/or,
  • the second thin film transistor Tr1 further includes a second modulation gate electrode 118b disposed between the first electrode 109b and the second electrode 108b, and the second modulation gate electrode 118b is disposed on the side of the semiconductor layer 102b away from the gate pillar 1062b.
  • the two modulation gate electrodes 118b are surrounded by the first dielectric layer 113b, so as to be spaced apart from the first electrode 109b, the second electrode 108b and the semiconductor layer 102b; the second modulation gate electrodes 118b of the plurality of second thin film transistors Tr1 located in the same layer are electrically connected.
  • FIG. 17b and FIG. 17c are schematic cross-sectional views along the CC direction in FIG. 17a.
  • the first modulation gate electrodes 118a of the plurality of first thin film transistors Tr0 located in the same layer are electrically connected together, and all the first modulation gate electrodes 118a of the plurality of first thin film transistors Tr0 located in the same layer may be electrically connected to each other. At the same time, some of the first modulation gate electrodes 118a of the plurality of first thin film transistors Tr0 located in the same layer may be electrically connected together.
  • the second modulation gate electrodes 118b of the plurality of second thin film transistors Tr1 located in the same layer are electrically connected together, and the second modulation gate electrodes 118b of the plurality of second thin film transistors Tr1 located in the same layer may be all electrically connected to At the same time, some of the second modulation gate electrodes 118b of the plurality of second thin film transistors Tr1 located in the same layer may be electrically connected together.
  • the first modulation gate electrodes 118a in the four first thin film transistors Tr0 located in the same layer are electrically connected together, so that the common modulation of the four memory cells 201A can be realized.
  • the number of common modulations of the storage units 201A may be selected as required.
  • the material of the first modulation gate electrode 118a and the material of the second modulation gate electrode 118b may refer to the above-mentioned materials of the gate electrode 106, the first electrode 109 and the second electrode 108, which will not be repeated here.
  • the threshold voltage of the first thin film transistor Tr0 can be adjusted through the first modulation gate electrode 118a. Since the second thin film transistor Tr1 includes the second modulation gate electrode 118b, the threshold voltage of the second thin film transistor Tr1 can be adjusted through the second modulation gate electrode 118b. Based on this, the storage performance of the memory 200 can be adjusted more flexibly. Illustratively, for the first thin film transistor Tr0, the potential of the first modulation gate electrode 118a can be set lower, so that the leakage current of the first electrode 109a and the second electrode 108a of the first thin film transistor Tr0 is reduced, so as to achieve a longer Storage hold time. In addition, the potential of the second modulation gate electrode 118b in the second thin film transistor Tr1 can be set higher, so that the overall current of the second thin film transistor Tr1 increases, and the data reading speed is improved.
  • the embodiments of the present application further provide a method for fabricating the thin film transistor 10 , which can be used to fabricate the above-mentioned thin film transistor 10 .
  • the fabrication method of the thin film transistor 10 includes:
  • the first electrode 109 , the first dielectric layer 113 , the second electrode 108 and the semiconductor layer 102 are stacked in sequence, and the first dielectric layer 113 separates the first electrode 109 and the second electrode 108 ; the semiconductor layer 102 is formed on the first dielectric layer 113 side; the first pole 109 and the second pole 108 are both electrically connected to the semiconductor layer 102 .
  • the formation order of the first electrode 109 , the first dielectric layer 113 , the second electrode 108 and the semiconductor layer 102 is not limited.
  • both the first electrode 109 and the second electrode 108 may be in direct contact with the semiconductor layer 102; or the first electrode 109 and the second electrode 108 may be in contact with the semiconductor layer 102 through other dielectric layers, respectively.
  • the materials of the first electrode 109 , the first dielectric layer 113 , the second electrode 108 and the semiconductor layer 102 reference may be made to the above-mentioned embodiments, and details are not repeated here.
  • the first dielectric layer 113 includes a surface close to the second pole 108 , a surface close to the first pole 109 and a side surface, wherein the surface close to the second pole 108 and the surface close to the first pole 109 are oppositely disposed.
  • the first electrode 109 may be formed as the drain electrode, and the second electrode 108 may be formed as the source electrode; or the first electrode 109 may be formed as the source electrode, and the second electrode 1081 may be formed as the drain electrode.
  • the gate electrode 106 includes a gate substrate 1061 on the top and a gate pillar 1062 extending from the gate substrate 1061 to the bottom, and the second dielectric layer 112 connects the gate electrode 106 with the semiconductor layer 102.
  • the first pole 109 and the second pole 108 are spaced apart.
  • gate substrate 1061 and the gate pillar 1062 may be formed simultaneously, or the gate substrate 1061 and the gate pillar 1062 may be formed separately.
  • steps S10 and S11 may be performed in sequence, or steps S11 and S10 may be performed in sequence.
  • An embodiment of the present application provides a method for fabricating a thin film transistor 10 . Since the method for fabricating a thin film transistor 10 provided by an embodiment of the present application has the same technical effect as the above-mentioned thin film transistor 10 , reference can be made to the above, and details are not repeated here.
  • manufacturing the thin film transistor 10 shown in FIG. 8a specifically includes the following steps:
  • a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .
  • the first conductive film 1090 , the first dielectric film 1130 and the second conductive film 1080 may be sequentially formed by chemical vapor deposition, physical vapor deposition, sputtering, electroplating and other methods.
  • first conductive film 1090, the first dielectric film 1130 and the second conductive film 1080 may be patterned by dry etching or wet etching.
  • first conductive film 1090, the first dielectric film 1130 and the second conductive film 1080 can be etched separately, or the first conductive film 1090, the first dielectric film 1130 and the second conductive film 1080 can be etched simultaneously eclipse.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the sidewall of the groove structure, that is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the second electrode 108; Both the diodes 108 are electrically connected to the semiconductor layer 102 .
  • an epitaxial growth method can be used to form a semiconductor thin film, the semiconductor thin film is a whole layer, covering the exposed surfaces of the first pole 109, the first dielectric layer 113 and the second pole 108; and then the semiconductor thin film is etched, except for forming In addition to the semiconductor thin film on the sidewall of the groove, the semiconductor thin film formed on other parts such as the bottom of the groove, the top surface of the second electrode 108 and the outside of the groove are etched away, thereby forming the semiconductor layer 102 .
  • the above-mentioned epitaxial growth methods include, for example, chemical vapor deposition, physical vapor deposition, sputtering, electroplating and other processes.
  • a second dielectric layer 112 is formed; the second dielectric layer 112 covers the semiconductor layer 102 , the second pole 108 and the first pole 109 .
  • this step S103 can be implemented in two ways.
  • the second dielectric layer 112 can be directly formed by chemical vapor deposition, physical vapor deposition, sputtering or electroplating. The exposed surfaces of the first pole 109 and the first dielectric layer 113 .
  • the seventh dielectric film covers the semiconductor layer 102 , the second electrode 108 , the first electrode 109 and the first dielectric layer 113 The exposed surface; then the seventh dielectric film is etched, except for the part formed on the side and bottom of the groove, the top surface of the second pole 108 and the top surface of the first semiconductor layer 102, the other seventh dielectric films are is etched away, thereby forming the second dielectric layer 112 .
  • the drawings of the first mode are not shown.
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061; the gate pillar 1062 extends into the groove structure, that is, the gate pillar 1062 extends along the A dielectric layer 113 and the sides of the second electrode 108 extend; the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109, and the second dielectric layer 112 connects the gate 106 with the semiconductor layer 102, the first electrode 109 and the The second pole 108 is spaced apart.
  • the process of forming the gate electrode 106 may specifically be: forming a conductive film first, and then etching the conductive film to form the gate electrode 106 .
  • making the thin film transistor 10 shown in FIG. 9 specifically includes the following steps:
  • a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .
  • step S110 for the specific implementation process of this step S110, reference may be made to the above-mentioned step S100, which will not be repeated here.
  • step S111 for the specific implementation process of this step S111, reference may be made to the foregoing step S101, which will not be repeated here.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure, that is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the second electrode 108, and the semiconductor layer 102 is also It extends from the sides of the first dielectric layer 113 and the second pole 108 to the surface of the first pole 109 close to the second pole 108, that is, the top surface of the first pole 109; the first pole 109 and the second pole 108 are both connected to the semiconductor Layer 102 is electrically connected.
  • an epitaxial growth method can be used to form a semiconductor thin film, the semiconductor thin film is a whole layer, covering the exposed surfaces of the first pole 109, the first dielectric layer 113 and the second pole 108; and then the semiconductor thin film is etched, except for forming Outside the semiconductor thin films on the sidewalls and bottom of the grooves, the semiconductor thin films formed on other parts such as the top surface of the second pole 108 and the outer sides of the grooves are etched away, thereby forming the semiconductor layer 102 .
  • a second dielectric layer 112 is formed; the second dielectric layer 112 covers the semiconductor layer 102 and the second electrode 108 .
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061; the gate pillar 1062 extends into the groove structure, that is, the gate pillar 1062 extends along the first A dielectric layer 113 and the sides of the second electrode 108 extend; the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109, and the second dielectric layer 112 connects the gate 106 with the semiconductor layer 102, the first electrode 109 and the The second pole 108 is spaced apart.
  • making the thin film transistor 10 shown in FIG. 10 specifically includes the following steps:
  • a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .
  • step S120 for the specific implementation process of this step S120, reference may be made to the above-mentioned step S100, which will not be repeated here.
  • step S121 for the specific implementation process of this step S121, reference may be made to the foregoing step S101, which will not be repeated here.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure, and the surface of the second electrode 108 on the side away from the first electrode 109, that is, the semiconductor layer 102 is formed on the first electrode 109.
  • the sides of the dielectric layer 113 and the second pole 108, the semiconductor layer 102 also extends from the sides of the first dielectric layer 113 and the second pole 108 to the surface of the second pole 108 on the side away from the first pole 109 (that is, the side of the second pole 108). top surface) and the surface of the first pole 109 close to the second pole 108 (ie, the top surface of the first pole 109 ); both the first pole 109 and the second pole 108 are electrically connected to the semiconductor layer 102 .
  • an epitaxial growth method can be used to form a semiconductor thin film, the semiconductor thin film is a whole layer, covering the exposed surfaces of the first pole 109, the first dielectric layer 113 and the second pole 108; and then the semiconductor thin film is etched, except for forming Out of the semiconductor thin film on the sidewall, bottom and top surface of the second pole 108 of the groove, the semiconductor thin film formed on the outer side of the groove is etched away, thereby forming the semiconductor layer 102 .
  • a second dielectric layer 112 is formed; the second dielectric layer 112 covers the semiconductor layer 102 .
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061; the gate pillar 1062 extends into the groove structure, that is, the gate pillar 1062 extends along the A dielectric layer 113 and the sides of the second electrode 108 extend; the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109, and the second dielectric layer 112 connects the gate 106 with the semiconductor layer 102, the first electrode 109 and the The second pole 108 is spaced apart.
  • step S124 for the specific implementation process of this step S124, reference may be made to the foregoing step S104, which will not be repeated here.
  • the difference between the first embodiment, the second embodiment and the third embodiment is that the structure of the formed semiconductor layer 102 is different.
  • making the thin film transistor 10 shown in FIG. 13 specifically includes the following steps:
  • a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .
  • step S130 for the specific implementation process of this step S130, reference may be made to the above-mentioned step S100, which will not be repeated here.
  • step S131 for the specific implementation process of this step S131, reference may be made to the foregoing step S101, which will not be repeated here.
  • the fifth dielectric layer 115 is formed at the bottom of the groove structure, that is, the fifth dielectric layer 115 is formed on the top surface of the first pole 109 ; wherein the fifth dielectric layer 115 is in contact with the first pole 109 .
  • the process of forming the fifth dielectric layer 115 may specifically include: firstly forming the fifth dielectric film, and then etching the fifth dielectric film to form the fifth dielectric layer 115 .
  • the fourth dielectric layer 114 is formed on the side of the second pole 108 away from the first pole 109, that is, the fourth dielectric layer 114 is formed on the top surface of the second pole 108; Layer 114 is in contact with second pole 108 .
  • the process of forming the fourth dielectric layer 114 may specifically be: firstly forming the sixth dielectric film, and then etching the sixth dielectric film to form the fourth dielectric layer 114 .
  • step S132 and step S133 may be performed step by step. In this case, step S132 may be performed first, and then step S133 may be performed; or step S133 may be performed first, and then step S132 may be performed. Step S132 and step S133 may also be performed simultaneously, that is, the fourth dielectric layer 114 and the fifth dielectric layer 115 are formed simultaneously.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure, and the surface of the fourth dielectric layer 114 on the side away from the second electrode 108, that is, the semiconductor layer 102 is formed on the first A side of the dielectric layer 113, the second electrode 108 and the fourth dielectric layer 114, the semiconductor layer 102 also extends from the side of the first dielectric layer 113, the second electrode 108 and the fourth dielectric layer 114 to the fourth dielectric layer 114 away from the first dielectric layer 114.
  • the surface on the side of the diode 108 ie the top surface of the fourth dielectric layer 114
  • the surface on the side of the fifth dielectric layer 115 away from the first electrode 109 ie the top surface of the fifth dielectric layer 115
  • the four dielectric layers 114 and the fifth dielectric layer 115 are all in contact with each other, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102 .
  • an epitaxial growth method can be used to form a semiconductor thin film first.
  • the semiconductor thin film is a whole layer, covering the fourth dielectric layer 114 , the fifth dielectric layer 115 , the first electrode 109 , the first dielectric layer 113 and the exposed second electrode 108 .
  • the semiconductor film is etched, except for the semiconductor film formed on the sidewall, bottom and top surface of the fourth dielectric layer 114 of the groove, the semiconductor film formed on the outside of the groove is etched away, thereby forming Semiconductor layer 102 .
  • a second dielectric layer 112 is formed; the second dielectric layer 112 covers the semiconductor layer 102 .
  • step S13 for the specific implementation process of this step S135, reference may be made to the above-mentioned step S103, which will not be repeated here.
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061; the gate pillar 1062 extends into the groove structure, that is, the gate pillar 1062 extends along the A dielectric layer 113 , the second electrode 108 and the fourth dielectric layer 114 extend from the sides; the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109 , and the second dielectric layer 112 connects the gate 106 and the semiconductor layer 102 , the first pole 109 and the second pole 108 are separated.
  • step S136 for the specific implementation process of this step S136, reference may be made to the foregoing step S104, which will not be repeated here.
  • Step S132 and Step S133 are added.
  • step S132 and step S133 are performed, and in some embodiments, one of step S132 and step S133 may also be performed.
  • the structure of the semiconductor layer 102 formed in step S134 is the same as that of the semiconductor layer 102 formed in the third embodiment. In some embodiments, the structure of the semiconductor layer 102 formed in step S134 may also be the same as the structure of the semiconductor layer 102 formed in the first embodiment or the second embodiment.
  • making the thin film transistor 10 shown in FIG. 14 specifically includes the following steps:
  • a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .
  • step S140 for the specific implementation process of this step S140, reference may be made to the above-mentioned step S100, which will not be repeated here.
  • step S141 for the specific implementation process of this step S141, reference may be made to the foregoing step S101, which will not be repeated here.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure, that is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the second electrode 108, and the semiconductor layer 102 is also It extends from the sides of the first dielectric layer 113 and the second pole 108 to the surface of the first pole 109 close to the second pole 108, that is, the top surface of the first pole 1109; the first pole 109 and the second pole 108 are both connected to the semiconductor Layer 102 is electrically connected.
  • step S142 for the specific implementation process of this step S142, reference may be made to the above-mentioned step S112, which will not be repeated here.
  • a third dielectric layer 116 is formed; the third dielectric layer 116 is formed on the sidewalls and the bottom of the groove structure.
  • this step S143 can be implemented in two ways.
  • the third dielectric layer 116 can be directly formed by chemical vapor deposition, physical vapor deposition, sputtering or electroplating. The exposed surfaces of the first pole 109 and the first dielectric layer 113 .
  • chemical vapor deposition, physical vapor deposition, sputtering or electroplating can be used to form an eighth dielectric film, and the eighth dielectric film covers the semiconductor layer 102, the second electrode 108, the first electrode 109 and the first dielectric layer 113. exposed surface; and then etch the eighth dielectric film, except for the part formed on the side and bottom of the groove, the other eighth dielectric films are etched away, thereby forming the third dielectric layer 116 .
  • the second dielectric layer 112 is formed; the second dielectric layer 112 covers the third dielectric layer 116 , the semiconductor layer 102 and the second electrode 108 ; wherein the material of the second dielectric layer 112 is a ferroelectric material.
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061; the gate pillar 1062 extends into the groove structure, that is, the gate pillar 1062 extends along the A dielectric layer 113 and the sides of the second electrode 108 extend; the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109, and the second dielectric layer 112 connects the gate 106 with the semiconductor layer 102, the first electrode 109 and the The second pole 108 is spaced apart.
  • step S145 for the specific implementation process of this step S145, reference may be made to the above-mentioned step S104, which will not be repeated here.
  • step S143 is added in the fifth embodiment.
  • the structure of the semiconductor layer 102 formed in step S142 is the same as that of the semiconductor layer 102 formed in the second embodiment. In some embodiments, the structure of the semiconductor layer 102 formed in step S142 may also be the same as the structure of the semiconductor layer 102 formed in the first embodiment or the third embodiment.
  • making the thin film transistor 10 shown in FIG. 15 specifically includes the following steps:
  • a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .
  • step S150 for the specific implementation process of this step S150, reference may be made to the above-mentioned step S100, which will not be repeated here.
  • step S151 for the specific implementation process of this step S151, reference may be made to the foregoing step S101, which will not be repeated here.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure, that is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the second electrode 108, and the semiconductor layer 102 is also It extends from the sides of the first dielectric layer 113 and the second pole 108 to the surface of the first pole 109 close to the second pole 108, that is, the top surface of the first pole 1109; the first pole 109 and the second pole 108 are both connected to the semiconductor Layer 102 is electrically connected.
  • step S152 for the specific implementation process of this step S152, reference may be made to the foregoing step S112, which will not be repeated here.
  • a third dielectric layer 116 is formed; the third dielectric layer 116 is formed on the sidewalls and the bottom of the groove structure.
  • step S153 for the specific implementation process of this step S153, reference may be made to the above-mentioned step S143, which will not be repeated here.
  • a first conductive layer 117 is formed; the first conductive layer 117 is formed on the sidewalls and the bottom of the groove structure.
  • a fourth conductive film can be formed first, and the fourth conductive film covers the exposed surfaces of the third dielectric layer 116, the semiconductor layer 102, the second electrode 108, the first dielectric layer 113 and the first electrode 109;
  • the thin film is etched, except for the part formed on the side and bottom of the groove, the other fourth conductive thin films are etched away, thereby forming the first conductive layer 117 .
  • the second dielectric layer 112 is formed; the second dielectric layer 112 covers the first conductive layer 117, the second dielectric layer 116, the semiconductor layer 102 and the second pole 108;
  • the material is a ferroelectric material.
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061; the gate pillar 1062 extends into the groove structure, that is, the gate pillar 1062 extends along the A dielectric layer 113 and the sides of the second electrode 108 extend; the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109, and the second dielectric layer 112 connects the gate 106 with the semiconductor layer 102, the first electrode 109 and the The second pole 108 is spaced apart.
  • step S156 for the specific implementation process of this step S156, reference may be made to the above-mentioned step S104, which will not be repeated here.
  • step S154 is added.
  • making the thin film transistor 10 shown in FIG. 12b specifically includes the following steps:
  • a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .
  • step S160 for the specific implementation process of this step S160, reference may be made to the above-mentioned step S100, which will not be repeated here.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 covers the second pole 108 , the exposed surface of the first dielectric layer 113 and the top surface of the first pole 109 , that is, the semiconductor layer 102 covers the second pole 108 The top and side surfaces, the side surfaces of the first dielectric layer 113 , and the top surface of the first pole 109 .
  • an epitaxial growth method can be used to form a semiconductor thin film, the semiconductor thin film is a whole layer, covering the exposed surfaces of the first pole 109, the first dielectric layer 113 and the second pole 108; and then the semiconductor thin film is etched, except for forming Except for the semiconductor thin films on the top and side surfaces of the second pole 108 , the side surfaces of the first dielectric layer 113 and the top surface of the first pole 109 , the semiconductor thin films formed in other parts are etched away, thereby forming the semiconductor layer 102 .
  • a second dielectric layer 112 is formed; the second dielectric layer 112 covers the semiconductor layer 102 .
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061 ; the gate pillar 1062 is arranged around the sides of the first dielectric layer 113 and the second electrode 108
  • the gate pillar 1062 is a hollow structure, the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109, and the second dielectric layer 112 connects the gate 106 with the semiconductor layer 102, the first electrode 109 and the first electrode 109. Diodes 108 are spaced apart.
  • making the thin film transistor shown in FIG. 12a specifically includes the following steps:
  • a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .
  • step S170 for the specific implementation process of this step S170, reference may be made to the foregoing step S100, which will not be repeated here.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the side surfaces of the second electrode 108 and the first dielectric layer 113, and the semiconductor layer 102 also extends from the side surfaces of the second electrode 108 and the first dielectric layer 113 to The top surface of the second pole 108 and the top surface of the first pole 109 .
  • an epitaxial growth method can be used to form a semiconductor thin film, the semiconductor thin film is a whole layer, covering the exposed surfaces of the first pole 109, the first dielectric layer 113 and the second pole 108; and then the semiconductor thin film is etched, except for forming Except for the semiconductor thin films on the left side of the second pole 108 and the first dielectric layer 113, the top surface of the second pole 108 and the top surface of the first pole 109, the semiconductor thin films formed in other parts are etched away, thereby forming Semiconductor layer 102 .
  • the second dielectric layer 112 is formed; the second dielectric layer 112 covers the semiconductor layer 102 .
  • this step S173 can be implemented in two ways.
  • the second dielectric layer 112 can be directly formed by chemical vapor deposition, physical vapor deposition, sputtering or electroplating. The exposed surfaces of the first pole 109 and the first dielectric layer 113 .
  • chemical vapor deposition, physical vapor deposition, sputtering or electroplating can be used to form a seventh dielectric film, and the seventh dielectric film covers the semiconductor layer 102 , the second electrode 108 , the first electrode 109 and the first dielectric layer 113 exposed surface; and then etch the seventh dielectric film, except for the seventh dielectric film formed on the surface of the semiconductor layer 102 away from the first pole 109, the seventh dielectric film formed in other places is etched away, thereby A second dielectric layer 112 is formed.
  • the drawings of the first mode are not shown.
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061 ; the gate pillar 1062 extends along the sides of the first dielectric layer 113 and the second electrode 108 , the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109 , and the second dielectric layer 112 separates the gate electrode 106 from the semiconductor layer 102 , the first electrode 109 and the second electrode 108 .
  • step S174 for the specific implementation process of this step S174, reference may be made to the above-mentioned step S104, which will not be repeated here.
  • making the thin film transistor shown in Figure 12c specifically includes the following steps:
  • a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .
  • step S180 for the specific implementation process of this step S180, reference may be made to the above-mentioned step S100, which will not be repeated here.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the sides of the first electrode 109, the first dielectric layer 113 and the second electrode 108, and the semiconductor layer 102 is further composed of the first electrode 109, the first dielectric layer 113 and the side surfaces of the second pole 108 extend to the surface of the second pole 108 on the side away from the first pole 109 , that is, the top surface of the second pole 108 .
  • an epitaxial growth method can be used to form a semiconductor thin film, the semiconductor thin film is a whole layer, covering the exposed surfaces of the first pole 109, the first dielectric layer 113 and the second pole 108; and then the semiconductor thin film is etched, except for forming Except for the semiconductor thin films on the left side of the first pole 109 , the first dielectric layer 113 and the second pole 108 and the top surface of the second pole 108 , the semiconductor thin films formed in other parts are etched away, thereby forming the semiconductor layer 102 .
  • a second dielectric layer 112 is formed; the second dielectric layer 112 covers the semiconductor layer 102 .
  • this step S183 can be implemented in two ways.
  • the second dielectric layer 112 can be directly formed by chemical vapor deposition, physical vapor deposition, sputtering or electroplating. The exposed surfaces of the first pole 109 and the first dielectric layer 113 .
  • Second, chemical vapor deposition, physical vapor deposition, sputtering or electroplating can be used to form a seventh dielectric film, and the seventh dielectric film covers the semiconductor layer 102 , the second electrode 108 , the first electrode 109 and the first dielectric layer 113 exposed surface; then the seventh dielectric film is etched, except for the seventh dielectric film formed on the side and top surface of the semiconductor layer 102, the seventh dielectric film formed in other places is etched away, thereby forming the second dielectric film. Dielectric layer 112 .
  • the drawings of the first mode are not shown.
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061 ; the gate pillar 1062 extends along the sides of the first dielectric layer 113 and the second electrode 108 , the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109 , and the second dielectric layer 112 separates the gate electrode 106 from the semiconductor layer 102 , the first electrode 109 and the second electrode 108 .
  • step S184 for the specific implementation process of this step S184, reference may be made to the above-mentioned step S104, which will not be repeated here.
  • the difference between the seventh embodiment, the eighth embodiment and the ninth embodiment and the above-mentioned other embodiments is that the structures of the formed stacked first pole 109 , the first dielectric layer 113 and the second pole 108 are different.
  • making the thin film transistor 10 shown in FIG. 16 specifically includes the following steps:
  • a first conductive film 1090 and a third dielectric film 1131 are sequentially stacked on the substrate 101 .
  • step S190 for the specific implementation process of this step S190, reference may be made to the above-mentioned step S100, which will not be repeated here.
  • the modulation gate electrode 118 is formed on the third dielectric film 1131 .
  • the specific process of forming the modulation gate electrode 118 may be as follows: forming the fifth conductive film first, and then patterning the fifth conductive film to form the modulation gate electrode 118 .
  • a fourth dielectric film 1132 is formed on the modulation gate electrode 118 ; wherein, the fourth dielectric film 1132 covers the modulation gate electrode 118 .
  • the fourth dielectric film 1132 may be formed by chemical vapor deposition, physical vapor deposition, sputtering, electroplating, and other methods.
  • the fourth dielectric film 1132 may be polished by chemical mechanical polishing technology.
  • step S193 is an optional step, for example, in some embodiments, step S193 may be omitted.
  • a second conductive film 1080 is formed on the fourth dielectric film 1132 .
  • the second conductive thin film 1080 can be formed by chemical vapor deposition, physical vapor deposition, sputtering, electroplating, or the like.
  • the second conductive film 1080 is patterned to form the second pole 108
  • the fourth dielectric film 1132 and the third dielectric film 1131 are patterned to form the first dielectric layer 113
  • the first conductive film is patterned.
  • 1090 is patterned to form the first electrode 109; wherein, the second electrode 108, the first dielectric layer 113 and the first electrode 109 form a groove structure, and the first dielectric layer 113 surrounds the modulation gate electrode 118, thereby connecting the modulation gate electrode 118 with the first electrode 118.
  • the second pole 108 and the first pole 109 are spaced apart.
  • step S195 for the specific implementation process of this step S195, reference may be made to the foregoing step S101, which will not be repeated here.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure, and the surface of the second electrode 108 on the side away from the first electrode 109, that is, the semiconductor layer 102 is formed on the first electrode 109.
  • the sides of the dielectric layer 113 and the second pole 108, the semiconductor layer 102 also extends from the sides of the first dielectric layer 113 and the second pole 108 to the surface of the second pole 108 on the side away from the first pole 109 (that is, the side of the second pole 108). top surface) and the surface of the first pole 109 close to the second pole 108 (ie, the top surface of the first pole 109 ); both the first pole 109 and the second pole 108 are electrically connected to the semiconductor layer 102 .
  • a second dielectric layer 112 is formed; the second dielectric layer 112 covers the semiconductor layer 102 .
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061; the gate pillar 1062 extends into the groove structure, that is, the gate pillar 1062 extends along the A dielectric layer 113 and the sides of the second electrode 108 extend; the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109, and the second dielectric layer 112 connects the gate 106 with the semiconductor layer 102, the first electrode 109 and the The second pole 108 is spaced apart.
  • step S198 for the specific implementation process of this step S198, reference may be made to the above-mentioned step S104, which will not be repeated here.
  • step S191 is added in the tenth embodiment.
  • making the thin film transistor 10 shown in FIG. 11 specifically includes the following steps:
  • a first conductive thin film 1090 and a first dielectric thin film 1130 are sequentially stacked on the substrate 101 .
  • step S200 for the specific implementation process of this step S200, reference may be made to the above-mentioned step S100, which will not be repeated here.
  • step S201 for the specific implementation process of this step S201, reference may be made to the foregoing step S101, which will not be repeated here.
  • the semiconductor layer 102 is formed; the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure, and the surface of the first dielectric layer 113 on the side away from the first electrode 109, that is, the semiconductor layer 102 is formed on the first electrode 109.
  • a side surface of the dielectric layer 113, and the semiconductor layer 102 also extends from the side surface of the first dielectric layer 113 to the surface of the first electrode 109 on the side close to the first dielectric layer 113 (ie, the top surface of the first electrode 109) and the first dielectric layer 113 is a surface away from the first electrode 109 (ie, the top surface of the first dielectric layer 113 ); the first electrode 109 is electrically connected to the semiconductor layer 102 .
  • an epitaxial growth method can be used to form a semiconductor thin film, which is a whole layer, covering the exposed surfaces of the first pole 109 and the first dielectric layer 113; Apart from the semiconductor thin film on the walls, the bottom and the top surface of the first dielectric layer 113 , the semiconductor thin film formed on the outer side of the groove is etched away, thereby forming the semiconductor layer 102 .
  • the second pole 108 is formed; the second pole 108 is located on the side of the first dielectric layer 113 away from the first pole 109 , that is, the second pole 108 is located on the top surface of the first dielectric layer 113 .
  • the process of forming the second electrode 108 may specifically include: firstly forming the second conductive film, and then etching the second conductive film to form the second electrode 108 .
  • a second dielectric layer 112 is formed; the second dielectric layer 112 covers the semiconductor layer 102 and the second electrode 108 .
  • this step S204 can be implemented in two ways.
  • the second dielectric layer 112 can be directly formed by chemical vapor deposition, physical vapor deposition, sputtering or electroplating. The exposed surfaces of the first pole 109 and the first dielectric layer 113 .
  • a seventh dielectric film covers the semiconductor layer 102 , the second electrode 108 , the first electrode 109 and the first dielectric layer 113 The exposed surface; then the seventh dielectric film is etched, except for the part formed on the side and bottom of the groove and the top and side surfaces of the second pole 108, the other seventh dielectric films are etched away, thereby forming the first dielectric film.
  • Two dielectric layers 112 are not shown.
  • the gate 106 is formed; the gate 106 includes a gate substrate 1061 and a gate pillar 1062 extending from the gate substrate 1061; the gate pillar 1062 extends into the groove structure, that is, the gate pillar 1062 extends along the A dielectric layer 113 and the sides of the second electrode 108 extend; the gate substrate 1061 is formed on the side of the gate pillar 1062 away from the first electrode 109, and the second dielectric layer 112 connects the gate 106 with the semiconductor layer 102, the first electrode 109 and the The second pole 108 is spaced apart.
  • the order of forming the semiconductor layer 102 and the second electrode 108 in the eleventh embodiment is different from that of the above-mentioned other embodiments.
  • the thin film transistor 10 provided in the embodiment of the present application may be manufactured by the method for manufacturing the thin film transistor 10 provided above, or other manufacturing methods, which are not limited thereto.
  • Embodiments of the present application further provide a method for fabricating a memory, including forming at least one layer of a memory array 201 on a substrate 101 .
  • making any layer of storage array 201 as shown in FIG. 4 , as shown in FIG. 30 specifically includes the following steps:
  • the first thin film transistor Tr0 can be manufactured by using the manufacturing method of the thin film transistor 10 provided in any of the above embodiments. It can be understood that the plurality of first thin film transistors Tr0 distributed in an array here may be formed synchronously.
  • the first signal line may be the read bit line RBL, and the second signal line may be the read word line RWL; in this case, the first pole 109a of the first thin film transistor Tr0 is electrically connected to the read bit line RBL, The second pole 108a is electrically connected to the read word line RWL; the first signal line may also be the read word line RWL, and the second signal line may be the read bit line RBL; in this case, the first pole 109a of the first thin film transistor Tr0 It is electrically connected to the read word line RWL, and the second pole 108a is electrically connected to the read bit line RBL.
  • first pole 109a and the first signal line may be formed synchronously, and the second pole 108a and the second signal line may be formed synchronously.
  • connection electrodes 111 distributed in an array; the gate electrode 106 a of a first thin film transistor Tr0 is electrically connected to a connection electrode 111 .
  • step S302 is an optional step.
  • step S302 may also be omitted.
  • the sixth conductive film may be formed first, and then the sixth conductive film may be etched to form a plurality of connection electrodes 111 .
  • the second thin film transistor Tr1 corresponds to one first thin film transistor Tr0, and the first electrode 109b of the second thin film transistor Tr1 is electrically connected to the gate 1106a of the corresponding first thin film transistor Tr0; here, the second thin film transistor Tr1 can be manufactured by using the manufacturing method of the thin film transistor 10 provided in any of the above embodiments. It can be understood that the plurality of second thin film transistors Tr1 distributed in an array here may be formed synchronously.
  • step S302 when the manufacturing method of any layer of the memory array 201 includes step S302, the first electrode 109b of the second thin film transistor Tr1 and the gate electrode 106a of the corresponding first thin film transistor Tr0 are electrically connected together through the connecting electrode 111 .
  • the second electrode 108b of the second thin film transistor Tr1 may be formed in synchronization with the write bit line WBL.
  • the write word line WWL may be formed in synchronization with the gate electrode 106b of the second thin film transistor Tr1.
  • steps S300 - S304 may be repeated to form the multi-layer memory array 201 .
  • the sixth dielectric layer 202 may be formed first. At this time, the sixth dielectric layer 202 serves as the substrate of the second-layer memory array 201 . Similarly, before fabricating the third-layer storage array 201, the fourth-layer storage array 201, etc., the sixth dielectric layer 202 can also be formed first.

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Abstract

本申请实施例提供一种薄膜晶体管、存储器及制作方法、电子设备，涉及存储器技术领域，可以降低薄膜晶体管的尺寸，提高面积利用率，且降低布线难度。该薄膜晶体管包括栅极、第一极、第二极、第一介质层、第二介质层以及半导体层。其中，栅极包括位于顶部的栅基底和从栅基底向底部延伸的栅极柱；第一极位于底部；第二极位于第一极和栅基底之间；第一介质层设置在第二极和第一极之间，第一介质层用于将第一极和第二极隔开；第二介质层覆盖栅基底的表面和栅极柱的表面；半导体层沿栅极柱的侧面设置，且第二介质层将半导体层与栅极隔开。第一极和第二极分别与半导体层电连接。

Description

薄膜晶体管、存储器及制作方法、电子设备
本申请要求于2021年01月26日提交国家知识产权局、申请号为202110106685.8发明名称为“薄膜晶体管、存储器及制作方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储器技术领域，尤其涉及一种薄膜晶体管、存储器及制作方法、电子设备。
背景技术
由于薄膜晶体管(thin film transistor，TFT)具有漏电流低，生长温度低，迁移率高等优点，因而薄膜晶体管已广泛应用于各种器件例如存储器中。
现有的薄膜晶体管的结构如图1所示，薄膜晶体管10包括设置在衬底101上的半导体层(也可以称为有源层)102、设置在半导体层102上且与半导体层102接触的源极103和漏极104、设置在半导体层102上的栅绝缘层105以及设置在栅绝缘层105上的栅极106。
由于现有的薄膜晶体管10的半导体层102是沿平行于栅极106的平面铺展，且源极103和漏极104位于同一层，因而导致薄膜晶体管10的尺寸较大，面积利用率低。此外，由于源极103和漏极104位于同一层，因而导致与源极103电连接的信号线和与漏极104电连接的信号线在布线时容易出现短路，不利于布线，增加了工艺难度。
发明内容
本申请实施例提供一种薄膜晶体管、存储器及制作方法、电子设备，可以降低薄膜晶体管的尺寸，提高面积利用率，且降低布线难度。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种薄膜晶体管，该薄膜晶体管包括栅极、第一极、第二极、第一介质层、第二介质层以及半导体层。其中，栅极包括位于顶部的栅基底和从栅基底向底部延伸的栅极柱；第一极位于底部；第二极位于第一极和栅基底之间；第一介质层设置在第二极和第一极之间，第一介质层用于将第一极和第二极隔开；半导体层沿栅极柱的侧面设置，且第二介质层将半导体层与栅极隔开。第一极和第二极分别与半导体层电连接。
相对于现有技术中，半导体层沿平行于栅极(现有技术中的栅极相当于本申请实施例中的栅基底)的平面设置，且第二极和第一极同层设置。本申请实施例中，由于半导体层沿栅极柱的侧面设置，且第一极位于底部，第二极位于第一极和栅基底之间，第一极和第二极分别与半导体层电连接，因而本申请实施例提供的薄膜晶体管在平行于栅基底的平面上的尺寸较小，因此本申请实施例降低了薄膜晶体管的尺寸，提高了面积利用率。此外，由于本申请实施例中的薄膜晶体管的第二极和第一极位于不同层，因此可以避免与第二极电连接的信号线和与第一极电连接的信号线在布线时出现短路，降低了工艺难度。
在一种可能的实施方式中，第二极靠近栅基底设置。这样可以避免在制作第一极 和第二极时，第一极和第二极直接导通。
在一种可能的实施方式中，栅极柱在栅基底上的投影的边界位于栅基底的边界内。此时，栅极柱设置在栅基底的中间区域。
在一种可能的实施方式中，栅极柱在栅基底上的投影的边界与栅基底的边界部分重叠。此时，栅极柱设置在栅基底的边缘区域。
在一种可能的实施方式中，栅极柱为中空结构；栅极柱在栅基底上的投影的外边界与栅基底的边界重叠。由于栅极柱为中空结构，因而可以将第二介质层、半导体层、第二极以及第一介质层等设置在中空结构内。
在一种可能的实施方式中，半导体层还包括沿栅基底的表面延伸的延伸部。这样可以增大半导体层的面积，进而增大半导体层与第二极电连接的面积，提高薄膜晶体管的开关速率。
在一种可能的实施方式中，半导体层还包括位于栅极柱和第一极之间的延伸部。这样可以增大半导体层的面积，进而增大半导体层与第一极电连接的面积，提高薄膜晶体管的开关速率。
在一种可能的实施方式中，半导体层围绕栅极柱的侧面设置一圈。这样可以增大半导体层的面积，提高薄膜晶体管的开关速率。
在一种可能的实施方式中，半导体层包围栅极柱的整个侧面。
在一种可能的实施方式中，第二极设置在半导体层远离第二介质层的一侧。
在一种可能的实施方式中，第二极设置在半导体层和第二介质层之间。
在一种可能的实施方式中，第二介质层的材料为铁电材料；薄膜晶体管还包括：设置在半导体层和第二介质层之间的第三介质层。此处，栅极、第二介质层和第三介质层可以构成复合栅结构，通过该复合栅结构，薄膜晶体管可以实现负电容晶体管性能，利用负电容可以提高薄膜晶体管的栅控能力。在薄膜晶体管应用于存储器中时，可以提高存储器的性能。
在一种可能的实施方式中，薄膜晶体管还包括：设置在第二介质层和第三介质层之间的第一导电层。此处，栅极、第二介质层、第一导电层和第三介质层构成的复合栅结构，可以使薄膜晶体管实现负电容晶体管性能，利用负电容可以提高薄膜晶体管的栅控能力。在薄膜晶体管应用于存储器中时，可以提高存储器的性能。
在一种可能的实施方式中，薄膜晶体管还包括：设置在第二极和半导体层之间的第四介质层；和/或，设置在第一极和半导体层之间的第五介质层。在第二极和半导体层之间设置第四介质层，可以避免第二极在与半导体层接触区域的扩散问题，降低第二极和半导体层接触的费米能级钉扎问题。在第一极和半导体层之间设置第五介质层，可以避免第一极在与半导体层接触区域的扩散问题，降低第一极和半导体层接触的费米能级钉扎问题。
在一种可能的实施方式中，第四介质层和第五介质层的厚度范围均为0.1nm～2nm。这样可以确保在栅极上提供有电压时，第二极和第一极能够通过半导体层导通，不会影响薄膜晶体管的性能。
在一种可能的实施方式中，薄膜晶体管还包括：设置在第一极和第二极之间的调制栅电极，且调制栅电极设置在半导体层远离栅极柱的一侧，调制栅电极由第一介质 层包围，从而与第一极、第二极和半导体层间隔开。此处，可以通过调制栅电极对薄膜晶体管的阈值电压进行调节。
在一种可能的实施方式中，第一极是漏极，第二极是源极；或者，第一极是源极，第二极是漏极。
第二方面，提供一种存储器，该存储器包括设置于衬底上的至少一层存储阵列；每层存储阵列包括阵列分布的多个存储单元、写字线、写位线、读字线以及读位线；存储单元包括层叠设置的第二薄膜晶体管和第一薄膜晶体管；第二薄膜晶体管的栅极与写字线电连接，第二极与写位线电连接；第一薄膜晶体管的第二极和第一极分别与读字线、读位线电连接；第二薄膜晶体管和第一薄膜晶体管为上述的薄膜晶体管；其中，第二薄膜晶体管的第一极靠近第一薄膜晶体管的栅极，且第二薄膜晶体管的第一极与第一薄膜晶体管的栅极电连接。由于存储器中的第二薄膜晶体管和第一薄膜晶体管为上述的薄膜晶体管，第二薄膜晶体管和第一薄膜晶体管具有与前述实施例相同的技术效果，因而此处不再赘述。
在一种可能的实施方式中，存储单元还包括设置在第一薄膜晶体管和第二薄膜晶体管之间的连接电极；第一薄膜晶体管的栅极与第二薄膜晶体管的第一极通过连接电极电连接在一起。
在一种可能的实施方式中，每层存储阵列中沿第一方向依次排列的多个存储单元中的第二薄膜晶体管的栅极与同一条写字线电连接；每层存储阵列中沿第二方向依次排列的多个存储单元中的第二薄膜晶体管的第二极与同一条写位线电连接；其中，第一方向和第二方向相交。由于每层存储阵列中沿第一方向依次排列的多个存储单元中的第二薄膜晶体管的栅极与同一条写字线电连接，沿第二方向依次排列的多个存储单元中的第二薄膜晶体管的第二极与同一条写位线电连接，因而在写操作过程中，可以逐行给多条写字线提供第一开关信号，以使多行第二薄膜晶体管逐行导通，在当前行的写字线提供第一开关信号的情况下，通过多条写位线给与当前行的写字线电连接的多个存储单元同时写入逻辑信息，从而可以逐行给存储单元写入逻辑信息，以实现存储阵列中的多个存储单元的快速写入。
在一种可能的实施方式中，每层存储阵列中沿第一方向依次排列的多个存储单元中的第一薄膜晶体管的第二极与同一条读位线电连接；每层存储阵列中沿第二方向依次排列的多个存储单元中的第一薄膜晶体管的第一极与同一条读字线电连接；或者，每层存储阵列中沿第一方向依次排列的多个存储单元中的第一薄膜晶体管的第二极与同一条读字线电连接；每层存储阵列中沿第二方向依次排列的多个存储单元中的第一薄膜晶体管的第一极与同一条读位线电连接；或者，每层存储阵列中沿第二方向依次排列的多个存储单元中的第一薄膜晶体管的第二极与同一条读位线电连接；每层存储阵列中沿第一方向依次排列的多个存储单元中的第一薄膜晶体管的第一极与同一条读字线电连接；或者，每层存储阵列中沿第二方向依次排列的多个存储单元中的第一薄膜晶体管的第二极与同一条读字线电连接；每层存储阵列中沿第一方向依次排列的多个存储单元中的第一薄膜晶体管的第一极与同一条读位线电连接；其中，第一方向和第二方向相交。在读操作过程中，可以逐行给多条读字线提供第三电平信号，在当前行的读字线提供第三电平信号的情况下，通过检测每条读位线上的电流，这样便可以 同时读出与当前行的读字线电连接的多个存储单元所存储的逻辑信息，从而可以逐行读取存储单元存储的逻辑信息，以可以实现存储阵列中的多个存储单元的快速读取。
在一种可能的实施方式中，第一方向和第二方向正交。
在一种可能的实施方式中，第一薄膜晶体管还包括设置在第一极和第二极之间的第一调制栅电极，且第一调制栅电极设置在半导体层远离栅极柱的一侧，第一调制栅电极由第一薄膜晶体管的第一介质层包围，从而与第二极、第一极和半导体层间隔开；位于同一层的多个第一薄膜晶体管的第一调制栅电极电连接在一起；和/或，第二薄膜晶体管还包括设置在第一极和第二极之间的第二调制栅电极，且第二调制栅电极设置在半导体层远离栅极柱的一侧，第二调制栅电极由第二薄膜晶体管的第一介质层包围，从而与第二极、第一极和半导体层间隔开；位于同一层的多个第二薄膜晶体管的第二调制栅电极电连接在一起。由于第一薄膜晶体管包括第一调制栅电极，因而可以通过第一调制栅电极对第一薄膜晶体管的阈值电压进行调节。此外，多个第一薄膜晶体管的第一调制栅电极电连接在一起可以实现对多个第一薄膜晶体管的共同调制。由于第二薄膜晶体管包括第二调制栅电极，因而可以通过第二调制栅电极对第二薄膜晶体管的阈值电压进行调节。此外，多个第二薄膜晶体管的第二调制栅电极电连接在一起可以实现对多个第二薄膜晶体管的共同调制。基于此，可以对存储器的存储性能进行更加灵活的调节。
在一种可能的实施方式中，存储器还包括集成电路；存储阵列设置于集成电路上。此时，存储器为片上存储器。
在一种可能的实施方式中，存储单元与集成电路电连接。这样可以通过集成电路控制存储单元。
第三方面，提供一种电子设备，该电子设备包括电路板以及与电路板电连接的存储器，存储器为上述的存储器。该电子设备具有与前述实施例相同的技术效果，此处不再赘述。
第四方面，提供一种薄膜晶体管的制作方法，该薄膜晶体管的制作方法包括：首先，在衬底上形成第一极、第一介质层、第二极以及半导体层；其中，第一极、第一介质层和第二极依次层叠设置，第一介质层将第一极和第二极隔开；半导体层形成在第一介质层的侧面；第二极和第一极均与半导体层电连接；然后，依次形成第二介质层和栅极；栅极包括位于顶部的栅基底和从栅基底向底部延伸的栅极柱，第二介质层将栅极与半导体层、第一极和第二极隔开。该薄膜晶体管的制作方法具有与前述实施例相同的技术效果，此处不再赘述。
在一种可能的实施方式中，形成第一极作为漏极，形成第二极作为源极；或者，形成第一极作为源极，形成第二极作为漏极。
在一种可能的实施方式中，在衬底上形成第一极、第一介质层、第二极以及半导体层包括：首先，在衬底上依次形成层叠的第一导电薄膜、第一介质薄膜和第二导电薄膜；然后，对第一导电薄膜、第一介质薄膜和第二导电薄膜进行构图，形成依次层叠的第一极、第一介质层和第二极；之后，在第一介质层和第二极的侧面形成半导体层。
在一种可能的实施方式中，在衬底上形成第一极、第一介质层、第二极以及半导 体层包括：首先，在衬底上形成依次层叠的第一导电薄膜和第三介电薄膜；接下来，在第三介质薄膜上形成调制栅电极；接下来，形成第四介电薄膜；其中，第四介质薄膜包围调制栅电极；接下来，在第四介质薄膜上形成第二导电薄膜；接下来，对第一导电薄膜进行构图形成第一极，对第四介电薄膜和第三介电薄膜进行构图形成第一介质层，对第二导电薄膜进行构图形成第二极；在第一介质层和第二极的侧面形成半导体层。此处，可以通过调制栅电极对薄膜晶体管的阈值电压进行调节。
在一种可能的实施方式中，在衬底上形成第一极、第一介质层、第二极以及半导体层包括：首先，在衬底上形成依次层叠的第一导电薄膜和第一介质薄膜；接下来，对第一导电薄膜和第一介质薄膜进行构图，形成依次层叠的第一极和第一介质层；接下来，在第一介质层的侧面形成半导体层；接下来，在第一介质层上形成第二极。
在一种可能的实施方式中，第二介质层的材料为铁电材料；在形成半导体层之后，在形成第二介质层之前，上述制作方法还包括：形成第三介质层；第三介质层形成在第一介质层的侧面。该第三介质层具有与上述实施例相同的技术效果，此处不再赘述。
在一种可能的实施方式中，在形成第三介质层之后，形成第二介质层之前，上述制作方法还包括：形成第一导电层；第一导电层形成在第一介质层的侧面。该第一导电层具有与上述实施例相同的技术效果，此处不再赘述。
在一种可能的实施方式中，在形成第一极之后，形成半导体层之前，上述制作方法还包括：形成第五介质层；其中，第五介质层分别与第一极和半导体层接触。这样可以避免第一极在与半导体层接触区域的扩散问题，降低第一极和半导体层接触的费米能级钉扎问题。
在一种可能的实施方式中，在形成第二极之后，形成半导体层之前；或者，在形成半导体层之后，在形成第二极之前，上述制作方法还包括：形成第四介质层；其中，第四介质层分别与第二极和半导体层接触。这样可以避免第二极在与半导体层接触区域的扩散问题，降低第二极和半导体层接触的费米能级钉扎问题。
第五方面，提供一种存储器的制作方法，该存储器的制作方法包括在衬底上形成至少一层存储阵列。任意一层存储阵列的制作方法，包括：首先，在所述衬底上形成多条平行排列的第一信号线；接下来，在多条第一信号线上形成阵列分布的多个第一薄膜晶体管以及多条平行排列的第二信号线；第一薄膜晶体管采用上述的薄膜晶体管的制作方法制作得到；其中，第一薄膜晶体管的第一极与第一信号线电连接，第一薄膜晶体管的第二极与第二信号线电连接；第一信号线为读位线和读字线中的一个，第二信号线为所述读位线和所述读字线中的另一个；接下来，在第一薄膜晶体管上形成阵列分布的多个第二薄膜晶体管以及多条平行排列的写位线；第二薄膜晶体管的第二极与写位线电连接；第二薄膜晶体管采用上述的薄膜晶体管的制作方法制作得到；其中，一个第二薄膜晶体管与一个第一薄膜晶体管对应，且第二薄膜晶体管的第一极与对应的第一薄膜晶体管的栅极电连接；接下来，在第二薄膜晶体管上形成多条平行排列的写字线；第二薄膜晶体管的栅极与写字线电连接。由于存储器中的第一薄膜晶体管和第二薄膜晶体管均采用上述的薄膜晶体管的制作方法制作得到，因而制作的存储器中第一薄膜晶体管和第二薄膜晶体管的尺寸较小，提高了面积利用率。
在一种可能的实施方式中，在多条所述第一信号线上形成阵列分布的多个第一薄 膜晶体管以及多条平行排列的第二信号线之后，在第一薄膜晶体管上形成阵列分布的多个第二薄膜晶体管以及多条平行排列的写位线之前，上述任意一层所述存储阵列的制作方法还包括：形成阵列分布的多个连接电极；第一薄膜晶体管的栅极与对应的第二薄膜晶体管的第一极通过连接电极电连接在一起。
附图说明
图1为现有技术提供的一种薄膜晶体管的结构示意图；
图2a为2T0C结构的存储器中一个存储单元的结构示意图；
图2b为一种存储单元中第二薄膜晶体管和第一薄膜晶体管的结构示意图；
图2c为另一种存储单元中第二薄膜晶体管和第一薄膜晶体管的结构示意图；
图3为本申请的实施例提供的一种电子设备的结构示意图；
图4为本申请的实施例提供的一种存储器的结构示意图；
图5为本申请的实施例提供的一种存储阵列的结构示意图；
图6a为本申请的另一实施例提供的一种存储阵列的结构示意图；
图6b为图6a中第一方向的剖面示意图；
图6c为图6a中第二方向的剖面示意图；
图6d为一种图6b或图6c中AA向的剖面示意图；
图6e为另一种图6b或图6c中AA向的剖面示意图；
图7为本申请的另一实施例提供的一种存储器的结构示意图；
图8a为本申请的实施例提供的一种薄膜晶体管的结构示意图；
图8b为一种图8a中BB向的剖面示意图；
图8c为另一种图8a中BB向的剖面示意图；
图9为本申请的另一实施例提供的一种薄膜晶体管的结构示意图；
图10为本申请的又一实施例提供的一种薄膜晶体管的结构示意图；
图11为本申请的再一实施例提供的一种薄膜晶体管的结构示意图；
图12a为本申请的另一实施例提供的一种薄膜晶体管的结构示意图；
图12b为本申请的又一实施例提供的一种薄膜晶体管的结构示意图；
图12c为本申请的再一实施例提供的一种薄膜晶体管的结构示意图；
图13为本申请的另一实施例提供的一种薄膜晶体管的结构示意图；
图14为本申请的又一实施例提供的一种薄膜晶体管的结构示意图；
图15为本申请的再一实施例提供的一种薄膜晶体管的结构示意图；
图16为本申请的另一实施例提供的一种薄膜晶体管的结构示意图；
图17a为本申请的又一实施例提供的一种存储阵列的结构示意图；
图17b为一种图17a中CC向的剖面示意图；
图17c为另一种图17a中CC向的剖面示意图；
图18为本申请的实施例提供的一种薄膜晶体管的制备方法的流程示意图；
图19为本申请的实施例提供的一种薄膜晶体管的制备过程的结构示意图；
图20为本申请的实施例提供的另一种薄膜晶体管的制备过程的结构示意图；
图21为本申请的实施例提供的又一种薄膜晶体管的制备过程的结构示意图；
图22为本申请的实施例提供的又一种薄膜晶体管的制备过程的结构示意图；
图23为本申请的实施例提供的又一种薄膜晶体管的制备过程的结构示意图；
图24为本申请的实施例提供的又一种薄膜晶体管的制备过程的结构示意图；
图25为本申请的实施例提供的又一种薄膜晶体管的制备过程的结构示意图；
图26为本申请的实施例提供的又一种薄膜晶体管的制备过程的结构示意图；
图27为本申请的实施例提供的又一种薄膜晶体管的制备过程的结构示意图；
图28为本申请的实施例提供的又一种薄膜晶体管的制备过程的结构示意图；
图29为本申请的实施例提供的又一种薄膜晶体管的制备过程的结构示意图；
图30为本申请的实施例提供的一种存储器的制备方法的流程示意图。
附图标记：
1-天线；2-天线；10-薄膜晶体管；100-电子设备；101-衬底；102-半导体层；103-源极；104-漏极；105-栅绝缘层；106-栅极；107-层间介电层；108-第二极；109-第一极；110-处理器；111-连接电极；112-第二介质层；113-第一介质层；114-第四介质层；115-第五介质层；116-第三介质层；117-第一导电层；118-调制栅电极；118a-第一调制栅电极；118b-第二调制栅电极；120-外部存储器接口；121-内部存储器；130-USB接口；140-充电管理模块；141-电源管理模块；142-电池；150-移动通信模块；160-无线通信模块；170-音频模块；180-传感器模块；190-按键；191-马达；192-指示器；193-摄像头；194-显示屏；195-SIM卡接口；200-存储器；201-存储阵列；201A-存储单元；202-第六介质层；203-集成电路；1080-第二导电薄膜；1090-第一导电薄膜；1121-第一介质部分；1122-第二介质部分；1130-第一介质薄膜；1131-第三介电薄膜；1132-第四介电薄膜。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。另外，术语“耦接”可以表示两个或两个以上部件有直接物理接触或电接触，也可以表示两个或两个以上部件彼此间并无直接接触，但通过中间媒介电连接或相互作用。
本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其 中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本申请实施例中关于附图的描述是基于附图所示的方位进行的描述，当附图所示的方位发生变化时，对应的描述也相应地发生变化。
随着集成电路技术的不断发展，计算机、手机等电子产品中芯片上单位面积设置的晶体管数量不断增加，从而使得电子产品的性能得到不断的优化。一方面，芯片上的处理器在单位时间能够运算的数据量不断提高；另一方面，芯片上的存储器的存储密度也在不断增长，从而满足信息时代下人们对于数据处理的需求。然而，由于处理器中的逻辑单元和存储器的存储单元在结构和工艺的不同，因而导致处理器和存储器的性能提高的程度出现差距，具体是存储器的存储密度、读写速度跟不上处理器的运算速度，出现“存储墙”，最终导致电子产品的整体性能提升受限。
为了解决上述问题，各种类型的存储器应运而生。在各种类型的存储器中，增益单元(gain cell)存储器应用较为广泛，其主要的目标应用场景为高速、高密度存储器。其中，2T0C结构的gain cell存储器能够实现纳秒级的读写速度以及毫秒级的存储时间。存储时间指的是存储器存储的信息保持的时间，也即从写入到正确读出存储信息的时间。然而，由于2T0C结构的gain cell存储器的存储时间较短，因而导致2T0C结构的gain cell存储器在实际应用中需要进行不断的刷新，这样一来，带来了较大的动态功耗。
基于上述，为了提高2T0C结构的存储器的保持时长，解决2T0C结构的gain cell存储器功耗较大的问题，目前可以基于TFT制备2T0C结构的gain cell存储器。一方面，可以利用TFT超低漏电的优点，极大的提高了2T0C结构的存储器的保持时间，降低了动态功耗；另一方面，还可以利用TFT制作工艺温度低的优点，实现3D(3dimensions，三维)存储器集成，提高存储密度。
参考图2a，图2a为2T0C结构的存储器中一个存储单元的结构示意图，存储单元包括第一薄膜晶体管Tr0和第二薄膜晶体管Tr1，第二薄膜晶体管Tr1的栅极与写字线WWL电连接，源极与写位线WBL电连接，漏极与第一薄膜晶体管Tr0的栅极电连接，第一薄膜晶体管Tr0的源极与读字线RWL电连接，漏极与读位线RBL电连接。
图2b和图2c分别为基于TFT的2T0C结构的存储器的一个存储单元中，第一薄膜晶体管Tr0和第二薄膜晶体管Tr1的结构示意图。参考图2b和图2c，第一薄膜晶体管Tr0和第二薄膜晶体管Tr1均包括设置在衬底101上的半导体层102、设置在半导体层102上，且与半导体层102接触的源极103和漏极104、设置在半导体层102上的栅绝缘层105以及设置在栅绝缘层105上的栅极106。此外，图2b和图2c中层间介电层107用于将不同的导电的膜层间隔开，信号线通过过孔与对应的电极电连接，例如读字线RWL通过过孔与第一薄膜晶体管Tr0的源极103电连接。
然而，由于图2b和图2c所示的第一薄膜晶体管Tr0和第二薄膜晶体管Tr1中的半导体层102均沿着平行于栅极106的平面铺展，且源极103和漏极104设置在同一层，这样一来，导致第一薄膜晶体管Tr0和第二薄膜晶体管Tr1的尺寸较大，第一薄膜晶体管Tr0和第二薄膜晶体管Tr1的面积利用率低。此外，由于源极103和漏极104位于同一层，因而导致与源极103电连接的信号线和与漏极104电连接的信号线容易出现短路，不利于布线，提高了工艺难度。
为解决上述问题，本申请实施例提供一种存储器，该存储器可以应用于电子设备中。该电子设备可以是手机、平板电脑、桌面型计算机、膝上型计算机、手持计算机、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本，以及蜂窝电话、个人数字助理(personal digital assistant，PDA)、增强现实(augmented reality，AR)设备、虚拟现实(virtual reality，VR)设备、人工智能(artificial intelligence，AI)设备、可穿戴式设备、车载设备、智能家居设备和/或智慧城市设备，本申请实施例对该电子设备的具体类型不作特殊限制。
图3示出了电子设备的结构示意图。电子设备100可以包括处理器110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理模块140，电源管理模块141，电池142，天线1，天线2，移动通信模块150，无线通信模块160，音频模块170，传感器模块180，按键190，马达191，指示器192，摄像头193，显示屏194，以及用户标识模块(subscriber identification module，SIM)卡接口195等。
可以理解的是，本申请实施例示意的结构并不构成对电子设备100的具体限定。在本申请另一些实施例中，电子设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-networkprocessing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
控制器可以根据指令操作码和时序信号，产生操作控制信号，完成取指令和执行指令的控制。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器110需要再次使用该指令或数据，可从所述存储器中直接调用。避免了重复存取，减少了处理器110的等待时间，因而提高了系统的效率。
在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
I2C接口是一种双向同步串行总线，包括一根串行数据线(serial data line，SDA)和一根串行时钟线(derail clock line，SCL)。I2S接口可以用于音频通信。
PCM接口也可以用于音频通信，将模拟信号抽样，量化和编码。
UART接口是一种通用串行数据总线，用于异步通信。该总线可以为双向通信总线。它将要传输的数据在串行通信与并行通信之间转换。
MIPI接口可以被用于连接处理器110与显示屏194，摄像头193等外围器件。MIPI接口包括摄像头串行接口(camera serial interface，CSI)，显示屏串行接口(displayserial interface，DSI)等。
GPIO接口可以通过软件配置。GPIO接口可以被配置为控制信号，也可被配置为数据信号。GPIO接口还可以被配置为I2C接口，I2S接口，UART接口，MIPI接口等。
USB接口130是符合USB标准规范的接口，具体可以是Mini USB接口，Micro USB接口，USB Type C接口等。USB接口130可以用于连接充电器为电子设备100充电，也可以用于电子设备100与外围设备之间传输数据。也可以用于连接耳机，通过耳机播放音频等。
可以理解的是，本发明实施例示意的各模块间的接口连接关系，只是示意性说明，并不构成对电子设备100的结构限定。在本申请另一些实施例中，电子设备100也可以采用上述实施例中不同的接口连接方式，或多种接口连接方式的组合。
充电管理模块140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。
电源管理模块141用于连接电池142，充电管理模块140与处理器110。电源管理模块141接收电池142和/或充电管理模块140的输入，为处理器110，内部存储器121，显示屏194，摄像头193，和无线通信模块160等供电。电源管理模块141还可以用于监测电池容量，电池循环次数，电池健康状态(漏电，阻抗)等参数。在其他一些实施例中，电源管理模块141也可以设置于处理器110中。在另一些实施例中，电源管理模块141和充电管理模块140也可以设置于同一个器件中。
电子设备100的无线通信功能可以通过天线1，天线2，移动通信模块150，无线通信模块160，调制解调处理器以及基带处理器等实现。
天线1和天线2用于发射和接收电磁波信号。电子设备100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块150可以提供应用在电子设备100上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块150可以包括至少一个滤波器，开关，功率放大器，低噪声放大器(lownoise amplifier，LNA)等。移动通信模块150可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。移动通信模块150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器，受话器等)输出声音信号，或通过显示屏194显示图像或视频。
无线通信模块160可以提供应用在电子设备100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。无线通信模块160可以是集成至少一个通信处理模块的一个或多个器件。无线通信模块160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器110。无线通信模块160还可以从处理器110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
在一些实施例中，电子设备100的天线1和移动通信模块150电连接，天线2和无线通信模块160电连接，使得电子设备100可以通过无线通信技术与网络以及其他设备通信。所述无线通信技术可以包括全球移动通讯系统(global system formobile communications，GSM)，通用分组无线服务(general packet radio service，GPRS)，码分多址接入(code division multiple access，CDMA)等。
电子设备100通过GPU，显示屏194，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏194和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏194用于显示图像，视频等。在一些实施例中，电子设备100可以包括1个或N个显示屏194，N为大于1的正整数。
电子设备100可以通过ISP，摄像头193，视频编解码器，GPU，显示屏194以及应用处理器等实现拍摄功能。
ISP用于处理摄像头193反馈的数据。
摄像头193用于捕获静态图像或视频。在一些实施例中，电子设备100可以包括1个或N个摄像头193，N为大于1的正整数。
外部存储器接口120可以用于连接外部存储卡，例如Micro SD卡，实现扩展电子设备100的存储能力。外部存储卡通过外部存储器接口120与处理器110通信，实现数据存储功能。例如将音乐，视频等文件保存在外部存储卡中。
内部存储器121可以用于存储计算机可执行程序代码，所述可执行程序代码包括指令。内部存储器121可以包括存储程序区和存储数据区。其中，存储程序区可存储操作系统，至少一个功能所需的应用程序(比如声音播放功能，图像播放功能等)等。存储数据区可存储电子设备100使用过程中所创建的数据(比如音频数据，电话本等)等。此外，内部存储器121可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件，闪存器件，通用闪存存储器(universal flash storage，UFS)等。处理器110通过运行存储在内部存储器121的指令，和/或存储在设置于处理器中的存储器的指令，执行电子设备100的各种功能应用以及数据处理。
电子设备100可以通过音频模块170以及应用处理器等实现音频功能。例如音乐播放，录音等。
音频模块170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信号。音频模块170还可以用于对音频信号编码和解码。
按键190包括开机键，音量键等。按键190可以是机械按键。也可以是触摸式按键。电子设备100可以接收按键输入，产生与电子设备100的用户设置以及功能控制有关的键信号输入。
马达191可以产生振动提示。马达191可以用于来电振动提示，也可以用于触摸振动反馈。
指示器192可以是指示灯，可以用于指示充电状态，电量变化，也可以用于指示消息，未接来电，通知等。
SIM卡接口195用于连接SIM卡。SIM卡可以通过插入SIM卡接口195，或从SIM卡接口195拔出，实现和电子设备100的接触和分离。电子设备100可以支持1个或N个SIM卡接口，N为大于1的正整数。
在此基础上，上述的电子设备100还可以包括电路板，例如印刷电路板(printed circuit board，PCB)。上述的处理器110、内部存储器121等可以设置在电路板上，且处理器110和内部存储器121等与电路板电连接。
本申请实施例提供的存储器可以用于作为上述电子设备100中的内部存储器121，也可以用于作为上述电子设备100的处理器110中的存储器。
本申请实施例提供的存储器可以是片外存储器，也可以是片上存储器(也可以称为嵌入式存储器)。
此外，本申请实施例提供的存储器可以为基于BEOL(back end of line，后端)工艺制备的存储器。
参考图4，存储器200包括设置于衬底101上的至少一层存储阵列201。附图4以存储器200包括两层存储阵列201为例进行示意。在存储器200包括多层存储阵列201的情况下，如图4所示，存储阵列201可以沿竖直方向依次堆叠。
此外，在存储器200包括多层存储阵列201的情况下，存储器200也可以称为三维集成存储器。
另外，存储阵列201的层数可以根据需要进行堆叠，堆叠的存储阵列201的层数越多，存储器200的存储密度越高。
在存储器200包括多层存储阵列201的情况下，在一些实施例中，参考图4，存储器200还包括设置在相邻两层存储阵列201之间的第六介质层202，相邻两层存储阵列201通过第六介质层202间隔开。
其中，第六介质层202的材料可以为SiO 2(二氧化硅)、Al 2O 3(氧化铝)、HfO 2(二氧化铪)、ZrO 2(氧化锆)、TiO 2(二氧化钛)、Y 2O 3(三氧化二钇)和Si 3N 4(氮化硅)等绝缘材料中的一种或多种。
此处，第六介质层202可以为单层结构，也可以为多层的叠层结构。此外，单层结构的材料以及多层的叠层结构中的每一层的材料均可以为SiO 2、Al 2O 3、HfO 2、ZrO 2、TiO 2、Y 2O 3、Si 3N 4中的一种或多种。
参考图5和图6a，每层存储阵列201包括阵列分布的多个存储单元201A、写字线WWL(write word line)、写位线WBL(write bit line)、读字线RWL(read word line)以及读位线RBL(read bit line)。
参考图6a、图6b、图6c、图6d和图6e，存储单元201A包括层叠设置的第一薄 膜晶体管Tr0和第二薄膜晶体管Tr1。
第一薄膜晶体管Tr0包括栅极106a，栅极106a包括位于顶部的栅基底1061a和从栅基底1061a向底部延伸的栅极柱1062a。第一薄膜晶体管Tr0还包括第一极109a、第二极108a、第一介质层113a、第二介质层112a和半导体层102a，第一极109a位于底部，第二极108a位于第一极109a和栅基底1061a之间；第一介质层113a设置在第二极108a和第一极109a之间，第一介质层113a用于将第一极109a和第二极108a隔开；半导体层102a沿栅极柱1062a的侧面设置，且第二介质层112a将半导体层102a与栅极106a隔开；其中，第一极109a和第二极108a分别与半导体层102a电连接。
如图6a、图6b、图6c和图6d所示，第二介质层112a覆盖栅基底1061a的表面和栅极柱1062a的表面；进一步地，第二介质层112a在第一极109a上围绕在栅极柱1062a外侧，半导体层102a围绕在第二介质层112a外侧，以及第二极108a设置在半导体层102a外侧，且与半导体层102a电连接，第二极108a在第一极109a上且二者之间由第一介质层113a隔开，第一极109a与半导体层102a电连接。
第二薄膜晶体管Tr1包括栅极106b，栅极106b包括位于顶部的栅基底1061b和从栅基底1061b向底部延伸的栅极柱1062b。第二薄膜晶体管Tr1还包括第一极109b、第二极108b、第一介质层113b、第二介质层112b和半导体层102b；第一极109b位于底部，第二极108b位于第一极109a和栅基底1061a之间；第一介质层113b设置在第二极108b和第一极109b之间，第一介质层113b用于将第一极109b和第二极108b隔开；第二介质层112b覆盖栅基底1061b的表面和栅极柱1062b的表面；半导体层102b沿栅极柱1062b的侧面设置，且第二介质层112b将半导体层102b与栅极106b隔开；其中，第一极109b和第二极108b分别与半导体层102b电连接。
如图6a、图6b、图6c和图6d所示，第二介质层112b在第一极109b上围绕在栅极柱1062b外侧，半导体层102b围绕在第二介质层112b外侧，第二极108b设置在半导体层102b外侧，且与半导体层102b电连接，第二极108b在第一极109b上且二者之间由第一介质层113b隔开，第一极109b与半导体层102b电连接。
其中，第二薄膜晶体管Tr1的栅极106b(gate，G)与写字线WWL电连接，第二极108b与写位线WBL电连接；第一薄膜晶体管Tr0的第一极109a和第二极108a分别与读字线RWL、读位线RBL电连接；第二薄膜晶体管Tr1的第一极109b靠近第一薄膜晶体管Tr0的栅极106a，且第二薄膜晶体管Tr1的第一极109b与第一薄膜晶体管Tr0的栅极106a电连接。
其中，图6b为图6a中第一方向X的剖面示意图；图6c为图6a中第二方向Y的剖面示意图；图6d为一种图6b或图6c中AA向的剖面示意图；图6e为另一种图6b或图6c中AA向的剖面示意图。
可以理解的是，本申请实施例提供的存储器200是基于2T0C结构的gain cell结构的存储器。
在一些实施例中，第二薄膜晶体管Tr1的第一极109b与第一薄膜晶体管Tr0的栅极106a直接接触。在另一些实施例中，参考图6a、图6b和图6c，第二薄膜晶体管Tr1的第一极109b与第一薄膜晶体管Tr0的栅极106a均与连接电极111接触，第二薄膜晶体管Tr1的第一极109b与第一薄膜晶体管Tr0的栅极106a通过连接电极111电 连接在一起。
需要说明的是，上述第二薄膜晶体管Tr1为写晶体管，第一薄膜晶体管Tr0为读晶体管。
上述第二薄膜晶体管Tr1和第一薄膜晶体管Tr0的结构可以相同，也可以不相同。应当理解到，在一些实施例中，第二薄膜晶体管Tr1在衬底上的投影和第一薄膜晶体管Tr0在衬底上的投影重叠。
应当理解到，写字线WWL可以与第二薄膜晶体管Tr1的栅极106b同步制作，写位线WBL可以与第二薄膜晶体管Tr1的第二极108b同步制作。
此处，可以是第一薄膜晶体管Tr0的第二极108a与读字线RWL电连接，第一极109a与读位线RBL电连接，在此情况下，第一薄膜晶体管Tr0的第二极108a和读字线RWL可以同步制作，第一薄膜晶体管Tr0的第一极109a和读位线RBL可以同步制作；也可以是第一薄膜晶体管Tr0的第二极108a与读位线RBL电连接，第一极109a与读字线RWL电连接，在此情况下，第一薄膜晶体管Tr0的第二极108a与读位线RBL可以同步制作，第一薄膜晶体管Tr0的第一极109a与读字线RWL可以同步制作。
在本申请的实施例中，对于第一薄膜晶体管Tr0，可以是第二极108a为源极(source，S)103，第一极109a为漏极(drain，D)104，也可以是第二极108a为漏极104，第一极109a为源极103。对于第二薄膜晶体管Tr1，可以是第二极108b为源极103，第一极109b为漏极104，也可以是第二极108b为漏极104，第一极109b为源极103。
另外，上述的第一薄膜晶体管Tr0和第二薄膜晶体管Tr1可以均为N型管，也可以均为P型管，当然还可以是，第一薄膜晶体管Tr0和第二薄膜晶体管Tr1中的一个为N型管，另一个为P型管。
在一些实施例中，每层存储阵列201包括的多个第一薄膜晶体管Tr0可以同步制作；和/或，每层存储阵列201包括的多个第二薄膜晶体管Tr1可以同步制作。
参考图5，以下以一个存储单元201A为例，对存储器200的写操作过程和读操作过程进行说明。
写操作过程：在写操作过程中，读字线RWL和读位线RBL的电压为0，第一薄膜晶体管Tr0不工作；写字线WWL提供第一开关信号，第一开关信号控制第二薄膜晶体管Tr1导通。当写入第一逻辑信息，第一逻辑信息例如为“0”时，写位线WBL提供第一电平信号，第一电平信号通过第二薄膜晶体管Tr1写入节点N；其中，第一电平信号可以控制第一薄膜晶体管Tr0导通。当写入第二逻辑信息，第二逻辑信息例如为“1”时，写位线WBL提供第二电平信号，第二电平信号通过第二薄膜晶体管Tr1写入节点N；其中，第二电平信号可以控制第一薄膜晶体管Tr0关断。
应当理解到，在写操作完成之后，读字线RWL和读位线RBL的电压为0，第一薄膜晶体管Tr0不工作；写字线WWL提供第二开关信号，第二开关信号控制第二薄膜晶体管Tr1关断，此时，节点N存储的电位不受外界影响。
读操作过程：写字线WWL提供第二开关信号，第二开关信号控制第二薄膜晶体管Tr1关断；读字线RWL提供第三电平信号，根据读位线RBL上电流的高低判断存储单元201A的存储的逻辑信息。当节点N存储的是第一电平信号时，由于第一电平 信号可以控制第一薄膜晶体管Tr0导通，因而在读字线RWL提供第三电平信号时，读字线RWL通过第一薄膜晶体管Tr0对读位线RBL充电，读位线RBL上的电压升高，这样一来，当检测到读位线RBL上的电流较大时，则可以读出存储单元201A存储的是逻辑信息“0”。当节点N存储的是第二电平信号时，由于第二电平信号可以控制第一薄膜晶体管Tr0关断，因此在读字线RWL提供第三电平信号时，读字线RWL不会通过第一薄膜晶体管Tr0对读位线RBL充电，读位线RBL维持0V电压，这样一来，当检测到读位线RBL上电流较小时，则可以读出存储单元201A存储的是逻辑信息“1”。
对于多个第二薄膜晶体管Tr1，在一些实施例中，参考图5、图6a和图6b，每层存储阵列201中沿第一方向X依次排列的多个存储单元201A中的第二薄膜晶体管Tr1的栅极106b与同一条写字线WWL电连接；参考图5、图6a和图6c，每层存储阵列201A中沿第二方向Y依次排列的多个存储单元201A中的第二薄膜晶体管Tr1的第二极108b与同一条写位线WBL电连接；其中，第一方向X和第二方向Y相交。
在一些示例中，第一方向X和第二方向Y正交。以下为了方便说明，以第一方向X为行方向，第二方向Y为列方向为例。
由于每层存储阵列201中沿第一方向X依次排列的多个存储单元201A中的第二薄膜晶体管Tr1的栅极106b与同一条写字线WWL电连接，沿第二方向Y依次排列的多个存储单元201A中的第二薄膜晶体管Tr1的第二极108b与同一条写位线WBL电连接，因而在写操作过程中，可以逐行给多条写字线WWL提供第一开关信号，以使多行第二薄膜晶体管Tr1逐行导通，在当前行的写字线WWL提供第一开关信号的情况下，通过多条写位线WBL给与当前行的写字线WWL电连接的多个存储单元201A同时写入逻辑信息，从而可以逐行给存储单元201A写入逻辑信息，以实现存储阵列201中的多个存储单元201A的快速写入。
对于多个第一薄膜晶体管Tr0，示例性地可以采用以下四种方式连接。
在第一薄膜晶体管Tr0的第一极109a与读位线RBL电连接，第二极108a与读字线RWL电连接的情况下，可以采用以下第一种方式或第二种方式。
第一种方式：参考图5、图6a和图6b，每层存储阵列201中沿第一方向X依次排列的多个存储单元201A中的第一薄膜晶体管Tr0的第二极108a与同一条读字线RWL电连接；参考图5、图6a和图6c，每层存储阵列201中沿第二方向Y依次排列的多个存储单元201A中的第一薄膜晶体管Tr0的第一极109a与同一条读位线RBL电连接；其中，第一方向X和第二方向Y相交。
由于每层存储阵列201中沿第一方向X依次排列的多个存储单元201A中的第一薄膜晶体管Tr0的第二极108a与同一条读字线RWL电连接，沿第二方向Y依次排列的多个存储单元201A中的第一薄膜晶体管Tr0的第一极109a与同一条读位线RBL电连接，因而在读操作过程中，可以逐行给多条读字线RWL提供第三电平信号，在当前行的读字线RWL提供第三电平信号的情况下，通过检测每条读位线RBL上的电流，这样便可以同时读出与当前行的读字线RWL电连接的多个存储单元201A所存储的逻辑信息，从而可以逐行读取存储单元201A存储的逻辑信息，以可以实现存储阵列201中的多个存储单元201A的快速读取。
第二种方式：每层存储阵列201中沿第二方向Y依次排列的多个存储单元201A 中的第一薄膜晶体管Tr0的第二极108a与同一条读字线RWL电连接；每层存储阵列201中沿第一方向X依次排列的多个存储单元201A中的第一薄膜晶体管Tr0的第一极109a与同一条读位线RBL电连接；其中，第一方向X和第二方向Y相交。
在第一薄膜晶体管Tr0的第一极109a与读字线RWL电连接，第二极108a与读位线RBL电连接的情况下，可以采用以下第三种方式或第四种方式。
第三种方式：每层存储阵列201中沿第一方向X依次排列的多个存储单元201A中的第一薄膜晶体管Tr0的第二极108a与同一条读位线RWL电连接；每层存储阵列201中沿第二方向Y依次排列的多个存储单元201A中的第一薄膜晶体管Tr0的第一极109a与同一条读字线RWL电连接；其中，第一方向X和第二方向Y相交。
第四种方式：每层存储阵列201中沿第二方向Y依次排列的多个存储单元201A中的第一薄膜晶体管Tr0的第二极108a与同一条读位线RWL电连接；每层存储阵列201中沿第一方向X依次排列的多个存储单元201A中的第一薄膜晶体管Tr0的第一极109a与同一条读字线RWL电连接；其中，第一方向X和第二方向Y相交。
需要说明的是，上述第二种方式、第三种方式、第四种方式具有与上述第一种方式相同的技术效果，可以参考上述对第一种方式的技术效果的描述，此处不再赘述。
基于上述，对于每层存储阵列201，可以沿第一方向X和/或第二方向Y增加存储单元201A的个数，以实现更大规模的存储阵列。
参考图7，在一些实施例中，存储器200还包括集成电路203；存储阵列201设置于集成电路203上。此时，存储器200为片上存储器。在此情况下，存储器200中的衬底为集成电路203。
此处，集成电路203的衬底可以是硅衬底，即集成电路203可以是硅衬底的集成电路。
此外，上述集成电路203可以是存储阵列201的控制电路，也可以是其它功能电路。
需要说明的是，由于制作薄膜晶体管的工艺温度较低，因而可以将存储阵列201集成于集成电路203的后道。此外，可以在集成电路203上实现多层存储阵列201的堆叠，以实现3D系统集成。
在一些示例中，存储阵列201中的存储单元201A可以与集成电路203电连接。例如，存储阵列201中的存储单元201A可以通过互联线连接至下方的集成电路203上。
本申请实施例还提供一种薄膜晶体管10，该薄膜晶体管可以作为上述的第一薄膜晶体管Tr0，也可以作为上述的第二薄膜晶体管Tr1。
以下对薄膜晶体管10的结构进行详细介绍。
参考图8a、图8b和图8c，薄膜晶体管10包括栅极106、第一极109、第二极108、第一介质层113、第二介质层112以及半导体层102。
其中，栅极106包括位于顶部的栅基底1061和从栅基底1061向底部延伸的栅极柱1062；第一极109位于底部；第二极108位于第一极109和栅基底1061之间；第一介质层113设置在第二极108和第一极109之间，第一介质层113用于将第一极109和第二极108隔开；第二介质层112覆盖栅基底1061的表面和栅极柱1062的表面； 半导体层102沿栅极柱1062的侧面设置，且第二介质层112将半导体层102与栅极106隔开。第一极109和第二极108分别与半导体层102电连接。
图8b为一种图8a中BB向的剖面示意图；图8c为另一种图8a中BB向的剖面示意图。
如图8a和图8b所示，第二介质层112在第一极109上围绕在栅极柱1062外侧，半导体层102围绕在第二介质层112外侧，第二极108设置在半导体层102外侧，且与半导体层102电连接，第二极108在第一极109上且二者之间由第一介质层113隔开，第一极109与半导体层102电连接。
需要说明的是，栅极柱1062包括与栅基底1061接触的表面、远离栅基底1061的表面以及侧面。其中，与栅基底1061接触的表面和远离栅基底1061的表面是相对设置的。
在一些实施例中，栅极柱1062和栅基底1061一体成型。在另一些实施例，栅极柱1062和栅基底1061分别单独制作。
在一些示例中，栅极柱1062垂直于栅基底1061设置。
此处，第一极109与半导体层102形成欧姆接触，第二极108与半导体层102形成欧姆接触。此外，第一极109与半导体层102电连接，可以是第一极109与半导体层102直接接触，也可以是第一极109与半导体层102不直接接触，而是通过其它介质电连接。同样的，第二极108与半导体层102电连接，可以是第二极108与半导体层102直接接触，也可以是第二极108与半导体层102不直接接触，而是通过其它介质电连接。
需要说明的是，可以是薄膜晶体管10中的第一极109为漏极，第二极108为源极，也可以是薄膜晶体管10中的第一极109为源极，第二极108为漏极。
此外，薄膜晶体管10可以是N型管，也可以是P型管。
另外，由于第二介质层112覆盖栅基底1061a的表面和栅极柱1062的表面，因而如图8a所示，第二介质层112包括第一介质部分1121和第二介质部分1122，第一介质部分1121覆盖栅基底1061的表面，第二介质部分1122覆盖栅极柱1062的表面。
基于此，在一些实施例中，第一介质部分1121和第二介质部分1122同步制作。在另一些实施例中，第一介质部分1121和第二介质部分1122可以分别单独制作。
考虑到第一极109和第二极108之间的距离若太近，则在制作第一极109和第二极108时可能会存在第一极109和第二极108直接导通的风险。为了避免第一极109和第二极108直接导通，因此在一些实施例中，第二极108靠近栅基底1061设置。
应当理解到，上述栅极106、第一极109和第二极108的材料均为导电材料，例如金属材料。具体的，栅极106、第一极109和第二极108的材料可以为TiN(氮化钛)、Ti(钛)、Au(金)、W(钨)、Mo(钼)、In-Ti-O(ITO，氧化铟锡)、Al(铝)、Cu(铜)、Ru(钌)、Ag(银)等导电材料中的一种或多种。
上述第一介质层113的材料和第二介质层112的材料可以参考上述第六介质层202的材料，此处不再赘述。此外，第一介质层113和第二介质层112可以为单层结构，也可以为多层的叠层结构。
上述半导体层102的材料可以为Si(硅)、poly-Si(p-Si，多晶硅)、amorphous-Si (a-Si，非晶硅)、In-Ga-Zn-O(IGZO，铟镓锌氧化物)多元化合物、ZnO(氧化锌)、ITO、TiO 2(二氧化钛)、MoS 2(二硫化钼)等半导体材料中的一种或多种。
本申请实施例提供一种薄膜晶体管10，薄膜晶体管10的栅极106包括位于顶部的栅基底1061和从栅基底1061向底部延伸的栅极柱1062，由于半导体层102沿栅极柱1062的侧面设置，且第一极109位于底部，第二极108位于第一极109和栅基底1061之间，第一极109和第二极108分别与半导体层102电连接，相对于现有技术中，半导体层102沿平行于栅极106(现有技术中的栅极106相当于本申请实施例中的栅基底1061)的平面设置，且第二极108和第一极109同层设置，因而本申请实施例提供的薄膜晶体管10在平行于栅基底1061的平面上的尺寸较小，因此本申请实施例降低了薄膜晶体管10的尺寸，提高了面积利用率。此外，由于本申请实施例中的薄膜晶体管10的第二极108和第一极109位于不同层，因此可以避免与第二极108电连接的信号线和与第一极109电连接的信号线在布线时出现短路，降低了工艺难度。
在存储器200中第一薄膜晶体管Tr0和第二薄膜晶体管Tr1的结构为上述薄膜晶体管10时，可以降低存储器200中第一薄膜晶体管Tr0和第二薄膜晶体管Tr1的尺寸，提高面积利用率。
对于上述栅极106的结构，示例性地可以采用以下三种实现方式。
第一种：如图8a、图9、图10、图11所示，栅极柱1062在栅基底1061上的投影的边界位于栅基底1061的边界内，即栅极柱1062设置在栅基底1061的中间区域。
第二种：如图12a和图12c所示，栅极柱1062在栅基底1061上的投影的边界与栅基底1061的边界部分重叠，即栅极柱1062设置在栅基底1061的边缘区域。
第三种：如图12b所示，栅极柱1062为中空结构；栅极柱1062在栅基底1061上的投影的外边界与栅基底11061的边界重叠。
应当理解到，由于栅极柱1062为中空结构，因而栅极柱1062在栅基底1061上的投影包括两个边界，分别为外边界和内边界。将靠近栅基底1061中心的边界称为内边界，将远离栅基底10161中心的边界称为外边界。
此外，由于栅极柱1062为中空结构，且栅极柱1062在栅基底1061上的投影的外边界与栅基底11061的边界重叠，因而第二介质层112的至少部分区域位于中空结构内，半导体层102的至少部分区域位于中空结构内，第二极108位于中空结构内，第一介质层113的至少部分区域位于中空结构内。
此处，在栅极柱1062为中空结构的情况下，栅极106从半导体层102的外侧对半导体层102内的电流进行调控。
对于上述半导体层102的结构，示例性地可以采用以下四种实现方式。
第一种：如图8a所示，半导体层102仅沿栅极柱1062的侧面设置。
如图8a所示，半导体层102仅包围栅极柱1062的侧面，且设置在第一极109上。
此处，第二极108、第一极109与半导体层102为端电连接或端接触。
第二种：图12c所示，半导体层102沿栅极柱1062的侧面设置，且半导体层102还包括沿栅基底1061的表面延伸的延伸部。第二介质层112将半导体层102与栅极106隔开。此外，如图12c所示，半导体层102设置在第一介质层113、第二极108的侧面，且覆盖第二极108顶面。
在一些示例中，如图12c所示，半导体层102还设置在第一极109的侧面。
第三种：如图9所示，半导体层102沿栅极柱1062的侧面设置，且半导体层102由栅极柱1062的侧面延伸至栅极柱1062的远离栅基底1061一侧，即位于栅极柱1062和第一极109之间，即半导体层102还包括位于栅极柱1062和第一极109之间的延伸部。此外，如图9所示，半导体层102覆盖第二介质层112的侧面和底部的表面。
在一些示例中，如图9所示，半导体层102设置在第一极109上。
第四种：如图10、图11、图12a和图12b所示，半导体层102沿栅极柱1062的侧面设置，且半导体层102还包括沿栅基底1061的表面延伸的延伸部以及位于栅极柱1062和第一极109之间的延伸部。此时，半导体层102呈“Z”字型。也可以说，如图10、图12a和图12b所示，半导体层102覆盖第二介质层112的侧面、底面和顶面。或者，如图11所示，半导体层102覆盖第二介质层112的侧面和底面，还覆盖第二极108的底面。
在一些示例中，如图10、图11、图12a和图12b所示，半导体层102设置在第一极109上。
在一些实施例中，如图8b所示，半导体层102围绕栅极柱1062的侧面设置一圈。在此情况下，可以是半导体层102包围栅极柱1062的整个侧面；也可以是半导体层102围绕栅极柱1062的侧面的一部分。
由于半导体层102围绕栅极柱1062的侧面设置一圈，因而可以增大半导体层102的面积，提高载流子迁移率。
对于上述的第二极108，在一些实施例中，可以是如图8a、图9、图10、图12a和图12b所示，第二极108设置在半导体层102远离第二介质层112的一侧。
应当理解到，在半导体层102还包括沿栅基底1061的表面延伸的延伸部的情况下，第二极108设置在半导体层102远离第二介质层112的一侧时，如图10、图12a和图12b所示，第二极108与第二介质层112不接触，二者之间被半导体层102隔开。在半导体层102沿栅极柱1062的侧面设置，且半导体层102不包括沿栅基底1061的表面延伸的延伸部的情况下，如图8a和图9所示，第二极108设置在半导体层102远离第二介质层112的一侧时，第二极108与第二介质层112接触。
在另一些实施例中，可以是如图11所示，第二极108设置在半导体层102靠近第二介质层112的一侧。在此情况下，第二极108位于第二介质层112和半导体层102之间。
此外，上述第二极108可以围绕栅极柱1062的侧面设置一圈，第二极108也可以绕栅极柱1062的侧面设置，但不是完整的一圈。
对于上述第一极109，第一极109位于底部，即第一极109设置在第二极108远离栅基底1061的一侧，在一些实施例中，可以是如图8a、图9、图10、图11、图12a和图12b所示，第一极109设置在栅极柱1062远离栅基底1061的一侧。在此情况下，半导体层102设置在第一极109上。在另一些实施例中，如图12c所示，第一极109设置在栅极柱1062的侧面。在此情况下，半导体层102还可以沿第一极109的侧面延伸。
在一些实施例中，如图13所示，上述薄膜晶体管10还包括：设置在第二极108 和半导体层102之间的第四介质层114；和/或，设置在第一极109和半导体层102之间的第五介质层115。
此处，第四介质层114的材料和第五介质层115的材料可以参考上述第六介质层202的材料，此处不再赘述。此外，第四介质层114和第五介质层115可以为单层结构，也可以为多层的叠层结构。
需要说明的是，第四介质层114设置在第二极108和半导体层102之间，第二极108和半导体层102可以接触，也可以不接触。第五介质层115设置在第一极109和半导体层102之间，第一极109和半导体层102可以接触，也可以不接触。
为了确保在栅极106上提供有电压时，第一极109和第二极108之间能够通过半导体层102导通，因而在一些实施例中，第四介质层114和第五介质层115的厚度范围均为0.1nm～2nm。
示例的，第四介质层114和第五介质层115的厚度可以是0.1nm、0.5nm、1nm、1.5nm和2nm等。
由于第四介质层114和第五介质层115的厚度较小，厚度范围为0.1nm～2nm，因而即使第四介质层114设置在第二极108和半导体层102之间，和/或，第五介质层115设置在第一极109和半导体层102之间，在栅极106上提供有电压时，第一极109和第二极108还是能够通过半导体层102导通，不会影响薄膜晶体管10的性能。此外，在第二极108和半导体层102之间设置第四介质层114，可以避免第二极108在与半导体层102接触区域的扩散问题，降低第二极108和半导体层102接触的费米能级钉扎问题。在第一极109和半导体层102之间设置第五介质层115，可以避免第一极109在与半导体层102接触区域的扩散问题，降低第一极109和半导体层102接触的费米能级钉扎问题。
在一些实施例中，上述第二介质层112的材料为铁电材料；在此情况下，如图14所示，上述薄膜晶体管10还包括：设置在半导体层102和第二介质层112之间的第三介质层116。
此处，第三介质层116的材料可以参考上述第六介质层202的材料，此处不再赘述。此外，第三介质层116可以为单层结构，也可以为多层的叠层结构。
可以理解的是，在第二介质层112的材料为铁电材料的情况下，栅极106、第二介质层112和第三介质层116构成复合栅结构，通过该复合栅结构，薄膜晶体管10可以实现负电容晶体管性能，利用负电容可以提高薄膜晶体管10的栅控能力。在薄膜晶体管10应用于存储器200中时，可以提高存储器200的性能。
需要说明的是，本申请实施例中，第一介质层113、第二介质层112、第三介质层116、第四介质层114和第五介质层115的材料可以相同，也可以不相同。
在此基础上，在第二介质层112的材料为铁电材料，薄膜晶体管10包括第三介质层116的情况下，如图15所示，薄膜晶体管10还包括：设置在第二介质层112和第三介质层116之间的第一导电层117。
其中，第一导电层117的材料可以参考上述栅极106、第一极109和第二极108的材料，此处不再赘述。
此处，栅极106、第二介质层112、第一导电层117和第三介质层116构成的复合 栅结构，可以使薄膜晶体管10实现负电容晶体管性能，利用负电容可以提高薄膜晶体管10的栅控能力。在薄膜晶体管10应用于存储器200中时，可以提高存储器200的性能。
在一些实施例中，如图16所示，上述薄膜晶体管10还包括：设置在第一极109和第二极108之间的调制栅电极118，且调制栅电极118由第一介质层113包围。
此处，调制栅电极118的材料可以参考上述栅极106、第一极109和第二极108的材料，此处不再赘述。
需要说明的是，调制栅电极118由第一介质层113包围，从而与第一极109、第二极108和半导体层102间隔开，即调制栅电极118通过第一介质层113与第一极109、第二极108和半导体层102进行电学隔离。
本申请实施例中，由于薄膜晶体管10包括调制栅电极118，因而可以通过调制栅电极118对薄膜晶体管10的阈值电压进行调节。
在上述薄膜晶体管10作为存储器200中的第一薄膜晶体管Tr0和第二薄膜晶体管Tr1的情况下，如图17a、图17b和图17c所示，在存储器200中，第一薄膜晶体管Tr0还包括设置在第一极109a和第二极108a之间的第一调制栅电极118a，且第一调制栅电极118a设置在半导体层102a远离栅极柱1062a的一侧，第一调制栅电极118a由第一介质层113a包围，从而与第一极109a、第二极108a和半导体层102a间隔开；位于同一层的多个第一薄膜晶体管Tr0的第一调制栅电极118a电连接在一起；和/或，第二薄膜晶体管Tr1还包括设置在第一极109b和第二极108b之间的第二调制栅电极118b，且第二调制栅电极118b设置在半导体层102b远离栅极柱1062b的一侧，第二调制栅电极118b由第一介质层113b包围，从而与第一极109b、第二极108b和半导体层102b间隔开；位于同一层的多个第二薄膜晶体管Tr1的第二调制栅电极118b电连接在一起。
需要说明的是，图17b和图17c均为图17a中沿CC向的剖面示意图。
此处，位于同一层的多个第一薄膜晶体管Tr0的第一调制栅电极118a电连接在一起，可以是位于同一层的多个第一薄膜晶体管Tr0的第一调制栅电极118a全部电连接在一起，也可以是位于同一层的多个第一薄膜晶体管Tr0的第一调制栅电极118a中的部分第一调制栅电极118a电连接在一起。同理，位于同一层的多个第二薄膜晶体管Tr1的第二调制栅电极118b电连接在一起，可以是位于同一层的多个第二薄膜晶体管Tr1的第二调制栅电极118b全部电连接在一起，也可以是位于同一层的多个第二薄膜晶体管Tr1的第二调制栅电极118b中的部分第二调制栅电极118b电连接在一起。
示例的，如图17b所示，位于同一层的四个第一薄膜晶体管Tr0中的第一调制栅电极118a电连接在一起，这样一来，可以实现对四个存储单元201A的共同调制。
需要说明的是，在实际应用中，可以根据需要选择存储单元201A共同调制的数量。
其中，第一调制栅电极118a的材料和第二调制栅电极118b的材料可以参考上述栅极106、第一极109和第二极108的材料，此处不再赘述。
由于第一薄膜晶体管Tr0包括第一调制栅电极118a，因而可以通过第一调制栅电极118a对第一薄膜晶体管Tr0的阈值电压进行调节。由于第二薄膜晶体管Tr1包括第 二调制栅电极118b，因而可以通过第二调制栅电极118b对第二薄膜晶体管Tr1的阈值电压进行调节。基于此，可以对存储器200的存储性能进行更加灵活的调节。示例的，对于第一薄膜晶体管Tr0，可以将第一调制栅电极118a的电位设置的较低，使得第一薄膜晶体管Tr0的第一极109a和第二极108a的泄露电流降低，实现更长的存储保持时间。此外，可以将第二薄膜晶体管Tr1中第二调制栅电极118b的电位设置的较高，使得第二薄膜晶体管Tr1的整体电流增大，提高数据读取速度。
本申请实施例还提供一种薄膜晶体管10的制作方法，可以用于制作上述的薄膜晶体管10。参考图18，该薄膜晶体管10的制作方法包括：
S10、在衬底上形成第一极109、第一介质层113、第二极108以及半导体层102。其中，第一极109、第一介质层113和第二极108依次层叠设置，第一介质层113将第一极109和第二极108隔开；半导体层102形成在第一介质层113的侧面；第一极109和第二极108均与半导体层102电连接。
需要说明的是，对于第一极109、第一介质层113、第二极108和半导体层102的形成顺序不做限定。
此处，可以是第一极109和第二极108均与半导体层102直接接触；也可以是第一极109和第二极108分别通过其它介质层与半导体层102接触。
此外，对于第一极109、第一介质层113、第二极108以及半导体层102的材料可以参考上述实施例，此处不再赘述。
另外，第一介质层113包括靠近第二极108的表面、靠近第一极109的表面以及侧面，其中，靠近第二极108的表面和靠近第一极109的表面相对设置。
在此基础上，可以是形成第一极109作为漏极，形成第二极108作为源极；也可以是形成第一极109作为源极，形成第二极1081作为漏极。
S11、依次形成第二介质层112和栅极106；栅极106包括位于顶部的栅基底1061和从栅基底1061向底部延伸的栅极柱1062，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，对于第二介质层112的材料，可以参考上述实施例，此处不再赘述。
此外，对于栅极106的材料，可以参考上述实施例，此处不再赘述。
需要说明的是，可以同时形成栅基底1061和栅极柱1062，也可以分别形成栅基底1061和栅极柱1062。
基于上述，本申请实施例在制作薄膜晶体管10时，可以依次执行步骤S10和S11，也可以依次执行步骤S11和S10。
本申请实施例提供一种薄膜晶体管10的制作方法，由于本申请实施例提供的薄膜晶体管10的制作方法具有与上述薄膜晶体管10相同的技术效果，因而可以参考上述，此处不再赘述。
以下对薄膜晶体管10的制作方法的具体实现方式进行举例说明。
实施例一
例如制作如图8a所示的薄膜晶体管10，具体包括如下步骤：
S100、如图19所示，在衬底101上依次形成层叠的第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
此处，可以利用化学气相沉积、物理气相沉积、溅射、电镀等方法依次形成第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
S101、如图19所示，对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图，形成依次层叠的第一极109、第一介质层113和第二极108；其中，第一极109、第一介质层113和第二极108构成凹槽结构。
此处，可以利用干法刻蚀或湿法刻蚀对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图。
此外，可以对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080分别进行单独刻蚀，也可以对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080同时进行刻蚀。
S102、如图19所示，形成半导体层102；半导体层102形成在凹槽结构的侧壁，即半导体层102形成在第一介质层113和第二极108的侧面；第一极109和第二极108均与半导体层102电连接。
此处，可以先利用外延生长法形成半导体薄膜，半导体薄膜是整层的，覆盖第一极109、第一介质层113和第二极108裸露的表面；再对半导体薄膜进行刻蚀，除了形成在凹槽的侧壁的半导体薄膜外，形成在其它部分例如凹槽的底部、第二极108的顶面以及凹槽的外侧的半导体薄膜被刻蚀掉，从而形成半导体层102。
上述的外延生长法例如包括化学气相沉积、物理气相沉积、溅射、电镀等工艺。
S103、如图19所示，形成第二介质层112；第二介质层112覆盖半导体层102、第二极108和第一极109。
需要说明的是，该步骤S103可以采用两种方式实现。第一种，可以利用化学气相沉积、物理气相沉积、溅射或电镀等方法直接形成第二介质层112，此时第二介质层112是整层的，覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的表面。第二种，可以先利用化学气相沉积、物理气相沉积、溅射或电镀等形成第七介质薄膜，第七介质薄膜覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的表面；再对第七介质薄膜进行刻蚀，除了形成在凹槽侧面、底部和第二极108的顶面、第一半导体层102的顶面的部分外，其它第七介质薄膜均被刻蚀掉，从而形成第二介质层112。此处，第一种方式附图未示意出。
S104、如图19所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062伸入凹槽结构内，即栅极柱1062沿第一介质层113和第二极108的侧面延伸；栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，形成栅极106的过程具体可以为：先形成导电薄膜，再对导电薄膜进行刻蚀形成栅极106。
实施例二
例如制作如图9所示的薄膜晶体管10，具体包括如下步骤：
S110、如图20所示，在衬底101上依次形成层叠的第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
此处，该步骤S110的具体实现过程可以参考上述步骤S100，此处不再赘述。
S111、如图20所示，对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图，形成依次层叠的第一极109、第一介质层113和第二极108；其中，第一极109、第一介质层113和第二极108构成凹槽结构。
此处，该步骤S111的具体实现过程可以参考上述步骤S101，此处不再赘述。
S112、如图20所示，形成半导体层102；半导体层102形成在凹槽结构的侧壁和底部，即半导体层102形成在第一介质层113和第二极108的侧面，半导体层102还由第一介质层113和第二极108的侧面延伸至第一极109靠近第二极108一侧的表面，即第一极109的顶面；第一极109和第二极108均与半导体层102电连接。
此处，可以先利用外延生长法形成半导体薄膜，半导体薄膜是整层的，覆盖第一极109、第一介质层113和第二极108裸露的表面；再对半导体薄膜进行刻蚀，除了形成在凹槽的侧壁和底部的半导体薄膜外，形成在其它部分例如第二极108的顶面以及凹槽的外侧的半导体薄膜被刻蚀掉，从而形成半导体层102。
S113、如图20所示，形成第二介质层112；第二介质层112覆盖半导体层102和第二极108。
此处，该步骤S113的具体实现过程可以参考上述步骤S103，此处不再赘述。
S114、如图20所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062伸入凹槽结构内，即栅极柱1062沿第一介质层113和第二极108的侧面延伸；栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S114的具体实现过程可以参考上述步骤S104，此处不再赘述。
实施例三
例如制作如图10所示的薄膜晶体管10，具体包括如下步骤：
S120、如图21所示，在衬底101上依次形成层叠的第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
此处，该步骤S120的具体实现过程可以参考上述步骤S100，此处不再赘述。
S121、如图21所示，对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图，形成依次层叠的第一极109、第一介质层113和第二极108；其中，第一极109、第一介质层113和第二极108构成凹槽结构。
此处，该步骤S121的具体实现过程可以参考上述步骤S101，此处不再赘述。
S122、如图21所示，形成半导体层102；半导体层102形成在凹槽结构的侧壁和底部，以及第二极108远离第一极109一侧的表面，即半导体层102形成在第一介质层113和第二极108的侧面，半导体层102还由第一介质层113和第二极108的侧面延伸至第二极108远离第一极109一侧的表面(即第二极108的顶面)以及第一极109靠近第二极108一侧的表面(即第一极109的顶面)；第一极109和第二极108均与半导体层102电连接。
此处，可以先利用外延生长法形成半导体薄膜，半导体薄膜是整层的，覆盖第一极109、第一介质层113和第二极108裸露的表面；再对半导体薄膜进行刻蚀，除了 形成在凹槽的侧壁、底部和第二极108的顶面的半导体薄膜外，形成在凹槽的外侧的半导体薄膜被刻蚀掉，从而形成半导体层102。
S123、如图21所示，形成第二介质层112；第二介质层112覆盖半导体层102。
此处，该步骤S123的具体实现过程可以参考上述步骤S103，此处不再赘述。
S124、如图21所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062伸入凹槽结构内，即栅极柱1062沿第一介质层113和第二极108的侧面延伸；栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S124的具体实现过程可以参考上述步骤S104，此处不再赘述。
需要说明的是，上述实施例一、实施例二和实施例三的区别之处在于形成的半导体层102的结构不同。
实施例四
例如制作如图13所示的薄膜晶体管10，具体包括如下步骤：
S130、如图22所示，在衬底101上依次形成层叠的第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
此处，该步骤S130的具体实现过程可以参考上述步骤S100，此处不再赘述。
S131、如图22所示，对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图，形成依次层叠的第一极109、第一介质层113和第二极108；其中，第一极109、第一介质层113和第二极108构成凹槽结构。
此处，该步骤S131的具体实现过程可以参考上述步骤S101，此处不再赘述。
S132、如图22所示，在凹槽结构的底部形成第五介质层115，即在第一极109的顶面形成第五介质层115；其中，第五介质层115与第一极109接触。
此处，形成第五介质层115的过程具体可以是：先形成第五介质薄膜，再对第五介质薄膜进行刻蚀形成第五介质层115。
S133、如图22所示，在第二极108远离第一极109的一侧形成第四介质层114，即在第二极108的顶面上形成第四介质层114；其中，第四介质层114与第二极108接触。
此处，形成第四介质层114的过程具体可以是：先形成第六介质薄膜，再对第六介质薄膜进行刻蚀形成第四介质层114。
需要说明的是，步骤S132和步骤S133可以分步执行，在此情况下，可以先执行步骤S132，再执行步骤S133；也可以先执行步骤S133，再执行步骤S132。步骤S132和步骤S133也可以同步执行，即同时形成第四介质层114和第五介质层115。
S134、如图22所示，形成半导体层102；半导体层102形成在凹槽结构的侧壁和底部，以及第四介质层114远离第二极108一侧的表面，即半导体层102形成在第一介质层113、第二极108和第四介质层114的侧面，半导体层102还由第一介质层113、第二极108和第四介质层114的侧面延伸至第四介质层114远离第二极108一侧的表面(即第四介质层114的顶面)以及第五介质层115远离第一极109一侧的表面(即第五介质层115的顶面)；半导体层102与第四介质层114、第五介质层115均接触， 第一极109和第二极108均与半导体层102电连接。
此处，可以先利用外延生长法形成半导体薄膜，半导体薄膜是整层的，覆盖第四介质层114、第五介质层115、第一极109、第一介质层113和第二极108裸露的表面；再对半导体薄膜进行刻蚀，除了形成在凹槽的侧壁、底部和第四介质层114的顶面的半导体薄膜外，形成在凹槽的外侧的半导体薄膜被刻蚀掉，从而形成半导体层102。
S135、如图22所示，形成第二介质层112；第二介质层112覆盖半导体层102。
此处，该步骤S135的具体实现过程可以参考上述步骤S103，此处不再赘述。
S136、如图22所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062伸入凹槽结构内，即栅极柱1062沿第一介质层113、第二极108和第四介质层114的侧面延伸；栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S136的具体实现过程可以参考上述步骤S104，此处不再赘述。
需要说明的是，实施例四和实施例三相比，增加了步骤S132和步骤S133。
在实施例四中，步骤S132和步骤S133均执行，在一些实施例中，也可以执行步骤S132和步骤S133中的一个。
此外，在实施例四中，步骤S134中形成的半导体层102的结构和实施例三中形成的半导体层102的结构相同。在一些实施例中，步骤S134中形成的半导体层102的结构也可以和实施例一或实施例二中形成的半导体层102的结构相同。
实施例五
例如制作如图14所示的薄膜晶体管10，具体包括如下步骤：
S140、如图23所示，在衬底101上依次形成层叠的第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
此处，该步骤S140的具体实现过程可以参考上述步骤S100，此处不再赘述。
S141、如图23所示，对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图，形成依次层叠的第一极109、第一介质层113和第二极108；其中，第一极109、第一介质层113和第二极108构成凹槽结构。
此处，该步骤S141的具体实现过程可以参考上述步骤S101，此处不再赘述。
S142、如图23所示，形成半导体层102；半导体层102形成在凹槽结构的侧壁和底部，即半导体层102形成在第一介质层113和第二极108的侧面，半导体层102还由第一介质层113和第二极108的侧面延伸至第一极109靠近第二极108一侧的表面，即第一极1109的顶面；第一极109和第二极108均与半导体层102电连接。
此处，该步骤S142的具体实现过程可以参考上述步骤S112，此处不再赘述。
S143、如图23所示，形成第三介质层116；第三介质层116形成在凹槽结构的侧壁和底部。
需要说明的是，该步骤S143可以采用两种方式实现。第一种，可以利用化学气相沉积、物理气相沉积、溅射或电镀等方法直接形成第三介质层116，此时第三介质层116是整层的，覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的 表面。第二种，可以先利用化学气相沉积、物理气相沉积、溅射或电镀等形成第八介质薄膜，第八介质薄膜覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的表面；再对第八介质薄膜进行刻蚀，除了形成在凹槽侧面和底部的部分外，其它第八介质薄膜均被刻蚀掉，从而形成第三介质层116。
S144、如图23所示，形成第二介质层112；第二介质层112覆盖第三介质层116、半导体层102和第二极108；其中，第二介质层112的材料为铁电材料。
此处，该步骤S144的具体实现过程可以参考上述步骤S103，此处不再赘述。
S145、如图23所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062伸入凹槽结构内，即栅极柱1062沿第一介质层113和第二极108的侧面延伸；栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S145的具体实现过程可以参考上述步骤S104，此处不再赘述。
需要说明的是，实施例五和实施例二相比，增加了步骤S143。
此外，在实施例五中，步骤S142中形成的半导体层102的结构和实施例二中形成的半导体层102的结构相同。在一些实施例中，步骤S142中形成的半导体层102的结构也可以和实施例一或实施例三中形成的半导体层102的结构相同。
实施例六
例如制作如图15所示的薄膜晶体管10，具体包括如下步骤：
S150、如图24所示，在衬底101上依次形成层叠的第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
此处，该步骤S150的具体实现过程可以参考上述步骤S100，此处不再赘述。
S151、如图24所示，对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图，形成依次层叠的第一极109、第一介质层113和第二极108；其中，第一极109、第一介质层113和第二极108构成凹槽结构。
此处，该步骤S151的具体实现过程可以参考上述步骤S101，此处不再赘述。
S152、如图24所示，形成半导体层102；半导体层102形成在凹槽结构的侧壁和底部，即半导体层102形成在第一介质层113和第二极108的侧面，半导体层102还由第一介质层113和第二极108的侧面延伸至第一极109靠近第二极108一侧的表面，即第一极1109的顶面；第一极109和第二极108均与半导体层102电连接。
此处，该步骤S152的具体实现过程可以参考上述步骤S112，此处不再赘述。
S153、如图24所示，形成第三介质层116；第三介质层116形成在凹槽结构的侧壁和底部。
此处，该步骤S153的具体实现过程可以参考上述步骤S143，此处不再赘述。
S154、如图24所示，形成第一导电层117；第一导电层117形成在凹槽结构的侧壁和底部。
此处，可以先形成第四导电薄膜，第四导电薄膜覆盖第三介质层116、半导体层102、第二极108、第一介质层113和第一极109裸露的表面；再对第四导电薄膜进行刻蚀，除了形成在凹槽侧面和底部的部分外，其它第四导电薄膜被刻蚀掉，从而形成 第一导电层117。
S155、如图24所示，形成第二介质层112；第二介质层112覆盖第一导电层117、第二介质层116、半导体层102和第二极108；其中，第二介质层112的材料为铁电材料。
此处，该步骤S155的具体实现过程可以参考上述步骤S103，此处不再赘述。
S156、如图24所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062伸入凹槽结构内，即栅极柱1062沿第一介质层113和第二极108的侧面延伸；栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S156的具体实现过程可以参考上述步骤S104，此处不再赘述。
需要说明的是，实施例六和实施例五相比，增加了步骤S154。
实施例七
例如制作如图12b所示的薄膜晶体管10，具体包括如下步骤：
S160、如图25所示，在衬底101上依次形成层叠的第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
此处，该步骤S160的具体实现过程可以参考上述步骤S100，此处不再赘述。
S161、如图25所示，对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图，形成依次层叠的第一极109、第一介质层113和第二极108；其中，第一介质层113和第二极108在第一极109上的投影的边界位于第一极109的边界内，即第一介质层113和第二极108位于第一极109的中间区域。
此处，该步骤S161的具体实现过程可以参考上述步骤S101，此处不再赘述。
S162、如图25所示，形成半导体层102；半导体层102覆盖第二极108、第一介质层113的裸露的表面以及第一极109的顶面，即半导体层102覆盖第二极108的顶面和侧面、第一介质层113的侧面以及第一极109的顶面。
此处，可以先利用外延生长法形成半导体薄膜，半导体薄膜是整层的，覆盖第一极109、第一介质层113和第二极108裸露的表面；再对半导体薄膜进行刻蚀，除了形成在第二极108的顶面和侧面、第一介质层113的侧面以及第一极109的顶面的半导体薄膜外，形成在其它部分的半导体薄膜被刻蚀掉，从而形成半导体层102。
S163、如图25所示，形成第二介质层112；第二介质层112覆盖半导体层102。
此处，该步骤S163的具体实现过程可以参考上述步骤S103，此处不再赘述。
S164、如图25所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062围绕第一介质层113和第二极108的侧面设置一圈，即栅极柱1062为中空结构，栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S164的具体实现过程可以参考上述步骤S104，此处不再赘述。
实施例八
例如制作如图12a所示的薄膜晶体管，具体包括如下步骤：
S170、如图26所示，在衬底101上依次形成层叠的第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
此处，该步骤S170的具体实现过程可以参考上述步骤S100，此处不再赘述。
S171、如图26所示，对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图，形成依次层叠的第一极109、第一介质层113和第二极108；其中，第一介质层113和第二极108在第一极109上的投影的边界与第一极109的边界部分重叠，即第一介质层113和第二极108位于第一极109的边缘区域。
此处，该步骤S171的具体实现过程可以参考上述步骤S101，此处不再赘述。
S172、如图26所示，形成半导体层102；半导体层102形成在第二极108和第一介质层113的侧面，半导体层102还由第二极108和第一介质层113的侧面延伸至第二极108顶面以及第一极109的顶面。
此处，可以先利用外延生长法形成半导体薄膜，半导体薄膜是整层的，覆盖第一极109、第一介质层113和第二极108裸露的表面；再对半导体薄膜进行刻蚀，除了形成在第二极108和第一介质层113的左侧面、第二极108的顶面以及第一极109的顶面的半导体薄膜外，形成在其它部分的半导体薄膜被刻蚀掉，从而形成半导体层102。
S173、如图26所示，形成第二介质层112；第二介质层112覆盖半导体层102。
需要说明的是，该步骤S173可以采用两种方式实现。第一种，可以利用化学气相沉积、物理气相沉积、溅射或电镀等方法直接形成第二介质层112，此时第二介质层112是整层的，覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的表面。第二种，可以先利用化学气相沉积、物理气相沉积、溅射或电镀等形成第七介质薄膜，第七介质薄膜覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的表面；再对第七介质薄膜进行刻蚀，除了形成在半导体层102远离第一极109的表面的第七介质薄膜外，形成在其它地方的第七介质薄膜均被刻蚀掉，从而形成第二介质层112。此处，第一种方式附图未示意出。
S174、如图26所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062沿第一介质层113和第二极108的侧面延伸，栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S174的具体实现过程可以参考上述步骤S104，此处不再赘述。
实施例九
例如制作如图12c所示的薄膜晶体管，具体包括如下步骤：
S180、如图27所示，在衬底101上依次形成层叠的第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080。
此处，该步骤S180的具体实现过程可以参考上述步骤S100，此处不再赘述。
S181、如图27所示，对第一导电薄膜1090、第一介质薄膜1130和第二导电薄膜1080进行构图，形成依次层叠的第一极109、第一介质层113和第二极108；其中，第一介质层113和第二极108在第一极109上的投影的边界与第一极109的边界重叠。
此处，该步骤S181的具体实现过程可以参考上述步骤S101，此处不再赘述。
S182、如图27所示，形成半导体层102；半导体层102形成在第一极109、第一介质层113和第二极108的侧面，半导体层102还由第一极109、第一介质层113和第二极108的侧面延伸至第二极108远离第一极109一侧的表面，即第二极108的顶面。此处，可以先利用外延生长法形成半导体薄膜，半导体薄膜是整层的，覆盖第一极109、第一介质层113和第二极108裸露的表面；再对半导体薄膜进行刻蚀，除了形成在第一极109、第一介质层113和第二极108的左侧面和第二极108的顶面的半导体薄膜外，形成在其它部分的半导体薄膜被刻蚀掉，从而形成半导体层102。
S183、如图27所示，形成第二介质层112；第二介质层112覆盖半导体层102。
需要说明的是，该步骤S183可以采用两种方式实现。第一种，可以利用化学气相沉积、物理气相沉积、溅射或电镀等方法直接形成第二介质层112，此时第二介质层112是整层的，覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的表面。第二种，可以先利用化学气相沉积、物理气相沉积、溅射或电镀等形成第七介质薄膜，第七介质薄膜覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的表面；再对第七介质薄膜进行刻蚀，除了形成在半导体层102侧面和顶面的第七介质薄膜外，形成在其它地方的第七介质薄膜均被刻蚀掉，从而形成第二介质层112。此处，第一种方式附图未示意出。
S184、如图27所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062沿第一介质层113和第二极108的侧面延伸，栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S184的具体实现过程可以参考上述步骤S104，此处不再赘述。
需要说明的是，实施例七、实施例八和实施例九与上述其它实施例的区别在于，形成的层叠的第一极109、第一介质层113和第二极108的结构不同。
实施例十
例如制作如图16所示的薄膜晶体管10，具体包括如下步骤：
S190、如图28所示，在衬底101上形成依次层叠的第一导电薄膜1090和第三介电薄膜1131。
此处，该步骤S190的具体实现过程可以参考上述步骤S100，此处不再赘述。
S191、如图28所示，在第三介质薄膜1131上形成调制栅电极118。
此处，形成调制栅电极118的具体过程可以为：先形成第五导电薄膜，再对第五导电薄膜进行构图，形成调制栅电极118。
S192、如图28所示，在调制栅电极118上形成第四介电薄膜1132；其中，第四介质薄膜1132覆盖调制栅电极118。
此处，可以利用化学气相沉积、物理气相沉积、溅射、电镀等方法形成第四介电薄膜1132。
S193、如图28所示，对第四介电薄膜1132进行磨平处理。
此处，可以利用化学机械抛光技术对第四介电薄膜1132进行磨平处理。
需要说明的是，该步骤S193为可选步骤，例如在一些实施例中，步骤S193可以 省略。
S194、如图28所示，在第四介电薄膜1132上形成第二导电薄膜1080。
此处，可以利用化学气相沉积、物理气相沉积、溅射、电镀等方法形成第二导电薄膜1080。
S195、如图28所示，对第二导电薄膜1080进行构图形成第二极108，对第四介电薄膜1132和第三介电薄膜1131进行构图形成第一介质层113，对第一导电薄膜1090进行构图形成第一极109；其中，第二极108、第一介质层113和第一极109构成凹槽结构，第一介质层113包围调制栅电极118，从而将调制栅电极118与第二极108、第一极109间隔开。
此处，该步骤S195的具体实现过程可以参考上述步骤S101，此处不再赘述。
S196、如图28所示，形成半导体层102；半导体层102形成在凹槽结构的侧壁和底部，以及第二极108远离第一极109一侧的表面，即半导体层102形成在第一介质层113和第二极108的侧面，半导体层102还由第一介质层113和第二极108的侧面延伸至第二极108远离第一极109一侧的表面(即第二极108的顶面)以及第一极109靠近第二极108一侧的表面(即第一极109的顶面)；第一极109和第二极108均与半导体层102电连接。
此处，该步骤S196的具体实现过程可以参考上述步骤S122，此处不再赘述。
S197、如图28所示，形成第二介质层112；第二介质层112覆盖半导体层102。
此处，该步骤S197的具体实现过程可以参考上述步骤S103，此处不再赘述。
S198、如图28所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062伸入凹槽结构内，即栅极柱1062沿第一介质层113和第二极108的侧面延伸；栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S198的具体实现过程可以参考上述步骤S104，此处不再赘述。
需要说明的是，本实施例十与上述其它实施例的区别主要在于，实施例十增加了步骤S191。
实施例十一
例如制作如图11所示的薄膜晶体管10，具体包括如下步骤：
S200、如图29所示，在衬底101上形成依次层叠的第一导电薄膜1090和第一介质薄膜1130。
此处，该步骤S200的具体实现过程可以参考上述步骤S100，此处不再赘述。
S201、如图29所示，对第一导电薄膜1090和第一介质薄膜1130进行构图，形成依次层叠的第一极109和第一介质层113；其中，第一介质层113和第一极109构成凹槽结构。
此处，该步骤S201的具体实现过程可以参考上述步骤S101，此处不再赘述。
S202、如图29所示，形成半导体层102；半导体层102形成在凹槽结构的侧壁和底部、以及第一介质层113远离第一极109一侧的表面，即半导体层102形成在第一介质层113的侧面，且半导体层102还由第一介质层113侧面延伸至第一极109靠近 第一介质层113一侧的表面(即第一极109的顶面)以及第一介质层113远离第一极109一侧的表面(即第一介质层113的顶面)；第一极109与半导体层102电连接。
此处，可以先利用外延生长法形成半导体薄膜，半导体薄膜是整层的，覆盖第一极109和第一介质层113裸露的表面；再对半导体薄膜进行刻蚀，除了形成在凹槽的侧壁、底部和第一介质层113的顶面的半导体薄膜外，形成在凹槽的外侧的半导体薄膜被刻蚀掉，从而形成半导体层102。
S203、如图29所示，形成第二极108；第二极108位于第一介质层113远离第一极109的一侧，即第二极108位于第一介质层113的顶面。
此处，形成第二极108的过程具体可以为：先形成第二导电薄膜，再对第二导电薄膜进行刻蚀形成第二极108。
S204、如图29所示，形成第二介质层112；第二介质层112覆盖半导体层102和第二极108。
需要说明的是，该步骤S204可以采用两种方式实现。第一种，可以利用化学气相沉积、物理气相沉积、溅射或电镀等方法直接形成第二介质层112，此时第二介质层112是整层的，覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的表面。第二种，可以先利用化学气相沉积、物理气相沉积、溅射或电镀等形成第七介质薄膜，第七介质薄膜覆盖半导体层102、第二极108、第一极109和第一介质层113裸露的表面；再对第七介质薄膜进行刻蚀，除了形成在凹槽侧面、底部和第二极108的顶面、侧面的部分外，其它第七介质薄膜均被刻蚀掉，从而形成第二介质层112。此处，第一种方式附图未示意出。
S205、如图29所示，形成栅极106；栅极106包括栅基底1061和从栅基底1061延伸的栅极柱1062；栅极柱1062伸入凹槽结构内，即栅极柱1062沿第一介质层113和第二极108的侧面延伸；栅基底1061形成在栅极柱1062远离第一极109的一侧，第二介质层112将栅极106与半导体层102、第一极109和第二极108隔开。
此处，该步骤S205的具体实现过程可以参考上述步骤S104，此处不再赘述。
需要说明的是，实施例十一与上述其它实施例的区别主要在于，实施例十一形成半导体层102和第二极108的顺序与上述其它实施例不同。
应当理解到，本申请实施例提供的薄膜晶体管10，可以采用上述提供的薄膜晶体管10的制作方法，还可以采用其它制作方法进行制作，对此不做限定。
本申请实施例还提供一种存储器的制作方法，包括在衬底101上形成至少一层存储阵列201。
例如制作如图4所示的任意一层存储阵列201，如图30所示，具体包括如下步骤：
S300、在衬底101上形成多条平行排列的第一信号线。
S301、在多条第一信号线上形成阵列分布的多个第一薄膜晶体管Tr0以及多条平行排列的第二信号线；其中，第一薄膜晶体管Tr0的第一极109a与第一信号线电连接，第一薄膜晶体管Tr0的第二极108a与第二信号线电连接；第一信号线为读位线RBL和读字线RWL中的一个，第二信号线为读位线RBL和读字线RWL中的另一个。此处，第一薄膜晶体管Tr0可以采用上述任一实施例提供的薄膜晶体管10的制作方法制作得到。可以理解，这里阵列分布的多个第一薄膜晶体管Tr0可以是同步形成的。
需要说明的是，可以是第一信号线为读位线RBL，第二信号线为读字线RWL；在此情况下，第一薄膜晶体管Tr0的第一极109a与读位线RBL电连接，第二极108a与读字线RWL电连接；也可以是第一信号线为读字线RWL，第二信号线为读位线RBL；在此情况下，第一薄膜晶体管Tr0的第一极109a与读字线RWL电连接，第二极108a与读位线RBL电连接。
可以理解的是，在一些实施例中，第一极109a与第一信号线可以同步形成，第二极108a与第二信号线可以同步形成。
S302、形成阵列分布的多个连接电极111；一个第一薄膜晶体管Tr0的栅极106a与一个连接电极111电连接在一起。
需要说明的是，该步骤S302为可选步骤。例如在一些实施例中，步骤S302还可以省略。
此处，可以先形成第六导电薄膜，再对第六导电薄膜进行刻蚀，以形成多个连接电极111。
S303、在第一薄膜晶体管Tr0上形成阵列分布的多个第二薄膜晶体管Tr1以及多条平行排列的写位线WBL；第二薄膜晶体管Tr1的第二极108b与写位线WBL电连接。其中，一个第二薄膜晶体管Tr1与一个第一薄膜晶体管Tr0对应，且第二薄膜晶体管Tr1的第一极109b与对应的第一薄膜晶体管Tr0的栅极1106a电连接；此处，第二薄膜晶体管Tr1可以采用上述任一实施例提供的薄膜晶体管10的制作方法制作得到。可以理解，这里阵列分布的多个第二薄膜晶体管Tr1可以是同步形成的。
需要说明的是，在任意一层存储阵列201的制作方法包括步骤S302时，第二薄膜晶体管Tr1的第一极109b与对应的第一薄膜晶体管Tr0的栅极106a通过连接电极111电连接在一起。
在一些实施例中，第二薄膜晶体管Tr1的第二极108b可以与写位线WBL同步形成。
S304、在第二薄膜晶体管Tr1上形成多条平行排列的写字线WWL；第二薄膜晶体管Tr1的栅极106b与写字线WWL电连接。
在一些实施例中，写字线WWL可以与第二薄膜晶体管Tr1的栅极106b同步形成。
基于上述，当存储器200包括设置在衬底101上的多层存储阵列201时，在制作存储器200时，可以重复步骤S300-S304，以形成多层存储阵列201。
此外，在制作完第一层存储阵列201后，在形成第二层存储阵列201之前，可以先形成第六介质层202。此时，第六介质层202作为第二层存储阵列201的衬底。同样的，在制作第三层存储阵列201、第四层存储阵列201等之前，也可以先形成第六介质层202。以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种薄膜晶体管，其特征在于，包括：
    栅极，所述栅极包括位于顶部的栅基底和从所述栅基底向底部延伸的栅极柱；
    位于底部的第一极；
    第二极，所述第二极位于所述第一极和所述栅基底之间；
    第一介质层，所述第一介质层设置在所述第二极和所述第一极之间，所述第一介质层用于将所述第二极和所述第一极隔开；
    半导体层，所述半导体层沿所述栅极柱的侧面设置，
    第二介质层，所述第二介质层将所述半导体层与所述栅极隔开；
    其中，所述第一极和所述第二极分别与所述半导体层电连接。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第二极靠近所述栅基底设置。
  3. 根据权利要求1或2所述的薄膜晶体管，其特征在于，所述半导体层还包括沿所述栅基底的表面延伸的延伸部。
  4. 根据权利要求1-3任一项所述的薄膜晶体管，其特征在于，所述半导体层还包括位于所述栅极柱和所述第一极之间的延伸部。
  5. 根据权利要求1所述的薄膜晶体管，其特征在于，所述半导体层包围所述栅极柱的整个侧面。
  6. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第二极设置在所述半导体层远离所述第二介质层的一侧。
  7. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第二极设置在所述半导体层和所述第二介质层之间。
  8. 根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：设置在所述第二极和所述半导体层之间的第四介质层；和/或，设置在所述第一极和所述半导体层之间的第五介质层。
  9. 根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：设置在所述第一极和所述第二极之间的调制栅电极，且所述调制栅电极由所述第一介质层包围。
  10. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第一极是漏极，所述第二极是源极；
    或者，所述第一极是源极，所述第二极是漏极。
  11. 一种存储器，其特征在于，包括设置于衬底上的至少一层存储阵列；每层所述存储阵列包括阵列分布的多个存储单元、写字线、写位线、读字线以及读位线；所述存储单元包括层叠设置的第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管的第一极和第二极分别与所述读字线、所述读位线电连接；所述第二薄膜晶体管的栅极与所述写字线电连接，第二极与所述写位线电连接；
    所述第一薄膜晶体管和所述第二薄膜晶体管为如权利要求1-10任一项所述的薄膜晶体管；
    其中，所述第二薄膜晶体管的第一极靠近所述第一薄膜晶体管的栅极，且所述第 二薄膜晶体管的第一极与所述第一薄膜晶体管的栅极电连接。
  12. 根据权利要求11所述的存储器，其特征在于，所述存储单元还包括设置在所述第一薄膜晶体管和所述第二薄膜晶体管之间的连接电极；
    所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的第一极通过所述连接电极电连接在一起。
  13. 根据权利要求11或12所述的存储器，其特征在于，每层所述存储阵列中沿第一方向依次排列的多个存储单元中的所述第二薄膜晶体管的所述栅极与同一条所述写字线电连接；
    每层所述存储阵列中沿第二方向依次排列的多个存储单元中的所述第二薄膜晶体管的第二极与同一条所述写位线电连接；
    其中，所述第一方向和所述第二方向正交。
  14. 根据权利要求11-13任一项所述的存储器，其特征在于，每层所述存储阵列中沿第一方向依次排列的多个存储单元中的所述第一薄膜晶体管的第二极与同一条所述读位线电连接；每层所述存储阵列中沿第二方向依次排列的多个存储单元中的所述第一薄膜晶体管的第一极与同一条所述读字线电连接；
    或者，每层所述存储阵列中沿第一方向依次排列的多个存储单元中的所述第一薄膜晶体管的第二极与同一条所述读字线电连接；每层所述存储阵列中沿第二方向依次排列的多个存储单元中的所述第一薄膜晶体管的第一极与同一条所述读位线电连接；
    或者，每层所述存储阵列中沿第二方向依次排列的多个存储单元中的所述第一薄膜晶体管的第二极与同一条所述读位线电连接；每层所述存储阵列中沿第一方向依次排列的多个存储单元中的所述第一薄膜晶体管的第一极与同一条所述读字线电连接；
    或者，每层存储阵列中沿第二方向依次排列的多个存储单元中的所述第一薄膜晶体管的第二极与同一条所述读字线电连接；每层所述存储阵列中沿第一方向依次排列的多个存储单元中的所述第一薄膜晶体管的第一极与同一条所述读位线电连接；
    其中，所述第一方向和所述第二方向正交。
  15. 根据权利要求11-14任一项所述的存储器，其特征在于，
    所述第一薄膜晶体管还包括设置在所述第一极和所述第二极之间的第一调制栅电极，且所述第一调制栅电极由所述第一薄膜晶体管的第一介质层包围；位于同一层的多个所述第一薄膜晶体管的所述第一调制栅电极电连接在一起；
    和/或，所述第二薄膜晶体管还包括设置在所述第一极和所述第二极之间的第二调制栅电极，且所述第二调制栅电极由所述第二薄膜晶体管的第一介质层包围；位于同一层的多个所述第二薄膜晶体管的所述第二调制栅电极电连接在一起。
  16. 一种电子设备，包括电路板以及与所述电路板电连接的存储器，其特征在于，所述存储器为如权利要求11-15任一项所述的存储器。
  17. 一种薄膜晶体管的制作方法，其特征在于，包括：
    在衬底上形成第一极、第一介质层、第二极以及半导体层；其中，所述第一极、所述第一介质层和所述第二极依次层叠设置，所述第一介质层将所述第一极和所述第二极隔开；所述半导体层形成在所述第一介质层的侧面；所述第一极和所述第二极均与所述半导体层电连接；
    依次形成第二介质层和栅极；所述栅极包括位于顶部的栅基底和从所述栅基底向底部延伸的栅极柱，所述第二介质层将所述栅极与所述半导体层、所述第一极和所述第二极隔开。
  18. 根据权利要求17所述的制作方法，其特征在于，形成所述第一极作为漏极，形成所述第二极作为源极；
    或者，形成所述第一极作为源极，形成所述第二极作为漏极。
  19. 根据权利要求17或18所述的制作方法，其特征在于，所述在衬底上形成第一极、第一介质层、第二极以及半导体层包括：
    在所述衬底上依次形成层叠的第一导电薄膜、第一介质薄膜和第二导电薄膜；
    对所述第一导电薄膜、所述第一介质薄膜和所述第二导电薄膜进行构图，形成依次层叠的所述第一极、所述第一介质层和所述第二极；
    在所述第一介质层和所述第二极的侧面形成所述半导体层。
  20. 根据权利要求17或18所述的制作方法，其特征在于，所述在衬底上形成第一极、第一介质层、第二极以及半导体层包括：
    在所述衬底上形成依次层叠的第一导电薄膜和第三介电薄膜；
    在所述第三介质薄膜上形成调制栅电极；
    形成第四介电薄膜；其中，所述第四介质薄膜包围所述调制栅电极；
    在所述第四介质薄膜上形成第二导电薄膜；
    对所述第一导电薄膜进行构图形成所述第一极，对所述第四介电薄膜和所述第三介电薄膜进行构图形成所述第一介质层，对所述第二导电薄膜进行构图形成第二极；
    在所述第一介质层和所述第二极的侧面形成所述半导体层。
  21. 根据权利要求17或18所述的制作方法，其特征在于，所述在衬底上形成第一极、第一介质层、第二极以及半导体层包括：
    在所述衬底上形成依次层叠的第一导电薄膜和第一介质薄膜；
    对所述第一导电薄膜和所述第一介质薄膜进行构图，形成依次层叠的所述第一极和所述第一介质层；
    在所述第一介质层的侧面形成所述半导体层；
    在所述第一介质层上形成所述第二极。
  22. 根据权利要求17-21任一项所述的制作方法，其特征在于，在形成所述第一极之后，形成所述半导体层之前，所述制作方法还包括：
    形成第五介质层；其中，所述第五介质层分别与所述第一极和所述半导体层接触。
  23. 根据权利要求17-22任一项所述的制作方法，其特征在于，在形成所述第二极之后，形成所述半导体层之前；或者，在形成所述半导体层之后，在形成所述第二极之前，所述制作方法还包括：
    形成第四介质层；其中，所述第四介质层分别与所述第二极和所述半导体层接触。
  24. 一种存储器的制作方法，其特征在于，包括在衬底上形成至少一层存储阵列；任意一层所述存储阵列的制作方法，包括：
    在所述衬底上形成多条平行排列的第一信号线；
    在多条所述第一信号线上形成阵列分布的多个第一薄膜晶体管以及多条平行排列 的第二信号线；所述第一薄膜晶体管采用如权利要求17-23任一项所述的制作方法制作得到；其中，所述第一薄膜晶体管的第一极与所述第一信号线电连接，所述第一薄膜晶体管的第二极与所述第二信号线电连接；所述第一信号线为读位线和读字线中的一个，所述第二信号线为所述读位线和所述读字线中的另一个；
    在所述第一薄膜晶体管上形成阵列分布的多个第二薄膜晶体管以及多条平行排列的写位线；所述第二薄膜晶体管的第二极与所述写位线电连接；所述第二薄膜晶体管采用如权利要求17-23任一项所述的制作方法制作得到；其中，一个所述第二薄膜晶体管与一个所述第一薄膜晶体管对应，且所述第二薄膜晶体管的第一极与对应的所述第一薄膜晶体管的栅极电连接；
    在所述第二薄膜晶体管上形成多条平行排列的写字线；所述第二薄膜晶体管的栅极与所述写字线电连接。
  25. 根据权利要求24所述的存储器的制作方法，其特征在于，所述在多条所述第一信号线上形成阵列分布的多个第一薄膜晶体管以及多条平行排列的第二信号线之后，所述在所述第一薄膜晶体管上形成阵列分布的多个第二薄膜晶体管以及多条平行排列的写位线之前，所述任意一层所述存储阵列的制作方法还包括：
    形成阵列分布的多个连接电极；所述第一薄膜晶体管的栅极与对应的所述第二薄膜晶体管的第一极通过所述连接电极电连接在一起。
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