WO2022165657A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2022165657A1
WO2022165657A1 PCT/CN2021/074978 CN2021074978W WO2022165657A1 WO 2022165657 A1 WO2022165657 A1 WO 2022165657A1 CN 2021074978 W CN2021074978 W CN 2021074978W WO 2022165657 A1 WO2022165657 A1 WO 2022165657A1
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Prior art keywords
pixel
line
lines
display substrate
data
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PCT/CN2021/074978
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English (en)
French (fr)
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WO2022165657A9 (zh
Inventor
韩龙
王品凡
曹方旭
李文强
刘利宾
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to EP21923685.8A priority Critical patent/EP4141945A4/en
Priority to PCT/CN2021/074978 priority patent/WO2022165657A1/zh
Priority to US17/628,425 priority patent/US12243970B2/en
Priority to CN202180000149.8A priority patent/CN115191035B/zh
Publication of WO2022165657A1 publication Critical patent/WO2022165657A1/zh
Publication of WO2022165657A9 publication Critical patent/WO2022165657A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • the four-curved screen design has been widely used in smart electronic products such as mobile phones and tablet computers.
  • the four-curved screen design is combined with 3D cover glass bonding technology, and the edges or corners of the display substrate are bent according to a certain bending radius to form a radian, so as to realize a comprehensive three-dimensional display of the front and side, so as to realize the four-curved shape.
  • 3D stereo effect which can create a three-dimensional immersion display, which is in line with the future technology development trend.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes: a plurality of pixel islands, a first opening, a second opening and a first channel region; the plurality of pixel islands are arranged in an array along a first direction and a second direction; the first openings are located adjacent to each other in the second direction between two pixel islands; the second opening is located between two adjacent pixel islands in the first direction; the first channel region is at least partially located between the first opening and the second opening; each pixel island includes at least one pixel , each pixel includes a plurality of first driving lines extending along the first direction, the first channel area is provided with a plurality of first connecting lines, and each pixel island also includes a plurality of connecting lines extending along the second direction, a plurality of connecting lines The plurality of first driving lines are arranged in different layers and cross each other to form a plurality of overlapping areas; The plurality of transition lines in the two upwardly adjacent pixel islands are respectively connected with the plurality
  • the display substrate leads out a plurality of first driving lines in each pixel island through a plurality of transfer lines, and connects a plurality of the plurality of adjacent pixel islands in the first direction through a plurality of first connection lines in the first channel area.
  • the first driving lines are respectively connected, so as to realize the connection of a plurality of first driving lines in two adjacent pixel islands in the first direction. Therefore, the display substrate can realize the wiring of the driving lines in the stretchable region or the bending region with the opening pattern.
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a plurality of pixel islands arranged in an array along a first direction and a second direction; a first opening located at two adjacent ones of the second between pixel islands; a second opening located between two adjacent pixel islands in the first direction; and a first channel region located between the first opening and the second opening,
  • Each of the pixel islands includes at least one pixel, each of the pixels includes a plurality of first drive lines extending along the first direction, a plurality of first connection lines are arranged in the first channel region, and each of the pixel islands It also includes a plurality of transfer lines extending along the second direction, the plurality of transfer lines and the plurality of first driving lines are arranged in different layers, and cross each other to form a plurality of overlapping areas; the plurality of transfer lines are The wiring is electrically connected to the plurality of first driving lines through the via holes located in part of the overlapping area, and the plurality of connecting lines in the two adjacent pixel islands in the first direction
  • each of the pixel islands includes two sub-regions and a transition region located between the two sub-regions, and the at least one pixel included in the pixel island is disposed on the In the two sub-regions, the patch cord is located in the patch area.
  • the plurality of first driving lines pass through the two sub-regions and the transition region, and the plurality of first driving lines are configured to drive the Pixels in the two sub-areas for light-emitting display.
  • the first opening extends along the first direction
  • the second opening extends along the second direction
  • the first opening and the second opening extend along the second direction.
  • the openings are alternately arranged in the first direction
  • the first openings and the second openings are also alternately arranged in the second direction.
  • the first channel region is located between the pixel island and the first opening.
  • each of the pixels includes a plurality of sub-pixels, and each of the sub-pixels includes a pixel driving circuit and an anode electrically connected to the pixel driving circuit.
  • the display substrate includes: a base substrate; a semiconductor layer, located on the base substrate; and a gate insulating layer, located on the semiconductor layer away from the base substrate the side of the first gate layer; the first gate layer is located on the side of the gate insulating layer away from the semiconductor layer; the interlayer insulating layer is located on the side of the first gate layer away from the gate insulating layer; a second gate layer, located on a side of the interlayer insulating layer away from the first gate layer; a passivation layer, located on a side of the second gate layer away from the interlayer insulating layer; a conductive layer located on a side of the passivation layer away from the second gate layer, and the plurality of first driving lines are located on at least one of the first gate layer and the second gate layer
  • the patch cord is located on the first conductive layer.
  • each of the pixel driving circuits includes: a first semiconductor unit, a second semiconductor unit, a third semiconductor unit, a fourth semiconductor unit, a fifth semiconductor unit located in the semiconductor layer a semiconductor unit, a sixth semiconductor unit, and a seventh semiconductor unit; a first electrode block on the first gate layer; and a second electrode block on the second gate layer, the first semiconductor unit including a a channel region and a first source region and a first drain region located on both sides of the first channel region, the second semiconductor unit includes a second channel region and two sides of the second channel region a second source region and a second drain region on both sides of the third semiconductor unit, the third semiconductor unit includes a third channel region and a third source region and a third drain region located on both sides of the third channel region, The fourth semiconductor unit includes a fourth channel region and a fourth source region and a fourth drain region located on both sides of the fourth channel region, and the fifth semiconductor unit includes a fifth channel region and a fourth drain region located on
  • the sixth semiconductor unit includes a sixth channel region and a sixth source electrode located on both sides of the sixth channel region region and a sixth drain region
  • the seventh semiconductor unit includes a seventh channel region and a seventh source region and a seventh drain region on both sides of the seventh channel region
  • the third source region region, the first drain region and the fifth source region are connected to the first node
  • the sixth drain region and the third drain region are connected
  • the first source region, the The second drain region and the fourth drain region are connected to the second node
  • the fifth drain region is connected to the seventh drain region
  • the plurality of first driving lines include: initialization signal lines located in the second gate layer; reset signal lines located in the first gate layer; a gate line located in the first gate layer; and a light emission control line located in the first gate layer, the initialization signal line is connected to the seventh source region and the sixth source region, the reset The signal line overlaps the seventh channel region and the sixth channel region, the gate line overlaps the third channel region and the second channel region, respectively, and the first electrode The block overlaps the first channel region, and the light emission control line overlaps the fourth channel region and the fifth channel region.
  • each of the pixel islands includes at least two pixels arranged along the second direction, and at least two of the plurality of first driving lines are connected to the same rotation line. Wiring is connected.
  • each of the pixel islands includes four of the pixels arranged in a matrix, and each of the pixel islands includes a first sub-area, a second sub-area, and a second sub-area located in the first sub-area.
  • An initialization signal line is electrically connected to the first connecting line through a via hole, and the second initialization signal line of the second pixel and the fourth pixel is connected to the first connecting line through a via hole.
  • the reset signal line of the first pixel and the reset signal line of the third pixel are first reset signal lines
  • the reset signal line and the reset signal line of the fourth pixel are the second reset signal line
  • the plurality of transfer lines include a second transfer line and a third transfer line
  • the first pixel and the The first reset signal line of the three pixels is electrically connected to the second patch line through a via hole
  • the second reset signal line of the second pixel and the fourth pixel is electrically connected to the second patch line through a via hole.
  • the gate line of the first pixel and the gate line of the third pixel are first gate lines
  • the gate line of the second pixel Line and the gate line of the fourth pixel are second gate lines
  • the plurality of transition lines include a fourth transition line
  • the first gate lines of the first pixel and the third pixel pass through
  • the hole is electrically connected to the third patch wire
  • the second gate lines of the second pixel and the fourth pixel are connected to the fourth patch wire through a via hole.
  • the light emission control line of the first pixel and the light emission control line of the third pixel are the first light emission control line
  • the light-emitting control line and the light-emitting control line of the fourth pixel are the second light-emitting control line
  • the plurality of transition lines include a fifth transition line
  • the first pixel and the third pixel are The first light emitting control line is electrically connected to the fifth connecting line through a via hole
  • the second light emitting control line of the second pixel and the fourth pixel is connected to the fifth connecting line through a via hole.
  • the light emission control line of the first pixel and the light emission control line of the third pixel are the first light emission control line
  • the light-emitting control line and the light-emitting control line of the fourth pixel are the second light-emitting control line
  • the plurality of transfer lines include a fifth transfer line and a sixth transfer line
  • the first pixel and the first The first light-emitting control line of the three pixels is electrically connected to the fifth patch line through a via hole
  • the second light-emitting control line of the second pixel and the fourth pixel is respectively connected to the fifth patch line via a via hole.
  • the sixth patch cord is connected.
  • the plurality of first connection lines are disposed on the first gate layer and the second gate layer.
  • the number of the plurality of transition lines is smaller than the number of the plurality of first driving lines.
  • each of the pixel islands includes a plurality of second driving lines extending along the second direction, the second channel region A plurality of second connection lines are provided, and the plurality of second connection lines respectively connect the plurality of second driving lines of the two pixel islands adjacent in the second direction.
  • the plurality of second driving lines include: a plurality of power supply lines, which are located in the first conductive layer, and each of the power supply lines is connected to all the power supply lines in the pixel driving circuit.
  • the fourth source region is connected; and a plurality of data lines are located in the first conductive layer, and each of the data lines is connected to the second source region in the pixel driving circuit.
  • the display substrate further includes: an insulating layer, located on a side of the first conductive layer away from the passivation layer; and a second conductive layer, located on the insulating layer away from the passivation layer
  • the second conductive layer includes a conductive grid located on the pixel island, the conductive grid is electrically connected to the plurality of power lines in the pixel island, and the A plurality of second connection lines, including power supply connection lines, are located on the second conductive layer and connected to the conductive grid.
  • the plurality of second connection lines further include a plurality of data connection lines, and the plurality of data lines are arranged and connected to the plurality of data connection lines in a one-to-one correspondence.
  • the plurality of second connection lines are disposed on the first conductive layer and the second conductive layer.
  • each of the pixels includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel
  • each of the pixel islands includes four pixels arranged in a matrix.
  • each of the pixel islands includes a first sub-area, a second sub-area, and a transition area between the first sub-area and the second sub-area
  • the first sub-area includes an area along the A first pixel and a second pixel arranged in a second direction
  • the second sub-region includes a third pixel and a fourth pixel arranged along the second direction
  • the data line of the second pixel and the data line of the first color sub-pixel in the second pixel are the first data line
  • the data line of the second color sub-pixel in the first pixel and the data line of the second pixel are the first data line.
  • the data line of the second color sub-pixel is the second data line
  • the data line of the third color sub-pixel in the first pixel and the data line of the third color sub-pixel in the second pixel are the third data line data line
  • the data line of the first color sub-pixel in the third pixel and the data line of the first color sub-pixel in the fourth pixel are the fourth data line
  • all the data lines in the third pixel
  • the data line of the second color sub-pixel and the data line of the second color sub-pixel in the fourth pixel are the fifth data line
  • the data line of the third color sub-pixel in the fourth pixel is the sixth data line
  • the plurality of second connection lines include a first data connection line, a second data connection line, a third data connection line, and a fourth data connection line.
  • connection line a fifth data connection line and a sixth data connection line
  • the first data connection line is connected with the first data line
  • the second data connection line is connected with the second data line
  • the first data connection line is connected with the first data line
  • the third data connection line is connected to the third data line
  • the fourth data connection line is connected to the fourth data line
  • the fifth data connection line is connected to the fifth data line
  • the sixth data connection line is connected to the fifth data line.
  • the connecting line is connected to the sixth data line.
  • the first data connection line, the second data connection line, and the fifth data connection line are located on the first conductive layer
  • the power supply connection line , the third data connection line, the fourth data connection line and the sixth data connection line are located on the second conductive layer.
  • the display substrate includes a first display area and a second display area, and the pixel density of the first display area is greater than the pixel density of the second display area, so The pixel island is located in the second display area.
  • the second display area is located at a corner of the first display area.
  • the second display area of the display substrate is bendable in a direction perpendicular to the first display area.
  • At least one embodiment of the present disclosure further provides a display device including the display substrate described in any one of the above.
  • FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a pixel in a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure along the direction AA in FIG. 2;
  • 4A-4D are schematic diagrams of a plurality of film layers of a pixel driving circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 5 is an equivalent schematic diagram of a pixel driving circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a second conductive layer in a display substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • the edges or corners of the display substrate can be bent according to a certain bending radius. Bend it to achieve a four-curved screen design.
  • the greater the stretching amount of the stretchable structure located in the four corner regions the lower the pixel density of the four corner regions, that is, the low pixel density region.
  • these opening patterns divide the pixel array into a plurality of isolated pixel islands; and the driving lines (such as gate lines, data lines, etc.) of the pixels in these pixel islands are all They need to be connected to each other, but these driving lines cannot directly cross these opening patterns, so the control lines and data lines of the pixel unit need to be routed around the opening patterns.
  • inventions of the present disclosure provide a display substrate and a display device.
  • the display substrate includes: a plurality of pixel islands, a first opening, a second opening and a first channel region; the plurality of pixel islands are arranged in an array along a first direction and a second direction; the first openings are located adjacent to each other in the second direction between two pixel islands; the second opening is located between two adjacent pixel islands in the first direction; the first channel region is at least partially located between the first opening and the second opening and will be opposite to each other in the first direction; Two adjacent pixel islands are connected; each pixel island overlaps with the first opening in the first direction, each pixel island includes at least one pixel, each pixel includes a plurality of first driving lines extending along the first direction, the first channel
  • the area is provided with a plurality of first connection lines, and each pixel island also includes a plurality of patch cords extending along the second direction.
  • the multiple patch cords and the multiple first drive lines are arranged in different layers and cross each other to form multiple overlaps.
  • a plurality of patch cords are electrically connected to a plurality of first drive lines through vias located in the partially overlapping area, and a plurality of patch cords in two adjacent pixel islands in the first direction are respectively connected to the first channel area
  • a plurality of first connection lines in the are connected.
  • the display substrate leads out a plurality of first driving lines in each pixel island through a plurality of transfer lines, and connects a plurality of the plurality of adjacent pixel islands in the first direction through a plurality of first connection lines in the first channel area.
  • the first driving lines are respectively connected, so as to realize the connection of a plurality of first driving lines in two adjacent pixel islands in the first direction. Therefore, the display substrate can realize the wiring of the driving lines in the stretchable region or the bending region with the opening pattern.
  • FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 includes a plurality of pixel islands 110 , a first opening 121 , a second opening 122 and a first channel region 130 ; the plurality of pixel islands 110 are arranged in an array along the first direction and the second direction.
  • the distance between the pixel islands 110 is relatively large, for example, the distance between adjacent pixel islands 110 is greater than the distance between adjacent pixels 140 in the pixel islands 110 .
  • the first opening 121 is located between two pixel islands 110 adjacent in the second direction; the second opening 122 is located between the two pixel islands 110 adjacent in the first direction; the first channel region 130 is located at least partially in Between the first opening 121 and the second opening 122 and connecting two pixel islands 110 adjacent in the first direction; each pixel island 110 overlaps the first opening 121 in the first direction, that is, the pixel
  • the orthographic projection of the island on a reference line extending along the first direction overlaps with the orthographic projection of the first opening on the reference line.
  • Each pixel island 110 includes at least one pixel 140, each pixel 140 includes a plurality of first driving lines 142 extending along the first direction, the first channel region 130 is provided with a plurality of first connection lines 132, and each pixel island 110 also includes a plurality of first driving lines 142 along the first direction.
  • a plurality of patch cords 112 extending in the second direction, the patch cords 112 and the first drive lines 142 are disposed in different layers and intersect each other to form a plurality of overlapping regions 150;
  • the vias 152 in the region 150 are electrically connected to the plurality of first driving lines 142 , and the plurality of connecting lines 112 in the two adjacent pixel islands 110 in the first direction are respectively connected with the plurality of first driving lines 112 in the first channel region 130 .
  • a connecting line 132 is connected.
  • the first driving line may be a gate line, which is located in one layer of the first gate layer and the second gate layer; at this time, the above-mentioned transfer line may be located in other conductive layers, such as Another layer of the first gate layer and the second gate layer, a first source-drain metal layer, a second source-drain metal layer, or a light shielding layer.
  • the above-mentioned via holes have different depths according to the difference of the first driving line and the transition line to which they are connected, and the adjacent via holes are arranged in a staggered position to avoid mutual interference.
  • a plurality of first driving lines 142 of each pixel 140 can be led out through the transition line 112, and then two adjacent pixel islands 110 in the first direction
  • the plurality of transition lines 112 in the first channel region 130 are respectively connected with the plurality of first connection lines 132 in the first channel region 130, so as to realize the plurality of first driving lines 142 in the two pixel islands 110 adjacent to each other in the first direction connected. Therefore, the display substrate can realize the wiring of the driving lines in the stretchable region or the bending region with the opening pattern.
  • the display substrate can ensure that the first opening and the second opening have larger sizes, so that the stretching or stretching of the display substrate can also be improved. Bending properties.
  • each pixel island 110 includes two sub-regions 114 and a transition region 116 located between the two sub-regions 114 , and at least one pixel 140 included in the pixel island 110 is disposed in the two sub-regions 114 , the patch cord 112 is located in the patch area 116 . Therefore, the above-mentioned transfer line 112 is placed in the display substrate by arranging the transfer area 116 in the pixel island 110, and the transfer area 116 is arranged between the two sub-regions 114, so that the pixels 140 in the pixel island 110 can be improved. distribution symmetry.
  • the plurality of first drive lines 142 pass through the two sub-regions 114 and the transition region 116 , and the plurality of first drive lines 142 are configured to drive the pixels 140 in the two sub-regions 114 to Illuminated display. It should be noted that one of the two sub-areas may be a dummy area (dummy), that is, an area not to be displayed.
  • the above-mentioned first driving lines 142 may include gate lines, emission control lines, initialization lines and other driving lines extending in the first direction.
  • the first openings 121 extend along the first direction
  • the second openings 122 extend along the second direction
  • the first openings 121 and the second openings 122 are alternately arranged in the first direction
  • the first openings 121 and the second openings 122 are also alternately arranged in the second direction. Therefore, in the area where the first opening and the second opening are located, the display substrate can be better bent or folded, which facilitates the formation of a four-curved screen design.
  • the first channel region 130 is located between the pixel island 110 and the first opening 121 , and between the first opening 121 and the end of the second opening 122 close to the first opening 121 .
  • the first channel region 130 can bypass the first opening 121 and the second opening 122, and realize efficient use of the space on the display substrate.
  • the first opening 121 overlaps with two adjacent pixel islands 110 in the first direction. Therefore, the distribution area of the first openings is larger, which facilitates the bending of the display substrate.
  • the orthographic projection of the second opening 122 on the first opening 121 is located in the middle of the first opening 121 . Therefore, the distribution of the second opening and the first opening of the display substrate has high symmetry, so that the bending can be performed flexibly.
  • each pixel 140 includes a plurality of sub-pixels 160 , and each sub-pixel 160 includes a pixel driving circuit 162 and an anode 164 electrically connected to the pixel driving circuit 162 .
  • FIG. 2 is a schematic plan view of a pixel in a display substrate according to an embodiment of the present disclosure.
  • 3 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure along the direction AA in FIG. 2 . As shown in FIG. 2 and FIG.
  • the display substrate 100 includes: a base substrate 101, a semiconductor layer 102, a gate insulating layer 103, a first gate layer 104, an interlayer insulating layer 105, a second gate layer 106, The passivation layer 107 and the first conductive layer 108; the semiconductor layer 102 is located on the base substrate 101; the gate insulating layer 103 is located on the side of the semiconductor layer 102 away from the base substrate 101; the first gate layer 104 is located on the gate insulating layer 103 is located on the side away from the semiconductor layer 102; the interlayer insulating layer 105 is located on the side of the first gate layer 104 away from the gate insulating layer 103; the second gate layer 106 is located on the interlayer insulating layer 105 away from the first gate layer 104 The passivation layer 107 is located on the side of the second gate layer 106 away from the interlayer insulating layer 105 ; the first conductive layer 108 is located on the side of the passivation layer 104 away from the first
  • the above-mentioned plurality of first driving lines 142 are located in at least one of the first gate layer 104 and the second gate layer 106 , and the above-mentioned transition lines 112 are located in the first conductive layer 108 . Therefore, by arranging the above-mentioned transfer line 112 on the first conductive layer 108, on the one hand, the existing conductive layer in the display substrate can be used, and on the other hand, it can be disposed in a different layer from the first driving line, so as to facilitate the formation of the above-mentioned cross-connection layer.
  • the stack area 150 can be connected flexibly.
  • the display substrate 100 further includes an insulating layer 109 and a second conductive layer 1010; the insulating layer 109 is located on the side of the first conductive layer 108 away from the passivation layer 107; the second The conductive layer 1010 is located on the side of the insulating layer 109 away from the first conductive layer 108 .
  • the second conductive layer 1010 includes a conductive grid 118 located on the pixel island 110 , and the conductive grid 118 is electrically connected to a plurality of power lines in the pixel island 110 .
  • each pixel driving circuit 162 includes: a first semiconductor unit 221 , a second semiconductor unit 222 , a third semiconductor unit 223 , a fourth semiconductor unit 224 , and a fifth semiconductor unit 225 located in the semiconductor layer 102 .
  • the sixth semiconductor unit 226 and the seventh semiconductor unit 227 the first electrode block 241 located in the first gate layer 104 ; and the second electrode block 261 located in the second gate layer 106 .
  • the first semiconductor unit 221 includes a first channel region 221C and a first source region 221S and a first drain region 221D on both sides of the first channel region 221C, and the second semiconductor unit 222 includes a second channel region 222C and a first drain region 221D.
  • the third semiconductor unit 223 includes the third channel region 223C and the third source on both sides of the third channel region 223C
  • the fourth semiconductor unit 224 includes the fourth channel region 224C and the fourth source region 224S and the fourth drain region 224D on both sides of the fourth channel region 224C
  • the fifth The semiconductor unit 225 includes a fifth channel region 225C and a fifth source region 225S and a fifth drain region 225D on both sides of the fifth channel region 225C
  • the sixth semiconductor unit 226 includes a sixth channel region 226C and a fifth source region 225S on both sides of the fifth channel region 225C.
  • the seventh semiconductor unit 227 includes a seventh channel region 227C and a seventh source region located on both sides of the seventh channel region 227C 227S and the seventh drain region 227D.
  • the third source region 223S, the first drain region 221D and the fifth source region 225S are connected to the first node N1, and the sixth drain region 226D and the third drain region 223D are connected , the first source region 221S, the second drain region 222D and the fourth drain region 224D are connected to the second node N2, the fifth drain region 225D and the seventh drain region 227D are connected;
  • the orthographic projection on the base substrate 101 at least partially overlaps with the orthographic projection of the first electrode blocks 241 on the base substrate 101 to form the storage capacitor Cst.
  • the plurality of first driving lines 142 include: initialization signal lines 1421 located in the second gate layer 106 ; reset signal lines 1422 located in the first gate layer 104 ; gate lines 1423 , located in the first gate layer 104; and the light emission control line 1424, located in the first gate layer 104; the initialization signal line 1421 is connected to the seventh source region 227S and the sixth source region 226S, and the reset signal line 1422 is connected to the seventh source region 227S and the sixth source region 226S.
  • the channel region 227C and the sixth channel region 226C overlap to form the seventh thin film transistor T7 and the sixth thin film transistor T6 with the seventh semiconductor unit 227 and the sixth semiconductor unit 226, and the gate line 1423 is respectively connected with the third channel region 223C and the second channel region 222C overlap to form the third thin film transistor T3 and the second thin film transistor T2 with the third semiconductor unit 223 and the second semiconductor unit 222, and the first electrode block 241 intersects the first channel region 221C stacked to form the first thin film transistor T1 with the first semiconductor unit 221, and the light emission control line 1424 overlapped with the fourth channel region 224C and the fifth channel region 225C to overlap the fourth semiconductor unit 224 and the fifth semiconductor unit 225 A fourth thin film transistor T4 and a fifth thin film transistor T5 are formed.
  • the display substrate 100 further includes a plurality of second driving lines 148; the plurality of second driving lines 148 include: a plurality of power supply lines 1481 located on the first conductive layer 108, each power supply line 1481 and connected to the fourth source region 224S in the pixel driving circuit 162 ; and a plurality of data lines 1482 located in the first conductive layer 108 , and each data line 1482 is connected to the second source region 222S in the pixel driving circuit 162 .
  • the number of patch lines 112 is less than the number of first drive lines 142 . Therefore, the number of the patch cords 112 can be reduced, thereby reducing the area occupied by the multiple patch cables 112 and increasing the pixel density.
  • each pixel island 110 includes at least two pixels 140 arranged along the second direction, and at least two of the plurality of first driving lines 142 are connected to the same patch line 112 . Therefore, the number of patch wires 112 can be reduced, thereby reducing the area occupied by a plurality of patch wires 112, increasing the pixel density, and further ensuring that the first opening and the second opening have larger sizes, thereby further improving the Displays the tensile or bending properties of the substrate.
  • each pixel island 110 includes four pixels 140 arranged in a matrix, and each pixel island 110 includes a first sub-region 114A, a second sub-region 114B, and a first sub-region 114A and a second sub-region 114B.
  • the transition area 116 between the two sub-areas 114B, the first sub-area 114A includes the first pixels 1401 and the second pixels 1402 arranged along the second direction, and the second sub-area 114B includes the third pixels 1403 arranged along the second direction and the fourth pixel 1404.
  • the initialization signal line 1421 of the first pixel 1401 and the initialization signal line 1421 of the third pixel 1403 are the first initialization signal line 1421A
  • the initialization signal line 1421 of the second pixel 1402 and the initialization signal line 1421 of the fourth pixel 1404 are the second initialization signal line 1421 Signal line 1421B
  • the plurality of patch cords 112 include a first patch cable 1121
  • the first initialization signal line 1421A of the first pixel 1401 and the third pixel 1403 is electrically connected to the first patch cable 1121 through the via 152
  • the second pixel 1402 and the second initialization signal line 1421B of the fourth pixel 1404 is connected to the first transition line 1121 through the via hole 152 . Therefore, the display substrate can lead out the initialization signal lines of four pixels through only one patch cord, thereby reducing the number of patch cables, reducing the area occupied by the multiple patch cables, and increasing the pixel density.
  • the reset signal line 1422 of the first pixel 1401 and the reset signal line 1422 of the third pixel 1403 are the first reset signal line 1422A, the reset signal line 1422 of the second pixel 1402 and the fourth reset signal line 1422
  • the reset signal line 1422 of the pixel 1404 is the second reset signal line 1422B; the plurality of transition lines 112 include the second transition line 1122 and the third transition line 1123, and the first reset signal line 1422A of the first pixel 1401 and the third pixel 1403 pass through
  • the via hole 152 is electrically connected to the second patch wire 1122 , and the second reset signal line 1422B of the second pixel 1402 and the fourth pixel 1404 is connected to the third patch wire 1123 through the via hole. Therefore, the display substrate can lead out the reset signal lines of the four pixels through only two patch cables, thereby further reducing the number of patch cables, reducing the area occupied by the multiple patch cables, and increasing the pixel density.
  • the gate line 1423 of the first pixel 1401 and the gate line 1423 of the third pixel 1403 are the first gate line 1423A, the gate line 1423 of the second pixel 1402 and the gate line 1423 of the fourth pixel 1404
  • the line 1423 is the second gate line 1423B;
  • the plurality of transfer lines 112 include a fourth transfer line 1124, and the first gate line 1423A of the first pixel 1401 and the third pixel 1403 is electrically connected to the third transfer line 1123 through the via hole 152,
  • the second gate lines 1423B of the second pixel 1402 and the fourth pixel 1404 are connected to the fourth transition line 1124 through the via hole 152 . Therefore, the display substrate can lead out the gate lines of the four pixels by adding only one patch cord, thereby further reducing the number of patch cables, reducing the area occupied by the multiple patch cables, and increasing the pixel density.
  • the light emission control line 1424 of the first pixel 1401 and the light emission control line 1424 of the third pixel 1403 are the first light emission control line 1424A, the light emission control line 1424 of the second pixel 1402 and the fourth light emission control line 1424
  • the light-emitting control line 1424 of the pixel 1404 is the second light-emitting control line 1424B;
  • the plurality of transition lines 112 include a fifth transition line 1125 and a sixth transition line 1126, and the first light-emitting control line 1424A of the first pixel 1401 and the third pixel 1403 pass through
  • the via hole 152 is electrically connected to the fifth patch wire 1125
  • the second light emission control wires 1424B of the second pixel 1402 and the fourth pixel 1404 are connected to the sixth patch wire 1126 through the via hole 152 . Therefore, the display substrate can lead out the light-emitting control lines of four pixels only by adding two patch cables, thereby further reducing the number of patch cables
  • FIG. 6 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • the light emission control line 1424 of the first pixel 1401 and the light emission control line 1424 of the third pixel 1403 are the first light emission control line 1424A, the light emission control line 1424 of the second pixel 1402 and the light emission control line of the fourth pixel 1404
  • the line 1424 is the second light-emitting control line 1424B;
  • the plurality of transfer lines 112 include the fifth transfer line 1125, and the first light-emitting control line 1424A of the first pixel 1401 and the third pixel 1403 is electrically connected to the fifth transfer line 1125 through the via hole 152
  • the second light-emitting control line 1424B of the second pixel 1402 and the fourth pixel 1404 is connected to the fifth patch line 1125 through the via hole 152 . Therefore, the display substrate can lead out the light-emitting control lines of four pixels only by adding one patch cord, thereby further reducing the number of patch cables
  • the embodiments shown in FIG. 1 and FIG. 6 only illustrate the case where one pixel island 110 includes four pixels 140 arranged in a matrix, but the embodiments of the present disclosure include but are not limited to this, the display substrate can be One patch cord connects different first drive lines with the same signal or with time-divisional signals, thereby reducing the number of patch cords.
  • a plurality of first connection lines 132 are disposed on the first gate layer 104 and the second gate layer 106 .
  • a plurality of first connection lines 132 are alternately disposed on the first gate layer 104 and the second gate layer 106 .
  • the distance between the orthographic projections of the adjacent first connection lines 132 on the base substrate 101 can be set smaller, that is, the plurality of first connection lines can be arranged more densely, thereby reducing the number of first connection lines.
  • the width of a channel region may increase the number of first connection lines in the first channel region.
  • the number of the plurality of patch cords 112 is the same as the number of the multiple first connection cables 132 , and the multiple patch cables 112 are arranged in a one-to-one correspondence with the multiple first connection cables 132 .
  • the display substrate can connect the transition lines in the two pixel islands adjacent in the first direction through the first connection lines, so as to realize connecting a plurality of transition lines in the two pixel islands adjacent in the first direction The first driving line is connected.
  • FIG. 7 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 further includes: a second channel region 170 located between the first opening 121 and the second opening 122 and connecting two adjacent pixel islands 110 in the second direction.
  • Each pixel island 110 includes a plurality of second driving lines 148 extending along the second direction, a plurality of second connecting lines 172 are provided in the second channel region 170 , and the plurality of second connecting lines 172 will be adjacent to each other in the second direction.
  • the plurality of second driving lines 148 of the two pixel islands 110 are connected to each other.
  • the plurality of second driving lines 148 include: a plurality of power supply lines 1481 located in the first conductive layer 108 , each of the power supply lines 1481 and the pixel driving circuit 162 and a plurality of data lines 1482 located in the first conductive layer 108 , and each data line 1482 is connected to the second source region 222S in the pixel driving circuit 162 .
  • the display substrate 100 further includes an insulating layer 109 and a second conductive layer 1010 ; the insulating layer 109 is located on the side of the first conductive layer 108 away from the passivation layer 107 ; The second conductive layer 1010 is located on the side of the insulating layer 109 away from the first conductive layer 108 .
  • the second conductive layer 1010 includes a conductive grid 118 located on the pixel island 110 , and the conductive grid 118 is electrically connected to the plurality of power lines 1481 in the pixel island 110 .
  • the plurality of second connection lines 172 include power connection lines 1721 , which are located in the second conductive layer 1010 and connected to the conductive grid 118 . Since the conductive grid 118 is electrically connected to the plurality of power supply lines 1481 in the pixel island 110, two adjacent pixel islands 110 in the second direction can The power lines 1481 of all the pixels 140 in the two adjacent pixel islands 110 in the direction are connected to each other.
  • FIG. 8 is a schematic diagram of a second conductive layer in a display substrate according to an embodiment of the present disclosure.
  • the power connection line 1721 is located on the second conductive layer 1010 and connected to the conductive grid 118 . Since the conductive grid 118 is electrically connected to the plurality of power supply lines 1481 in the pixel island 110, two adjacent pixel islands 110 in the second direction can The power lines 1481 of all the pixels 140 in the two adjacent pixel islands 110 in the direction are connected to each other.
  • the plurality of second connection lines 172 further include a plurality of data connection lines 1722 , and the plurality of data connection lines 1722 are arranged and connected in a one-to-one correspondence with the plurality of data lines 1482 .
  • the display substrate can connect the data lines 1482 of all the pixels 140 in the two adjacent pixel islands 110 in the second direction through a plurality of data connection lines.
  • a plurality of second connection lines 172 are provided on the first conductive layer 108 and the second conductive layer 1010 ; for example, a plurality of second connection lines 172 are alternately provided on the first conductive layer 108 and The second conductive layer 1010 .
  • the distance between the orthographic projections of the adjacent second connection lines 172 on the base substrate 101 can be set smaller, that is, the plurality of second connection lines can be arranged more densely, thereby reducing the The width of the second channel region or the number of the second connection lines in the second channel region is increased.
  • each pixel 140 includes a first color sub-pixel 1601, a second color sub-pixel 1602 and a third color sub-pixel 1603, and each pixel island 110 includes four pixels 140 arranged in a matrix,
  • Each pixel island 140 includes a first sub-region 144A, a second sub-region 144B, and a transition region 146 located between the first sub-region 144A and the second sub-region 144B;
  • the first sub-region 144A includes a first sub-region 144A arranged along the second direction.
  • a pixel 1401 and a second pixel 1402, the second sub-region 144B includes a third pixel 1403 and a fourth pixel 1404 arranged along the second direction; the data lines 1482 of the first color sub-pixel 1601 in the first pixel 1401 and The data line 1482 of the first color sub-pixel 1601 in the second pixel 1402 is the first data line 1482A, the data line 1482 of the second color sub-pixel 1602 in the first pixel 1401 and the second color sub-pixel in the second pixel 1402
  • the data line 1482 of the pixel 1602 is the second data line 1482B, the data line 1482 of the third color sub-pixel 1603 in the first pixel 1401 and the data line 1482 of the third color sub-pixel 1603 in the second pixel 1402 are the third data Line 1482C, the data line 1482 of the first color sub-pixel 1601 in the third pixel 1403 and the data line 1482 of the first color sub-pixel 1601 in the fourth pixel 1404 are the fourth data line 14
  • 144A, 144B, 146, 1401, 1402, 1403 and 1404 are not shown in FIG. 7;
  • the division of the second pixel 1402 , the third pixel 1403 and the fourth pixel 1404 can be referred to FIG. 1 .
  • the plurality of second connection lines 172 include a first data connection line 1722A, a second data connection line 1722B, a third data connection line 1722C, a fourth data connection line 1722D, and a fifth data connection line 1722E and the sixth data connection line 1722F;
  • the first data connection line 1722A is connected with the first data line 1482A
  • the second data connection line 1722B is connected with the second data line 1482B
  • the third data connection line 1722C is connected with the third data line 1482C
  • the fourth data connection line 1722D is connected with the fourth data line 1482D
  • the fifth data connection line 1722E is connected with the fifth data line 1284E
  • the sixth data connection line 1722F is connected with the sixth data line 1482D. Therefore, the display substrate can connect the data lines of sub-pixels located in the same column in two adjacent pixel islands in the second direction through the same data connection line.
  • the first data connection line 1722A, the second data connection line 1722B, and the fifth data connection line 1722E are located on the first conductive layer 108 ;
  • the line 1722C, the fourth data connection line 1722D and the sixth data connection line 1722F are located on the second conductive layer 1010 .
  • the first data connection line 1722A, the second data connection line 1722B, the third data connection line 1722C, the fourth data connection line 1722D, the fifth data connection line 1722E, the sixth data connection line 1722F and the power connection line 1721 are
  • the distance between the orthographic projections on the base substrate 101 can be set to be smaller, that is, the second connection lines can be set more densely, so that the width of the second channel region can be reduced or the number of thirds in the second channel region can be increased. 2 The number of connecting lines.
  • FIG. 9 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 includes a first display area 181 and a second display area 182 , the pixel density of the first display area 181 is greater than that of the second display area 182 , and the pixel islands 110 are located in the second display area 182 .
  • the third connection line can also be routed through the above-mentioned first channel area, second channel area and transfer area.
  • the display substrate 100 further includes a transition area 183 between the first display area 181 and the second display area 182 , the transition area 183 has a pixel density less than that of the first display area 181 , but the transition area 183 may be greater than or equal to the pixel density of the second display area 182 .
  • the transition region 183 is not provided with the above-mentioned openings, and can be provided with a row driving circuit for driving the pixels of the display substrate 100 to perform light-emitting display.
  • the second display area 182 is located at a corner of the first display area 181 .
  • the planar shape of the display substrate 100 is approximately a rounded rectangle, and the second display areas 182 are located at four corner areas of the display substrate 100 , that is, the above-mentioned second display areas 182 can be curved, thereby realizing a four-curved screen design.
  • the planar shape of the first display area 181 includes a first rectangle and two second rectangles on both sides of the first rectangle in the second direction
  • the second display The planar shape of the region includes four fan shapes, which are respectively located on two sides of the two second rectangles along the first direction.
  • the display substrate 100 of the second display area 182 is bendable in a direction perpendicular to the first display area 181 .
  • the display substrate 100 includes a light-emitting side, that is, the side where the light emitted by the display substrate 100 exits, and the portion of the display substrate 100 located in the second display area 182 can be bent to the side opposite to the light-emitting side, thereby realizing a
  • the 3D stereoscopic effect of the curved shape can create a sense of stereoscopic immersion.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • the display device 900 includes the above-mentioned display substrate 100 . Since the display substrate 100 can realize the wiring of the driving lines in the stretchable region or the bending region with the opening pattern, the display device 900 including the display substrate 100 can also realize the wiring in the stretchable region or the bending region with the opening pattern.
  • the folding area realizes the wiring of the driving lines, so that the four-curved screen design can be realized while having a narrow frame width.
  • the above-mentioned display device may be an electronic product with a display function, such as a television, a mobile phone, a computer, a navigator, and an electronic picture frame.
  • a display function such as a television, a mobile phone, a computer, a navigator, and an electronic picture frame.

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Abstract

一种显示基板和显示装置。该显示基板包括：多个像素岛、第一开口、第二开口和第一通道区；第一通道区至少部分位于第一开口和第二开口之间并将在第一方向上相邻的两个像素岛相连；各像素岛包括至少一个像素，各像素包括沿第一方向延伸的多条第一驱动线，第一通道区设置有多条第一连接线，各像素岛还包括沿第二方向延伸的多条转接线，多条转接线与多条第一驱动线异层设置，且相互交叉以形成多个交叠区；多条转接线通过位于部分交叠区的过孔与多条第一驱动线电性相连，在第一方向上相邻的两个像素岛中的多条转接线分别与第一通道区中的多条第一连接线相连。由此，该显示基板可实现在具有开口图案的可拉伸区或者弯折区实现驱动线的布线。

Description

显示基板和显示装置 技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，柔性显示技术因其功耗低、体积小、便携、显示方式多样等优点已经被广泛地应用在各种各样的显示装置中。为了提升显示品质和使用效果，四曲面屏设计在手机、平板电脑等智能电子产品中得到广泛应用。四曲面屏设计是结合3D玻璃盖板(Cover Glass)贴合技术，将显示基板的边缘或角落按照一定弯曲半径进行弯曲并形成弧度，以实现正面侧面的全面立体显示，从而实现四曲面形态的3D立体效果，由此可营造显示立体沉浸感，符合未来技术发展趋势。
发明内容
本公开实施例提供一种显示基板和显示装置。该显示基板包括：多个像素岛、第一开口、第二开口和第一通道区；多个像素岛沿第一方向和第二方向阵列设置；第一开口位于在第二方向上相邻的两个像素岛之间；第二开口位于在第一方向上相邻的两个像素岛之间；第一通道区至少部分位于第一开口和第二开口之间；各像素岛包括至少一个像素，各像素包括沿第一方向延伸的多条第一驱动线，第一通道区设置有多条第一连接线，各像素岛还包括沿第二方向延伸的多条转接线，多条转接线与多条第一驱动线异层设置，且相互交叉以形成多个交叠区；多条转接线通过位于部分交叠区的过孔与多条第一驱动线电性相连，在第一方向上相邻的两个像素岛中的多条转接线分别与第一通道区中的多条第一连接线相连。该显示基板通过多条转接线将各像素岛中的多条第一驱动线引出，并通过第一通道区中多条第一连接线将在第一方向上相邻的两个像素岛的多条第一驱动线分别相连，从而实现将在第一方向上相邻的两个像素岛中的多条第一驱动线相连。由此，该显示基板可实现在具有开口图案的可拉伸区或者弯折区实现驱动线的布线。
本公开至少一个实施例提供一种显示基板，其包括：多个像素岛，沿第一方向和第二方向阵列设置；第一开口，位于在所述第二方向上相邻的两个所述 像素岛之间；第二开口，位于在所述第一方向上相邻的两个所述像素岛之间；以及第一通道区，位于所述第一开口和所述第二开口之间，各所述像素岛包括至少一个像素，各所述像素包括沿所述第一方向延伸的多条第一驱动线，所述第一通道区设置有多条第一连接线，各所述像素岛还包括沿所述第二方向延伸的多条转接线，所述多条转接线与所述多条第一驱动线异层设置，且相互交叉以形成多个交叠区；所述多条转接线通过位于部分所述交叠区的过孔与所述多条第一驱动线电性相连，在所述第一方向上相邻的两个所述像素岛中的多条转接线分别与所述第一通道区中的所述多条第一连接线相连。
例如，在本公开一实施例提供的显示基板中，各所述像素岛包括两个子区域和位于两个子区域之间的转接区，所述像素岛包括的所述至少一个像素设置在所述两个子区域中，所述转接线位于所述转接区。
例如，在本公开一实施例提供的显示基板中，所述多条第一驱动线穿过所述两个子区域和所述转接区，所述多条第一驱动线被配置为驱动所述两个子区域中的像素以进行发光显示。
例如，在本公开一实施例提供的显示基板中，所述第一开口沿所述第一方向延伸，所述第二开口沿所述第二方向延伸，所述第一开口和所述第二开口在所述第一方向上交替排列，所述第一开口和所述第二开口在所述第二方向上也交替排列。
例如，在本公开一实施例提供的显示基板中，所述第一通道区位于所述像素岛与所述第一开口之间。
例如，在本公开一实施例提供的显示基板中，各所述像素包括多个子像素，各所述子像素包括像素驱动电路和与所述像素驱动电路电性相连的阳极。
例如，在本公开一实施例提供的显示基板中，该显示基板包括：衬底基板；半导体层，位于所述衬底基板上；栅极绝缘层，位于所述半导体层远离所述衬底基板的一侧；第一栅极层，位于所述栅极绝缘层远离所述半导体层的一侧；层间绝缘层，位于所述第一栅极层远离所述栅极绝缘层的一侧；第二栅极层，位于所述层间绝缘层远离所述第一栅极层的一侧；钝化层，位于所述第二栅极层远离所述层间绝缘层的一侧；以及第一导电层，位于所述钝化层远离所述第二栅极层的一侧，所述多条第一驱动线位于所述第一栅极层和所述第二栅极层中的至少之一，所述转接线位于所述第一导电层。
例如，在本公开一实施例提供的显示基板中，各所述像素驱动电路包括： 位于所述半导体层的第一半导体单元、第二半导体单元、第三半导体单元、第四半导体单元、第五半导体单元、第六半导体单元和第七半导体单元；位于所述第一栅极层的第一电极块；以及位于所述第二栅极层的第二电极块，所述第一半导体单元包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区，所述第二半导体单元包括第二沟道区和位于所述第二沟道区两侧的第二源极区和第二漏极区，所述第三半导体单元包括第三沟道区和位于所述第三沟道区两侧的第三源极区和第三漏极区，所述第四半导体单元包括第四沟道区和位于所述第四沟道区两侧的第四源极区和第四漏极区，所述第五半导体单元包括第五沟道区和位于所述第五沟道区两侧的第五源极区和第五漏极区，所述第六半导体单元包括第六沟道区和位于所述第六沟道区两侧的第六源极区和第六漏极区，所述第七半导体单元包括第七沟道区和位于所述第七沟道区两侧的第七源极区和第七漏极区，所述第三源极区、所述第一漏极区和所述第五源极区连接至第一节点，所述第六漏极区和所述第三漏极区相连，所述第一源极区、所述第二漏极区和所述第四漏极区连接至第二节点，所述第五漏极区和所述第七漏极区相连，所述第二电极块在衬底基板上的正投影与所述第一电极块在所述衬底基板上的正投影至少部分重叠以形成存储电容。
例如，在本公开一实施例提供的显示基板中，所述多条第一驱动线包括：初始化信号线，位于所述第二栅极层；复位信号线，位于所述第一栅极层；栅线，位于所述第一栅极层；以及发光控制线，位于所述第一栅极层，所述初始化信号线与所述第七源极区和第六源极区相连，所述复位信号线与所述第七沟道区和所述第六沟道区交叠，所述栅线分别与所述第三沟道区和所述第二沟道区交叠，所述第一电极块与所述第一沟道区交叠，所述发光控制线与所述第四沟道区和所述第五沟道区交叠。
例如，在本公开一实施例提供的显示基板中，各所述像素岛包括沿第二方向排列的至少两个像素，所述多条第一驱动线中的至少两条与同一条所述转接线相连。
例如，在本公开一实施例提供的显示基板中，各所述像素岛包括呈矩阵排列的四个所述像素，各所述像素岛包括第一子区域、第二子区域和位于所述第一子区域和所述第二子区域之间的转接区，所述第一子区域包括沿所述第二方向排列的第一像素和第二像素，所述第二子区域包括沿所述第二方向排列的第三像素和第四像素，所述第一像素的所述初始化信号线和所述第三像素的所述 初始化信号线为第一初始化信号线，所述第二像素的所述初始化信号线和所述第四像素的所述初始化信号线为第二初始化信号线，所述多条转接线包括第一转接线，所述第一像素和所述第三像素的所述第一初始化信号线通过过孔与所述第一转接线电性相连，所述第二像素和所述第四像素的所述第二初始化信号线通过过孔与所述第一转接线相连。
例如，在本公开一实施例提供的显示基板中，所述第一像素的所述复位信号线和所述第三像素的所述复位信号线为第一复位信号线，所述第二像素的所述复位信号线和所述第四像素的所述复位信号线为第二复位信号线，所述多条转接线包括第二转接线和第三转接线，所述第一像素和所述第三像素的所述第一复位信号线通过过孔与所述第二转接线电性相连，所述第二像素和所述第四像素的所述第二复位信号线通过过孔与所述第三转接线相连。
例如，在本公开一实施例提供的显示基板中，所述第一像素的所述栅线和所述第三像素的所述栅线为第一栅线，所述第二像素的所述栅线和所述第四像素的所述栅线为第二栅线，所述多条转接线包括第四转接线，所述第一像素和所述第三像素的所述第一栅线通过过孔与所述第三转接线电性相连，所述第二像素和所述第四像素的所述第二栅线通过过孔与所述第四转接线相连。
例如，在本公开一实施例提供的显示基板中，所述第一像素的所述发光控制线和所述第三像素的所述发光控制线为第一发光控制线，所述第二像素的所述发光控制线和所述第四像素的所述发光控制线为第二发光控制线，所述多条转接线包括第五转接线，所述第一像素和所述第三像素的所述第一发光控制线通过过孔与所述第五转接线电性相连，所述第二像素和所述第四像素的所述第二发光控制线通过过孔与所述第五转接线相连。
例如，在本公开一实施例提供的显示基板中，所述第一像素的所述发光控制线和所述第三像素的所述发光控制线为第一发光控制线，所述第二像素的所述发光控制线和所述第四像素的所述发光控制线为第二发光控制线，所述多条转接线包括第五转接线和第六转接线，所述第一像素和所述第三像素的所述第一发光控制线通过过孔与所述第五转接线电性相连，所述第二像素和所述第四像素的所述第二发光控制线通过过孔分别与所述第六转接线相连。
例如，在本公开一实施例提供的显示基板中，所述多条第一连接线设置在所述第一栅极层和所述第二栅极层。
例如，在本公开一实施例提供的显示基板中，所述多条转接线的数量小于 所述多条第一驱动线的数量。
例如，在本公开一实施例提供的显示基板中，其还包括：第二通道区，各所述像素岛包括沿所述第二方向延伸的多条第二驱动线，所述第二通道区设置有多条第二连接线，所述多条第二连接线分别将在所述第二方向上相邻的两个所述像素岛的所述多条第二驱动线相连。
例如，在本公开一实施例提供的显示基板中，多条第二驱动线包括：多条电源线，位于所述第一导电层，各所述电源线且与所述像素驱动电路中的所述第四源极区相连；以及多条数据线，位于所述第一导电层，各所述数据线与所述像素驱动电路中的所述第二源极区相连。
例如，在本公开一实施例提供的显示基板中，其还包括：绝缘层，位于所述第一导电层远离钝化层的一侧；以及第二导电层，位于所述绝缘层远离所述第一导电层的一侧，所述第二导电层包括位于所述像素岛的导电网格，所述导电网格与所述像素岛中的所述多条电源线均电性相连，所述多条第二连接线包括电源连接线，位于所述第二导电层，且与所述导电网格相连。
例如，在本公开一实施例提供的显示基板中，所述多条第二连接线还包括多条数据连接线，所述多条数据线与所述多条数据连接线一一对应设置并连接。
例如，在本公开一实施例提供的显示基板中，所述多条第二连接线设置在所述第一导电层和所述第二导电层。
例如，在本公开一实施例提供的显示基板中，各所述像素包括第一颜色子像素、第二颜色子像素和第三颜色子像素，各所述像素岛包括呈矩阵排列的四个所述像素，各所述像素岛包括第一子区域、第二子区域和位于所述第一子区域和所述第二子区域之间的转接区，所述第一子区域包括沿所述第二方向排列的第一像素和第二像素，所述第二子区域包括沿所述第二方向排列的第三像素和第四像素，所述第一像素中的所述第一颜色子像素的数据线和所述第二像素中的第一颜色子像素的数据线为第一数据线，所述第一像素中的所述第二颜色子像素的数据线和所述第二像素中的第二颜色子像素的数据线为第二数据线，所述第一像素中的所述第三颜色子像素的数据线和所述第二像素中的第三颜色子像素的数据线为第三数据线，所述第三像素中的所述第一颜色子像素的数据线和所述第四像素中的第一颜色子像素的数据线为第四数据线，所述第三像素中的所述第二颜色子像素的数据线和所述第四像素中的第二颜色子像素的 数据线为第五数据线，所述第三像素中的所述第三颜色子像素的数据线和所述第四像素中的第三颜色子像素的数据线为第六数据线，所述多条第二连接线包括第一数据连接线、第二数据连接线、第三数据连接线、第四数据连接线、第五数据连接线和第六数据连接线，所述第一数据连接线与所述第一数据线相连，所述第二数据连接线与所述第二数据线相连，所述第三数据连接线与所述第三数据线相连，所述第四数据连接线与所述第四数据线相连，所述第五数据连接线与所述第五数据线相连，所述第六数据连接线与所述第六数据线相连。
例如，在本公开一实施例提供的显示基板中，所述第一数据连接线、所述第二数据连接线、所述第五数据连接线位于所述第一导电层，所述电源连接线、所述第三数据连接线、所述第四数据连接线和所述第六数据连接线位于所述第二导电层。
例如，在本公开一实施例提供的显示基板中，所述显示基板包括第一显示区域和第二显示区域，所述第一显示区域的像素密度大于所述第二显示区域的像素密度，所述像素岛位于所述第二显示区域。
例如，在本公开一实施例提供的显示基板中，所述第二显示区域位于所述第一显示区域的角落。
例如，在本公开一实施例提供的显示基板中，所述显示基板的所述第二显示区域在垂直于所述第一显示区域的方向上可弯曲。
本公开至少一个实施例还提供一种显示装置，其包括上述任一项所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种显示基板的平面示意图；
图2为本公开一实施例提供的一种显示基板中像素的平面示意图；
图3为本公开一实施例提供的一种显示基板沿图2中AA方向的剖面示意图；
图4A-4D为本公开一实施例提供一种显示基板中像素驱动电路的多个膜层的示意图；
图5为本公开一实施例提供的一种显示基板中像素驱动电路的等效示意图；
图6为本公开一实施例提供的另一种显示基板的平面示意图；
图7为本公开一实施例提供的一种显示基板的平面示意图；
图8为本公开一实施例提供的一种显示基板中第二导电层的示意图；
图9为本公开一实施例提供的一种显示基板的平面示意图；以及
图10为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
通常，可通过降低显示基板的四个角落区域的像素密度(PPI)，并在这四个角落区域设置带有开口图案的可拉伸结构，从而可将显示基板的边缘或角落按照一定弯曲半径进行弯曲，从而实现四曲面屏设计。此时，位于四个角落区域的可拉伸结构的拉伸量越大，则这四个角落区域的像素密度越低，即为低像素密度区。另一方面，由于这四个角落区域设置有开口图案，这些开口图案将像素阵列分割为孤立的多个像素岛；而这些像素岛中的像素的驱动线(例如栅线、数据线等)均需要相互连接，但是这些驱动线无法直接跨过这些开口图案，因此像素单元的控制线和数据线需要绕开开口图案进行布线。
对此，本公开实施例提供一种显示基板和显示装置。该显示基板包括：多个像素岛、第一开口、第二开口和第一通道区；多个像素岛沿第一方向和第二 方向阵列设置；第一开口位于在第二方向上相邻的两个像素岛之间；第二开口位于在第一方向上相邻的两个像素岛之间；第一通道区至少部分位于第一开口和第二开口之间并将在第一方向上相邻的两个像素岛相连；各像素岛在第一方向上与第一开口交叠，各像素岛包括至少一个像素，各像素包括沿第一方向延伸的多条第一驱动线，第一通道区设置有多条第一连接线，各像素岛还包括沿第二方向延伸的多条转接线，多条转接线与多条第一驱动线异层设置，且相互交叉以形成多个交叠区；多条转接线通过位于部分交叠区的过孔与多条第一驱动线电性相连，在第一方向上相邻的两个像素岛中的多条转接线分别与第一通道区中的多条第一连接线相连。该显示基板通过多条转接线将各像素岛中的多条第一驱动线引出，并通过第一通道区中多条第一连接线将在第一方向上相邻的两个像素岛的多条第一驱动线分别相连，从而实现将在第一方向上相邻的两个像素岛中的多条第一驱动线相连。由此，该显示基板可实现在具有开口图案的可拉伸区或者弯折区实现驱动线的布线。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图1为本公开一实施例提供的一种显示基板的平面示意图。如图1所示，该显示基板100包括多个像素岛110、第一开口121、第二开口122和第一通道区130；多个像素岛110沿第一方向和第二方向阵列设置。像素岛110之间的距离较大，例如，相邻像素岛110之间的距离大于像素岛110中相邻像素140之间的距离。第一开口121位于在第二方向上相邻的两个像素岛110之间；第二开口122位于在第一方向上相邻的两个像素岛110之间；第一通道区130至少部分位于第一开口121和第二开口122之间并将在第一方向上相邻的两个像素岛110相连；各像素岛110在第一方向上与第一开口121交叠，也就是说，像素岛在沿第一方向延伸的一条参考直线上的正投影与第一开口在该参考直线上的正投影相互交叠。
各像素岛110包括至少一个像素140，各像素140包括沿第一方向延伸的多条第一驱动线142，第一通道区130设置有多条第一连接线132，各像素岛110还包括沿第二方向延伸的多条转接线112，多条转接线112与多条第一驱动线142异层设置，且相互交叉以形成多个交叠区150；多条转接线112通过位于部分交叠区150的过孔152与多条第一驱动线142电性相连，在第一方向上相邻的两个像素岛110中的多条转接线112分别与第一通道区130中的多条 第一连接线132相连。需要说明的是，在显示基板中，第一驱动线可为栅线，位于第一栅极层和第二栅极层中的一层；此时，上述的转接线可位于其他导电层，例如第一栅极层和第二栅极层中的另一层、第一源漏金属层、第二源漏金属层、或者遮光层。另外，上述的过孔根据其所连接的第一驱动线和转接线的不同而具有不同的深度，并且相邻的过孔错位设置，避免相互干扰。在本公开实施例提供的显示基板中，在各像素岛110中，各像素140的多条第一驱动线142可通过转接线112引出，然后在第一方向上相邻的两个像素岛110中的多条转接线112分别与第一通道区130中的多条第一连接线132相连，从而实现将在第一方向上相邻的两个像素岛110中的多条第一驱动线142相连。由此，该显示基板可实现在具有开口图案的可拉伸区或者弯折区实现驱动线的布线。并且，该显示基板通过充分利用第一开口和第二开口之间的第一通道区，从而可保证第一开口和第二开口具有较大的尺寸，从而也可提高该显示基板的拉伸或弯曲性能。
在一些示例中，如图1所示，各像素岛110包括两个子区域114和位于两个子区域114之间的转接区116，像素岛110包括的至少一个像素140设置在两个子区域114中，转接线112位于转接区116。由此，该显示基板通过在像素岛110中设置转接区116来放置上述的转接线112，并且将转接区116设置在两个子区域114之间，从可提高像素140在像素岛110中的分布对称性。
在一些示例中，如图1所示，多条第一驱动线142穿过两个子区域114和转接区116，多条第一驱动线142被配置为驱动两个子区域114中的像素140以进行发光显示。需要说明的是，两个子区域中的一个可以是虚设区域(dummy)，即不进行显示的区域。
例如，上述的第一驱动线142可包括栅线、发射控制线、初始化线等沿第一方向延伸的驱动线。
在一些示例中，如图1所示，第一开口121沿所述第一方向延伸，第二开口122沿第二方向延伸，第一开口121和第二开口122在第一方向上交替排列，第一开口121和第二开口122在第二方向上也交替排列。由此，在第一开口和第二开口所在的区域，该显示基板可更好地进行弯曲或者折叠，便于形成实现四曲面屏设计。
在一些示例中，如图1所示，第一通道区130位于像素岛110与第一开口121之间，且位于第一开口121与第二开口122靠近第一开口121的端部之间。 由此，第一通道区130可绕开第一开口121和第二开口122，并实现高效利用显示基板上的空间。
在一些示例中，如图1所示，第一开口121在第一方向上与相邻的两个像素岛110均交叠。由此，第一开口的分布面积较大，从而利于显示基板进行弯曲。
在一些示例中，如图1所示，第二开口122在第一开口121上的正投影位于第一开口121的中间。由此，该显示基板的第二开口和第一开口的分布具有较高的对称性，从而可灵活地进行弯曲。
在一些示例中，如图1所示，各像素140包括多个子像素160，各子像素160包括像素驱动电路162和像素驱动电路162电性相连的阳极164。
图2为本公开一实施例提供的一种显示基板中像素的平面示意图。图3为本公开一实施例提供的一种显示基板沿图2中AA方向的剖面示意图。如图2和图3所示，该显示基板100包括：衬底基板101、半导体层102、栅极绝缘层103、第一栅极层104、层间绝缘层105、第二栅极层106、钝化层107和第一导电层108；半导体层102位于衬底基板101上；栅极绝缘层103位于半导体层102远离衬底基板101的一侧；第一栅极层104位于栅极绝缘层103远离半导体层102的一侧；层间绝缘层105位于第一栅极层104远离栅极绝缘层103的一侧；第二栅极层106位于层间绝缘层105远离第一栅极层104的一侧；钝化层107位于第二栅极层106远离层间绝缘层105的一侧；第一导电层108位于钝化层104远离第二栅极层106的一侧。上述的多条第一驱动线142位于第一栅极层104和第二栅极层106中的至少之一，上述的转接线112位于第一导电层108。由此，通过将上述的转接线112设置在第一导电层108，一方面可利用该显示基板中既有的导电层，另一方面可与第一驱动线异层设置，方便形成上述的交叠区150，从可灵活地进行连线。
在一些示例中，如图2和图3所示，该显示基板100还包括绝缘层109和第二导电层1010；绝缘层109位于第一导电层108远离钝化层107的一侧；第二导电层1010位于绝缘层109远离第一导电层108的一侧。第二导电层1010包括位于像素岛110的导电网格118，导电网格118与像素岛110中的多条电源线均电性相连。
图4A-4D为本公开一实施例提供一种显示基板中像素驱动电路的多个膜层的示意图；图5为本公开一实施例提供的一种显示基板中像素驱动电路的等 效示意图。如图4A和图5所示，各像素驱动电路162包括：位于半导体层102的第一半导体单元221、第二半导体单元222、第三半导体单元223、第四半导体单元224、第五半导体单元225、第六半导体单元226和第七半导体单元227；位于第一栅极层104的第一电极块241；以及位于第二栅极层106的第二电极块261。第一半导体单元221包括第一沟道区221C和位于第一沟道区221C两侧的第一源极区221S和第一漏极区221D，第二半导体单元222包括第二沟道区222C和位于第二沟道区222C两侧的第二源极区222S和第二漏极区222D，第三半导体单元223包括第三沟道区223C和位于第三沟道区223C两侧的第三源极区223S和第三漏极区223D，第四半导体单元224包括第四沟道区224C和位于第四沟道区224C两侧的第四源极区224S和第四漏极区224D，第五半导体单元225包括第五沟道区225C和位于第五沟道区225C两侧的第五源极区225S和第五漏极区225D，第六半导体单元226包括第六沟道区226C和位于第六沟道区226C两侧的第六源极区226S和第六漏极区226D，第七半导体单元227包括第七沟道区227C和位于第七沟道区227C两侧的第七源极区227S和第七漏极区227D。
如图4A和图5所示，第三源极区223S、第一漏极区221D和第五源极区225S连接至第一节点N1，第六漏极区226D和第三漏极区223D相连，第一源极区221S、第二漏极区222D和第四漏极区224D连接至第二节点N2，第五漏极区225D和第七漏极区227D相连；第二电极块261在衬底基板101上的正投影与第一电极块241在衬底基板101上的正投影至少部分重叠以形成存储电容Cst。
如图4B、图4C和图5所示，多条第一驱动线142包括：初始化信号线1421，位于第二栅极层106；复位信号线1422，位于第一栅极层104；栅线1423，位于第一栅极层104；以及发光控制线1424，位于第一栅极层104；初始化信号线1421与第七源极区227S和第六源极区226S相连，复位信号线1422与第七沟道区227C和第六沟道区226C交叠，以与第七半导体单元227和第六半导体单元226形成第七薄膜晶体管T7和第六薄膜晶体管T6，栅线1423分别与第三沟道区223C和第二沟道区222C交叠，以与第三半导体单元223和第二半导体单元222形成第三薄膜晶体管T3和第二薄膜晶体管T2，第一电极块241与第一沟道区221C交叠，以与第一半导体单元221形成第一薄膜晶体管T1，发光控制线1424与第四沟道区224C和第五沟道区225C交叠，以与第四 半导体单元224和第五半导体单元225形成第四薄膜晶体管T4和第五薄膜晶体管T5。
如图4D和图5所示，该显示基板100还包括多条第二驱动线148；多条第二驱动线148包括：多条电源线1481，位于第一导电层108，各电源线1481且与像素驱动电路162中的第四源极区224S相连；以及多条数据线1482，位于第一导电层108，各数据线1482与像素驱动电路162中的第二源极区222S相连。
在一些示例中，如图1所示，多条转接线112的数量小于多条第一驱动线142的数量。从而可减小转接线112的数量，从而降低多条转接线112所占据的面积，提高像素密度。
在一些示例中，如图1所示，各像素岛110包括沿第二方向排列的至少两个像素140，多条第一驱动线142中的至少两条与同一条转接线112相连。由此，可减小转接线112的数量，从而降低多条转接线112所占据的面积，提高像素密度，并且可进一步保证第一开口和第二开口具有较大的尺寸，从而可进一步提高该显示基板的拉伸或弯曲性能。
在一些示例中，如图1所示，各像素岛110包括呈矩阵排列的四个像素140，各像素岛110包括第一子区域114A、第二子区域114B和位于第一子区域114A和第二子区域114B之间的转接区116，第一子区域114A包括沿第二方向排列的第一像素1401和第二像素1402，第二子区域114B包括沿第二方向排列的第三像素1403和第四像素1404。第一像素1401的初始化信号线1421和第三像素1403的初始化信号线1421为第一初始化信号线1421A，第二像素1402的初始化信号线1421和第四像素1404的初始化信号线1421为第二初始化信号线1421B；多条转接线112包括第一转接线1121，第一像素1401和第三像素1403的第一初始化信号线1421A通过过孔152与第一转接线1121电性相连，第二像素1402和第四像素1404的第二初始化信号线1421B通过过孔152与第一转接线1121相连。由此，该显示基板可仅通过一条转接线就可将四个像素的初始化信号线引出，从而可降低转接线的数量，以降低多条转接线所占据的面积，提高像素密度。
在一些示例中，如图1所示，第一像素1401的复位信号线1422和第三像素1403的复位信号线1422为第一复位信号线1422A，第二像素1402的复位信号线1422和第四像素1404的复位信号线1422为第二复位信号线1422B； 多条转接线112包括第二转接线1122和第三转接线1123，第一像素1401和第三像素1403的第一复位信号线1422A通过过孔152与第二转接线1122电性相连，第二像素1402和第四像素1404的第二复位信号线1422B通过过孔与第三转接线1123相连。由此，该显示基板可仅通过两条转接线就可将四个像素的复位信号线引出，从而可进一步降低转接线的数量，以降低多条转接线所占据的面积，提高像素密度。
在一些示例中，如图1所示，第一像素1401的栅线1423和第三像素1403的栅线1423为第一栅线1423A，第二像素1402的栅线1423和第四像素1404的栅线1423为第二栅线1423B；多条转接线112包括第四转接线1124，第一像素1401和第三像素1403的第一栅线1423A通过过孔152与第三转接线1123电性相连，第二像素1402和第四像素1404的第二栅线1423B通过过孔152与第四转接线1124相连。由此，该显示基板可仅通过增加一条转接线就可将四个像素的栅线引出，从而可进一步降低转接线的数量，以降低多条转接线所占据的面积，提高像素密度。
在一些示例中，如图1所示，第一像素1401的发光控制线1424和第三像素1403的发光控制线1424为第一发光控制线1424A，第二像素1402的发光控制线1424和第四像素1404的发光控制线1424为第二发光控制线1424B；多条转接线112包括第五转接线1125和第六转接线1126，第一像素1401和第三像素1403的第一发光控制线1424A通过过孔152与第五转接线1125电性相连，第二像素1402和第四像素1404的第二发光控制线1424B通过过孔152与第六转接线1126相连。由此，该显示基板可仅通过增加二条转接线就可将四个像素的发光控制线引出，从而可进一步降低转接线的数量，以降低多条转接线所占据的面积，提高像素密度。
图6为本公开一实施例提供的另一种显示基板的平面示意图。如图6所示，第一像素1401的发光控制线1424和第三像素1403的发光控制线1424为第一发光控制线1424A，第二像素1402的发光控制线1424和第四像素1404的发光控制线1424为第二发光控制线1424B；多条转接线112包括第五转接线1125，第一像素1401和第三像素1403的第一发光控制线1424A通过过孔152与第五转接线1125电性相连，第二像素1402和第四像素1404的第二发光控制线1424B通过过孔152与第五转接线1125相连。由此，该显示基板可仅通过增加一条转接线就可将四个像素的发光控制线引出，从而可进一步降低转接 线的数量，以降低多条转接线所占据的面积，提高像素密度。
值得注意的是，图1和图6所示的实施例仅示出了一个像素岛110包括矩阵排列的四个像素140的情况，但本公开实施例包括但不限于此，该显示基板可通过一条转接线将信号相同或者信号可分时的不同第一驱动线相连，从而减小转接线的数量。
在一些示例中，如图1所示，多条第一连接线132设置在第一栅极层104和第二栅极层106。例如，多条第一连接线132交替设置在第一栅极层104和第二栅极层106。此时，相邻的第一连接线132在衬底基板101上的正投影之间的距离可设置得较小，也就是说，多条第一连接线可设置得更密集，从而可降低第一通道区的宽度或者增加第一通道区中第一连接线的数量。
在一些示例中，如图1所示，多条转接线112的数量与多条第一连接线132的数量相同，多条转接线112与多条第一连接线132一一对应设置。由此，该显示基板可通过第一连接线将在第一方向上相邻的两个像素岛中的转接线相连，从而实现将在第一方向上相邻的两个像素岛中的多条第一驱动线相连。
图7为本公开一实施例提供的一种显示基板的平面示意图。如图7所示，该显示基板100还包括：第二通道区170，位于第一开口121和第二开口122之间并将在第二方向上相邻的两个像素岛110相连。各像素岛110包括沿第二方向延伸的多条第二驱动线148，第二通道区170设置有多条第二连接线172，多条第二连接线172分别将在第二方向上相邻的两个像素岛110的多条第二驱动线148相连。
在一些示例中，如图2、图3和图7所示，多条第二驱动线148包括：多条电源线1481，位于第一导电层108，各电源线1481且与像素驱动电路162中的第四源极区224S相连；以及多条数据线1482，位于第一导电层108，各数据线1482与像素驱动电路162中的第二源极区222S相连。
在一些示例中，如图2、图3和图7所示，该显示基板100还包括绝缘层109和第二导电层1010；绝缘层109位于第一导电层108远离钝化层107的一侧；第二导电层1010位于绝缘层109远离第一导电层108的一侧。第二导电层1010包括位于像素岛110的导电网格118，导电网格118与像素岛110中的多条电源线1481均电性相连。
此时，如图7所示，多条第二连接线172包括电源连接线1721，位于第二导电层1010，且与导电网格118相连。由于导电网格118与像素岛110中的多 条电源线1481均电性相连，因此在第二方向上相邻的两个像素岛110可仅通过一条第二连接线172就可将在第二方向上相邻的两个像素岛110中所有像素140的电源线1481相连。
图8为本公开一实施例提供的一种显示基板中第二导电层的示意图。如图8所示，电源连接线1721位于第二导电层1010，且与导电网格118相连。由于导电网格118与像素岛110中的多条电源线1481均电性相连，因此在第二方向上相邻的两个像素岛110可仅通过一条第二连接线172就可将在第二方向上相邻的两个像素岛110中所有像素140的电源线1481相连。
在一些示例中，如图7所示，多条第二连接线172还包括多条数据连接线1722，多条数据连接线1722与多条数据线1482一一对应设置并连接。由此，该显示基板可通过多条数据连接线将在第二方向上相邻的两个像素岛110中所有像素140的数据线1482相连。
在一些示例中，如图7所示，多条第二连接线172设置在第一导电层108和第二导电层1010；例如，多条第二连接线172交替设置在第一导电层108和第二导电层1010。此时，相邻的第二连接线172在衬底基板101上的正投影之间的距离可设置得较小，也就是说，多条第二连接线可设置得更密集，从而可降低第二通道区的宽度或者增加第二通道区中第二连接线的数量。
在一些示例中，如图7所示，各像素140包括第一颜色子像素1601、第二颜色子像素1602和第三颜色子像素1603，各像素岛110包括呈矩阵排列的四个像素140，各像素岛140包括第一子区域144A、第二子区域144B和位于第一子区域144A和第二子区域144B之间的转接区146；第一子区域144A包括沿第二方向排列的第一像素1401和第二像素1402，第二子区域144B包括沿所述第二方向排列的第三像素1403和第四像素1404；第一像素1401中的第一颜色子像素1601的数据线1482和第二像素1402中的第一颜色子像素1601的数据线1482为第一数据线1482A，第一像素1401中的第二颜色子像素1602的数据线1482和第二像素1402中的第二颜色子像素1602的数据线1482为第二数据线1482B，第一像素1401中的第三颜色子像素1603的数据线1482和第二像素1402中的第三颜色子像素1603的数据线1482为第三数据线1482C，第三像素1403中的第一颜色子像素1601的数据线1482和第四像素1404中的第一颜色子像素1601的数据线1482为第四数据线1482D，第三像素1403中的第二颜色子像素1602的数据线1482和第四像素1404中的第二颜色子像素 1602的数据线1482为第五数据线1482E，第三像素1403中的第三颜色子像素1603的数据线1482和第四像素1404中的第三颜色子像素1603的数据线1482为第六数据线1482F。需要说明的是，为了清楚，图7中没有示出144A、144B、146、1401、1402、1403和1404；第一子区域144A、第二子区域144B、转接区146、第一像素1401、第二像素1402、第三像素1403和第四像素1404的划分可参见图1。
如图7和图8所示，多条第二连接线172包括第一数据连接线1722A、第二数据连接线1722B、第三数据连接线1722C、第四数据连接线1722D、第五数据连接线1722E和第六数据连接线1722F；第一数据连接线1722A与第一数据线1482A相连，第二数据连接线1722B与第二数据线1482B相连，第三数据连接线1722C与第三数据线1482C相连，第四数据连接线1722D与第四数据线1482D相连，第五数据连接线1722E与第五数据线1284E相连，第六数据连接线1722F与第六数据线1482D相连。由此，该显示基板可通过同一数据连接线将在第二方向上相邻两个像素岛中位于同一列的子像素的数据线相连。
在一些示例中，如图7和图8所示，第一数据连接线1722A、第二数据连接线1722B、第五数据连接线1722E位于第一导电层108；电源连接线1721、第三数据连接线1722C、第四数据连接线1722D和第六数据连接线1722F位于第二导电层1010。由此，第一数据连接线1722A、第二数据连接线1722B、第三数据连接线1722C、第四数据连接线1722D、第五数据连接线1722E、第六数据连接线1722F和电源连接线1721在衬底基板101上的正投影之间的距离可设置得较小，也就是说，这些第二连接线可设置得更密集，从而可降低第二通道区的宽度或者增加第二通道区中第二连接线的数量。
图9为本公开一实施例提供的一种显示基板的平面示意图。如图9所示，显示基板100包括第一显示区域181和第二显示区域182，第一显示区域181的像素密度大于第二显示区域182的像素密度，像素岛110位于第二显示区域182。
值得注意的是，由于第一显示区域181的像素密度大于第二显示区域182的像素密度，第一显示区域181中存在较多的像素，这些像素可通过第三连接线与对应的驱动电路相连。此时，第三连接线也可通过上述的第一通道区、第二通道区和转接区进行走线。
在一些示例中，该显示基板100还包括位于第一显示区域181和第二显示 区域182之间的过渡区域183，过渡区域183的像素密度小于第一显示区域181的像素密度，但是过渡区域183的像素密度可大于等于第二显示区域182的像素密度。过渡区域183不设置上述的开口，并且可设置用于驱动该显示基板100的像素进行发光显示的行驱动电路。在一些示例中，如图9所示，第二显示区域182位于第一显示区域181的角落。例如，该显示基板100的平面形状大致为圆角矩形，第二显示区域182位于在该显示基板100的四个角落区域，即上述的第二显示区域182可进行弯曲，从而可实现四曲面屏设计。
在一些示例中，如图9所示，第一显示区域181的平面形状包括第一矩形和位于第一矩形在所述第二方向上的两侧的两个第二矩形，所述第二显示区域的平面形状包括四个扇形，分别位于所述两个第二矩形沿所述第一方向上的两侧。
在一些示例中，第二显示区域182的显示基板100在垂直于第一显示区域181的方向上可弯曲。例如，该显示基板100包括出光侧，即显示基板100发出的光线出射的一侧，显示基板100位于第二显示区域182的部分可向与该出光侧相反的一侧进行弯曲，从而实现一种曲面形态的3D立体效果，由此可营造显示立体沉浸感。
本公开一实施例还提供一种显示装置。图10为本公开一实施例提供的一种显示装置的示意图。如图10所示，该显示装置900包括上述的显示基板100。由于该显示基板100可实现在具有开口图案的可拉伸区或者弯折区实现驱动线的布线，因此包括该显示基板100的显示装置900也可实现在具有开口图案的可拉伸区或者弯折区实现驱动线的布线，从而在具有较窄的边框宽度的同时，实现四曲面屏设计。
例如，上述的显示装置可为电视、手机、电脑、导航仪、电子画框等具有显示功能的电子产品。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化 或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (28)

  1. 一种显示基板，包括：
    多个像素岛，沿第一方向和第二方向阵列设置；
    第一开口，位于在所述第二方向上相邻的两个所述像素岛之间；
    第二开口，位于在所述第一方向上相邻的两个所述像素岛之间；以及
    第一通道区，至少部分位于所述第一开口和所述第二开口之间，
    其中，各所述像素岛包括至少一个像素，各所述像素包括沿所述第一方向延伸的多条第一驱动线，所述第一通道区设置有多条第一连接线，
    各所述像素岛还包括沿所述第二方向延伸的多条转接线，所述多条转接线与所述多条第一驱动线异层设置，且相互交叉以形成多个交叠区；所述多条转接线通过位于部分所述交叠区的过孔与所述多条第一驱动线电性相连，
    在所述第一方向上相邻的两个所述像素岛中的多条转接线分别与所述第一通道区中的所述多条第一连接线相连。
  2. 根据权利要求1所述的显示基板，其中，各所述像素岛包括两个子区域和位于两个子区域之间的转接区，所述像素岛包括的所述至少一个像素设置在所述两个子区域中，所述转接线位于所述转接区。
  3. 根据权利要求2所述的显示基板，其中，所述多条第一驱动线穿过所述两个子区域和所述转接区，所述多条第一驱动线被配置为驱动所述两个子区域中的像素以进行发光显示。
  4. 根据权利要求1所述的显示基板，其中，所述第一开口沿所述第一方向延伸，所述第二开口沿所述第二方向延伸，所述第一开口和所述第二开口在所述第一方向上交替排列，所述第一开口和所述第二开口在所述第二方向上也交替排列。
  5. 根据权利要求4所述的显示基板，其中，所述第一通道区位于所述像素岛与所述第一开口之间。
  6. 根据权利要求1-5中任一项所述的显示基板，其中，各所述像素包括多个子像素，各所述子像素包括像素驱动电路和与所述像素驱动电路电性相连的阳极。
  7. 根据权利要求6所述的显示基板，包括：
    衬底基板；
    半导体层，位于所述衬底基板上；
    栅极绝缘层，位于所述半导体层远离所述衬底基板的一侧；
    第一栅极层，位于所述栅极绝缘层远离所述半导体层的一侧；
    层间绝缘层，位于所述第一栅极层远离所述栅极绝缘层的一侧；
    第二栅极层，位于所述层间绝缘层远离所述第一栅极层的一侧；
    钝化层，位于所述第二栅极层远离所述层间绝缘层的一侧；以及
    第一导电层，位于所述钝化层远离所述第二栅极层的一侧，
    其中，所述多条第一驱动线位于所述第一栅极层和所述第二栅极层中的至少之一，所述转接线位于所述第一导电层。
  8. 根据权利要求7所述的显示基板，其中，各所述像素驱动电路包括：
    位于所述半导体层的第一半导体单元、第二半导体单元、第三半导体单元、第四半导体单元、第五半导体单元、第六半导体单元和第七半导体单元；
    位于所述第一栅极层的第一电极块；以及
    位于所述第二栅极层的第二电极块，
    其中，所述第一半导体单元包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区，所述第二半导体单元包括第二沟道区和位于所述第二沟道区两侧的第二源极区和第二漏极区，所述第三半导体单元包括第三沟道区和位于所述第三沟道区两侧的第三源极区和第三漏极区，所述第四半导体单元包括第四沟道区和位于所述第四沟道区两侧的第四源极区和第四漏极区，所述第五半导体单元包括第五沟道区和位于所述第五沟道区两侧的第五源极区和第五漏极区，所述第六半导体单元包括第六沟道区和位于所述第六沟道区两侧的第六源极区和第六漏极区，所述第七半导体单元包括第七沟道区和位于所述第七沟道区两侧的第七源极区和第七漏极区，
    所述第三源极区、所述第一漏极区和所述第五源极区连接至第一节点，所述第六漏极区和所述第三漏极区相连，所述第一源极区、所述第二漏极区和所述第四漏极区连接至第二节点，所述第五漏极区和所述第七漏极区相连，
    所述第二电极块在衬底基板上的正投影与所述第一电极块在所述衬底基板上的正投影至少部分重叠以形成存储电容。
  9. 根据权利要求8所述的显示基板，其中，所述多条第一驱动线包括：
    初始化信号线，位于所述第二栅极层；
    复位信号线，位于所述第一栅极层；
    栅线，位于所述第一栅极层；以及
    发光控制线，位于所述第一栅极层，
    其中，所述初始化信号线与所述第七源极区和第六源极区相连，所述复位信号线与所述第七沟道区和所述第六沟道区交叠，所述栅线分别与所述第三沟道区和所述第二沟道区交叠，所述第一电极块与所述第一沟道区交叠，所述发光控制线与所述第四沟道区和所述第五沟道区交叠。
  10. 根据权利要求9所述的显示基板，其中，各所述像素岛包括沿第二方向排列的至少两个像素，所述多条第一驱动线中的至少两条与同一条所述转接线相连。
  11. 根据权利要求9所述的显示基板，其中，各所述像素岛包括呈矩阵排列的四个所述像素，各所述像素岛包括第一子区域、第二子区域和位于所述第一子区域和所述第二子区域之间的转接区，所述第一子区域包括沿所述第二方向排列的第一像素和第二像素，所述第二子区域包括沿所述第二方向排列的第三像素和第四像素，
    所述第一像素的所述初始化信号线和所述第三像素的所述初始化信号线为第一初始化信号线，所述第二像素的所述初始化信号线和所述第四像素的所述初始化信号线为第二初始化信号线，
    所述多条转接线包括第一转接线，所述第一像素和所述第三像素的所述第一初始化信号线通过过孔与所述第一转接线电性相连，所述第二像素和所述第四像素的所述第二初始化信号线通过过孔与所述第一转接线相连。
  12. 根据权利要求11所述的显示基板，其中，所述第一像素的所述复位信号线和所述第三像素的所述复位信号线为第一复位信号线，所述第二像素的所述复位信号线和所述第四像素的所述复位信号线为第二复位信号线，
    所述多条转接线包括第二转接线和第三转接线，所述第一像素和所述第三像素的所述第一复位信号线通过过孔与所述第二转接线电性相连，所述第二像素和所述第四像素的所述第二复位信号线通过过孔与所述第三转接线相连。
  13. 根据权利要求12所述的显示基板，其中，所述第一像素的所述栅线和所述第三像素的所述栅线为第一栅线，所述第二像素的所述栅线和所述第四像素的所述栅线为第二栅线，
    所述多条转接线包括第四转接线，所述第一像素和所述第三像素的所述第一栅线通过过孔与所述第三转接线电性相连，所述第二像素和所述第四像素的 所述第二栅线通过过孔与所述第四转接线相连。
  14. 根据权利要求13所述的显示基板，其中，所述第一像素的所述发光控制线和所述第三像素的所述发光控制线为第一发光控制线，所述第二像素的所述发光控制线和所述第四像素的所述发光控制线为第二发光控制线，
    所述多条转接线包括第五转接线，所述第一像素和所述第三像素的所述第一发光控制线通过过孔与所述第五转接线电性相连，所述第二像素和所述第四像素的所述第二发光控制线通过过孔与所述第五转接线相连。
  15. 根据权利要求13所述的显示基板，其中，所述第一像素的所述发光控制线和所述第三像素的所述发光控制线为第一发光控制线，所述第二像素的所述发光控制线和所述第四像素的所述发光控制线为第二发光控制线，
    所述多条转接线包括第五转接线和第六转接线，所述第一像素和所述第三像素的所述第一发光控制线通过过孔与所述第五转接线电性相连，所述第二像素和所述第四像素的所述第二发光控制线通过过孔分别与所述第六转接线相连。
  16. 根据权利要求9所述的显示基板，其中，所述多条第一连接线设置在所述第一栅极层和所述第二栅极层。
  17. 根据权利要求1-16中任一项所述的显示基板，其中，所述多条转接线的数量小于所述多条第一驱动线的数量。
  18. 根据权利要求7所述的显示基板，还包括：
    第二通道区，
    其中，各所述像素岛包括沿所述第二方向延伸的多条第二驱动线，所述第二通道区设置有多条第二连接线，所述多条第二连接线分别将在所述第二方向上相邻的两个所述像素岛的所述多条第二驱动线相连。
  19. 根据权利要求18所述的显示基板，其中，多条第二驱动线包括：
    多条电源线，位于所述第一导电层，各所述电源线且与所述像素驱动电路中的所述第四源极区相连；以及
    多条数据线，位于所述第一导电层，各所述数据线与所述像素驱动电路中的所述第二源极区相连。
  20. 根据权利要求19所述的显示基板，还包括：
    绝缘层，位于所述第一导电层远离钝化层的一侧；以及
    第二导电层，位于所述绝缘层远离所述第一导电层的一侧，
    其中，所述第二导电层包括位于所述像素岛的导电网格，所述导电网格与所述像素岛中的所述多条电源线均电性相连，
    所述多条第二连接线包括电源连接线，位于所述第二导电层，且与所述导电网格相连。
  21. 根据权利要求20所述的显示基板，其中，所述多条第二连接线还包括多条数据连接线，所述多条数据线与所述多条数据连接线一一对应设置并连接。
  22. 根据权利要求20所述的显示基板，其中，所述多条第二连接线设置在所述第一导电层和所述第二导电层。
  23. 根据权利要求20所述的显示基板，其中，各所述像素包括第一颜色子像素、第二颜色子像素和第三颜色子像素，各所述像素岛包括呈矩阵排列的四个所述像素，各所述像素岛包括第一子区域、第二子区域和位于所述第一子区域和所述第二子区域之间的转接区，所述第一子区域包括沿所述第二方向排列的第一像素和第二像素，所述第二子区域包括沿所述第二方向排列的第三像素和第四像素，
    所述第一像素中的所述第一颜色子像素的数据线和所述第二像素中的第一颜色子像素的数据线为第一数据线，所述第一像素中的所述第二颜色子像素的数据线和所述第二像素中的第二颜色子像素的数据线为第二数据线，所述第一像素中的所述第三颜色子像素的数据线和所述第二像素中的第三颜色子像素的数据线为第三数据线，
    所述第三像素中的所述第一颜色子像素的数据线和所述第四像素中的第一颜色子像素的数据线为第四数据线，所述第三像素中的所述第二颜色子像素的数据线和所述第四像素中的第二颜色子像素的数据线为第五数据线，所述第三像素中的所述第三颜色子像素的数据线和所述第四像素中的第三颜色子像素的数据线为第六数据线，
    所述多条第二连接线包括第一数据连接线、第二数据连接线、第三数据连接线、第四数据连接线、第五数据连接线和第六数据连接线，所述第一数据连接线与所述第一数据线相连，所述第二数据连接线与所述第二数据线相连，所述第三数据连接线与所述第三数据线相连，所述第四数据连接线与所述第四数据线相连，所述第五数据连接线与所述第五数据线相连，所述第六数据连接线与所述第六数据线相连。
  24. 根据权利要求23所述的显示基板，其中，所述第一数据连接线、所述第二数据连接线、所述第五数据连接线位于所述第一导电层，所述电源连接线、所述第三数据连接线、所述第四数据连接线和所述第六数据连接线位于所述第二导电层。
  25. 根据权利要求1-24中任一项所述的显示基板，其中，所述显示基板包括第一显示区域和第二显示区域，所述第一显示区域的像素密度大于所述第二显示区域的像素密度，所述像素岛位于所述第二显示区域。
  26. 根据权利要求25所述的显示基板，其中，所述第二显示区域位于所述第一显示区域的角落。
  27. 根据权利要求25所述的显示基板，其中，所述显示基板的所述第二显示区域在垂直于所述第一显示区域的方向上可弯曲。
  28. 一种显示装置，包括根据权利要求1-27中任一项所述的显示基板。
PCT/CN2021/074978 2021-02-03 2021-02-03 显示基板和显示装置 Ceased WO2022165657A1 (zh)

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