WO2022165807A1 - 显示基板、显示面板和显示装置 - Google Patents

显示基板、显示面板和显示装置 Download PDF

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Publication number
WO2022165807A1
WO2022165807A1 PCT/CN2021/075844 CN2021075844W WO2022165807A1 WO 2022165807 A1 WO2022165807 A1 WO 2022165807A1 CN 2021075844 W CN2021075844 W CN 2021075844W WO 2022165807 A1 WO2022165807 A1 WO 2022165807A1
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WIPO (PCT)
Prior art keywords
sub
pixel
transistor
base substrate
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/075844
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English (en)
French (fr)
Inventor
刘珂
石领
陈义鹏
刘烺
张振华
田学伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/629,360 priority Critical patent/US12238999B2/en
Priority to PCT/CN2021/075844 priority patent/WO2022165807A1/zh
Priority to EP25185664.7A priority patent/EP4600943A3/en
Priority to CN202180000206.2A priority patent/CN115191014B/zh
Priority to EP21923818.5A priority patent/EP4131236B1/en
Publication of WO2022165807A1 publication Critical patent/WO2022165807A1/zh
Anticipated expiration legal-status Critical
Priority to US19/024,409 priority patent/US20250160165A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • under-screen camera With the increase of users' demands for diversified use of display devices and the emergence of design requirements for a high screen-to-body ratio of display devices, a solution of "under-screen camera” has emerged.
  • imaging modules such as cameras are embedded in the display area to reduce the size of the frame area of the display device, thereby increasing the screen ratio.
  • the "under-screen camera” solution on the basis of increasing the screen ratio of the display device, how to ensure the light transmittance and display effect at the position corresponding to the imaging module in the display substrate has become the concern of developers. important topic.
  • a display substrate includes a first display area and a second display area, the light transmittance of the first display area is greater than the light transmittance of the second display area, the display The substrate includes: a base substrate; a plurality of sub-pixels disposed on the base substrate and located in the first display area, the sub-pixels include a first pixel driving circuit and a first light-emitting device, the first pixel driving a circuit is electrically connected to the first light-emitting device for driving the first light-emitting device to emit light; and a plurality of sub-pixels disposed on the base substrate and located in the second display area, located in the second display area
  • the sub-pixels in the area include a second pixel driving circuit and a second light-emitting device, the second pixel driving circuit is electrically connected to the second light-emitting device, and is used for driving the second light-emitting device to emit light, wherein the second pixel driving circuit is located in the second light-emit
  • the plurality of sub-pixels in the first display area includes a plurality of sub-pixel groups, each sub-pixel group includes a first sub-pixel and a second sub-pixel, and the first pixel driving circuit includes a first sub-pixel driving circuit and a second sub-pixel A driving circuit, the first sub-pixel driving circuit is used to drive the first light-emitting device of the first sub-pixel to emit light, the second sub-pixel driving circuit is used to drive the first light-emitting device of the second sub-pixel to emit light, and the first light-emitting device of the second sub-pixel is used to emit light.
  • a sub-pixel driving circuit includes at least a first reset transistor, the second sub-pixel driving circuit includes at least a second reset transistor, and the first reset transistor of the first sub-pixel driving circuit and the second sub-pixel driving circuit The second reset transistor is at least partially shared.
  • the orthographic projections of each of the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit on the base substrate are all falling
  • the occupied area of the first sub-pixel driving circuit is in the orthographic projection on the base substrate.
  • the first reset transistor includes a common transistor and a first sub-transistor
  • the second reset transistor includes the common transistor and a second sub-transistor
  • the common transistor the first sub-transistor
  • Each of the transistor and the second sub-transistor includes a gate, a source and a drain, and the gate of each of the common transistor, the first sub-transistor and the second sub-transistor is connected to A reset control signal is input, one of the source or drain of the shared transistor is connected to an initialization voltage signal, and the other of the source or drain of the shared transistor is connected to the first sub-transistor and the first sub-transistor, respectively.
  • the two sub-transistors are electrically connected.
  • the display substrate further includes a semiconductor layer disposed on the base substrate and a first conductive layer on a side of the semiconductor layer away from the base substrate, the display substrate It also includes a reset signal line disposed on the base substrate, the reset signal line is used to transmit a reset control signal, and the reset signal line is located in the first conductive layer; and the reset signal line includes a reset signal line located on the first conductive layer.
  • the semiconductor layer includes a common channel portion, a first channel portion and a second channel portion in the first display region, the semiconductor layer includes a common channel portion, a first channel portion and a second channel portion in the first display region, the The orthographic projections of the first portion, the second portion and the third portion on the base substrate are in the same location as the common channel portion, the first channel portion and the second channel portion, respectively.
  • the orthographic projections on the base substrate overlap, the gate of the common transistor includes the first portion, the gate of the first sub-transistor includes the second portion, and the gate of the second sub-transistor includes the the third part.
  • the common transistor includes a common source portion and a common drain portion in the semiconductor layer
  • the first sub-transistor includes a first sub-source portion in the semiconductor layer and a first sub-drain portion
  • the second sub-transistor includes a second sub-source portion and a second sub-drain portion in the semiconductor layer
  • the common source portion and the common drain portion are respectively located on both sides of the common channel portion
  • the first sub-source portion and the first sub-drain portion are respectively located on both sides of the first channel portion
  • the second sub-source portion and the second sub-drain portion are respectively located on both sides of the second channel portion.
  • the display substrate further includes an initialization voltage line disposed on the base substrate and a first connection portion disposed on the base substrate; the common source portion and the One of the common drain parts is electrically connected to the initialization voltage line through a first via hole, and the other of the common source part and the common drain part is connected to the first sub-source part and the first sub-source part and the one of the first sub-drain portions extends continuously; and the other of the first sub-source portion and the first sub-drain portion is electrically connected to one end of the first connection portion through a second via hole .
  • the first sub-pixel driving circuit further includes a first driving transistor, the first driving transistor includes a gate, and the other end of the first connection part is connected to the The gate of the first drive transistor is electrically connected.
  • the display substrate further includes a first transparent conductive connection portion disposed on the base substrate; the other one of the common source portion and the common drain portion is further connected to the common source portion and the common drain portion.
  • one of the second sub-source portion and the second sub-drain portion extends continuously; and the other of the second sub-source portion and the second sub-drain portion is connected to the second sub-source portion and the second sub-drain portion through a third via hole
  • One end of the first transparent conductive connection portion is electrically connected.
  • the second sub-pixel driving circuit further includes a second driving transistor, the second driving transistor includes a gate, and the other end of the first transparent conductive connection portion is connected to a fourth via hole.
  • the gate of the second driving transistor is electrically connected.
  • the initialization voltage line is located in a second conductive layer
  • the first connection portion is located in a third conductive layer
  • the second conductive layer is located in the first conductive layer away from the substrate
  • the third conductive layer is located on the side of the second conductive layer away from the base substrate.
  • the first transparent conductive connection portion is located in a first transparent conductive layer, and the first transparent conductive layer is located on a side of the third conductive layer away from the base substrate.
  • the first sub-pixel driving circuit further includes a first initialization transistor including an active layer in the semiconductor layer; the second sub-pixel driving circuit further includes including a second initialization transistor, the second initialization transistor including an active layer in the semiconductor layer; and the orthographic projection of the first transparent conductive connection on the base substrate and the first initialization transistor
  • the orthographic projection of the active layer on the base substrate partially overlaps, and the orthographic projection of the first transparent conductive connection part on the base substrate and the active layer of the second initialization transistor are on the base substrate.
  • the orthographic projections on the base substrate partially overlap.
  • the display substrate further includes a first scan signal line and a second scan signal line disposed on the base substrate, the first scan signal line is used for supplying scan signals to the a first sub-pixel driving circuit, the second scanning signal line is used for supplying scanning signals to the second sub-pixel driving circuit; and the orthographic projection of the first scanning signal line on the base substrate is the same as the The orthographic projection of the active layer of the first initialization transistor on the base substrate partially overlaps, and the orthographic projection of the second scanning signal line on the base substrate is in the same position as the active layer of the second initialization transistor. The orthographic projections on the base substrate overlap.
  • the first transparent conductive connection part includes at least a first part, a second part and a third part, the third part of the first transparent conductive connection part extends along a first direction, the first part The second portion of a transparent conductive connection portion extends in a second direction, and the first portion of the first transparent conductive connection portion extends in an oblique direction relative to both the first direction and the second direction.
  • the orthographic projection of the first portion of the first transparent conductive connection on the base substrate and the orthographic projection of the active layer of the first initialization transistor on the base substrate Partially overlapping; and/or, the orthographic projection of the third portion of the first transparent conductive connection portion on the base substrate and the orthographic projection of the active layer of the second initialization transistor on the base substrate partially overlapping; and/or, the second portion of the first transparent conductive connection portion is located in the light-transmitting area between the first sub-pixel and the second sub-pixel.
  • the active layer of the first initialization transistor is spaced apart from other parts of the first sub-pixel driving circuit located in the semiconductor layer; and/or, the second initialization transistor The active layer is spaced apart from other parts of the second sub-pixel driving circuit located in the semiconductor layer.
  • the display substrate further includes a second connection part disposed on the base substrate, and a first end of the second connection part is electrically connected to the initialization voltage line through a fifth via hole connected, the second end of the second connection part is electrically connected to the first end of the active layer of the first initialization transistor through a sixth via hole.
  • the display substrate further includes a second transparent conductive connection part disposed on the base substrate, and a first end of the second transparent conductive connection part is connected to the second transparent conductive connection part through a seventh via hole
  • the second end of the second connection portion is electrically connected, and the second end of the second transparent conductive connection portion is electrically connected to the first end of the active layer of the second initialization transistor through an eighth via hole.
  • the second connection portion is located in the third conductive layer; and/or the second transparent conductive connection portion is located in the first transparent conductive layer.
  • the orthographic projection of the sixth via on the base substrate at least partially overlaps the orthographic projection of the seventh via on the base substrate.
  • the display substrate further includes a third transparent conductive connection part disposed on the base substrate, and one end of the third transparent conductive connection part is connected to the first through a ninth via hole
  • the scan signal line is electrically connected
  • the other end of the third transparent conductive connection portion is electrically connected to the second scan signal line through a tenth via hole.
  • the display substrate further includes a first light-emitting control line and a second light-emitting control line disposed on the base substrate, and the first light-emitting control line is used for supplying a light-emitting control signal to the the first sub-pixel driving circuit, the second light-emitting control line is used for supplying light-emitting control signals to the second sub-pixel driving circuit; and the display substrate further comprises a fourth transparent substrate disposed on the base substrate A conductive connection part, one end of the fourth transparent conductive connection part is electrically connected to the first light-emitting control line through an eleventh via hole, and the other end of the fourth transparent conductive connection part is electrically connected to the first light-emitting control line through a twelfth via hole The second light-emitting control line is electrically connected.
  • the first sub-pixel and the second sub-pixel share the reset signal line and the initialization voltage line.
  • the plurality of sub-pixel groups at least include a first sub-pixel group and a second sub-pixel group that are located in the same row and adjacent to each other; and the display substrate further includes a first sub-pixel group disposed on the base substrate.
  • the first conductive lead, one end of the first conductive lead is electrically connected to the reset signal line in the first sub-pixel group through the thirteenth via hole, and the other end of the first conductive lead is electrically connected to the reset signal line in the first sub-pixel group through the fourteenth via hole.
  • the reset signal lines in the second sub-pixel group are electrically connected.
  • the display substrate further includes a second conductive lead disposed on the base substrate, one end of the second conductive lead is connected to the first sub-pixel group through a fifteenth via hole
  • the initialization voltage line is electrically connected
  • the other end of the second conductive lead is electrically connected to the initialization voltage line in the second sub-pixel group through the sixteenth via hole.
  • the third transparent conductive connection part and/or the fourth transparent conductive connection part are located in the first transparent conductive layer; and, the first conductive lead and/or the The second conductive lead is located in the second transparent conductive layer, wherein the second transparent conductive layer is located on the side of the first transparent conductive layer away from the base substrate.
  • the display substrate further includes: data signal lines for transmitting data signals; and driving voltage lines for transmitting driving voltages; and both the data signal lines and the driving voltage lines are located at in the first transparent conductive layer.
  • the driving voltage line is disconnected at the first subpixel driving circuit and the second subpixel driving circuit, such that the driving voltage line includes a first driving voltage subline and a second driving voltage sub-line, the first driving voltage sub-line and the second driving voltage sub-line are spaced apart in the extending direction of the driving voltage line; and the display substrate further includes a third connecting part, the first driving voltage sub-line One end of the three connecting parts is electrically connected to the first driving voltage sub-line through the seventeenth via hole, and the other end is electrically connected to the second driving voltage sub-line through the eighteenth via hole.
  • the display substrate includes a fourth conductive layer disposed on the base substrate, and the fourth conductive layer is located between the first transparent conductive layer and the second transparent conductive layer and the third connection portion is located in the fourth conductive layer.
  • an orthographic projection of at least one of the first conductive lead and the second conductive lead on the base substrate is the same as that of at least one of the data line and the driving voltage line An orthographic intersection on the base substrate.
  • the first light-emitting device includes at least a first electrode and a light-emitting material layer, and the light-emitting material layer is disposed on a side of the first electrode away from the base substrate; and the first The area of the orthographic projection of the first electrode of a sub-pixel on the base substrate is larger than the area of the orthographic projection of the first electrode of the second sub-pixel on the base substrate.
  • the orthographic projection of the first electrode of the first sub-pixel on the base substrate covers the orthographic projection of the occupied area of the first sub-pixel driving circuit on the base substrate and/or, the orthographic projection of the first electrode of the second sub-pixel on the base substrate covers the orthographic projection of the occupied area of the second sub-pixel driving circuit on the base substrate.
  • the first subpixel is a red subpixel or a blue subpixel
  • the second subpixel is a green subpixel
  • a display panel including the display substrate as described above.
  • a display device comprising the above-mentioned display substrate or the above-mentioned display panel.
  • the display device further includes at least one image sensor; and wherein an orthographic projection of the at least one image sensor on the substrate substrate falls into the first display area on the substrate within the orthographic projection on the base substrate.
  • FIG. 1 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure, in which a planar structure of a display substrate included in the display device is schematically shown.
  • FIG. 2 is a schematic cross-sectional view of a display device according to some exemplary embodiments of the present disclosure, taken along line AA' in FIG. 1 .
  • FIG. 3 is a partial enlarged view of a display substrate at part I in FIG. 1 according to some exemplary embodiments of the present disclosure.
  • FIG. 4 is a partial enlarged view of a display substrate at part II in FIG. 3 according to some exemplary embodiments of the present disclosure.
  • FIG. 5 is a partial enlarged view of a display substrate at part III in FIG. 4 according to some exemplary embodiments of the present disclosure.
  • 6A is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure.
  • 6B is an equivalent circuit diagram of a pixel driving circuit of one sub-pixel of the display substrate located in the first display area according to some exemplary embodiments of the present disclosure.
  • 6C is an equivalent circuit diagram of a pixel driving circuit of one sub-pixel of the display substrate located in the first display area according to some exemplary embodiments of the present disclosure.
  • FIG. 7 is a plan view illustrating an exemplary embodiment of a sub-pixel in a second display area of a display substrate according to some exemplary embodiments of the present disclosure, in which one repeating unit in the second display area is schematically illustrated floor plan.
  • FIG. 8 is a plan view illustrating a semiconductor layer of an exemplary embodiment of a subpixel included in one repeating unit of FIG. 7 .
  • FIG. 9 is a plan view illustrating a combination of a semiconductor layer and a first conductive layer of an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 .
  • FIG. 10 is a plan view illustrating a combination of a semiconductor layer, a first conductive layer, and a second conductive layer of an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 .
  • FIG. 11 is a plan view illustrating a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer of an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 .
  • FIGS. 12A and 12B respectively illustrate a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer of an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 . floor plan.
  • FIG. 13 is a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer showing an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 floor plan.
  • 14A is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line BB' in FIG. 12B according to some exemplary embodiments of the present disclosure.
  • 14B is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line CC' in FIG. 13 according to some exemplary embodiments of the present disclosure.
  • FIG. 15 is a plan view illustrating an exemplary embodiment of a sub-pixel in a first display area of a display substrate according to some exemplary embodiments of the present disclosure, in which a repeating unit of one repeating unit in the first display area is schematically illustrated floor plan.
  • FIG. 16A is a plan view illustrating a semiconductor layer of an exemplary embodiment of a sub-pixel included in one repeating unit in FIG. 15 .
  • FIG. 16B is a partial enlarged view showing the semiconductor layer shown in FIG. 16A at the reset transistor.
  • 17A is a plan view illustrating a first conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.
  • 17B is a plan view illustrating a combination of a semiconductor layer and a first conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.
  • 18A is a plan view illustrating a second conductive layer of a sub-pixel group in a first display area of a display substrate according to some exemplary embodiments of the present disclosure.
  • 18B is a plan view illustrating a combination of a semiconductor layer, a first conductive layer, and a second conductive layer of a subpixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.
  • 19A is a plan view illustrating a third conductive layer of a sub-pixel group in a first display area of a display substrate according to some exemplary embodiments of the present disclosure.
  • 19B is a plan view illustrating a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer of a subpixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.
  • 20A is a plan view illustrating a first transparent conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.
  • 20B is a plan view illustrating a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a first transparent conductive layer of a subpixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure .
  • 21A is a plan view illustrating a fourth conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.
  • 21B is a diagram illustrating a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, and a fourth conductive layer of a subpixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure
  • Floor plan of the composition of layers
  • 22A is a plan view illustrating a second transparent conductive layer of a sub-pixel group in a first display area of a display substrate according to some exemplary embodiments of the present disclosure.
  • 22B is a diagram illustrating a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, a fourth conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure Plan view of the combination of layer and second transparent conductive layer.
  • 23A is a plan view illustrating a fifth conductive layer of a sub-pixel group in a first display area of a display substrate according to some exemplary embodiments of the present disclosure.
  • 23B is a diagram illustrating a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, a fourth conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure Plan view of the combination of layer, second transparent conductive layer, and fifth conductive layer.
  • 24A is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line DD' in FIG. 21B according to some exemplary embodiments of the present disclosure.
  • 24B is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line EE' in FIG. 23A according to some exemplary embodiments of the present disclosure.
  • 25A and 25B are plan views illustrating exemplary embodiments of a plurality of sub-pixel groups in a first display area of a display substrate according to some exemplary embodiments of the present disclosure.
  • FIGS. 26A , 26B and 26C respectively illustrate a blocking layer, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a Plan view of the combination of the first transparent conductive layer, the fourth conductive layer, the second transparent conductive layer, and the fifth conductive layer.
  • FIG. 27 is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line FF' in FIG. 26A according to some exemplary embodiments of the present disclosure.
  • the X axis, the Y axis and the Z axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense.
  • the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as X only, Y only, Z only, or Any combination of two or more of X, Y and Z such as XYZ, XYY, YZ and ZZ.
  • the term "and/or" includes any and all combinations of one or more of the associated listed items.
  • first the terms “first”, “second”, etc. may be used herein to describe various components, components, elements, regions, layers and/or sections, these components, components, elements, regions, layers and/or parts shall not be limited by these terms. Rather, these terms are used to distinguish one element, member, element, region, layer and/or section from another. Thus, for example, a first part, first member, first element, first region, first layer and/or first section discussed below could be termed a second part, second member, second element, second region , the second layer and/or the second portion without departing from the teachings of the present disclosure.
  • spatially relational terms eg, "upper,” “lower,” “left,” “right,” etc. may be used herein to describe one element or feature relative to another element or feature as shown in the figures relation. It should be understood that the spatially relational terms are intended to encompass other different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “above” the other elements or features.
  • the expression "the same layer” refers to the formation of a film layer for forming a specific pattern using the same film forming process, and then using the same mask to pattern the film layer through a patterning process.
  • layer structure Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or sections located on the "same layer” are composed of the same material and formed by the same patterning process, typically, multiple elements, components, structures and/or sections located on the "same layer” or parts with approximately the same thickness.
  • the expression “repeating unit” refers to a combination of a plurality of sub-pixels, for example, a combination of a plurality of sub-pixels used to display one pixel point, and a plurality of "repeating units” are repeatedly arranged in an array on the base substrate.
  • a repeating unit may include at least one pixel, for example, may include 2, 3, 4, or more sub-pixels.
  • the repeating unit located in the first display area is referred to as the first repeating unit, and the repeating unit located in the second display area is called the second repeating unit.
  • pixel density refers to the number of repeating units or sub-pixels per unit area.
  • pixel density can be expressed using PPI, which means the number of pixels per unit area.
  • distributed density refers to the number of features (eg repeating units, sub-pixels, spacers, etc.) per unit area.
  • FIG. 1 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure, in which a planar structure of a display substrate included in the display device is schematically shown.
  • FIG. 2 is a schematic cross-sectional view of a display device according to some exemplary embodiments of the present disclosure, taken along line AA' in FIG. 1 .
  • the display device includes a display substrate.
  • the display substrate may be an electroluminescent display substrate, such as an OLED display substrate.
  • a display device includes a display substrate 100 .
  • the display substrate 100 includes a display area, and the display area may include a first display area AA1 and a second display area AA2.
  • the second display area AA2 at least partially surrounds (eg, completely surrounds) the first display area AA1.
  • the display substrate 100 may include a base substrate 1 .
  • the sensor 2 can be disposed on the back side of the base substrate 1 located in the first display area AA1 (shown as the lower side in FIG. 2 , for example, the side opposite to the light-emitting direction during display), and the first display area AA1 can satisfy the sensor 2 for Imaging requirements for light transmittance.
  • the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2.
  • the sensor 2 is, for example, an image sensor, an infrared sensor, or the like.
  • the sensor 2 is configured to receive light from the display side of the display substrate 100 (the upper side in FIG. 2 , for example, in the direction of the displayed light, or in the direction of the human eye during display), so as to perform image capturing, distance perception, For operations such as light intensity sensing, these lights, for example, pass through the first display area AA1 and then irradiate onto the sensor, so as to be sensed by the sensor.
  • the second display area AA2 completely surrounds the first display area AA1, but the embodiments of the present disclosure are not limited thereto.
  • the first display area AA1 may be located at the upper edge of the display substrate.
  • the first display area AA1 is surrounded by the second display area AA2 on three sides, and the upper side of the first display area AA1 is connected to the upper side of the display substrate. side flush.
  • the first display area AA1 may be located at the position of the upper edge of the display substrate and arranged along the entire width of the display substrate.
  • the shape of the first display area AA1 may be a circle, an ellipse, a polygon or a rectangle
  • the shape of the second display area AA2 may be a circle, a circle, an ellipse or a rectangle, but the embodiments of the present disclosure are not limited to this.
  • the shapes of the first display area AA1 and the second display area AA2 may be rectangles, rounded rectangles, or other suitable shapes.
  • the OLED display technology can be used. Because OLED display substrates have the advantages of wide viewing angle, high contrast ratio, fast response, low power consumption, foldability, flexibility, etc., they are more and more widely used in display products. With the development and in-depth application of OLED display technology, the demand for high screen-to-body ratio displays is getting stronger and stronger.
  • the solution of the camera under the screen is adopted. In this way, the notch area can be eliminated, digging holes in the display screen can be avoided, the screen ratio can be increased, and a better visual experience can be obtained.
  • the display substrate may include a base substrate 1 and various film layers disposed on the base substrate 1 .
  • the display substrate may further include a driving circuit layer, a light emitting device layer and an encapsulation layer disposed on the base substrate 1 .
  • the driving circuit layer 3 , the light emitting device layer 4 and the encapsulation layer 5 are schematically shown in FIG. 2 .
  • the driving circuit layer 3 includes a driving circuit structure
  • the light emitting device layer 4 includes a light emitting device such as an OLED.
  • the driving circuit structure controls the light-emitting device of each sub-pixel to emit light, so as to realize the display function.
  • the drive circuit structure includes thin film transistors, storage capacitors, and various signal lines.
  • the various signal lines include gate lines, data lines, ELVDD power lines, and ELVSS power lines, etc., so as to provide various signals such as control signals, data signals, and power supply voltages for the pixel driving circuit in each sub-pixel.
  • the first display area AA1 may correspond to an under-screen camera, that is, the first display area AA1 may be an under-screen camera area.
  • the display substrate 100 includes two first display areas AA1 as an example for description.
  • Each of the first display areas AA1 may be in the shape of a circle, a substantially circle, an ellipse, a polygon, or the like.
  • the two first display areas AA1 are arranged at intervals, and a spaced area SR exists between the two first display areas AA1.
  • two sensors 2 may be set to correspond to two sub-display areas respectively, so as to form a display device having a dual-camera structure.
  • embodiments of the present disclosure are not limited thereto, and in other embodiments, fewer (eg, one) or more sub-display areas and sensors 2 may be provided.
  • the shape of the sub-display area may also be determined according to the shape of the hardware structure to be installed.
  • the orthographic projection of each sub-display area on the base substrate may have one or more of the following shapes: circular , ovals, rectangles, rounded rectangles, squares, diamonds, trapezoids, polygons, and various combinations of these shapes.
  • a display area having a light transmittance higher than that of a normal display area is provided in the display substrate, and a hardware structure such as a camera is installed in the display area.
  • a hardware structure such as a camera
  • the A way to reduce the pixel density in the first display area that is, the PPI in the first display area is smaller than the PPI in the second display area, for example, the PPI in the first display area is usually set to the PPI in the second display area less than one-half of .
  • this way of reducing the PPI will reduce the display quality in the first display area, and compared with the normal display area, the picture displayed in the first display area will appear grainy visually.
  • the pixel driving circuits of the pixels in the first display area are usually arranged outside the under-screen imaging area, for example, the pixel driving circuits are arranged in the above-mentioned space area SR, in this case , during display, there will be black borders in the display area between the two sensors 2 , which will have a bad influence on the overall display quality.
  • the pixel driving circuit when the pixel driving circuit is arranged outside the under-screen imaging area, the pixel driving circuit arranged outside must be electrically connected to the light-emitting elements (such as OLED) of each pixel arranged in the under-screen imaging area through conductive wires. Due to the limitation of the spacing between them and the line width and line spacing of the conductive leads, the realization of high PPI in the under-screen camera area will be limited, that is, the under-screen camera area with high PPI cannot be realized.
  • Embodiments of the present disclosure provide at least a display substrate, a display panel, and a display device.
  • the display substrate includes a first display area and a second display area, the light transmittance of the first display area is greater than the light transmittance of the second display area, and the display substrate includes: a base substrate; a plurality of sub-pixels located in the base substrate and in the first display area, the sub-pixels include a first pixel driving circuit and a first light-emitting device, and the first pixel driving circuit is electrically connected to the first light-emitting device , for driving the first light-emitting device to emit light; and a plurality of sub-pixels disposed on the base substrate and located in the second display area, the sub-pixels located in the second display area include a second pixel driver a circuit and a second light emitting device, the second pixel driving circuit is electrically connected to the second light emitting device for driving the second light emitting device to emit light, wherein the plurality of sub-pixels
  • multiple sub-pixels can share at least a part of the reset transistor, which is beneficial to reduce the area of the occupied area of the pixel driving circuit corresponding to a part of the sub-pixels, thereby enabling under-screen imaging
  • the PPI of the area is relatively high, and the transmittance of the camera area under the screen is guaranteed to meet the requirements.
  • FIG. 3 is a partial enlarged view of a display substrate at part I in FIG. 1 according to some exemplary embodiments of the present disclosure.
  • FIG. 4 is a partial enlarged view of a display substrate at part II in FIG. 3 according to some exemplary embodiments of the present disclosure.
  • FIG. 5 is a partial enlarged view of a display substrate at part III in FIG. 4 according to some exemplary embodiments of the present disclosure.
  • the display substrate may include a first display area AA1 and a second display area AA2, the light transmittance of the first display area AA1 is higher than the light transmittance of the second display area AA2, the first display area AA1
  • the area AA1 may correspond to the sensor 2 , that is, the orthographic projection of the sensor 2 on the base substrate 1 falls within the orthographic projection of the first display area AA1 on the base substrate 1 .
  • FIG. 6A is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure.
  • 7 is a plan view illustrating an exemplary embodiment of sub-pixels in a second display area AA2 of a display substrate according to some exemplary embodiments of the present disclosure, in which one repetition in the second display area AA2 is schematically shown Floor plan of the unit.
  • FIG. 8 is a plan view illustrating a semiconductor layer of an exemplary embodiment of a subpixel included in one repeating unit of FIG. 7 .
  • FIG. 9 is a plan view illustrating a combination of a semiconductor layer and a first conductive layer of an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 .
  • FIG. 10 is a plan view illustrating a combination of a semiconductor layer, a first conductive layer, and a second conductive layer of an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 .
  • FIG. 11 is a plan view illustrating a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer of an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 .
  • FIGS. 12A and 12B respectively illustrate a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer of an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 . floor plan.
  • FIG. 12A and 12B respectively illustrate a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer of an exemplary embodiment of a subpixel included in one repeating
  • FIG. 13 is a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer showing an exemplary embodiment of a subpixel included in one repeating unit in FIG. 7 floor plan.
  • 14A is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line BB' in FIG. 12B according to some exemplary embodiments of the present disclosure.
  • 14B is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line CC' in FIG. 13 according to some exemplary embodiments of the present disclosure.
  • a plurality of pixels may be provided in the first display area AA1 .
  • a plurality of pixels may be arranged on the base substrate 1 in an array along the first direction X and the second direction Y.
  • each of the plurality of pixels may include sub-pixel 11 , sub-pixel 12 and sub-pixel 13 .
  • the sub-pixel 11, the sub-pixel 12 and the sub-pixel 13 may be described as a red sub-pixel, a blue sub-pixel and a green sub-pixel, respectively, but the embodiments of the present disclosure are not limited thereto.
  • each of the plurality of pixels 20 may include a sub-pixel 21 , a sub-pixel 22 and a sub-pixel 23 .
  • the sub-pixels 21 , 22 and 23 may be described as red sub-pixels, blue sub-pixels and green sub-pixels, respectively, but embodiments of the present disclosure are not limited thereto.
  • the second display area AA2 may be provided with a plurality of repeating units arranged in an array.
  • the repeating unit located in the second display area AA2 is referred to as the second repeating unit Unit P2.
  • one second repeating unit P2 may include at least one pixel, for example, in the embodiment shown in FIG. 7 , one second repeating unit P2 includes 2 pixels.
  • one second repeating unit P2 may include a plurality of sub-pixels, such as the above-mentioned sub-pixels 21 , 22 and 23 .
  • the first display area AA1 is provided with a plurality of repeating units arranged in an array.
  • the repeating unit located in the first display area AA1 is referred to as the first repeating unit P1.
  • one first repeating unit P1 may include at least one pixel, for example, in some embodiments, one first repeating unit P1 includes 2 pixels.
  • one first repeating unit P1 may include a plurality of sub-pixels, such as the sub-pixels 11 , the sub-pixels 12 and the sub-pixels 13 described above.
  • each repeating unit may include at least two sub-units of different colors Pixels, such as a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, the first color, the second color and the third color are different colors from each other.
  • the arrangement of sub-pixels in each repeating unit may refer to conventional pixel arrangements, such as GGRB, RGBG, RGB, etc., which are not limited in the embodiments of the present disclosure.
  • the sub-pixels located in the first display area AA1 and the second display area AA2 may include pixel driving circuits and light emitting devices.
  • the light-emitting device may be an OLED light-emitting device, including a stacked anode, an organic light-emitting layer, and a cathode.
  • the pixel driving circuit may include a plurality of thin film transistors and at least one storage capacitor.
  • first direction X and the second direction Y are perpendicular to each other, the embodiments of the present disclosure are not limited thereto.
  • the structure of the pixel driving circuit of the sub-pixels located in the first display area AA1 and the second display area AA2 will be described in detail by taking the 7T1C pixel driving circuit as an example, but the embodiments of the present disclosure are not limited to For the 7T1C pixel driving circuit, other known pixel driving circuit structures can be applied to the embodiments of the present disclosure without conflict.
  • the display substrate 100 further includes a pixel defining layer PDL located on the side of the first electrode (eg, the anode) away from the pixel driving circuit, and the pixel defining layer PDL includes multiple Each sub-pixel corresponds to at least one pixel-defining layer opening (eg, one), and the actual light-emitting area or display area of the sub-pixel is approximately equal to the pixel-defining layer opening corresponding to the sub-pixel.
  • a pixel defining layer PDL located on the side of the first electrode (eg, the anode) away from the pixel driving circuit
  • the pixel defining layer PDL includes multiple
  • Each sub-pixel corresponds to at least one pixel-defining layer opening (eg, one), and the actual light-emitting area or display area of the sub-pixel is approximately equal to the pixel-defining layer opening corresponding to the sub-pixel.
  • the area of the pixel-defining layer opening or the actual light-emitting area corresponding to each sub-pixel is smaller than the area of the first electrode (eg, the anode), and the projection on the base substrate completely falls within the projection of the first electrode on the base substrate within.
  • the first electrode eg, the anode
  • the projection on the base substrate completely falls within the projection of the first electrode on the base substrate within.
  • each sub-pixel located in the second display area AA2 may include a light-emitting device (eg, OLED), and for the convenience of description, the light-emitting device located in the second display area AA2 is referred to as the first Two light-emitting devices 42 .
  • the second light emitting device 42 may include an anode 42A, a light emitting material layer 42B, and a cathode 42C, which are provided in layers. It should be noted that, for the sake of clarity, the anode of the second light emitting device 42 is used to schematically illustrate the second light emitting device 42 in the plan view, thereby schematically representing the sub-pixels located in the second display area AA2.
  • the anode 42A of the second light emitting device 42 may include an anode body 421 and an anode connection part 422 .
  • the orthographic projection of the anode body 421 on the base substrate 1 may have a regular shape, such as a circle, an ellipse, a rectangle, a hexagon, an octagon, a rounded rectangle, and the like.
  • a pixel driving circuit for driving the second light emitting device 42 (to be described later) is also provided in the second display area AA2 , and the anode connecting portion 422 is electrically connected to the pixel driving circuit of the second light emitting device 42 .
  • the second repeating unit P2 may include a plurality of sub-pixels arranged in 4 rows and 4 columns.
  • the sub-pixels 21 and the sub-pixels 22 are arranged in the first and third columns, respectively.
  • two sub-pixels 23 are arranged in the second and fourth columns, respectively.
  • the sub-pixels 22 and the sub-pixels 21 are arranged in the first and third columns, respectively.
  • two sub-pixels 23 are arranged in the second and fourth columns, respectively.
  • the arrangement of the sub-pixels shown in FIG. 7 is only an exemplary arrangement of some embodiments of the present disclosure, rather than a limitation of the embodiments of the present disclosure. In other embodiments, the sub-pixels may be Use other arrangements.
  • the area of the orthographic projection of the anode body portion 421 of one sub-pixel 21 on the base substrate 1 is smaller than that of the anode body portion 421 of one sub-pixel 22 on the base substrate 1
  • the area of the orthographic projection of the anode main body 421 of one subpixel 23 on the base substrate 1 is smaller than the orthographic projection area of the anode main body 421 of one subpixel 21 on the base substrate 1 .
  • the actual light-emitting area of a green sub-pixel is the smallest
  • the actual light-emitting area of a blue sub-pixel is the largest
  • the actual light-emitting area of a red sub-pixel is between the green sub-pixel and the blue sub-pixel.
  • the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst.
  • the pixel driving circuit is used for driving organic light emitting diodes (ie OLEDs).
  • the plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
  • Each transistor includes a gate, a source and a drain.
  • the display substrate may further include a plurality of signal lines, for example, the plurality of signal lines include: a scan signal line 61 for transmitting the scan signal Sn, for transmitting the reset control signal RESET (for example, the reset control signal RESET may the reset signal line 62 for the scan signal of the previous row), the light-emitting control line 63 for transmitting the light-emitting control signal En, the data signal line 64 for transmitting the data signal Dm, the driving voltage line 65 for transmitting the driving voltage VDD, The initialization voltage line 66 for transmitting the initialization voltage Vint, and the power supply line 67 for transmitting the VSS voltage.
  • the plurality of signal lines include: a scan signal line 61 for transmitting the scan signal Sn, for transmitting the reset control signal RESET (for example, the reset control signal RESET may the reset signal line 62 for the scan signal of the previous row), the light-emitting control line 63 for transmitting the light-emitting control signal En, the data signal line 64 for transmitting the data signal
  • the storage capacitor Cst may include two capacitor plates Cst1 and Cst2.
  • the capacitor plate Cst1 may be referred to as one end, the first end or the first storage capacitor electrode of the storage capacitor Cst, and the capacitor plate Cst2 may be referred to as the storage capacitor.
  • the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 and the seventh transistor T7 may be formed along the active layer as in FIG. 8 .
  • the active layer may have a bent or bent shape, and may include a first active layer 20a corresponding to the first transistor T1, a second active layer 20b corresponding to the second transistor T2, a first active layer 20b corresponding to the third transistor T3.
  • the active layer may include, for example, polysilicon, and include, for example, a channel region, a source region, and a drain region.
  • the channel region may be undoped or of a different type of doping than the source and drain regions, and thus have semiconductor properties.
  • the source region and the drain region are located on both sides of the channel region, respectively, and are doped with impurities and thus have conductivity. Impurities may vary depending on whether the TFT is an N-type or P-type transistor.
  • the first transistor T1 includes a first active layer 20a and a first gate G1.
  • the first active layer 20a includes a first channel region 201a, a first source region 203a and a first drain region 205a.
  • the gate G1 of the first transistor T1 is electrically connected to the reset signal line 62
  • the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66 .
  • the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2 and the gate G3 of the third transistor T3. As shown in FIG.
  • the drain D1 of the first transistor T1 , one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2 and the gate G3 of the third transistor T3 are electrically connected to the node N1 .
  • the first transistor T1 is turned on according to the reset control signal RESET transmitted through the reset signal line 62 to transmit the initialization voltage Vint to the gate G1 of the third transistor T3, thereby performing an initialization operation to switch the gate G3 of the third transistor T3 to the gate G1. Voltage initialization. That is, herein, the first transistor T1 is also referred to as a reset transistor.
  • the second transistor T2 includes a second active layer 20b and a second gate G2.
  • the second active layer 20b includes a second channel region 201b, a second source region 203b, and a second drain region 205b.
  • the gate G2 of the second transistor T2 is electrically connected to the scan signal line 61
  • the source S2 of the second transistor T2 is electrically connected to the node N3
  • the drain D2 of the second transistor T2 is electrically connected to the node N1.
  • the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing diode connection of the third transistor T3.
  • the second transistor T2 is also referred to as a compensation transistor.
  • the third transistor T3 includes a third active layer 20c and a third gate G3.
  • the third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c.
  • the third source region 203c and the third drain region 205c extend in opposite directions with respect to the third channel region 201c.
  • the third source region 203c of the third transistor T3 is connected to the fourth drain region 205d and the fifth drain region 205e.
  • the third drain region 205c is connected to the second source region 203b and the sixth source region 203f.
  • the gate G3 of the third transistor T3 is electrically connected at the node N1 through the via holes VAH1 and VAH2 and the first connection portion 68 .
  • the gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3.
  • the third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the OLED.
  • the third transistor T3 is also referred to as a driving transistor.
  • the fourth transistor T4 includes a fourth active layer 20d and a fourth gate G4.
  • the fourth active layer 20d includes a fourth channel region 201d, a fourth source region 203d and a fourth drain region 205d.
  • the fourth transistor T4 serves as a switching device for selecting the target sub-pixel to emit light.
  • the fourth gate G4 is connected to the scan signal line 61
  • the fourth source region 203d is connected to the data signal line 64 through the via hole VAH4
  • the fourth drain region 205d is connected to the first transistor T1 and the fifth transistor T5, that is, the electrical Connect to node N2.
  • the fourth transistor T4 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform a switching operation to transmit the data signal Dm to the source S3 of the third transistor T3.
  • the fourth transistor T4 is also referred to as a switching transistor.
  • the fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5.
  • the fifth active layer 20e includes a fifth channel region 201e, a fifth source region 203e and a fifth drain region 205e.
  • the fifth source region 203e may be connected to the driving voltage line 65 through the via hole VAH6.
  • the gate G5 of the fifth transistor T5 is electrically connected to the light emission control line 63
  • the source S5 of the fifth transistor T5 is electrically connected to the driving voltage line 65 .
  • the drain D5 of the fifth transistor T5 is electrically connected to the node N2.
  • the fifth transistor T5 is also referred to as an operation control transistor.
  • the sixth transistor T6 includes a sixth active layer 20f and a sixth gate electrode G6, and the sixth active layer 20f includes a sixth channel region 201f, a sixth source region 203f, and a sixth drain region 205f.
  • the sixth drain region 205f may be connected to the anode of the OLED through the via hole VAH7.
  • the gate G6 of the sixth transistor T6 is electrically connected to the light emission control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, that is, electrically connected to the OLED the anode.
  • the fifth transistor T5 and the sixth transistor T6 are turned on concurrently (eg, simultaneously) according to the light emission control signal En transmitted through the light emission control line 63 to transmit the driving voltage VDD to the OLED, thereby allowing the driving current Id to flow into the OLED.
  • the sixth transistor T6 is also referred to as a light emission control transistor.
  • the seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7.
  • the seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g, and a seventh channel region 201g.
  • the seventh drain region 205g is connected to the first source region 203a of the first transistor T1.
  • the seventh drain region 205g may be electrically connected to the initialization voltage line 66 through the via hole VAH8, the second connection part 69 and the via hole VAH5.
  • the gate G7 of the seventh transistor T7 is electrically connected to the reset signal line 62
  • the source S7 of the seventh transistor T7 is electrically connected to the node N4
  • the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66 .
  • the initialization voltage Vint transmitted by the initialization voltage line 66 may be supplied to the OLED, eg, to the first electrode (eg, anode) of the OLED, to initialize the voltage on the first electrode of the OLED.
  • the seventh transistor T7 may also be referred to as an initialization transistor T7.
  • One end (hereinafter referred to as a first storage capacitor electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1 , and the other end (hereinafter referred to as a second storage capacitor electrode) Cst2 is electrically connected to the driving voltage line 65 .
  • the anode of the OLED is electrically connected to the node N4, and the cathode is electrically connected to the power line 67 to receive the common voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.
  • each of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 are p-channel field effect transistors, but the embodiments of the present disclosure are not limited thereto, the thin film transistors T1, T2 At least some of , T3, T4, T5, T6, and T7 may be n-channel field effect transistors.
  • the reset control signal RESET having a low level is supplied through the reset signal line 62 .
  • the first transistor T1 is turned on based on the low level of the reset control signal RESET, and the initialization voltage Vint from the initialization voltage line 66 is transferred to the gate G1 of the third transistor T3 through the first transistor T1. Therefore, the third transistor T3 is initialized due to the initialization voltage Vint.
  • the scan signal Sn having a low level is supplied through the scan signal line 61 .
  • the fourth transistor T4 and the second transistor T2 are turned on based on the low level of the scan signal Sn. Therefore, the third transistor T3 is placed in a diode-connected state and biased in the forward direction by the turned-on second transistor T2.
  • a compensation voltage Dm+Vth (eg, Vth is a negative value) obtained by subtracting the threshold voltage Vth of the third transistor T3 from the data signal Dm supplied via the data signal line 64 is applied to the gate G3 of the third transistor T3 .
  • the driving voltage VDD and the compensation voltage Dm+Vth are applied to both terminals of the storage capacitor Cst, so that charges corresponding to the voltage difference between the respective terminals are stored in the storage capacitor Cst.
  • the light emission control signal En from the light emission control line 63 changes from high level to low level. Subsequently, in the light emission stage, the fifth transistor T5 and the sixth transistor T6 are turned on based on the low level of the light emission control signal En.
  • a driving current is generated based on the difference between the voltage of the gate G3 of the third transistor T3 and the driving voltage VDD.
  • the driving current Id corresponding to the difference between the driving current and the bypass current is supplied to the OLED through the sixth transistor T6.
  • the gate-source voltage of the third transistor T3 is maintained at (Dm+Vth)-VDD due to the storage capacitor Cst.
  • the drive current Id is proportional to (Dm-VDD) 2 . Therefore, the driving current Id may not be affected by the variation of the threshold voltage Vth of the third transistor T3.
  • the display substrate includes a base substrate 1 and a plurality of film layers disposed on the base substrate 1 .
  • the plurality of film layers include at least a semiconductor layer 20 , a first conductive layer 21 , a second conductive layer 22 , a third conductive layer 23 and a fourth conductive layer 24 .
  • the semiconductor layer 20 , the first conductive layer 21 , the second conductive layer 22 and the third conductive layer 23 are disposed away from the base substrate 1 in sequence.
  • the plurality of film layers further include at least a plurality of insulating film layers, for example, the plurality of insulating film layers may include a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer IDL and a passivation layer PVX .
  • the first gate insulating layer GI1 may be disposed between the semiconductor layer 20 and the first conductive layer 21
  • the second gate insulating layer GI2 may be disposed between the first conductive layer 21 and the second conductive layer 22
  • the interlayer insulating layer IDL may be Disposed between the second conductive layer 22 and the third conductive layer 23
  • the passivation layer PVX may be disposed between the third conductive layer 23 and the fourth conductive layer 24 .
  • the semiconductor layer 20 may be formed of a semiconductor material such as low temperature polysilicon, and its film thickness may be in the range of 400-800 angstroms, for example, 500 angstroms.
  • the first conductive layer 21 and the second conductive layer 22 may be formed of a conductive material forming the gate of the thin film transistor, for example, the conductive material may be Mo, and the film thickness may be in the range of 2000-4000 angstroms, such as 3000 angstroms.
  • the third conductive layer 23 and the fourth conductive layer 24 may be formed of a conductive material forming the source and drain electrodes of the thin film transistor, for example, the conductive material may include Ti, Al, etc., and the third conductive layer 23 may have Ti/Al/
  • the layered structure formed by Ti can have a film thickness in the range of 6000-9000 angstroms.
  • the thickness of each layer of Ti/Al/Ti may be about 500 angstroms, 6000 angstroms, and 6000 angstroms, respectively. 500 angstroms.
  • the first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed of silicon oxide, silicon nitride or silicon oxynitride, and each layer may have a thickness of about 1000 ⁇ 2000 angstroms.
  • the interlayer insulating layer IDL and the passivation layer PVX may be formed of silicon oxide, silicon nitride, or silicon oxynitride, and have a thickness of about 3000 ⁇ 6000 angstroms.
  • the display substrate includes a scan signal line 61 , a reset signal line 62 , and a light emission control line 63 arranged along the row direction X to apply the scan signal Sn, the reset control signal RESET, the light emission control signal En and the initialization voltage Vint to the respective sub-pixels, respectively and initialization voltage line 66 .
  • the display substrate may further include a data signal line 64 and a driving voltage crossing the scan signal line 61, the reset signal line 62, the light emission control line 63 and the initialization voltage line 66 to apply the data signal Dm and the driving voltage VDD to each sub-pixel, respectively.
  • Line 65 is a data signal line 64 and a driving voltage crossing the scan signal line 61, the reset signal line 62, the light emission control line 63 and the initialization voltage line 66 to apply the data signal Dm and the driving voltage VDD to each sub-pixel, respectively.
  • the scan signal lines 61 , the reset signal lines 62 and the light emission control lines 63 are all located in the first conductive layer 21 .
  • the gates G1 to G7 of the above transistors are also located in the first conductive layer 21 .
  • the overlapping portion of the reset signal line 62 and the semiconductor layer 20 forms the gate G1 of the first transistor T1 and the gate G7 of the seventh transistor T7, respectively, and the overlapping portion of the scanning signal line 61 and the semiconductor layer 20 respectively forms the second transistor T2
  • the gate G2 of the fourth transistor T4 and the gate G4 of the fourth transistor T4 forms the gate G6 of the sixth transistor T6 and the gate G5 of the fifth transistor T5, respectively.
  • the display substrate may further include a plurality of first storage capacitor electrodes Cst1.
  • the plurality of first storage capacitor electrodes Cst1 are also located in the first conductive layer 21 .
  • the portion of the first storage capacitor electrode Cst1 overlapping with the semiconductor layer 20 forms the third gate G3 of the third transistor T3.
  • the first storage capacitor electrode Cst1 also forms one terminal of the storage capacitor Cst. That is, the first storage capacitor electrode Cst1 simultaneously functions as the gate G3 of the third transistor T3 and one electrode of the storage capacitor Cst.
  • the orthographic projection of the first storage capacitor electrode Cst1 on the base substrate 1 may have a substantially rectangular shape.
  • substantially rectangular may include rectangles, rectangles with rounded corners at least one corner, rectangles with chamfered corners at least one corner, and the like.
  • the initialization voltage lines 66 are located in the second conductive layer 22 .
  • the display substrate may further include a plurality of second storage capacitor electrodes Cst2.
  • the plurality of second storage capacitor electrodes Cst2 are also located in the second conductive layer 22 .
  • the plurality of second storage capacitor electrodes Cst2 are respectively provided corresponding to the plurality of first storage capacitor electrodes Cst1. That is, the orthographic projections of the plurality of second storage capacitor electrodes Cst2 on the base substrate 1 at least partially overlap with the orthographic projections of the corresponding first storage capacitor electrodes Cst1 on the base substrate 1 .
  • the second storage capacitor electrode Cst2 forms the other terminal of the storage capacitor Cst.
  • the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 are disposed opposite to each other, their orthographic projections on the base substrate 1 at least partially overlap each other, and the second gate insulating layer GI2 is disposed therebetween.
  • the first storage capacitor electrode Cst1 may be electrically connected to the node N1 through the via holes VAH1 and VAH2 and the first connection part 68
  • the second storage capacitor electrode Cst2 may be electrically connected to the driving voltage line 65 through the via hole VAH9, that is, both Connect to different voltage signals. In this way, a portion where the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 overlap each other may form the storage capacitor Cst.
  • the second storage capacitor electrode Cst2 may include through holes TH2 to facilitate the first storage capacitor electrode Cst1 located under the second storage capacitor electrode Cst2 and the components located in the third conductive layer 23 electrical connection.
  • a portion of the first connection portion 68 is formed in the via hole VAH1 to form the conductive plug 681 .
  • the conductive plug 681 extends through the through hole TH2 and is electrically connected to the first storage capacitor electrode Cst1. In this way, one end of the first connection portion 68 is electrically connected to one end Cst1 of the storage capacitor.
  • the orthographic projection of the through hole TH2 on the base substrate 1 may have a substantially rectangular shape.
  • substantially rectangular may include rectangles or squares, rectangles or squares with at least one corner rounded, rectangles or squares with at least one corner chamfered, and the like.
  • the data signal lines 64 and the driving voltage lines 65 are located in the third conductive layer 23 .
  • the first connection portion 68 and the second connection portion 69 are also located in the third conductive layer 23 .
  • the third connection part 70 is located in the fourth conductive layer 24 .
  • One end of the third connection part 70 is electrically connected to the sixth transistor T6, and the other end is electrically connected to the anode of the OLED.
  • the display substrate 100 may further include an insulating layer, such as a planarization layer PLN, disposed between the fourth conductive layer 24 and the fifth conductive layer 25 .
  • the planarization layer PLN may include a single film layer or a plurality of film layers.
  • the plurality of film layers of the planarization layer PLN may be represented as a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3, respectively.
  • the via hole VAH10 may penetrate the planarization layer PLN.
  • the anode 42A of the second light emitting device 42 is located in the fifth conductive layer 25 .
  • a part of the anode connection part 422 is formed in the via hole VAH10 , and the part extends downward to be electrically connected with a part of the third connection part 10 .
  • each sub-pixel on the display substrate needs to be arranged in a prescribed manner, so that the extension lengths of the third connection portions 70 in each sub-pixel may be equal or unequal.
  • FIG. 12A shows a plan view of the pixel driving circuit of the sub-pixel 21 or the sub-pixel 22
  • FIG. 12B shows the pixel driving circuit of the sub-pixel 23 . floor plan.
  • the extension length of the third connection part 70 in the sub-pixel 23 may be smaller than the extension length of the third connection part 70 in the sub-pixel 21 or the sub-pixel 22 .
  • 6B is an equivalent circuit diagram of a pixel driving circuit of one sub-pixel group located in the first display area of the display substrate according to some exemplary embodiments of the present disclosure.
  • 15 is a plan view illustrating an exemplary embodiment of sub-pixels in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure, in which one repetition in the first display area AA1 is schematically shown Floor plan of the unit.
  • 16A is a plan view illustrating a semiconductor layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 16B is a partial enlarged view showing the semiconductor layer shown in FIG. 16A at the reset transistor.
  • 17A is a plan view illustrating a first conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure.
  • 17B is a plan view illustrating a combination of a semiconductor layer and a first conductive layer of a sub-pixel group in the first display area AA1 of the display substrate according to some exemplary embodiments of the present disclosure.
  • 18A is a plan view illustrating a second conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure.
  • 18B is a plan view illustrating a combination of a semiconductor layer, a first conductive layer, and a second conductive layer of a subpixel group in the first display area AA1 of the display substrate according to some exemplary embodiments of the present disclosure.
  • 19A is a plan view illustrating a third conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure.
  • 19B is a plan view illustrating a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer of a sub-pixel group in the first display area AA1 of the display substrate according to some exemplary embodiments of the present disclosure .
  • 20A is a plan view illustrating a first transparent conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure.
  • 20B is a diagram illustrating a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a first transparent conductive layer of a sub-pixel group in the first display area AA1 of the display substrate according to some exemplary embodiments of the present disclosure floor plan.
  • 21A is a plan view illustrating a fourth conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure.
  • 20B is a diagram illustrating a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, and a fourth sub-pixel group in the first display area AA1 of the display substrate according to some exemplary embodiments of the present disclosure
  • a plan view of the combination of conductive layers. 22A is a plan view illustrating a second transparent conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure.
  • 22B illustrates semiconductor layers, first conductive layers, second conductive layers, first transparent conductive layers, fourth sub-pixel groups in the first display area AA1 of the display substrate according to some exemplary embodiments of the present disclosure
  • 23A is a plan view illustrating a fifth conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure.
  • 23B illustrates semiconductor layers, first conductive layers, second conductive layers, first transparent conductive layers, fourth sub-pixel groups in the first display area AA1 of the display substrate according to some exemplary embodiments of the present disclosure Plan view of the combination of the conductive layer, the second transparent conductive layer, and the fifth conductive layer.
  • 24A is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line DD' in FIG. 21B according to some exemplary embodiments of the present disclosure.
  • 24B is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line EE' in FIG. 23A according to some exemplary embodiments of the present disclosure.
  • elements with the same or similar functions and/or structures in the first display area and the second display area may be represented by the same reference numerals,
  • the respective transistors, storage capacitors, and signal lines located in the first display area may be represented by reference numerals corresponding to the respective transistors, storage capacitors, and signal lines located in the second display area, respectively.
  • these elements and structures are located in the first display area AA1.
  • the pixel driving circuits of the sub-pixels 11, 12, 13 may include: a plurality of thin film transistors and a storage capacitor Cst.
  • the pixel driving circuit is used for driving organic light emitting diodes (ie OLEDs).
  • the plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
  • Each transistor includes a gate, a source and a drain.
  • the plurality of signal lines include: a scan signal line 61 for transmitting a scan signal Sn, a reset signal line 62 for transmitting a reset control signal RESET (for example, the reset control signal RESET may be the scan signal of the previous row),
  • the display substrate further includes a pixel defining layer on the side of the first electrode away from the pixel driving circuit.
  • the pixel defining layer It includes a plurality of openings, each sub-pixel corresponds to at least one (eg, one) pixel-defining layer opening, and the actual light-emitting area or display area of the sub-pixel is approximately equal to the pixel-defining layer opening corresponding to the sub-pixel.
  • the area of the pixel-defining layer opening or the actual light-emitting area corresponding to each sub-pixel is smaller than the area of the first electrode (eg, the anode), and the projection on the base substrate completely falls within the projection of the first electrode on the base substrate within.
  • each sub-pixel located in the first display area AA1 may include a light-emitting device (eg, OLED).
  • the light-emitting device located in the first display area AA1 is referred to as The first light emitting device 41 .
  • the first light emitting device 41 may include an anode 41A (refer to FIG. 24B ), a light emitting material layer, and a cathode arranged in layers. It should be noted that, for the sake of clarity, the related drawings use the anode of the first light emitting device 41 to schematically illustrate the first light emitting device 41, thereby schematically representing the sub-pixels located in the first display area AA1.
  • the anode of the first light emitting device 41 includes an anode body 411 and an anode connection part 412 .
  • the orthographic projection of the anode body 411 on the base substrate 1 may have a regular shape, such as a circle, an ellipse, a rectangle, a hexagon, an octagon, a rounded rectangle, and the like.
  • a pixel driving circuit (to be described later) for driving the first light emitting device 41 is also provided in the first display area AA1 , and the anode connecting portion 412 is electrically connected to the pixel driving circuit of the first light emitting device 41 .
  • the pixel defining layer opening and anode are schematically shown.
  • the orthographic projection of the opening OPH on the base substrate 1 may have a regular shape, such as a circle, an ellipse, a rectangle, a hexagon, an octagon, a rounded rectangle, and the like.
  • the projection of the opening OPH on the base substrate 1 completely falls within the projection of the anode body 411 on the base substrate 1 .
  • the approximate positions and shapes of the first electrodes (eg, anodes) of the sub-pixels are mainly shown to represent the distribution of each sub-pixel.
  • the arrangement of sub-pixels in each repeating unit may refer to conventional pixel arrangements, such as GGRB, RGBG, RGB, etc., which are not limited in the embodiments of the present disclosure.
  • the first repeating unit P1 may include a plurality of sub-pixels arranged in 4 rows and 4 columns.
  • the sub-pixels 11 and 12 are arranged in the first and third columns, respectively.
  • two sub-pixels 13 are arranged in the second column and the fourth column, respectively.
  • the sub-pixels 12 and the sub-pixels 11 are arranged in the first and third columns, respectively.
  • two sub-pixels 13 are arranged in the second and fourth columns, respectively.
  • the arrangement of the sub-pixels shown in FIG. 15 is only an exemplary arrangement of some embodiments of the present disclosure, rather than a limitation of the embodiments of the present disclosure. In other embodiments, the sub-pixels may be Use other arrangements.
  • the display substrate may include a plurality of sub-pixel groups located in the first display area AA1, for example, one sub-pixel group may include at least two sub-pixel groups pixel.
  • one sub-pixel group may include at least two sub-pixel groups pixel.
  • two sub-pixels in the at least two sub-pixels are respectively referred to as a first sub-pixel and a second sub-pixel.
  • the first sub-pixel may be one of the above-mentioned sub-pixels 11, 12 and 13
  • the second sub-pixel may be one of the above-mentioned sub-pixels 11, 12 and 13 different from the first sub-pixel.
  • the first subpixel and the second subpixel may be subpixels of different colors.
  • the area of the orthographic projection of the anode body portion 421 of one sub-pixel 11 on the base substrate 1 is smaller than that of the anode body portion 421 of one sub-pixel 12 on the base substrate 1
  • the area of the orthographic projection of the anode main body 421 of one subpixel 13 on the base substrate 1 is smaller than the orthographic projection area of the anode main body 421 of one subpixel 11 on the base substrate 1 .
  • the actual light-emitting area of a green sub-pixel is the smallest
  • the actual light-emitting area of a blue sub-pixel is the largest
  • the actual light-emitting area of a red sub-pixel is between the green sub-pixel and the blue sub-pixel.
  • the first sub-pixel in one sub-pixel group, may be one of a red sub-pixel and a blue sub-pixel, and the second sub-pixel may be a green sub-pixel.
  • the first sub-pixel in one sub-pixel group, may be one of a red sub-pixel and a blue sub-pixel, and the second sub-pixel may be a green sub-pixel.
  • FIG. 15 to FIG. 23B show plan views of a sub-pixel group located in the first display area AA1, wherein, in each plan view, the picture on the upper left side is the first sub-pixel 11 ( 12 ) , and the lower right figure is a plan view of the second sub-pixel 13 .
  • a first sub-pixel driving circuit and a second sub-pixel driving circuit are provided.
  • the dashed-line box on the left in FIG. 6B shows the first sub-pixel driving circuit DR1
  • the dashed-line box on the right in FIG. 6B shows the second sub-pixel driving circuit DR2 .
  • the first sub-pixel driving circuit DR1 is used for driving the first light-emitting device 41 of the first sub-pixel 11 ( 12 ) to emit light
  • the second sub-pixel driving circuit DR2 is used for driving the first light-emitting device 41 of the second sub-pixel 13 to emit light.
  • each of the first subpixel driving circuit DR1 and the second subpixel driving circuit DR2 may include a plurality of thin film transistors and a storage capacitor Cst.
  • the plurality of thin film transistors may include a first transistor (also called a reset transistor) T1, a second transistor (also called a compensation transistor) T2, a third transistor (also called a driving transistor) T3, a fourth transistor ( Also referred to as a switching transistor) T4, a fifth transistor (also referred to as an operation control transistor) T5, a sixth transistor (also referred to as a light emission control transistor) T6, and a seventh transistor (also referred to as an initialization transistor) T7.
  • Each transistor includes a gate, a source and a drain.
  • the plurality of thin film transistors T1 to T7 included in the first sub-pixel driving circuit DR1 are respectively referred to as the first reset transistor T1, the first compensation transistor T2, the first driving transistor T3, The first switching transistor T4, the first operation control transistor T5, the first light emission control transistor T6 and the first initialization transistor T7;
  • the plurality of thin film transistors T1-T7 included in the second sub-pixel driving circuit DR2 are respectively referred to as second reset transistors T1', a second compensation transistor T2, a second driving transistor T3, a second switching transistor T4, a second operation control transistor T5, a second light emission control transistor T6, and a second initialization transistor T7.
  • the first reset transistor T1 of the first subpixel driving circuit DR1 and the second reset transistor T1' of the second subpixel driving circuit DR2 are at least partially shared.
  • the first reset transistor may include a common transistor T10 and a first sub-transistor T11
  • the second reset transistor may include the common transistor T10 and a second sub-transistor T12.
  • the common transistor T10 serves both as a part of the first reset transistor and as a part of the second reset transistor, and is used in the first sub-pixel driving circuit DR1 and the second sub-pixel driving circuit DR1 respectively. function in circuit DR2.
  • the common transistor T10, the first sub-transistor T11 and the second sub-transistor T12 each include a gate G1, a source S1 and a drain D1, the common transistor T10, the gate of each of the first sub-transistor T11 and the second sub-transistor T12 is connected to the reset control signal RESET, and one of the source or drain of the common transistor T10 is connected to an initialization voltage Signal Vint, the other one of the source or the drain of the common transistor T10 is electrically connected to the first sub-transistor T11 and the second sub-transistor T12, respectively.
  • the pixel driving circuits of multiple sub-pixels may share at least a part of the reset transistor, which is beneficial to reduce the area of the occupied area of the pixel driving circuits corresponding to some sub-pixels, thereby enabling
  • the PPI of the under-screen camera area is high, and the light transmittance of the under-screen camera area is guaranteed to meet the requirements.
  • the display substrate includes a base substrate 1 and a plurality of film layers disposed on the base substrate 1 .
  • the plurality of film layers at least include a semiconductor layer 20, a first conductive layer 21, a second conductive layer 22, a third conductive layer 23, a first transparent conductive layer 26, a fourth conductive layer 24, a Two transparent conductive layers 28 and a fifth conductive layer 25 .
  • the semiconductor layer 20 , the first conductive layer 21 , the second conductive layer 22 , the third conductive layer 23 , the first transparent conductive layer 26 , the fourth conductive layer 24 , the second transparent conductive layer 28 and the fifth conductive layer 25 are in turn away from the substrate
  • the base substrate 1 is provided.
  • the plurality of film layers further include at least a plurality of insulating film layers, for example, the plurality of insulating film layers may include a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer IDL, and a passivation layer PVX and the planarization layer PLN.
  • the plurality of insulating film layers may include a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer IDL, and a passivation layer PVX and the planarization layer PLN.
  • the first gate insulating layer GI1 may be disposed between the semiconductor layer 20 and the first conductive layer 21, the second gate insulating layer GI2 may be disposed between the first conductive layer 21 and the second conductive layer 22, and the interlayer insulating layer IDL may be Disposed between the second conductive layer 22 and the third conductive layer 23 , the passivation layer PVX may be disposed between the third conductive layer 23 and the first transparent conductive layer 26 .
  • the planarization layer PLN may include a plurality of film layers, which are respectively referred to as a first planarization layer PLN1 , a second planarization layer PLN2 and a third planarization layer PLN3 for convenience of description.
  • the first planarization layer PLN1 may be disposed between the first transparent conductive layer 26 and the fourth conductive layer 24, and the second planarization layer PLN2 may be disposed between the fourth conductive layer 24 and the second transparent conductive layer 28 , the third planarization layer PLN3 may be disposed between the second transparent conductive layer 28 and the fifth conductive layer 25 .
  • the reset transistor T1, the compensation transistor T2, the driving transistor T3, the switching transistor T4, the operation control transistor T5, the light emission control transistor T6 and the initialization transistor T7 included in the pixel driving circuit of each sub-pixel may be along the lines such as The active layer in FIG. 16A is formed.
  • the active layer may have a bent or bent shape, and may include a first active layer 20a corresponding to the reset transistor T1, a second active layer 20b corresponding to the transistor T2, and a third active layer corresponding to the driving transistor T3 20c, the fourth active layer 20d corresponding to the switching transistor T4, the fifth active layer 20e corresponding to the operation control transistor T5, the sixth active layer 20f corresponding to the light emission control transistor T6, and the sixth active layer 20f corresponding to the initialization transistor T7 Seven active layers 20g.
  • the active layers 20 b to 20 f of the transistor T2 , the second driving transistor T3 , the second switching transistor T4 , the second operation control transistor T5 and the second light emission control transistor T6 are formed as part of the continuous extension of the semiconductor layer 20 .
  • the seventh active layer 20g of the first initialization transistor T7 of the first sub-pixel driving circuit DR1 of the first sub-pixel 11 ( 12 ) and the first sub-pixel driving circuit DR1 are located in the semiconductor Other parts in the layer 20 (ie, the first reset transistor T1, the first compensation transistor T2, the first drive transistor T3, the first switch transistor T4, the first operation control transistor T5 and the first light emission of the first sub-pixel drive circuit DR1
  • the active layers 20a-20f of the control transistor T6 are arranged at intervals; the seventh active layer 20g of the second initialization transistor T7 of the second sub-pixel driving circuit DR2 of the second sub-pixel 13 and the second sub-pixel driving circuit DR2
  • Other parts in the semiconductor layer 20 ie, the second reset transistor T1 ′, the second compensation transistor T2 , the second driving transistor T3 , the second switching transistor T4 , the second operation control transistor of the second sub-pixel driving circuit DR2 ) T5 and the active layers 20a-20f) of the second
  • the active layer 20a of the first reset transistor T1 of the first sub-pixel driving circuit DR1 of the first sub-pixel 11 ( 12 ) and the second sub-pixel driving circuit DR2 of the second sub-pixel 13 The active layers 20a of the two reset transistors T1' are at least partially shared.
  • the common transistor T10 includes a common active layer 200a including a common channel portion 2010a, a common source portion 2030a and a common drain portion 2050a.
  • the first sub-transistor T11 includes a first sub-active layer 211a including a first channel portion 2011a, a first sub-source portion 2031a and a first sub-drain portion 2051a.
  • the second sub-transistor T12 includes a second sub-active layer 212a including a second channel portion 2012a, a second sub-source portion 2032a and a second sub-drain portion 2052a.
  • the common source portion 2030a and the common drain portion 2050a are located on both sides of the common channel portion 2010a, respectively, and the first sub-source portion 2031a and the first sub-drain portion 2051a are respectively located on both sides of the common channel portion 2010a.
  • the second sub-source portion 2032a and the second sub-drain portion 2052a are located on both sides of the second channel portion 2012a, respectively.
  • the common active layer 200a, the first sub-active layer 211a and the second sub-active layer 212a extend continuously. For example, one end of the common active layer 200a is connected to both the first sub-active layer 211a and the second sub-active layer 212a.
  • the common active layer 200a and the first sub-active layer 211a constitute the active layer 20a of the first reset transistor T1 of the first sub-pixel driving circuit DR1 of the first sub-pixel 11 ( 12 ).
  • the common active layer 200a and the second sub-active layer 212a constitute the active layer 20a of the second reset transistor T1' of the second sub-pixel driving circuit DR2 of the second sub-pixel 13. That is, the active layer 20a of the first reset transistor T1 and the active layer 20a of the second reset transistor T1' have at least a common part—the common active layer 200a.
  • the active layer 20 a of the second reset transistor T1 ′ of the second sub-pixel driving circuit DR2 is formed in the occupied area of the first sub-pixel driving circuit DR1 , which is beneficial to reduce the second sub-pixel driving circuit DR1 The area of the occupied area of the pixel drive circuit DR2.
  • the active layer 20g of the first initialization transistor T7 and the active layer 20a of the first reset transistor T1 are arranged at intervals.
  • the active layer 20a of the first reset transistor T1 is connected to the active layer 20b of the first compensation transistor T2, and the active layer 20b of the first compensation transistor T2 is connected to the active layer 20c of the first driving transistor T3 and the first light emission control transistor T6
  • the active layer 20f of the first driving transistor T3 is connected to the active layer 20d of the first switching transistor T4 and the active layer 20e of the first operation control transistor T5.
  • the active layer 20f of the first light emission control transistor T6, the active layer 20d of the first switching transistor T4, and the active layer 20e of the first operation control transistor T5 extend continuously.
  • the active layer 20g of the first initialization transistor T7 is provided spaced apart from these active layers.
  • the active layer 20b of the second compensation transistor T2 is connected to the active layer 20c of the second driving transistor T3 and the active layer 20f of the second light emission control transistor T6, and the second driving transistor T3
  • the active layer 20c connects the active layer 20d of the second switching transistor T4 and the active layer 20e of the second operation control transistor T5. That is, the active layer 20b of the second compensation transistor T2, the active layer 20c of the second driving transistor T3, the active layer 20f of the second light emission control transistor T6, the active layer 20d of the second switching transistor T4 and the second operation
  • the active layer 20e of the control transistor T5 extends continuously.
  • the active layer 20g of the second initialization transistor T7 is provided spaced apart from these active layers.
  • the active layer 20g of the first initialization transistor T7 is away from the active layer 20a of the first reset transistor T1 along the direction away from the sub-pixel.
  • the direction of the scanning signal line 61 extends, that is, the active layer 20g of the first initialization transistor T7 is located above and rightward of the active layer 20a of the first reset transistor T1.
  • the active layer 20g of the first initialization transistor T7 can extend toward the active layers of the adjacent sub-pixels located above the same column, which is beneficial to the formation of the active layers of the sub-pixels located in the same column to be continuous extended structure.
  • the active layer 20g of the first initialization transistor T7 is relative to the active layer 20a of the first reset transistor T1 along a scan close to the sub-pixel
  • the direction of the signal line 61 extends, that is, the active layer 20g of the first initialization transistor T7 is located at the lower right of the active layer 20a of the first reset transistor T1.
  • the outline of the occupied area of the active layer of one sub-pixel located in the first display area AA1 is square or approximately square.
  • the expression "occupied area” refers to the largest area covered by the orthographic projection of a pattern, layer structure, etc. on the base substrate, specifically, the orthographic projection of a pattern, layer structure, etc. on the base substrate has a The two farthest sides in one direction X and the two farthest sides in the second direction Y, the extension lines of these four sides will intersect to enclose an area, which is the pattern, The occupied area of the layer structure, etc.
  • the occupied area of its active layer has a rectangular or substantially rectangular shape, as shown in FIG. 8 , which is indicated by a dotted line frame Figure 2 shows the occupied area of the active layer of one sub-pixel located in the second display area AA2, the occupied area has a dimension along the first direction X (ie width W2) and a dimension along the second direction Y (ie length L2), wherein the length L2 is greater than the width W2, or in other words, the length L2 is more than 1.2 times the width W2, that is, the occupied area has a rectangular shape.
  • the occupied area of its active layer has a square or approximately square shape, as shown in FIG. 16A , a dotted frame is used to schematically illustrate the area located in the first display area AA1
  • the occupied area of the active layer of one sub-pixel in the occupied area has a dimension along the first direction X (ie width W1) and a dimension along the second direction Y (ie length L1), wherein the length L1 is substantially equal to the width W1.
  • the occupied area of the active layer of one sub-pixel located in the first display area AA1 is smaller than that of the active layer of one sub-pixel of the same color located in the second display area AA2 area. In this way, the area of the occupied area of the pixel driving circuit of the sub-pixel located in the first display area AA1 can be reduced, which will be described in further detail below.
  • the scan signal line 61 , the reset signal line 62 and the light emission control line 63 are all located in the first conductive layer 21 .
  • the gates G1 to G7 of the above transistors are also located in the first conductive layer 21 .
  • the first storage capacitor electrode Cst1 is also located in the first conductive layer 21 .
  • the first conductive layer 21 is located on the side of the semiconductor layer 20 away from the base substrate 1 .
  • the first sub-pixel 11 ( 12 ) and the second sub-pixel 13 share a reset signal line 62 . That is, the reset signal line 62 is provided only in the occupied area of the first sub-pixel driving circuit DR1 of the first sub-pixel 11 ( 12 ), and not in the occupied area of the second sub-pixel driving circuit DR2 of the second sub-pixel 13 .
  • a reset signal line 62 is provided.
  • the scanning signal line 61 , the reset signal line 62 and the light emission control line 63 are provided; In the occupied area of the sub-pixel drive circuit DR2, the scanning signal line 61 and the light emission control line 63 are provided.
  • the overlapping portion of the scanning signal line 61 and the semiconductor layer 20 forms the gate G2 of the first compensation transistor T2 and the gate of the first switching transistor T4 , respectively G4, and another part of the scanning signal line 61 overlapping with the semiconductor layer 20 also forms the gate G7 of the first initialization transistor T7. That is, in the embodiment of the present disclosure, in the first display area AA1, the gates of the first initialization transistor T7, the first compensation transistor T2 and the first switching transistor T4 are all supplied with the scan signal Sn.
  • the initialization voltage Vint transmitted by the initialization voltage line 66 may be supplied to the OLED, eg, to the first electrode (eg, anode) of the OLED, to initialize the first electrode of the OLED voltage on.
  • the overlapping portions of the scanning signal line 61 and the semiconductor layer 20 form the gate G2 of the second compensation transistor T2 and the gate G4 of the second switching transistor T4, respectively, and the scanning signal line 61 and the semiconductor layer
  • the other portion where 20 overlaps also forms the gate G7 of the second initialization transistor T7. That is, in the embodiment of the present disclosure, in the first display area AA1, the gates of the second initialization transistor T7, the second compensation transistor T2 and the second switching transistor T4 all supply the scan signal Sn.
  • one reset signal line 62 includes a first part 621 , a second part 622 and a third part 623 located in the first display area AA1 , the first part 621 , the first part 621 , the third part 623
  • the orthographic projections of the second portion 622 and the third portion 623 on the base substrate 1 are located where the common channel portion 2010a, the first channel portion 2011a and the second channel portion 2012a are located, respectively.
  • the gate of T12 includes the third portion 623 .
  • the first portion 621 of the reset signal line 62 may extend substantially along the second direction Y, and the second portion 622 and the third portion 623 of the reset signal line 62 may extend substantially along the first direction X, that is, the first portion of the reset signal line 62
  • the portion 621 is substantially perpendicular to the second portion 622 and the third portion 623 of the reset signal line 62 .
  • the gate of each of the common transistor T10, the first sub-transistor T11 and the second sub-transistor T12 is connected to the reset control signal RESET.
  • the first reset transistor T1 (including the shared transistor T10 and the first sub-transistor T11 ) of the first sub-pixel driving circuit DR1 and the second sub-pixel driving circuit DR2
  • the orthographic projection of each of the reset transistors T1 ′ (including the common transistor T10 and the second sub-transistor T12 ) on the substrate 1 falls into the occupied area of the first sub-pixel driving circuit DR1 on the substrate. In the orthographic projection on the substrate 1. In this way, the area of the occupied region of the second subpixel driving circuit DR2 of the second subpixel can be reduced.
  • the orthographic projection of the first reset transistor T1 of the first sub-pixel driving circuit DR1 on the base substrate 1 can be performed by the first reset of the first sub-pixel driving circuit DR1
  • the orthographic projection of the channel region of the transistor T1 on the base substrate 1 is represented;
  • the orthographic projection of the second reset transistor T1' of the second sub-pixel driving circuit DR2 on the base substrate 1 can be represented by the An orthographic representation of the channel region of the second reset transistor T1 ′ of the second sub-pixel driving circuit DR2 on the base substrate 1 .
  • the initialization voltage line 66 and the second storage capacitor electrode Cst2 are located in the second conductive layer 22 .
  • the second conductive layer 22 is located on the side of the first conductive layer 21 away from the base substrate 1 .
  • the first sub-pixel 11 ( 12 ) and the second sub-pixel 13 share one initialization voltage line 66 . That is, the initialization voltage line 66 is provided only in the occupied area of the first sub-pixel driving circuit DR1 of the first sub-pixel 11 ( 12 ), and not in the occupied area of the second sub-pixel driving circuit DR2 of the second sub-pixel 13 .
  • the initialization voltage line 66 is set.
  • the second storage capacitor electrode Cst2 includes a through hole TH2, and the combination of the solid portion of the second storage capacitor electrode Cst2 and the through hole TH2 is in the base substrate 1
  • the orthographic projection on is in the shape of a rectangle or rounded rectangle.
  • the second storage capacitor electrode Cst2 has a notch NTH1 at one corner, that is, the second storage capacitor electrode Cst2 is located on the base substrate 1
  • the orthographic projection on is "L" shaped.
  • the orthographic projection of the combination of the solid portion of the second storage capacitor electrode Cst2 and the notch NTH1 on the base substrate 1 is in the shape of a rectangle or a rounded rectangle.
  • the notch NTH1 exposes a part of the first storage capacitor electrode Cst1 located under the second storage capacitor electrode Cst2 so that the first storage capacitor electrode Cst1 is electrically connected with other parts.
  • the area of the orthographic projection of the second storage capacitor electrode Cst2 of one sub-pixel located in the first display area AA1 on the base substrate 1 is larger than that of the one sub-pixel located in the second display area AA2.
  • the area of the orthographic projection of the second storage capacitor electrode Cst2 on the base substrate 1 is small.
  • the second storage capacitor electrode Cst2 of a sub-pixel located in the first display area AA1 is designed to be "L" shaped, and it is not necessary to form the through hole in the second storage capacitor electrode Cst2, which is beneficial to ensure the
  • the overlapping area of the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 of one sub-pixel in the first display area AA1 is larger, that is, the capacitance value of the storage capacitor Cst is guaranteed to be larger.
  • connection part 168 , the connection part 169 , the connection part 170 , and the connection part 171 are located in the third conductive layer 23 .
  • the third conductive layer 23 is located on the side of the second conductive layer 22 away from the base substrate 1 .
  • connection portion 168 is formed in the via hole VH6, the portion extending downward to be electrically connected with the portion of the first storage capacitor electrode Cst1 exposed by the notch NTH1.
  • Another portion of the connection portion 168 is formed in the via hole VH2, the portion extending downward to be electrically connected with the drain D2 of the first compensation transistor T2 and the drain D1 of the first reset transistor T1.
  • the first storage capacitor electrode Cst1, the drain D2 of the first compensation transistor T2 and the drain D1 of the first reset transistor T1 can be electrically connected through the connection part 168, that is, the node N1 shown in FIG. 6B is formed.
  • the connection part 169 includes a first connection sub-part 1691 and a second connection sub-part 1692 .
  • the first connecting sub-portion 1691 and the second connecting sub-portion 1692 are connected to each other to form a continuously extending connecting portion 169 .
  • a portion of the first connection sub-portion 1691 is formed in the via hole VH12 , and the portion extends downward to be electrically connected to the initialization voltage line 66 .
  • Another portion of the first connection sub-portion 1691 is formed in the via hole VH124, the portion extending downward to be electrically connected to one of the common source portion 2030a and the common drain portion 2050a of the common transistor T10.
  • the initialization voltage Vint transmitted by the initialization voltage line 66 can be supplied to the source of the first reset transistor T1 of the first sub-pixel drive circuit DR1 electrode or drain electrode and the source electrode or drain electrode of the second reset transistor T1' of the second sub-pixel driving circuit DR2.
  • Another portion of the second connection sub-portion 1692 is formed in the via hole VH4, and the portion extends downward to be electrically connected to the drain D7 of the first initialization transistor T7. In this way, the initialization voltage Vint transmitted by the initialization voltage line 66 can be supplied to the drain D7 of the first initialization transistor T7.
  • connection portion 170 is formed in the via hole VH5, and the portion extends downward to be electrically connected to the source S7 of the first initialization transistor T7.
  • Another portion of the connection portion 170 is formed in the via hole VH10, and the portion extends downward to be electrically connected to the drain D6 of the first light emission control transistor T6.
  • the connection part 170 the source S7 of the first initialization transistor T7 and the drain D6 of the first light emission control transistor T6 can be electrically connected, that is, the N4 node shown in FIG. 6B is formed.
  • connection portion 171 A portion of the connection portion 171 is formed in the via hole VH7, and the portion extends downward to be electrically connected to the second storage capacitor electrode Cst2. Another portion of the connection portion 171 is formed in the via hole VH9, and the portion extends downward to be electrically connected to the source S5 of the first operation control transistor T5. Through the connection portion 171, the second storage capacitor electrode Cst2 can be electrically connected to the source S5 of the first operation control transistor T5.
  • connection portion 168', the connection portion 170' and the connection portion 171' are located in the third conductive layer 23.
  • connection portion 168' is formed in the via hole VH6', the portion extending downward to be electrically connected with the portion of the first storage capacitor electrode Cst1 exposed by the notch NTH1.
  • Another portion of the connection portion 168' is formed in the via hole VH2', the portion extending downward to be electrically connected to the drain D2 of the second compensation transistor T2.
  • connection portion 170' A portion of the connection portion 170' is formed in the via hole VH5', the portion extending downward to be electrically connected to the source S7 of the second initialization transistor T7. Another portion of the connection portion 170' is formed in the via hole VH10', the portion extending downward to be electrically connected to the drain D6 of the second light emission control transistor T6. Through the connection portion 170', the source S7 of the second initialization transistor T7 and the drain D6 of the second light emission control transistor T6 can be electrically connected.
  • connection portion 171' A portion of the connection portion 171' is formed in the via hole VH7', the portion extending downward to be electrically connected to the second storage capacitor electrode Cst2. Another portion of the connection portion 171' is formed in the via hole VH9', the portion extending downward to be electrically connected to the source S5 of the second operation control transistor T5. Through the connection portion 171', the second storage capacitor electrode Cst2 can be electrically connected to the source S5 of the second operation control transistor T5.
  • a first transparent conductive layer 26 is provided, for example, the first transparent conductive layer 26 may be composed of a transparent conductive material such as indium tin oxide (ie, ITO) and the like .
  • ITO indium tin oxide
  • the data signal lines 164 and the driving voltage lines 165 are located in the first transparent conductive layer 26 . That is, the data signal lines 164 and the driving voltage lines 165 are formed of a transparent conductive material such as indium tin oxide (ie, ITO).
  • ITO indium tin oxide
  • the display substrate may further include a plurality of transparent conductive connections in the first transparent conductive layer 26 .
  • the plurality of transparent conductive connection parts may include a first transparent conductive connection part 161 , a second transparent conductive connection part 162 , a third transparent conductive connection part 163 and a fourth transparent conductive connection part 166 . That is, these transparent conductive connection parts are all composed of a transparent conductive material such as indium tin oxide (ie, ITO).
  • the display substrate may also include a plurality of conductive leads located in the first transparent conductive layer 26 .
  • the plurality of conductive leads may include a third conductive lead 263 and a fourth conductive lead 266 . That is, these conductive leads are all composed of a transparent conductive material such as indium tin oxide (ie, ITO).
  • the components used to electrically connect the elements in the pixel driving circuit of a plurality of subpixels in one subpixel group are called conductive connection parts, and the components used to electrically connect components located in different subpixel groups (
  • the components of the elements in the pixel driving circuit of a plurality of sub-pixels in an adjacent sub-pixel group) are called conductive leads, and such expressions are only for the convenience of description, and are not intended to specifically limit that these components must be different, for example,
  • Some features of the components may be the same, eg, at least some of the components may be located in the same conductive layer, eg, all in the first transparent conductive layer 26, or at least some of the components may be made of the same conductive material
  • the composition is, for example, composed of a transparent conductive material such as indium tin oxide (ie, ITO).
  • the data line 164 may extend substantially continuously along the second direction Y.
  • a portion of the data signal line 164 is formed in the via hole VH3, the portion extending downward to be electrically connected to the source S4 of the first switching transistor T4, thereby supplying the data signal Dm transmitted by the data signal line 164 to the first switching transistor T4 .
  • the driving voltage line 165 is disconnected at the pixel driving circuits of the sub-pixels in the first display area AA1, divided into two parts. For the convenience of description, these two parts are denoted as a first driving voltage sub-line 1651 and a second driving voltage sub-line 1652, respectively.
  • the orthographic projection of the first driving voltage sub-line 1651 on the base substrate 1 intersects with the orthographic projection of the initialization voltage line 66 on the base substrate 1 , and the positive projection of the first driving voltage sub-line 1651 on the base substrate 1 The projection at least partially overlaps the orthographic projection of the reset signal line 62 on the base substrate 1 .
  • the orthographic projection of the second driving voltage sub-line 1652 on the base substrate 1 intersects with the orthographic projection of the light emission control line 63 on the base substrate 1, and the second driving voltage sub-line 1652 on the base substrate 1 crosses the orthographic projection of the second driving voltage sub-line 1652
  • the orthographic projection at least partially overlaps the orthographic projection of the second storage capacitor electrode Cst2 on the base substrate 1 .
  • a portion of the second driving voltage sub-line 1652 is formed in the via hole VH20, and the portion extends downward to be electrically connected to a portion of the connection portion 171, thereby being electrically connected to the second storage capacitor electrode Cst2. In this way, electrical connection between the driving voltage line, the second storage capacitor electrode Cst2 and the source S5 of the first operation control transistor T5 can be achieved.
  • the first driving voltage sub-line 1651 and the second driving voltage sub-line 1652 are spaced apart from each other in the second direction Y by a certain distance.
  • the orthographic projection of one end of the first driving voltage sub-line 1651 close to the second driving voltage sub-line 1652 on the base substrate 1 partially overlaps with the orthographic projection of the reset signal line 62 on the base substrate 1, and the second driving voltage sub-line 1652
  • the orthographic projection of the end of the line 1652 close to the first driving voltage sub-line 1651 on the base substrate 1 partially overlaps the orthographic projection of the portion of the second storage capacitor electrode Cst2 close to the light emission control line 63 on the base substrate 1 .
  • the spaced-apart first driving voltage sub-line 1651 and the second driving voltage sub-line 1652 will be electrically connected together by a connection part, which will be described in detail below.
  • a first transparent conductive connection part 161 is provided between the first subpixel and the second subpixel, for connecting the first transparent conductive connection part 161 located in the occupied area of the first subpixel
  • the two reset transistors T1' (including the common transistor T10 and the second sub-transistor T12) are electrically connected to the second sub-pixel driving circuit DR2.
  • one end of the first transparent conductive connection part 161 is electrically connected to one of the second sub-source part 2032 a and the second sub-drain part 2052 a through the via hole VH21 , the first transparent conductive The other end of the connecting portion 161 is electrically connected to the gate of the second driving transistor T3 of the second sub-pixel driving circuit DR2 through the via hole VH22.
  • the second reset transistor T1' (including the common transistor T10 and the second sub-transistor T12) located in the occupied area of the first sub-pixel can be electrically connected into the second sub-pixel driving circuit DR2.
  • the orthographic projection of the first transparent conductive connection portion 161 on the base substrate 1 partially overlaps with the orthographic projection of the active layer 20g of the first initialization transistor T7 on the base substrate 1, and The orthographic projection of the first transparent conductive connection portion 161 on the base substrate 1 partially overlaps the orthographic projection of the active layer 20g of the second initialization transistor T7 on the base substrate 1 .
  • the first transparent conductive connection part 161 includes at least a first part 1611 , a second part 1612 and a third part 1613 .
  • the second part 1612 is located between the first part 1611 and the third part 1613 and connects the first part 1611 and the third part 1613 .
  • the first transparent conductive connecting portion 161 is a connecting portion extending continuously.
  • the third portion 1613 of the first transparent conductive connection portion extends along the first direction X
  • the second portion 1612 of the first transparent conductive connection portion extends along the second direction Y
  • the third portion 1612 of the first transparent conductive connection portion extends along the second direction Y.
  • a portion 1611 extends in an inclined direction inclined with respect to both the first direction X and the second direction Y.
  • the orthographic projection of the first portion 1611 of the first transparent conductive connection portion on the base substrate 1 overlaps with the orthographic portion of the active layer 20g of the first initialization transistor T7 on the base substrate 1 .
  • the orthographic projection of the third portion 1613 of the first transparent conductive connection portion on the base substrate 1 overlaps with the orthographic projection of the active layer 20g of the second initialization transistor T7 on the base substrate 1 .
  • the second portion 1612 of the first transparent conductive connection is located in the light-transmitting area between the first subpixel and the second subpixel. For example, a part of the first part 1611 of the first transparent conductive connection part and a part of the third part 1613 of the first transparent conductive connection part are also located between the first subpixel and the second subpixel in the light-transmitting area.
  • a second transparent conductive connection part 162 is provided between the first subpixel and the second subpixel for resetting the occupied area of the first subpixel
  • the signal line 66 is electrically connected to the second sub-pixel driving circuit DR2, so that the reset signal RESET is connected to the second sub-pixel driving circuit DR2.
  • the resistance of the first transparent conductive connection part 161 may be reduced.
  • the line width of the first transparent conductive connection part 161 may be increased, eg, the line width of the first transparent conductive connection part 161 may be larger than that of each of the conductive connection parts 162 , 163 and 166 .
  • the extension length of the first transparent conductive connection part 161 can be shortened.
  • the first transparent conductive connection part may be formed by using the conductive parts located in two conductive layers in parallel, for example, the first part of the first transparent conductive connection part may be located in the first transparent conductive layer, and the second part may be located in the first transparent conductive layer. In the third conductive layer, the fourth conductive layer or the second transparent conductive layer, the first part and the second part are connected in parallel to form the first transparent conductive connection part.
  • the first transparent conductive connection part 161 may be disposed on the most edge side. That is, the arrangement order of the transparent conductive connection parts 161 , 162 , 163 and 166 is not limited to the one shown in FIGS. 20A to 20B .
  • the first transparent conductive connection part 161 may be disposed on a side of the second conductive connection part 162 away from the third conductive connection part 163 . In this way, the influence of other electronic components or electrical environment on the first transparent conductive connection portion 161 can be minimized, thereby ensuring the stability of the reset signal transmitted by the first transparent conductive connection portion 161 .
  • the transmission path of the reset signal can be made
  • the resistances are basically the same, or in other words, the resistances on the transmission paths of the reset signals of different sub-pixels can be adjusted.
  • the resistors R1 and R3 in FIG. 6C schematically represent the resistors on the path where the reset signal is transmitted to the gate of the driving transistor T3 of the first sub-pixel
  • the resistors R2 and R4 schematically represent the reset signal transmission. resistance on the path to the gate of the drive transistor T3 of the second sub-pixel.
  • the line width of the first transparent conductive connection part 161 can be increased, the extension length of the first transparent conductive connection part 161 can be shortened, or two conductive layers (such as the first transparent conductive layer and the second transparent conductive layer can be used)
  • the conductive parts in the layer are connected in parallel to form a first transparent conductive connection part to adjust the resistance on the path where the reset signal is transmitted to the gate of the driving transistor T3 of the second sub-pixel, so that the reset signal is transmitted
  • the resistances on the paths to the gates of the driving transistors T3 of the two sub-pixels are substantially the same.
  • the coupling capacitance acting on the node N1 can be adjusted to adjust the potential at the node N1 of different sub-pixels, so that the potential at the node N1 of different sub-pixels remains stable, that is, basically the same.
  • Cst1-ref1 in FIG. 6C schematically shows the coupling capacitance acting on the node N1 of the first sub-pixel driving circuit DR1
  • Cst1-ref2 schematically shows the node N1 acting on the second sub-pixel driving circuit DR2 the coupling capacitor.
  • the first transparent conductive connection 161 ie, the wire for transmitting the reset signal to the gate of the driving transistor of the second sub-pixel driving circuit
  • the driving voltage line eg, the first driving voltage sub-line 1651
  • the positions of the transparent conductive connection parts 161, 162, 163 may be exchanged; or, the first transparent conductive connection part 161 may overlap the film layer having the VDD potential; or, a part of the initialization signal line 66 may be downward extending so as to overlap the first transparent conductive connecting portion 161 .
  • the first transparent conductive connection part 161 may be arranged to overlap with a conductive part or a film layer having a constant potential to form a coupling capacitance acting on the node N1.
  • the overlapping areas of the two sub-pixels eg, the first sub-pixel and the second sub-pixel
  • the reset transistor can be made different, so as to realize the differentiated design of different sub-pixels, so as to adjust all parts of the node N1.
  • the electrical environment of the conductive parts In this way, the potentials at the node N1 in the pixel driving circuits of different sub-pixels can be kept consistent, which is beneficial to improve the uniformity of the display substrate.
  • resistors R1 ⁇ R4 and the coupling capacitors Cst1 -reff1 and Cst1 -ref2 are simultaneously arranged in FIG. 6C , the embodiments of the present disclosure are not limited thereto.
  • only the resistances R1 ⁇ R4 may be set to adjust the resistances on the path where the reset signal is transmitted to the gates of the driving transistors T3 of the two sub-pixels.
  • only the coupling capacitor acting on the node N1 may be set to adjust the potentials at the nodes N1 of different sub-pixels.
  • one end of the second transparent conductive connection part 162 is electrically connected to the connection part 169 through a via hole VH23
  • the other end of the second transparent conductive connection part 162 is electrically connected to the second transparent conductive connection part 162 through a via hole VH24
  • One end of the active layer 20g of the second initialization transistor T7 of the sub-pixel drive circuit DR2 is electrically connected.
  • the orthographic projection of the via hole VH23 on the base substrate 1 at least partially overlaps the orthographic projection of the via hole VH4 on the base substrate 1 . That is, one end of the second transparent conductive connecting portion 162 is electrically connected to one end (the lower end in FIG.
  • the other end of the second transparent conductive connection portion 162 is electrically connected to the seventh source region 203g or the seventh drain region 205g of the second initialization transistor T7 through the via hole VH24.
  • the reset signal RESET transmitted by the reset signal line 66 can be supplied to the source or drain of the second initialization transistor T7 of the second sub-pixel driving circuit DR2.
  • the second transparent conductive connection part 162 includes at least a first part 1621 , a second part 1622 and a third part 1623 , and the second part 1622 is located between the first part 1621 and the third part 1623 .
  • the first portion 1621 of the second transparent conductive connection portion extends along the first direction X
  • the third portion 1623 of the second transparent conductive connection portion extends along the second direction Y
  • the second transparent conductive connection portion extends in an inclined direction that is inclined with respect to both the first direction X and the second direction Y.
  • the second transparent conductive connection part 162 may be located in a light-transmitting area between the first sub-pixel and the second sub-pixel.
  • the first part 1621 , the second part 1622 and the third part 1623 of the second transparent conductive connection part 162 are all located in the light-transmitting area between the first sub-pixel and the second sub-pixel.
  • connection portion 172 and the conductive connection portion 173 are located in the fourth conductive layer 24 .
  • connection part 172 A part of the connection part 172 is formed in the via hole VH1 , and the part extends downward to be electrically connected with the first driving voltage sub-line 1651 .
  • Another part of the connection part 172 is formed in the via hole VH7 ′′′, and the part extends downward to be electrically connected with the second driving voltage sub-line 1652 . That is, through the connection part 172 , the first driving voltage sub-line 1651 can be connected to It is electrically connected to the second driving voltage sub-line 1652, so that the driving voltage lines of each sub-pixel located in the same column can be connected, so as to supply the driving voltage signal VDD to each sub-pixel.
  • the first driving voltage sub-line 1651 and the second driving voltage sub-line 1652 may not be disconnected at the pixel driving circuit, and thus, the connection part 172 may not be provided.
  • the first driving voltage sub-line 1651 and the second driving voltage sub-line 1652 may be disconnected at the pixel driving circuit, and at the same time, a connection part 172 may also be provided. In this way, the connection part 172 is connected in parallel with a part of the driving voltage line 165 , which is beneficial to reduce the resistance on the driving voltage line 165 .
  • a part of the conductive connection part 173 is formed in the via hole VH10' which exposes a part of the connection part 170, so that the conductive connection part 173 can be electrically connected to the connection part 170.
  • a second transparent conductive layer 28 is provided in the first display area AA1.
  • the second transparent conductive layer 28 may be made of a transparent conductive material such as indium tin oxide (ie, ITO). constitute.
  • the second transparent conductive layer 28 is located on the side of the fourth conductive layer 24 away from the base substrate 1 .
  • the display substrate further includes a first conductive lead 181 and a second conductive lead 182 disposed on the base substrate 1 .
  • the first conductive lead 181 and the second conductive lead 182 may be located in the second transparent conductive layer 28 . That is, the first conductive lead 181 and the second conductive lead 182 are composed of a transparent conductive material such as indium tin oxide (ie, ITO).
  • transistors T1, T1' in addition to the reset transistors T1, T1', other transistors T2-T7 in the first and second sub-pixel driving circuits DR1 and DR2 may be mirror-arranged.
  • FIGS. 25A and 25B are plan views illustrating exemplary embodiments of a plurality of sub-pixel groups in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure.
  • 20A, 20B, 22A, 22B, and 25A and 25B in the first display area AA1, the scan signal line 61, the reset signal line 62, the light emission control line 63 and the The initialization voltage lines 66 are electrically connected through conductive leads or transparent conductive connections located in the transparent conductive layer, respectively.
  • conductive leads or transparent conductive connections located in the transparent conductive layer, respectively.
  • the light transmittance of the first display area AA1 can be guaranteed to be large.
  • the first scanning signal line 61 of the first sub-pixel 11 ( 12 ) and the second scanning signal line 61 of the second sub-pixel 13 are electrically connected through the third transparent conductive connection part 163
  • the first light-emitting control line 63 of the first sub-pixel 11 ( 12 ) and the second light-emitting control line 63 of the second sub-pixel 13 are electrically connected through a fourth transparent conductive connection portion 166 .
  • third conductive leads 263 are respectively disposed to electrically connect the scanning signal lines 61 of each sub-pixel group in the same row together.
  • a portion of the third conductive lead 263 on the left is formed in the via hole VH15 , and the portion extends downward to be electrically connected to one end of the first scan signal line 61 .
  • a portion of the third conductive lead 263 located on the right side is formed in the via hole VH15 , and the portion extends downward to be electrically connected to one end of the second scan signal line 61 .
  • fourth conductive leads 266 are respectively provided to electrically connect the light-emitting control lines 63 of each sub-pixel group in the same row together.
  • a part of the fourth conductive lead 266 on the left is formed in the via hole VH17 , and the part extends downward to be electrically connected with one end of the first light emission control line 63 .
  • a part of the fourth conductive lead 266 on the right side is formed in the via hole VH17 , and the part extends downward to be electrically connected with one end of the second light emission control line 63 .
  • First conductive leads 181 are respectively provided on both sides of the reset signal line 62 of one sub-pixel group. A portion of a first conductive lead 181 is formed in the via hole VH13 , and the portion extends downward to be electrically connected to one end of the reset signal line 62 . A portion of the other first conductive lead 181 is formed in the via hole VH14 , and the portion extends downward to be electrically connected to the other end of the reset signal line 62 . By means of the first conductive lead 181, the reset signal lines 62 of the sub-pixel groups in the same row can be electrically connected, so as to supply the reset signal Reset.
  • Second conductive leads 182 are respectively provided on both sides of the initialization voltage line 66 of one sub-pixel group. A portion of a second conductive lead 182 is formed in the via hole VH11 , and the portion extends downward to be electrically connected to one end of the initialization voltage line 66 . A portion of the other second conductive lead 182 is formed in the via hole VH12 , and the portion extends downward to be electrically connected to the other end of the initialization voltage line 66 .
  • the initialization voltage lines 66 of the sub-pixel groups in the same row can be electrically connected, so as to supply the lighting initialization voltage signal Vinit.
  • the plurality of sub-pixel groups at least include a first sub-pixel group SP1 and a second sub-pixel group SP2 that are located in the same row and are adjacent to each other.
  • One end of a first conductive lead 181 is electrically connected to the reset signal line 62 in the first sub-pixel group SP1 through the via hole VH13, and the other end of the first conductive lead 181 is electrically connected to the reset signal line 62 in the second sub-pixel group SP1 through the via hole VH14.
  • the reset signal line 62 is electrically connected.
  • One end of a second conductive lead 182 is electrically connected to the initialization voltage line 66 in the first sub-pixel group SP1 through the via hole VH11, and the other end of the second conductive lead 182 is connected to the second sub-pixel group SP2 through the via hole VH12.
  • the initialization voltage line 66 is electrically connected.
  • the orthographic projection of at least one of the first conductive lead 181 and the second conductive lead 182 on the base substrate 1 is the same as the data line 164 and the driving voltage line
  • the orthographic projection of at least one of the first driving voltage sub-lines 1651 and/or the second driving voltage sub-lines 1652 on the base substrate 1 intersects.
  • the first electrode (eg, the anode) of the first light emitting device 41 may be located in the fifth conductive layer 25 .
  • the anode of the first light emitting device 41 includes the anode body 411 and the anode connection part 412 .
  • a part of the anode connection part 412 may be formed in the via hole VH10 ′′, and the via hole VH10 ′′ exposes a part of the conductive connection part 173 , so that the anode connection part 412 can be electrically connected to Connected to the conductive connection part 173 and then to the connection part 170 . That is, through the conductive connection part 173 and the connection part 170 , the anode of the first light emitting device 41 of the first sub-pixel, the source S7 of the first initialization transistor T7 and the drain D6 of the first light emission control transistor T6 can be electrically connected to each other. connected, i.e. forming the N4 node shown in FIG. 6B.
  • a portion of the anode connection portion 412 may be formed in the via hole VH10", which exposes a portion of the conductive connection portion 173, so that the anode connection portion 412 may be electrically connected to the conductive connection portion 173.
  • the connecting part 173 is then connected to the connecting part 170 . That is, through the conductive connection part 173 and the connection part 170 , the anode of the first light emitting device 41 of the second sub-pixel, the source S7 of the second initialization transistor T7 and the drain D6 of the second light emission control transistor T6 can be electrically connected, i.e. forming the N4 node shown in FIG. 6B.
  • the pixel driving circuits of the sub-pixel 11 , the sub-pixel 12 and the sub-pixel 13 can be substantially reduced to the size of the first light emitting device 41 . size, and placed under the light emitting device 41 .
  • the pixel driving circuit of each sub-pixel can be built into the corresponding sub-pixel, and it does not need to be externally placed in the spacer area SR, which can avoid the above-mentioned Various problems caused by external pixel drive circuits.
  • the pixel driving circuit of each sub-pixel is built into the corresponding sub-pixel, and is hidden under the light-emitting device of the corresponding sub-pixel, which can ensure that the light transmittance of the first display area is relatively large. , that is, it is beneficial to realize the high transmittance of the first display area.
  • the first display area AA1 between each adjacent sub-pixel, there is a light-transmitting area TRA.
  • the pixel driving circuit of each sub-pixel can be basically reduced to the size of the first light-emitting device 41 and placed under the light-emitting device 41, it is beneficial to realize a larger area of the light-transmitting region TRA, thereby ensuring the first display region The transmittance is high. Moreover, in the light-transmitting area TRA, only transparent conductive leads are provided without any opaque leads, thereby further ensuring that the light transmittance of the first display area is large.
  • the area of the area occupied by the pixel driving circuits of the respective sub-pixels 21 , 22 and 23 is relatively large.
  • the area of the occupied area of the pixel driving circuit of sub-pixel 23 ie, the green sub-pixel
  • the pixel driving circuit of sub-pixel 13 ie, the green sub-pixel
  • the occupied area of the pixel driving circuit of each sub-pixel 21, 22, 23 in the second display area AA2 can be represented by the following area: Referring to FIG. 12A and FIG. 12B, for each sub-pixel 21, 22, 23
  • the data signal line 64 and the sixth active layer 20f of the first light-emitting control transistor T6 are located at the leftmost and the rightmost respectively, that is, the two are in the first direction X.
  • the initialization voltage line 66 and the light-emitting control line 63 are located on the uppermost side and the lowermost side respectively, that is, the distance between the two in the second direction Y is the largest.
  • the data signal line 64 has the first side away from the sixth active layer 20f of the first light-emitting control transistor T6, and the first light-emitting control transistor
  • the sixth active layer 20f of T6 has a second side away from the data signal line 64
  • the initialization voltage line 66 has a third side away from the light emission control line 63
  • the light emission control line 63 has a fourth side away from the initialization voltage line 66
  • the first side and the second side extend along the second direction Y
  • the third side and the fourth side extend along the first direction X
  • the extension lines of these four sides will Cross to form an area, which is the area occupied by the pixel driving circuit of a sub-pixel located in the second display area AA2, such as the area AR22 surrounded by a dotted frame as shown in FIG. 12A .
  • the occupied area of the pixel driving circuit of each sub-pixel 11, 12, 13 in the first display area AA1 can be represented by the following area: Referring to FIG. 23A and FIG. 23B, for the first sub-pixel 11 (12 ), vias VH11, VH12, VH13, VH14, VH15, VH16, VH17, VH18 and VH23 are located on the outermost side of the pixel driver circuit, respectively, and vias VH9 and VH10” are located on the outermost side of the pixel driver circuit. The centers of each two adjacent via holes in the holes are connected in sequence, and can be surrounded to form an area, such as the area AR1 surrounded by a dotted frame as shown in FIG.
  • the area AR1 can be located in the first display area AA1
  • One of the areas The occupied area of the first sub-pixel driving circuit of the first sub-pixel.
  • the vias VH24, VH16', VH18', VH9, VH10", VH17, VH15 and VH3 are located in the pixel driving circuit respectively.
  • On the outermost side connect the centers of every two adjacent vias among the 8 vias in turn to form an area, such as the area AR2 enclosed by the dotted frame as shown in FIG. 23B .
  • the occupied area of the light emitting device of the sub-pixel in the second display area AA2 may be represented by the coverage area of the orthographic projection of the anode of the light emitting device on the base substrate.
  • the occupied area of the light emitting device of the sub-pixel in the first display area AA1 can be represented by the coverage area of the orthographic projection of the anode of the light emitting device on the base substrate.
  • the PPI in the first display area AA1 is substantially equal to the PPI in the second display area. That is to say, within the same area, the number of the first repeating units P1 arranged in the first display area AA1 is substantially equal to the number of the second repeating units P2 arranged in the second display area AA2.
  • the number of sub-pixels arranged in one display area AA1 is substantially equal to the number of sub-pixels of the same color arranged in the second display area AA2. In this way, both the first display area and the second display area have higher PPI, and both can achieve higher display quality and better display uniformity.
  • the expressions “substantially equal”, “substantially equal” and the like may mean that the ratio of the two values being compared is approximately equal to 1, for example, the ratio of the two values being compared may be between 0.8 and 1.2 within the range.
  • the area of the occupied area of the light emitting device of each sub-pixel in the first display area AA1 is substantially equal to the area of the occupied area of the light emitting device of the sub-pixel of the same color in the second display area AA2.
  • the area of the orthographic projection of the anode of the first light-emitting device 41 of the sub-pixel 11 on the base substrate 1 is substantially equal to the area of the orthographic projection of the anode of the second light-emitting device 42 of the sub-pixel 21 on the base substrate 1;
  • the area of the orthographic projection of the anode of the first light-emitting device 41 of the sub-pixel 12 on the base substrate 1 is substantially equal to the area of the orthographic projection of the anode of the second light-emitting device 42 of the sub-pixel 22 on the base substrate 1;
  • the area of the orthographic projection of the anode of the first light emitting device 41 of 13 on the base substrate 1 is substantially equal to the area of the orthographic projection of the anode of the second light emitting device 42 of the sub-pixel 23 on the base substrate 1 .
  • the PPI in the first display area AA1 is basically equal to the PPI in the second display area, and in addition, the display uniformity between the first display area and the second display area can be better. In addition, the uniformity of the lifetime of the luminescent material between the first display area and the second display area is also good.
  • the embodiments of the present disclosure are not limited to the above-mentioned embodiments.
  • the area occupied by the light-emitting device of each sub-pixel in the first display area AA1 is the same as that in the second display area AA2.
  • the areas of the occupied areas of the light-emitting devices of the sub-pixels of the colors may also be unequal, as long as the PPI in the first display area AA1 and the PPI in the second display area can be substantially equal.
  • the area occupied by the pixel driving circuit of each sub-pixel 11, 12, 13 in the first display area AA1 is reduced, which is beneficial to hide the pixel driving circuit of each sub-pixel in the corresponding sub-pixel below the light-emitting device of the pixel.
  • the active layer 20g of the first initialization transistor T7 is close to the active layer 20a of the first reset transistor T1 along the edge of the The direction of the scanning signal line 61 of the sub-pixel extends, that is, the active layer 20g of the first initialization transistor T7 is located at the lower right of the active layer 20a of the first reset transistor T1.
  • the outline of the occupied area of the active layer of one first sub-pixel located in the first display area AA1 is square or approximately square.
  • the orthographic projection of the anode body of the first light emitting device 41 of the first sub-pixel 11 ( 12 ) on the base substrate is a circle.
  • the orthographic projection of the anode of the first light emitting device 41 of the first sub-pixel 11 ( 12 ) on the base substrate 1 and the occupied area AR1 of the pixel driving circuit of the first sub-pixel 11 ( 12 ) are on the base substrate 1
  • the orthographic projection on 1 at least partially overlaps, for example, the orthographic projection of the anode of the first light emitting device 41 of the first sub-pixel 11 (12) on the base substrate 1 substantially completely covers the pixel driving of the first sub-pixel 11 (12)
  • the orthographic projection of the occupied area AR1 of the circuit on the base substrate 1 is described.
  • substantially complete coverage means covering more than 90% of the entire area of a certain orthographic projection.
  • the orthographic projection of the anode of the first light-emitting device 41 of the second sub-pixel 13 on the base substrate 1 and the orthographic projection of the occupied area AR2 of the pixel driving circuit of the second sub-pixel 13 on the base substrate 1 are at least Partially overlapping, for example, the orthographic projection of the anode of the first light-emitting device 41 of the second sub-pixel 13 on the base substrate 1 substantially completely covers the occupied area AR2 of the pixel driving circuit of the second sub-pixel 13 on the base substrate 1. Orthographic projection.
  • the area of the orthographic projection of the anode of the first light-emitting device 41 of the sub-pixel 13 on the base substrate 1 is smaller than that of the anode of the first light-emitting device 41 of the sub-pixel 11 on the base substrate 1 .
  • the projected area, the orthographic projection area of the anode of the first light emitting device 41 of the sub-pixel 11 on the base substrate 1 is smaller than the orthographic projection area of the anode of the first light emitting device 41 of the sub-pixel 12 on the base substrate 1 .
  • the reset transistor in the pixel driving circuit of the second sub-pixel 13 is set to be at least partially shared with the reset transistor in the pixel driving circuit of the first sub-pixel 11 ( 12 ), which can be The number of transistors that need to be arranged in the occupied area AR2 of the pixel driving circuit of the second sub-pixel 13 is reduced, so that the area of the occupied area AR2 of the pixel driving circuit of the second sub-pixel 13 can be reduced.
  • the pixel driving circuit that is, the pixel driving circuit of the second sub-pixel 13 is hidden under the anode of its light-emitting device.
  • the orthographic projection of the anode of the first light emitting device 41 of each sub-pixel on the base substrate 1 at least covers the storage capacitor Cst (including the first storage capacitor electrode) of the pixel driving circuit of the sub-pixel Orthographic projections of Cst1 and the second storage capacitor electrode Cst2) and a plurality of transistors on the base substrate 1.
  • the expression "orthographic projection of a transistor on the underlying substrate” includes a combination of orthographic projections of the active layer, gate, source and drain of the transistor on the underlying substrate.
  • the orthographic projection of the anode of the first light-emitting device 41 of the second sub-pixel 13 on the base substrate 1 covers the second compensation transistor T2 and the second driving transistor of the pixel driving circuit of the second sub-pixel 13 Orthographic projections of T3 , the second switching transistor T4 , the second operation control transistor T5 , the second light emission control transistor T6 , the second initialization transistor T7 and the storage capacitor Cst on the base substrate 1 .
  • the orthographic projection of the anode of the first light-emitting device 41 of the first sub-pixel 11 ( 12 ) on the base substrate 1 covers the first reset transistor of the pixel driving circuit of the first sub-pixel 11 ( 12 ) T1, the first compensation transistor T2, the first driving transistor T3, the first switching transistor T4, the first operation control transistor T5, the first light emission control transistor T6, the first initialization transistor T7 and the storage capacitor Cst on the base substrate 1 Orthographic projection.
  • the orthographic projection of the anode of the first light-emitting device 41 of the first sub-pixel 11 ( 12 ) on the base substrate 1 also covers the second reset transistor T1 ′ of the pixel driving circuit of the second sub-pixel 13 on the base substrate 1 orthographic projection on .
  • the pixel driving circuit of each sub-pixel can be arranged below the light-emitting device (eg, anode), so that the pixel driving circuit does not occupy the light-transmitting area between each sub-pixel , which is beneficial for the first display area to have high light transmittance, and at the same time, it is possible to achieve high PPI in the first display area, that is, it is beneficial to realize the high display quality of the camera area under the screen.
  • the light-emitting device eg, anode
  • FIGS. 26A , 26B and 26C respectively illustrate a blocking layer, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a Plan view of the combination of the first transparent conductive layer, the fourth conductive layer, the second transparent conductive layer, and the fifth conductive layer.
  • 27 is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line FF' in FIG. 26A according to some exemplary embodiments of the present disclosure.
  • the display substrate may further include a blocking layer LS.
  • the shielding layer LS may be disposed between the base substrate 1 and the semiconductor layer 20 to protect the semiconductor layer 20 to prevent the active layer of each transistor of the pixel driving circuit of each sub-pixel from being affected by external light.
  • the shielding layer LS may be composed of an opaque metal material.
  • the blocking layer LS may also include a semiconductor film layer such as amorphous silicon, polysilicon, or the like.
  • the orthographic projection of the shielding layer LS of each sub-pixel on the base substrate 1 may cover the orthographic projection of the occupied area AR1 or AR2 of the pixel driving circuit of the sub-pixel on the base substrate 1 .
  • the pixel driving circuit of each sub-pixel can be prevented from being affected by external light.
  • the shielding layer LS can be connected to a fixed voltage to prevent it from being in a suspended state (ie, floating).
  • the blocking layer LS may be in the shape of a plane or a grid.
  • the orthographic projection of the blocking layer LS on the base substrate 1 may at least partially overlap with the orthographic projection of the structures or parts located in the first transparent conductive layer and/or the second transparent conductive layer on the base substrate 1 .
  • the first light emitting device 41 may include an anode, a layer of a light emitting material, and a cathode arranged in layers.
  • the display substrate may include a sixth conductive layer in which the cathode CAT is located.
  • the sixth conductive layer in the first display area AA1, may be patterned. That is, the sixth conductive layer may include a plurality of cathodes CAT and a plurality of cathode openings 271 . Cathode openings 271 may be located between adjacent cathodes CAT.
  • the orthographic projection of the cathode CAT of the first light-emitting device 41 of each sub-pixel on the base substrate 1 may cover the anode of the first light-emitting device 41 of the sub-pixel on the base substrate 1 orthographic projection.
  • the orthographic projection of each cathode opening 271 on the base substrate 1 may overlap with the orthographic projection of the light transmission area TRA between each sub-pixel on the base substrate 1 .
  • At least some embodiments of the present disclosure also provide a display panel including the display substrate as described above.
  • the display panel may be an OLED display panel.
  • the display device may include the display substrate as described above.
  • the display device may include any device or product having a display function.
  • the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio Players, mobile medical devices, cameras, wearable devices (such as head-mounted devices, electronic clothing, electronic wristbands, electronic necklaces, electronic accessories, electronic tattoos, or smart watches), TV sets, etc.
  • the display panel and the display device according to the embodiments of the present disclosure have all the features and advantages of the above-mentioned display substrate. For details, reference may be made to the above description, which will not be repeated here.

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Abstract

提供一种显示基板、显示面板和显示装置。显示基板包括第一显示区域和第二显示区域，第一显示区域的透光率大于第二显示区域的透光率。位于所述第一显示区域中的多个子像素包括多个子像素组，每一个子像素组包括第一子像素和第二子像素，所述第一像素驱动电路包括第一子像素驱动电路和第二子像素驱动电路，所述第一子像素驱动电路用于驱动第一子像素的第一发光器件发光，所述第二子像素驱动电路用于驱动第二子像素的第一发光器件发光，所述第一子像素驱动电路至少包括第一复位晶体管，所述第二子像素驱动电路至少包括第二复位晶体管，所述第一子像素驱动电路的第一复位晶体管与所述第二子像素驱动电路的第二复位晶体管至少部分共用。

Description

显示基板、显示面板和显示装置 技术领域
本公开涉及显示技术领域，并且具体地涉及一种显示基板、显示面板和显示装置。
背景技术
随着用户对显示装置的多样化使用需求的增加，以及显示装置的高屏占比的设计要求的出现，目前出现了“屏下摄像头”的方案。在“屏下摄像头”的方案中，将摄像头等成像模块嵌入在显示区域中，以缩小显示装置的边框区域的尺寸，从而提高屏占比。目前，在“屏下摄像头”的方案中，在提高显示装置的屏占比的基础上，如何兼顾保证显示基板中对应设置成像模块的位置处的透光率以及显示效果，成为研发人员关注的重要课题。
在本部分中公开的以上信息仅用于对本公开的技术构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
在一个方面，提供一种显示基板，所述显示基板包括第一显示区域和第二显示区域，所述第一显示区域的透光率大于所述第二显示区域的透光率，所述显示基板包括：衬底基板；设置于所述衬底基板且位于所述第一显示区域中的多个子像素，所述子像素包括第一像素驱动电路和第一发光器件，所述第一像素驱动电路与所述第一发光器件电连接，用于驱动所述第一发光器件发光；和设置于所述衬底基板且位于所述第二显示区域中的多个子像素，位于所述第二显示区域中的子像素包括第二像素驱动电路和第二发光器件，所述第二像素驱动电路与所述第二发光器件电连接，用于驱动所述第二发光器件发光，其中，位于所述第一显示区域中的多个子像素包括多个子像素组，每一个子像素组包括第一子像素和第二子像素，所述第一像素驱动电路包括第一子像素驱动电路和第二子像素驱动电路，所述第一子像素驱动电路用于驱动第一子像素的第一发光器件发光，所述第二子像素驱动电路用于驱动第二子像素的第一发光器件发光，所述第一子像素驱动电路至少包括第一复位晶体管，所述第二子像素驱动电路至 少包括第二复位晶体管，所述第一子像素驱动电路的第一复位晶体管与所述第二子像素驱动电路的第二复位晶体管至少部分共用。
根据一些示例性的实施例，所述第一子像素驱动电路的第一复位晶体管与所述第二子像素驱动电路的第二复位晶体管中每一个在所述衬底基板上的正投影均落入所述第一子像素驱动电路的占用区域在所述衬底基板上的正投影内。
根据一些示例性的实施例，所述第一复位晶体管包括共用晶体管和第一子晶体管，所述第二复位晶体管包括所述共用晶体管和第二子晶体管，所述共用晶体管、所述第一子晶体管和所述第二子晶体管中的每一个均包括栅极、源极和漏极，所述共用晶体管、所述第一子晶体管和所述第二子晶体管中的每一个的栅极均接入复位控制信号，所述共用晶体管的源极或漏极中的一个接入初始化电压信号，所述共用晶体管的源极或漏极中的另一个分别与所述第一子晶体管和所述第二子晶体管电连接。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的半导体层和位于所述半导体层远离所述衬底基板的一侧的第一导电层，所述显示基板还包括设置于所述衬底基板上的复位信号线，所述复位信号线用于传输复位控制信号，所述复位信号线位于所述第一导电层；以及所述复位信号线包括位于所述第一显示区域中的第一部分、第二部分和第三部分，所述半导体层包括位于所述第一显示区域中的共用沟道部分、第一沟道部分和第二沟道部分，所述第一部分、所述第二部分和所述第三部分在所述衬底基板上的正投影分别与所述共用沟道部分、所述第一沟道部分和所述第二沟道部分在所述衬底基板上的正投影重合，所述共用晶体管的栅极包括所述第一部分，所述第一子晶体管的栅极包括所述第二部分，所述第二子晶体管的栅极包括所述第三部分。
根据一些示例性的实施例，所述共用晶体管包括位于所述半导体层中的共用源极部分和共用漏极部分，所述第一子晶体管包括位于所述半导体层中的第一子源极部分和第一子漏极部分，所述第二子晶体管包括位于所述半导体层中的第二子源极部分和第二子漏极部分；以及所述共用源极部分和所述共用漏极部分分别位于所述共用沟道部分的两侧，所述第一子源极部分和所述第一子漏极部分分别位于所述第一沟道部分的两侧，所述第二子源极部分和所述第二子漏极部分分别位于所述第二沟道部分的两侧。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的初始化电压线和设置于所述衬底基板上的第一连接部；所述共用源极部分和所述共用漏极部 分中的一个通过第一过孔与所述初始化电压线电连接，所述共用源极部分和所述共用漏极部分中的另一个与所述第一子源极部分和所述第一子漏极部分中的一个连续延伸；以及所述第一子源极部分和所述第一子漏极部分中的另一个通过第二过孔与所述第一连接部的一端电连接。
根据一些示例性的实施例，所述第一子像素驱动电路还包括第一驱动晶体管，所述第一驱动晶体管包括栅极，所述第一连接部的另一端通过第三过孔与所述第一驱动晶体管的栅极电连接。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的第一透明导电连接部；所述共用源极部分和所述共用漏极部分中的另一个还与所述第二子源极部分和所述第二子漏极部分中的一个连续延伸；以及所述第二子源极部分和所述第二子漏极部分中的另一个通过第三过孔与所述第一透明导电连接部的一端电连接。
根据一些示例性的实施例，所述第二子像素驱动电路还包括第二驱动晶体管，所述第二驱动晶体管包括栅极，所述第一透明导电连接部的另一端通过第四过孔与所述第二驱动晶体管的栅极电连接。
根据一些示例性的实施例，所述初始化电压线位于第二导电层中，所述第一连接部位于第三导电层中，所述第二导电层位于所述第一导电层远离所述衬底基板的一侧，所述第三导电层位于所述第二导电层远离所述衬底基板的一侧。
根据一些示例性的实施例，所述第一透明导电连接部位于第一透明导电层中，所述第一透明导电层位于所述第三导电层远离所述衬底基板的一侧。
根据一些示例性的实施例，所述第一子像素驱动电路还包括第一初始化晶体管，所述第一初始化晶体管包括位于所述半导体层中的有源层；所述第二子像素驱动电路还包括第二初始化晶体管，所述第二初始化晶体管包括位于所述半导体层中的有源层；以及所述第一透明导电连接部在所述衬底基板上的正投影与所述第一初始化晶体管的有源层在所述衬底基板上的正投影部分重叠，以及所述第一透明导电连接部在所述衬底基板上的正投影与所述第二初始化晶体管的有源层在所述衬底基板上的正投影部分重叠。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的第一扫描信号线和第二扫描信号线，所述第一扫描信号线用于供应扫描信号给所述第一子像素驱动电路，所述第二扫描信号线用于供应扫描信号给所述第二子像素驱动电路；以及所述第一扫描信号线在所述衬底基板上的正投影与所述第一初始化晶体管的有源层 在所述衬底基板上的正投影部分重叠，所述第二扫描信号线在所述衬底基板上的正投影与所述第二初始化晶体管的有源层在所述衬底基板上的正投影部分重叠。
根据一些示例性的实施例，所述第一透明导电连接部至少包括第一部分、第二部分和第三部分，所述第一透明导电连接部的第三部分沿第一方向延伸，所述第一透明导电连接部的第二部分沿第二方向延伸，所述第一透明导电连接部的第一部分沿相对于第一方向和第二方向均倾斜的倾斜方向延伸。
根据一些示例性的实施例，所述第一透明导电连接部的第一部分在所述衬底基板上的正投影与所述第一初始化晶体管的有源层在所述衬底基板上的正投影部分重叠；和/或，所述第一透明导电连接部的第三部分在所述衬底基板上的正投影与所述第二初始化晶体管的有源层在所述衬底基板上的正投影部分重叠；和/或，所述第一透明导电连接部的第二部分位于第一子像素和第二子像素之间的透光区域中。
根据一些示例性的实施例，所述第一初始化晶体管的有源层与所述第一子像素驱动电路位于所述半导体层中的其他部分间隔设置；和/或，所述第二初始化晶体管的有源层与所述第二子像素驱动电路位于所述半导体层中的其他部分间隔设置。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的第二连接部，所述第二连接部的第一端通过第五过孔与所述初始化电压线电连接，所述第二连接部的第二端通过第六过孔与所述第一初始化晶体管的有源层的第一端电连接。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的第二透明导电连接部，所述第二透明导电连接部的第一端通过第七过孔与所述第二连接部的第二端电连接，所述第二透明导电连接部的第二端通过第八过孔与所述第二初始化晶体管的有源层的第一端电连接。
根据一些示例性的实施例，所述第二连接部位于所述第三导电层中；和/或，所述第二透明导电连接部位于所述第一透明导电层中。
根据一些示例性的实施例，所述第六过孔在所述衬底基板上的正投影与所述第七过孔在所述衬底基板上的正投影至少部分重叠。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的第三透明导电连接部，所述第三透明导电连接部的一端通过第九过孔与所述第一扫描信号线电连接，所述第三透明导电连接部的另一端通过第十过孔与所述第二扫描信号线电连接。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的第一发 光控制线和第二发光控制线，所述第一发光控制线用于供应发光控制信号给所述第一子像素驱动电路，所述第二发光控制线用于供应发光控制信号给所述第二子像素驱动电路；以及所述显示基板还包括设置于所述衬底基板上的第四透明导电连接部，所述第四透明导电连接部的一端通过第十一过孔与所述第一发光控制线电连接，所述第四透明导电连接部的另一端通过第十二过孔与所述第二发光控制线电连接。
根据一些示例性的实施例，在至少一个子像素组中，所述第一子像素和所述第二子像素共用所述复位信号线和所述初始化电压线。
根据一些示例性的实施例，所述多个子像素组至少包括位于同一行且相邻的第一子像素组和第二子像素组；以及所述显示基板还包括设置于所述衬底基板上的第一导电引线，所述第一导电引线的一端通过第十三过孔与第一子像素组中的复位信号线电连接，所述第一导电引线的另一端通过第十四过孔与第二子像素组中的复位信号线电连接。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板上的第二导电引线，所述第二导电引线的一端通过第十五过孔与第一子像素组中的初始化电压线电连接，所述第二导电引线的另一端通过第十六过孔与第二子像素组中的初始化电压线电连接。
根据一些示例性的实施例，所述第三透明导电连接部和/或所述第四透明导电连接部位于所述第一透明导电层中；和，所述第一导电引线和/或所述第二导电引线位于第二透明导电层中，其中，所述第二透明导电层位于所述第一透明导电层远离所述衬底基板的一侧。
根据一些示例性的实施例，所述显示基板还包括：用于传输数据信号的数据信号线；和用于传输驱动电压的驱动电压线；以及所述数据信号线和所述驱动电压线均位于所述第一透明导电层中。
根据一些示例性的实施例，所述驱动电压线在所述第一子像素驱动电路和所述第二子像素驱动电路处断开，以使得所述驱动电压线包括第一驱动电压子线和第二驱动电压子线，所述第一驱动电压子线和第二驱动电压子线在所述驱动电压线的延伸方向上间隔开；以及所述显示基板还包括第三连接部，所述第三连接部的一端通过第十七过孔与所述第一驱动电压子线电连接，另一端通过第十八过孔与所述第二驱动电压子线电连接。
根据一些示例性的实施例，所述显示基板包括设置于所述衬底基板上的第四导电 层，所述第四导电层位于所述第一透明导电层与所述第二透明导电层之间；以及所述第三连接部位于所述第四导电层中。
根据一些示例性的实施例，所述第一导电引线和所述第二导电引线中的至少一个在所述衬底基板上的正投影与所述数据线和所述驱动电压线中的至少一个在所述衬底基板上的正投影交叉。
根据一些示例性的实施例，所述第一发光器件至少包括第一电极和发光材料层，所述发光材料层设置在所述第一电极远离所述衬底基板的一侧；以及所述第一子像素的第一电极在所述衬底基板上的正投影的面积大于所述第二子像素的第一电极在所述衬底基板上的正投影的面积。
根据一些示例性的实施例，所述第一子像素的第一电极在所述衬底基板上的正投影覆盖所述第一子像素驱动电路的占用区域在所述衬底基板上的正投影；和/或，所述第二子像素的第一电极在所述衬底基板上的正投影覆盖所述第二子像素驱动电路的占用区域在所述衬底基板上的正投影。
根据一些示例性的实施例，所述第一子像素为红色子像素或蓝色子像素，所述第二子像素为绿色子像素。
在另一方面，提供一种显示面板，包括如上所述的显示基板。
在又一方面，提供一种显示装置，包括如上所述的显示基板或如上所述的显示面板。
根据一些示例性的实施例，所述显示装置还包括至少一个图像传感器；以及其中，所述至少一个图像传感器在所述衬底基板上的正投影落入所述第一显示区域在所述衬底基板上的正投影内。
附图说明
通过参照附图详细描述本公开的示例性实施例，本公开的特征及优点将变得更加明显。
图1是根据本公开的一些示例性实施例的显示装置的平面示意图，其中示意性示出了显示装置包括的显示基板的平面结构。
图2是根据本公开的一些示例性实施例的显示装置沿图1中的线AA’截取的截面示意图。
图3是根据本公开的一些示例性实施例的显示基板在图1中的部分I处的局部放 大图。
图4是根据本公开的一些示例性实施例的显示基板在图3中的部分II处的局部放大图。
图5是根据本公开的一些示例性实施例的显示基板在图4中的部分III处的局部放大图。
图6A是根据本公开的一些示例性实施例的显示基板的一个像素驱动电路的等效电路图。
图6B是根据本公开的一些示例性实施例的显示基板的位于第一显示区域中的一个子像素的像素驱动电路的等效电路图。
图6C是根据本公开的一些示例性实施例的显示基板的位于第一显示区域中的一个子像素的像素驱动电路的等效电路图。
图7是示出根据本公开的一些示例性实施例的显示基板的第二显示区域中的子像素的示例性实施方式的平面图，其中示意性示出了第二显示区域中的一个重复单元的平面图。
图8是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层的平面图。
图9是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层和第一导电层的组合的平面图。
图10是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层、第一导电层和第二导电层的组合的平面图。
图11是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层、第一导电层、第二导电层和第三导电层的组合的平面图。
图12A和图12B分别是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层、第一导电层、第二导电层、第三导电层和第四导电层的组合的平面图。
图13是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层、第一导电层、第二导电层、第三导电层、第四导电层和第五导电层的组合的平面图。
图14A是示出根据本公开的一些示例性实施例的显示基板的沿图12B中的线BB’截取的截面结构的示意图。
图14B是示出根据本公开的一些示例性实施例的显示基板的沿图13中的线CC’截取的截面结构的示意图。
图15是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素的示例性实施方式的平面图，其中示意性示出了第一显示区域中的一个重复单元的平面图。
图16A是示出图15中一个重复单元包括的子像素的示例性实施方式的半导体层的平面图。
图16B是示出图16A中所示的半导体层在复位晶体管处的局部放大图。
图17A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的第一导电层的平面图。
图17B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的半导体层和第一导电层的组合的平面图。
图18A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的第二导电层的平面图。
图18B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的半导体层、第一导电层和第二导电层的组合的平面图。
图19A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的第三导电层的平面图。
图19B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的半导体层、第一导电层、第二导电层和第三导电层的组合的平面图。
图20A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的第一透明导电层的平面图。
图20B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的半导体层、第一导电层、第二导电层和第一透明导电层的组合的平面图。
图21A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的第四导电层的平面图。
图21B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的半导体层、第一导电层、第二导电层、第一透明导电层和第四导电层的组合的平面图。
图22A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的第二透明导电层的平面图。
图22B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的 子像素组的半导体层、第一导电层、第二导电层、第一透明导电层、第四导电层和第二透明导电层的组合的平面图。
图23A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的第五导电层的平面图。
图23B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的子像素组的半导体层、第一导电层、第二导电层、第一透明导电层、第四导电层、第二透明导电层和第五导电层的组合的平面图。
图24A是示出根据本公开的一些示例性实施例的显示基板的沿图21B中的线DD’截取的截面结构的示意图。
图24B是示出根据本公开的一些示例性实施例的显示基板的沿图23A中的线EE’截取的截面结构的示意图。
图25A和图25B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域中的多个子像素组的示例性实施方式的平面图。
图26A、图26B和图26C分别是示出图15中一个重复单元包括的3个子像素的示例性实施方式的遮挡层、半导体层、第一导电层、第二导电层、第三导电层、第一透明导电层、第四导电层、第二透明导电层和第五导电层的组合的平面图。
图27是示出根据本公开的一些示例性实施例的显示基板的沿图26A中的线FF’截取的截面结构的示意图。
具体实施例
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接 连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在......之间”对“直接在......之间”、“相邻”对“直接相邻”或“在......上”对“直接在......上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XYY、YZ和ZZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
在本文中，术语“大约”、“近似”、“大致”和其它类似的术语用作近似的术语而不是用作程度的术语，并且它们意图解释将由本领域普通技术人员认识到的测量值或计算值的固有偏差。考虑到工艺波动、测量问题和与特定量的测量有关的误差(即，测量系统的局限性)等因素，如这里所使用的“大约”或“近似”包括所陈述的值，并表示对于本领域普通技术人员所确定的特定值在可接受的偏差范围内。例如，“大约”可以表示在一个或更多个标准偏差内，或者在所陈述的值的±30％、±20％、±10％、±5％内。
需要说明的是，在本文中，表示“同一层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺， 而形成的层结构中的特定图形可以是连续的也可以是不连续的。即，位于“同一层”的多个元件、部件、结构和/或部分由相同的材料构成，并且通过同一次构图工艺形成，通常，位于“同一层”的多个元件、部件、结构和/或部分具有大致相同的厚度。
本领域技术人员应该理解，在本文中，除非另有说明，表述“连续延伸”、“一体结构”、“整体结构”或类似表述表示：多个元件、部件、结构和/或部分是位于同一层的，并且在制造过程中通常通过同一次构图工艺形成的，这些元件、部件、结构和/或部分之间没有间隔或断裂处，而是连续延伸的结构。
在本文中，表述“重复单元”表示多个子像素的组合，例如，用来显示一个像素点的多个子像素的组合，多个“重复单元”在衬底基板上成阵列地重复排列。例如，一个重复单元可以包括至少一个像素，例如可以包括2个、3个、4个、或更多个子像素。此外，在本文中，为了描述方便，将位于第一显示区域中的重复单元称为第一重复单元，将位于第二显示区域中的重复单元称为第二重复单元。
在本文中，表述“像素密度”表示单位面积内的重复单元或子像素的个数。例如，可以使用PPI来表示像素密度，PPI的含义为每单位面积的像素个数。类似地，表述“分布密度”表示单位面积内的部件(例如重复单元、子像素、隔垫物等)的个数。
图1是根据本公开的一些示例性实施例的显示装置的平面示意图，其中示意性示出了显示装置包括的显示基板的平面结构。图2是根据本公开的一些示例性实施例的显示装置沿图1中的线AA’截取的截面示意图。
例如，所述显示装置包括显示基板。所述显示基板可以为电致发光显示基板，例如OLED显示基板。
如图1所示，根据本公开实施例的显示装置包括显示基板100。该显示基板100包括显示区域，所述显示区域可以包括第一显示区域AA1和第二显示区域AA2。例如，第一显示区域AA1和第二显示区域AA2。例如，第二显示区域AA2至少部分围绕(例如，完全围绕)第一显示区域AA1。
如图2所示，所述显示基板100可以包括衬底基板1。传感器2可以设置到衬底基板1的位于第一显示区域AA1的背面(在图2中示出为下侧，例如显示时出光方向相反的一侧)，第一显示区域AA1可以满足传感器2对于光透过率的成像要求。
例如，第一显示区域AA1的透光率大于第二显示区域AA2的透光率。传感器2例如为图像传感器或红外传感器等。该传感器2配置为接收来自显示基板100的显示侧(图2中的上侧，例如，显示出光方向上，或，显示时人眼所在的方向)的光线， 从而可以进行图像拍摄、距离感知、光强感知等操作，这些光线例如透过第一显示区域AA1后照射到传感器上，从而被传感器感测。
需要说明的是，在图示的示例性实施例中，第二显示区域AA2完全围绕第一显示区域AA1，但是，本公开的实施例不局限于此。例如，在其它实施例中，第一显示区域AA1可以位于显示基板的上侧边缘的位置，例如，第一显示区域AA1的三侧被第二显示区域AA2包围，其上侧与显示基板的上侧平齐。再例如，第一显示区域AA1可以位于显示基板的上侧边缘的位置，并且沿显示基板的整个宽度布置。
例如，第一显示区域AA1的形状可以为圆形、椭圆形、多边形或矩形，第二显示区域AA2的形状可以为圆形、圆环形、椭圆形或矩形，但本公开的实施例不限于此。又例如，第一显示区域AA1和第二显示区域AA2的形状可以均为矩形、圆角矩形或者其它合适的形状。
在图1至图2所示的显示基板中，可以采用OLED显示技术。由于OLED显示基板具有广视角、高对比度、快响应、低功耗、可折叠、柔性等优势，在显示产品中得到越来越广泛地应用。随着OLED显示技术的发展和深入应用，对高屏占比显示屏的需求越来越强烈。在图1至图2所示的显示基板中，采用了屏下摄像头的方案。这样，可以消除notch区，避免在显示屏中挖孔，并且能够提高屏占比，具有较佳的视觉体验。
例如，所述显示基板可以包括衬底基板1以及设置在衬底基板1上的各个膜层。例如，所述显示基板还可以包括设置在衬底基板1上的驱动电路层、发光器件层和封装层。例如，图2中示意性地示出了驱动电路层3、发光器件层4和封装层5。驱动电路层3包括驱动电路结构，发光器件层4包括例如OLED的发光器件。所述驱动电路结构控制各个子像素的发光器件发光，以实现显示功能。该驱动电路结构包括薄膜晶体管、存储电容器以及各种信号线。所述各种信号线包括栅线、数据线、ELVDD电源线和ELVSS电源线等，以便为每个子像素中的像素驱动电路提供控制信号、数据信号、电源电压等各种信号。
例如，所述第一显示区域AA1可以对应屏下摄像头，即第一显示区域AA1可以为屏下摄像区。在本公开的实施例中，以所述显示基板100包括2个第一显示区域AA1为例进行描述。每一个所述第一显示区域AA1可以呈圆形、大致圆形、椭圆形、多边形等形状。2个第一显示区域AA1间隔设置，在2个第一显示区域AA1之间存在间隔区域SR。
例如，结合参照图1和图2，在图示的实施例中，可以设置2个传感器2分别对应两个子显示区域，以形成具有双摄像头结构的显示装置。但是，本公开的实施例不局限于此，在其他实施例中，可以设置更少(例如一个)或更多个子显示区域和传感器2。此外，还可以根据需要安装的所述硬件结构的形状确定所述子显示区域的形状，例如，各个子显示区域在衬底基板上的正投影可以具有下列形状的一种或多种：圆形、椭圆形、矩形、圆角矩形、正方形、菱形、梯形、多边形等形状以及这些形状的各种组合。
在本公开的实施例中，在显示基板中设置具有比正常显示区的透光率更高的透光率的显示区域，将例如摄像头等的硬件结构安装于所述显示区域中。这样，可以实现屏下摄像等功能，从而可以提高屏占比，实现全面屏的效果。
在相关技术中，为了使得设置有传感器2的显示区域(即上述第一显示区域AA1)中的透光率高于正常显示区域(即上述第二显示区域AA2)中的透光率，通常采用降低第一显示区域中的像素密度的方式，即，第一显示区域中的PPI小于第二显示区域中的PPI，例如，通常将第一显示区域中的PPI设置为第二显示区域中的PPI的二分之一以下。但是，这种降低PPI的方式会降低第一显示区域中的显示质量，与正常显示区域相比，第一显示区域中显示的画面在视觉上会出现明显的颗粒感。另外，在相关技术中，还通常将第一显示区域中像素的像素驱动电路设置在屏下摄像区之外，例如，将所述像素驱动电路设置在上述间隔区域SR中，在这种情况下，在显示时会导致两个传感器2之间的显示区域中存在黑边，对整体显示质量带来不良的影响。此外，在像素驱动电路设置在屏下摄像区之外时，必须通过导电引线将设置在外的像素驱动电路与设置在屏下摄像区内的各个像素的发光元件(例如OLED)电连接，由于像素之间间距以及导电引线的线宽、线距的限制，屏下摄像区实现高PPI会受到限制，即无法实现高PPI的屏下摄像区。
本公开的实施例至少提供一种显示基板、显示面板和显示装置。所述显示基板包括第一显示区域和第二显示区域，所述第一显示区域的透光率大于所述第二显示区域的透光率，所述显示基板包括：衬底基板；设置于所述衬底基板且位于所述第一显示区域中的多个子像素，所述子像素包括第一像素驱动电路和第一发光器件，所述第一像素驱动电路与所述第一发光器件电连接，用于驱动所述第一发光器件发光；和设置于所述衬底基板且位于所述第二显示区域中的多个子像素，位于所述第二显示区域中的子像素包括第二像素驱动电路和第二发光器件，所述第二像素驱动电路与所述第二 发光器件电连接，用于驱动所述第二发光器件发光，其中，位于所述第一显示区域中的多个子像素包括多个子像素组，每一个子像素组包括第一子像素和第二子像素，所述第一像素驱动电路包括第一子像素驱动电路和第二子像素驱动电路，所述第一子像素驱动电路用于驱动第一子像素的第一发光器件发光，所述第二子像素驱动电路用于驱动第二子像素的第一发光器件发光，所述第一子像素驱动电路至少包括第一复位晶体管，所述第二子像素驱动电路至少包括第二复位晶体管，所述第一子像素驱动电路的第一复位晶体管与所述第二子像素驱动电路的第二复位晶体管至少部分共用。在本公开的实施例中，在屏下摄像区，多个子像素可以共用复位晶体管的至少一部分，这样，有利于缩小一部分子像素对应的像素驱动电路的占用区域的面积，从而能够实现屏下摄像区的PPI较高，同时保证屏下摄像区的透光率满足要求。
图3是根据本公开的一些示例性实施例的显示基板在图1中的部分I处的局部放大图。图4是根据本公开的一些示例性实施例的显示基板在图3中的部分II处的局部放大图。图5是根据本公开的一些示例性实施例的显示基板在图4中的部分III处的局部放大图。
结合参照图1至图5，所述显示基板可以包括第一显示区域AA1和第二显示区域AA2，第一显示区域AA1的透光率高于第二显示区域AA2的透光率，第一显示区域AA1可以与所述传感器2对应，即，传感器2在衬底基板1上的正投影落入所述第一显示区域AA1在衬底基板1上的正投影内。
图6A是根据本公开的一些示例性实施例的显示基板的一个像素驱动电路的等效电路图。图7是示出根据本公开的一些示例性实施例的显示基板的第二显示区域AA2中的子像素的示例性实施方式的平面图，其中示意性示出了第二显示区域AA2中的一个重复单元的平面图。图8是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层的平面图。图9是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层和第一导电层的组合的平面图。图10是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层、第一导电层和第二导电层的组合的平面图。图11是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层、第一导电层、第二导电层和第三导电层的组合的平面图。图12A和图12B分别是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层、第一导电层、第二导电层、第三导电层和第四导电层的组合的平面图。图13是示出图7中一个重复单元包括的子像素的示例性实施方式的半导体层、第一导电层、第二导电层、第三导电层、第四导 电层和第五导电层的组合的平面图。图14A是示出根据本公开的一些示例性实施例的显示基板的沿图12B中的线BB’截取的截面结构的示意图。图14B是示出根据本公开的一些示例性实施例的显示基板的沿图13中的线CC’截取的截面结构的示意图。
结合参照图1至图7，在本公开的实施例中，在第一显示区域AA1中，可以设置多个像素。多个像素可以沿第一方向X和第二方向Y成阵列地布置在衬底基板1上。例如，所述多个像素中的每一个可以包括子像素11、子像素12和子像素13。为了方便理解，可以将子像素11、子像素12和子像素13分别描述为红色子像素、蓝色子像素和绿色子像素，但是，本公开的实施例不局限于此。
在第二显示区域AA2中，可以设置多个像素。多个像素可以沿第一方向X和第二方向Y成阵列地布置在衬底基板1上。例如，所述多个像素20中的每一个可以包括子像素21、子像素22和子像素23。为了方便理解，可以将子像素21、子像素22和子像素23分别描述为红色子像素、蓝色子像素和绿色子像素，但是，本公开的实施例不局限于此。
在本公开的实施例中，第二显示区域AA2中可以设置有阵列排布的多个重复单元，在本文中，为了方便描述，将位于第二显示区域AA2中的重复单元称为第二重复单元P2。在一些实施例中，一个第二重复单元P2可以包括至少一个像素，例如，在图7所示的实施例中，一个第二重复单元P2包括2个像素。相应地，一个第二重复单元P2可以包括多个子像素，例如上述的子像素21、子像素22和子像素23。
在本公开的实施例中，第一显示区域AA1中设置有阵列排布的多个重复单元，在本文中，为了方便描述，将位于第一显示区域AA1中的重复单元称为第一重复单元P1。在一些实施例中，一个第一重复单元P1可以包括至少一个像素，例如，在一些实施例中，一个第一重复单元P1包括2个像素。相应地，一个第一重复单元P1可以包括多个子像素，例如上述的子像素11、子像素12和子像素13。
需要说明的是，以红色、绿色和蓝色为例对本公开的实施例进行说明，但是，本公开实施例不局限于此，也就是说，每一个重复单元可以包括至少两种不同颜色的子像素，例如第一颜色子像素、第二颜色子像素和第三颜色子像素，第一颜色、第二颜色和第三颜色为彼此不同的颜色。在本公开的一些实施例中，每一个重复单元中的子像素的排布方式可以参考常规的像素排布方式，例如GGRB、RGBG、RGB等，本公开的实施例对此不作限制。
应该理解，在本公开的实施例中，位于第一显示区域AA1和第二显示区域AA2 中的子像素可以包括像素驱动电路和发光器件。例如，所述发光器件可以为OLED发光器件，包括层叠设置的阳极、有机发光层和阴极。所述像素驱动电路可以包括多个薄膜晶体管和至少一个存储电容器。
需要说明的是，虽然在图示的实施例中，第一方向X和第二方向Y相互垂直，但是，本公开的实施例不局限于此。
下面，以7T1C像素驱动电路为例，对位于第一显示区域AA1和第二显示区域AA2中的子像素的所述像素驱动电路的结构进行详细描述，但是，本公开的实施例并不局限于7T1C像素驱动电路，在不冲突的情况下，其它已知的像素驱动电路结构都可以应用于本公开的实施例中。
应该理解，在本公开的实施例中，结合参照图13和图14B，显示基板100还包括位于第一电极(例如阳极)远离像素驱动电路一侧的像素界定层PDL，像素界定层PDL包括多个开口，各个子像素对应至少一个像素界定层开口(例如一个)，子像素的实际发光区域或显示区域与该子像素对应的像素界定层开口大致相当。在一些实施例中，各个子像素对应的像素界定层开口或者实际发光区域面积小于第一电极(例如阳极)的面积，且在衬底基板上的投影完全落入第一电极在衬底基板投影之内。为了方便示意，在本公开的实施例中，都仅示出了子像素的第一电极(例如阳极)的大概位置和形状，以表示各个子像素的分布。
结合参照图7、图13和图14B，位于第二显示区域AA2中的每一个子像素可以包括发光器件(例如OLED)，为了方便描述，将位于第二显示区域AA2中的发光器件称为第二发光器件42。例如，第二发光器件42可以包括层叠设置的阳极42A、发光材料层42B和阴极42C。需要说明的是，为清楚起见，在平面图中使用了第二发光器件42的阳极来示意性的示出第二发光器件42，从而示意性地表示位于第二显示区域AA2中的子像素。例如，在第二显示区域AA2中，第二发光器件42的阳极42A可以包括阳极主体421和阳极连接部422。阳极主体421在衬底基板1上的正投影可以具有规则形状，例如圆形、椭圆形、矩形、六边形、八边形、圆角矩形等。第二显示区域AA2中还设置有用于驱动所述第二发光器件42的像素驱动电路(将在下文描述)，阳极连接部422与第二发光器件42的像素驱动电路电连接。
例如，参照图7，第二重复单元P2可以包括以4行4列排布的多个子像素。在第一行中，子像素21和子像素22分别设置在第一列和第三列。在第二行中，两个子像素23分别设置在第二列和第四列。在第三行中，子像素22和子像素21分别设置在第 一列和第三列。在第四行中，两个子像素23分别设置在第二列和第四列。
需要说明的是，图7中示出的子像素的排布方式仅是本公开的一些实施例的示例性排布方式，而不是对本公开实施例的限制，在其他实施例中，子像素可以采用其他排布方式。
例如，在本公开的一些实施例中，参照图7，一个子像素21的阳极主体部421在衬底基板1上的正投影的面积小于一个子像素22的阳极主体部421在衬底基板1上的正投影的面积，一个子像素23的阳极主体部421在衬底基板1上的正投影的面积小于一个子像素21的阳极主体部421在衬底基板1上的正投影的面积。即，一个绿色子像素的实际发光面积最小，一个蓝色子像素的实际发光面积最大，一个红色子像素的实际发光面积介于绿色子像素和蓝色子像素之间。
结合参照图6A、图7至图14B，所述像素驱动电路可以包括：多个薄膜晶体管以及一个存储电容器Cst。所述像素驱动电路用于驱动有机发光二极管(即OLED)。多个薄膜晶体管包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7。每一个晶体管均包括栅极、源极和漏极。
所述显示基板还可以包括多根信号线，例如，所述多根信号线包括：用于传输扫描信号Sn的扫描信号线61，用于传输复位控制信号RESET(例如，该复位控制信号RESET可以为前一行的扫描信号)的复位信号线62，用于传输发光控制信号En的发光控制线63，用于传输数据信号Dm的数据信号线64，用于传输驱动电压VDD的驱动电压线65，用于传输初始化电压Vint的初始化电压线66，以及用于传输VSS电压的电源线67。
存储电容器Cst可以包括两个电容极板Cst1和Cst2，在本文中，电容极板Cst1可以称为存储电容器Cst的一端、第一端或第一存储电容电极，电容极板Cst2可以称为存储电容器Cst的另一端、第二端或第二存储电容电极。
第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7可沿着如图8中的有源层形成。有源层可具有弯曲或弯折形状，并且可包括对应于第一晶体管T1的第一有源层20a、对应于第二晶体管T2的第二有源层20b、对应于第三晶体管T3的第三有源层20c、对应于第四晶体管T4的第四有源层20d、对应于第五晶体管T5的第五有源层20e、对应于第六晶体管T6的第六有源层20f以及对应于第七晶体管T7的第七有源层20g。
有源层可以包括例如多晶硅，并且例如包括沟道区、源极区和漏极区。沟道区可不进行掺杂或掺杂类型与源极区、漏极区不同，并因此具有半导体特性。源极区和漏极区分别位于沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可根据TFT是N型还是P型晶体管而变化。
第一晶体管T1包括第一有源层20a以及第一栅极G1。第一有源层20a包括第一沟道区201a、第一源极区203a和第一漏极区205a。第一晶体管T1的栅极G1电连接至复位信号线62，第一晶体管T1的源极S1电连接至初始化电压线66。第一晶体管T1的漏极D1与存储电容器Cst的一端Cst1、第二晶体管T2的漏极D2以及第三晶体管T3的栅极G3电连接。如图6A所示，第一晶体管T1的漏极D1、存储电容器Cst的一端Cst1、第二晶体管T2的漏极D2以及第三晶体管T3的栅极G3电连接于节点N1处。第一晶体管T1根据通过复位信号线62传输的复位控制信号RESET导通，以将初始化电压Vint传输至第三晶体管T3的栅极G1，从而执行初始化操作来将第三晶体管T3的栅极G3的电压初始化。即，在本文中，第一晶体管T1也称为复位晶体管。
第二晶体管T2包括第二有源层20b和第二栅极G2。第二有源层20b包括第二沟道区201b、第二源极区203b以及第二漏极区205b。第二晶体管T2的栅极G2电连接至扫描信号线61，第二晶体管T2的源极S2电连接于节点N3，并且第二晶体管T2的漏极D2电连接于节点N1。第二晶体管T2根据通过扫描信号线61传输的扫描信号Sn导通，以将第三晶体管T3的栅极G3和漏极D3彼此电连接，从而执行第三晶体管T3的二极管连接。在本文中，第二晶体管T2也称为补偿晶体管。
第三晶体管T3包括第三有源层20c和第三栅极G3。第三有源层20c包括第三源极区203c、第三漏极区205c以及连接第三源极区203c和第三漏极区205c的第三沟道区201c。第三源极区203c和第三漏极区205c相对于第三沟道区201c在相对的两个方向上延伸。第三晶体管T3的第三源极区203c连接至第四漏极区205d和第五漏极区205e。第三漏极区205c连接至第二源极区203b和第六源极区203f。第三晶体管T3的栅极G3通过过孔VAH1和VAH2以及第一连接部68电连接于节点N1处。第三晶体管T3的栅极G3电连接至节点N1，第三晶体管T3的源极S3电连接至节点N2，第三晶体管T3的漏极D3电连接至节点N3。第三晶体管T3根据第四晶体管T4的开关操作接收数据信号Dm，以向OLED供应驱动电流Id。在本文中，第三晶体管T3也称为驱动晶体管。
第四晶体管T4包括第四有源层20d和第四栅极G4。第四有源层20d包括第四沟 道区201d、第四源极区203d和第四漏极区205d。第四晶体管T4用作选择发光目标子像素的开关装置。第四栅极G4连接至扫描信号线61，第四源极区203d通过过孔VAH4连接至数据信号线64，并且第四漏极区205d连接至第一晶体管T1和第五晶体管T5，即电连接至节点N2。第四晶体管T4根据通过扫描信号线61传输的扫描信号Sn导通，以执行开关操作来将数据信号Dm传输至第三晶体管T3的源极S3。在本文中，第四晶体管T4也称为开关晶体管。
第五晶体管T5包括第五有源层20e和第五栅极G5。第五有源层20e包括第五沟道区201e、第五源极区203e和第五漏极区205e。第五源极区203e可通过过孔VAH6连接至驱动电压线65。第五晶体管T5的栅极G5电连接至发光控制线63，第五晶体管T5的源极S5电连接至驱动电压线65。第五晶体管T5的漏极D5电连接至节点N2。在本文中，第五晶体管T5也称为操作控制晶体管。
第六晶体管T6包括第六有源层20f和第六栅极G6，并且第六有源层20f包括第六沟道区201f、第六源极区203f和第六漏极区205f。第六漏极区205f可通过过孔VAH7连接至OLED的阳极。第六晶体管T6的栅极G6电连接至发光控制线63，第六晶体管T6的源极S6电连接至节点N3，并且第六晶体管T6的漏极D6电连接至节点N4，即电连接至OLED的阳极。第五晶体管T5和第六晶体管T6根据通过发光控制线63传输的发光控制信号En并发(例如同时)导通，以将驱动电压VDD传输至OLED，从而允许驱动电流Id流进OLED中。在本文中，第六晶体管T6也称为发光控制晶体管。
第七晶体管T7包括第七有源层20g和第七栅极G7。第七有源层20g包括第七源极区203g、第七漏极区205g和第七沟道区201g。第七漏极区205g连接至第一晶体管T1的第一源极区203a。第七漏极区205g可通过过孔VAH8、第二连接部69和过孔VAH5电连接至初始化电压线66。第七晶体管T7的栅极G7电连接至复位信号线62，第七晶体管T7的源极S7电连接至节点N4，并且第七晶体管T7的漏极D7电连接至初始化电压线66。在第七晶体管T7的控制下，可以将初始化电压线66传输的初始化电压Vint供应给OLED，例如，供应给OLED的第一电极(例如阳极)，以初始化OLED的第一电极上的电压。在本文中，第七晶体管T7也可以称为初始化晶体管T7。
存储电容器Cst的一端(下文称为第一存储电容电极)Cst1电连接至节点N1，另一端(下文称为第二存储电容电极)Cst2电连接至驱动电压线65。
OLED的阳极电连接至节点N4，阴极电连接至电源线67，以接收公共电压VSS。 相应地，OLED从第三晶体管T3接收驱动电流Id来发光，从而显示图像。
需要说明的是，在图6A中，各个薄膜晶体管T1、T2、T3、T4、T5、T6和T7是p沟道场效应晶体管，但是，本公开的实施例不局限于此，薄膜晶体管T1、T2、T3、T4、T5、T6和T7中的至少一些可以是n沟道场效应晶体管。
在操作中，在初始化阶段，具有低电平的复位控制信号RESET通过复位信号线62供应。随后，第一晶体管T1基于复位控制信号RESET的低电平导通，并且来自初始化电压线66的初始化电压Vint通过第一晶体管T1传送至第三晶体管T3的栅极G1。因此，第三晶体管T3由于初始化电压Vint而被初始化。
在数据编程阶段，具有低电平的扫描信号Sn通过扫描信号线61供应。随后，第四晶体管T4和第二晶体管T2基于扫描信号Sn的低电平导通。因此，第三晶体管T3通过导通的第二晶体管T2被置于二极管连接状态并且在正方向上偏置。
随后，通过从经由数据信号线64供应的数据信号Dm中减去第三晶体管T3的阈值电压Vth获得的补偿电压Dm+Vth(例如，Vth是负值)施加至第三晶体管T3的栅极G3。随后，驱动电压VDD和补偿电压Dm+Vth施加至存储电容器Cst的两个端子，使得与相应端子之间的电压差对应的电荷存储在存储电容器Cst中。
在发光阶段，来自发光控制线63的发光控制信号En从高电平变为低电平。随后，在发光阶段，第五晶体管T5和第六晶体管T6基于发光控制信号En的低电平导通。
随后，基于第三晶体管T3的栅极G3的电压与驱动电压VDD之间的差生成驱动电流。与驱动电流和旁路电流之间的差对应的驱动电流Id通过第六晶体管T6供应给OLED。
在发光阶段，基于第三晶体管T3的电流-电压关系，第三晶体管T3的栅源电压由于存储电容器Cst而保持在(Dm+Vth)-VDD处。驱动电流Id与(Dm-VDD) 2成比例。因此，驱动电流Id可以不受第三晶体管T3的阈值电压Vth变动的影响。
结合参照图7至图14B，所述显示基板包括衬底基板1以及设置于所述衬底基板1上的多个膜层。在一些实施例中，所述多个膜层至少包括半导体层20、第一导电层21、第二导电层22、第三导电层23和第四导电层24。半导体层20、第一导电层21、第二导电层22和第三导电层23依次远离衬底基板1设置。所述多个膜层还至少包括多个绝缘膜层，例如，所述多个绝缘膜层可以包括第一栅绝缘层GI1、第二栅绝缘层GI2、层间绝缘层IDL和钝化层PVX。第一栅绝缘层GI1可以设置在半导体层20与第一导电层21之间，第二栅绝缘层GI2可以设置在第一导电层21与第二导电层22之间， 层间绝缘层IDL可以设置在第二导电层22与第三导电层23之间，钝化层PVX可以设置在第三导电层23与第四导电层24之间。
例如，半导体层20可以由诸如低温多晶硅的半导体材料形成，其膜层厚度可以在400～800埃的范围内，例如500埃。第一导电层21和第二导电层22可以由形成薄膜晶体管的栅极的导电材料形成，例如该导电材料可以为Mo，其膜层厚度可以在2000～4000埃的范围内，例如3000埃。第三导电层23和第四导电层24可以由形成薄膜晶体管的源极和漏极的导电材料形成，例如该导电材料可以包括Ti、Al等，第三导电层23可以具有由Ti/Al/Ti形成的叠层结构，其膜层厚度可以在6000～9000埃的范围内。例如，在第三导电层23或第四导电层24具有由Ti/Al/Ti形成的叠层结构的情况下，Ti/Al/Ti每一层的厚度可以分别为约500埃、6000埃和500埃。例如，第一栅绝缘层GI1和第二栅绝缘层GI2可以由氧化硅、氮化硅或氮氧化硅形成，每一层可以具有约1000～2000埃的厚度。例如，层间绝缘层IDL和钝化层PVX可以由氧化硅、氮化硅或氮氧化硅形成，具有约3000～6000埃的厚度。
所述显示基板包括沿着行方向X布置以向各个子像素分别施加扫描信号Sn、复位控制信号RESET、发光控制信号En和初始化电压Vint的扫描信号线61、复位信号线62、发光控制线63和初始化电压线66。所述显示基板还可以包括与扫描信号线61、复位信号线62、发光控制线63和初始化电压线66交叉以向各个子像素分别施加数据信号Dm和驱动电压VDD的数据信号线64以及驱动电压线65。
结合参照图9、图12A和图12B，扫描信号线61、复位信号线62和发光控制线63均位于第一导电层21中。上述各个晶体管的栅极G1～G7也均位于第一导电层21中。例如，复位信号线62与半导体层20重叠的部分分别形成第一晶体管T1的栅极G1和第七晶体管T7的栅极G7，扫描信号线61与半导体层20重叠的部分分别形成第二晶体管T2的栅极G2和第四晶体管T4的栅极G4，发光控制线63与半导体层20重叠的部分分别形成第六晶体管T6的栅极G6和第五晶体管T5的栅极G5。
继续参照图9，所述显示基板还可以包括多个第一存储电容电极Cst1。所述多个第一存储电容电极Cst1也位于第一导电层21中。第一存储电容电极Cst1与半导体层20重叠的部分形成第三晶体管T3的第三栅极G3。第一存储电容电极Cst1也形成存储电容器Cst的一个端子。即，第一存储电容电极Cst1同时用作第三晶体管T3的栅极G3和存储电容器Cst的一个电极。
例如，第一存储电容电极Cst1在衬底基板1上的正投影可以呈大致矩形形状。此 处的“大致矩形”可以包括矩形，至少一个角为圆角的矩形，至少一个角为倒角的矩形等形状。
如图10所示，初始化电压线66位于第二导电层22中。所述显示基板还可以包括多个第二存储电容电极Cst2。所述多个第二存储电容电极Cst2也位于第二导电层22中。多个第二存储电容电极Cst2分别与多个第一存储电容电极Cst1对应设置。即，多个第二存储电容电极Cst2在衬底基板1上的正投影与对应的第一存储电容电极Cst1在衬底基板1上的正投影至少部分重叠。第二存储电容电极Cst2形成存储电容器Cst的另一个端子。即，第一存储电容电极Cst1和第二存储电容电极Cst2相对设置，二者在衬底基板1上的正投影彼此至少部分重叠，并且它们之间设置有第二栅绝缘层GI2。例如，第一存储电容电极Cst1可以通过过孔VAH1和VAH2以及第一连接部68电连接于节点N1处，第二存储电容电极Cst2可以通过过孔VAH9电连接至驱动电压线65，即二者连接至不同的电压信号。这样，第一存储电容电极Cst1和第二存储电容电极Cst2彼此重叠的部分可以形成所述存储电容器Cst。
结合参照图10、图12和图14A，第二存储电容电极Cst2可以包括通孔TH2，以便于位于第二存储电容电极Cst2下方的第一存储电容电极Cst1与位于第三导电层23中的部件的电连接。例如，第一连接部68的一部分形成于过孔VAH1中，以形成导电插塞681。该导电插塞681延伸通过通孔TH2，与第一存储电容电极Cst1电连接。以此方式，第一连接部68的一端与存储电容器的一端Cst1电连接。
例如，通孔TH2在衬底基板1上的正投影可以呈大致矩形形状。此处的“大致矩形”可以包括矩形或正方形，至少一个角为圆角的矩形或正方形，至少一个角为倒角的矩形或正方形等形状。
参照图11，数据信号线64以及驱动电压线65位于第三导电层23中。另外，第一连接部68和第二连接部69也位于第三导电层23中。
参照图12A、图12B和图13，第三连接部70位于第四导电层24中。第三连接部70的一端电连接至第六晶体管T6，另一端电连接至OLED的阳极。
参照图13和图14B，所述显示基板100还可以包括设置在第四导电层24与第五导电层25之间的绝缘层，例如平坦化层PLN。例如，平坦化层PLN可以包括单个膜层或多个膜层。在平坦化层PLN包括多个膜层的情况下，平坦化层PLN的多个膜层可以分别表示为第一平坦化层PLN1、第二平坦化层PLN2和第三平坦化层PLN3。过孔VAH10可以贯穿该平坦化层PLN。第二发光器件42的阳极42A位于第五导电层25 中。阳极连接部422的一部分形成于过孔VAH10中，该部分向下延伸以与第三连接部10的一部分电连接。
这样，第三连接部70的一端通过过孔VAH7与第六晶体管T6电连接，第三连接部70的另一端通过过孔VAH10与阳极连接部422电连接。为了满足预设的PPI的要求，显示基板上的各个子像素需要按照规定的方式排列，这样，各个子像素中的第三连接部70的延伸长度可以相等或不相等。
例如，参照图7、图12A和图12B，其中，图12A示出了所述子像素21或子像素22的像素驱动电路的平面图，图12B示出了所述子像素23的像素驱动电路的平面图。在本公开的实施例中，子像素23中的第三连接部70的延伸长度可以小于子像素21或子像素22中的第三连接部70的延伸长度。
图6B是根据本公开的一些示例性实施例的显示基板的位于第一显示区域中的一个子像素组的像素驱动电路的等效电路图。图15是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素的示例性实施方式的平面图，其中示意性示出了第一显示区域AA1中的一个重复单元的平面图。图16A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的半导体层的平面图。图16B是示出图16A中所示的半导体层在复位晶体管处的局部放大图。图17A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的第一导电层的平面图。图17B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的半导体层和第一导电层的组合的平面图。图18A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的第二导电层的平面图。图18B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的半导体层、第一导电层和第二导电层的组合的平面图。图19A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的第三导电层的平面图。图19B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的半导体层、第一导电层、第二导电层和第三导电层的组合的平面图。图20A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的第一透明导电层的平面图。图20B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的半导体层、第一导电层、第二导电层和第一透明导电层的组合的平面图。图21A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的第四 导电层的平面图。图20B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的半导体层、第一导电层、第二导电层、第一透明导电层和第四导电层的组合的平面图。图22A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的第二透明导电层的平面图。图22B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的半导体层、第一导电层、第二导电层、第一透明导电层、第四导电层和第二透明导电层的组合的平面图。图23A是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的第五导电层的平面图。图23B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的子像素组的半导体层、第一导电层、第二导电层、第一透明导电层、第四导电层、第二透明导电层和第五导电层的组合的平面图。图24A是示出根据本公开的一些示例性实施例的显示基板的沿图21B中的线DD’截取的截面结构的示意图。图24B是示出根据本公开的一些示例性实施例的显示基板的沿图23A中的线EE’截取的截面结构的示意图。
需要说明的是，在下面的描述中，主要说明位于第一显示区域AA1中的子像素的结构与位于第二显示区域AA2中的子像素的结构的不同之处，对于二者的相同之处，可以参照上文的描述。
还需要说明的是，为了使得本文的描述更简洁，在下文中，在第一显示区域和第二显示区域中具有相同或相似的功能和/或结构的元件可以使用相同的附图标记来表示，例如，位于第一显示区域中的各个晶体管、存储电容器、信号线可以分别使用与位于第二显示区域中的各个晶体管、存储电容器、信号线对应的附图标记表示。应该理解，在下文的描述中，这些元件和结构是位于第一显示区域AA1中的。
结合参照图6B、图15至图24B，在第一显示区域AA1中，所述子像素11、12、13的像素驱动电路可以包括：多个薄膜晶体管以及一个存储电容器Cst。所述像素驱动电路用于驱动有机发光二极管(即OLED)。多个薄膜晶体管包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7。每一个晶体管均包括栅极、源极和漏极。
所述多根信号线包括：用于传输扫描信号Sn的扫描信号线61，用于传输复位控制信号RESET(例如，该复位控制信号RESET可以为前一行的扫描信号)的复位信号线62，用于传输发光控制信号En的发光控制线63，用于传输数据信号Dm的数据信号线164，用于传输驱动电压VDD的驱动电压线165，用于传输初始化电压Vint的 初始化电压线66，以及用于传输VSS电压的电源线67。
应该理解，与上述第二显示区域AA2类似，在本公开的实施例中，在第一显示区域AA1中，显示基板还包括位于第一电极远离像素驱动电路一侧的像素界定层，像素界定层包括多个开口，各个子像素对应至少一个(例如一个)像素界定层开口，子像素的实际发光区域或显示区域与该子像素对应的像素界定层开口大致相当。在一些实施例中，各个子像素对应的像素界定层开口或者实际发光区域面积小于第一电极(例如阳极)的面积，且在衬底基板上的投影完全落入第一电极在衬底基板投影之内。
如图15以及图23A～图23B所示，位于第一显示区域AA1中的每一个子像素可以包括发光器件(例如OLED)，为了方便描述，将位于第一显示区域AA1中的发光器件称为第一发光器件41。例如，第一发光器件41可以包括层叠设置的阳极41A(参照图24B)、发光材料层和阴极。需要说明的是，为清楚起见，相关附图使用了第一发光器件41的阳极来示意性的示出第一发光器件41，从而示意性地表示位于第一显示区域AA1中的子像素。例如，在第一显示区域AA1中，第一发光器件41的阳极包括阳极主体411和阳极连接部412。阳极主体411在衬底基板1上的正投影可以具有规则形状，例如圆形、椭圆形、矩形、六边形、八边形、圆角矩形等。第一显示区域AA1中还设置有用于驱动所述第一发光器件41的像素驱动电路(将在下文描述)，阳极连接部412与第一发光器件41的像素驱动电路电连接。
参照图15，示意性示出了像素界定层开口和阳极。与阳极主体一致，开口OPH在衬底基板1上的正投影可以具有规则形状，例如圆形、椭圆形、矩形、六边形、八边形、圆角矩形等。开口OPH在衬底基板1上的投影完全落入阳极主体411在衬底基板1的投影之内。
需要说明的是，为了方便示意，在本公开的实施例中，主要示出了子像素的第一电极(例如阳极)的大概位置和形状，以表示各个子像素的分布。
例如，在本公开的一些实施例中，每一个重复单元中的子像素的排布方式可以参考常规的像素排布方式，例如GGRB、RGBG、RGB等，本公开的实施例对此不作限制。
与第二重复单元P2类似，参照图15，第一重复单元P1可以包括以4行4列排布的多个子像素。在第一行中，子像素11和子像素12分别设置在第一列和第三列。在第二行中，两个子像素13分别设置在第二列和第四列。在第三行中，子像素12和子像素11分别设置在第一列和第三列。在第四行中，两个子像素13分别设置在第二列 和第四列。
需要说明的是，图15中示出的子像素的排布方式仅是本公开的一些实施例的示例性排布方式，而不是对本公开实施例的限制，在其他实施例中，子像素可以采用其他排布方式。
参照图6B、图15至图23B，在本公开的实施例中，所述显示基板可以包括位于所述第一显示区域AA1中的多个子像素组，例如，一个子像素组可以包括至少两个子像素。为了描述方便，将所述至少两个子像素中的两个子像素分别称为第一子像素和第二子像素。例如，所述第一子像素可以是上述子像素11、12和13中的一个，所述第二子像素可以是上述子像素11、12和13中不同于所述第一子像素的一个。例如，所述第一子像素和所述第二子像素可以是不同颜色的子像素。
例如，在本公开的一些实施例中，参照图15，一个子像素11的阳极主体部421在衬底基板1上的正投影的面积小于一个子像素12的阳极主体部421在衬底基板1上的正投影的面积，一个子像素13的阳极主体部421在衬底基板1上的正投影的面积小于一个子像素11的阳极主体部421在衬底基板1上的正投影的面积。即，一个绿色子像素的实际发光面积最小，一个蓝色子像素的实际发光面积最大，一个红色子像素的实际发光面积介于绿色子像素和蓝色子像素之间。
在本公开的实施例中，在一个子像素组中，所述第一子像素可以是红色子像素和蓝色子像素中的一个，所述第二子像素可以是绿色子像素。这样，在下文中，以所述第一子像素为子像素11或子像素12以及所述第二子像素为子像素13为例，对本公开的一些示例性实施方式进行描述。
需要说明的是，图15至图23B示出了位于第一显示区域AA1中的一个子像素组的平面图，其中，在各个平面图中，左上侧的图为所述第一子像素11(12)的平面图，右下侧的图为所述第二子像素13的平面图。
参照图6B，在一个子像素组的等效电路图中，设置有第一子像素驱动电路和第二子像素驱动电路。示意性地，图6B中左侧的虚线框示出了第一子像素驱动电路DR1，图6B中右侧的点划线框示出了第二子像素驱动电路DR2。第一子像素驱动电路DR1用于驱动所述第一子像素11(12)的第一发光器件41发光。第二子像素驱动电路DR2用于驱动所述第二子像素13的第一发光器件41发光。
与图6A的一个子像素的像素驱动电路类似，所述第一子像素驱动电路DR1和所述第二子像素驱动电路DR2中的每一个可以包括：多个薄膜晶体管以及一个存储电容 器Cst。例如，所述多个薄膜晶体管可以包括第一晶体管(也称为复位晶体管)T1、第二晶体管(也称为补偿晶体管)T2、第三晶体管(也称为驱动晶体管)T3、第四晶体管(也称为开关晶体管)T4、第五晶体管(也称为操作控制晶体管)T5、第六晶体管(也称为发光控制晶体管)T6和第七晶体管(也称为初始化晶体管)T7。每一个晶体管均包括栅极、源极和漏极。
在本公开的实施例中，为了描述方便，将第一子像素驱动电路DR1包括的多个薄膜晶体管T1～T7分别称为第一复位晶体管T1、第一补偿晶体管T2、第一驱动晶体管T3、第一开关晶体管T4、第一操作控制晶体管T5、第一发光控制晶体管T6和第一初始化晶体管T7；将第二子像素驱动电路DR2包括的多个薄膜晶体管T1～T7分别称为第二复位晶体管T1’、第二补偿晶体管T2、第二驱动晶体管T3、第二开关晶体管T4、第二操作控制晶体管T5、第二发光控制晶体管T6和第二初始化晶体管T7。
在本公开的实施例中，所述第一子像素驱动电路DR1的第一复位晶体管T1与所述第二子像素驱动电路DR2的第二复位晶体管T1’至少部分共用。
需要说明的是，在本文中，“第一复位晶体管和第二复位晶体管至少部分共用”表示的意思是：第一复位晶体管和第二复位晶体管之间存在共用的部分，即，该部分既作为第一复位晶体管的一部分，在第一子像素驱动电路中发挥作用；又作为第二复位晶体管的一部分，在第二子像素驱动电路中发挥作用。
例如，结合参照图6B，所述第一复位晶体管可以包括共用晶体管T10和第一子晶体管T11，所述第二复位晶体管包括所述共用晶体管T10和第二子晶体管T12。这样，在该示例性实施例中，共用晶体管T10既作为所述第一复位晶体管的一部分，又作为所述第二复位晶体管的一部分，分别在第一子像素驱动电路DR1和第二子像素驱动电路DR2中发挥作用。
例如，继续参照图6B，所述共用晶体管T10、所述第一子晶体管T11和所述第二子晶体管T12中的每一个均包括栅极G1、源极S1和漏极D1，所述共用晶体管T10、所述第一子晶体管T11和所述第二子晶体管T12中的每一个的栅极均接入复位控制信号RESET，所述共用晶体管T10的源极或漏极中的一个接入初始化电压信号Vint，所述共用晶体管T10的源极或漏极中的另一个分别与所述第一子晶体管T11和所述第二子晶体管T12电连接。
在本公开的实施例中，在屏下摄像区，多个子像素的像素驱动电路可以共用复位晶体管的至少一部分，这样，有利于缩小一些子像素对应的像素驱动电路的占用区域 的面积，从而能够实现屏下摄像区的PPI较高，同时保证屏下摄像区的透光率满足要求。
结合参照图15至图24B，所述显示基板包括衬底基板1以及设置于所述衬底基板1上的多个膜层。在一些实施例中，所述多个膜层至少包括半导体层20、第一导电层21、第二导电层22、第三导电层23、第一透明导电层26、第四导电层24、第二透明导电层28和第五导电层25。半导体层20、第一导电层21、第二导电层22、第三导电层23、第一透明导电层26、第四导电层24、第二透明导电层28和第五导电层25依次远离衬底基板1设置。所述多个膜层还至少包括多个绝缘膜层，例如，所述多个绝缘膜层可以包括第一栅绝缘层GI1、第二栅绝缘层GI2、层间绝缘层IDL、钝化层PVX和平坦化层PLN。第一栅绝缘层GI1可以设置在半导体层20与第一导电层21之间，第二栅绝缘层GI2可以设置在第一导电层21与第二导电层22之间，层间绝缘层IDL可以设置在第二导电层22与第三导电层23之间，钝化层PVX可以设置在第三导电层23与第一透明导电层26之间。例如，平坦化层PLN可以包括多个膜层，为了方便描述，分别称为第一平坦化层PLN1、第二平坦化层PLN2和第三平坦化层PLN3。在一些实施例中，第一平坦化层PLN1可以设置在第一透明导电层26与第四导电层24之间，第二平坦化层PLN2可以设置在第四导电层24和第二透明导电层28之间，第三平坦化层PLN3可以设置在第二透明导电层28和第五导电层25之间。
在第一显示区域AA1中，各个子像素的像素驱动电路包括的复位晶体管T1、补偿晶体管T2、驱动晶体管T3、开关晶体管T4、操作控制晶体管T5、发光控制晶体管T6和初始化晶体管T7可沿着如图16A中的有源层形成。有源层可具有弯曲或弯折形状，并且可包括对应于复位晶体管T1的第一有源层20a、对应于晶体管T2的第二有源层20b、对应于驱动晶体管T3的第三有源层20c、对应于开关晶体管T4的第四有源层20d、对应于操作控制晶体管T5的第五有源层20e、对应于发光控制晶体管T6的第六有源层20f以及对应于初始化晶体管T7的第七有源层20g。
参照图16A，在一个子像素组中，第一子像素11(12)的第一子像素驱动电路DR1的第一复位晶体管T1、第一补偿晶体管T2、第一驱动晶体管T3、第一开关晶体管T4、第一操作控制晶体管T5和第一发光控制晶体管T6的有源层20a～20f形成为半导体层20的连续延伸的一部分；第二子像素13的第二子像素驱动电路DR2的第二补偿晶体管T2、第二驱动晶体管T3、第二开关晶体管T4、第二操作控制晶体管T5和第二发光控制晶体管T6的有源层20b～20f形成为半导体层20的连续延伸的一部分。
需要说明的是，在本文中，“连续延伸”表述部件中间没有任何断开的地方。
在一个子像素组中，第一子像素11(12)的第一子像素驱动电路DR1的第一初始化晶体管T7的第七有源层20g与所述第一子像素驱动电路DR1位于所述半导体层20中的其他部分(即第一子像素驱动电路DR1的第一复位晶体管T1、第一补偿晶体管T2、第一驱动晶体管T3、第一开关晶体管T4、第一操作控制晶体管T5和第一发光控制晶体管T6的有源层20a～20f)间隔设置；第二子像素13的第二子像素驱动电路DR2的第二初始化晶体管T7的第七有源层20g与所述第二子像素驱动电路DR2位于所述半导体层20中的其他部分(即第二子像素驱动电路DR2的第二复位晶体管T1’、第二补偿晶体管T2、第二驱动晶体管T3、第二开关晶体管T4、第二操作控制晶体管T5和第二发光控制晶体管T6的有源层20a～20f)间隔设置。
在一个子像素组中，第一子像素11(12)的第一子像素驱动电路DR1的第一复位晶体管T1的有源层20a和第二子像素13的第二子像素驱动电路DR2的第二复位晶体管T1’的有源层20a至少部分共用。例如，参照图16B，共用晶体管T10包括共用有源层200a，该共用有源层200a包括共用沟道部分2010a、共用源极部分2030a和共用漏极部分2050a。第一子晶体管T11包括第一子有源层211a，该第一子有源层211a包括第一沟道部分2011a、第一子源极部分2031a和第一子漏极部分2051a。第二子晶体管T12包括第二子有源层212a，该第二子有源层212a包括第二沟道部分2012a、第二子源极部分2032a和第二子漏极部分2052a。所述共用源极部分2030a和所述共用漏极部分2050a分别位于所述共用沟道部分2010a的两侧，所述第一子源极部分2031a和所述第一子漏极部分2051a分别位于所述第一沟道部分2011a的两侧，所述第二子源极部分2032a和所述第二子漏极部分2052a分别位于所述第二沟道部分2012a的两侧。所述共用有源层200a、所述第一子有源层211a和第二子有源层212a连续延伸。例如，所述共用有源层200a的一端连接所述第一子有源层211a和第二子有源层212a两者。
在本公开的实施例中，共用有源层200a和第一子有源层211a构成第一子像素11(12)的第一子像素驱动电路DR1的第一复位晶体管T1的有源层20a。共用有源层200a和第二子有源层212a构成第二子像素13的第二子像素驱动电路DR2的第二复位晶体管T1’的有源层20a。即，第一复位晶体管T1的有源层20a和第二复位晶体管T1’的有源层20a至少存在共用的部分——共用有源层200a。
在本公开的实施例中，第二子像素驱动电路DR2的第二复位晶体管T1’的有源层20a形成在第一子像素驱动电路DR1的占用区域中，这样，有利于减小第二子像素驱 动电路DR2的占用区域的面积。
继续参照图16A，在第一子像素驱动电路DR1中，第一初始化晶体管T7的有源层20g与第一复位晶体管T1的有源层20a间隔设置。第一复位晶体管T1的有源层20a连接第一补偿晶体管T2的有源层20b，第一补偿晶体管T2的有源层20b连接第一驱动晶体管T3的有源层20c和第一发光控制晶体管T6的有源层20f，第一驱动晶体管T3的有源层20c连接第一开关晶体管T4的有源层20d和第一操作控制晶体管T5的有源层20e。即，所述共用有源层200a、所述第一子有源层211a和第二子有源层212a、第一补偿晶体管T2的有源层20b、第一驱动晶体管T3的有源层20c、第一发光控制晶体管T6的有源层20f、第一开关晶体管T4的有源层20d和第一操作控制晶体管T5的有源层20e连续延伸。第一初始化晶体管T7的有源层20g与这些有源层间隔设置。
在第二子像素驱动电路DR2中，第二补偿晶体管T2的有源层20b连接第二驱动晶体管T3的有源层20c和第二发光控制晶体管T6的有源层20f，第二驱动晶体管T3的有源层20c连接第二开关晶体管T4的有源层20d和第二操作控制晶体管T5的有源层20e。即，第二补偿晶体管T2的有源层20b、第二驱动晶体管T3的有源层20c、第二发光控制晶体管T6的有源层20f、第二开关晶体管T4的有源层20d和第二操作控制晶体管T5的有源层20e连续延伸。第二初始化晶体管T7的有源层20g与这些有源层间隔设置。
结合参照图8和图9，对于位于第二显示区域AA2中的一个子像素而言，第一初始化晶体管T7的有源层20g自第一复位晶体管T1的有源层20a沿远离该子像素的扫描信号线61的方向延伸，即，第一初始化晶体管T7的有源层20g位于第一复位晶体管T1的有源层20a的右上方。通过这样的设置方式，第一初始化晶体管T7的有源层20g可以朝向位于同一列的上方的相邻的子像素的有源层延伸，有利于位于同一列的子像素的有源层形成为连续延伸的结构。
参照图16A和图17，对于位于第一显示区域AA1中的子像素而言，第一初始化晶体管T7的有源层20g相对于第一复位晶体管T1的有源层20a沿靠近该子像素的扫描信号线61的方向延伸，即，第一初始化晶体管T7的有源层20g位于第一复位晶体管T1的有源层20a的右下方。通过这样的设置方式，位于第一显示区域AA1中的一个子像素的有源层的占用区域的轮廓为正方形或近似正方形。
在本文中，表述“占用区域”表示一个图案、层结构等在衬底基板上的正投影所覆盖的最大区域，具体地，一个图案、层结构等在衬底基板上的正投影具有在第一方 向X上相距最远的两个侧边以及在第二方向Y上相距最远的两个侧边，这四条侧边的延长线会交叉，以包围形成一个区域，该区域即为图案、层结构等的占用区域。
具体地，参照图8和图16A，对于位于第二显示区域AA2中的一个子像素而言，其有源层的占用区域具有矩形或大致矩形的形状，如图8所示，使用虚线框示意性示出了位于第二显示区域AA2中的一个子像素的有源层的占用区域，该占用区域具有沿第一方向X的尺寸(即宽度W2)和沿第二方向Y的尺寸(即长度L2)，其中，长度L2大于宽度W2，或者说，长度L2为宽度W2的1.2倍以上，即，该占用区域具有长方形的形状。
对于位于第一显示区域AA1中的一个子像素而言，其有源层的占用区域具有正方形或大致正方形的形状，如图16A所示，使用虚线框示意性示出了位于第一显示区域AA1中的一个子像素的有源层的占用区域，该占用区域具有沿第一方向X的尺寸(即宽度W1)和沿第二方向Y的尺寸(即长度L1)，其中，长度L1基本等于宽度W1。
在本公开的实施例中，位于第一显示区域AA1中的一个子像素的有源层的占用区域的面积小于位于第二显示区域AA2中的一个同颜色的子像素的有源层的占用区域的面积。这样，可以减小位于第一显示区域AA1中的子像素的像素驱动电路的占用区域的面积，关于这一点，下文将进一步详细描述。
类似地，如图17A和图17B所示，扫描信号线61、复位信号线62和发光控制线63均位于第一导电层21中。上述各个晶体管的栅极G1～G7也均位于第一导电层21中。第一存储电容电极Cst1也位于第一导电层21中。第一导电层21位于半导体层20远离衬底基板1的一侧。
参照图17A和图17B，所述第一子像素11(12)和所述第二子像素13共用一条复位信号线62。即，仅在第一子像素11(12)的第一子像素驱动电路DR1的占用区域中设置有复位信号线62，在第二子像素13的第二子像素驱动电路DR2的占用区域中不设置复位信号线62。即，在第一子像素11(12)的第一子像素驱动电路DR1的占用区域中，设置有扫描信号线61、复位信号线62和发光控制线63；在第二子像素13的第二子像素驱动电路DR2的占用区域中，设置有扫描信号线61和发光控制线63。
结合参照图6B和图17B，在第一子像素11(12)中，扫描信号线61与半导体层20重叠的部分分别形成第一补偿晶体管T2的栅极G2和第一开关晶体管T4的栅极G4，并且，扫描信号线61与半导体层20重叠的另一部分还形成第一初始化晶体管T7的栅极G7。也就是说，在本公开的实施例中，在第一显示区域AA1中，第一初始化 晶体管T7、第一补偿晶体管T2和第一开关晶体管T4的栅极均供应扫描信号Sn。
如上所述，在第一初始化晶体管T7的控制下，可以将初始化电压线66传输的初始化电压Vint供应给OLED，例如，供应给OLED的第一电极(例如阳极)，以初始化OLED的第一电极上的电压。
在第二子像素13中，扫描信号线61与半导体层20重叠的部分分别形成第二补偿晶体管T2的栅极G2和第二开关晶体管T4的栅极G4，并且，扫描信号线61与半导体层20重叠的另一部分还形成第二初始化晶体管T7的栅极G7。也就是说，在本公开的实施例中，在第一显示区域AA1中，第二初始化晶体管T7、第二补偿晶体管T2和第二开关晶体管T4的栅极均供应扫描信号Sn。
继续参照图17A，在一个子像素中，一条复位信号线62包括位于所述第一显示区域AA1中的第一部分621、第二部分622和第三部分623，所述第一部分621、所述第二部分622和所述第三部分623在所述衬底基板1上的正投影分别与所述共用沟道部分2010a、所述第一沟道部分2011a和所述第二沟道部分2012a在所述衬底基板1上的正投影重合，所述共用晶体管T10的栅极包括所述第一部分621，所述第一子晶体管T11的栅极包括所述第二部分622，所述第二子晶体管T12的栅极包括所述第三部分623。
例如，复位信号线62的第一部分621可以基本沿第二方向Y延伸，复位信号线62的第二部分622和第三部分623可以基本沿第一方向X延伸，即，复位信号线62的第一部分621基本垂直于复位信号线62的第二部分622和第三部分623。
以此方式，所述共用晶体管T10、所述第一子晶体管T11和所述第二子晶体管T12中的每一个的栅极均接入复位控制信号RESET。
这样，在本公开的实施例中，所述第一子像素驱动电路DR1的第一复位晶体管T1(包括共用晶体管T10和第一子晶体管T11)与所述第二子像素驱动电路DR2的第二复位晶体管T1’(包括共用晶体管T10和第二子晶体管T12)中每一个在所述衬底基板1上的正投影均落入所述第一子像素驱动电路DR1的占用区域在所述衬底基板1上的正投影内。以此方式，可以减少第二子像素的第二子像素驱动电路DR2的占用区域的面积。
需要说明的是，在此处，所述第一子像素驱动电路DR1的第一复位晶体管T1在所述衬底基板1上的正投影可以用所述第一子像素驱动电路DR1的第一复位晶体管T1的沟道区域在所述衬底基板1上的正投影表示；所述第二子像素驱动电路DR2的 第二复位晶体管T1’在所述衬底基板1上的正投影可以用所述第二子像素驱动电路DR2的第二复位晶体管T1’的沟道区域在所述衬底基板1上的正投影表示。
如图18A和图18B所示，初始化电压线66和第二存储电容电极Cst2位于第二导电层22中。第二导电层22位于第一导电层21远离衬底基板1的一侧。
参照图18A和图18B，所述第一子像素11(12)和所述第二子像素13共用一条初始化电压线66。即，仅在第一子像素11(12)的第一子像素驱动电路DR1的占用区域中设置有初始化电压线66，在第二子像素13的第二子像素驱动电路DR2的占用区域中不设置初始化电压线66。
参照图10，对于位于第二显示区域AA2中的一个子像素而言，第二存储电容电极Cst2包括通孔TH2，第二存储电容电极Cst2的实体部分和通孔TH2的组合在衬底基板1上的正投影呈矩形或圆角矩形的形状。
参照图18A和图18B，对于位于第一显示区域AA1中的一个子像素而言，第二存储电容电极Cst2在一个拐角处具有凹口NTH1，即，第二存储电容电极Cst2在衬底基板1上的正投影呈“L”形。换句话说，第二存储电容电极Cst2的实体部分和凹口NTH1的组合在衬底基板1上的正投影呈矩形或圆角矩形的形状。
凹口NTH1暴露位于第二存储电容电极Cst2下方的第一存储电容电极Cst1的一部分，以便第一存储电容电极Cst1与其他部分电连接。
在本公开的实施例中，位于第一显示区域AA1中的一个子像素的第二存储电容电极Cst2在衬底基板1上的正投影的面积比位于第二显示区域AA2中的一个子像素的第二存储电容电极Cst2在衬底基板1上的正投影的面积小。在此基础上，将位于第一显示区域AA1中的一个子像素的第二存储电容电极Cst2设计成“L”形，无需在第二存储电容电极Cst2中形成所述通孔，有利于保证位于第一显示区域AA1中的一个子像素的第一存储电容电极Cst1与第二存储电容电极Cst2的交叠面积较大，即，保证存储电容器Cst的电容值较大。
如图19A和图19B所示，连接部168、连接部169、连接部170和连接部171位于第三导电层23中。第三导电层23位于第二导电层22远离衬底基板1的一侧。
连接部168的一部分形成于过孔VH6中，该部分向下延伸以与凹口NTH1暴露的第一存储电容电极Cst1的部分电连接。连接部168的另一部分形成于过孔VH2中，该部分向下延伸以与第一补偿晶体管T2的漏极D2和第一复位晶体管T1的漏极D1电连接。通过连接部168，可以使得第一存储电容电极Cst1、第一补偿晶体管T2的漏 极D2和第一复位晶体管T1的漏极D1电连接，即形成图6B中所示的节点N1。
连接部169包括第一连接子部1691和第二连接子部1692。第一连接子部1691和第二连接子部1692彼此连接，以形成连续延伸的连接部169。第一连接子部1691的一部分形成于过孔VH12中，该部分向下延伸以与初始化电压线66电连接。第一连接子部1691的另一部分形成于过孔VH124中，该部分向下延伸以与共用晶体管T10的共用源极部分2030a和共用漏极部分2050a中的一个电连接。以此方式，将初始化电压线66与共用晶体管T10的源极或漏极电连接，可以将初始化电压线66传输的初始化电压Vint供应给第一子像素驱动电路DR1的第一复位晶体管T1的源极或漏极和第二子像素驱动电路DR2的第二复位晶体管T1’的源极或漏极。
第二连接子部1692的另一部分形成于过孔VH4中，该部分向下延伸以与第一初始化晶体管T7的漏极D7电连接。以此方式，可以将初始化电压线66传输的初始化电压Vint供应给第一初始化晶体管T7的漏极D7。
连接部170的一部分形成于过孔VH5中，该部分向下延伸以与第一初始化晶体管T7的源极S7电连接。连接部170的另一部分形成于过孔VH10中，该部分向下延伸以与第一发光控制晶体管T6的漏极D6电连接。通过连接部170，可以使得第一初始化晶体管T7的源极S7和第一发光控制晶体管T6的漏极D6电连接，即形成图6B中所示的N4节点。
连接部171的一部分形成于过孔VH7中，该部分向下延伸以与第二存储电容电极Cst2电连接。连接部171的另一部分形成于过孔VH9中，该部分向下延伸以与第一操作控制晶体管T5的源极S5电连接。通过连接部171，可以使得第二存储电容电极Cst2与第一操作控制晶体管T5的源极S5电连接。
继续参照图19A和图19B，在所述第二子像素13所在的区域中，连接部168’、连接部170’和连接部171’位于第三导电层23中。
连接部168’的一部分形成于过孔VH6’中，该部分向下延伸以与凹口NTH1暴露的第一存储电容电极Cst1的部分电连接。连接部168’的另一部分形成于过孔VH2’中，该部分向下延伸以与第二补偿晶体管T2的漏极D2电连接。通过连接部168’，可以使得第一存储电容电极Cst1和第二补偿晶体管T2的漏极D2电连接。
连接部170’的一部分形成于过孔VH5’中，该部分向下延伸以与第二初始化晶体管T7的源极S7电连接。连接部170’的另一部分形成于过孔VH10’中，该部分向下延伸以与第二发光控制晶体管T6的漏极D6电连接。通过连接部170’，可以使得第二初始 化晶体管T7的源极S7和第二发光控制晶体管T6的漏极D6电连接。
连接部171’的一部分形成于过孔VH7’中，该部分向下延伸以与第二存储电容电极Cst2电连接。连接部171’的另一部分形成于过孔VH9’中，该部分向下延伸以与第二操作控制晶体管T5的源极S5电连接。通过连接部171’，可以使得第二存储电容电极Cst2与第二操作控制晶体管T5的源极S5电连接。
结合参照图20A和图20B，在第一显示区域AA1中，设置有第一透明导电层26，例如，该第一透明导电层26可以由诸如氧化铟锡(即ITO)等的透明导电材料构成。
在第一显示区域AA1中，数据信号线164以及驱动电压线165位于第一透明导电层26中。即，数据信号线164以及驱动电压线165由诸如氧化铟锡(即ITO)等的透明导电材料构成。
所述显示基板还可以包括位于第一透明导电层26中的多个透明导电连接部。例如，所述多个透明导电连接部可以包括第一透明导电连接部161、第二透明导电连接部162、第三透明导电连接部163和第四透明导电连接部166。即，这些透明导电连接部均由诸如氧化铟锡(即ITO)等的透明导电材料构成。
所述显示基板还可以包括位于第一透明导电层26中的多个导电引线。例如，所述多个导电引线可以包括第三导电引线263和第四导电引线266。即，这些导电引线均由诸如氧化铟锡(即ITO)等的透明导电材料构成。
需要说明的是，在本文中，将用于电连接一个子像素组内的多个子像素的像素驱动电路中的元件的部件称为导电连接部，将用于电连接分别位于不同子像素组(例如相邻的子像素组)中的多个子像素的像素驱动电路中的元件的部件称为导电引线，这样的表述仅出于方便描述的目的，而不意图特别限制这些部件必须不同，例如，这些部件的一些特征可以是相同的，例如，这些部件中的至少一些可以位于同一导电层，例如，均位于第一透明导电层26中，或者，这些部件中的至少一些可以由相同的导电材料构成，例如，都由诸如氧化铟锡(即ITO)等的透明导电材料构成。
例如，数据线164可以基本沿第二方向Y连续延伸。数据信号线164的一部分形成于过孔VH3中，该部分向下延伸以与第一开关晶体管T4的源极S4电连接，从而将数据信号线164传输的数据信号Dm供应给第一开关晶体管T4。
驱动电压线165在第一显示区域AA1中的子像素的像素驱动电路处断开，分成两个部分。为了方便描述，将这两个部分分别表示为第一驱动电压子线1651和第二驱动电压子线1652。
例如，第一驱动电压子线1651在衬底基板1上的正投影与初始化电压线66在衬底基板1上的正投影交叉，并且第一驱动电压子线1651在衬底基板1上的正投影与复位信号线62在衬底基板1上的正投影至少部分重叠。
再例如，第二驱动电压子线1652在衬底基板1上的正投影与发光控制线63在衬底基板1上的正投影交叉，并且第二驱动电压子线1652在衬底基板1上的正投影与第二存储电容电极Cst2在衬底基板1上的正投影至少部分重叠。第二驱动电压子线1652的一部分形成于过孔VH20中，该部分向下延伸以与连接部171的一部分电连接，从而与第二存储电容电极Cst2电连接。通过这样的方式，可以实现驱动电压线、第二存储电容电极Cst2和第一操作控制晶体管T5的源极S5之间的电连接。
第一驱动电压子线1651和第二驱动电压子线1652在第二方向Y上彼此间隔开一定的距离。例如，第一驱动电压子线1651靠近第二驱动电压子线1652的一端在衬底基板1上的正投影与复位信号线62在衬底基板1上的正投影部分重叠，第二驱动电压子线1652靠近第一驱动电压子线1651的一端在衬底基板1上的正投影与第二存储电容电极Cst2靠近发光控制线63的部分在衬底基板1上的正投影部分重叠。间隔开的第一驱动电压子线1651和第二驱动电压子线1652将通过连接部电连接在一起，关于这一点，将在下文中详细说明。
在本公开的实施例中，在所述第一子像素和所述第二子像素之间设置有第一透明导电连接部161，用于将位于所述第一子像素的占用区域中的第二复位晶体管T1’(包括共用晶体管T10和第二子晶体管T12)电连接至第二子像素驱动电路DR2中。
参照图20A和图20B，所述第一透明导电连接部161的一端通过过孔VH21与第二子源极部分2032a和第二子漏极部分2052a中的一个电连接，所述第一透明导电连接部161的另一端通过过孔VH22与所述第二子像素驱动电路DR2的第二驱动晶体管T3的栅极电连接。以此方式，可以将位于所述第一子像素的占用区域中的第二复位晶体管T1’(包括共用晶体管T10和第二子晶体管T12)电连接至第二子像素驱动电路DR2中。
例如，所述第一透明导电连接部161在所述衬底基板1上的正投影与所述第一初始化晶体管T7的有源层20g在所述衬底基板1上的正投影部分重叠，以及所述第一透明导电连接部161在所述衬底基板1上的正投影与所述第二初始化晶体管T7的有源层20g在所述衬底基板1上的正投影部分重叠。
例如，所述第一透明导电连接部161至少包括第一部分1611、第二部分1612和 第三部分1613。所述第二部分1612位于第一部分1611和第三部分1613之间，连接第一部分1611和第三部分1613。即，所述第一透明导电连接部161为连续延伸的连接部。所述第一透明导电连接部的第三部分1613沿第一方向X延伸，所述第一透明导电连接部的第二部分1612沿第二方向Y延伸，所述第一透明导电连接部的第一部分1611沿相对于第一方向X和第二方向Y均倾斜的倾斜方向延伸。
所述第一透明导电连接部的第一部分1611在所述衬底基板1上的正投影与所述第一初始化晶体管T7的有源层20g在所述衬底基板1上的正投影部分重叠。所述第一透明导电连接部的第三部分1613在所述衬底基板1上的正投影与所述第二初始化晶体管T7的有源层20g在所述衬底基板1上的正投影部分重叠。所述第一透明导电连接部的第二部分1612位于所述第一子像素和所述第二子像素之间的透光区域中。例如，所述第一透明导电连接部的第一部分1611的一部分以及所述第一透明导电连接部的第三部分1613的一部分也位于所述第一子像素和所述第二子像素之间的透光区域中。
在本公开的实施例中，在所述第一子像素和所述第二子像素之间设置有第二透明导电连接部162，用于将位于所述第一子像素的占用区域中的复位信号线66电连接至第二子像素驱动电路DR2中，从而将复位信号RESET接入第二子像素驱动电路DR2中。
在本公开的一些示例性实施例中，可以降低第一透明导电连接部161的电阻。例如，可以增加第一透明导电连接部161的线宽，例如，第一透明导电连接部161的线宽可以大于导电连接部162、163和166中每一个的线宽。例如，可以缩短第一透明导电连接部161的延伸长度。例如，可以采用位于两个导电层中的导电部并联形成第一透明导电连接部，例如，第一透明导电连接部的第一部分可以位于所述第一透明导电层中，第二部分可以位于所述第三导电层、所述第四导电层或第二透明导电层中，所述第一部分和所述第二部分并联，以形成所述第一透明导电连接部。
在本公开的一些示例性实施例中，在透明导电连接部161、162、163和166中，第一透明导电连接部161可以设置在最边缘的一侧。即，透明导电连接部161、162、163和166的排列顺序不局限于图20A～图20B中示出的方式。例如，第一透明导电连接部161可以设置在第二导电连接部162远离第三导电连接部163的一侧。以此方式，可以尽量减小其他电子元器件或电学环境对第一透明导电连接部161的影响，从而可以保证第一透明导电连接部161传输的复位信号的稳定性。
在本公开的一些示例性实施例中，结合参照图6C和图20B，通过调整复位信号传 输至两个子像素的驱动晶体管T3的栅极的路径上的电阻，可以使得所述复位信号的传输路径上的电阻基本一致，或者说，可以实现不同子像素的复位信号的传输路径上的电阻可调。例如，图6C中的电阻R1和R3示意性地表示了复位信号传输至所述第一子像素的驱动晶体管T3的栅极的路径上的电阻，电阻R2和R4示意性地表示了复位信号传输至所述第二子像素的驱动晶体管T3的栅极的路径上的电阻。
例如，如上所述，可以增加第一透明导电连接部161的线宽，缩短第一透明导电连接部161的延伸长度，或者采用位于两个导电层(例如第一透明导电层和第二透明导电层)中的导电部并联形成第一透明导电连接部，来调整所述复位信号传输至所述第二子像素的驱动晶体管T3的栅极的的路径上的电阻，从而使得所述复位信号传输至两个子像素的驱动晶体管T3的栅极的的路径上的电阻基本一致。
继续参照图6C和图20B，可以调整作用于节点N1的耦合电容，来调整不同子像素的节点N1处的电位，从而使得不同子像素的节点N1处的电位保持稳定，即基本一致。例如，图6C中的Cst1-ref1示意性示出了作用于第一子像素驱动电路DR1的节点N1的耦合电容，Cst1-ref2示意性示出了作用于第二子像素驱动电路DR2的节点N1的耦合电容。
例如，可以将第一透明导电连接部161(即用于传输复位信号至第二子像素驱动电路的驱动晶体管的栅极的导线)移到靠近驱动电压线(例如第一驱动电压子线1651)的附近，即，透明导电连接部161、162、163的位置可以交换；或者，第一透明导电连接部161可以与具有VDD电位的膜层交叠；或者，将初始化信号线66的一部分向下延伸，使其与第一透明导电连接部161交叠。即，在一些示例性实施例中，可以设置第一透明导电连接部161与具有恒定电位的导电部或膜层交叠，以形成作用于节点N1的耦合电容。再例如，可以使共用复位晶体管的两个子像素(例如所述第一子像素和所述第二子像素)中的交叠面积不同，实现不同子像素的差异化设计，以调整节点N1各处的导电部分的电学环境。以此方式，可以保持不同子像素的像素驱动电路中的节点N1处的电位一致，有利于提高显示基板的均一性。
需要说明的是，虽然电阻R1～R4和耦合电容Cst1-reff1、Cst1-ref2同时设置于图6C中，但是，本公开的实施例并不局限于此。例如，在一些实施例中，可以仅设置所述电阻R1～R4，以调整复位信号传输至两个子像素的驱动晶体管T3的栅极的路径上的电阻。在一些实施例中，可以仅设置作用于节点N1的耦合电容，以调整不同子像素的节点N1处的电位。
参照图20A和图20B，所述第二透明导电连接部162的一端通过过孔VH23与连接部169电连接，所述第二透明导电连接部162的另一端通过过孔VH24与所述第二子像素驱动电路DR2的第二初始化晶体管T7的有源层20g的一端电连接。例如，过孔VH23在衬底基板1上的正投影与过孔VH4在衬底基板1上的正投影至少部分重叠。即，所述第二透明导电连接部162的一端通过过孔VH23与连接部169的一端(图20B中为下端)电连接。所述第二透明导电连接部162的另一端通过过孔VH24与所述第二初始化晶体管T7的第七源极区203g或第七漏极区205g电连接。以此方式，可以将复位信号线66传输的复位信号RESET供应至第二子像素驱动电路DR2的第二初始化晶体管T7的源极或漏极。
例如，所述第二透明导电连接部162至少包括第一部分1621、第二部分1622和第三部分1623，所述第二部分1622位于第一部分1621和第三部分1623之间。所述第二透明导电连接部的第一部分1621沿第一方向X延伸，所述第二透明导电连接部的第三部分1623沿第二方向Y延伸，所述第二透明导电连接部的第二部分1622沿相对于第一方向X和第二方向Y均倾斜的倾斜方向延伸。
所述第二透明导电连接部162可以位于所述第一子像素和所述第二子像素之间的透光区域中。例如，所述第二透明导电连接部162的第一部分1621、第二部分1622和第三部分1623均位于所述第一子像素和所述第二子像素之间的透光区域中。
如图21A和图21B所示，连接部172和导电连接部173位于第四导电层24中。
连接部172的一部分形成于过孔VH1中，该部分向下延伸以与第一驱动电压子线1651电连接。连接部172的另一部分形成于过孔VH7”’中，该部分向下延伸以与第二驱动电压子线1652电连接。也就是说，通过连接部172，可以将第一驱动电压子线1651与第二驱动电压子线1652电连接起来，这样，位于同一列的各个子像素的驱动电压线就可以连接起来，以便于给各个子像素供应驱动电压信号VDD。
在本公开的一些实施例中，第一驱动电压子线1651与第二驱动电压子线1652在像素驱动电路处可以不断开，这样，可以无需设置所述连接部172。
在本公开的一些实施例中，第一驱动电压子线1651与第二驱动电压子线1652在像素驱动电路处可以断开，同时，还可以设置连接部172。这样，连接部172与驱动电压线165的一部分并联，有利于降低驱动电压线165上的电阻。
导电连接部173的一部分形成于过孔VH10’中，该过孔VH10’暴露连接部170的一部分，这样，可以将导电连接部173电连接至连接部170。
如图22A和图22B所示，在第一显示区域AA1中，设置有第二透明导电层28，例如，该第二透明导电层28可以由诸如氧化铟锡(即ITO)等的透明导电材料构成。该第二透明导电层28位于第四导电层24远离衬底基板1的一侧。所述显示基板还包括设置于所述衬底基板1上的第一导电引线181和第二导电引线182。第一导电引线181和第二导电引线182可以位于第二透明导电层28中。即，第一导电引线181和第二导电引线182由诸如氧化铟锡(即ITO)等的透明导电材料构成。
如图22A和图22B所示，除了复位晶体管T1、T1’之外，第一子像素驱动电路DR1和第二子像素驱动电路DR2中的其他晶体管T2～T7可以是镜像设置的。
图25A和图25B是示出根据本公开的一些示例性实施例的显示基板的第一显示区域AA1中的多个子像素组的示例性实施方式的平面图。结合参照图20A、图20B、图22A、图22B和图25A和图25B，在第一显示区域AA1中，沿第一方向X延伸的扫描信号线61、复位信号线62、发光控制线63和初始化电压线66分别通过位于透明导电层中的导电引线或透明导电连接部电连接。这样，在第一显示区域AA1的透光区域中，仅布置有透明的导电引线和透明导电连接部，而不会布置由金属等不透光材料构成的导电引线。以此方式，可以保证第一显示区域AA1的透光率较大。
例如，在一个子像素组内，所述第一子像素11(12)的第一扫描信号线61和所述第二子像素13的第二扫描信号线61通过第三透明导电连接部163电连接，所述第一子像素11(12)的第一发光控制线63和所述第二子像素13的第二发光控制线63通过第四透明导电连接部166电连接。
例如，在一个子像素组的两侧，分别设置有第三导电引线263，以将位于同一行的各个子像素组的扫描信号线61电连接在一起。位于左侧的第三导电引线263的一部分形成于过孔VH15中，该部分向下延伸以与第一扫描信号线61的一端电连接。位于右侧的第三导电引线263的一部分形成于过孔VH15中，该部分向下延伸以与第二扫描信号线61的一端电连接。借助第三透明导电连接部163和第三导电引线263，可以将同一行的子像素的扫描信号线61电连接起来，以便于供应扫描信号Sn。
在一个子像素组的两侧，分别设置有第四导电引线266，以将位于同一行的各个子像素组的发光控制线63电连接在一起。位于左侧的第四导电引线266的一部分形成于过孔VH17中，该部分向下延伸以与第一发光控制线63的一端电连接。位于右侧的第四导电引线266的一部分形成于过孔VH17中，该部分向下延伸以与第二发光控制线63的一端电连接。借助第四透明导电连接部166和第四导电引线266，可以将同一 行的子像素的发光控制线63电连接起来，以便于供应发光控制信号Em。
在一个子像素组的复位信号线62两侧，分别设置有第一导电引线181。一条第一导电引线181的一部分形成于过孔VH13中，该部分向下延伸以与复位信号线62的一端电连接。另一条第一导电引线181的一部分形成于过孔VH14中，该部分向下延伸以与复位信号线62的另一端电连接。借助第一导电引线181，可以将同一行的子像素组的复位信号线62电连接起来，以便于供应复位信号Reset。
在一个子像素组的初始化电压线66两侧，分别设置有第二导电引线182。一条第二导电引线182的一部分形成于过孔VH11中，该部分向下延伸以与初始化电压线66的一端电连接。另一条第二导电引线182的一部分形成于过孔VH12中，该部分向下延伸以与初始化电压线66的另一端电连接。借助第二导电引线182，可以将同一行的子像素组的初始化电压线66电连接起来，以便于供应发光初始化电压信号Vinit。
换句话说，结合参照图25A和图25B，所述多个子像素组至少包括位于同一行且相邻的第一子像素组SP1和第二子像素组SP2。一条第一导电引线181的一端通过过孔VH13与第一子像素组SP1中的复位信号线62电连接，该条第一导电引线181的另一端通过过孔VH14与第二子像素组SP1中的复位信号线62电连接。一条第二导电引线182的一端通过过孔VH11与第一子像素组SP1中的初始化电压线66电连接，该条第二导电引线182的另一端通过过孔VH12与第二子像素组SP2中的初始化电压线66电连接。
在本公开的实施例中，所述第一导电引线181和所述第二导电引线182中的至少一个在所述衬底基板1上的正投影与所述数据线164和所述驱动电压线165(第一驱动电压子线1651和/或第二驱动电压子线1652)中的至少一个在所述衬底基板1上的正投影交叉。
如图23A和图23B所示，第一发光器件41的第一电极(例如阳极)可以位于第五导电层25中。如上所述，第一发光器件41的阳极包括阳极主体411和阳极连接部412。
在所述第一子像素11(12)中，阳极连接部412的一部分可以形成于过孔VH10”中，该过孔VH10”暴露导电连接部173的一部分，这样，可以将阳极连接部412电连接至导电连接部173，然后连接至连接部170。即，通过导电连接部173和连接部170，可以使得所述第一子像素的第一发光器件41的阳极、第一初始化晶体管T7的源极S7和第一发光控制晶体管T6的漏极D6电连接，即形成图6B中所示的N4节点。
在所述第二子像素13中，阳极连接部412的一部分可以形成于过孔VH10”中，该过孔VH10”暴露导电连接部173的一部分，这样，可以将阳极连接部412电连接至导电连接部173，然后连接至连接部170。即，通过导电连接部173和连接部170，可以使得所述第二子像素的第一发光器件41的阳极、第二初始化晶体管T7的源极S7和第二发光控制晶体管T6的漏极D6电连接，即形成图6B中所示的N4节点。
结合参照图4、图23A和图23B以及图25A和图25B，在第一显示区域AA1中，子像素11、子像素12和子像素13的像素驱动电路都可以基本缩小至第一发光器件41的大小，并且放置在发光器件41下方。这样，在第一显示区域AA1(即屏下摄像区)中，可以将各个子像素的像素驱动电路内置于相应的子像素中，不需要将其外置于间隔区域SR中，可以避免上述的像素驱动电路外置导致的各种问题。而且，在本公开的实施例中，将各个子像素的像素驱动电路内置于相应的子像素中，并且藏在相应的子像素的发光器件下方，可以保证第一显示区域的透光率较大，即有利于实现第一显示区域的高透光率。可以结合参照图4，在第一显示区域AA1中，在各个相邻的子像素之间，存在透光区域TRA。由于各个子像素的像素驱动电路都可以基本缩小至第一发光器件41的大小，并且放置在发光器件41下方，所以，有利于实现透光区域TRA的面积较大，从而能够保证第一显示区域的透光率较大。而且，在透光区域TRA中，仅设置有透明导电引线，而不存在任何不透光引线，从而能够进一步保证第一显示区域的透光率较大。
参照图7和图13，在第二显示区域AA2中，各个子像素21、22、23的像素驱动电路的占用区域的面积较大。例如，子像素23(即绿色子像素)的像素驱动电路的占用区域的面积大于子像素13(即绿色子像素)的像素驱动电路的占用区域的面积。
在本文中，在第二显示区域AA2中各个子像素21、22、23的像素驱动电路的占用区域可以使用如下的区域表示：参照图12A和图12B，对于各个子像素21、22、23的像素驱动电路而言，在第一方向X上，数据信号线64和第一发光控制晶体管T6的第六有源层20f分别位于最左侧和最右侧，即二者在第一方向X上的距离最大；在第二方向Y上，初始化电压线66和发光控制线63分别位于最上侧和最下侧，即二者在第二方向Y上的距离最大。这样，在一个子像素的像素驱动电路在衬底基板上的正投影中，数据信号线64具有远离第一发光控制晶体管T6的第六有源层20f的第一侧边，第一发光控制晶体管T6的第六有源层20f具有远离数据信号线64的第二侧边，初始化电压线66具有远离发光控制线63的第三侧边，发光控制线63具有远离初始化电压 线66的第四侧边，其中，所述第一侧边和所述第二侧边沿第二方向Y延伸，所述第三侧边和所述第四侧边沿第一方向X延伸，这四条侧边的延长线会交叉，以包围形成一个区域，该区域即为位于第二显示区域AA2中的一个子像素的像素驱动电路的占用区域，如图12A中所示的由虚线框包围的区域AR22。
在本文中，在第一显示区域AA1中各个子像素11、12、13的像素驱动电路的占用区域可以使用如下的区域表示：参照图23A和图23B，对于所述第一子像素11(12)，过孔VH11、VH12、VH13、VH14、VH15、VH16、VH17、VH18和VH23分别位于像素驱动电路的最外侧，并且过孔VH9和VH10”位于像素驱动电路的最外侧，将这11个过孔中每两个相邻的过孔的中心依次连接，可以包围形成一个区域，如图23B中所示的由虚线框包围的区域AR1，该区域AR1可以为位于第一显示区域AA1中的一个第一子像素的第一子像素驱动电路的占用区域。对于所述第二子像素13，过孔VH24、VH16’、VH18’、VH9、VH10”、VH17、VH15和VH3分别位于像素驱动电路的最外侧，将这8个过孔中每两个相邻的过孔的中心依次连接，可以包围形成一个区域，如图23B中所示的由虚线框包围的区域AR2，该区域AR2可以为位于第一显示区域AA1中的一个第二子像素的第二子像素驱动电路的占用区域。
在本文中，除非另有特别说明，在第二显示区域AA2中的子像素的发光器件的占用区域可以用该发光器件的阳极在衬底基板上的正投影的覆盖区域表示。类似地，在第一显示区域AA1中的子像素的发光器件的占用区域可以用该发光器件的阳极在衬底基板上的正投影的覆盖区域表示。
在本公开的实施例中，第一显示区域AA1中的PPI与第二显示区域中的PPI基本相等。也就是说，在相等的面积内，第一显示区域AA1中布置的第一重复单元P1的个数与第二显示区域AA2中布置的第二重复单元P2的个数基本相等，或者说，第一显示区域AA1中布置的子像素的个数与第二显示区域AA2中布置的同颜色的子像素的个数基本相等。这样，使得第一显示区域和第二显示区域都具有较高的PPI，均能实现较高的显示质量，并且显示均一性较好。
在本文中，除非另有说明，表述“基本相等”、“基本等于”等可以表示被比较的两个值的比率约等于1，例如，被比较的两个值的比率可以在0.8～1.2的范围内。
在一些实施例中，第一显示区域AA1中的各个子像素的发光器件的占用区域的面积与第二显示区域AA2中的同颜色的子像素的发光器件的占用区域的面积基本相等。例如，子像素11的第一发光器件41的阳极在衬底基板1上的正投影的面积与子像素 21的第二发光器件42的阳极在衬底基板1上的正投影的面积基本相等；子像素12的第一发光器件41的阳极在衬底基板1上的正投影的面积与子像素22的第二发光器件42的阳极在衬底基板1上的正投影的面积基本相等；子像素13的第一发光器件41的阳极在衬底基板1上的正投影的面积与子像素23的第二发光器件42的阳极在衬底基板1上的正投影的面积基本相等。通过这样的设置，有利于实现第一显示区域AA1中的PPI与第二显示区域中的PPI基本相等，另外，还可以使得第一显示区域和第二显示区域之间的显示均一性较好，并且第一显示区域和第二显示区域之间的发光材料的寿命均一性也较好。
需要说明的是，本公开的实施例不局限于上述实施方式，在其他实施例中，第一显示区域AA1中的各个子像素的发光器件的占用区域的面积与第二显示区域AA2中的同颜色的子像素的发光器件的占用区域的面积也可以不相等，只要能实现第一显示区域AA1中的PPI与第二显示区域中的PPI基本相等即可。
在本公开的实施例中，在第一显示区域AA1中各个子像素11、12、13的像素驱动电路的占用区域的面积被缩小，有利于将各个子像素的像素驱动电路藏在相应的子像素的发光器件的下方。
如上所述，参照图17B，对于位于第一显示区域AA1中的一个第一子像素而言，第一初始化晶体管T7的有源层20g相对于第一复位晶体管T1的有源层20a沿靠近该子像素的扫描信号线61的方向延伸，即，第一初始化晶体管T7的有源层20g位于第一复位晶体管T1的有源层20a的右下方。通过这样的设置方式，位于第一显示区域AA1中的一个第一子像素的有源层的占用区域的轮廓为正方形或近似正方形。参照图23A和图23B，第一子像素11(12)、的第一发光器件41的阳极主体在衬底基板上的正投影为圆形。通过这样的设置方式，有利于实现各个子像素的阳极覆盖该子像素的像素驱动电路。
参照图23B，第一子像素11(12)的第一发光器件41的阳极在衬底基板1上的正投影与第一子像素11(12)的像素驱动电路的占用区域AR1在衬底基板1上的正投影至少部分重叠，例如，第一子像素11(12)的第一发光器件41的阳极在衬底基板1上的正投影基本完全覆盖第一子像素11(12)的像素驱动电路的占用区域AR1在衬底基板1上的正投影。
在本文中，除非另有特别说明，表述“基本完全覆盖”表示覆盖某一正投影的整体面积的90％以上。
参照图23B，第二子像素13的第一发光器件41的阳极在衬底基板1上的正投影与第二子像素13的像素驱动电路的占用区域AR2在衬底基板1上的正投影至少部分重叠，例如，第二子像素13的第一发光器件41的阳极在衬底基板1上的正投影基本完全覆盖第二子像素13的像素驱动电路的占用区域AR2在衬底基板1上的正投影。
在本公开的实施例中，子像素13的第一发光器件41的阳极在衬底基板1上的正投影的面积小于子像素11的第一发光器件41的阳极在衬底基板1上的正投影的面积，子像素11的第一发光器件41的阳极在衬底基板1上的正投影的面积小于子像素12的第一发光器件41的阳极在衬底基板1上的正投影的面积。
在本公开的实施例中，将所述第二子像素13的像素驱动电路中的复位晶体管设置为与所述第一子像素11(12)的像素驱动电路中的复位晶体管至少部分共用，可以减少需要在所述第二子像素13的像素驱动电路的占用区域AR2中设置的晶体管的数量，从而可以减小所述第二子像素13的像素驱动电路的占用区域AR2的面积。这样，尽管所述第二子像素13第一发光器件41的阳极的面积较小，仍可以保证所述第二子像素13第一发光器件41的阳极可以基本覆盖所述第二子像素13的像素驱动电路，即，将所述第二子像素13的像素驱动电路藏在其发光器件的阳极下方。
例如，在第一显示区域AA1中，各个子像素的第一发光器件41的阳极在衬底基板1上的正投影至少覆盖该子像素的像素驱动电路的存储电容器Cst(包括第一存储电容电极Cst1和第二存储电容电极Cst2)和多个晶体管在衬底基板1上的正投影。
在本文中，除非另有特别说明，表述“晶体管在衬底基板上的正投影”包括晶体管的有源层、栅极、源极和漏极在衬底基板上的正投影的组合。
例如，参照图23B，第二子像素13的第一发光器件41的阳极在衬底基板1上的正投影覆盖该第二子像素13的像素驱动电路的第二补偿晶体管T2、第二驱动晶体管T3、第二开关晶体管T4、第二操作控制晶体管T5、第二发光控制晶体管T6、第二初始化晶体管T7和存储电容器Cst在衬底基板1上的正投影。
例如，参照图23B，第一子像素11(12)的第一发光器件41的阳极在衬底基板1上的正投影覆盖该第一子像素11(12)的像素驱动电路的第一复位晶体管T1、第一补偿晶体管T2、第一驱动晶体管T3、第一开关晶体管T4、第一操作控制晶体管T5、第一发光控制晶体管T6、第一初始化晶体管T7和存储电容器Cst在衬底基板1上的正投影。此外，第一子像素11(12)的第一发光器件41的阳极在衬底基板1上的正投影还覆盖第二子像素13的像素驱动电路的第二复位晶体管T1’在衬底基板1上的正投 影。
在本公开的实施例中，通过这样的设置方式，可以将各个子像素的像素驱动电路设置在发光器件(例如阳极)的下方，使得像素驱动电路不会占用各个子像素之间的透光区域，有利于第一显示区域具有高透光率，同时，可以实现第一显示区域中的高PPI，即有利于实现屏下摄像区的高显示质量。
图26A、图26B和图26C分别是示出图15中一个重复单元包括的3个子像素的示例性实施方式的遮挡层、半导体层、第一导电层、第二导电层、第三导电层、第一透明导电层、第四导电层、第二透明导电层和第五导电层的组合的平面图。图27是示出根据本公开的一些示例性实施例的显示基板的沿图26A中的线FF’截取的截面结构的示意图。
参照图26A至图27，在本公开的实施例中，所述显示基板还可以包括遮挡层LS。遮挡层LS可以设置在衬底基板1与半导体层20之间，用于保护半导体层20，以避免各个子像素的像素驱动电路的各个晶体管的有源层受到外界光的影响。
例如，遮挡层LS可以由不透光的金属材料构成。遮挡层LS也可以包含诸如非晶硅、多晶硅等的半导体膜层。
各个子像素的遮挡层LS在衬底基板1上的正投影可以覆盖该子像素的像素驱动电路的占用区域AR1或AR2在衬底基板1上的正投影。通过这样的设置，可以避免各个子像素的像素驱动电路受到外界光的影响。
例如，遮挡层LS可以接入一固定电压，以避免其处于悬置状态(即floating)。
在一些实施例中，遮挡层LS可以呈面状或网格状。遮挡层LS在衬底基板1上的正投影可以与位于所述第一透明导电层和/或所述第二透明导电层中的结构或部分在衬底基板1上的正投影至少部分重叠。
返回参照图4，第一发光器件41可以包括层叠设置的阳极、发光材料层和阴极。所述显示基板可以包括第六导电层，阴极CAT位于该第六导电层中。
在一些实施例中，在第一显示区域AA1中，第六导电层可以被图案化。即，第六导电层可以包括多个阴极CAT和多个阴极开口271。阴极开口271可以位于相邻的阴极CAT之间。
例如，在第一显示区域AA1中，各个子像素的第一发光器件41的阴极CAT在衬底基板1上的正投影可以覆盖该子像素的第一发光器件41的阳极在衬底基板1上的正投影。各个阴极开口271在衬底基板1上的正投影可以与各个子像素之间的透光区域 TRA在衬底基板1上的正投影重叠。通过这样的设置，可以保证第一显示区域AA1中的透光区域的透光率较高。
本公开的至少一些实施例还提供一种显示面板，所述显示面板包括如上所述的显示基板。例如，所述显示面板可以是OLED显示面板。
参照图1，本公开的至少一些实施例还提供一种显示装置。该显示装置可以包括如上所述的显示基板。
所述显示装置可以包括任何具有显示功能的设备或产品。例如，所述显示装置可以是智能电话、移动电话、电子书阅读器、台式电脑(PC)、膝上型PC、上网本PC、个人数字助理(PDA)、便携式多媒体播放器(PMP)、数字音频播放器、移动医疗设备、相机、可穿戴设备(例如头戴式设备、电子服饰、电子手环、电子项链、电子配饰、电子纹身、或智能手表)、电视机等。
应该理解，根据本公开实施例的显示面板和显示装置具有上述显示基板的所有特点和优点，具体可以参见上文的描述，在此不再赘述。
虽然本公开的总体技术构思的一些实施例已被显示和说明，本领域普通技术人员将理解，在不背离所述总体技术构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (30)

  1. 一种显示基板，所述显示基板包括第一显示区域和第二显示区域，所述第一显示区域的透光率大于所述第二显示区域的透光率，其特征在于，所述显示基板包括：
    衬底基板；
    设置于所述衬底基板且位于所述第一显示区域中的多个子像素，所述子像素包括第一像素驱动电路和第一发光器件，所述第一像素驱动电路与所述第一发光器件电连接，用于驱动所述第一发光器件发光；和
    设置于所述衬底基板且位于所述第二显示区域中的多个子像素，位于所述第二显示区域中的子像素包括第二像素驱动电路和第二发光器件，所述第二像素驱动电路与所述第二发光器件电连接，用于驱动所述第二发光器件发光，
    其中，位于所述第一显示区域中的多个子像素包括多个子像素组，每一个子像素组包括第一子像素和第二子像素，所述第一像素驱动电路包括第一子像素驱动电路和第二子像素驱动电路，所述第一子像素驱动电路用于驱动第一子像素的第一发光器件发光，所述第二子像素驱动电路用于驱动第二子像素的第一发光器件发光，所述第一子像素驱动电路至少包括第一复位晶体管，所述第二子像素驱动电路至少包括第二复位晶体管，所述第一子像素驱动电路的第一复位晶体管与所述第二子像素驱动电路的第二复位晶体管至少部分共用。
  2. 根据权利要求1所述的显示基板，其特征在于，所述第一子像素驱动电路的第一复位晶体管与所述第二子像素驱动电路的第二复位晶体管中每一个在所述衬底基板上的正投影均落入所述第一子像素驱动电路的占用区域在所述衬底基板上的正投影内。
  3. 根据权利要求1或2所述的显示基板，其特征在于，所述第一复位晶体管包括共用晶体管和第一子晶体管，所述第二复位晶体管包括所述共用晶体管和第二子晶体管，所述共用晶体管、所述第一子晶体管和所述第二子晶体管中的每一个均包括栅极、源极和漏极，所述共用晶体管、所述第一子晶体管和所述第二子晶体管中的每一个的栅极均接入复位控制信号，所述共用晶体管的源极或漏极中的一个接入初始化电压信号，所述共用晶体管的源极或漏极中的另一个分别与所述第一子晶体管和所述第 二子晶体管电连接。
  4. 根据权利要求3所述的显示基板，其特征在于，所述显示基板还包括设置于所述衬底基板上的半导体层和位于所述半导体层远离所述衬底基板的一侧的第一导电层，所述显示基板还包括设置于所述衬底基板上的复位信号线，所述复位信号线用于传输复位控制信号，所述复位信号线位于所述第一导电层；以及
    所述复位信号线包括位于所述第一显示区域中的第一部分、第二部分和第三部分，所述半导体层包括位于所述第一显示区域中的共用沟道部分、第一沟道部分和第二沟道部分，所述第一部分、所述第二部分和所述第三部分在所述衬底基板上的正投影分别与所述共用沟道部分、所述第一沟道部分和所述第二沟道部分在所述衬底基板上的正投影重合，所述共用晶体管的栅极包括所述第一部分，所述第一子晶体管的栅极包括所述第二部分，所述第二子晶体管的栅极包括所述第三部分。
  5. 根据权利要求4所述的显示基板，其特征在于，所述共用晶体管包括位于所述半导体层中的共用源极部分和共用漏极部分，所述第一子晶体管包括位于所述半导体层中的第一子源极部分和第一子漏极部分，所述第二子晶体管包括位于所述半导体层中的第二子源极部分和第二子漏极部分；以及
    所述共用源极部分和所述共用漏极部分分别位于所述共用沟道部分的两侧，所述第一子源极部分和所述第一子漏极部分分别位于所述第一沟道部分的两侧，所述第二子源极部分和所述第二子漏极部分分别位于所述第二沟道部分的两侧。
  6. 根据权利要求5所述的显示基板，其特征在于，所述显示基板还包括设置于所述衬底基板上的初始化电压线和设置于所述衬底基板上的第一连接部；
    所述共用源极部分和所述共用漏极部分中的一个通过第一过孔与所述初始化电压线电连接，所述共用源极部分和所述共用漏极部分中的另一个与所述第一子源极部分和所述第一子漏极部分中的一个连续延伸；以及
    所述第一子源极部分和所述第一子漏极部分中的另一个通过第二过孔与所述第一连接部的一端电连接。
  7. 根据权利要求6所述的显示基板，其特征在于，所述第一子像素驱动电路还 包括第一驱动晶体管，所述第一驱动晶体管包括栅极，所述第一连接部的另一端通过第三过孔与所述第一驱动晶体管的栅极电连接。
  8. 根据权利要求6或7所述的显示基板，其特征在于，所述显示基板还包括设置于所述衬底基板上的第一透明导电连接部；
    所述共用源极部分和所述共用漏极部分中的另一个还与所述第二子源极部分和所述第二子漏极部分中的一个连续延伸；以及
    所述第二子源极部分和所述第二子漏极部分中的另一个通过第三过孔与所述第一透明导电连接部的一端电连接。
  9. 根据权利要求8所述的显示基板，其特征在于，所述第二子像素驱动电路还包括第二驱动晶体管，所述第二驱动晶体管包括栅极，所述第一透明导电连接部的另一端通过第四过孔与所述第二驱动晶体管的栅极电连接。
  10. 根据权利要求8所述的显示基板，其特征在于，所述初始化电压线位于第二导电层中，所述第一连接部位于第三导电层中，所述第二导电层位于所述第一导电层远离所述衬底基板的一侧，所述第三导电层位于所述第二导电层远离所述衬底基板的一侧。
  11. 根据权利要求10所述的显示基板，其特征在于，所述第一透明导电连接部位于第一透明导电层中，所述第一透明导电层位于所述第三导电层远离所述衬底基板的一侧。
  12. 根据权利要求8所述的显示基板，其特征在于，所述第一子像素驱动电路还包括第一初始化晶体管，所述第一初始化晶体管包括位于所述半导体层中的有源层；
    所述第二子像素驱动电路还包括第二初始化晶体管，所述第二初始化晶体管包括位于所述半导体层中的有源层；以及
    所述第一透明导电连接部在所述衬底基板上的正投影与所述第一初始化晶体管的有源层在所述衬底基板上的正投影部分重叠，以及所述第一透明导电连接部在所述衬底基板上的正投影与所述第二初始化晶体管的有源层在所述衬底基板上的正投影部 分重叠。
  13. 根据权利要求12所述的显示基板，其特征在于，所述显示基板还包括设置于所述衬底基板上的第一扫描信号线和第二扫描信号线，所述第一扫描信号线用于供应扫描信号给所述第一子像素驱动电路，所述第二扫描信号线用于供应扫描信号给所述第二子像素驱动电路；以及
    所述第一扫描信号线在所述衬底基板上的正投影与所述第一初始化晶体管的有源层在所述衬底基板上的正投影部分重叠，所述第二扫描信号线在所述衬底基板上的正投影与所述第二初始化晶体管的有源层在所述衬底基板上的正投影部分重叠。
  14. 根据权利要求12所述的显示基板，其特征在于，所述第一透明导电连接部至少包括第一部分、第二部分和第三部分，所述第一透明导电连接部的第三部分沿第一方向延伸，所述第一透明导电连接部的第二部分沿第二方向延伸，所述第一透明导电连接部的第一部分沿相对于第一方向和第二方向均倾斜的倾斜方向延伸。
  15. 根据权利要求14所述的显示基板，其特征在于，所述第一透明导电连接部的第一部分在所述衬底基板上的正投影与所述第一初始化晶体管的有源层在所述衬底基板上的正投影部分重叠；和/或，
    所述第一透明导电连接部的第三部分在所述衬底基板上的正投影与所述第二初始化晶体管的有源层在所述衬底基板上的正投影部分重叠；和/或，
    所述第一透明导电连接部的第二部分位于第一子像素和第二子像素之间的透光区域中。
  16. 根据权利要求12所述的显示基板，其特征在于，所述第一初始化晶体管的有源层与所述第一子像素驱动电路位于所述半导体层中的其他部分间隔设置；和/或，
    所述第二初始化晶体管的有源层与所述第二子像素驱动电路位于所述半导体层中的其他部分间隔设置。
  17. 根据权利要求12所述的显示基板，其特征在于，所述显示基板还包括设置于所述衬底基板上的第二连接部，所述第二连接部的第一端通过第五过孔与所述初始 化电压线电连接，所述第二连接部的第二端通过第六过孔与所述第一初始化晶体管的有源层的第一端电连接。
  18. 根据权利要求17所述的显示基板，其特征在于，所述显示基板还包括设置于所述衬底基板上的第二透明导电连接部，所述第二透明导电连接部的第一端通过第七过孔与所述第二连接部的第二端电连接，所述第二透明导电连接部的第二端通过第八过孔与所述第二初始化晶体管的有源层的第一端电连接。
  19. 根据权利要求18所述的显示基板，其特征在于，所述第二连接部位于所述第三导电层中；和/或，所述第二透明导电连接部位于所述第一透明导电层中。
  20. 根据权利要求13所述的显示基板，其特征在于，所述显示基板还包括设置于所述衬底基板上的第三透明导电连接部，所述第三透明导电连接部的一端通过第九过孔与所述第一扫描信号线电连接，所述第三透明导电连接部的另一端通过第十过孔与所述第二扫描信号线电连接。
  21. 根据权利要求12所述的显示基板，其特征在于，所述显示基板还包括设置于所述衬底基板上的第一发光控制线和第二发光控制线，所述第一发光控制线用于供应发光控制信号给所述第一子像素驱动电路，所述第二发光控制线用于供应发光控制信号给所述第二子像素驱动电路；以及
    所述显示基板还包括设置于所述衬底基板上的第四透明导电连接部，所述第四透明导电连接部的一端通过第十一过孔与所述第一发光控制线电连接，所述第四透明导电连接部的另一端通过第十二过孔与所述第二发光控制线电连接。
  22. 根据权利要求6所述的显示基板，其特征在于，在至少一个子像素组中，所述第一子像素和所述第二子像素共用所述复位信号线和所述初始化电压线。
  23. 根据权利要求21所述的显示基板，其特征在于，所述多个子像素组至少包括位于同一行且相邻的第一子像素组和第二子像素组；以及
    所述显示基板还包括设置于所述衬底基板上的第一导电引线，所述第一导电引线 的一端通过第十三过孔与第一子像素组中的复位信号线电连接，所述第一导电引线的另一端通过第十四过孔与第二子像素组中的复位信号线电连接。
  24. 根据权利要求23所述的显示基板，其特征在于，所述显示基板还包括设置于所述衬底基板上的第二导电引线，所述第二导电引线的一端通过第十五过孔与第一子像素组中的初始化电压线电连接，所述第二导电引线的另一端通过第十六过孔与第二子像素组中的初始化电压线电连接。
  25. 根据权利要求24所述的显示基板，其特征在于，所述第三透明导电连接部和/或所述第四透明导电连接部位于所述第一透明导电层中；和，
    所述第一导电引线和/或所述第二导电引线位于第二透明导电层中，
    其中，所述第二透明导电层位于所述第一透明导电层远离所述衬底基板的一侧；
    所述显示基板还包括：用于传输数据信号的数据信号线；和用于传输驱动电压的驱动电压线；以及
    所述数据信号线和所述驱动电压线均位于所述第一透明导电层中。
  26. 根据权利要求25所述的显示基板，其中，所述驱动电压线在所述第一子像素驱动电路和所述第二子像素驱动电路处断开，以使得所述驱动电压线包括第一驱动电压子线和第二驱动电压子线，所述第一驱动电压子线和第二驱动电压子线在所述驱动电压线的延伸方向上间隔开；
    所述显示基板还包括第三连接部，所述第三连接部的一端通过第十七过孔与所述第一驱动电压子线电连接，另一端通过第十八过孔与所述第二驱动电压子线电连接；
    所述显示基板包括设置于所述衬底基板上的第四导电层，所述第四导电层位于所述第一透明导电层与所述第二透明导电层之间；以及
    所述第三连接部位于所述第四导电层中。
  27. 根据权利要求1或2所述的显示基板，其特征在于，所述第一发光器件至少包括第一电极和发光材料层，所述发光材料层设置在所述第一电极远离所述衬底基板的一侧；
    所述第一子像素的第一电极在所述衬底基板上的正投影的面积大于所述第二子 像素的第一电极在所述衬底基板上的正投影的面积；以及
    所述第一子像素的第一电极在所述衬底基板上的正投影覆盖所述第一子像素驱动电路的占用区域在所述衬底基板上的正投影；和/或，所述第二子像素的第一电极在所述衬底基板上的正投影覆盖所述第二子像素驱动电路的占用区域在所述衬底基板上的正投影。
  28. 一种显示面板，包括根据权利要求1-27中任一项所述的显示基板。
  29. 一种显示装置，包括根据权利要求1-27中任一项所述的显示基板或根据权利要求28所述的显示面板。
  30. 根据权利要求29所述的显示装置，其中，所述显示装置还包括至少一个图像传感器；以及
    其中，所述至少一个图像传感器在所述衬底基板上的正投影落入所述第一显示区域在所述衬底基板上的正投影内。
PCT/CN2021/075844 2021-02-07 2021-02-07 显示基板、显示面板和显示装置 Ceased WO2022165807A1 (zh)

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