WO2022174385A1 - 显示面板、显示装置 - Google Patents

显示面板、显示装置 Download PDF

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Publication number
WO2022174385A1
WO2022174385A1 PCT/CN2021/076832 CN2021076832W WO2022174385A1 WO 2022174385 A1 WO2022174385 A1 WO 2022174385A1 CN 2021076832 W CN2021076832 W CN 2021076832W WO 2022174385 A1 WO2022174385 A1 WO 2022174385A1
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WO
WIPO (PCT)
Prior art keywords
area
signal line
light
pixel
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/076832
Other languages
English (en)
French (fr)
Inventor
黄耀
邱远游
王智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202510214472.5A priority Critical patent/CN120076588A/zh
Priority to PCT/CN2021/076832 priority patent/WO2022174385A1/zh
Priority to CN202180000235.9A priority patent/CN115552613B/zh
Priority to EP21926105.4A priority patent/EP4141948A4/en
Priority to US17/771,073 priority patent/US12020642B2/en
Publication of WO2022174385A1 publication Critical patent/WO2022174385A1/zh
Anticipated expiration legal-status Critical
Priority to US18/633,563 priority patent/US12507552B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the under-screen camera technology is to set a light-transmitting area on the display panel, and set the camera facing the light-transmitting area to achieve full-screen display.
  • only light-emitting units are usually arranged in the light-transmitting area, and transition display areas are arranged on both sides of the light-transmitting area in the row direction, and a transition display area is provided in the transition display area for driving the light-emitting unit.
  • the pixel driver circuit of the unit The data lines located in the same sub-pixel column as the light-emitting units in the light-transmitting area need to be connected to the pixel driving circuits located in the transition display area by means of wiring.
  • the transition display area is also provided with main display areas on both sides in the column direction, and the data lines in the main display area on one side of the transition display area need to run through the transition area.
  • the display area extends to the main display area on the other side of the transition display area.
  • the data lines running through the transition display area are prone to crosstalk with the above-mentioned data lines connected to the transition display area by means of wiring.
  • a display panel includes a light-transmitting area, a first transition display area, a first main display area, and a second main display area; the first transition display area is located in the the two sides of the light-transmitting area in the row direction; the first main display area is located on one side of the light-transmitting area and the first transition display area in the column direction, and the second main display area is located in the light-transmitting area , the other side of the first transition display area in the column direction; the display panel further includes: a first light-emitting unit, a first pixel driving circuit, a first signal line, a second signal line, and a third signal line.
  • the first light-emitting unit is located in the light-transmitting area; the first pixel driving circuit is located in the first transition display area, and is used for providing driving current to the first light-emitting unit; the first signal line extends along the column direction, and the At least part of the first signal line is located in the first main display area, and is used for providing driving signals to the pixel driving circuit located in the same sub-pixel column as the first pixel driving circuit; the second signal line extends along the column direction, and The second signal line is at least partially located in the second main display area, and is used for providing driving signals to pixel driving circuits located in the same sub-pixel column as the first pixel driving circuit; the third signal line is connected to the The first signal lines are located in different conductive layers, the third signal lines and the second signal lines are located in different conductive layers, and the third signal lines are respectively connected to the first signal lines and the second signal lines through via holes.
  • the display panel further includes a first wiring area; the first wiring area is located on a side of the first transition display area away from the light-transmitting area; the first wiring area A main display area is also located on one side of the first wiring area in the column direction, and the second main display area is also located on the other side of the first wiring area in the column direction; the third At least part of the signal line is located in the first wiring area.
  • the display panel further includes: a second light-emitting unit, a second pixel driving circuit, a fourth signal line, a fifth signal line, and a sixth signal line.
  • the second light-emitting unit is located in the first wiring area;
  • the second pixel driving circuit is located in the first transition display area, and is used for providing driving current to the second light-emitting unit;
  • the fourth signal line extends along the column direction, and At least part of the fourth signal line is located in the first main display area, and is used for providing driving signals to pixel driving circuits located in the same sub-pixel column as the second pixel driving circuit;
  • the fifth signal line extends along the column direction , and the fifth signal line is at least partially located in the second main display area, and is used to provide driving signals to the pixel driving circuits located in the same sub-pixel column as the second pixel driving circuit;
  • the sixth signal line is located in the second main display area.
  • the sixth signal line is respectively connected with the fourth signal line and the fifth signal line through
  • the display panel further includes a third sub-pixel, the third sub-pixel is located in the first transition display area, and the third sub-pixel includes: a third light-emitting unit, a third sub-pixel Three pixel driving circuits, the third pixel driving circuit is used to provide driving current to the third light emitting unit; the third sub-pixel, the first pixel driving circuit and the second pixel driving circuit are located in different sub-pixel columns.
  • both the first light-emitting unit and the first pixel driving circuit are multiple, and the first pixel driving circuit and the first light-emitting unit connected thereto are located in the same row, Each of the first pixel driving circuits and the first light emitting units connected thereto are spaced apart by the same sub-pixel columns in the row direction.
  • both the second light-emitting unit and the second pixel driving circuit are multiple, and the second pixel driving circuit and the second light-emitting unit connected thereto are located in the same row, Each of the second pixel driving circuits and the second light emitting units connected thereto are spaced apart by the same sub-pixel columns in the row direction.
  • the first routing area includes an arc-shaped routing area and a straight routing area
  • the arc-shaped routing area is located in the first main display area and the second main display area.
  • the arc shape formed by the arc-shaped routing area is convex along the direction of the first routing area away from the light-transmitting area;
  • the third signal line is located in the The straight line area extends along the column direction, the third signal line extends in the arc line area along the arc extension direction of the arc line area;
  • the sixth signal line extends in the straight line
  • the wiring area extends along the column direction, and the sixth signal line extends in the arc-shaped wiring area along the arc extending direction of the arc-shaped wiring area.
  • the arc-shaped routing area is located at a boundary position of the first routing area.
  • the display panel further includes a second wiring area, and the second wiring area is located on both sides of the light-transmitting area and the first transition display area in the column direction, so The first wiring area and the second wiring area form a rectangle surrounding the first transition display area and the light-transmitting area;
  • the third signal line is also located in the second wiring area, and the The third signal line extends to the second routing area along the column direction, and extends to the first routing area along the row direction;
  • the sixth signal line is also located in the second routing area, the first Six signal lines extend to the second routing area in a column direction, and extend to the first routing area in a row direction.
  • the display panel further includes a second transitional display area, the second transitional display area is adjacently disposed on one side of the second wiring area in the column direction, the second transitional display area
  • the display panel further includes: a fifth light-emitting unit and a fifth pixel driving circuit, wherein the fifth light-emitting unit is located in the second wiring area; a fifth pixel driving circuit is located in the second transition display area, and is used for driving the fifth The light-emitting unit provides driving current.
  • the display panel further includes a sixth sub-pixel, the sixth sub-pixel is located in the second transition display area, and the sixth sub-pixel includes: a sixth light-emitting unit, a sixth sub-pixel A six-pixel driving circuit, a sixth pixel driving circuit, is used for providing a driving current to the sixth light-emitting unit; the sixth pixel driving circuit and the fifth pixel driving circuit are located in different sub-pixel columns.
  • the fifth pixel driving circuit and the fifth light-emitting unit are multiple, and each of the fifth pixel driving circuit and the fifth light-emitting unit connected thereto are in a column Equally spaced rows of subpixels in the direction.
  • the first transition display area includes a first sub-transition display area and a second sub-transition display area, and the second sub-transition display area is located between the first sub-transition display area and the second sub-transition display area. between the first wiring areas; the first pixel driving circuit is located in the first sub-transition display area, and the second pixel driving circuit is located in the second sub-transition display area.
  • the pixel densities of the first main display area and the second main display area are equal, and the pixel densities of the first wiring area, the first transition display area, and the light-transmitting area are equal. equal; the pixel density of the first main display area is greater than the pixel density of the light-transmitting area.
  • pixel densities of the first main display area and the second main display area are equal, and the first wiring area, the first transition display area, the light-transmitting area, the second The pixel density of the wiring area and the second transition display area is the same; the pixel density of the first main display area is greater than the pixel density of the light transmission area.
  • a plurality of transfer wires, the plurality of transfer wires include a plurality of first transfer wires and a plurality of second transfer wires.
  • the display panel further includes: a base substrate, a first conductive layer, a second conductive layer, and a third conductive layer, the first conductive layer is disposed on one side of the base substrate, and at least part of the first conductive layer is used for forming the first patch cord; a second conductive layer is disposed on the side of the first conductive layer away from the base substrate, and at least part of the second conductive layer is used to form the second patch cord; the third Three conductive layers are disposed on the side of the second conductive layer away from the base substrate, and at least part of the third conductive layer is used to form the first signal line, the second signal line, and the fourth signal line , the fifth signal line; wherein, the orthographic projection of the first switching wire on the base substrate and the orthographic projection of the second switching wire on the base substrate are alternately distributed in turn in the vertical direction of its extension direction .
  • the display panel further includes: a seventh signal line, an eighth signal line, and a ninth signal line, where the seventh signal line extends along the row direction and is located far from the first wiring area On one side of the light-transmitting area, the seventh signal line is formed by part of the first conductive layer or part of the second conductive layer; the eighth signal line extends along the row direction and is at least partially located in the first conductive layer In the transition display area, the eighth signal line is formed by part of the first conductive layer or part of the second conductive layer; the ninth signal line extends along the row direction and is located in the first routing area, the ninth signal line extends in the row direction The signal line is formed by part of the third conductive layer, and the ninth signal line is respectively connected to the seventh signal line and the eighth signal line through via holes.
  • the display panel includes a driving transistor and a capacitor connected to the gate of the driving transistor; part of the first conductive layer is used to form the gate of the driving transistor, and part of the first conductive layer is used to form the gate of the driving transistor, and part of the The second conductive layer is used to form an electrode of the capacitor; the first signal line, the second signal line, the fourth signal line, and the fifth signal line are used to provide data signals to the gate of the driving transistor.
  • the display panel further includes a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the base substrate, at least part of the fourth conductive layer for forming the anodes of the first light-emitting unit and the second light-emitting unit.
  • the display panel further includes a fifth transparent conductive layer, the fifth transparent conductive layer is located between the third conductive layer and the fourth conductive layer, and the fifth transparent conductive layer is located between the third conductive layer and the fourth conductive layer.
  • the layer includes a first connection line for connecting the first pixel driving circuit and the anode of the first light-emitting unit, and connecting the second pixel driving circuit and the second light-emitting unit anode.
  • the third signal line is located in the first transition display area.
  • the display panel further includes: a base substrate, a third conductive layer, and a fourth conductive layer, wherein the third conductive layer is disposed on one side of the base substrate, and at least part of the The third conductive layer is used to form the first signal line and the second signal line; the fourth conductive layer is located on the side of the third conductive layer away from the base substrate, at least part of the fourth conductive layer and at least part of the fourth conductive layer is used to form the third signal line.
  • a display device comprising: the above-mentioned display panel and a camera, wherein the camera is directly opposite to a light-transmitting area of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel in the related art
  • Fig. 2 is a partial enlarged view of the dotted line frame A in Fig. 1;
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure
  • FIG. 4 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a first pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 11 is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 10;
  • FIG. 12 is a structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • Fig. 13 is the structural layout of the active layer in Fig. 12;
  • Fig. 14 is the structural layout of the first conductive layer in Fig. 12;
  • Fig. 15 is the structural layout of the second conductive layer in Fig. 12;
  • FIG. 16 is a structural layout of the third conductive layer in FIG. 12 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a schematic structural diagram of a display panel in the related art
  • FIG. 2 is a partial enlarged view of the dotted frame A in FIG. 1
  • the display panel includes a main display area 01 , a light-transmitting area 03 , and a transition display area 02 .
  • the sub-pixel P with the light-emitting unit and the pixel driving circuit D without the light-emitting unit are provided in the transition display area 02 of the display panel.
  • the display panel can provide driving current to the light-emitting unit A located in the light-transmitting area 03 through the pixel driving circuit D located in the transition display area 02 . Since the light-transmitting area 03 is not provided with a pixel driving circuit, the light-transmitting area has a higher light transmittance. As shown in FIG. 2 , in order to realize normal driving, the data line d8 located in the same sub-pixel column as the light-emitting unit A needs to be connected to the pixel driving circuit D that provides the driving current to the light-emitting unit A. In the related art, the way in which the data line d8 is connected to the pixel driving circuit D in the transition display area 02 can be as shown in FIG.
  • the data line d8 bypasses the hub area B, and is connected through the gate line g located in the edge routing area.
  • the data line d7 is located in the transition display area 02 , wherein the data line d7 is connected to the pixel driving circuit D in the transition display area 02 .
  • the side of the transition display area 02 away from the main display area 01 also needs to set the main display area, as shown in FIG. The main display area on one side.
  • the data line d7 and part of the data line d2 are located in the same sub-pixel column, and the data line d7 and the data line d2 located in the same sub-pixel column are prone to signal crosstalk.
  • the present exemplary embodiment provides a display panel, as shown in FIG. 3 , which is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure.
  • the display panel may include a light-transmitting area 1, a first transition display area 2, a first wiring area 3, a first main display area 41, and a second main display area 42; the first transition display area 2 is located in the On both sides of the light transmission area 1 in the row direction Y, the first wiring area 3 is located on the side of the first transition display area 2 away from the light transmission area 1; the first main display area 41 is located at the side of the first transition display area 2 away from the light transmission area 1;
  • the light-transmitting area 1, the first transition display area 2, and the first wiring area 3 are on one side of the column direction X, and the second main display area 42 is located in the light-transmitting area 1 and the first transition display area.
  • the display panel further includes: a first light-emitting unit A1, a first pixel driving circuit D1, a first signal line d1, a second signal line d2, and a third signal line g3.
  • the first light-emitting unit A1 may be located in the light-transmitting area 1; the first pixel driving circuit D1 may be located in the first transition display area 2, and the first pixel driving circuit D1 may be used to provide driving for the first light-emitting unit A1 current.
  • the first signal line d1 may extend along the column direction X, and at least part of the first signal line d1 is located in the first main display area 41, and is used to be located in the same sub-pixel column as the first pixel driving circuit D1.
  • the pixel driving circuit provided by the pixel driving circuit provides driving signals;
  • the second signal line d2 may extend along the column direction X, and the second signal line d2 is at least partially located in the second main display area 42 for driving the first pixel and the
  • the circuit D1 is located in the pixel driving circuit of the same sub-pixel column to provide driving signals; at least part of the third signal line g3 may be located in the first wiring area 3, and the third signal line d3 may pass through the via hole 81 and the The first signal line d1 and the second signal line d2 are connected.
  • the first signal line d1 and the second signal line d2 may be data signal lines.
  • the third signal line g3 and the first signal line d1 may be located in a different conductive layer, and the third signal line g3 and the second signal line d2 may be located in a different conductive layer.
  • the first signal line d1 and the second signal line d2 are connected by the third signal line g3 located in the first wiring area 3, which avoids the sub-region where the first pixel driving circuit D1 in the first transition display area 2 is located.
  • Two data lines appear in the pixel column, thereby avoiding signal crosstalk between the two data lines with close spacing.
  • the first area is located on one side of the second area in the column direction
  • the area through which the first area moves in the column direction covers the second area .
  • the display panel may further include a signal line d7 and a signal line d8, the signal line d7 may be at least partially located in the first transition display area 2, and the signal line d7 may be used to connect the first pixel driver In the circuit D1, at least part of the signal line d8 may be located in the second main display area 42, and the signal line d8 may be used to provide driving signals (eg, data signals) to sub-pixel units located in the same sub-pixel column as the first light-emitting unit A1.
  • the signal line d7 and the signal line d8 in this exemplary embodiment may have the same connection structure as the signal line d7 and the signal line d8 in FIG.
  • the gate line g may be located between the first main display area 41 and the light-transmitting area 1 .
  • the gate line g may be located on a different conductive layer from the signal line d7, and the gate line g may be located on a different conductive layer from the signal line d8.
  • FIG. 4 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the gate line g may also be formed in the first transition display area 2 , and at least part of the sub-pixel rows in the first transition display area 2 may be correspondingly provided with a gate line g.
  • the third signal line g3 may also be located in other regions.
  • FIG. 5 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the display panel may not be provided with the first wiring area, and at least part of the third signal line g3 may be located in the first transition display area 2 .
  • the signal line d7 may be located in the same conductive layer as the first signal line d1 and the second signal line d2.
  • the third signal line g3 and the first signal line d1 are located in different conductive layers
  • the third signal line g3 and the second signal line d2 are located in different conductive layers, therefore, the third signal line g3 and the signal line d7 are located in different conductive layers, so this arrangement can also reduce the signal crosstalk between the third signal line g3 and the signal line d7.
  • the display panel may further include: a second light emitting unit A2, a second pixel driving circuit D2, a fourth signal line d4, a fifth signal line d5, and a sixth signal line g6.
  • the second light-emitting unit A2 may be located in the first wiring area 3; the second pixel driving circuit D2 may be located in the first transition display area 2, and the second pixel driving circuit D2 may be used to transmit the signal to the second light-emitting unit A2 provide drive current.
  • the fourth signal line d4 may extend along the column direction X, and at least part of the fourth signal line d4 is located in the first main display area 41, and is used to be located in the same sub-pixel column as the second pixel driving circuit D2.
  • the pixel driving circuit provided by the pixel driving circuit provides driving signals; the fifth signal line d5 may extend in the column direction, and at least part of the fifth signal line d5 may be located in the second main display area 42 for driving the second pixel and the second pixel.
  • Circuit D2 is located in the pixel driving circuit of the same sub-pixel column to provide driving signals; at least part of the sixth signal line g6 may be located in the first routing area 3, and the sixth signal line g6 may be connected to the sixth signal line g6 through a via hole respectively.
  • the four signal lines d4 and the fifth signal line d5 are connected.
  • the fourth signal line d4 and the fifth signal line d5 may be data lines, the sixth signal line g6 and the fourth signal line d4 may be located in different conductive layers, and the sixth signal line g6 and the fifth signal line d5 may be located in different conductive layers layer, the fourth signal line d4 and the fifth signal line d5 may be located in the same conductive layer.
  • the sixth signal line g6 may also be located in the first transition display area 2, and the sixth signal line g6 may extend along the column direction X to directly connect the fourth signal line d4 and the Five signal lines d5.
  • the second light-emitting unit can be provided in the first wiring area, and no pixel driving circuit is provided, and the display panel drives the second light-emitting unit through the second pixel driving circuit D2 located in the first transition display area 2 Unit A2.
  • the display panel can ensure that the first wiring area 3 emits light normally without affecting the normal wiring of the third signal line g3 and the sixth signal line g6 in the first wiring area 3 .
  • the first transitional display area 2 may include a first sub-transitional display area 201 and a second sub-transitional display area 202, and the second sub-transitional display area 202 may be located in Between the first sub-transition display area 201 and the first wiring area 3; the first pixel driving circuit D1 may be located in the first sub-transition display area 201, and the second pixel driving circuit D2 may be in the second sub-transition display area 202 .
  • This arrangement enables the first light-emitting unit A1 to be connected to the pixel driving circuit in the first sub-transition display area 201 that is closer to it, thereby reducing the resistance caused by the conductive line between the first light-emitting unit A1 and the first pixel driving circuit D1.
  • this setting allows the second light-emitting unit A2 to be connected to the pixel driving circuit in the second sub-transition display area 202 that is closer to it, thereby reducing the amount of damage caused by the second light-emitting unit A2 and the second pixel driving circuit D2. Voltage drop caused by resistance of conductors between wires.
  • the display panel may further include a third sub-pixel P3, the third sub-pixel P3 may be located in the first transition display area 2, and the third sub-pixel P3 may be located in the first transition display area 2.
  • the sub-pixel P3 may include a third light-emitting unit and a third pixel driving circuit, and the third pixel driving circuit may be configured to provide a driving current to the third light-emitting unit.
  • the display panel may further include a data line d6 located in the same sub-pixel column as the third sub-pixel P3, the data line d6 may extend along the column direction, and extend through the first transition display area in the column direction to extend to the first main display area and the second main display area, so that the data line d6 can provide data signals to the pixel driving circuits located in the same sub-pixel column as the third sub-pixel P3.
  • the third sub-pixel may be located in a different sub-pixel column from the first pixel driving circuit and the second pixel driving circuit.
  • This setting can make the data line d6 for connecting the third sub-pixel P3, the data line for connecting the first pixel driving circuit D1 and the data line for connecting the second pixel driving circuit D2 to be located in different sub-pixel columns, thereby avoiding A plurality of data lines are located in the same sub-pixel column.
  • both the first light-emitting unit A1 and the first pixel driving circuit D1 may be multiple, and the first pixel driving circuit D1 and the The first light-emitting units A1 may be located in the same row, and each of the first pixel driving circuits D1 and the first light-emitting units A1 connected thereto may be spaced apart by the same sub-pixel column in the row direction. That is, each of the first pixel driving circuits D1 and the first light emitting units A1 connected thereto may be spaced apart by the same distance in the row direction.
  • This setting can make the second connecting lines 72 for connecting the first pixel driving circuit D1 and the first light emitting unit A1 to have the same length, that is, each connecting line has the same voltage drop under the action of the same voltage, thereby making the display panel Can have better display uniformity.
  • the second light-emitting unit A2 and the second pixel driving circuit D2 may be multiple, and the second pixel driving circuit D2 and the second light-emitting unit A2 connected thereto may be located at In the same row, each of the second pixel driving circuits D2 and the second light emitting units A2 connected thereto may be spaced apart by the same sub-pixel columns in the row direction. That is, each of the second pixel driving circuits D2 and the second light emitting units A2 connected thereto may be spaced apart by the same distance in the row direction.
  • This setting can make the first connecting lines 71 for connecting the second pixel driving circuit D2 and the second light emitting unit A2 to have the same length, that is, each connecting line has the same voltage drop under the action of the same voltage, so that the display panel Can have better display uniformity.
  • the first routing area 3 may include an arc-shaped routing area 301 and a straight routing area 302, and the arc-shaped routing area 301 may be located in the first main display area 41 and the second main display area 42
  • the arc shape formed by the arc-shaped wiring area 301 may protrude along the direction in which the first wiring area 3 is away from the light-transmitting area 1 .
  • the third signal line g3 may extend along the column direction X in the straight line area 302 , and the third signal line g3 may extend along the arc line area 301 in the arc line area 301 .
  • the arc extension direction extends.
  • the sixth signal line g6 may extend along the column direction in the straight line area 302 , and the sixth signal line g6 may be routed along the arc in the arc line area 301 The arc-shaped extension direction of the zone extends.
  • the third signal line g3 may be connected to the first signal line d1 and the second signal line d2 through the via hole 81 respectively.
  • the sixth signal line g6 may also be connected to the fourth signal line d4 and the fifth signal line d5 through the via hole 82, respectively.
  • the vias 81 and 82 may be disposed near the edges of the first routing area 3 in the column direction, for example, the vias 81 and 82 may be disposed at the edges of the first routing area 3 on both sides in the column direction.
  • the arc-shaped routing area 301 may be located at the boundary position of the first routing area 3 .
  • the light-transmitting area 1 may be circular
  • the first transition display area 2 may include a boundary 203 facing the side of the light-transmitting area 1
  • the boundary 203 may be a straight line
  • the straight line where the boundary 203 is located may be related to the circle.
  • Shaped light-transmitting area 1 is tangent.
  • the arc-shaped routing area 301 may extend to the straight line where the boundary 203 is located.
  • the display panel may further include a third transition display area 53 surrounding the light-transmitting area 1 .
  • the pixel density of the first main display area 41 and the second main display area 42 may be equal, the first wiring area 3 , the first transition display area 2 , the light transmission area 1 , and the third transition display area 53
  • the pixel density can be equal.
  • the pixel density of the first main display area 41 may be greater than the pixel density of the light transmission area 1 .
  • FIG. 8 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the display panel may further include a second wiring area 6, and the second wiring area 6 may be located on both sides of the light-transmitting area 1 and the first transition display area 2 in the column direction X, and the first The wiring area 3 and the second wiring area 6 may form a rectangle surrounding the first transition display area 2 and the light-transmitting area 1 .
  • the third signal line g3 may also be located in the second wiring region 6, and the third signal line g3 may extend to the second wiring region 6 along the column direction X, and extend to the second wiring region 6 along the row direction Y.
  • the first wiring area 3; the sixth signal line g6 may also be located in the second wiring area 6, and the sixth signal line g6 may extend to the second wiring area 6 along the column direction X, And it extends to the first wiring area 3 along the row direction Y.
  • the third signal line g3 may be connected to the first signal line d1 and the second signal line d2 through the via hole 81 respectively.
  • the sixth signal line g6 may also be connected to the fourth signal line d4 and the fifth signal line d5 through the via hole 82, respectively.
  • the vias 81 and 82 can be arranged near the edge of the second wiring area 6 away from the light-transmitting area 1 .
  • the vias 81 and 82 can be arranged on the side of the second wiring area 6 away from the light-transmitting area 1 . edge position.
  • the display panel may further include a fourth transition display area 54 surrounding the light-transmitting area 1 .
  • the pixel densities of the first main display area 41 and the second main display area 42 may be equal, and the first wiring area 3 , the first transition display area 2 , and the light-transmitting area 1 , the pixel density of the second wiring area 6 and the fourth transition display area 54 may be the same.
  • the pixel density of the first main display area 41 may be greater than the pixel density of the light transmission area 1 .
  • FIG. 9 it is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • the display panel may further include a second transitional display area 7, and the second transitional display area 7 is disposed adjacent to one side of the second wiring area 6 in the column direction.
  • the display panel may further include: a fifth light-emitting unit A5, a fifth pixel driving circuit D5, the fifth light-emitting unit A5 may be located in the second wiring area 6; the fifth pixel driving circuit D5 may be located in the second transition In the display area 7, the fifth pixel driving circuit D5 can be used to provide a driving current to the fifth light-emitting unit.
  • the display panel can ensure that the second wiring area 6 emits light normally without affecting the normal wiring of the third signal line g3 and the sixth signal line g6 in the second wiring area 6 .
  • the display panel further includes a sixth sub-pixel P6, the sixth sub-pixel P6 may be located in the second transition display area 7, and the sixth sub-pixel P6
  • a sixth light-emitting unit and a sixth pixel driving circuit may be included, and the sixth pixel driving circuit may be configured to provide a driving current to the sixth light-emitting unit.
  • the sixth sub-pixel P6 and the fifth pixel driving circuit may be located in different sub-pixel columns. This arrangement can make the data line for connecting the fifth pixel driving circuit D5 and the data line for connecting the sixth sub-pixel P6 to be located in different sub-pixel columns, thereby avoiding overlapping of the two data lines in the same sub-pixel column.
  • the fifth pixel driving circuit D5 can also be located in a different sub-pixel column from the first pixel driving circuit D1, so that the data lines used to connect the fifth pixel driving circuit D5 can extend through the second wiring area and the second transition display area respectively to A first main display area and a second main display area.
  • the sixth sub-pixel P6 can also be located in a different sub-pixel column from the first pixel driving circuit, so that the data line for connecting the sixth sub-pixel P6 can extend through the second wiring area and the second transition display area to the first main display area and the second main display area.
  • the second transition display area 7 may be adjacently disposed on the side of the second wiring area away from the light-transmitting area 1. It should be understood that in other exemplary embodiments, the second transition display area 7 can also be adjacently disposed on the side of the second wiring area facing the light-transmitting area 1 .
  • the fifth pixel driving circuit D5 and the fifth light-emitting unit A5 may be multiple, and each of the fifth pixel driving circuit D5 and the fifth light-emitting unit A5 connected thereto
  • the same sub-pixel rows may be spaced in the column direction. That is, each of the fifth pixel driving circuits D5 and the fifth light-emitting units A5 connected thereto may be spaced apart by the same distance in the row direction.
  • This setting can make the connecting lines 73 connected between the five-pixel driving circuit D5 and the fifth light-emitting unit A5 have the same length, and each connecting line 73 has the same voltage drop under the action of the same voltage, so that the display panel can have the same length. Better display uniformity.
  • the light-transmitting area 1 may be circular. It should be understood that, in other exemplary embodiments, the light-transmitting area 1 may also be rectangular or elliptical. and other shapes.
  • FIG. 10 it is a schematic structural diagram of a first pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first pole of the first transistor T1 is connected to the node N, the second pole is connected to the initialization signal terminal Vinit, and the gate is connected to the reset signal terminal Re; the first pole of the second transistor T2 is connected to the first pole of the driving transistor T3, and the second pole is connected
  • the gate is connected to the gate driving signal terminal Gate; the gate of the driving transistor T3 is connected to the node N; the first pole of the fourth transistor T4 is connected to the data signal terminal Da, and the second pole is connected to the second pole of the driving transistor T3, The gate is connected to the gate driving signal terminal Gate;
  • the first pole of the fifth transistor T5 is connected to the first power supply signal terminal VDD, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the sixth transistor The first pole of T6 is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first pole of the seventh transistor T7 is connected to the initialization signal terminal Vinit, and
  • the pixel driving circuit may be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power terminal VSS.
  • the transistors T1-T7 may all be P-type transistors.
  • Other pixel driving circuits in the display panel may have the same structure as the first pixel driving circuit.
  • FIG. 11 it is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 10 .
  • Gate represents the timing of the gate driving signal terminal Gate
  • Re represents the timing of the reset signal terminal Re
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.
  • the reset signal terminal Re outputs a low level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the initialization signal terminal Vinit inputs the initialization signal to the node N and the second pole of the sixth transistor T6.
  • the gate driving signal terminal Gate outputs a low level signal
  • the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da outputs a driving signal to write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the output current I ( ⁇ WCox/2L)(Vdata+Vth ⁇ Vdd ⁇ Vth) 2 of the driving transistor in the pixel driving circuit of the present disclosure.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the display panel may include a base substrate 0, an active layer, a first conductive layer, a second conductive layer, and a third conductive layer that are stacked in sequence. 12 , 13 , 14 , 15 and 16
  • FIG. 12 is a structural layout of an exemplary embodiment of a display panel of the present disclosure
  • FIG. 13 is a structural layout of the active layer in FIG. 12
  • FIG. 15 is the structural layout of the second conductive layer in FIG. 12
  • FIG. 16 is the structural layout of the third conductive layer in FIG. 12 .
  • the active layer may include a first active part 61 , a second active part 62 , a third active part 63 , a fourth active part 64 , a fifth active part 65 , a sixth active part
  • the active part 66 the seventh active part 67 , the eighth active part 68 , the tenth active part 610 , the eleventh active part 611 , the twelfth active part 612 , and the thirteenth active part 613 .
  • the second active part 62 can be used to form the first channel region of the second transistor T2
  • the third active part 63 can be used to form the second channel of the second transistor T2 Area.
  • the sixth active part 66 may be used to form the channel region of the driving transistor T3.
  • the seventh active part 67 may be used to form the first channel region of the first transistor T1, and the eighth active part 68 may be used to form the second channel region of the first transistor T1.
  • the tenth active part 610 may be used to form a channel region of the fourth transistor T4.
  • the eleventh active part 611 may be used to form a channel region of the fifth transistor T5.
  • the twelfth active part 612 may be used to form a channel region of the sixth transistor T6.
  • the thirteenth active part 613 may be used to form the channel region of the seventh transistor.
  • the fourth active part 64 may be connected between the second active part 62 and the third active part 63 .
  • the first conductive layer may include: a first conductive portion 11 , a second conductive portion 12 , a first grid line 13 , a second grid line 14 , a third grid line 17 , and a sixth conductive portion Section 16.
  • the first conductive portion 11 may also be a strip-shaped structure extending along the row direction Y, and the orthographic projection of the first conductive portion 11 on the base substrate may cover the orthographic projection of the sixth active portion 66 on the base substrate to form a driving transistor.
  • Gate of T3 The second conductive portion 12 may be used to form part of the first electrode of the capacitor C.
  • the first gate line 13 may be used to provide the gate driving signal terminal in FIG. 10 .
  • the orthographic projection of the first grid line 13 on the base substrate may extend along the row direction Y, and the orthographic projection of the first grid line 13 on the base substrate may be located at the position of the first conductive portion 11 .
  • a part of the conductive portion 131 of the first gate line 13 may be used to form the second conductive portion of the second transistor T2.
  • a gate, part of the conductive portion 134 of the first gate line 13 can be used to form the gate of the fourth transistor T4.
  • the second gate line 14 may be used to provide the reset signal terminal in FIG. 10 .
  • the orthographic projection of the second grid line 14 on the base substrate extends along the row direction Y, and the orthographic projection of the second grid line 14 on the base substrate may be located on the second conductive portion 12 in the
  • the orthographic projection of the base substrate is away from the orthographic projection of the first gate line 13 on the side of the base substrate, and part of the conductive portion 141 of the second gate line 14 can be used to form the first gate line of the first transistor T1.
  • the gate, part of the conductive portion 142 of the second gate line 14 can be used to form the second gate of the first transistor T1.
  • the third gate line 17 may be used to provide the enable signal terminal in FIG. 10 .
  • the orthographic projection of the third grid line 17 on the base substrate may be located on the side of the orthographic projection of the first conductive portion 11 on the base substrate away from the orthographic projection of the first grid line 13 on the base substrate.
  • the third gate line 17 may include a conductive portion 175 and a conductive portion 176, the conductive portion 175 may be used to form the gate of the fifth transistor, and the conductive portion 176 may be used to form the gate of the sixth transistor.
  • the gate of the seventh transistor T7 may share the conductive portion 147 in the second gate line 14 corresponding to the next row of pixel units.
  • the orthographic projection of the sixth conductive portion 16 on the base substrate may extend along the column direction X and be connected to the first gate line 13 , and part of the sixth conductive portion 16 may be used to form the first gate of the second transistor T2 . Two gates.
  • the second conductive layer may include a third conductive portion 23 , and the orthographic projection of the third conductive portion 23 on the base substrate may be the same as that of the second conductive portion 12 on the base substrate.
  • the orthographic projections at least partially overlap, and the third conductive portion 23 is electrically connected to the first conductive portion 11 , and the third conductive portion 23 can be used to form the second electrode of the capacitor C.
  • the third conductive layer may include a fourth conductive part 34 , a first connection part 31 , a power line 321 , a fifth conductive part 35 , seven conductive parts 37 , a second connection part 39 , and a third connection part 310 , data line 311 .
  • the fifth conductive part 35 may be connected between the fourth conductive part 34 and the power line 321 .
  • the orthographic projection of the fourth conductive portion 34 on the base substrate may at least partially overlap with the orthographic projection of the third conductive portion 23 on the base substrate, and the fourth conductive portion 34 may be connected to the base substrate through the via hole 93 .
  • the second conductive portion 12 is electrically connected, and the fourth conductive portion 34 may be used to form part of the first electrode of the capacitor C.
  • the orthographic projection of the fifth conductive portion 35 on the base substrate at least partially coincides with the orthographic projection of the first active portion 61 on the base substrate.
  • the seventh conductive portion 37 can be connected to the fourth conductive portion 34, and the orthographic projection of the seventh conductive portion 37 on the base substrate and the orthographic projection of the fourth active portion 64 on the base substrate at least partially overlap.
  • the second connection part 39 may connect the active layer on the side of the eighth active part 68 through the via hole 96 to connect the second electrode of the first transistor T1.
  • the third connection part 310 may connect the active layer between the twelfth active part 612 and the thirteenth active part 613 through the via hole 97 to connect the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 Diode.
  • the first pole of the seventh transistor T7 may be connected to the second connection part 39 in the next row of pixel units.
  • the data line 311 may be connected to the first electrode of the fourth transistor T4 through the via hole 98 .
  • the first connection part 31 can be electrically connected to the first conductive part 11 through the via hole 92 , and the first connection part 31 can be electrically connected to the second sub-conductive part 232 through the via hole 91 .
  • the fifth active part 65 may be electrically connected to the first connection part 31 through the via hole 95 , so that the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor.
  • the display panel may further include a fifth transparent conductive layer on the side of the third conductive layer away from the base substrate, and a fourth conductive layer on the side of the fifth transparent conductive layer away from the base substrate,
  • the organic light-emitting layer located on the fourth conductive layer away from the base substrate, the fourth conductive layer can be used to form the anode of the light-emitting unit, and the organic light-emitting layer can be used to form the light-emitting layer of the light-emitting unit.
  • the first pixel driving circuit may also have other structures, and correspondingly, the display panel may also have other corresponding layout structures.
  • the third signal line g3 and the sixth signal line g6 may be located in any one or two layers of the above-mentioned first conductive layer and second conductive layer.
  • the number of the third signal lines may be multiple
  • the number of the sixth signal lines may be multiple
  • the multiple third signal lines and the multiple sixth signal lines may be formed
  • a plurality of transfer wires, the plurality of transfer wires include a plurality of first transfer wires and a plurality of second transfer wires.
  • At least part of the first conductive layer is used to form the first patch cord; at least part of the second conductive layer is used to form the second patch cord; wherein, the first patch cord is formed on the base substrate
  • the orthographic projection of and the orthographic projection of the second patch wire on the base substrate may be alternately distributed in sequence in the vertical direction of the extending direction thereof.
  • the display panel arranges a plurality of patch lines on different conductive layers, so that the integration degree of the patch cables can be increased, that is, more third signal lines g3 and sixth signal lines g6 can be integrated in a limited size in the column direction.
  • the third conductive layer may be used to form the first signal line d1 , the second signal line d2 , the fourth signal line d4 , the Five signal lines d5.
  • the first signal line d1 , the second signal line d2 , the fourth signal line d4 , and the fifth signal line d5 may all be data lines, that is, the data line 311 in FIG. 16 .
  • the connection lines 72 and 71 may be formed by part of the fifth transparent conductive layer.
  • the connection line 73 may be formed of part of the anode layer.
  • the third signal line g3 may be formed of a part of the anode layer.
  • the transition line formed by the third signal line g3 or the sixth signal line g6 is located in the first conductive layer and extends in the column direction.
  • the first gate line 13 , the second gate line 14 and the third gate line 17 are located in the first conductive layer and extend in the row direction. Therefore, the above-mentioned transition line may intersect with the above-mentioned gate line, thus causing the display panel to fail to display normally.
  • the display panel further includes: a seventh signal line g7, an eighth signal line g8, and a ninth signal line d9
  • the seventh signal line g7 may extend in the row direction, and Located on the side of the first wiring area 3 away from the light-transmitting area 1, the seventh signal line g7 may be formed by part of the first conductive layer or part of the second conductive layer; the eighth signal line The g8 may extend in the row direction and be at least partially located in the first transition display area, the eighth signal line g8 may be formed by part of the first conductive layer or part of the second conductive layer; the ninth signal line d9 It can extend in the row direction and is located in the first routing area 3, the ninth signal line d9 can be formed by a part of the third conductive layer, and the ninth signal line d9 can be respectively connected with all the through holes 83.
  • the seventh signal line g7 and the eighth signal line g8 are connected.
  • the interconnected seventh signal line g7 , eighth signal line g8 , and ninth signal line d9 may form the above-mentioned first gate line 13 , second gate line 14 , and third gate line 17 .
  • the vias 83 may be disposed near the edges of the first wiring area 3 on both sides in the column direction.
  • the vias 83 may be disposed at the edges of the first wiring area 3 on both sides in the column direction.
  • the seventh signal line g7 and the eighth signal line g8 are switched through the ninth signal line d9 located in the third conductive layer, thereby avoiding the connection between the gate line and the first wiring area 3 in the display panel.
  • the third signal line or the sixth signal line intersects.
  • the present exemplary embodiment also provides a display device, the display device comprising: the above-mentioned display panel and a camera, wherein the camera is directly opposite to the light-transmitting area of the display panel.
  • the display device may be a display device such as a mobile phone, a tablet computer, or the like.

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Abstract

一种显示面板、显示装置。显示面板包括透光区（1）、第一过渡显示区（2）、第一主显示区（41）、第二主显示区（42）。显示面板还包括：第一发光单元（A1）、第一像素驱动电路（D1）、第一信号线（d1）、第二信号线（d2）、第三信号线（g3）。第一发光单元（A1）位于透光区（1）；第一像素驱动电路（D1）位于第一过渡显示区（2），用于向第一发光单元（A1）提供驱动电流；第一信号线（d1）沿列方向（X）延伸，且位于第一主显示区（41）；第二信号线（d2）沿列方向（X）延伸，且位于第二主显示区（42）；第三信号线（g3）与第一信号线（d1）位于不同导电层，第三信号线（g3）与第二信号线（d2）位于不同导电层，且第三信号线（g3）分别通过过孔（81）与第一信号线（d1）、第二信号线（d2）连接。该显示面板的透光区（1）在列方向（X）上的两侧均设置有主显示区。

Description

显示面板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示装置。
背景技术
屏下摄像头技术是在显示面板上设置透光区，将摄像头与透光区正对设置，从而实现全屏显示。相关技术中，为了提高透光区的透光率，通常在透光区中仅设置发光单元，在透光区行方向的两侧设置过渡显示区，在过渡显示区中设置用于驱动该发光单元的像素驱动电路。与透光区中发光单元位于同一子像素列的数据线需要通过绕线的方式连接位于过渡显示区中的像素驱动电路。然而，当透光区的周围均环绕有主显示区时，过渡显示区在列方向上的两侧也均设置有主显示区，位于过渡显示区一侧主显示区中的数据线需要贯穿过渡显示区以延伸至过渡显示区另一侧的主显示区。然而，贯穿过渡显示区的数据线容易与上述通过绕线方式连接于过渡显示区的数据线发生串扰。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种显示面板，所述显示面板包括透光区、第一过渡显示区、第一主显示区、第二主显示区；所述第一过渡显示区位于所述透光区在行方向上的两侧；所述第一主显示区位于所述透光区、第一过渡显示区在列方向上的一侧，所述第二主显示区位于所述透光区、第一过渡显示区在列方向上的另一侧；所述显示面板还包括：第一发光单元、第一像素驱动电路、第一信号线、第二信号线、第三信号线。第一发光单元位于所述透光区；第一像素驱动电路位于所述第一过渡显示区，用于向所述第一发光单元提供驱动电流；第一信号线沿列方向延伸，且所述第一信号线的至少部分位于所述第一主显示区，用于向与所述第一像素驱动电路位于同一子像素列的像素驱动电路提供驱动信号；第二信号线沿列方向延伸，且所述第二信号线至少部分位于所述第二主显示区，用于向与所述第一像素驱动电路位于同一子像素列的像素驱动电路提供驱动信号；所述第三信号线与所述第一信号线位于不同导电层，所述第三信号线与第二信号线位于不同导电层，且所述第三信号线分别通过过孔与所述第一信号线、第二信号线连接。
本公开一种示例性实施例中，所述显示面板还包括第一走线区；所述第一走线区位于所述第一过渡显示区远离所述透光区的一侧；所述第一主显示区还位于所述第一走线区在列方向上的一侧，所述第二主显示区还位于所述第一走线区在列方向上的另一侧；所述第三信号线的至少部分位于所述第一走线区。
本公开一种示例性实施例中，所述显示面板还包括：第二发光单元、第二像素驱动电 路、第四信号线、第五信号线、第六信号线。第二发光单元位于所述第一走线区；第二像素驱动电路位于所述第一过渡显示区，用于向所述第二发光单元提供驱动电流；第四信号线沿列方向延伸，且所述第四信号线的至少部分位于所述第一主显示区，用于向与所述第二像素驱动电路位于同一子像素列的像素驱动电路提供驱动信号；第五信号线沿列方向延伸，且所述第五信号线至少部分位于所述第二主显示区，用于向与所述第二像素驱动电路位于同一子像素列的像素驱动电路提供驱动信号；第六信号线位于所述第一走线区，所述第六信号线分别通过过孔与所述第四信号线、第五信号线连接。
本公开一种示例性实施例中，所述显示面板还包括第三子像素，所述第三子像素位于所述第一过渡显示区，所述第三子像素包括：第三发光单元、第三像素驱动电路，第三像素驱动电路用于向所述第三发光单元提供驱动电流；所述第三子像素与所述第一像素驱动电路、第二像素驱动电路均位于不同子像素列。
本公开一种示例性实施例中，所述第一发光单元和所述第一像素驱动电路均为多个，所述第一像素驱动电路和与其连接的所述第一发光单元位于同一行，每个所述第一像素驱动电路和与其连接的所述第一发光单元在行方向上间隔相同子像素列。
本公开一种示例性实施例中，所述第二发光单元和所述第二像素驱动电路均为多个，所述第二像素驱动电路和与其连接的所述第二发光单元位于同一行，每个所述第二像素驱动电路和与其连接的所述第二发光单元在行方向上间隔相同子像素列。
本公开一种示例性实施例中，所述第一走线区包括弧形走线区和直线走线区，所述弧形走线区位于所述第一主显示区和所述第二主显示区之间，且沿弧形延伸，所述弧形走线区所成弧形沿所述第一走线区远离所述透光区的方向凸起；所述第三信号线在所述直线走线区中沿列方向延伸，所述第三信号线在所述弧形走线区中沿所述弧形走线区的弧形延伸方向延伸；所述第六信号线在所述直线走线区中沿列方向延伸，所述第六信号线在所述弧形走线区中沿所述弧形走线区的弧形延伸方向延伸。
本公开一种示例性实施例中，所述弧形走线区位于所述第一走线区的边界位置。
本公开一种示例性实施例中，所述显示面板还包括第二走线区，所述第二走线区位于所述透光区、第一过渡显示区在列方向上的两侧，所述第一走线区和所述第二走线区形成环绕所述第一过渡显示区和所述透光区的矩形；所述第三信号线还位于所述第二走线区，所述第三信号线沿列方向延伸至所述第二走线区，且沿行方向延伸至所述第一走线区；所述第六信号线还位于所述第二走线区，所述第六信号线沿列方向延伸至所述第二走线区，且沿行方向延伸至所述第一走线区。
本公开一种示例性实施例中，所述显示面板还包括第二过渡显示区，所述第二过渡显示区相邻设置于所述第二走线区在列方向上的一侧，所述显示面板还包括：第五发光单元、第五像素驱动电路，第五发光单元位于所述第二走线区；第五像素驱动电路位于所述第二过渡显示区，用于向所述第五发光单元提供驱动电流。
本公开一种示例性实施例中，所述显示面板还包括第六子像素，所述第六子像素位于 所述第二过渡显示区，所述第六子像素包括：第六发光单元、第六像素驱动电路，第六像素驱动电路，用于向所述第六发光单元提供驱动电流；所述第六像素驱动电路与所述第五像素驱动电路位于不同子像素列。
本公开一种示例性实施例中，所述第五像素驱动电路和所述第五发光单元均为多个，每个所述第五像素驱动电路和与其连接的所述第五发光单元在列方向上间隔相同的子像素行。
本公开一种示例性实施例中，所述第一过渡显示区包括第一子过渡显示区和第二子过渡显示区，所述第二子过渡显示区位于所述第一子过渡显示区和所述第一走线区之间；所述第一像素驱动电路位于所述第一子过渡显示区，所述第二像素驱动电路位于所述第二子过渡显示区。
本公开一种示例性实施例中，所述第一主显示区和所述第二主显示区的像素密度相等，所述第一走线区、第一过渡显示区、透光区的像素密度相等；所述第一主显示区的像素密度大于所述透光区的像素密度。
本公开一种示例性实施例中，所述第一主显示区和所述第二主显示区的像素密度相等，所述第一走线区、第一过渡显示区、透光区、第二走线区、第二过渡显示区的像素密度相同；所述第一主显示区的像素密度大于所述透光区的像素密度。
本公开一种示例性实施例中，所述第三信号线为多条，所述第六信号线为多条，多条所述第三信号线和所述多条所述第六信号线形成多条转接线，多条所述转接线包括多条第一转接线和多条第二转接线。所述显示面板还包括：衬底基板、第一导电层、第二导电层、第三导电层，第一导电层设置于所述衬底基板的一侧，至少部分所述第一导电层用于形成所述第一转接线；第二导电层设置于所述第一导电层背离所述衬底基板的一侧，至少部分所述第二导电层用于形成所述第二转接线；第三导电层设置于所述第二导电层背离所述衬底基板的一侧，至少部分所述第三导电层用于形成所述第一信号线、所述第二信号线、第四信号线、第五信号线；其中，所述第一转接线在所述衬底基板的正投影与所述第二转接线在所述衬底基板的正投影在其延伸方向的垂直方向上依次交替分布。
本公开一种示例性实施例中，所述显示面板还包括：第七信号线、第八信号线、第九信号线，第七信号线沿行方向延伸，位于所述第一走线区远离所述透光区的一侧，所述第七信号线由部分所述第一导电层或部分所述第二导电层形成；第八信号线沿行方向延伸，且至少部分位于所述第一过渡显示区，所述第八信号线由部分所述第一导电层或部分所述第二导电层形成；第九信号线沿行方向延伸，位于所述第一走线区，所述第九信号线由部分所述第三导电层形成，所述第九信号线通过过孔分别与所述第七信号线、第八信号线连接。
本公开一种示例性实施例中，所述显示面板包括驱动晶体管，以及连接于所述驱动晶体管栅极的电容；部分所述第一导电层用于形成所述驱动晶体管的栅极，部分所述第二导电层用于形成所述电容的一电极；所述第一信号线、第二信号线、第四信号线、第五信号 线用于向所述驱动晶体管的栅极提供数据信号。
本公开一种示例性实施例中，所述显示面板还包括第四导电层，第四导电层位于所述第三导电层背离所述衬底基板的一侧，至少部分所述第四导电层用于形成所述第一发光单元、第二发光单元的阳极。
本公开一种示例性实施例中，所述显示面板还包括第五透明导电层，第五透明导电层位于所述第三导电层和所述第四导电层之间，所述第五透明导电层包括第一连接线，所述第一连接线用于连接所述第一像素驱动电路和所述第一发光单元的阳极，以及连接所述第二像素驱动电路和所述第二发光单元的阳极。
本公开一种示例性实施例中，所述第三信号线位于所述第一过渡显示区。
本公开一种示例性实施例中，所述显示面板还包括：衬底基板、第三导电层、第四导电层，第三导电层设置于所述衬底基板的一侧，至少部分所述第三导电层用于形成所述第一信号线、所述第二信号线；第四导电层位于所述第三导电层背离所述衬底基板的一侧，至少部分所述第四导电层用于形成所述第一发光单元、第二发光单元的阳极；且至少部分所述第四导电层用于形成所述第三信号线。
根据本公开的一个方面，提供一种显示装置，该显示装置包括：上述的显示面板和摄像头，所述摄像头与所述显示面板的透光区正对。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种显示面板的结构示意图；
图2为图1中的虚线框A处的局部放大图；
图3为本公开显示面板一种示例性实施例的结构示意图；
图4为本公开显示面板另一种示例性实施例的结构示意图；
图5为本公开显示面板另一种示例性实施例中的结构示意图；
图6为本公开显示面板另一种示例性实施例中的结构示意图；
图7为本公开显示面板另一种示例性实施例中的结构示意图；
图8为本公开显示面板另一种示例性实施例中的结构示意图；
图9为本公开显示面板另一种示例性实施例中的结构示意图；
图10为本公开显示面板一种示例性实施例中第一像素驱动电路的结构示意图；
图11为图10像素驱动电路一种驱动方法中各节点的时序图；
图12为本公开显示面板一种示例性实施例的结构版图；
图13为图12中有源层的结构版图；
图14为图12中第一导电层的结构版图；
图15为图12中第二导电层的结构版图；
图16为图12中第三导电层的结构版图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1、2所示，图1为相关技术中一种显示面板的结构示意图，图2为图1中的虚线框A处的局部放大图。如图1、2所示，该显示面板包括主显示区01、透光区03、过渡显示区02。如图2所示，显示面板的透光区03中仅设置有发光单元A，显示面板的过渡显示区02中设置有带有发光单元的子像素P和不带发光单元的像素驱动电路D。该显示面板可以通过位于过渡显示区02中的像素驱动电路D向位于透光区03中的发光单元A提供驱动电流。由于透光区03没有设置像素驱动电路，因而透光区具有较高的透光率。如图2所示，为实现正常驱动，与发光单元A位于同一子像素列的数据线d8需要连接向该发光单元A提供驱动电流的像素驱动电路D。相关技术中，实现数据线d8连接过渡显示区02中的像素驱动电路D的方式可以如图2所示，数据线d8绕过集线区B，从而通过位于边沿走线区的栅线g连接位于过渡显示区02数据线d7，其中数据线d7连接过渡显示区02中的像素驱动电路D。当过渡显示区02远离主显示区01的一侧也需要设置主显示区时，如图2所示，位于主显示区01的数据线d2需要穿过过渡显示区02以连接过渡显示区02另一侧的主显示区。然而，数据线d7和部分数据线d2位于同一子像素列，位于同一子像素列的数据线d7和数据线d2容易发生信号串扰。
基于此，本示例性实施例提供一种显示面板，如图3所示，为本公开显示面板一种示例性实施例的结构示意图。所述显示面板可以包括透光区1、第一过渡显示区2、第一走 线区3、第一主显示区41、第二主显示区42；所述第一过渡显示区2位于所述透光区1在行方向Y上的两侧，所述第一走线区3位于所述第一过渡显示区2远离所述透光区1的一侧；所述第一主显示区41位于所述透光区1、第一过渡显示区2、第一走线区3在列方向X上的一侧，所述第二主显示区42位于所述透光区1、第一过渡显示区2、第一走线区3在列方向X上的另一侧。所述显示面板还包括：第一发光单元A1、第一像素驱动电路D1、第一信号线d1、第二信号线d2、第三信号线g3。第一发光单元A1可以位于所述透光区1；第一像素驱动电路D1可以位于所述第一过渡显示区2，第一像素驱动电路D1可以用于向所述第一发光单元A1提供驱动电流。第一信号线d1可以沿列方向X延伸，且所述第一信号线d1的至少部分位于所述第一主显示区41，用于向与所述第一像素驱动电路D1位于同一子像素列的像素驱动电路提供驱动信号；第二信号线d2可以沿列方向X延伸，且所述第二信号线d2至少部分位于所述第二主显示区42，用于向与所述第一像素驱动电路D1位于同一子像素列的像素驱动电路提供驱动信号；第三信号线g3的至少部分可以位于所述第一走线区3，所述第三信号线d3可以分别通过过孔81与所述第一信号线d1、第二信号线d2连接。其中，第一信号线d1、第二信号线d2可以为数据信号线。第三信号线g3可以与第一信号线d1位于不同导电层，第三信号线g3可以与第二信号线d2位于不同导电层。
本示例性实施例通过位于第一走线区3中的第三信号线g3连接第一信号线d1和第二信号线d2，避免了第一过渡显示区2中第一像素驱动电路D1所在子像素列出现两条数据线，从而避免了间距较近的该两条数据线发生信号串扰。
需要说明的是，本示例性实施例中，关于描述“第一区位于第二区在列方向上的一侧”，可以理解为，第一区在列方向上移动所经过区域覆盖第二区。
本示例性实施例中，如图3所示，显示面板还可以信号线d7和信号线d8，信号线d7至少部分可以位于第一过渡显示区2，信号线d7可以用于连接第一像素驱动电路D1，信号线d8至少部分可以位于第二主显示区42，信号线d8可以用于向与第一发光单元A1位于同一子像素列的子像素单元提供驱动信号(例如数据信号)。本示例性实施例中的信号线d7和信号线d8可以和图2中信号线d7和信号线d8具有相同的连接结构，本示例性实施例中的信号线d7和信号线d8可以通过栅线g连接。其中，栅线g可以位于第一主显示区41和透光区1之间。栅线g可以与信号线d7位于不同导电层，栅线g可以与信号线d8位于不同导电层。
如图4所示，为本公开显示面板另一种示例性实施例的结构示意图。本实施例性实施例中，栅线g还可以形成于第一过渡显示区2中，第一过渡显示区2中的至少部分子像素行可以对应设置一条栅线g。
本示例性实施例中，第三信号线g3还可以位于其他区域。例如，如图5所示，为本公开显示面板另一种示例性实施例的结构示意图。本示例性实施例中，显示面板可以不设置第一走线区，第三信号线g3至少部分可以位于第一过渡显示区2。信号线d7可以与第 一信号线d1、第二信号线d2位于同一导电层，同时由于第三信号线g3与第一信号线d1位于不同导电层，第三信号线g3与第二信号线d2位于不同导电层，因此，第三信号线g3与信号线d7位于不同导电层，从而该设置同样可以降低第三信号线g3和信号线d7之间的信号串扰。
如图6所示，为本公开显示面板另一种示例性实施例的结构示意图。所述显示面板还可以包括：第二发光单元A2、第二像素驱动电路D2、第四信号线d4、第五信号线d5、第六信号线g6。第二发光单元A2可以位于所述第一走线区3；第二像素驱动电路D2可以位于所述第一过渡显示区2，第二像素驱动电路D2可以用于向所述第二发光单元A2提供驱动电流。第四信号线d4可以沿列方向X延伸，且所述第四信号线d4的至少部分位于所述第一主显示区41，用于向与所述第二像素驱动电路D2位于同一子像素列的像素驱动电路提供驱动信号；第五信号线d5可以沿列方向延伸，且所述第五信号线d5至少部分可以位于所述第二主显示区42，用于向与所述第二像素驱动电路D2位于同一子像素列的像素驱动电路提供驱动信号；第六信号线g6的至少部分可以位于所述第一走线区3，所述第六信号线g6可以分别通过过孔与所述第四信号线d4、第五信号线d5连接。其中，第四信号线d4、第五信号线d5可以为数据线，第六信号线g6可以与第四信号线d4位于不同导电层，第六信号线g6可以与第五信号线d5位于不同导电层，第四信号线d4和第五信号线d5可以位于同一导电层。应该理解的是，在其他示例性实施例中，第六信号线g6还可以位于第一过渡显示区2，第六信号线g6可以沿列方向X延伸，以直接连接第四信号线d4和第五信号线d5。
本示例性实施例可以在第一走线区中仅设置第二发光单元，且不设置像素驱动电路，该显示面板通过位于第一过渡显示区2中的第二像素驱动电路D2驱动第二发光单元A2。该显示面板可以在不影响第一走线区3中第三信号线g3和第六信号线g6正常走线的情况下，保证第一走线区3正常发光。
本示例性实施例中，如图6所示，所述第一过渡显示区2可以包括第一子过渡显示区201和第二子过渡显示区202，所述第二子过渡显示区202可以位于所述第一子过渡显示区201和所述第一走线区3之间；所述第一像素驱动电路D1可以位于所述第一子过渡显示区201，所述第二像素驱动电路D2可以位于所述第二子过渡显示区202。该设置可以使得第一发光单元A1可以和与其较近的第一子过渡显示区201中的像素驱动电路连接，从而降低由于第一发光单元A1和第一像素驱动电路D1之间导电线电阻引起的压降，同时该设置可以使得第二发光单元A2可以和与其较近的第二子过渡显示区202中的像素驱动电路连接，从而降低由于第二发光单元A2和第二像素驱动电路D2之间导电线电阻引起的压降。
本示例性实施例中，如图3-6所示，所述显示面板还可以包括第三子像素P3，所述第三子像素P3可以位于所述第一过渡显示区2，所述第三子像素P3可以包括第三发光单元和第三像素驱动电路，第三像素驱动电路可以用于向所述第三发光单元提供驱动电流。该 显示面板还可以包括与第三子像素P3位于同一子像素列的数据线d6，数据线d6可以沿列方向延伸，且在列方向上贯穿第一过渡显示区以延伸至第一主显示区和第二主显示区，从而数据线d6可以向与第三子像素P3位于同一子像素列的像素驱动电路提供数据信号。其中，所述第三子像素可以与所述第一像素驱动电路、第二像素驱动电路均位于不同子像素列。该设置可以使得用于连接第三子像素P3的数据线d6与用于连接第一像素驱动电路D1的数据线、用于连接第二像素驱动电路D2的数据线位于不同子像素列，从而避免了多条数据线位于同一子像素列。
本示例性实施例中，如图3-6所示，所述第一发光单元A1和所述第一像素驱动电路D1均可以为多个，所述第一像素驱动电路D1和与其连接的所述第一发光单元A1可以位于同一行，每个所述第一像素驱动电路D1可以和与其连接的所述第一发光单元A1在行方向上间隔相同子像素列。即每个所述第一像素驱动电路D1和与其连接的所述第一发光单元A1在行方向上可以间隔相同距离。该设置可以使得用于连接第一像素驱动电路D1和第一发光单元A1的第二连接线72具有相同的长度，即每条连接线在相同电压作用下具有相同的压降，从而使得显示面板可以具有更好的显示均一性。
本示例性实施例中，所述第二发光单元A2和所述第二像素驱动电路D2均可以为多个，所述第二像素驱动电路D2和与其连接的所述第二发光单元A2可以位于同一行，每个所述第二像素驱动电路D2和与其连接的所述第二发光单元A2在行方向上可以间隔相同子像素列。即每个所述第二像素驱动电路D2和与其连接的所述第二发光单元A2在行方向上可以间隔相同距离。该设置可以使得用于连接第二像素驱动电路D2和第二发光单元A2的第一连接线71具有相同的长度，即每条连接线在相同电压作用下具有相同的压降，从而使得显示面板可以具有更好的显示均一性。
本示例性实施例中，如图7所示，为本公开显示面板另一种示例性实施例中的结构示意图。所述第一走线区3可以包括弧形走线区301和直线走线区302，所述弧形走线区301可以位于所述第一主显示区41和所述第二主显示区42之间，且沿弧形延伸，所述弧形走线区301所成弧形可以沿所述第一走线区3远离所述透光区1的方向凸起。所述第三信号线g3在所述直线走线区302中可以沿列方向X延伸，所述第三信号线g3在所述弧形走线区301中可以沿所述弧形走线区的弧形延伸方向延伸。相同的，所述第六信号线g6在所述直线走线区302中可以沿列方向延伸，所述第六信号线g6在所述弧形走线区301中可以沿所述弧形走线区的弧形延伸方向延伸。其中，第三信号线g3可以分别通过过孔81与第一信号线d1、第二信号线d2连接。第六信号线g6也可以分别通过过孔82与第四信号线d4、第五信号线d5连接。其中，过孔81、82可以设置于第一走线区3在列方向两侧边沿的附近，例如，过孔81、82可以设置于第一走线区3在列方向两侧的边沿位置。所述弧形走线区301可以位于所述第一走线区3的边界位置。如图7所示，所述透光区1可以为圆形，第一过渡显示区2可以包括面向透光区1一侧的边界203，边界203可以为直线，且边界203所在直线可以与圆形透光区1相切。弧形走线区301可以延伸至边界203所在 直线。显示面板还可以包括有围绕透光区1的第三过渡显示区53。所述第一主显示区41和所述第二主显示区42的像素密度可以相等，所述第一走线区3、第一过渡显示区2、透光区1、第三过渡显示区53的像素密度可以相等。所述第一主显示区41的像素密度可以大于所述透光区1的像素密度。
本示例性实施例中，如图8所示，为本公开显示面板另一种示例性实施例中的结构示意图。所述显示面板还可以包括第二走线区6，所述第二走线区6可以位于所述透光区1、第一过渡显示区2在列方向X上的两侧，所述第一走线区3和所述第二走线区6可以形成环绕所述第一过渡显示区2和所述透光区1的矩形。所述第三信号线g3还可以位于所述第二走线区6，所述第三信号线g3可以沿列方向X延伸至所述第二走线区6，且沿行方向Y延伸至所述第一走线区3；所述第六信号线g6也可以位于所述第二走线区6，所述第六信号线g6可以沿列方向X延伸至所述第二走线区6，且沿行方向Y延伸至所述第一走线区3。其中，第三信号线g3可以分别通过过孔81与第一信号线d1、第二信号线d2连接。第六信号线g6也可以分别通过过孔82与第四信号线d4、第五信号线d5连接。其中，过孔81、82可以设置于第二走线区6远离透光区1一侧边沿的附近，例如，过孔81、82可以设置于第二走线区6远离透光区1一侧的边沿位置。
如图8所示，显示面板还可以包括有围绕透光区1的第四过渡显示区54。本示例性实施例中，所述第一主显示区41和所述第二主显示区42的像素密度可以相等，所述第一走线区3、第一过渡显示区2、透光区1、第二走线区6、第四过渡显示区54的像素密度可以相同。所述第一主显示区41的像素密度可以大于所述透光区1的像素密度。
本示例性实施例中，如图9所示，为本公开显示面板另一种示例性实施例中的结构示意图。所述显示面板还可以包括第二过渡显示区7，所述第二过渡显示区7相邻设置于所述第二走线区6在列方向上的一侧。所述显示面板还可以包括：第五发光单元A5、第五像素驱动电路D5，第五发光单元A5可以位于所述第二走线区6；第五像素驱动电路D5可以位于所述第二过渡显示区7，第五像素驱动电路D5可以用于向所述第五发光单元提供驱动电流。本示例性实施例可以在第二走线区6中仅设置第五发光单元A5，且不设置像素驱动电路，该显示面板可以通过位于第二过渡显示区7中的第五像素驱动电路D5驱动第五发光单元A5。从而该显示面板可以在不影响第二走线区6中第三信号线g3和第六信号线g6正常走线的情况下，保证第二走线区6正常发光。
本示例性实施例中，如图9所示，所述显示面板还包括第六子像素P6，所述第六子像素P6可以位于所述第二过渡显示区7，所述第六子像素P6可以包括第六发光单元、第六像素驱动电路，第六像素驱动电路可以用于向所述第六发光单元提供驱动电流。所述第六子像素P6与所述第五像素驱动电路可以位于不同子像素列。该设置可以使得用于连接第五像素驱动电路D5的数据线与用于连接第六子像素P6的数据线位于不同子像素列，从而避免了两数据线在同一子像素列交叠。第五像素驱动电路D5还可以与第一像素驱动电路D1位于不同子像素列，从而用于连接第五像素驱动电路D5的数据线可以贯穿第二走线区、 第二过渡显示区分别延伸至第一主显示区和第二主显示区。第六子像素P6也可以与第一像素驱动电路位于不同子像素列，从而用于连接第六子像素P6的数据线可以贯穿第二走线区、第二过渡显示区分别延伸至第一主显示区和第二主显示区。
本示例性实施例中，如图9所示，第二过渡显示区7可以相邻设置于第二走线区远离透光区1的一侧，应该理解的是，在其他示例性实施例中，第二过渡显示区7还可以相邻设置于第二走线区面向透光区1的一侧。
本示例性实施例中，所述第五像素驱动电路D5和所述第五发光单元A5可以均为多个，每个所述第五像素驱动电路D5和与其连接的所述第五发光单元A5在列方向上可以间隔相同的子像素行。即每个所述第五像素驱动电路D5和与其连接的所述第五发光单元A5在行方向上可以间隔相同距离。该设置可以使得连接于五像素驱动电路D5和第五发光单元A5之间的连接线73具有相同的长度，每条连接线73在相同电压作用下具有相同的压降，从而使得显示面板可以具有更好的显示均一性。
本示例性实施例中，如图7、8、9所示，透光区1可以为圆形，应该理解的是，在其他示例性实施例中，透光区1还可以为矩形、椭圆形等其他形状。
本示例性实施例中，如图10所示，为本公开显示面板一种示例性实施例中第一像素驱动电路的结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接节点N，第二极连接初始化信号端Vinit，栅极连接复位信号端Re；第二晶体管T2第一极连接驱动晶体管T3的第一极，第二极连接节点N；栅极连接栅极驱动信号端Gate；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第二极，栅极连接栅极驱动信号端Gate；第五晶体管T5的第一极连接第一电源信号端VDD，第二极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第七晶体管T7的第一极连接初始化信号端Vinit，第二极连接第六晶体管T6的第二极。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，晶体管T1-T7可以均为P型晶体管。该显示面板中的其他像素驱动电路可以与第一像素驱动电路具有相同的结构。
如图11所示，为图10像素驱动电路一种驱动方法中各节点的时序图。其中，Gate表示栅极驱动信号端Gate的时序，Re表示复位信号端Re的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：复位信号端Re输出低电平信号，第一晶体管T1、第七晶体管T7导通，初始化信号端Vinit向节点N，第六晶体管T6的第二极输入初始化信号。在补偿阶段t2：栅极驱动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth，其中 Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压。发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例中，该显示面板可以包括依次层叠设置的衬底基板0、有源层、第一导电层、第二导电层、第三导电层。如图12、13、14、15、16所示，图12为本公开显示面板一种示例性实施例的结构版图，图13为图12中有源层的结构版图，图14为图12中第一导电层的结构版图，图15为图12中第二导电层的结构版图，图16为图12中第三导电层的结构版图。
如图12、13所示，有源层可以包括第一有源部61、第二有源部62、第三有源部63、第四有源部64、第五有源部65、第六有源部66、第七有源部67、第八有源部68、第十有源部610、第十一有源部611、第十二有源部612、第十三有源部613。其中，所述第二有源部62可以用于形成所述第二晶体管T2的第一沟道区，所述第三有源部63可以用于形成所述第二晶体管T2的第二沟道区。第六有源部66可以用于形成所述驱动晶体管T3的沟道区。第七有源部67可以用于形成所述第一晶体管T1的第一沟道区，第八有源部68可以用于形成所述第一晶体管T1的第二沟道区。第十有源部610可以用于形成第四晶体管T4的沟道区。第十一有源部611可以用于形成第五晶体管T5的沟道区。第十二有源部612可以用于形成第六晶体管T6的沟道区。第十三有源部613可以用于形成第七晶体管的沟道区。第四有源部64可以连接于所述第二有源部62和所述第三有源部63之间。
如图12、14所示，所述第一导电层可以包括：第一导电部11、第二导电部12、第一栅线13、第二栅线14、第三栅线17、第六导电部16。第一导电部11也可以为沿行方向Y延伸的条形结构，第一导电部11在衬底基板的正投影可以覆盖第六有源部66在衬底基板的正投影，以形成驱动晶体管T3的栅极。所述第二导电部12可以用于形成电容C的部分第一电极。第一栅线13可以用于提供图10中的栅极驱动信号端。第一栅线13在所述衬底基板的正投影可以沿所述行方向Y延伸，且所述第一栅线13在所述衬底基板的正投影可以位于所述第一导电部11在所述衬底基板正投影与所述第二导电部12在所述衬底基板正投影之间，所述第一栅线13的部分导电部131可以用于形成所述第二晶体管T2的第一栅极，所述第一栅线13的部分导电部134可以用于形成第四晶体管T4的栅极。第二栅线14可以用于提供图10中的复位信号端。第二栅线14在所述衬底基板的正投影沿所述行方向Y延伸，且所述第二栅线14在所述衬底基板正投影可以位于所述第二导电部12在所述衬底基板正投影远离所述第一栅线13在所述衬底基板正投影的一侧，所述第二栅线14的部分导电部141可以用于形成所述第一晶体管T1的第一栅极，所述第二栅线14的部分导 电部142可以用于形成所述第一晶体管T1的第二栅极。第三栅线17可以用于提供图10中的使能信号端。第三栅线17在衬底基板的正投影可以位于第一导电部11在衬底基板正投影远离第一栅线13在衬底基板正投影的一侧。第三栅线17可以包括导电部175和导电部176，导电部175可以用于形成第五晶体管的栅极，导电部176可以用于形成第六晶体管的栅极。其中，第七晶体管T7的栅极可以共用下一行像素单元对应第二栅线14中的导电部147。第六导电部16在所述衬底基板的正投影可以沿所述列方向X延伸，且连接于所述第一栅线13，部分第六导电部16可以用于形成第二晶体管T2的第二栅极。
如图12、15所示，第二导电层可以包括第三导电部23，所述第三导电部23在所述衬底基板的正投影可以与所述第二导电部12在衬底基板的正投影至少部分重合，且所述第三导电部23与所述第一导电部11电连接，所述第三导电部23可以用于形成所述电容C的第二电极。
如图12、16所示，第三导电层可以包括第四导电部34、第一连接部31、电源线321、第五导电部35、七导电部37、第二连接部39、第三连接部310、数据线311。第五导电部35可以连接于所述第四导电部34和所述电源线321之间。所述第四导电部34在所述衬底基板的正投影可以与所述第三导电部23衬底基板的正投影至少部分重合，且所述第四导电部34可以通过过孔93与所述第二导电部12电连接，所述第四导电部34可以用于形成所述电容C的部分第一电极。所述第五导电部35在所述衬底基板的正投影与所述第一有源部61在所述衬底基板的正投影至少部分重合。第七导电部37可以连接所述第四导电部34，且所述第七导电部37在所述衬底基板的正投影与所述第四有源部64在所述衬底基板的正投影至少部分重合。第二连接部39可以通过过孔96连接第八有源部68一侧的有源层以连接第一晶体管T1的第二极。第三连接部310可以通过过孔97连接第十二有源部612和第十三有源部613之间的有源层，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。第七晶体管T7的第一极可以连接下一行像素单元中的第二连接部39。数据线311可以通过过孔98与第四晶体管T4的第一极连接。第一连接部31可以通过过孔92与所述第一导电部11电连接，且所述第一连接部31可以通过过孔91与第二子导电部232电连接。第五有源部65可以通过过孔95与所述第一连接部31电连接，以使得第二晶体管T2的第二极电连接驱动晶体管的栅极。
本示例性实施例中，显示面板还可以包括位于所述第三导电层背离衬底基板一侧的第五透明导电层以及位于第五透明导电层背离衬底基板一侧的第四导电层、位于第四导电层背离衬底基板的有机发光层，第四导电层可以用于形成发光单元的阳极，有机发光层可以用于形成发光单元的发光层。应该理解的是，在其他示例性实施例中，第一像素驱动电路还可以为其他结构，相应的，显示面板还可以有其他对应的版图结构。
本示例性实施例中，如图3-9所示，第三信号线g3、第六信号线g6可以位于上述的第一导电层、第二导电层中的任意一层或两层。本示例性实施例中，所述第三信号线可以为多条，所述第六信号线可以为多条，多条所述第三信号线和所述多条所述第六信号线可 以形成多条转接线，多条所述转接线包括多条第一转接线和多条第二转接线。至少部分所述第一导电层用于形成所述第一转接线；至少部分所述第二导电层用于形成所述第二转接线；其中，所述第一转接线在所述衬底基板的正投影与所述第二转接线在所述衬底基板的正投影可以在其延伸方向的垂直方向上依次交替分布。该显示面板将多条转接线设置于不同导电层，从而可以增加转接线的集成度，即可以在有限的列方向尺寸上集成更多的第三信号线g3和第六信号线g6。
本示例性实施例中，如图3-9所示，至少部分所述第三导电层可以用于形成所述第一信号线d1、所述第二信号线d2、第四信号线d4、第五信号线d5。第一信号线d1、所述第二信号线d2、第四信号线d4、第五信号线d5可以均为数据线，即图16中数据线311。本示例性实施例中，如图5、6所示，连接线72、连接线71可以由部分第五透明导电层形成。如图9所示，连接线73可以由部分阳极层形成。本示例性实施例中，如图5所示，第三信号线g3可以由部分阳极层形成。
本示例性实施例中，如图9所示，第三信号线g3或第六信号线g6形成的转接线位于第一导电层且沿列方向延伸，如图14所示，第一栅线13、第二栅线14、第三栅线17位于第一导电层且沿行方向延伸，因此，上述转接线可能会与上述栅线相交，从而导致显示面板无法正常显示。
本示例性实施例中，如图9所示，所述显示面板还包括：第七信号线g7、第八信号线g8、第九信号线d9，第七信号线g7可以沿行方向延伸，且位于所述第一走线区3远离所述透光区1的一侧，所述第七信号线g7可以由部分所述第一导电层或部分所述第二导电层形成；第八信号线g8可以沿行方向延伸，且至少部分位于所述第一过渡显示区，所述第八信号线g8可以由部分所述第一导电层或部分所述第二导电层形成；第九信号线d9可以沿行方向延伸，且位于所述第一走线区3，所述第九信号线d9可以由部分所述第三导电层形成，所述第九信号线d9可以通过过孔83分别与所述第七信号线g7、第八信号线g8连接。其中，相互连接的第七信号线g7、第八信号线g8、第九信号线d9可以形成上述的第一栅线13、第二栅线14、第三栅线17。过孔83可以设置于第一走线区3在列方向两侧边沿的附近，例如，过孔83可以设置于第一走线区3在列方向两侧的边沿位置。本公开的显示面板通过位于第三导电层的第九信号线d9对第七信号线g7、第八信号线g8进行转接，从而避免了显示面板中栅线与第一走线区3中的第三信号线或第六信号线相交。
本示例性实施例还提供一种显示装置，该显示装置包括：上述的显示面板和摄像头，所述摄像头与所述显示面板的透光区正对。该显示装置可以为手机、平板电脑等显示装置。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (23)

  1. 一种显示面板，其中，所述显示面板包括透光区、第一过渡显示区、第一主显示区、第二主显示区；
    所述第一过渡显示区位于所述透光区在行方向上的两侧；
    所述第一主显示区位于所述透光区、第一过渡显示区在列方向上的一侧，所述第二主显示区位于所述透光区、第一过渡显示区在列方向上的另一侧；
    所述显示面板还包括：
    第一发光单元，位于所述透光区；
    第一像素驱动电路，位于所述第一过渡显示区，用于向所述第一发光单元提供驱动电流；
    第一信号线，沿列方向延伸，且所述第一信号线的至少部分位于所述第一主显示区，用于向与所述第一像素驱动电路位于同一子像素列的像素驱动电路提供驱动信号；
    第二信号线，沿列方向延伸，且所述第二信号线至少部分位于所述第二主显示区，用于向与所述第一像素驱动电路位于同一子像素列的像素驱动电路提供驱动信号；
    第三信号线，所述第三信号线与所述第一信号线位于不同导电层，所述第三信号线与第二信号线位于不同导电层，且所述第三信号线分别通过过孔与所述第一信号线、第二信号线连接。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括第一走线区；
    所述第一走线区位于所述第一过渡显示区远离所述透光区的一侧；
    所述第一主显示区还位于所述第一走线区在列方向上的一侧，所述第二主显示区还位于所述第一走线区在列方向上的另一侧；
    所述第三信号线的至少部分位于所述第一走线区。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    第二发光单元，位于所述第一走线区；
    第二像素驱动电路，位于所述第一过渡显示区，用于向所述第二发光单元提供驱动电流；
    第四信号线，沿列方向延伸，且所述第四信号线的至少部分位于所述第一主显示区，用于向与所述第二像素驱动电路位于同一子像素列的像素驱动电路提供驱动信号；
    第五信号线，沿列方向延伸，且所述第五信号线至少部分位于所述第二主显示区，用于向与所述第二像素驱动电路位于同一子像素列的像素驱动电路提供驱动信号；
    第六信号线，位于所述第一走线区，所述第六信号线分别通过过孔与所述第四信号线、第五信号线连接。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板还包括第三子像素，所述第三子像素位于所述第一过渡显示区，所述第三子像素包括：
    第三发光单元；
    第三像素驱动电路，用于向所述第三发光单元提供驱动电流；
    所述第三子像素与所述第一像素驱动电路位于不同子像素列，所述第三子像素与第二像素驱动电路位于不同子像素列。
  5. 根据权利要求1所述的显示面板，其中，所述第一发光单元和所述第一像素驱动电路均为多个，所述第一像素驱动电路和与其连接的所述第一发光单元位于同一行，每个所述第一像素驱动电路和与其连接的所述第一发光单元在行方向上间隔相同子像素列。
  6. 根据权利要求3所述的显示面板，其中，所述第二发光单元和所述第二像素驱动电路均为多个，所述第二像素驱动电路和与其连接的所述第二发光单元位于同一行，每个所述第二像素驱动电路和与其连接的所述第二发光单元在行方向上间隔相同子像素列。
  7. 根据权利要求3所述的显示面板，其中，所述第一走线区包括弧形走线区和直线走线区，所述弧形走线区位于所述第一主显示区和所述第二主显示区之间，且沿弧形延伸，所述弧形走线区所成弧形沿所述第一走线区远离所述透光区的方向凸起；
    所述第三信号线在所述直线走线区中沿列方向延伸，所述第三信号线在所述弧形走线区中沿所述弧形走线区的弧形延伸方向延伸；
    所述第六信号线在所述直线走线区中沿列方向延伸，所述第六信号线在所述弧形走线区中沿所述弧形走线区的弧形延伸方向延伸。
  8. 根据权利要求7所述的显示面板，其中，所述弧形走线区位于所述第一走线区的边界位置。
  9. 根据权利要求3所述的显示面板，其中，所述显示面板还包括第二走线区，所述第二走线区位于所述透光区、第一过渡显示区在列方向上的两侧，所述第一走线区和所述第二走线区形成环绕所述第一过渡显示区和所述透光区的矩形；
    所述第三信号线还位于所述第二走线区，所述第三信号线沿列方向延伸至所述第二走线区，且沿行方向延伸至所述第一走线区；
    所述第六信号线还位于所述第二走线区，所述第六信号线沿列方向延伸至所述第二走线区，且沿行方向延伸至所述第一走线区。
  10. 根据权利要求9所述的显示面板，其中，所述显示面板还包括第二过渡显示区，所述第二过渡显示区相邻设置于所述第二走线区在列方向上的一侧，所述显示面板还包括：
    第五发光单元，位于所述第二走线区；
    第五像素驱动电路，位于所述第二过渡显示区，用于向所述第五发光单元提供驱动电流。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括第六子像素，所述第六子像素位于所述第二过渡显示区，所述第六子像素包括：
    第六发光单元；
    第六像素驱动电路，用于向所述第六发光单元提供驱动电流；
    所述第六像素驱动电路与所述第五像素驱动电路位于不同子像素列。
  12. 根据权利要求11所述的显示面板，其中，所述第五像素驱动电路和所述第五发光单元均为多个，每个所述第五像素驱动电路和与其连接的所述第五发光单元在列方向上间隔相同的子像素行。
  13. 根据权利要求3所述的显示面板，其中，所述第一过渡显示区包括第一子过渡显示区和第二子过渡显示区，所述第二子过渡显示区位于所述第一子过渡显示区和所述第一走线区之间；
    所述第一像素驱动电路位于所述第一子过渡显示区，所述第二像素驱动电路位于所述第二子过渡显示区。
  14. 根据权利要求2所述的显示面板，其中，
    所述第一主显示区和所述第二主显示区的像素密度相等，所述第一走线区、第一过渡显示区、透光区的像素密度相等；
    所述第一主显示区的像素密度大于所述透光区的像素密度。
  15. 根据权利要求10所述的显示面板，其中，
    所述第一主显示区和所述第二主显示区的像素密度相等，所述第一走线区、第一过渡显示区、透光区、第二走线区、第二过渡显示区的像素密度相同；
    所述第一主显示区的像素密度大于所述透光区的像素密度。
  16. 根据权利要求3所述的显示面板，其中，所述第三信号线为多条，所述第六信号线为多条，多条所述第三信号线和所述多条所述第六信号线形成多条转接线，多条所述转接线包括多条第一转接线和多条第二转接线；
    所述显示面板还包括：
    衬底基板；
    第一导电层，设置于所述衬底基板的一侧，至少部分所述第一导电层用于形成所述第一转接线；
    第二导电层，设置于所述第一导电层背离所述衬底基板的一侧，至少部分所述第二导电层用于形成所述第二转接线；
    第三导电层，设置于所述第二导电层背离所述衬底基板的一侧，至少部分所述第三导电层用于形成所述第一信号线、所述第二信号线、第四信号线、第五信号线；
    其中，所述第一转接线在所述衬底基板的正投影与所述第二转接线在所述衬底基板的正投影在其延伸方向的垂直方向上依次交替分布。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板还包括：
    第七信号线，沿行方向延伸，位于所述第一走线区远离所述透光区的一侧，所述第七信号线由部分所述第一导电层或部分所述第二导电层形成；
    第八信号线，沿行方向延伸，且至少部分位于所述第一过渡显示区，所述第八信号线由部分所述第一导电层或部分所述第二导电层形成；
    第九信号线，沿行方向延伸，位于所述第一走线区，所述第九信号线由部分所述第三导电层形成，所述第九信号线通过过孔分别与所述第七信号线、第八信号线连接。
  18. 根据权利要求16所述的显示面板，其中，所述显示面板包括驱动晶体管，以及连接于所述驱动晶体管栅极的电容；
    部分所述第一导电层用于形成所述驱动晶体管的栅极，部分所述第二导电层用于形成所述电容的一电极；
    所述第一信号线、第二信号线、第四信号线、第五信号线用于向所述驱动晶体管的栅极提供数据信号。
  19. 根据权利要求18所述的显示面板，其中，所述显示面板还包括：
    第四导电层，位于所述第三导电层背离所述衬底基板的一侧，至少部分所述第四导电层用于形成所述第一发光单元、第二发光单元的阳极。
  20. 根据权利要求19所述的显示面板，其中，所述显示面板还包括：
    第五透明导电层，位于所述第三导电层和所述第四导电层之间，所述第五透明导电层包括第一连接线，所述第一连接线用于连接所述第一像素驱动电路和所述第一发光单元的阳极，以及连接所述第二像素驱动电路和所述第二发光单元的阳极。
  21. 根据权利要求1所述的显示面板，其中，
    所述第三信号线位于所述第一过渡显示区。
  22. 根据权利要求21所述的显示面板，其中，所述显示面板还包括：
    衬底基板；
    第三导电层，设置于所述衬底基板的一侧，至少部分所述第三导电层用于形成所述第一信号线、所述第二信号线；
    第四导电层，位于所述第三导电层背离所述衬底基板的一侧，至少部分所述第四导电层用于形成所述第一发光单元、第二发光单元的阳极；且至少部分所述第四导电层用于形成所述第三信号线。
  23. 一种显示装置，其中，包括：
    权利要求1-22任一项所述的显示面板；
    摄像头，所述摄像头与所述显示面板的透光区正对。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116453447A (zh) * 2023-05-12 2023-07-18 昆山国显光电有限公司 显示面板及其驱动方法、显示装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220392964A1 (en) * 2021-06-03 2022-12-08 Wuhan Tianma Microelectronics Co., Ltd. Display panel and display device
CN121368935A (zh) * 2024-05-17 2026-01-20 京东方科技集团股份有限公司 多路选择器、阵列基板、显示面板和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140086708A (ko) * 2012-12-28 2014-07-08 엘지디스플레이 주식회사 표시장치와 그의 제조방법
CN109541867A (zh) * 2018-12-28 2019-03-29 厦门天马微电子有限公司 一种显示面板和显示装置
CN110610667A (zh) * 2019-10-28 2019-12-24 武汉天马微电子有限公司 一种显示面板和显示装置
CN110850652A (zh) * 2019-11-06 2020-02-28 鸿富锦精密工业（深圳）有限公司 阵列基板、显示面板及显示装置
CN111599852A (zh) * 2020-06-02 2020-08-28 京东方科技集团股份有限公司 一种显示面板、显示装置及显示面板的制作方法
CN111969019A (zh) * 2020-08-24 2020-11-20 合肥维信诺科技有限公司 显示面板和显示装置
CN112186021A (zh) * 2020-09-30 2021-01-05 武汉天马微电子有限公司 显示面板及显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118042866A (zh) 2018-12-25 2024-05-14 武汉华星光电半导体显示技术有限公司 显示面板
KR102792464B1 (ko) 2019-01-10 2025-04-07 삼성디스플레이 주식회사 표시 장치
CN109962092B (zh) * 2019-03-29 2021-09-24 上海天马微电子有限公司 一种显示面板和显示装置
CN210182387U (zh) 2019-08-09 2020-03-24 武汉华星光电半导体显示技术有限公司 显示面板及电子设备
CN210926018U (zh) 2019-09-20 2020-07-03 北京小米移动软件有限公司 显示面板、显示屏及电子设备
WO2021134005A1 (en) 2019-12-27 2021-07-01 Hg Medical Technologies Llc Iontophoretic wound treatment device
CN111326560B (zh) * 2020-01-23 2023-08-22 京东方科技集团股份有限公司 显示基板和显示装置
CN111402743A (zh) 2020-03-24 2020-07-10 昆山国显光电有限公司 显示面板及显示装置
CN111446282B (zh) 2020-04-28 2022-04-22 京东方科技集团股份有限公司 显示基板及显示装置
CN113744649A (zh) 2020-05-29 2021-12-03 京东方科技集团股份有限公司 一种显示面板及显示装置
CN112117320B (zh) * 2020-09-30 2022-08-09 武汉天马微电子有限公司 一种显示面板和显示装置
CN112271203B (zh) * 2020-10-29 2025-02-14 京东方科技集团股份有限公司 显示面板及显示装置
CN114298380A (zh) 2021-12-07 2022-04-08 嘉兴蓝匠仓储系统软件有限公司 一种基于时间窗的有轨制导车动态路径规划方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140086708A (ko) * 2012-12-28 2014-07-08 엘지디스플레이 주식회사 표시장치와 그의 제조방법
CN109541867A (zh) * 2018-12-28 2019-03-29 厦门天马微电子有限公司 一种显示面板和显示装置
CN110610667A (zh) * 2019-10-28 2019-12-24 武汉天马微电子有限公司 一种显示面板和显示装置
CN110850652A (zh) * 2019-11-06 2020-02-28 鸿富锦精密工业（深圳）有限公司 阵列基板、显示面板及显示装置
CN111599852A (zh) * 2020-06-02 2020-08-28 京东方科技集团股份有限公司 一种显示面板、显示装置及显示面板的制作方法
CN111969019A (zh) * 2020-08-24 2020-11-20 合肥维信诺科技有限公司 显示面板和显示装置
CN112186021A (zh) * 2020-09-30 2021-01-05 武汉天马微电子有限公司 显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116453447A (zh) * 2023-05-12 2023-07-18 昆山国显光电有限公司 显示面板及其驱动方法、显示装置

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