WO2022178785A1 - 整流器及其驱动方法、设备 - Google Patents

整流器及其驱动方法、设备 Download PDF

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Publication number
WO2022178785A1
WO2022178785A1 PCT/CN2021/077974 CN2021077974W WO2022178785A1 WO 2022178785 A1 WO2022178785 A1 WO 2022178785A1 CN 2021077974 W CN2021077974 W CN 2021077974W WO 2022178785 A1 WO2022178785 A1 WO 2022178785A1
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WIPO (PCT)
Prior art keywords
terminal
gate
output
signal
digital signal
Prior art date
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Ceased
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PCT/CN2021/077974
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English (en)
French (fr)
Inventor
郜笠旭
贾立刚
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN202180094107.5A priority Critical patent/CN116868495A/zh
Priority to PCT/CN2021/077974 priority patent/WO2022178785A1/zh
Priority to EP21927223.4A priority patent/EP4283856A4/en
Publication of WO2022178785A1 publication Critical patent/WO2022178785A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H02M7/2195—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration the switches being synchronously commutated at the same frequency of the AC input voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/081—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters wherein the phase of the control voltage is adjustable with reference to the AC source
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter

Definitions

  • the present application relates to the technical field of AC/DC conversion, and in particular, to a rectifier and a driving method and device thereof.
  • WPT Wireless power transfer
  • AC/DC (alternating current/direct current) converters also called rectifiers
  • the function of the rectifier is to convert alternating current into direct current.
  • wireless charging or wireless power transfer can be physically divided into a power transmitting side and a power receiving side.
  • the power transmitting circuit on the power transmitting side transmits an alternating electromagnetic field
  • the power receiving circuit on the power receiving side receives the alternating electromagnetic field and outputs an alternating current signal.
  • the rectifier receives the AC signal, converts it into a DC signal, and transmits it to the load. Therefore, the stability of the signal output by the rectifier is directly related to the effect of the post-stage communication.
  • Embodiments of the present application provide a rectifier and a driving method and device thereof, which are used to improve the stability of an output signal of the rectifier.
  • a first aspect of the embodiments of the present application provides a rectifier, including: a first logic circuit, including a first comparator, a second comparator, and a first AND gate; a forward input terminal of the first comparator and a first voltage The terminals are coupled to each other, the reverse input terminal of the first comparator is coupled to the second voltage terminal; the forward input terminal of the second comparator is coupled to the third voltage terminal, and the reverse input terminal of the second comparator is coupled to the fourth voltage terminal; the first input terminal of the first AND gate is coupled to the output terminal of the first comparator, and the second input terminal of the first AND gate is coupled to the output terminal of the second comparator
  • the first rising edge filter circuit coupled with the output end of the first AND gate and the first control end, is used to receive the digital signal output by the output end of the first AND gate, and filter out the digital signal in each pulse period
  • the rising edge signal of Ans before generates a switch control signal, and transmits the switch control signal to the first control terminal; wherein, A>0.
  • the oscillating high-level signal in the digital signal output by the output terminal of the first AND gate is filtered out, so that the first control terminal Among the received high-level signals of the switch control signal, only the required high-level signal remains, and the waveform of the switch control signal is regular.
  • the first control terminal can be prevented from receiving the turn-on signal, thereby preventing the controllable switch tube coupled to the first control terminal from being turned on.
  • the high-level signal received by the first control terminal is only the required high-level signal, so that the controllable switches coupled to the first control terminal are all turned on in the main power transmission stage, so that the output stability of the rectifier is stable. , the fluctuation is small.
  • the rectifier further includes: a second logic circuit, including a third comparator, a fourth comparator, and a second AND gate; a forward input terminal of the third comparator is coupled to the fourth voltage terminal, and the third comparator The reverse input terminal of the comparator is coupled with the second voltage terminal; the forward input terminal of the fourth comparator is coupled with the third voltage terminal, and the reverse input terminal of the fourth comparator is coupled with the first voltage terminal ; The first input end of the second AND gate is coupled with the output end of the third comparator, and the second input end of the second AND gate is coupled with the output end of the fourth comparator;
  • the second rising edge filter circuit It is coupled with the output terminal of the second AND gate and the second control terminal, and is used for receiving the digital signal output by the output terminal of the second AND gate, and filtering out the rising edge signal of the digital signal at the front Bns of each pulse period, A switch control signal is generated, and the switch control signal is transmitted to the second control terminal; wherein, B>0.
  • the oscillating high-level signal in the digital signal output by the output terminal of the second AND gate is filtered, so that the first control terminal Among the received high-level signals of the switch control signal, only the required high-level signal remains, and the waveform of the switch control signal is regular.
  • the second control terminal can be prevented from receiving the turn-on signal, thereby preventing the controllable switch tube coupled to the second control terminal from being turned on.
  • the high-level signal received by the second control terminal is only the required high-level signal, so that the controllable switches coupled to the second control terminal are all turned on in the main power transmission stage, so that the output stability of the rectifier is stable. , the fluctuation is small.
  • the first rising edge filter circuit includes a first delay circuit and a third AND gate; the first delay circuit is coupled to the output end of the first AND gate and the first input end of the third AND gate; The second input terminal of the three AND gate is also coupled to the output terminal of the first AND gate, and the output terminal of the third AND gate is coupled to the first control terminal.
  • the rectification control circuit After the delayed digital signal output from the output end of the first delay circuit and the digital signal output from the output end of the first AND gate are ANDed, the oscillating high-level signal can be filtered out.
  • the rectification control circuit outputs a regular switch control signal to the first control terminal.
  • the second rising edge filter circuit includes a second delay circuit and a fourth AND gate; the second delay circuit is coupled to the output end of the second AND gate and the first input end of the fourth AND gate; the first The second input terminal of the four AND gate is further coupled to the output terminal of the second AND gate, and the output terminal of the fourth AND gate is coupled to the second control terminal.
  • the second AND gate After performing AND operation between the delayed digital signal output by the output end of the second delay circuit and the digital signal output by the output end of the second AND gate, the second AND gate can be filtered out.
  • the oscillating high-level signal in the digital signal output by the output end of the gate causes the rectifier control circuit to output a regular switch control signal to the second control end.
  • the first rising edge filter circuit includes a first current trend judging circuit, a fifth AND gate and a first flip-flop; the first current trend judging circuit is coupled to the current terminal and the first input terminal of the fifth AND gate It is used to receive and process the signal of the current end.
  • the signal of the current end is on an upward trend, input 1 to the first input end of the fifth AND gate; when the signal of the current end is on a downward trend, send 1 to the fifth AND gate.
  • the first input end of the gate inputs 0; the second input end of the fifth AND gate is coupled with the output end of the first AND gate, and the output end of the fifth AND gate is coupled with the set end of the first flip-flop;
  • the reset terminal of the first flip-flop is coupled to the output terminal of the first AND gate, and the output terminal of the first flip-flop is coupled to the first control terminal.
  • the oscillating high-level signal in the digital signal output by the output end of the first AND gate is filtered out to avoid the rectifier caused by the ringing problem.
  • the output is not stable.
  • the second rising edge filter circuit includes a second current trend judging circuit, a sixth AND gate and a second flip-flop; the second current trend judging circuit is coupled to the current terminal and the first input terminal of the sixth AND gate It is used to receive and process the signal of the current end.
  • the signal of the current end is rising, input 0 to the first input end of the sixth AND gate; when the signal of the current end is showing a downward trend, send 0 to the sixth and gate.
  • the first input end of the gate is input 1; the second input end of the sixth AND gate is coupled with the output end of the first AND gate, and the output end of the sixth AND gate is coupled with the set end of the second flip-flop;
  • the reset terminal of the second flip-flop is coupled to the output terminal of the second AND gate, and the output terminal of the second flip-flop is coupled to the second control terminal.
  • the oscillating high-level signal in the digital signal output by the output end of the second AND gate is filtered out, so as to avoid the rectifier caused by the ringing problem.
  • the output is not stable.
  • the rectifier further includes: a second logic circuit and a second rising edge filter circuit; the second rising edge filter circuit includes a sixth AND gate and a second flip-flop; the first current trend judgment circuit is also connected to the sixth AND gate. It is also used to input 0 to the first input terminal of the sixth AND gate when the signal at the current terminal is on an upward trend; when the signal at the current terminal is on a downward trend, send 0 to the sixth AND gate
  • the first input terminal of the AND gate is input 1; the second input terminal of the sixth AND gate is coupled to the output terminal of the first AND gate, and the output terminal of the sixth AND gate is coupled to the set terminal of the second flip-flop ;
  • the reset terminal of the second flip-flop is coupled to the output terminal of the second AND gate, and the output terminal of the second flip-flop is coupled to the second control terminal.
  • the first current trend judging circuit receives and processes the signal of the current end, and when the signal of the current end shows an upward trend, it inputs 1 to the first input end of the fifth AND gate, and simultaneously inputs 0 to the first input end of the sixth AND gate .
  • the signal at the current terminal I has a downward trend
  • 0 is input to the first input terminal of the fifth AND gate 34
  • 1 is input to the first input terminal of the sixth AND gate 44 .
  • the rectifier further includes a rectifier circuit, and the first control terminal is coupled to the rectifier circuit.
  • the rectifier further includes a second rising edge filter circuit;
  • the rectifier circuit includes a first switch, a second switch, a third switch and a fourth switch;
  • the first switch is used to connect the first voltage terminal and the second voltage terminal, The control terminal of the first switch is coupled to the first control terminal;
  • the second switch is used to connect the third voltage terminal and the fourth voltage terminal, the control terminal of the second switch is coupled to the first control terminal;
  • the third switch used to connect the first voltage terminal and the third voltage terminal, the control terminal of the third switch is coupled to the second control terminal;
  • the fourth switch is used to connect the second voltage terminal and the fourth voltage terminal, the fourth switch The control terminal is coupled to the second control terminal.
  • a device including a power receiving circuit and the rectifier of any one of the first aspect; the power receiving circuit is used to provide the first voltage terminal and the fourth voltage terminal with an alternating current signal and the rectifier. The first voltage terminal and the fourth voltage terminal are coupled.
  • the power receiving circuit includes a cable, and the cable is coupled to the current terminal of the rectifier.
  • the current terminal can directly receive the current on the cable, no other components are required, and the structure is simple.
  • a method for driving a rectifier where the rectifier includes a first logic circuit and a first rising edge filter circuit; the first logic circuit includes a first comparator, a second comparator, and a first AND gate ;
  • a driving method of a rectifier comprising: the forward input terminal of the first comparator receives the signal of the first voltage terminal, the reverse input terminal of the first comparator receives the signal of the second voltage terminal, the first comparator compares the forward input terminal and the The signal received by the reverse input terminal is compared, and the operation result is output from the output terminal of the first comparator; the forward input terminal of the second comparator receives the signal of the third voltage terminal, and the reverse input terminal of the second comparator The terminal receives the signal of the fourth voltage terminal, the second comparator performs a comparison operation on the signals received by the forward input terminal and the reverse input terminal, and outputs the operation result from the output terminal of the second comparator; the first AND gate first The input terminal receives the signal output
  • the first rising edge filter circuit receives the digital signal output from the output terminal of the first AND gate, and filters out the digital signal at each pulse.
  • the rising edge signal of Ans before the cycle generates a switch control signal, and transmits the switch control signal to the first control terminal; wherein, A>0.
  • the rectifier further includes a second logic circuit and a second rising edge filter circuit;
  • the second logic circuit includes a third comparator, a fourth comparator and a second AND gate;
  • the driving method of the rectifier further includes: a third comparison The forward input terminal of the comparator receives the signal of the fourth voltage terminal, the reverse input terminal of the third comparator receives the signal of the second voltage terminal, and the third comparator compares the signals received by the forward input terminal and the reverse input terminal , and output the operation result from the output terminal of the third comparator;
  • the forward input terminal of the fourth comparator receives the signal of the third voltage terminal, the reverse input terminal of the fourth comparator receives the signal of the first voltage terminal, and the fourth comparator
  • the comparator performs a comparison operation on the signals received by the forward input terminal and the reverse input terminal, and outputs the operation result from the output terminal of the fourth comparator;
  • the first input terminal of the second AND gate receives the output terminal output of the third comparator
  • the second input terminal of the second AND gate
  • the second rising edge filter circuit receives the digital signal output from the output terminal of the second AND gate, and filters out the rising edge signal of the digital signal at the front Bns of each pulse period to generate a switch control signal, and transmit the switch control signal to the second control terminal; wherein, B>0.
  • the first rising edge filter circuit includes a first delay circuit and a third AND gate; the first rising edge filter circuit receives the digital signal output from the output end of the first AND gate, and filters out the digital signal in each The rising edge signal of Ans before the pulse period generates a switch control signal, and transmits the switch control signal to the first control terminal, including: the first delay circuit receives the digital signal output from the output terminal of the first AND gate, The delay function of the delay circuit, after delaying the digital signal ans, outputs the delayed digital signal; wherein, the high level of the delayed digital signal and the digital signal in the previous Ans of each pulse cycle is staggered; a ⁇ A; The third AND gate performs logical operation on the delayed digital signal output by the first delay circuit and the digital signal output by the output end of the first AND gate to filter out the rising edge signal of the digital signal before Ans of each pulse period, A switch control signal is generated, and the switch control signal is transmitted to the first control terminal.
  • the first rising edge filter circuit includes a first current trend judgment circuit, a fifth AND gate, and a first flip-flop; the first rising edge filter circuit receives the digital signal output from the output end of the first AND gate, and filters the circuit. Divide the rising edge signal of the digital signal before Ans of each pulse period, generate the switch control signal, and transmit the switch control signal to the first control terminal, including: the first current trend judgment circuit receives and processes the signal of the current terminal, and the current When the signal at the current terminal is rising, input 1 to the first input terminal of the fifth AND gate; when the signal at the current terminal is falling, input 0 to the first input terminal of the fifth AND gate; the fifth AND gate Perform logical operation on the digital signal output by the output end of the first AND gate and the signal output by the first current trend judgment circuit, filter out the rising edge signal of the digital signal before Ans of each pulse period, and output the operation result to the first A set terminal of a flip-flop; the first flip-flop generates a switch control signal according to the signals of the reset terminal and the
  • the second rising edge filter circuit includes a second delay circuit and a fourth AND gate; the second rising edge filter circuit receives the digital signal output from the output end of the second AND gate, and filters out the digital signal in each The rising edge signal of Bns before the pulse period generates a switch control signal, and transmits the switch control signal to the second control terminal, including: the second delay circuit receives the digital signal output from the output terminal of the second AND gate, The delay function of the delay circuit, after delaying the digital signal by bns, outputs the delayed digital signal; wherein, the high level of the delayed digital signal and the digital signal in the first Bns of each pulse cycle is staggered; b ⁇ B; The fourth AND gate performs a logical operation on the delayed digital signal output by the second delay circuit and the digital signal output by the output end of the second AND gate, so as to filter out the rising edge signal of the digital signal before Bns of each pulse period, A switch control signal is generated, and the switch control signal is transmitted to the second control terminal.
  • the second delay circuit receives the
  • the second rising edge filter circuit includes a second current trend judgment circuit, a sixth AND gate, and a second flip-flop; the second rising edge filter circuit receives the digital signal output from the output end of the second AND gate, and filters Divide the rising edge signal of the digital signal at the first Bns of each pulse period, generate a switch control signal, and transmit the switch control signal to the second control terminal, including: the second current trend judgment circuit receives and processes the signal of the current terminal.
  • the sixth AND gate Perform logical operation on the digital signal output from the output end of the second AND gate and the signal output by the second current trend judgment circuit, filter out the rising edge signal of the digital signal before Bns of each pulse period, and output the operation result to the first
  • the set terminal of the two flip-flops; the second flip-flop generates a switch control signal according to the signals of the reset terminal and the set terminal, and transmits the switch control signal to the second control terminal.
  • the rectifier further includes a second logic circuit and a second rising edge filter circuit;
  • the second rising edge filter circuit includes a sixth AND gate and a second flip-flop;
  • the second rising edge filter circuit receives the output of the second AND gate The digital signal output by the terminal, and filter out the rising edge signal of the digital signal before Bns of each pulse period, generate a switch control signal, and transmit the switch control signal to the second control terminal, including: the first current trend judgment circuit receives And process the signal at the current end, when the signal at the current end is on the rise, input 0 to the first input end of the sixth AND gate; when the signal at the current end is on a downward trend, input 0 to the first input end of the sixth AND gate The terminal input is 1; the sixth AND gate performs logical operation on the digital signal output by the output terminal of the second AND gate and the signal output by the first current trend judgment circuit, and filters out the rising edge signal of the digital signal before each pulse cycle. , and output the operation result to the set terminal of the second flip-flop; the second
  • FIG. 1 is a schematic diagram of a wireless power transmission system provided by the related art
  • FIG. 2 is a schematic diagram of a wireless power transmission system according to an embodiment of the present application.
  • 3a is a schematic structural diagram of a rectifier provided by an embodiment of the application.
  • Fig. 3b is a theoretical waveform diagram of the rectifier shown in Fig. 3a;
  • Fig. 3c is the waveform diagram when the rectifier shown in Fig. 3a is ringing
  • FIG. 4a is a schematic structural diagram of another rectifier provided by an embodiment of the present application.
  • Fig. 4b is a waveform diagram of the rectifier shown in Fig. 4a;
  • FIG. 5a is a schematic structural diagram of another rectifier provided by an embodiment of the present application.
  • Fig. 5b is a waveform diagram of the rectifier shown in Fig. 5a;
  • FIG. 6a is a schematic structural diagram of another rectifier provided by an embodiment of the present application.
  • FIG. 6b is a schematic diagram of the specific structure of the rectifier shown in FIG. 6a;
  • Figure 6c is a waveform diagram of the rectifier shown in Figure 6a;
  • FIG. 6d is a schematic diagram of a rectification principle of a rectifier circuit provided by an embodiment of the application.
  • FIG. 6e is a schematic diagram of a rectification principle of another rectifier circuit provided by an embodiment of the present application.
  • 6f is a schematic structural diagram of a device provided by an embodiment of the application.
  • FIG. 7a is a schematic structural diagram of another device provided by an embodiment of the present application.
  • Fig. 7b is a waveform diagram of the rectification control circuit in the device shown in Fig. 7a;
  • FIG. 7c is a schematic structural diagram of another device provided by an embodiment of the present application.
  • FIG. 8a is a schematic structural diagram of another device provided by an embodiment of the present application.
  • FIG. 8b is a waveform diagram of the rectification control circuit in the device shown in FIG. 8a.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary.
  • the term “coupled” can be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • the embodiment of the present application provides a device, which can be an electric vehicle, an electric motorcycle, an electric bicycle, a rechargeable household appliance (such as a soymilk maker, a cleaning robot), an electronic device (such as a smartphone, a tablet computer, a smart watch, a Bluetooth headsets, wearable devices), virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, drones, medical electronic components, etc.
  • a device which can be an electric vehicle, an electric motorcycle, an electric bicycle, a rechargeable household appliance (such as a soymilk maker, a cleaning robot), an electronic device (such as a smartphone, a tablet computer, a smart watch, a Bluetooth headsets, wearable devices), virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, drones, medical electronic components, etc.
  • VR virtual reality
  • AR augmented reality
  • the battery charging methods of electric vehicles usually include contact charging and wireless charging.
  • the contact charging uses the metal contact between the plug and the socket to conduct electricity
  • the wireless charging uses the coupled alternating magnetic field as the medium to realize the transmission of electric energy.
  • contact charging has many advantages and will become the mainstream way of charging electric vehicles in the future.
  • AC/DC alternating current/direct current converters
  • the function of a rectifier is to convert alternating current into direct current.
  • the power transmitting end of the wireless power transmission system generally includes a power transmitting circuit, and the power transmitting circuit transmits the alternating current in the form of an alternating magnetic field.
  • the power receiving end of the wireless power transmission system generally includes a power receiving circuit, and the power receiving circuit receives the alternating magnetic field from the power transmitting circuit and outputs an alternating current signal.
  • the voltage signal received by the first connection point AC1 of the receiving end and the voltage signal received by the second connection point AC2 are AC signals, and the AC signals need to be rectified into DC signals by a rectifier. That is, the power receiving circuit receives the AC signal transmitted by the power transmitting circuit, and supplies the AC signal to the rectifier (the first connection point AC1 and the second connection point AC2 of the rectifier) as an AC source.
  • the wireless power transfer system shown in FIG. 2 can implement wireless power transfer (WPT) based on the Qi (trademark of the WPC organization) protocol dominated by the WPC (wireless power consortium, a standard organization that mainly promotes low-frequency wireless power transfer).
  • WPT wireless power transfer
  • the working characteristic of the Qi protocol is that the coil L0 in the power transmitting circuit and the coil L1 in the power receiving circuit are very close, and the operating frequency can be adjusted within the specified range (110-205KHz) as required.
  • the rectifier includes a rectifier circuit, and the rectifier circuit includes a first switch, a second switch, a third switch, and a fourth switch.
  • the first switch includes a first controllable switch tube M1
  • the second switch includes a second controllable switch tube M2
  • the third switch includes a third controllable switch tube M1
  • the fourth switch includes a fourth controllable switch tube M4 is taken as an example to illustrate.
  • the control terminal of the first controllable switch M1 is coupled to the first control terminal NG1, and the control terminal of the second controllable switch M2 is coupled to the first control terminal NG1.
  • the control terminal of the third controllable switch tube M1 is coupled to the second control terminal NG2 of the rectification control circuit.
  • the control terminal of the fourth controllable switch tube M4 is coupled to the second control terminal NG2.
  • the first control terminal NG1 controls the first controllable switch M1 and the second controllable switch M2, and the second control terminal NG2 controls the third controllable switch M3 and the fourth controllable switch M4.
  • the first control terminal NG1 is at a high level
  • the first controllable switch M1 and the second controllable switch M2 are turned on; when the first control terminal NG1 is at a low level, the first controllable switch M1 and the second controllable switch M2 are turned on.
  • the controllable switch tube M2 is turned off.
  • the third controllable switch M3 and the fourth controllable switch M4 are turned on, and when the second control terminal NG2 is at a low level, the third controllable switch M3 and the fourth controllable switch tube M4 is turned off.
  • a rectification control circuit for transmitting a switch control signal to a first control terminal NG1 and a second control terminal NG2 of the rectification circuit.
  • the rectifier includes a rectification circuit and a rectification control circuit
  • the rectification control circuit includes a first logic circuit 10 and a second logic circuit 20 .
  • the first logic circuit 10 includes a first comparator 11 , a second comparator 12 and a first AND gate 13 .
  • the forward input terminal of the first comparator 11 is coupled to the first voltage terminal V1, and the reverse input terminal of the first comparator 11 is coupled to the second voltage terminal V2.
  • the forward input terminal of the second comparator 12 is coupled to the third voltage terminal V3, and the reverse input terminal of the second comparator 12 is coupled to the fourth voltage terminal V4.
  • the first input terminal of the first AND gate 13 is coupled to the output terminal of the first comparator 11
  • the second input terminal of the first AND gate 13 is coupled to the output terminal of the second comparator 12 .
  • the first comparator 11 When the voltage of the first voltage terminal V1 is higher than the voltage of the second voltage terminal V2, the first comparator 11 outputs the digital signal 1. When the voltage of the first voltage terminal V1 is lower than the voltage of the second voltage terminal V2, the first comparator 11 outputs the digital signal 1. 11 outputs digital signal 0. When the voltage of the third voltage terminal V3 is higher than the voltage of the fourth voltage terminal V4, the second comparator 12 outputs the digital signal 1. When the voltage of the third voltage terminal V3 is lower than the voltage of the fourth voltage terminal V4, the second comparator 12 outputs the digital signal 1. The comparator 12 outputs a digital signal 0.
  • the first AND gate 13 performs an AND operation and outputs a digital For signal 1, the first control terminal NG1 is at a high level. Otherwise, the first control terminal NG1 is at a low level.
  • the second logic circuit 20 includes a third comparator 21 , a fourth comparator 22 and a second AND gate 23 .
  • the forward input terminal of the third comparator 21 is coupled to the fourth voltage terminal V4, and the reverse input terminal of the third comparator 21 is coupled to the second voltage terminal V2.
  • the forward input terminal of the fourth comparator 22 is coupled to the third voltage terminal V3, and the reverse input terminal of the fourth comparator 22 is coupled to the first voltage terminal V1.
  • the first input terminal of the second AND gate 23 is coupled to the output terminal of the third comparator 21 , and the second input terminal of the second AND gate 23 is coupled to the output terminal of the fourth comparator 22 .
  • the third comparator 21 When the voltage of the fourth voltage terminal V4 is higher than the voltage of the second voltage terminal V2, the third comparator 21 outputs the digital signal 1. When the voltage of the fourth voltage terminal V4 is lower than the voltage of the second voltage terminal V2, the third comparator 21 outputs the digital signal 1. The comparator 21 outputs a digital signal 0. When the voltage of the third voltage terminal V3 is higher than the voltage of the first voltage terminal V1, the fourth comparator 22 outputs the digital signal 1. When the voltage of the third voltage terminal V3 is lower than the voltage of the first voltage terminal V1, the fourth comparator 22 outputs the digital signal 1. The comparator 22 outputs a digital signal 0.
  • the second AND gate 23 performs an AND operation to output a digital Signal 1, the second control terminal NG2 is high level. Otherwise, the second control terminal NG2 is at a low level.
  • the first voltage terminal V1 is coupled to the first connection point AC1 to receive the square wave signal output by the power receiving circuit.
  • the fourth voltage terminal V4 is coupled to the second connection point AC2 and receives the square wave signal output by the power receiving circuit. That is, the power receiving circuit provides a differential voltage, and the differential voltage is respectively coupled to the first voltage terminal V1 and the fourth voltage terminal V4.
  • the second voltage terminal V2 is coupled to the output terminal Vrect of the rectifier circuit.
  • the third voltage terminal V3 is coupled to the reference ground terminal VGND.
  • the current flowing through the coil L1 in the power receiving circuit is IL1 in Fig. 3b, which is a current similar to a sine wave.
  • the voltage signal received by the first connection point AC1 of the receiving end and the voltage signal received by the second connection point AC2 are a square wave, and the voltage signal received by the first connection point AC1 of the receiving end and the voltage received by the second connection point AC2
  • the DC voltage generated after the signal is rectified by the rectifier circuit is Vrect in Figure 3b.
  • the rectifier may appear ringing. This phenomenon will cause great interference to the switching logic of the rectifier circuit. In severe cases, it will cause the rectifier output to oscillate and affect the power transmitter and the power transmitter. Communication between power receivers.
  • the current generated by the coil L1 in the power receiving circuit is no longer a standard sine wave, but there is a small current on both sides of a large sinusoidal current due to the parallel resonance capacitor C2 in the power receiving circuit (see Figure 2). shown) to produce a sinusoidal current.
  • the ringing phenomenon causes the rectifier circuit to be re-conducted by the small sinusoidal current caused by parallel resonance soon after it is turned off. Usually, the frequency of these small sinusoidal currents is very high. After the rectifier circuit is turned on, it needs to be turned off immediately. Turning off immediately and accurately will cause the rectification logic error, causing the output Vrect of the rectifier circuit to oscillate.
  • a rectification control circuit is provided. As shown in FIG. 4a, the rectification control circuit further includes a first on-time control circuit in addition to the first logic circuit 10 and the second logic circuit 20. circuit and a second on-time control circuit.
  • the first on-time control circuit is coupled to the first logic circuit 10 for extending the duration of the on-time signal (high-level signal) output by the first logic circuit 10 .
  • the second on-time control circuit is coupled to the second logic circuit 20 for extending the duration of the on-time signal output by the second logic circuit 20 .
  • the rectification control circuit causes the When the first control terminal NG1 outputs an on-signal, after the first on-time control circuit is set, the outputted on-signal at this time is continuously output (a duration can be set). It continues until the large sinusoidal current generated by the power receiving circuit causes the rectifier control circuit to output a turn-on signal to the first control terminal NG1 of the rectifier circuit. Therefore, the problem of oscillation of the output of the rectifier due to oscillation of the output conduction signal of the first control terminal NG1 is avoided.
  • the rectifier control circuit After setting the second on-time control circuit, the rectifier control circuit outputs the on-signal to the first control terminal NG1 of the rectifier circuit with a regular waveform, which can avoid oscillation due to the output of the on-time signal from the second control terminal NG2. , causing the rectifier output to oscillate.
  • an embodiment of the present application further provides a rectification control circuit, which further includes a first rising edge filter circuit 30 in addition to the above-mentioned first logic circuit 10 .
  • the first rising edge filter circuit 30 is coupled to the output terminal NG1-1 of the first AND gate 13 and the first control terminal NG1, and is used for receiving the digital signal output by the output terminal NG1-1 of the first AND gate 13, and The rising edge signal of the digital signal at the first Ans (A nanosecond) of each pulse period is filtered out, a switch control signal is generated, and the switch control signal is transmitted to the first control terminal NG1.
  • the digital signal output by the output terminal NG1-1 of the first AND gate 13 has waveform oscillation (such as the dotted circle).
  • the digital signal output by the output terminal NG1-1 of the first AND gate 13 is filtered, and each pulse The rising edge signal of Ans before the cycle is filtered out, and the digital signal after Ans is output normally. In this way, as shown in FIG.
  • the high-level signal at the dot-dashed circle in the digital signal output by the output terminal NG1-1 of the first AND gate 13 can be filtered out, and the first rising edge filter circuit 30 sends the first rising edge filter circuit 30 to the first
  • the switch control signal output by the control terminal NG1 is a regular waveform.
  • the filter time A can be adjusted according to the resonant frequency, output load current, and output voltage.
  • A 500ns.
  • the oscillating high-level signal (the high-level signal at the dashed circle) in the digital signal output by the output terminal NG1-1 of the first AND gate 13 can be filtered out.
  • the value of A is different, and the waveform of the switch control signal output by the first rising edge filter circuit 30 to the first control terminal NG1 is also slightly different.
  • the rectification control circuit further includes a second rising edge filter circuit 40 in addition to the above-mentioned second logic circuit 20 .
  • the second rising edge filter circuit 40 is coupled to the output terminal NG2-1 and the second control terminal NG2 of the second AND gate 23, and is used for receiving the digital signal output from the output terminal NG2-1 of the second AND gate 23, and The rising edge signal of the digital signal at the first Bns of each pulse period is filtered out, a switch control signal is generated, and the switch control signal is transmitted to the second control terminal NG2.
  • the digital signal output by the output terminal NG2-1 of the second AND gate 23 has waveform oscillation (such as the dotted circle).
  • the digital signal output from the output terminal NG2-1 of the second AND gate 23 is filtered, and each pulse The rising edge signal of Bns before the cycle is filtered out, and the digital signal after Bns is output normally. In this way, as shown in FIG.
  • the high-level signal at the dot-dashed circle in the digital signal output by the output terminal NG2-1 of the second AND gate 23 can be filtered out, and the second rising edge filter circuit 40 sends the second rising edge filter circuit 40 to the second
  • the switch control signal output by the control terminal NG2 is a regular waveform.
  • the filtering time B is related to the resonant frequency.
  • the oscillating high-level signal in the digital signal output by the output terminal NG2-1 of the second AND gate 23 can be filtered out (the high-level signal at the dotted circle Signal).
  • the value of B is different, and the waveform of the switch control signal output by the second rising edge filter circuit 40 to the second control terminal NG2 is also slightly different.
  • the forward input terminal of the first comparator 11 receives the signal from the first voltage terminal V1
  • the reverse input terminal of the first comparator 11 receives the signal from the second voltage terminal V2
  • the first comparator 11 receives the signal from the second voltage terminal V2.
  • a comparison operation is performed on the signals received by the forward input terminal and the reverse input terminal, and the operation result is output from the output terminal of the first comparator 11 .
  • the output terminal of the first comparator 11 When the voltage of the first voltage terminal V1 is higher than the voltage of the second voltage terminal V2 ( V1 > V2 ), the output terminal of the first comparator 11 outputs the digital signal 1 . When the voltage of the first voltage terminal V1 is lower than the voltage of the second voltage terminal V2 ( V1 ⁇ V2 ), the output terminal of the first comparator 11 outputs a digital signal 0 .
  • the forward input terminal of the second comparator 12 receives the signal of the third voltage terminal V3, the reverse input terminal of the second comparator 12 receives the signal of the fourth voltage terminal V4, and the second comparator 12 compares the forward input terminal and the reverse input terminal with the signal of the fourth voltage terminal V4.
  • a comparison operation is performed on the signal received at the input terminal, and the operation result is output from the output terminal of the second comparator 12 .
  • the output terminal of the second comparator 12 When the voltage of the third voltage terminal V3 is higher than the voltage of the fourth voltage terminal V4 ( V3 > V4 ), the output terminal of the second comparator 12 outputs the digital signal 1 . When the voltage of the third voltage terminal V3 is lower than the voltage of the fourth voltage terminal V4 ( V3 ⁇ V4 ), the output terminal of the second comparator 12 outputs a digital signal 0 .
  • the first input end of the first AND gate 13 receives the signal output by the output end of the first comparator 11
  • the second input end of the first AND gate 13 receives the signal output by the output end of the second comparator 12
  • the first AND gate 13 The logic operation is performed on the signals received by the first input terminal and the second input terminal, and the operation result is output from the output terminal NG1-1 of the first AND gate 13.
  • the output terminal NG1-1 of the first AND gate 13 outputs digital signal 1.
  • the output terminal NG1-1 of the first AND gate 13 outputs digital signal 0.
  • the output terminal NG1-1 of the first AND gate 13 outputs digital signal 0.
  • the output terminal NG1-1 of the first AND gate 13 outputs digital signal 0.
  • the current IL1 generated by the coil L1 in the power receiving circuit is no longer a standard sine wave, but there is a small current IL1 on both sides of a large sinusoidal current due to the parallel resonance capacitor C2 in the power receiving circuit (such as Figure 2) produces a sinusoidal current. Therefore, the voltages at the first connection point AC1 and the second connection point AC2 fluctuate correspondingly. That is to say, the voltages of the first voltage terminal V1 and the fourth voltage terminal V4 fluctuate correspondingly.
  • the voltage of the first voltage terminal V1 is lower than the voltage of the second voltage terminal V2, and the output terminal of the first comparator 11 outputs a digital signal 0.
  • the voltage of the third voltage terminal V3 is lower than the voltage of the fourth voltage terminal V4 at the dot-dash box, and the output terminal of the second comparator 12 outputs a digital signal 0.
  • the output terminal NG1-1 of the first AND gate 13 outputs a digital signal 0 (at the position indicated by the arrow in the box with the dotted line in the figure).
  • the voltage of the first voltage terminal V1 is higher than the voltage of the second voltage terminal V2 before and after the dot-dash line box, and the output terminal of the first comparator 11 outputs a digital signal 1 .
  • the voltage of the third voltage terminal V3 is higher than the voltage of the fourth voltage terminal V4 before and after the dot-dash line box, and the output terminal of the second comparator 12 outputs a digital signal 1.
  • the output terminal NG1 - 1 of the first AND gate 13 outputs the digital signal 1 .
  • the digital signal output by the output terminal NG1-1 of the first AND gate 13 is a short period of time before the actual high-level signal (in the box with the dotted line in FIG. 5b)
  • the oscillating high-level signal (as shown in the dot-dash circle in Figure 5b).
  • the first rising edge filter circuit 30 receives the digital signal output by the output end NG1-1 of the first AND gate 13, and filters out the rising edge signal of the digital signal before Ans of each pulse period, generates a switch control signal, and sets the The switch control signal is transmitted to the first control terminal NG1.
  • the first rising edge filter circuit 30 receives the digital signal output from the output terminal NG1-1 of the first AND gate 13, and filters the oscillating high-level signal in the digital signal output from the output terminal NG1-1 of the first AND gate 13. Except for the high-level signal in the switch control signal output to the first control terminal NG1, only the required high-level signal remains.
  • the forward input terminal of the third comparator 21 receives the signal of the fourth voltage terminal V4
  • the reverse input terminal of the third comparator 21 receives the signal of the second voltage terminal V2
  • the third comparator 21 receives the signal of the forward input
  • the output terminal of the fourth comparator 22 When the voltage of the fourth voltage terminal V4 is higher than the voltage of the second voltage terminal V2 ( V4 > V2 ), the output terminal of the fourth comparator 22 outputs the digital signal 1 . When the voltage of the fourth voltage terminal V4 is lower than the voltage of the second voltage terminal V2 ( V4 ⁇ V2 ), the output terminal of the fourth comparator 22 outputs a digital signal 0 .
  • the forward input terminal of the fourth comparator 22 receives the signal of the third voltage terminal V3, and the reverse input terminal of the fourth comparator 22 receives the signal of the first voltage terminal V1.
  • a comparison operation is performed on the signal received at the input terminal, and the operation result is output from the output terminal of the fourth comparator 22 .
  • the output terminal of the fourth comparator 22 When the voltage of the third voltage terminal V3 is higher than the voltage of the first voltage terminal V1 ( V3 > V1 ), the output terminal of the fourth comparator 22 outputs the digital signal 1 . When the voltage of the third voltage terminal V3 is lower than the voltage of the first voltage terminal V1 ( V3 ⁇ V1 ), the output terminal of the fourth comparator 22 outputs a digital signal 0 .
  • the first input terminal of the second AND gate 23 receives the signal output from the output terminal of the third comparator 21
  • the second input terminal of the second AND gate 23 receives the signal output from the output terminal of the fourth comparator 22
  • the second AND gate 23 Logic operation is performed on the signals received by the first input terminal and the second input terminal, and the operation result is output from the output terminal NG2-1 of the second AND gate 23.
  • the output terminal NG2-1 of the second AND gate 23 outputs digital signal 1.
  • the output terminal NG2-1 of the second AND gate 23 outputs digital signal 0.
  • the voltage of the first voltage terminal V1 and the fourth voltage terminal V4 have a phase difference of about 180°. Based on this, ignoring the waveform oscillation, in the first paragraph, V1>V2, V3>V4.
  • the output terminal NG1 - 1 of the first AND gate 13 outputs the digital signal 1 .
  • the output terminal NG2-1 of the second AND gate 23 outputs the digital signal 0.
  • the output terminal NG1-1 of the first AND gate 13 outputs a digital signal 0.
  • the output terminal NG2-1 of the second AND gate 23 outputs the digital signal 1.
  • the digital signal output by the output terminal NG2-1 of the second AND gate 23 is a high-level signal (such as There is an oscillating high-level signal for a short period of time before (in the box with the dashed-dotted line in Fig. 5b) (in the circle with the dashed-dotted line in Fig. 5b).
  • the second rising edge filter circuit 40 receives the digital signal output from the output terminal NG2-1 of the second AND gate 23, and filters out the rising edge signal of the digital signal at the front Bns of each pulse period, generates a switch control signal, and uses The switch control signal is transmitted to the second control terminal NG2.
  • the second rising edge filter circuit 40 receives the digital signal output from the output terminal NG2-1 of the second AND gate 23, and filters the oscillating high-level signal in the digital signal output from the output terminal NG2-1 of the second AND gate 23. In addition, only the high-level signal in the switch control signal output to the second control terminal NG2 is a high-level signal that is actually required.
  • the digital output terminal NG1-1 of the first AND gate 13 outputs the digital signal.
  • the oscillating high-level signal in the signal is filtered out, so that only the high-level signal in the switch control signal received by the first control terminal NG1 remains the high-level signal that is actually required, and the waveform of the switch control signal is regular. In this way, when the ringing phenomenon occurs, the first control terminal NG1 can be prevented from receiving the turn-on signal, thereby preventing the controllable switch tube coupled to the first control terminal NG1 from being turned on.
  • the high-level signal received by the first control terminal NG1 is only a required high-level signal, so that the controllable switches coupled to the first control terminal NG1 are all turned on in the main power transmission stage, so that the output of the rectifier is turned on. Stability, less fluctuation.
  • the rectifier includes a rectification control circuit and a rectification circuit.
  • the rectification control circuit includes a first logic circuit 10 , a first rising edge filter circuit 30 , a second logic circuit 20 and a second rising edge filter circuit 40 .
  • the first logic circuit 10 includes a first comparator 11 , a second comparator 12 and a first AND gate 13 .
  • the forward input terminal of the first comparator 11 is coupled to the first voltage terminal V1, and the reverse input terminal of the first comparator 11 is coupled to the second voltage terminal V2.
  • the output terminal of the first comparator 11 When the voltage of the first voltage terminal V1 is higher than the voltage of the second voltage terminal V2 , the output terminal of the first comparator 11 outputs a digital signal 1 . When the voltage of the first voltage terminal V1 is lower than the voltage of the second voltage terminal V2, the output terminal of the first comparator 11 outputs a digital signal 0.
  • the forward input terminal of the second comparator 12 is coupled to the third voltage terminal V3, and the reverse input terminal of the second comparator 12 is coupled to the fourth voltage terminal V4.
  • the output terminal of the second comparator 12 When the voltage of the third voltage terminal V3 is higher than the voltage of the fourth voltage terminal V4 , the output terminal of the second comparator 12 outputs the digital signal 1 . When the voltage of the third voltage terminal V3 is lower than the voltage of the fourth voltage terminal V4, the output terminal of the second comparator 12 outputs a digital signal 0.
  • the first input terminal of the first AND gate 13 is coupled to the output terminal of the first comparator 11
  • the second input terminal of the first AND gate 13 is coupled to the output terminal of the second comparator 12 .
  • the output terminal NG1-1 of the first AND gate 13 outputs digital signal 1.
  • the output terminal NG1-1 of the first AND gate 13 outputs digital signal 0.
  • the digital signal output by the output terminal NG1-1 of the first AND gate 13 is, before the actual high-level signal is required, An oscillating high level signal for a short period of time.
  • the first rising edge filter circuit 30 includes a first delay circuit 31 and a third AND gate 32 .
  • the first delay circuit 31 is coupled to the output terminal NG1 - 1 of the first AND gate 13 and the first input terminal of the third AND gate 32 .
  • the first delay circuit 31 receives the digital signal output by the output end NG1-1 of the first AND gate 13, and through the delay action of the first delay circuit 31, the digital signal output by the output end NG1-1 of the first AND gate 13 is processed. After the signal is delayed by ans, the delayed digital signal is output to the first input terminal of the third AND gate 32 .
  • a ⁇ A The delayed digital signal is staggered from the high level of the digital signal in the first Ans of each pulse period.
  • the structure of the first delay circuit 31 is not limited.
  • the first delay circuit 31 includes a first inverter 311 , a second inverter 312 and a third capacitor C3 .
  • the first inverter 311 and the second inverter 312 are connected in series between the output end NG1-1 of the first AND gate 13 and the first input end of the third AND gate 32, and one end of the third capacitor C3 is coupled to the first input end of the third AND gate 32. Between the first inverter 311 and the second inverter 312, the other end is coupled to the reference ground.
  • the second input terminal of the third AND gate 32 is also coupled to the output terminal NG1-1 of the first AND gate 13, and the output terminal of the third AND gate 32 is coupled to the first control terminal NG1.
  • the third AND gate 32 performs a logical operation on the delayed digital signal output by the first delay circuit 31 and the digital signal output by the output terminal NG1-1 of the first AND gate 13, so as to filter out the digital signal before each pulse period
  • the rising edge signal of Ans generates a switch control signal, and transmits the switch control signal to the first control terminal NG1.
  • the second input terminal of the third AND gate 32 is coupled to the output terminal NG1-1 of the first AND gate 13, which is equivalent to the difference between the second input terminal of the third AND gate 32 and the third capacitor C3. One end is coupled to each other.
  • the first input terminal of the third AND gate 32 is coupled to the other terminal of the third capacitor C3. It is equivalent to saying that the third AND gate 32 performs an AND operation on the voltages across the third capacitor C3, so as to play a delay role.
  • the oscillating high-level signal in the digital signal output by the output terminal NG1-1 of the first AND gate 13 and the third capacitor C3 (that is, the output terminal NG1-1 of the first delay circuit 31) 2)
  • the oscillating high-level signals in the output delayed digital signal are completely staggered. Only when the digital signals output by both are 1, the switch control signal output by the output end of the third AND gate 32 to the first control end NG1 is 1, otherwise, the output end of the third AND gate 32 is directed to the first control end NG1.
  • the switch control signal output by the terminal NG1 is 0.
  • the second logic circuit 20 includes a third comparator 21 , a fourth comparator 22 and a second AND gate 23 .
  • the forward input terminal of the third comparator 21 is coupled to the fourth voltage terminal V4, and the reverse input terminal of the third comparator 21 is coupled to the second voltage terminal V2.
  • the output terminal of the second comparator 12 When the voltage of the fourth voltage terminal V4 is higher than the voltage of the second voltage terminal V2 , the output terminal of the second comparator 12 outputs the digital signal 1 . When the voltage of the fourth voltage terminal V4 is lower than the voltage of the second voltage terminal V2, the output terminal of the second comparator 12 outputs a digital signal 0.
  • the forward input terminal of the fourth comparator 22 is coupled to the third voltage terminal V3, and the reverse input terminal of the fourth comparator 22 is coupled to the first voltage terminal V1.
  • the output terminal of the fourth comparator 22 When the voltage of the third voltage terminal V3 is higher than the voltage of the first voltage terminal V1 , the output terminal of the fourth comparator 22 outputs the digital signal 1 . When the voltage of the third voltage terminal V3 is lower than the voltage of the first voltage terminal V1, the output terminal of the fourth comparator 22 outputs a digital signal 0.
  • the first input terminal of the second AND gate 23 is coupled to the output terminal of the third comparator 21 , and the second input terminal of the second AND gate 23 is coupled to the output terminal of the fourth comparator 22 .
  • the output terminal NG2-1 of the second AND gate 23 outputs digital signal 1.
  • the output terminal NG2-1 of the second AND gate 23 outputs digital signal 0.
  • the digital signal output by the output terminal NG2-1 of the second AND gate 23 is, before the actual high-level signal is required, An oscillating high level signal for a short period of time.
  • the second rising edge filter circuit 40 includes a second delay circuit 41 and a fourth AND gate 42 .
  • the second delay circuit 41 is coupled to the output terminal NG2 - 1 of the second AND gate 23 and the first input terminal of the fourth AND gate 42 .
  • the second delay circuit 41 receives the digital signal output by the output terminal NG2-1 of the second AND gate 23, and through the delay function of the second delay circuit 41, the digital signal output by the output terminal NG2-1 of the second AND gate 23 is processed. After the signal is delayed by bns, the delayed digital signal is output to the first input terminal of the fourth AND gate 42 .
  • the delayed digital signal is staggered from the high level of the digital signal in the first Bns of each pulse period.
  • the digital signal output by the output terminal NG2-1 of the second AND gate 23 can be completely filtered out Medium oscillating high level signal.
  • the second delay circuit 41 is used for receiving the digital signal output by the output terminal NG2-1 of the second AND gate 23, and delaying the digital signal output by the output terminal NG2-1 of the second AND gate 23 and outputting it to the first The first input terminal of the quad AND gate 42 .
  • the second delay circuit 41 includes a third inverter 411 , a fourth inverter 412 and a fourth capacitor C4 .
  • the third inverter 411 and the fourth inverter 412 are connected in series between the output end NG2-1 of the second AND gate 23 and the first input end of the fourth AND gate 42, and one end of the fourth capacitor C4 is coupled to the first input end of the fourth AND gate 42. Between the three inverters 411 and the fourth inverter 412, the other end is coupled to the reference ground.
  • the digital signal output from the output terminal NG2-1 of the second AND gate 23 is transmitted to the fourth capacitor C4, the fourth capacitor C4 is charged, and then the output terminal NG2-1 of the second AND gate 23 outputs the digital signal.
  • the digital signal is transmitted to the first input terminal of the fourth AND gate 42 .
  • the delayed digital signal output by the fourth capacitor C4 ie, the output terminal NG2-2 of the second delay circuit 41
  • the digital signal output by the output terminal NG2-1 of the second AND gate 23 have a certain dislocation.
  • the oscillating high-level signal in the digital signal output by the output terminal NG2-1 of the second AND gate 23 and the fourth capacitor C4 (that is, the output terminal of the second delay circuit 41) can be
  • the oscillating high-level signals in the delayed digital signal output by NG2-2) are completely staggered.
  • the second input terminal of the fourth AND gate 42 is further coupled to the output terminal NG2-1 of the second AND gate 23, and the output terminal of the fourth AND gate 42 is coupled to the second control terminal NG2.
  • the fourth AND gate 42 performs a logical operation on the delayed digital signal output by the second delay circuit 41 and the digital signal output by the output terminal NG2-1 of the second AND gate 23 to filter out the digital signal before each pulse period.
  • the rising edge signal of Bns generates a switch control signal, and transmits the switch control signal to the second control terminal NG2.
  • the second input terminal of the fourth AND gate 42 is coupled to the output terminal NG2-1 of the second AND gate 23, which is equivalent to the difference between the second input terminal of the fourth AND gate 42 and the fourth capacitor C4. One end is coupled to each other.
  • the first input terminal of the fourth AND gate 42 is coupled to the other terminal of the fourth capacitor C4. It is equivalent to saying that the fourth AND gate 42 performs an AND operation on the voltages across the fourth capacitor C4, so as to play a delay role.
  • the oscillating high-level signal in the digital signal output by the output terminal NG2-1 of the second AND gate 23 and the fourth capacitor C4 (that is, the output terminal NG2-1 of the second delay circuit 41) 2)
  • the oscillating high-level signals in the output delayed digital signal are completely staggered. Only when the digital signals output by both are 1, the switch control signal output by the output terminal of the fourth AND gate 42 to the second control terminal NG2 is 1, otherwise, the output terminal of the fourth AND gate 42 is connected to the second control terminal NG2.
  • the switch control signal output by the terminal NG2 is 0.
  • the rectifier circuit includes a first switch 51 , a second switch 52 , a third switch 53 and a fourth switch 54 .
  • the first switch 51 is used for connecting the first connection point AC1 and the second voltage terminal V2, and the control terminal of the first switch 51 is coupled to the first control terminal NG1.
  • the first switch 51 for example, includes one first controllable switch tube M1, or includes a plurality of first controllable switch tubes M1 connected in parallel.
  • the second switch 52 is used for connecting the third voltage terminal V3 and the second connection point AC2, and the control terminal of the second switch 52 is coupled to the first control terminal NG1.
  • the second switch 52 for example, includes one second controllable switch tube M2, or includes a plurality of second controllable switch tubes M2 connected in parallel.
  • the third switch 53 is used to connect the first connection point AC1 and the third voltage terminal V3, and the control terminal of the third switch 53 is coupled to the second control terminal NG2 of the rectification control circuit.
  • the third switch 53 for example, includes one third controllable switch tube M3, or includes a plurality of third controllable switch tubes M3 connected in parallel.
  • the fourth switch 54 is used for connecting the second connection point AC2 and the second voltage terminal V2, and the fourth switch 54 is coupled to the second control terminal NG2.
  • the fourth switch 54 for example, includes one fourth controllable switch tube M4, or includes a plurality of fourth controllable switch tubes M4 connected in parallel.
  • the first voltage terminal V1 of the rectification control circuit is coupled to the first connection point AC1
  • the fourth voltage terminal V4 of the rectification control circuit is coupled to the second connection point AC2.
  • the second voltage terminal V2 is the output voltage terminal of the rectifier circuit.
  • the switch control signal received by the first control terminal NG1 is 1, and the switch control signal received by the second control terminal NG2 is 0.
  • the third switch 53 and the fourth switch 54 are turned off, and the first switch 51 and the second switch 52 are turned on, forming a loop as shown by the arrow in FIG. 6d.
  • the high-level signal of the first connection point AC1 is transmitted to the second voltage terminal V2 (the output terminal Vrect of the rectifier circuit).
  • the switch control signal received by the first control terminal NG1 is 0, and the switch control signal received by the second control terminal NG2 is 1.
  • the first switch 51 and the second switch 52 are turned off, and the third switch 53 and the fourth switch 54 are turned on, forming a loop as shown by the arrow in FIG. 6e.
  • the high-level signal of the second connection point AC2 is transmitted to the second voltage terminal V2 (the output terminal Vrect of the rectifier circuit).
  • the output terminal Vrect outputs a DC voltage.
  • the rectifier further includes a tank circuit, which is coupled to the second voltage terminal V2 and the third voltage terminal V3, and is used for performing the electrical signal on the second voltage terminal V2.
  • the cache is also used to release the electrical signals stored inside it.
  • the tank circuit is not limited. As shown in FIG. 6f, the tank circuit may include, for example, an output capacitor Cout.
  • the second voltage terminal V2 of the rectifier (which can also be understood as the output terminal of the rectifier) is coupled to the load for transmitting electrical signals to the load.
  • the energy storage circuit releases the electrical signals stored in it to supply power to the load.
  • the rectifier provided in this embodiment of the present application when applied to a device, as shown in FIG. 6f , the first connection point AC1 and the second connection point AC2 of the rectifier are coupled to the power receiving circuit in the device, and the first connection point AC1 and the second connection point AC2 of the rectifier are coupled to the power receiving circuit in the device.
  • the electrical signals of the connection point AC1 and the second connection point AC2 come from the power receiving circuit.
  • the oscillating high-level signal in the delayed digital signal output by the output terminal NG1-2 of the first delay circuit 31 can be caused to
  • the oscillating high-level signal in the digital signal output by the output terminal NG1-1 of the first AND gate 13 is staggered, and the delayed digital signal output by the output terminal NG1-2 of the first delay circuit 31 is combined with the first AND gate.
  • the oscillating high-level signal can be filtered out, and the rectification control circuit outputs a regular switch control signal to the first control terminal NG1.
  • the oscillating high-level signal in the delayed digital signal output by the output terminal NG2-2 of the second delay circuit 41 can be connected with the second AND gate.
  • the oscillating high-level signal in the digital signal output by the output terminal NG2-1 of 23 is staggered, and the delayed digital signal output by the output terminal NG2-2 of the second delay circuit 41 and the output terminal NG2 of the second AND gate 23 are staggered.
  • the oscillating high-level signal in the digital signal output by the output terminal NG2-1 of the second AND gate 23 can be filtered out, so that the rectifier control circuit outputs regularly to the second control terminal NG2 switch control signal.
  • the second embodiment is the same as the first embodiment in that the structure of the rectifier circuit is the same.
  • the difference between the second embodiment and the first embodiment is that the structure of the first rising edge filter circuit 30 in the rectification control circuit is different.
  • the rectifier includes a rectification control circuit and a rectification circuit.
  • the rectification control circuit includes a first logic circuit 10 , a first rising edge filter circuit 30 , a second logic circuit 20 and a second rising edge filter circuit 40 .
  • the structure of the first logic circuit 10 and the structure of the second logic circuit 20 may be the same as those in the first embodiment, and reference may be made to the description of the first logic circuit 10 and the second logic circuit 20 in the first embodiment, which will not be repeated here.
  • the first rising edge filter circuit 30 includes a first current trend judgment circuit 33 , a fifth AND gate 34 and a first flip-flop 35 .
  • the first current trend judgment circuit 33 is coupled to the current terminal I and the first input terminal of the fifth AND gate 34 .
  • the first current trend judging circuit 33 is used to receive and process the signal of the current terminal I.
  • the output terminal NG1-3 of the first current trend judging circuit 33 is sent to the fifth AND gate 34.
  • the output terminal NG1 - 3 of the first current trend judgment circuit 33 inputs the digital signal 0 to the first input terminal of the fifth AND gate 34 .
  • the power receiving circuit of the device will receive the alternating magnetic field sent by the self-power transmitting circuit of the power transmitting end and output alternating current.
  • the current flowing through the coil L1 in the power receiving circuit is IL1 in Fig. 7b, which is a current similar to a sine wave.
  • the current IL1 of the coil L1 is divided into a phase with an upward trend and a stage with a downward trend.
  • the current terminal I in the first current trend judging circuit 33 can be coupled to the coil L1 in the power receiving circuit for receiving the current IL1 output by the coil L1 with the same sine wave.
  • the first current trend judging circuit 33 judges the change trend of the current IL1 output by the coil L1, and when the signal at the current terminal I is on an upward trend, the output terminal NG1-3 of the first current trend judging circuit 33 goes to the fifth and The digital signal 1 is input to the first input terminal of the gate 34 .
  • the output terminal NG1 - 3 of the first current trend judgment circuit 33 inputs the digital signal 0 to the first input terminal of the fifth AND gate 34 .
  • the structure of the first current trend judgment circuit 33 is not limited, for example, it may be a digital circuit or an analog circuit.
  • the first current trend judging circuit 33 determines whether the first-order derivative of the current IL1 output by the coil L1 (that is, the slope) is obtained by judging whether the first-order derivative of the current IL1 output by the coil L1 is greater than 0, so as to determine whether the output of the coil L1 is larger than 0. Trend of current IL1.
  • the first-order derivative of the current IL1 output by the coil L1 is greater than 0, it is judged that the current IL1 output by the coil L1 has an upward trend, and the output terminal NG1-3 of the first current trend judgment circuit 33 is connected to the first current of the fifth AND gate 34. Input terminal input digital signal 1.
  • the output terminal NG1-3 of the first current trend determination circuit 33 is connected to the first current of the fifth AND gate 34.
  • the digital signal 0 is input to the input terminal.
  • the first current trend judging circuit 33 determines the trend of the current IL1 output by the coil L1 by sampling the current IL1 output by the coil L1 and comparing the magnitude of the current value between the latter current value and the former current value. When the latter current value is greater than the former current value, it is determined that the current IL1 output by the coil L1 is on an upward trend, and the output terminal NG1-3 of the first current trend determination circuit 33 is input to the first input terminal of the fifth AND gate 34 digital signal 1. When the latter current value is smaller than the former current value, it is determined that the current IL1 output by the coil L1 has a downward trend, and the output terminal NG1-3 of the first current trend determination circuit 33 is input to the first input terminal of the fifth AND gate 34 digital signal 0.
  • the first current trend judging circuit 33 can also judge the trend of the current at the current terminal I in other ways, and the above is only an illustration, and is not limited.
  • the second input terminal of the fifth AND gate 34 is coupled to the output terminal NG1-1 of the first AND gate 13, and the output terminal NG1-4 of the fifth AND gate 34 is coupled to the set terminal S of the first flip-flop 35 catch.
  • the fifth AND gate 34 performs a logical operation on the digital signal output by the output terminal NG1-1 of the first AND gate 13 and the signal output by the first current trend judgment circuit 33, and outputs the operation result to the setting of the first flip-flop 35 terminal S.
  • the oscillating high level signal in the digital signal output by the output terminal NG1-1 of the first AND gate 13 always appears in the stage when the current IL1 output by the coil L1 shows a downward trend.
  • the output terminal NG1-3 of the first current trend judging circuit 33 inputs the digital signal 0 to the first input terminal of the fifth AND gate 34.
  • the digital signal 1 is input to the second input terminal of the fifth AND gate 34, and the first current trend
  • the output terminal NG1-3 of the judging circuit 33 inputs the digital signal to the first input terminal of the fifth AND gate 34 as 0.
  • the output terminal NG1 - 4 of the fifth AND gate 34 outputs a digital signal 0 to the set terminal S of the first flip-flop 35 . Therefore, the oscillating high-level signal in the digital signal output by the output end NG1-1 of the first AND gate 13 can be filtered out, so as to filter the rising edge signal of the digital signal before Ans of each pulse period.
  • the reset terminal R of the first flip-flop 35 is coupled to the output terminal NG1-1 of the first AND gate 13, and the output terminal Q of the first flip-flop 35 is coupled to the first control terminal NG1.
  • the first flip-flop 35 generates a switch control signal according to the signals of the reset terminal R and the set terminal S, and transmits the switch control signal from the output terminal Q to the first control terminal NG1.
  • the first flip-flop 35 is a first RS flip-flop (latch).
  • the first RS flip-flop when the digital signal received by the set terminal S of the first RS flip-flop is 1, and the digital signal received by the reset terminal R of the first RS flip-flop is also 1, the first RS flip-flop
  • the output terminal Q of the output terminal NG1 outputs a digital signal 1 to the first control terminal NG1.
  • the output terminal Q of the first RS flip-flop sends to the first RS flip-flop.
  • the control terminal NG1 outputs a digital signal 0.
  • the digital signal received by the reset terminal R of the first RS flip-flop when the digital signal received by the reset terminal R of the first RS flip-flop is an oscillating high-level signal, the digital signal received by the set terminal S of the first RS flip-flop is 0, and the first RS flip-flop receives a digital signal of 0.
  • the output Q of the flip-flop follows the previous output state. In the previous output state, the digital signal received by the set terminal S of the first RS flip-flop is 0, the digital signal received by the reset terminal R of the first RS flip-flop is also 0, and the output of the first RS flip-flop is 0.
  • the terminal Q outputs a digital signal 0 to the first control terminal NG1. Therefore, when the digital signal received by the reset terminal R of the first RS flip-flop is an oscillating high-level signal, the output terminal Q of the first RS flip-flop outputs a digital signal 0 to the first control terminal NG1.
  • the digital signal received by the reset terminal R of the first RS flip-flop is a high-level signal
  • the digital signal received by the set terminal S of the first RS flip-flop is 1 first.
  • the output terminal Q of the first RS flip-flop outputs a digital signal 1 to the first control terminal NG1.
  • the digital signal received by the set terminal S of the first RS flip-flop becomes 0.
  • the output terminal Q of the first RS flip-flop follows the previous output state, and the output terminal Q of the first RS flip-flop goes to the first RS flip-flop.
  • the control terminal NG1 still outputs digital signal 1.
  • the digital signal received by the reset terminal R of the first RS flip-flop is 0, that is, the digital signal output by the output terminal NG1-1 of the first AND gate 13 is 0, the output terminal NG1-4 of the fifth AND gate 34
  • the output digital signal must be 0, that is, the digital signal received by the set terminal S of the first RS flip-flop must be 0. Therefore, based on the rectification control circuit provided by the embodiment of the present application, it does not appear that the digital signal received at the set terminal S of the first RS flip-flop is 1, and the digital signal received by the reset terminal R of the first RS flip-flop is also 0 status.
  • the first RS flip-flop generates the switch control signal according to the signals of the reset terminal R and the set terminal S, filters out the oscillating high-level signal, and only retains the high-level signal that is actually required. .
  • the first current trend judging circuit 33 judges the current trend of the current terminal I, and the first current trend judging circuit 33 outputs the digital signal 1 only when the current of the current terminal I shows an upward trend.
  • the output terminal NG1 of the first AND gate 13 can be filtered out.
  • the set terminal S of the first RS flip-flop receives the digital signal output by the output terminal NG1-4 of the fifth AND gate 34, and the reset terminal R of the first RS flip-flop receives the digital signal output by the output terminal NG1-1 of the first AND gate 13.
  • the output terminal Q follows the previous output state. Therefore, when the current at the current terminal I is in the rising part of the sine wave, the switch control signal output by the output terminal Q of the first RS flip-flop is always 1.
  • the first flip-flop 35 is a first D flip-flop.
  • the digital signal received at the reset terminal R of the first D flip-flop is 1, and the clock terminal CK of the first D flip-flop is used as the rising edge of the signal received by the set terminal S.
  • the output terminal Q of the D flip-flop outputs the signal received by the input terminal D (the fifth voltage terminal V5 coupled to the input terminal D is a fixed high-level signal terminal, such as an input digital signal 1).
  • the output terminal Q of the first D flip-flop always outputs digital signal 0.
  • the output terminal Q of the first D flip-flop follows the previous output state .
  • the first trigger 35 may also be other triggers, which are not limited in this embodiment of the present application, and the above two triggers are only an illustration.
  • the second rising edge filter circuit 40 includes a second current trend judgment circuit 43 , a sixth AND gate 44 and a second flip-flop 45 .
  • the second current trend judgment circuit 43 is coupled to the current terminal I and the first input terminal of the sixth AND gate 44 .
  • the second current trend judging circuit 43 is used to receive and process the signal of the current terminal I.
  • the output terminal NG2-3 of the second current trend judging circuit 43 sends the signal to the sixth AND gate 44.
  • 0 is input to the first input terminal of
  • 1 is input to the first input terminal of the sixth AND gate 44 from the output terminal NG2 - 3 of the second current trend judgment circuit 43 when the signal of the current terminal I shows a downward trend.
  • the second current trend judging circuit 43 and the first current trend judging circuit 33 can be connected to the same current terminal I, that is, both can be connected to the coil L1 flowing through the power receiving circuit.
  • the structure and principle of the second current trend judging circuit 43 may be the same as those of the above-mentioned first current trend judging circuit 33 . Reference can be made to the above description of the first current trend judging circuit 33 , which will not be repeated here.
  • the second input terminal of the sixth AND gate 44 is coupled to the output terminal NG1-1 of the first AND gate 13, and the output terminal NG2-4 of the sixth AND gate 44 is coupled to the set terminal of the second flip-flop 45 .
  • the sixth AND gate 44 performs a logical operation on the digital signal output by the output terminal NG2-1 of the second AND gate 23 and the signal output by the second current trend judgment circuit 43, and outputs the operation result to the setting of the second flip-flop 45 end.
  • the oscillating high level signal in the digital signal output by the output terminal NG2-1 of the second AND gate 23 always appears in the stage when the current IL1 output by the coil L1 is on an upward trend. While the second current trend judging circuit 43 inputs the digital signal 0 to the first input terminal of the sixth AND gate 44 from the output terminal NG2 - 3 of the second current trend judging circuit 43 when the signal at the current terminal I is on an upward trend.
  • the digital signal 1 is input to the second input terminal of the sixth AND gate 44, and the second current trend
  • the output terminal NG2-3 of the judgment circuit 43 inputs a digital signal of 0 to the first input terminal of the sixth AND gate 44.
  • the output terminal NG2 - 4 of the sixth AND gate 44 outputs a digital signal 0 to the set terminal of the second flip-flop 45 . Therefore, the oscillating high-level signal in the digital signal output by the output end NG2-1 of the second AND gate 23 can be filtered out, so as to filter the rising edge signal of the digital signal before Bns of each pulse period.
  • the reset terminal of the second flip-flop 45 is coupled to the output terminal NG2-1 of the second AND gate 23, and the output terminal of the second flip-flop 45 is coupled to the second control terminal NG2.
  • the second flip-flop 45 generates a switch control signal according to the signals of the reset terminal and the set terminal, and transmits the switch control signal from the output terminal to the second control terminal NG2.
  • the second flip-flop 45 is a second RS flip-flop.
  • the second The output terminal of the RS flip-flop outputs a digital signal 1 to the second control terminal NG2.
  • the output terminal of the second RS flip-flop sends to the second control Terminal NG2 outputs digital signal 0.
  • the output terminal NG2-4 of the sixth AND gate 44 The output digital signal must be 0, that is, the digital signal received by the set terminal S of the second RS flip-flop must be 0. Therefore, based on the rectification control circuit provided by the embodiment of the present application, it does not appear that the digital signal received at the set terminal S of the second RS flip-flop is 1, and the digital signal received by the reset terminal R of the second RS flip-flop is also 0 status.
  • the switch control signal generated by the second RS flip-flop according to the signals of the reset terminal R and the set terminal S filters out the oscillating high-level signal, and only retains the actual high-level signal. .
  • the second flip-flop 45 is a second D flip-flop.
  • the digital signal received at the reset terminal R of the second D flip-flop is 1
  • the clock terminal CK of the second D flip-flop is used as the rising edge of the signal received by the set terminal S
  • the second The output terminal Q of the D flip-flop outputs the signal of the input terminal D (the fifth voltage terminal V5 coupled to the input terminal D is a fixed high-level signal terminal, for example, an input digital signal 1).
  • the output terminal Q of the second D flip-flop always outputs digital signal 0.
  • the digital signal received at the clock terminal CK of the second D flip-flop is 0, the digital signal received at the reset terminal R of the second D flip-flop is 1, and the output terminal Q of the second D flip-flop follows the previous output state.
  • the second trigger 45 may also be other triggers, which is not limited in the embodiment of the present application, and the above two triggers are only an illustration.
  • the difference between the third embodiment and the second embodiment is that the structure of the second rising edge filter circuit 40 is different.
  • the second rising edge filter circuit 40 includes a sixth AND gate 44 and a second flip-flop 45 .
  • the first current trend judging circuit 33 is also coupled to the first input terminal of the sixth AND gate 44 .
  • the first current trend judging circuit 33 is also used to input 0 from the output terminal NG1-3 of the first current trend judging circuit 33 to the first input terminal of the sixth AND gate 44 when the signal of the current terminal I is on an upward trend; In the case that the signal at the current terminal I has a downward trend, the output terminal NG1 - 3 of the first current trend judgment circuit 33 inputs 1 to the first input terminal of the sixth AND gate 44 .
  • the first current trend judgment circuit 33 receives and processes the signal of the current terminal I.
  • the output terminal NG1 of the first current trend judgment circuit 33 -3 inputs 1 to the first input terminal of the fifth AND gate 34 and simultaneously inputs 0 to the first input terminal of the sixth AND gate 44 .
  • the output terminal NG1 - 3 of the first current trend judgment circuit 33 inputs 0 to the first input terminal of the fifth AND gate 34 , and simultaneously inputs 0 to the first input terminal of the sixth AND gate 44 . Input 1 at the input.
  • the second input terminal of the sixth AND gate 44 is coupled to the output terminal NG1-1 of the first AND gate 13, and the output terminal NG2-4 of the sixth AND gate 44 is coupled to the set terminal S of the second flip-flop 45 catch.
  • the sixth AND gate 44 performs logical operations on the digital signal output by the output terminal NG2-1 of the second AND gate 23 and the signal output by the first current trend judgment circuit 33, and filters out the rise of the digital signal before Bns of each pulse period. edge signal, and output the operation result to the set terminal S of the second flip-flop 45 .
  • the reset terminal R of the second flip-flop 45 is coupled to the output terminal NG2-1 of the second AND gate 23, and the output terminal of the second flip-flop 45 is coupled to the second control terminal NG2.
  • the second flip-flop 45 generates a switch control signal according to the signals of the reset terminal R and the set terminal S, and transmits the switch control signal to the second control terminal NG2.
  • the first current trend judging circuit 33 receives and processes the signal of the current terminal I, and when the signal of the current terminal I shows an upward trend, it inputs 1 to the first input terminal of the fifth AND gate 34, and simultaneously sends 1 to the sixth AND gate 44.
  • the first input terminal of 0 is input.
  • 0 is input to the first input terminal of the fifth AND gate 34
  • 1 is input to the first input terminal of the sixth AND gate 44 .

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Abstract

本申请实施例提供一种整流器及其驱动方法、设备，涉及交流直流转换技术领域，用于提高整流器输出信号的稳定性。整流器包括：第一逻辑电路。第一逻辑电路中的第一比较器的正向输入端与第一电压端相耦接，反向输入端与第二电压端相耦接；第二比较器的正向输入端与第三电压端相耦接，反向输入端与第四电压端相耦接；第一与门的第一输入端与第一比较器的输出端相耦接，第二输入端与第二比较器的输出端相耦接；第一上升沿滤波电路，与第一与门的输出端和第一控制端相耦接，用于接收第一与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将开关控制信号传输至第一控制端。

Description

整流器及其驱动方法、设备 技术领域
本申请涉及交流直流转换技术领域，尤其涉及一种整流器及其驱动方法、设备。
背景技术
近几年，智能手机、平板电脑、智能手表、蓝牙耳机、穿戴设备等物联网(the internet of things，IOT)环境中使用的电子设备的数量逐渐增加。无线电力传输(wireless power transfer，WPT)是一项不经由导线而直接在空间进行电力传输的技术，和传统的电力传输相比，设备间无需导线连接，在一些应用场合给用户带来了极大的使用便利。因此，比起以往，对无线电力传输的需求呈增长趋势。
由于通常电的产生和传输是交流形式的，而许多终端用电设备使用的是直流电源。因此，AC/DC(交流/直流)转换器(也称为整流器)在电力电子系统中得到了广泛应用。其中，整流器(rectifier)的作用是把交流电转换为直流电。如图1所示，无线充电或无线电力传输在物理上可分为功率发送侧和功率接收侧。功率发送侧的功率发送电路发送交变电磁场，功率接收侧的功率接收电路接收交变电磁场，并输出交流电信号。整流器接收交流电信号并转换为直流电信号，传输至负载端。因此，整流器输出的信号的稳定性直接与后级通信的效果息息相关。
因此，如何提高整流器输出信号的稳定性，成为本领域技术人员急需解决的技术问题。
发明内容
本申请实施例提供一种整流器及其驱动方法、设备，用于提高整流器输出信号的稳定性。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种整流器，包括：第一逻辑电路，包括第一比较器、第二比较器以及第一与门；第一比较器的正向输入端与第一电压端相耦接，第一比较器的反向输入端与第二电压端相耦接；第二比较器的正向输入端与第三电压端相耦接，第二比较器的反向输入端与第四电压端相耦接；第一与门的第一输入端与第一比较器的输出端相耦接，第一与门的第二输入端与第二比较器的输出端相耦接；第一上升沿滤波电路，与第一与门的输出端和第一控制端相耦接，用于接收第一与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将开关控制信号传输至第一控制端；其中，A>0。
通过在第一与门的与第一控制端之间增加第一上升沿滤波电路，对第一与门的输出端输出的数字信号中的震荡高电平信号进行滤除，使得第一控制端接收到的开关控制信号中的高电平信号仅剩实需高电平信号，开关控制信号的波形有规律。这样一来，在振铃现象发生时，可避免第一控制端接收到导通信号，从而避免与第一控制端相耦 接的可控开关管导通。第一控制端接收到的高电平信号仅剩实需高电平信号，使得与第一控制端相耦接的可控开关管都是在主功率传输阶段导通，使得整流器的输出稳定性，波动较小。
可选的，整流器还包括：第二逻辑电路，包括第三比较器、第四比较器以及第二与门；第三比较器的正向输入端与第四电压端相耦接，第三比较器的反向输入端与第二电压端相耦接；第四比较器的正向输入端与第三电压端相耦接，第四比较器的反向输入端与第一电压端相耦接；第二与门的第一输入端与第三比较器的输出端相耦接，第二与门的第二输入端与第四比较器的输出端相耦接；第二上升沿滤波电路，与第二与门的输出端和第二控制端相耦接，用于接收第二与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将开关控制信号传输至第二控制端；其中，B>0。
通过在第二与门的与第二控制端之间增加第二上升沿滤波电路，对第二与门的输出端输出的数字信号中的震荡高电平信号进行滤除，使得第额控制端接收到的开关控制信号中的高电平信号仅剩实需高电平信号，开关控制信号的波形有规律。这样一来，在振铃现象发生时，可避免第二控制端接收到导通信号，从而避免与第二控制端相耦接的可控开关管导通。第二控制端接收到的高电平信号仅剩实需高电平信号，使得与第二控制端相耦接的可控开关管都是在主功率传输阶段导通，使得整流器的输出稳定性，波动较小。
可选的，第一上升沿滤波电路包括第一延时电路和第三与门；第一延时电路与第一与门的输出端和第三与门的第一输入端相耦接；第三与门的第二输入端还与第一与门的输出端相耦接，第三与门的输出端与第一控制端相耦接。通过在第一上升沿滤波电路中设置第一延时电路，可使第一延时电路的输出端输出的延时数字信号中的震荡高电平信号，与第一与门的输出端输出的数字信号中的震荡高电平信号错开，在将第一延时电路的输出端输出的延时数字信号与第一与门的输出端输出的数字信号进行与运算后，可以滤除震荡高电平信号，整流控制电路向第一控制端输出有规律的开关控制信号。
可选的，第二上升沿滤波电路包括第二延时电路和第四与门；第二延时电路与第二与门的输出端和第四与门的第一输入端相耦接；第四与门的第二输入端还与第二与门的输出端相耦接，第四与门的输出端与第二控制端相耦接。通过在第二上升沿滤波电路中设置第二延时电路，可使第二延时电路的输出端输出的延时数字信号中的震荡高电平信号，与第二与门的输出端输出的数字信号中的震荡高电平信号错开，在将第二延时电路的输出端输出的延时数字信号与第二与门的输出端输出的数字信号进行与运算后，可以滤除第二与门的输出端输出的数字信号中的震荡高电平信号，使得整流控制电路向第二控制端输出有规律的开关控制信号。
可选的，第一上升沿滤波电路包括第一电流趋势判断电路、第五与门以及第一触发器；第一电流趋势判断电路，与电流端和第五与门的第一输入端相耦接；用于接收并处理电流端的信号，在电流端的信号呈上升趋势的情况下，向第五与门的第一输入端输入1；在电流端的信号呈下降趋势的情况下，向第五与门的第一输入端输入0；第五与门的第二输入端与第一与门的输出端相耦接，第五与门的输出端与第一触发器的 置位端相耦接；第一触发器的复位端与第一与门的输出端相耦接，第一触发器的输出端与第一控制端相耦接。第一与门的输出端输出的数字信号中的震荡高电平信号出现时，电流端的电流呈下降趋势。第一与门的输出端输出的数字信号中的实需高电平信号出现时，电流端的电流呈上升趋势。在第一电流趋势判断电路、第五与门以及第一触发器的共同作用下，滤除第一与门的输出端输出的数字信号中的震荡高电平信号，避免因振铃问题导致整流器输出不稳定的问题。
可选的，第二上升沿滤波电路包括第二电流趋势判断电路、第六与门以及第二触发器；第二电流趋势判断电路，与电流端和第六与门的第一输入端相耦接；用于接收并处理电流端的信号，在电流端的信号呈上升趋势的情况下，向第六与门的第一输入端输入0；在电流端的信号呈下降趋势的情况下，向第六与门的第一输入端输入1；第六与门的第二输入端与第一与门的输出端相耦接，第六与门的输出端与第二触发器的置位端相耦接；第二触发器的复位端与第二与门的输出端相耦接，第二触发器的输出端与第二控制端相耦接。第二与门的输出端输出的数字信号中的震荡高电平信号出现时，电流端的电流呈上升趋势。第二与门的输出端输出的数字信号中的实需高电平信号出现时，电流端的电流呈下降趋势。在第二电流趋势判断电路、第六与门以及第二触发器的共同作用下，滤除第二与门的输出端输出的数字信号中的震荡高电平信号，避免因振铃问题导致整流器输出不稳定的问题。
可选的，整流器还包括：第二逻辑电路和第二上升沿滤波电路；第二上升沿滤波电路包括第六与门以及第二触发器；第一电流趋势判断电路，还与第六与门的第一输入端相耦接；还用于在电流端的信号呈上升趋势的情况下，向第六与门的第一输入端输入0；在电流端的信号呈下降趋势的情况下，向第六与门的第一输入端输入1；第六与门的第二输入端与第一与门的输出端相耦接，第六与门的输出端与第二触发器的置位端相耦接；第二触发器的复位端与第二与门的输出端相耦接，第二触发器的输出端与第二控制端相耦接。第一电流趋势判断电路接收并处理电流端的信号，在电流端的信号呈上升趋势的情况下，向第五与门的第一输入端输入1，同时向第六与门的第一输入端输入0。在电流端I的信号呈下降趋势的情况下，向第五与门34的第一输入端输入0，同时向第六与门44的第一输入端输入1。无需再单独设置上述第二电路趋势判断电路，可简化整流器的结构。
可选的，整流器还包括整流电路，第一控制端与整流电路相耦接。
可选的，整流器还包括第二上升沿滤波电路；整流电路包括第一开关、第二开关、第三开关以及第四开关；第一开关，用于连通第一电压端和第二电压端，第一开关的控制端与第一控制端相耦接；第二开关，用于连通第三电压端和第四电压端，第二开关的控制端与第一控制端相耦接；第三开关，用于连通第一电压端和第三电压端，第三开关的控制端与第二控制端相耦接；第四开关，用于连通第二电压端和第四电压端，第四开关的控制端与第二控制端相耦接。
本申请实施例的第二方面，提供一种设备，包括功率接收电路和第一方面任一项的整流器；功率接收电路，用于向第一电压端和第四电压端提供交流信号与整流器的第一电压端和第四电压端相耦接。
可选的，功率接收电路包括线缆，线缆与整流器的电流端相耦接。这样一来，电 流端可以直接接收线缆上的电流，无需设置其他部件，结构简单。
本申请实施例的第三方面，提供一种整流器的驱动方法，整流器包括第一逻辑电路和第一上升沿滤波电路；第一逻辑电路包括第一比较器、第二比较器以及第一与门；整流器的驱动方法，包括：第一比较器的正向输入端接收第一电压端的信号，第一比较器的反向输入端接收第二电压端的信号，第一比较器对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从第一比较器的输出端输出；第二比较器的正向输入端接收第三电压端的信号，第二比较器的反向输入端接收第四电压端的信号，第二比较器对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从第二比较器的输出端输出；第一与门第一输入端接收第一比较器的输出端输出的信号，第一与门的第二输入端接收第二比较器的输出端输出的信号，第一与门对第一输入端和第二输入端接收到的信号进行逻辑运算，并将运算结果从第一与门的输出端输出；第一上升沿滤波电路，接收第一与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，将开关控制信号传输至第一控制端；其中，A>0。整流器的驱动方法的有益效果与上述整流器的有益效果相同，此处不再赘述。
可选的，整流器还包括第二逻辑电路和第二上升沿滤波电路；第二逻辑电路包括第三比较器、第四比较器以及第二与门；整流器的驱动方法，还包括：第三比较器的正向输入端接收第四电压端的信号，第三比较器的反向输入端接收第二电压端的信号，第三比较器对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从第三比较器的输出端输出；第四比较器的正向输入端接收第三电压端的信号，第四比较器的反向输入端接收第一电压端的信号，第四比较器对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从第四比较器的输出端输出；第二与门第一输入端接收第三比较器的输出端输出的信号，第二与门的第二输入端接收第四比较器的输出端输出的信号，第二与门对第一输入端和第二输入端接收到的信号进行逻辑运算，并将运算结果从第二与门的输出端输出；第二上升沿滤波电路，接收第二与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将开关控制信号传输至第二控制端；其中，B>0。
可选的，第一上升沿滤波电路包括第一延时电路和第三与门；第一上升沿滤波电路，接收第一与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将开关控制信号传输至第一控制端，包括：第一延时电路接收第一与门的输出端输出的数字信号，经第一延时电路的延时作用，对数字信号延时ans后，输出延时数字信号；其中，延时数字信号与数字信号在每个脉冲周期的前Ans中的高电平错时；a≤A；第三与门对第一延时电路输出的延时数字信号和第一与门的输出端输出的数字信号进行逻辑运算，以滤除数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将开关控制信号传输至第一控制端。
可选的，第一上升沿滤波电路包括第一电流趋势判断电路、第五与门以及第一触发器；第一上升沿滤波电路，接收第一与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将开关控制信号传输至第一控制端，包括：第一电流趋势判断电路接收并处理电流端的信号，在电流端 的信号呈上升趋势的情况下，向第五与门的第一输入端输入1；在电流端的信号呈下降趋势的情况下，向第五与门的第一输入端输入0；第五与门对第一与门的输出端输出的数字信号和第一电流趋势判断电路输出的信号进行逻辑运算，滤除数字信号在每个脉冲周期的前Ans的上升沿信号，并将运算结果输出至第一触发器的置位端；第一触发器根据复位端和置位端的信号，生成开关控制信号，并将开关控制信号传输至第一控制端。
可选的，第二上升沿滤波电路包括第二延时电路和第四与门；第二上升沿滤波电路，接收第二与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将开关控制信号传输至第二控制端，包括：第二延时电路接收第二与门的输出端输出的数字信号，经第二延时电路的延时作用，对数字信号延时bns后，输出延时数字信号；其中，延时数字信号与数字信号在每个脉冲周期的前Bns中的高电平错时；b≤B；第四与门对第二延时电路输出的延时数字信号和第二与门的输出端输出的数字信号进行逻辑运算，以滤除数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将开关控制信号传输至第二控制端。
可选的，第二上升沿滤波电路包括第二电流趋势判断电路、第六与门以及第二触发器；第二上升沿滤波电路，接收第二与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将开关控制信号传输至第二控制端，包括：第二电流趋势判断电路接收并处理电流端的信号，在电流端的信号呈上升趋势的情况下，向第六与门的第一输入端输入0；在电流端的信号呈下降趋势的情况下，向第六与门的第一输入端输入1；第六与门对第二与门的输出端输出的数字信号和第二电流趋势判断电路输出的信号进行逻辑运算，滤除数字信号在每个脉冲周期的前Bns的上升沿信号，并将运算结果输出至第二触发器的置位端；第二触发器根据复位端和置位端的信号，生成开关控制信号，并将开关控制信号传输至第二控制端。
可选的，整流器还包括第二逻辑电路和第二上升沿滤波电路；第二上升沿滤波电路包括第六与门以及第二触发器；第二上升沿滤波电路，接收第二与门的输出端输出的数字信号，并滤除数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将开关控制信号传输至第二控制端，包括：第一电流趋势判断电路接收并处理电流端的信号，在电流端的信号呈上升趋势的情况下，向第六与门的第一输入端输入0；在电流端的信号呈下降趋势的情况下，向第六与门的第一输入端输入1；第六与门对第二与门的输出端输出的数字信号和第一电流趋势判断电路输出的信号进行逻辑运算，滤除数字信号在每个脉冲周期的前Bns的上升沿信号，并将运算结果输出至第二触发器的置位端；第二触发器根据复位端和置位端的信号，生成开关控制信号，并将开关控制信号传输至第二控制端。
附图说明
图1为相关技术提供的一种无线功率传输系统的原理图；
图2为本申请实施例提供的一种无线功率传输系统的原理图；
图3a为本申请实施例提供的一种整流器的结构示意图；
图3b为图3a所示的整流器的理论波形图；
图3c为图3a所示的整流器振铃时的波形图；
图4a为本申请实施例提供的另一种整流器的结构示意图；
图4b为图4a所示的整流器的波形图；
图5a为本申请实施例提供的又一种整流器的结构示意图；
图5b为图5a所示的整流器的波形图；
图6a为本申请实施例提供的又一种整流器的结构示意图；
图6b为图6a所示的整流器具体结构示意图；
图6c为图6a所示的整流器的波形图；
图6d为本申请实施例提供的一种整流电路的整流原理示意图；
图6e为本申请实施例提供的另一种整流电路的整流原理示意图；
图6f为本申请实施例提供的一种设备的结构示意图；
图7a为本申请实施例提供的另一种设备的结构示意图；
图7b为图7a所示的设备中的整流控制电路的波形图；
图7c为本申请实施例提供的又一种设备的结构示意图；
图8a为本申请实施例提供的另一种设备的结构示意图；
图8b为图8a所示的设备中的整流控制电路的波形图。
附图标记
10-第一逻辑电路；11-第一比较器；12-第二比较器；13-第一与门；20-第二逻辑电路；21-第三比较器；22-第四比较器；23-第二与门；30-第一上升沿滤波电路；31-第一延时电路；311-第一反相器；312-第二反相器；32-第三与门；33-第一电流趋势判断电路；34-第五与门；35-第一触发器；40-第二上升沿滤波电路；41-第二延时电路；411-第三反相器；412-第四反相器；42-第四与门；43-第二电流趋势判断电路；44-第六与门；45-第二触发器；51-第一开关；52-第二开关；53-第三开关；54-第四开关；V1-第一电压端；V2-第二电压端；V3-第三电压端；V4-第四电压端；V5-第五电压端；VGND-参考地端；Vrect-整流电路的输出端；M1-第一可控开关管；M2-第二可控开关管；M3-第三可控开关管；M4-第四可控开关管；NG1-第一控制端；NG2-第二控制端；AC1-第一连接点；AC2-第二连接点；NG1-1-第一与门的输出端；NG2-1-第二与门的输出端；C3-第三电容；C4-第四电容；Cout-输出电容；NG1-2-第一延时电路的输出端；NG2-2-第二延时电路的输出端；I-电流端；NG1-3-第一电流趋势判断电路的输出端；NG2-3-第二电流趋势判断电路的输出端；L1-线圈；IL1-线圈输出的电流；NG1-4-第五与门的输出端；NG2-4-第六与门的输出端；R-复位端；S-置位端；CK-D触发器的时钟端；D-D触发器的输入端；Q-触发器的输出端。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“耦接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。
本申请实施例提供一种设备，该设备可以是电动汽车、电动摩托车、电动自行车、充电的家用电器(例如豆浆机、扫地机器人)、电子设备(例如智能手机、平板电脑、智能手表、蓝牙耳机、穿戴设备)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机、医疗电子组件等。本申请实施例对上述设备的具体形式不做特殊限制。
以电动汽车为例，电动汽车的电池充电方法通常包括：接触式充电和无线充电。其中，接触式充电采用插头与插座的金属接触来导电，无线充电是以耦合的交变磁场为媒介实现电能的传递。与接触式充电相比，无线充电拥有众多优点，成为未来电动汽车充电的主流方式。
由于通常电的产生和传输是交流形式的，而许多终端用电设备使用的是直流电源。因此，AC/DC(交流/直流)转换器(也称为整流器)在电力电子系统中得到了广泛应用。整流器(rectifier)的作用是把交流电转换为直流电。
实际应用中，如图2所示，无线功率传输系统的功率发送端一般包括功率发送电路，功率发送电路将交流电以交变磁场形式进行发送。无线功率传输系统的功率接收端一般包括功率接收电路，功率接收电路接收来自功率发送电路的交变磁场并输出交流信号。接收端的第一连接点AC1接收到的电压信号和第二连接点AC2接收到的电压信号是交流信号，需要通过整流器把交流信号整成直流信号。即，功率接收电路接收功率发送电路发送的交流信号，并作为交流源向整流器(整流器的第一连接点AC1和第二连接点AC2)提供交流信号。
图2所示的无线功率传输系统可基于由WPC(wireless power consortium，一个主推低频无线电力传输的标准组织)主导的Qi(WPC组织的商标)协议实现无线电力传输(wireless power transfer，WPT)。Qi协议的工作特点是功率发送电路中的线圈L0和功率接收电路中的线圈L1距离很近，工作频率可以根据需要在规定的范围内(110～205KHz)调整。
关于整流器的结构，如图2所示，整流器包括整流电路，整流电路包括第一开关、第二开关、第三开关以及第四开关。图2中以第一开关包括第一可控开关管M1、第二开关包括第二可控开关管M2、第三开关包括第三可控开关管M1、第四开关包括第四可控开关管M4为例进行示意。
第一可控开关管M1的控制端与第一控制端NG1相耦接，第二可控开关管M2的控制端与第一控制端NG1相耦接。第三可控开关管M1的控制端与整流控制电路的第二控制端NG2相耦接。第四可控开关管M4的控制端与第二控制端NG2相耦接。
整流器工作过程中，第一控制端NG1控制第一可控开关管M1和第二可控开关管M2，第二控制端NG2控制第三可控开关管M3和第四可控开关管M4。当第一控制端NG1为高电平时，第一可控开关管M1和第二可控开关管M2导通，当第一控制端NG1为低电平时，第一可控开关管M1和第二可控开关管M2关断。
同理，当第二控制端NG2为高电平时，第三可控开关管M3和第四可控开关管M4导通，当第二控制端NG2为低电平时，第三可控开关管M3和第四可控开关管M4关断。
在一些实施例中，提供一种整流控制电路，用于向整流电路的第一控制端NG1和第二控制端NG2传输开关控制信号。
如图3a所示，整流器包括整流电路和整流控制电路，整流控制电路包括第一逻辑电路10和第二逻辑电路20。
第一逻辑电路10，包括第一比较器11、第二比较器12以及第一与门13。第一比较器11的正向输入端与第一电压端V1相耦接，第一比较器11的反向输入端与第二电压端V2相耦接。第二比较器12的正向输入端与第三电压端V3相耦接，第二比较器12的反向输入端与第四电压端V4相耦接。第一与门13的第一输入端与第一比较器11的输出端相耦接，第一与门13的第二输入端与第二比较器12的输出端相耦接。
当第一电压端V1的电压高于第二电压端V2的电压，第一比较器11输出数字信号1，当第一电压端V1的电压低于第二电压端V2的电压，第一比较器11输出数字信号0。当第三电压端V3的电压高于第四电压端V4的电压时，第二比较器12输出数字信号1，当第三电压端V3的电压低于第四电压端V4的电压时，第二比较器12输出数字信号0。
因此，当第一电压端V1的电压高于第二电压端V2的电压，第三电压端V3的电压高于第四电压端V4的电压时，第一与门13进行与运算后，输出数字信号1，第一控制端NG1为高电平。反之，则第一控制端NG1为低电平。
第二逻辑电路20，包括第三比较器21、第四比较器22以及第二与门23。第三比较器21的正向输入端与第四电压端V4相耦接，第三比较器21的反向输入端与第二电压端V2相耦接。第四比较器22的正向输入端与第三电压端V3相耦接，第四比较器22的反向输入端与第一电压端V1相耦接。第二与门23的第一输入端与第三比较器21的输出端相耦接，第二与门23的第二输入端与第四比较器22的输出端相耦接。
当第四电压端V4的电压高于第二电压端V2的电压时，第三比较器21输出数字信号1，当第四电压端V4的电压低于第二电压端V2的电压时，第三比较器21输出数字信号0。当第三电压端V3的电压高于第一电压端V1的电压时，第四比较器22输出数字信号1，当第三电压端V3的电压低于第一电压端V1的电压时，第四比较器22输出数字信号0。
因此，当第四电压端V4的电压高于第二电压端V2的电压，第三电压端V3的电压高于第一电压端V1的电压时，第二与门23进行与运算后，输出数字信号1，第二控制端NG2为高电平。反之，则第二控制端NG2为低电平。
其中，第一电压端V1与第一连接点AC1相耦接，接收功率接收电路输出的方波信号。第四电压端V4与第二连接点AC2相耦接，接收功率接收电路输出的方波信号。 即，功率接收电路提供差分电压，差分电压分别与第一电压端V1和第四电压端V4相耦接。第二电压端V2与整流电路的输出端Vrect相耦接。第三电压端V3与参考地端VGND相耦接。
在实践中发现，采用上述整流控制电路向整流电路的第一控制端NG1和第二控制端NG2传输开关控制信号的过程中，由于Qi协议下的无线充电开关频率范围分布较宽，在较高的工作频率下，整流器不易出问题。
如图3b所示，流经功率接收电路中的线圈L1的电流为图3b中的IL1，是一个类似于正弦波一样的电流。接收端的第一连接点AC1接收到的电压信号和第二连接点AC2接收到的电压信号是一个方波，接收端的第一连接点AC1接收到的电压信号和第二连接点AC2接收到的电压信号经过整流电路整流后产生的直流电压为图3b中的Vrect。
然而，在较低的工作频率下，整流器有可能会出现振铃现象，这种现象的出现给整流电路的开关逻辑带来很大干扰，严重时会导致整流器输出产生震荡并且影响功率发送端与功率接收端间的通信。
如图3c所示，功率接收电路中的线圈L1产生的电流不再是标准正弦波，而是在一个大的正弦电流两侧存在小的由于功率接收电路中的并联谐振电容C2(如图2所示)产生的正弦电流。振铃现象导致整流电路在关断后不久又被并联谐振导致的小正弦电流重新导通，通常情况下这些小的正弦电流频率很高，在整流电路导通后就需要马上关断，如果无法做到马上准确关断就会导致整流逻辑错误，使得整流电路的输出Vrect震荡。
基于此，在一些实施例中，提供一种整流控制电路，如图4a所示，整流控制电路在包括第一逻辑电路10和第二逻辑电路20的基础上，还包括第一导通时间控制电路和第二导通时间控制电路。
第一导通时间控制电路与第一逻辑电路10相耦接，用于延长第一逻辑电路10输出的导通信号(高电平信号)的持续时间。
第二导通时间控制电路与第二逻辑电路20相耦接，用于延长第二逻辑电路20输出的导通信号的持续时间。
如图4b所示，因功率接收电路中的并联谐振电容C2(如图2所示)产生的正弦电流(大的正弦电流两侧存在的小的正弦电流)，导致整流控制电路向整流电路的第一控制端NG1输出导通信号时，在设置第一导通时间控制电路后，此时输出的导通信号持续输出(可设定一个持续时间)。一直持续到，由功率接收电路产生的大的正弦电流使整流控制电路向整流电路的第一控制端NG1输出导通信号。从而避免了因第一控制端NG1输出导通信号震荡，导致整流器输出产生震荡的问题。同理，在设置第二导通时间控制电路后，整流控制电路向整流电路的第一控制端NG1输出导通信号也为有规律的波形，可避免因第二控制端NG2输出导通信号震荡，导致整流器输出产生震荡的问题。
然而，如图4b所示，以第一导通时间控制电路为例，在第一导通时间控制电路控制整流控制电路向第一控制端NG1持续输出导通信号的期间，如果并联谐振电容C2产生的正弦电流存在过零(也就是电流改变了方向)，而又没有关断整流电路中的第 一可控开关管M1和第二可控开关管M2，会导致电流倒灌。这样一来，不仅有效率上的损失，如果倒灌严重还可能会导致整流器存在可靠性问题。
基于此，如图5a所示，本申请实施例还提供一种整流控制电路，在包括上述第一逻辑电路10的基础上，还包括第一上升沿滤波电路30。
第一上升沿滤波电路30，与第一与门13的输出端NG1-1和第一控制端NG1相耦接，用于接收第一与门13的输出端NG1-1输出的数字信号，并滤除数字信号在每个脉冲周期的前Ans(A纳秒)的上升沿信号，生成开关控制信号，并将开关控制信号传输至第一控制端NG1。
如图5b所示，因整流器的振铃问题，导致第一与门13的输出端NG1-1输出的数字信号存在波形震荡(如点划线圆圈处)。在增加与第一与门13的输出端NG1-1相耦接的第一上升沿滤波电路30后，对第一与门13的输出端NG1-1输出的数字信号进行滤波，将每个脉冲周期的前Ans的上升沿信号滤除，对Ans后的数字信号正常输出。这样一来，如图5b所示，可滤除第一与门13的输出端NG1-1输出的数字信号中点划线圆圈处的高电平信号，第一上升沿滤波电路30向第一控制端NG1输出的开关控制信号为有规律的波形图。
其中，A>0。可根据谐振频率、输出负载电流、输出电压调整滤波时间A。
例如，在一些实施例中，A<500ns。通过调整A的取值，可以滤除第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号(划线圆圈处的高电平信号)。A的取值不同，第一上升沿滤波电路30向第一控制端NG1输出的开关控制信号的波形也略有不同。
在此基础上，如图5a所示，整流控制电路在包括上述第二逻辑电路20的基础的上，还包括：第二上升沿滤波电路40。
第二上升沿滤波电路40，与第二与门23的输出端NG2-1和第二控制端NG2相耦接，用于接收第二与门23的输出端NG2-1输出的数字信号，并滤除数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将开关控制信号传输至第二控制端NG2。
其中，B>0。
同理，如图5b所示，因整流器的振铃问题，导致第二与门23的输出端NG2-1输出的数字信号存在波形震荡(如点划线圆圈处)。在增加与第二与门23的输出端NG2-1相耦接的第二上升沿滤波电路40后，对第二与门23的输出端NG2-1输出的数字信号进行滤波，将每个脉冲周期的前Bns的上升沿信号滤除，对Bns后的数字信号正常输出。这样一来，如图5b所示，可滤除第二与门23的输出端NG2-1输出的数字信号中点划线圆圈处的高电平信号，第二上升沿滤波电路40向第二控制端NG2输出的开关控制信号为有规律的波形图。
其中，B>0。滤波时间B与谐振频率有关，通过调整B的取值，可以滤除第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号(划点线圆圈处的高电平信号)。B的取值不同，第二上升沿滤波电路40向第二控制端NG2输出的开关控制信号的波形也略有不同。
需要说明的是，如图5b所示，若是第一与门13的输出端NG1-1输出的数字信号 和第二与门23的输出端NG2-1输出的数字信号分别看各自的脉冲周期，则A可以等于B。当然，A也可以不等于B。若统一同一时间段为一个脉冲周期，因第一与门13的输出端NG1-1输出的数字信号和第二与门23的输出端NG2-1输出的数字信号开始输出高电平信号的时间点不同，此时A不等于B。
下面，对本申请实施例提供的整流控制电路的驱动方法进行说明。
整流控制电路驱动过程中，第一比较器11的正向输入端接收第一电压端V1的信号，第一比较器11的反向输入端接收第二电压端V2的信号，第一比较器11对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从第一比较器11的输出端输出。
当第一电压端V1的电压高于第二电压端V2的电压(V1>V2)时，第一比较器11的输出端输出数字信号1。当第一电压端V1的电压低于第二电压端V2的电压(V1<V2)时，第一比较器11的输出端输出数字信号0。
第二比较器12的正向输入端接收第三电压端V3的信号，第二比较器12的反向输入端接收第四电压端V4的信号，第二比较器12对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从第二比较器12的输出端输出。
当第三电压端V3的电压高于第四电压端V4的电压(V3>V4)时，第二比较器12的输出端输出数字信号1。当第三电压端V3的电压低于第四电压端V4的电压(V3<V4)时，第二比较器12的输出端输出数字信号0。
第一与门13第一输入端接收第一比较器11的输出端输出的信号，第一与门13的第二输入端接收第二比较器12的输出端输出的信号，第一与门13对第一输入端和第二输入端接收到的信号进行逻辑运算，并将运算结果从第一与门13的输出端NG1-1输出。
当第一比较器11的输出端输出数字信号1，第二比较器12的输出端输出数字信号1，第一与门13进行与逻辑运算后，第一与门13的输出端NG1-1输出数字信号1。当第一比较器11的输出端输出数字信号1，第二比较器12的输出端输出数字信号0，第一与门13进行与逻辑运算后，第一与门13的输出端NG1-1输出数字信号0。
当第一比较器11的输出端输出数字信号0，第二比较器12的输出端输出数字信号1，第一与门13进行与逻辑运算后，第一与门13的输出端NG1-1输出数字信号0。当第一比较器11的输出端输出数字信号0，第二比较器12的输出端输出数字信号0，第一与门13进行与逻辑运算后，第一与门13的输出端NG1-1输出数字信号0。
如图5b所示，因功率接收电路中的线圈L1产生的电流IL1不再是标准正弦波，而是在一个大的正弦电流两侧存在小的由于功率接收电路中的并联谐振电容C2(如图2所示)产生的正弦电流。因此，第一连接点AC1和第二连接点AC2处的电压对应性的产生了波动。也就是说，第一电压端V1和第四电压端V4的电压对应性的产生了波动。
第一电压端V1的波形图中，点划线方框处，第一电压端V1的电压低于第二电压端V2的电压，第一比较器11的输出端输出数字信号0。第四电压端V4的波形图中，点划线方框处，第三电压端V3的电压低于第四电压端V4的电压，第二比较器12的输出端输出数字信号0。此时，第一与门13的输出端NG1-1输出数字信号0(如图中 点划线方框处箭头所指的位置处)。
第一电压端V1的波形图中，点划线方框前后处第一电压端V1的电压都高于第二电压端V2的电压，第一比较器11的输出端输出数字信号1。第四电压端V4的波形图中，点划线方框前后处第三电压端V3的电压都高于第四电压端V4的电压，第二比较器12的输出端输出数字信号1。此时，第一与门13的输出端NG1-1输出数字信号1。
基于此，如图5b所示，第一与门13的输出端NG1-1输出的数字信号为，实需高电平信号(如图5b中点划线方框处)之前具有一个短时间段的震荡高电平信号(如图5b中点划线圆圈处)。
第一上升沿滤波电路30，接收第一与门13的输出端NG1-1输出的数字信号，并滤除数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将开关控制信号传输至第一控制端NG1。
第一上升沿滤波电路30，接收第一与门13的输出端NG1-1输出的数字信号，对第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号进行滤除，向第一控制端NG1输出的开关控制信号中的高电平信号仅剩实需高电平信号。
同理，第三比较器21的正向输入端接收第四电压端V4的信号，第三比较器21的反向输入端接收第二电压端V2的信号，第三比较器21对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从第三比较器21的输出端输出。
当第四电压端V4的电压高于第二电压端V2的电压(V4>V2)时，第四比较器22的输出端输出数字信号1。当第四电压端V4的电压低于第二电压端V2的电压(V4<V2)时，第四比较器22的输出端输出数字信号0。
第四比较器22的正向输入端接收第三电压端V3的信号，第四比较器22的反向输入端接收第一电压端V1的信号，第四比较器22对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从第四比较器22的输出端输出。
当第三电压端V3的电压高于第一电压端V1的电压(V3>V1)时，第四比较器22的输出端输出数字信号1。当第三电压端V3的电压低于第一电压端V1的电压(V3<V1)时，第四比较器22的输出端输出数字信号0。
第二与门23第一输入端接收第三比较器21的输出端输出的信号，第二与门23的第二输入端接收第四比较器22的输出端输出的信号，第二与门23对第一输入端和第二输入端接收到的信号进行逻辑运算，并将运算结果从第二与门23的输出端NG2-1输出。
当第三比较器21的输出端输出数字信号1，第四比较器22的输出端输出数字信号1，第二与门23进行与逻辑运算后，第二与门23的输出端NG2-1输出数字信号1。当第三比较器21的输出端输出数字信号1，第四比较器22的输出端输出数字信号0，第二与门23进行与逻辑运算后，第二与门23的输出端NG2-1输出数字信号0。
当第三比较器21的输出端输出数字信号0，第四比较器22的输出端输出数字信号1，第二与门23进行与逻辑运算后，第二与门23的输出端NG2-1输出数字信号0。当第三比较器21的输出端输出数字信号0，第四比较器22的输出端输出数字信号0，第二与门23进行与逻辑运算后，第二与门23的输出端NG2-1输出数字信号0。
其中，如图5b所示，一个脉冲中，第一电压端V1的电压和第四电压端V4相位相差约180°。基于此，忽略到波形震荡，在第一段中，V1>V2，V3>V4。第一与门13的输出端NG1-1输出数字信号1。同时满足，V4<V2，V3<V1。第二与门23的输出端NG2-1输出数字信号0。在第二段中，V1<V2，V3<V4。第一与门13的输出端NG1-1输出数字信号0。同时满足，V4>V2，V3>V1。第二与门23的输出端NG2-1输出数字信号1。
也就是说，第一与门13输出数字信号1时，第二与门23的输出端NG2-1输出数字信号0。第一与门13输出数字信号0时，第二与门23的输出端NG2-1输出数字信号1。
受第一电压端V1和第四电压端V4的电压产生的波动影响，如图5b所示，第二与门23的输出端NG2-1输出的数字信号为，实需高电平信号(如图5b中点划线方框处)之前具有一个短时间段的震荡高电平信号(如图5b中点划线圆圈处)。
第二上升沿滤波电路40，接收第二与门23的输出端NG2-1输出的数字信号，并滤除数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将开关控制信号传输至第二控制端NG2。
第二上升沿滤波电路40，接收第二与门23的输出端NG2-1输出的数字信号，对第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号进行滤除，向第二控制端NG2输出的开关控制信号中的高电平信号仅剩实需高电平信号。
本申请实施例提供的整流控制电路，通过在第一与门13的与第一控制端NG1之间增加第一上升沿滤波电路30，对第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号进行滤除，使得第一控制端NG1接收到的开关控制信号中的高电平信号仅剩实需高电平信号，开关控制信号的波形有规律。这样一来，在振铃现象发生时，可避免第一控制端NG1接收到导通信号，从而避免与第一控制端NG1相耦接的可控开关管导通。第一控制端NG1接收到的高电平信号仅剩实需高电平信号，使得与第一控制端NG1相耦接的可控开关管都是在主功率传输阶段导通，使得整流器的输出稳定性，波动较小。
下面，以几个详细的实施例，对本申请实施例提供的整流器进行说明。
实施例一
如图6a所示，整流器包括整流控制电路和整流电路。
整流控制电路包括第一逻辑电路10、第一上升沿滤波电路30、第二逻辑电路20以及第二上升沿滤波电路40。
第一逻辑电路10，包括第一比较器11、第二比较器12以及第一与门13。
第一比较器11的正向输入端与第一电压端V1相耦接，第一比较器11的反向输入端与第二电压端V2相耦接。
当第一电压端V1的电压高于第二电压端V2的电压时，第一比较器11的输出端输出数字信号1。当第一电压端V1的电压低于第二电压端V2的电压时，第一比较器11的输出端输出数字信号0。
第二比较器12的正向输入端与第三电压端V3相耦接，第二比较器12的反向输入端与第四电压端V4相耦接。
当第三电压端V3的电压高于第四电压端V4的电压时，第二比较器12的输出端输出数字信号1。当第三电压端V3的电压低于第四电压端V4的电压时，第二比较器12的输出端输出数字信号0。
第一与门13的第一输入端与第一比较器11的输出端相耦接，第一与门13的第二输入端与第二比较器12的输出端相耦接。
当第一比较器11的输出端输出数字信号1，第二比较器12的输出端输出数字信号1，第一与门13进行与逻辑运算后，第一与门13的输出端NG1-1输出数字信号1。当第一比较器11的输出端输出数字信号0，第二比较器12的输出端输出数字信号0，第一与门13进行与逻辑运算后，第一与门13的输出端NG1-1输出数字信号0。
受第一电压端V1和第四电压端V4的电压产生的波动影响，如图6c所示，第一与门13的输出端NG1-1输出的数字信号为，实需高电平信号之前具有一个短时间段的震荡高电平信号。
关于第一上升沿滤波电路30的结构，如图6a所示，第一上升沿滤波电路30包括第一延时电路31和第三与门32。
第一延时电路31与第一与门13的输出端NG1-1和第三与门32的第一输入端相耦接。
第一延时电路31接收第一与门13的输出端NG1-1输出的数字信号，经第一延时电路31的延时作用，对第一与门13的输出端NG1-1输出的数字信号延时ans后，将延时数字信号输出至第三与门32的第一输入端。
其中，a≤A。延时数字信号与数字信号在每个脉冲周期的前Ans中的高电平错时。通过使a大于第一与门13的输出端NG1-1输出的数字信号中震荡高电平信号持续的时间，可完全的滤除掉第一与门13的输出端NG1-1输出的数字信号中震荡高电平信号。
不对第一延时电路31的结构进行限定，在一些实施例中，如图6b所示，第一延时电路31包括第一反相器311、第二反相器312以及第三电容C3。
第一反相器311和第二反相器312串联在第一与门13的输出端NG1-1与第三与门32的第一输入端之间，第三电容C3的一端耦接与第一反相器311和第二反相器312之间，另一端耦接于参考地端。
第三与门32的第二输入端还与第一与门13的输出端NG1-1相耦接，第三与门32的输出端与第一控制端NG1相耦接。
第三与门32对第一延时电路31输出的延时数字信号和第一与门13的输出端NG1-1输出的数字信号进行逻辑运算，以滤除数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将开关控制信号传输至第一控制端NG1。
如图6b所示，第三与门32的第二输入端与第一与门13的输出端NG1-1相耦接，相当于第三与门32的第二输入端与第三电容C3的一端相耦接。第三与门32的第一输入端与第三电容C3的另一端相耦接。相当于说第三与门32对第三电容C3两端的电压进行与运算，从而可起到延时作用。
当第三与门32的第一输入端接收到的数字信号为1，第三与门32的第二输入端接收到的数字信号为1时，第三与门32的输出端向第一控制端NG1输出的开关控制 信号为1。当第三与门32的第一输入端接收到的数字信号为0，第三与门32的第二输入端接收到的数字信号为0时，第三与门32的输出端向第一控制端NG1输出的开关控制信号为0。
当第三与门32的第一输入端接收到的数字信号为1，第三与门32的第二输入端接收到的数字信号为0时，第三与门32的输出端向第一控制端NG1输出的开关控制信号为0。当第三与门32的第一输入端接收到的数字信号为0，第三与门32的第二输入端接收到的数字信号为1时，第三与门32的输出端向第一控制端NG1输出的开关控制信号为0。
基于此，如图6c所示，第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号和第三电容C3(也就是第一延时电路31的输出端NG1-2)输出的延时数字信号中的震荡高电平信号完全错开。只有在二者输出的数字信号均为1时，第三与门32的输出端向第一控制端NG1输出的开关控制信号才为1，反之，第三与门32的输出端向第一控制端NG1输出的开关控制信号为0。
可以理解的是，由于第一与门13的输出端NG1-1输出的数字信号的主功率传输阶段(图6c中第一与门13的输出端NG1-1输出的数字信号的加粗部分)持续的时间比较长，因此，即使第一延时电路31的输出端NG1-2输出的延时数字信号的主功率传输阶段(图6c中第一延时电路31的输出端NG1-2输出的延时数字信号的加粗部分)与第一与门13的输出端NG1-1输出的数字信号的主功率传输阶段有延时错位，但二者还是会有信号同为1的时候。因此，经第三与门32进行与运算后，第三与门32仍会向第一控制端NG1输出数字信号1。
第二逻辑电路20，包括第三比较器21、第四比较器22以及第二与门23。
第三比较器21的正向输入端与第四电压端V4相耦接，第三比较器21的反向输入端与第二电压端V2相耦接。
当第四电压端V4的电压高于第二电压端V2的电压时，第二比较器12的输出端输出数字信号1。当第四电压端V4的电压低于第二电压端V2的电压时，第二比较器12的输出端输出数字信号0。
第四比较器22的正向输入端与第三电压端V3相耦接，第四比较器22的反向输入端与第一电压端V1相耦接。
当第三电压端V3的电压高于第一电压端V1的电压时，第四比较器22的输出端输出数字信号1。当第三电压端V3的电压低于第一电压端V1的电压时，第四比较器22的输出端输出数字信号0。
第二与门23的第一输入端与第三比较器21的输出端相耦接，第二与门23的第二输入端与第四比较器22的输出端相耦接。
当第三比较器21的输出端输出数字信号1，第四比较器22的输出端输出数字信号1，第二与门23进行与逻辑运算后，第二与门23的输出端NG2-1输出数字信号1。当第三比较器21的输出端输出数字信号0，第四比较器22的输出端输出数字信号0，第二与门23进行与逻辑运算后，第二与门23的输出端NG2-1输出数字信号0。
受第一电压端V1和第四电压端V4的电压产生的波动影响，如图6c所示，第二与门23的输出端NG2-1输出的数字信号为，实需高电平信号之前具有一个短时间段 的震荡高电平信号。
第二上升沿滤波电路40包括第二延时电路41和第四与门42。
第二延时电路41与第二与门23的输出端NG2-1和第四与门42的第一输入端相耦接。
第二延时电路41接收第二与门23的输出端NG2-1输出的数字信号，经第二延时电路41的延时作用，对第二与门23的输出端NG2-1输出的数字信号延时bns后，将延时数字信号输出至第四与门42的第一输入端。
其中，b≤B。延时数字信号与数字信号在每个脉冲周期的前Bns中的高电平错时。
通过使b大于第二与门23的输出端NG2-1输出的数字信号中震荡高电平信号持续的时间，可完全的滤除掉第二与门23的输出端NG2-1输出的数字信号中震荡高电平信号。
第二延时电路41，用于接收第二与门23的输出端NG2-1输出的数字信号，并对第二与门23的输出端NG2-1输出的数字信号进行延时后输出至第四与门42的第一输入端。
不对第二延时电路41的结构进行限定，在一些实施例中，如图6b所示，第二延时电路41包括第三反相器411、第四反相器412以及第四电容C4。
第三反相器411和第四反相器412串联在第二与门23的输出端NG2-1与第四与门42的第一输入端之间，第四电容C4的一端耦接于第三反相器411和第四反相器412之间，另一端耦接于参考地端。
如图6c所示，第二与门23的输出端NG2-1输出的数字信号传输至第四电容C4，第四电容C4进行充电，随后将第二与门23的输出端NG2-1输出的数字信号传输至第四与门42的第一输入端。第四电容C4(也就是第二延时电路41的输出端NG2-2)输出的延时数字信号与第二与门23的输出端NG2-1输出的数字信号有一定的错位。通过调整第四电容C4的大小，可使第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号和第四电容C4(也就是第二延时电路41的输出端NG2-2)输出的延时数字信号中的震荡高电平信号完全错开。
第四与门42的第二输入端还与第二与门23的输出端NG2-1相耦接，第四与门42的输出端与第二控制端NG2相耦接。
第四与门42对第二延时电路41输出的延时数字信号和第二与门23的输出端NG2-1输出的数字信号进行逻辑运算，以滤除数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将开关控制信号传输至第二控制端NG2。
如图6b所示，第四与门42的第二输入端与第二与门23的输出端NG2-1相耦接，相当于第四与门42的第二输入端与第四电容C4的一端相耦接。第四与门42的第一输入端与第四电容C4的另一端相耦接。相当于说第四与门42对第四电容C4两端的电压进行与运算，从而可起到延时作用。
当第四与门42的第一输入端接收到的数字信号为1，第四与门42的第二输入端接收到的数字信号为1时，第四与门42的输出端向第二控制端NG2输出的开关控制信号为1。当第四与门42的第一输入端接收到的数字信号为0，第四与门42的第二输入端接收到的数字信号为0时，第四与门42的输出端向第二控制端NG2输出的开关 控制信号为0。
当第四与门42的第一输入端接收到的数字信号为1，第四与门42的第二输入端接收到的数字信号为0时，第四与门42的输出端向第二控制端NG2输出的开关控制信号为0。当第四与门42的第一输入端接收到的数字信号为0，第四与门42的第二输入端接收到的数字信号为1时，第四与门42的输出端向第二控制端NG2输出的开关控制信号为0。
基于此，如图6c所示，第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号和第四电容C4(也就是第二延时电路41的输出端NG2-2)输出的延时数字信号中的震荡高电平信号完全错开。只有在二者输出的数字信号均为1时，第四与门42的输出端向第二控制端NG2输出的开关控制信号才为1，反之，第四与门42的输出端向第二控制端NG2输出的开关控制信号为0。
如图6a所示，整流电路包括第一开关51、第二开关52、第三开关53以及第四开关54。
第一开关51，用于连通第一连接点AC1和第二电压端V2，第一开关51的控制端与第一控制端NG1相耦接。
第一开关51，例如包括一个第一可控开关管M1，或包括多个并联的第一可控开关管M1。
第二开关52，用于连通第三电压端V3和第二连接点AC2，第二开关52的控制端与第一控制端NG1相耦接。
第二开关52，例如包括一个第二可控开关管M2，或包括多个并联的第二可控开关管M2。
第三开关53，用于连通第一连接点AC1和第三电压端V3，第三开关53的控制端与整流控制电路的第二控制端NG2相耦接。
第三开关53，例如包括一个第三可控开关管M3，或包括多个并联的第三可控开关管M3。
第四开关54，用于连通第二连接点AC2以及第二电压端V2，第四开关54与第二控制端NG2相耦接。
第四开关54，例如包括一个第四可控开关管M4，或包括多个并联的第四可控开关管M4。
如图6a所示，整流控制电路的第一电压端V1与第一连接点AC1相耦接，整流控制电路的第四电压端V4与第二连接点AC2相耦接。
其中，第二电压端V2为整流电路的输出电压端。
通过上述关于图6c的描述可知，第一控制端NG1接收到的开关控制信号为1时，第二控制端NG2接收到的开关控制信号为0。第一控制端NG1接收到的开关控制信号为0时，第二控制端NG2接收到的开关控制信号为1。也就是说，受第一控制端NG1控制的第一开关51和第二开关52，与受第二控制端NG2控制的第三开关53和第四开关54错时导通。
基于此，如图6d所示，第一控制端NG1接收到的开关控制信号为1，第二控制端NG2接收到的开关控制信号为0。第三开关53和第四开关54关断，第一开关51 和第二开关52导通，形成的回路如图6d中箭头所示。此时，将第一连接点AC1的高电平信号传输至第二电压端V2(整流电路的输出端Vrect)。同理，如图6e所示，第一控制端NG1接收到的开关控制信号为0，第二控制端NG2接收到的开关控制信号为1。第一开关51和第二开关52关断，第三开关53和第四开关54导通，形成的回路如图6e中箭头所示。此时，将第二连接点AC2的高电平信号传输至第二电压端V2(整流电路的输出端Vrect)。
这样一来，如图6c所示，第一连接点AC1和第二连接点AC2处的交流电压经整流电路整流后，输出端Vrect输出的为直流电压。
在一些实施例中，如图6f所示，整流器还包括储能电路，储能电路与第二电压端V2和第三电压端V3相耦接，用于对第二电压端V2的电信号进行缓存，还用于释放存储在其内部的电信号。
不对储能电路的结构进行限定，如图6f所示，储能电路例如可以包括输出电容Cout。
整流器的第二电压端V2(也可以理解为整流器的输出端)与负载相耦接，用于向负载传输电信号。在第一连接点AC1和第二连接点AC2均无法向第二电压端V2传输电信号时，储能电路释放存储在其内部的电信号，向负载供电。
其中，当将本申请实施例提供的整流器应用到设备中时，如图6f所示，整流器的第一连接点AC1和第二连接点AC2的与设备中的功率接收电路相耦接，第一连接点AC1和第二连接点AC2的电信号来自功率接收电路。
本申请实施例提供的整流器，通过在整流控制电路中增加第一延时电路31，可使第一延时电路31的输出端NG1-2输出的延时数字信号中的震荡高电平信号，与第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号错开，在将第一延时电路31的输出端NG1-2输出的延时数字信号与第一与门13的输出端NG1-1输出的数字信号进行与运算后，可以滤除震荡高电平信号，整流控制电路向第一控制端NG1输出有规律的开关控制信号。
同理，通过在整流控制电路中增加第二延时电路41，可使第二延时电路41的输出端NG2-2输出的延时数字信号中的震荡高电平信号，与第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号错开，在将第二延时电路41的输出端NG2-2输出的延时数字信号与第二与门23的输出端NG2-1输出的数字信号进行与运算后，可以滤除第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号，使得整流控制电路向第二控制端NG2输出有规律的开关控制信号。
实施例二
实施例二与实施例一的相同之处在于，整流电路的结构相同。
实施例二与实施例一的不同之处在于，整流控制电路中的第一上升沿滤波电路30的结构不同。
如图7a所示，整流器包括整流控制电路和整流电路。
整流控制电路包括第一逻辑电路10、第一上升沿滤波电路30、第二逻辑电路20以及第二上升沿滤波电路40。
第一逻辑电路10的结构和第二逻辑电路20的结构，可以与实施例一相同，可参考实施例一中关于第一逻辑电路10和第二逻辑电路20的描述，此处不再赘述。
第一上升沿滤波电路30，包括第一电流趋势判断电路33、第五与门34以及第一触发器35。
第一电流趋势判断电路33，与电流端I和第五与门34的第一输入端相耦接。第一电流趋势判断电路33用于接收并处理电流端I的信号，在电流端I的信号呈上升趋势的情况下，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号1。在电流端I的信号呈下降趋势的情况下，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号0。
其中，设备的功率接收电路会接收由功率发送端的自功率发送电路发送的交变磁场并输出交流电。流经功率接收电路中的线圈L1的电流为图7b中的IL1，是一个类似于正弦波一样的电流。线圈L1的电流IL1分为呈上升趋势的阶段和呈下降趋势的阶段。
第一电流趋势判断电路33中的电流端I可以与功率接收电路中的线圈L1相耦接，用于接收线圈L1输出的正弦波一样的电流IL1。
第一电流趋势判断电路33对线圈L1输出的电流IL1的变化趋势进行判断，在电流端I的信号呈上升趋势的情况下，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号1。在电流端I的信号呈下降趋势的情况下，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号0。
其中，不对第一电流趋势判断电路33的结构进行限定，例如可以是数字电路或者模拟电路。
例如，第一电流趋势判断电路33通过对线圈L1输出的电流IL1求一阶导数(即求斜率)，通过判断线圈L1输出的电流IL1的一阶导数是否大于0，来判断出线圈L1输出的电流IL1的趋势。在线圈L1输出的电流IL1的一阶导数大于0的情况下，判断线圈L1输出的电流IL1呈上升趋势，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号1。在线圈L1输出的电流IL1的一阶导数小于0的情况下，判断线圈L1输出的电流IL1呈下降趋势，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号0。
或者，第一电流趋势判断电路33通过对线圈L1输出的电流IL1进行采样，并对比后一电流值与前一电流值的大小，从而判断出线圈L1输出的电流IL1的趋势。在后一电流值大于前一电流值的情况下，判断线圈L1输出的电流IL1呈上升趋势，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号1。在后一电流值小于前一电流值的情况下，判断线圈L1输出的电流IL1呈下降趋势，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号0。
当然，第一电流趋势判断电路33还可以通过其他方式判断电流端I电流的趋势，上述仅是一种示意，不做限定。
第五与门34的第二输入端与第一与门13的输出端NG1-1相耦接，第五与门34的输出端NG1-4与第一触发器35的置位端S相耦接。
第五与门34对第一与门13的输出端NG1-1输出的数字信号和第一电流趋势判断 电路33输出的信号进行逻辑运算，并将运算结果输出至第一触发器35的置位端S。
如图7b所示，第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号总是出现在线圈L1输出的电流IL1呈下降趋势的阶段。而第一电流趋势判断电路33在电流端I的信号呈下降趋势的情况下，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号0。
这样一来，第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号出现时，向第五与门34的第二输入端输入数字信号1，而第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入数字信号为0。第五与门34经与运算后，第五与门34的输出端NG1-4向第一触发器35的置位端S输出数字信号0。从而可以滤除第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号，以实现滤除数字信号在每个脉冲周期的前Ans的上升沿信号。
第一触发器35的复位端R与第一与门13的输出端NG1-1相耦接，第一触发器35的输出端Q与第一控制端NG1相耦接。
也就是说，第一触发器35根据复位端R和置位端S的信号，生成开关控制信号，并将开关控制信号从输出端Q传输至第一控制端NG1。
关于第一触发器35的结构，在一种可能的实施例中，如图7a所示，第一触发器35为第一RS触发器(latch)。根据RS触发器的原理，在第一RS触发器的置位端S接收到的数字信号为1，第一RS触发器的复位端R接收到的数字信号也为1时，第一RS触发器的输出端Q向第一控制端NG1输出数字信号1。在第一RS触发器的置位端S接收到的数字信号为0，第一RS触发器的复位端R接收到的数字信号也为0时，第一RS触发器的输出端Q向第一控制端NG1输出数字信号0。
在第一RS触发器的置位端S接收到的数字信号为0，第一RS触发器的复位端R接收到的数字信号为1时，第一RS触发器的输出端Q跟随上一个输出状态。
如图7b所示，在第一RS触发器的复位端R接收到的数字信号为震荡高电平信号时，第一RS触发器的置位端S接收到的数字信号为0，第一RS触发器的输出端Q跟随上一个输出状态。而上一个输出状态中，第一RS触发器的置位端S接收到的数字信号为0，第一RS触发器的复位端R接收到的数字信号也为0，第一RS触发器的输出端Q向第一控制端NG1输出数字信号0。因此，在第一RS触发器的复位端R接收到的数字信号为震荡高电平信号时，第一RS触发器的输出端Q向第一控制端NG1输出数字信号0。
如图7b所示，在第一RS触发器的复位端R接收到的数字信号为实需高电平信号时，第一RS触发器的置位端S接收到的数字信号先为1，此时第一RS触发器的输出端Q向第一控制端NG1输出数字信号1。随后，第一RS触发器的置位端S接收到的数字信号变为0，此时第一RS触发器的输出端Q跟随上一个输出状态，第一RS触发器的输出端Q向第一控制端NG1仍输出数字信号1。
由于若第一RS触发器的复位端R接收到的数字信号为0，即，第一与门13的输出端NG1-1输出的数字信号为0，第五与门34的输出端NG1-4输出的数字信号必然为0，即，第一RS触发器的置位端S接收到的数字信号必然为0。因此，基于本申请实施例提供的整流控制电路，不会出现在第一RS触发器的置位端S接收到的数字信 号为1，第一RS触发器的复位端R接收到的数字信号也0的状态。
基于此，如图7b所示，第一RS触发器根据复位端R和置位端S的信号生成的开关控制信号，滤除掉了震荡高电平信号，只保留了实需高电平信号。
如图7b所示，第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号出现时，电流端I的电流(线圈L1输出的电流IL1)呈下降趋势。第一与门13的输出端NG1-1输出的数字信号中的实需高电平信号出现时，电流端I的电流呈上升趋势。因此，通过第一电流趋势判断电路33判断电流端I的电流趋势，只有在电流端I的电流呈上升趋势时，第一电流趋势判断电路33才输出数字信号1。
第五与门34将第一电流趋势判断电路33输出的数字信号和第一与门13的输出端NG1-1输出的数字信号进行与运算后，可以滤除第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号。第一RS触发器的置位端S接收第五与门34的输出端NG1-4输出的数字信号，第一RS触发器的复位端R接收第一与门13的输出端NG1-1输出的数字信号，根据第一RS触发器的保持功能，可在置位端S接收到的数字信号为0，复位端R接收到的数字信号为1时，输出端Q跟随上一个输出状态。从而使得电流端I的电流为正弦波的上升部分阶段时，第一RS触发器的输出端Q输出的开关控制信号始终为1。
这样一来，不仅可以滤除第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号，避免因振铃问题导致整流器输出不稳定的问题。还可以仅滤除第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号，不滤除实需高电平信号，不造成功率浪费。
关于第一触发器35的结构，在另一种可能的实施例中，如图7c所示，第一触发器35为第一D触发器。
根据D触发器的原理，在第一D触发器的复位端R接收到的数字信号为1，第一D触发器的时钟端CK作为置位端S接收到的信号的上升沿时刻，第一D触发器的输出端Q输出输入端D接收到的信号(与输入端D相耦接的第五电压端V5为固定高电平信号端，例如输入数字信号1)。在第一D触发器的复位端R接收到的数字信号为0时，无论第一D触发器的时钟端CK接收到的数字信号为1还是0，第一D触发器的输出端Q始终输出数字信号0。在第一D触发器的时钟端CK接收到的数字信号为0，第一D触发器的复位端R接收到的数字信号为1时，第一D触发器的输出端Q跟随上一个输出状态。
基于此，如图7b所示，在第一D触发器的复位端R接收到的数字信号为震荡高电平信号时，第一D触发器的时钟端CK接收到的数字信号为0，第一D触发器的输出端Q跟随上一个输出状态。而上一个输出状态中，第一D触发器的复位端R接收到的数字信号为0，第一D触发器的输出端Q向第一控制端NG1输出数字信号0。因此，在第一D触发器的复位端R接收到的数字信号为震荡高电平信号时，第一D触发器的输出端Q向第一控制端NG1输出数字信号0。
当然，第一触发器35还可以是其他触发器，本申请实施例对此不作限定，上述两种触发器仅为一种示意。如图7a所示，第二上升沿滤波电路40包括第二电流趋势判断电路43、第六与门44以及第二触发器45。
第二电流趋势判断电路43，与电流端I和第六与门44的第一输入端相耦接。第二电流趋势判断电路43用于接收并处理电流端I的信号，在电流端I的信号呈上升趋势的情况下，第二电流趋势判断电路43的输出端NG2-3向第六与门44的第一输入端输入0；在电流端I的信号呈下降趋势的情况下，第二电流趋势判断电路43的输出端NG2-3向第六与门44的第一输入端输入1。
第二电流趋势判断电路43与第一电流趋势判断电路33可连接同一电流端I，即，二者均可连接流经功率接收电路中的线圈L1。
第二电流趋势判断电路43的结构和原理，可以与上述第一电流趋势判断电路33的结构和原理相同，可以参考上述关于第一电流趋势判断电路33的描述，此处不再赘述。
第六与门44的第二输入端与第一与门13的输出端NG1-1相耦接，第六与门44的输出端NG2-4与第二触发器45的置位端相耦接。
第六与门44对第二与门23的输出端NG2-1输出的数字信号和第二电流趋势判断电路43输出的信号进行逻辑运算，并将运算结果输出至第二触发器45的置位端。
如图7b所示，第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号总是出现在线圈L1输出的电流IL1呈上升趋势的阶段。而第二电流趋势判断电路43在电流端I的信号呈上升趋势的情况下，第二电流趋势判断电路43的输出端NG2-3向第六与门44的第一输入端输入数字信号0。
这样一来，第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号出现时，向第六与门44的第二输入端输入数字信号1，而第二电流趋势判断电路43的输出端NG2-3向第六与门44的第一输入端输入数字信号为0。第六与门44经与运算后，第六与门44的输出端NG2-4向第二触发器45的置位端输出数字信号0。从而可以滤除第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号，以实现滤除数字信号在每个脉冲周期的前Bns的上升沿信号。
第二触发器45的复位端与第二与门23的输出端NG2-1相耦接，第二触发器45的输出端与第二控制端NG2相耦接。
也就是说，第二触发器45根据复位端和置位端的信号，生成开关控制信号，并将开关控制信号传输从输出端至第二控制端NG2。
关于第二触发器45的结构，在一种可能的实施例中，如图7c所示，第二触发器45为第二RS触发器。
同理，根据RS触发器的原理，在第二RS触发器的置位端S接收到的数字信号为1，第二RS触发器的复位端R接收到的数字信号也为1时，第二RS触发器的输出端向第二控制端NG2输出数字信号1。在第二RS触发器的置位端S接收到的数字信号为0，第二RS触发器的复位端R接收到的数字信号也为0时，第二RS触发器的输出端向第二控制端NG2输出数字信号0。
在第二RS触发器的置位端S接收到的数字信号为0，第二RS触发器的复位端R接收到的数字信号为1时，第二RS触发器的输出端跟随上一个输出状态。
如图7b所示，在第二RS触发器的复位端R接收到的数字信号为震荡高电平信号时，第二RS触发器的置位端S接收到的数字信号为0，第二RS触发器的输出端跟随 上一个输出状态。而上一个输出状态中，第二RS触发器的置位端S接收到的数字信号为0，第二RS触发器的复位端R接收到的数字信号也为0，第二RS触发器的输出端向第二控制端NG2输出数字信号0。因此，在第二RS触发器的复位端R接收到的数字信号为震荡高电平信号时，第二RS触发器的输出端向第二控制端NG2仍输出数字信号0。
如图7b所示，在第二RS触发器的复位端R接收到的数字信号为实需高电平信号时，第二RS触发器的置位端S接收到的数字信号先为1，此时第二RS触发器的输出端向第二控制端NG2输出数字信号1。随后，第二RS触发器的置位端S接收到的数字信号变为0，此时第二RS触发器的输出端跟随上一个输出状态，第二RS触发器的输出端向第二控制端NG2仍输出数字信号1。
由于若第二RS触发器的复位端R接收到的数字信号为0，即，第二与门23的输出端NG2-1输出的数字信号为0，第六与门44的输出端NG2-4输出的数字信号必然为0，即，第二RS触发器的置位端S接收到的数字信号必然为0。因此，基于本申请实施例提供的整流控制电路，不会出现在第二RS触发器的置位端S接收到的数字信号为1，第二RS触发器的复位端R接收到的数字信号也0的状态。
基于此，如图7b所示，第二RS触发器根据复位端R和置位端S的信号生成的开关控制信号，滤除掉了震荡高电平信号，只保留了实需高电平信号。
同理，第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号出现时，电流端I的电流呈上升趋势。第二与门23的输出端NG2-1输出的数字信号中的实需高电平信号出现时，电流端I的电流呈下降趋势。在第二电流趋势判断电路43、第六与门44以及第二RS触发器的共同作用下，滤除第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号，避免因振铃问题导致整流器输出不稳定的问题。
关于第二触发器35的结构，在另一种可能的实施例中，如图7c所示，第二触发器45为第二D触发器。
根据D触发器的原理，在第二D触发器的复位端R接收到的数字信号为1，第二D触发器的时钟端CK作为置位端S接收到的信号的上升沿时刻，第二D触发器的输出端Q输出输入端D的信号(与输入端D相耦接的第五电压端V5为固定高电平信号端，例如输入数字信号1)。在第二D触发器的复位端R接收到的数字信号为0时，无论第二D触发器的时钟端CK接收到的数字信号为1还是0，第二D触发器的输出端Q始终输出数字信号0。在第二D触发器的时钟端CK接收到的数字信号为0，第二D触发器的复位端R接收到的数字信号为1，第二D触发器的输出端Q跟随上一个输出状态。
基于此，如图7b所示，在第二D触发器的复位端R接收到的数字信号为震荡高电平信号时，第二D触发器的时钟端CK接收到的数字信号为0，第二D触发器的输出端Q跟随上一个输出状态。而上一个输出状态中，第二D触发器的复位端R接收到的数字信号为0，第二D触发器的输出端Q向第二控制端NG2输出数字信号0。因此，在第二D触发器的复位端R接收到的数字信号为震荡高电平信号时，第二D触发器的输出端Q向第二控制端NG2输出数字信号0。
当然，第二触发器45还可以是其他触发器，本申请实施例对此不作限定，上述两 种触发器仅为一种示意。
本申请实施例中，第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号出现时，电流端I的电流呈下降趋势。第一与门13的输出端NG1-1输出的数字信号中的实需高电平信号出现时，电流端I的电流呈上升趋势。在第一电流趋势判断电路33、第五与门34以及第一触发器35的共同作用下，滤除第一与门13的输出端NG1-1输出的数字信号中的震荡高电平信号，避免因振铃问题导致整流器输出不稳定的问题。
同理，第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号出现时，电流端I的电流呈上升趋势。第二与门23的输出端NG2-1输出的数字信号中的实需高电平信号出现时，电流端I的电流呈下降趋势。在第二电流趋势判断电路43、第六与门44以及第二触发器45的共同作用下，滤除第二与门23的输出端NG2-1输出的数字信号中的震荡高电平信号，避免因振铃问题导致整流器输出不稳定的问题。
实施例三
实施例三与实施例二的不同在于，第二上升沿滤波电路40的结构不同。
如图8a所示，第二上升沿滤波电路40包括第六与门44以及第二触发器45。
第一电流趋势判断电路33，还与第六与门44的第一输入端相耦接。第一电流趋势判断电路33还用于在电流端I的信号呈上升趋势的情况下，第一电流趋势判断电路33的输出端NG1-3向第六与门44的第一输入端输入0；在电流端I的信号呈下降趋势的情况下，第一电流趋势判断电路33的输出端NG1-3向第六与门44的第一输入端输入1。
也就是说，如图8b所示，第一电流趋势判断电路33接收并处理电流端I的信号，在电流端I的信号呈上升趋势的情况下，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入1，同时向第六与门44的第一输入端输入0。在电流端I的信号呈下降趋势的情况下，第一电流趋势判断电路33的输出端NG1-3向第五与门34的第一输入端输入0，同时向第六与门44的第一输入端输入1。
第六与门44的第二输入端与第一与门13的输出端NG1-1相耦接，第六与门44的输出端NG2-4与第二触发器45的置位端S相耦接。
第六与门44对第二与门23的输出端NG2-1输出的数字信号和第一电流趋势判断电路33输出的信号进行逻辑运算，滤除数字信号在每个脉冲周期的前Bns的上升沿信号，并将运算结果输出至第二触发器45的置位端S。
第二触发器45的复位端R与第二与门23的输出端NG2-1相耦接，第二触发器45的输出端与第二控制端NG2相耦接。第二触发器45根据复位端R和置位端S的信号，生成开关控制信号，并将开关控制信号传输至第二控制端NG2。
第六与门44和第二触发器45的结构和原理和实施例二中相同，可参考实施例二中的相关描述，此处不再赘述。
第一电流趋势判断电路33接收并处理电流端I的信号，在电流端I的信号呈上升趋势的情况下，向第五与门34的第一输入端输入1，同时向第六与门44的第一输入端输入0。在电流端I的信号呈下降趋势的情况下，向第五与门34的第一输入端输入0，同时向第六与门44的第一输入端输入1。无需再单独设置上述第二电路趋势判断 电路，可简化整流器的结构。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种整流器，其特征在于，包括：
    第一逻辑电路，包括第一比较器、第二比较器以及第一与门；所述第一比较器的正向输入端与第一电压端相耦接，所述第一比较器的反向输入端与第二电压端相耦接；所述第二比较器的正向输入端与第三电压端相耦接，所述第二比较器的反向输入端与第四电压端相耦接；所述第一与门的第一输入端与所述第一比较器的输出端相耦接，所述第一与门的第二输入端与所述第二比较器的输出端相耦接；
    第一上升沿滤波电路，与所述第一与门的输出端和第一控制端相耦接，用于接收所述第一与门的输出端输出的数字信号，并滤除所述数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至所述第一控制端；
    其中，A>0。
  2. 根据权利要求1所述的整流器，其特征在于，所述整流器还包括：
    第二逻辑电路，包括第三比较器、第四比较器以及第二与门；所述第三比较器的正向输入端与所述第四电压端相耦接，所述第三比较器的反向输入端与所述第二电压端相耦接；所述第四比较器的正向输入端与所述第三电压端相耦接，所述第四比较器的反向输入端与第一电压端相耦接；所述第二与门的第一输入端与所述第三比较器的输出端相耦接，所述第二与门的第二输入端与所述第四比较器的输出端相耦接；
    第二上升沿滤波电路，与所述第二与门的输出端和第二控制端相耦接，用于接收所述第二与门的输出端输出的数字信号，并滤除所述数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至所述第二控制端；
    其中，B>0。
  3. 根据权利要求1或2所述的整流器，其特征在于，所述第一上升沿滤波电路包括第一延时电路和第三与门；
    所述第一延时电路与所述第一与门的输出端和所述第三与门的第一输入端相耦接；
    所述第三与门的第二输入端还与所述第一与门的输出端相耦接，所述第三与门的输出端与所述第一控制端相耦接。
  4. 根据权利要求2或3所述的整流器，其特征在于，所述第二上升沿滤波电路包括第二延时电路和第四与门；
    所述第二延时电路与所述第二与门的输出端和所述第四与门的第一输入端相耦接；
    所述第四与门的第二输入端还与所述第二与门的输出端相耦接，所述第四与门的输出端与所述第二控制端相耦接。
  5. 根据权利要求1或2所述的整流器，其特征在于，所述第一上升沿滤波电路包括第一电流趋势判断电路、第五与门以及第一触发器；
    所述第一电流趋势判断电路，与电流端和所述第五与门的第一输入端相耦接；用于接收并处理所述电流端的信号，在所述电流端的信号呈上升趋势的情况下，向所述 第五与门的第一输入端输入1；在所述电流端的信号呈下降趋势的情况下，向所述第五与门的第一输入端输入0；
    所述第五与门的第二输入端与所述第一与门的输出端相耦接，所述第五与门的输出端与所述第一触发器的置位端相耦接；
    所述第一触发器的复位端与所述第一与门的输出端相耦接，所述第一触发器的输出端与所述第一控制端相耦接。
  6. 根据权利要求2或5所述的整流器，其特征在于，所述第二上升沿滤波电路包括第二电流趋势判断电路、第六与门以及第二触发器；
    所述第二电流趋势判断电路，与电流端和所述第六与门的第一输入端相耦接；用于接收并处理所述电流端的信号，在所述电流端的信号呈上升趋势的情况下，向所述第六与门的第一输入端输入0；在所述电流端的信号呈下降趋势的情况下，向所述第六与门的第一输入端输入1；
    所述第六与门的第二输入端与所述第一与门的输出端相耦接，所述第六与门的输出端与所述第二触发器的置位端相耦接；
    所述第二触发器的复位端与所述第二与门的输出端相耦接，所述第二触发器的输出端与所述第二控制端相耦接。
  7. 根据权利要求5所述的整流器，其特征在于，所述整流器还包括：第二逻辑电路和第二上升沿滤波电路；
    所述第二上升沿滤波电路包括第六与门以及第二触发器；
    所述第一电流趋势判断电路，还与所述第六与门的第一输入端相耦接；还用于在所述电流端的信号呈上升趋势的情况下，向所述第六与门的第一输入端输入0；在所述电流端的信号呈下降趋势的情况下，向所述第六与门的第一输入端输入1；
    所述第六与门的第二输入端与所述第一与门的输出端相耦接，所述第六与门的输出端与所述第二触发器的置位端相耦接；
    所述第二触发器的复位端与所述第二与门的输出端相耦接，所述第二触发器的输出端与所述第二控制端相耦接。
  8. 根据权利要求1-7任一项所述的整流器，其特征在于，所述整流器还包括整流电路，所述第一控制端与所述整流电路相耦接。
  9. 根据权利要求8所述的整流器，其特征在于，所述整流器还包括第二上升沿滤波电路；
    所述整流电路包括第一开关、第二开关、第三开关以及第四开关；
    所述第一开关，用于连通所述第一电压端和所述第二电压端，所述第一开关的控制端与所述第一控制端相耦接；
    所述第二开关，用于连通所述第三电压端和所述第四电压端，所述第二开关的控制端与所述第一控制端相耦接；
    所述第三开关，用于连通所述第一电压端和所述第三电压端，所述第三开关的控制端与第二控制端相耦接；
    所述第四开关，用于连通所述第二电压端和所述第四电压端，所述第四开关的控制端与所述第二控制端相耦接。
  10. 一种设备，其特征在于，包括功率接收电路和权利要求1-9任一项所述的整流器；所述功率接收电路与所述整流器的第一电压端和第四电压端相耦接，用于向所述第一电压端和所述第四电压端提供交流信号。
  11. 根据权利要求10所述的设备，其特征在于，所述功率接收电路包括线缆，所述线缆与所述整流器的电流端相耦接。
  12. 一种整流器的驱动方法，其特征在于，整流器包括第一逻辑电路和第一上升沿滤波电路；第一逻辑电路包括第一比较器、第二比较器以及第一与门；
    所述整流器的驱动方法，包括：
    所述第一比较器的正向输入端接收第一电压端的信号，所述第一比较器的反向输入端接收第二电压端的信号，所述第一比较器对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从所述第一比较器的输出端输出；
    所述第二比较器的正向输入端接收第三电压端的信号，所述第二比较器的反向输入端接收第四电压端的信号，所述第二比较器对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从所述第二比较器的输出端输出；
    所述第一与门第一输入端接收所述第一比较器的输出端输出的信号，所述第一与门的第二输入端接收所述第二比较器的输出端输出的信号，所述第一与门对第一输入端和第二输入端接收到的信号进行逻辑运算，并将运算结果从所述第一与门的输出端输出；
    所述第一上升沿滤波电路，接收所述第一与门的输出端输出的数字信号，并滤除所述数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，将所述开关控制信号传输至第一控制端；
    其中，A>0。
  13. 根据权利要求12所述的整流器的驱动方法，其特征在于，整流器还包括第二逻辑电路和第二上升沿滤波电路；第二逻辑电路包括第三比较器、第四比较器以及第二与门；
    所述整流器的驱动方法，还包括：
    所述第三比较器的正向输入端接收所述第四电压端的信号，所述第三比较器的反向输入端接收所述第二电压端的信号，所述第三比较器对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从所述第三比较器的输出端输出；
    所述第四比较器的正向输入端接收所述第三电压端的信号，所述第四比较器的反向输入端接收所述第一电压端的信号，所述第四比较器对正向输入端和反向输入端接收到的信号进行比较运算，并将运算结果从所述第四比较器的输出端输出；
    所述第二与门第一输入端接收所述第三比较器的输出端输出的信号，所述第二与门的第二输入端接收所述第四比较器的输出端输出的信号，所述第二与门对第一输入端和第二输入端接收到的信号进行逻辑运算，并将运算结果从所述第二与门的输出端输出；
    所述第二上升沿滤波电路，接收所述第二与门的输出端输出的数字信号，并滤除所述数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至第二控制端；
    其中，B>0。
  14. 根据权利要求12所述的整流器的驱动方法，其特征在于，所述第一上升沿滤波电路包括第一延时电路和第三与门；
    所述第一上升沿滤波电路，接收所述第一与门的输出端输出的数字信号，并滤除所述数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至第一控制端，包括：
    所述第一延时电路接收所述第一与门的输出端输出的数字信号，经所述第一延时电路的延时作用，对所述数字信号延时ans后，输出延时数字信号；其中，所述延时数字信号与所述数字信号在每个脉冲周期的前Ans中的高电平错时；a≤A；
    所述第三与门对所述第一延时电路输出的所述延时数字信号和所述第一与门的输出端输出的数字信号进行逻辑运算，以滤除所述数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至所述第一控制端。
  15. 根据权利要求12所述的整流器的驱动方法，其特征在于，所述第一上升沿滤波电路包括第一电流趋势判断电路、第五与门以及第一触发器；
    所述第一上升沿滤波电路，接收所述第一与门的输出端输出的数字信号，并滤除所述数字信号在每个脉冲周期的前Ans的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至第一控制端，包括：
    所述第一电流趋势判断电路接收并处理电流端的信号，在所述电流端的信号呈上升趋势的情况下，向所述第五与门的第一输入端输入1；在所述电流端的信号呈下降趋势的情况下，向所述第五与门的第一输入端输入0；
    所述第五与门对所述第一与门的输出端输出的数字信号和所述第一电流趋势判断电路输出的信号进行逻辑运算，滤除所述数字信号在每个脉冲周期的前Ans的上升沿信号，并将运算结果输出至所述第一触发器的置位端；
    所述第一触发器根据复位端和置位端的信号，生成开关控制信号，并将所述开关控制信号传输至所述第一控制端。
  16. 根据权利要求13所述的整流器的驱动方法，其特征在于，所述第二上升沿滤波电路包括第二延时电路和第四与门；
    所述第二上升沿滤波电路，接收所述第二与门的输出端输出的数字信号，并滤除所述数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至第二控制端，包括：
    所述第二延时电路接收所述第二与门的输出端输出的数字信号，经所述第二延时电路的延时作用，对所述数字信号延时bns后，输出延时数字信号；其中，所述延时数字信号与所述数字信号在每个脉冲周期的前Bns中的高电平错时；b≤B；
    所述第四与门对所述第二延时电路输出的所述延时数字信号和所述第二与门的输出端输出的数字信号进行逻辑运算，以滤除所述数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至所述第二控制端。
  17. 根据权利要求13所述的整流器的驱动方法，其特征在于，所述第二上升沿滤波电路包括第二电流趋势判断电路、第六与门以及第二触发器；
    所述第二上升沿滤波电路，接收所述第二与门的输出端输出的数字信号，并滤除 所述数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至第二控制端，包括：
    所述第二电流趋势判断电路接收并处理电流端的信号，在所述电流端的信号呈上升趋势的情况下，向所述第六与门的第一输入端输入0；在所述电流端的信号呈下降趋势的情况下，向所述第六与门的第一输入端输入1；
    所述第六与门对所述第二与门的输出端输出的数字信号和所述第二电流趋势判断电路输出的信号进行逻辑运算，滤除所述数字信号在每个脉冲周期的前Bns的上升沿信号，并将运算结果输出至所述第二触发器的置位端；
    所述第二触发器根据复位端和置位端的信号，生成开关控制信号，并将所述开关控制信号传输至所述第二控制端。
  18. 根据权利要求15所述的整流器的驱动方法，其特征在于，所述整流器还包括第二逻辑电路和第二上升沿滤波电路；第二上升沿滤波电路包括第六与门以及第二触发器；
    所述第二上升沿滤波电路，接收所述第二与门的输出端输出的数字信号，并滤除所述数字信号在每个脉冲周期的前Bns的上升沿信号，生成开关控制信号，并将所述开关控制信号传输至第二控制端，包括：
    所述第一电流趋势判断电路接收并处理电流端的信号，在所述电流端的信号呈上升趋势的情况下，向所述第六与门的第一输入端输入0；在所述电流端的信号呈下降趋势的情况下，向所述第六与门的第一输入端输入1；
    所述第六与门对所述第二与门的输出端输出的数字信号和所述第一电流趋势判断电路输出的信号进行逻辑运算，滤除所述数字信号在每个脉冲周期的前Bns的上升沿信号，并将运算结果输出至所述第二触发器的置位端；
    所述第二触发器根据复位端和置位端的信号，生成开关控制信号，并将所述开关控制信号传输至所述第二控制端。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103973142A (zh) * 2014-06-06 2014-08-06 余丽丽 无线电力传输芯片片内全同步桥式整流器架构以及电路
US20160344302A1 (en) * 2015-05-18 2016-11-24 Rohm Co., Ltd. Synchronous rectifier circuit
CN207135003U (zh) * 2017-07-26 2018-03-23 江西联智集成电路有限公司 有源整流器
CN111355393A (zh) * 2020-05-09 2020-06-30 成都市易冲半导体有限公司 一种无线充电接收端的高度自适应同步整流的控制方法
CN111512534A (zh) * 2017-12-21 2020-08-07 华为技术有限公司 用于无线电力传输接收器的低谐波下变频整流器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760279A (en) * 1986-07-02 1988-07-26 Kabushiki Kaisha Toshiba Noise cancelling circuit
FR2748583B1 (fr) * 1996-05-07 1998-06-26 Asulab Sa Stabilisation d'un circuit electronique de regulation du mouvement mecanique d'une piece d'horlogerie
CN106487235B (zh) * 2016-11-30 2017-11-10 无锡华润矽科微电子有限公司 同步整流时序控制器、无线充电全桥同步整流电路及系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103973142A (zh) * 2014-06-06 2014-08-06 余丽丽 无线电力传输芯片片内全同步桥式整流器架构以及电路
US20160344302A1 (en) * 2015-05-18 2016-11-24 Rohm Co., Ltd. Synchronous rectifier circuit
CN207135003U (zh) * 2017-07-26 2018-03-23 江西联智集成电路有限公司 有源整流器
CN111512534A (zh) * 2017-12-21 2020-08-07 华为技术有限公司 用于无线电力传输接收器的低谐波下变频整流器
CN111355393A (zh) * 2020-05-09 2020-06-30 成都市易冲半导体有限公司 一种无线充电接收端的高度自适应同步整流的控制方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4283856A4 *

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