WO2022226818A1 - 显示基板、显示面板和显示基板制造方法 - Google Patents

显示基板、显示面板和显示基板制造方法 Download PDF

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Publication number
WO2022226818A1
WO2022226818A1 PCT/CN2021/090437 CN2021090437W WO2022226818A1 WO 2022226818 A1 WO2022226818 A1 WO 2022226818A1 CN 2021090437 W CN2021090437 W CN 2021090437W WO 2022226818 A1 WO2022226818 A1 WO 2022226818A1
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Prior art keywords
electrode
light
auxiliary electrode
layer
substrate
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PCT/CN2021/090437
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English (en)
French (fr)
Inventor
徐攀
袁志东
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/754,000 priority Critical patent/US12232399B2/en
Priority to EP21938304.9A priority patent/EP4216295A4/en
Priority to PCT/CN2021/090437 priority patent/WO2022226818A1/zh
Priority to CN202180000946.6A priority patent/CN115623879A/zh
Publication of WO2022226818A1 publication Critical patent/WO2022226818A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80523—Multilayers, e.g. opaque multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a method for manufacturing the display substrate.
  • OLED display technology has gradually been widely used, and has become the most potential display technology to replace Liquid Crystal Display (LCD). Compared with LCD display technology, OLED display technology has a better experience in terms of picture quality, response speed, lightness and so on.
  • OLED display technology is undoubtedly much more complicated than LCD display technology, especially the panel circuit of OLED is complex, and it cannot be unified in order to cope with the emergence of various corresponding technologies in different application scenarios.
  • the voltage rise (IR Rise) of the cathode of a larger size top-emitting OLED must be addressed.
  • an OLED is a current-type device, and a power source is required to emit light to make the pixels self-illuminate, and a power line for supplying power to the light-emitting device needs to occupy a large frame, resulting in poor appearance.
  • embodiments of the present disclosure provide a display substrate, a display panel, and a method for manufacturing the display substrate for reducing the frame size while improving the voltage drop increase of the cathode of a large-sized top-emitting OLED.
  • Embodiments of the present disclosure provide a display substrate, including: a substrate; a plurality of pixel units disposed on the substrate, the plurality of pixel units are arranged on the substrate in an array along a row direction and a column direction, and a plurality of pixel units are arranged on the substrate in an array.
  • the pixel unit includes at least a first pixel unit, the first pixel unit includes a first light-emitting area and a first non-light-emitting area; a first light-emitting element disposed in the first light-emitting area, the first light-emitting element includes a first electrode, a light-emitting layer and a second electrode; a scan drive circuit arranged in the first non-light emitting area; a first auxiliary electrode arranged on the side of the scan drive circuit away from the substrate, the first auxiliary electrode is located in a first partial area in the first non-light emitting area, wherein, The first auxiliary electrodes are arranged in the row direction or the column direction; the scan driving circuit includes a plurality of sub-scanning driving circuits, and the sub-scanning driving circuits are located in the second partial area in the first non-light-emitting area; the first partial area in the first non-light-emitting area and The orthographic projections of the second partial region in the first non-light-
  • the first auxiliary electrode is located on the same layer as the first electrode.
  • the plurality of pixel units further include a second pixel unit, the second pixel unit includes a second light-emitting area and a second non-light-emitting area, and the scan driving circuit is not disposed in the second non-light-emitting area.
  • the above-mentioned display substrate further includes: a second light-emitting element disposed in the second light-emitting region, the second light-emitting element comprising: a third electrode, a light-emitting layer and a fourth electrode; a second auxiliary electrode, a second light-emitting element
  • the auxiliary electrode is located in the first partial area in the second non-light-emitting area, wherein the second auxiliary electrode and the third electrode are located in the same layer, the third electrode and the first electrode are located in the same layer, and the second auxiliary electrode is arranged in parallel with the first auxiliary electrode , the second auxiliary electrode and the fourth electrode are electrically connected.
  • the above-mentioned display substrate further comprises: a source and drain electrode disposed on the side of the layer where the third electrode is located close to the substrate, and the source and drain electrode are located in the second non-light-emitting region; a third auxiliary electrode, a third auxiliary electrode In the second partial region located in the second non-light-emitting region, the extension direction of the third auxiliary electrode is in contact with the orthographic projection of the extension direction of the second auxiliary electrode on the substrate, the source and drain electrodes and the second non-light-emitting region The orthographic projections of the two partial regions on the substrate are separated from each other, the third auxiliary electrode and the source and drain electrodes are arranged on the same layer, and the third auxiliary electrode and the second auxiliary electrode are electrically connected.
  • one second auxiliary electrode corresponds to one or more rows of second pixel units; and/or one third auxiliary electrode corresponds to one or more columns of second pixel units.
  • the above-mentioned display substrate further includes: a first signal line; the first auxiliary electrode includes: a first main body part; There is an overlap between the orthographic projection on the substrate and the orthographic projection of the first signal line on the substrate.
  • the above-mentioned display substrate further includes: a first signal line; the second auxiliary electrode includes: a second main body part; There is an overlap between the orthographic projection on the substrate and the orthographic projection of the first signal line on the substrate.
  • the above-mentioned display substrate further includes a second signal line;
  • the third auxiliary electrode includes: a third main body part; a third narrowed part connected to the third main body part, and the third narrowed part is on the substrate There is an overlap between the orthographic projection of the second signal line on the substrate.
  • the above-mentioned display substrate further includes: a non-display area; and a second electrode bus line disposed in the non-display area, and the second electrode bus line is used for transmitting a reference voltage signal to the second electrode and/or the fourth electrode.
  • the first auxiliary electrode and the second auxiliary electrode are disposed on the same layer as the second electrode bus line, the first auxiliary electrode and the second electrode bus line are connected, and the second auxiliary electrode and the second electrode bus line are connected; or
  • the third auxiliary electrode and the fourth electrode bus line are arranged on the same layer, and the third auxiliary electrode and the fourth electrode bus line are connected.
  • the above-mentioned display substrate further includes: a planarization layer and an insulating layer arranged in a stacked layer, disposed between the second auxiliary electrode and the third auxiliary electrode, the planarization layer includes a first via hole, and the insulating layer includes the second via hole, the orthographic projection of the first via hole and the second via hole on the substrate overlaps; and the first auxiliary electrode is electrically connected to the second auxiliary electrode through the first via hole and the second via hole.
  • the first via and the second via are circular vias, and the diameter of the second via is larger than the diameter of the first via; or the first via and the second via are polygonal vias , the area of the second via is larger than the area of the first via.
  • the above-mentioned display substrate further includes: a pixel definition layer disposed between the second electrode and the first auxiliary electrode, the pixel definition layer includes a third via hole, and the first auxiliary electrode passes through the first via hole and the first auxiliary electrode.
  • the two electrodes are electrically connected.
  • a pixel defining layer is disposed between the fourth electrode and the second auxiliary electrode, the pixel defining layer includes a third via hole; and the second auxiliary electrode is electrically connected to the fourth electrode through the third via hole.
  • the first via hole is a circular via hole
  • the third via hole is a strip-shaped via hole
  • the dimension of the strip-shaped via hole in the row direction is larger than the diameter of the first via hole
  • the orthographic projections of the first via and the third via on the substrate are spaced apart from each other.
  • the orthographic projection of the pixel-defining layer on the substrate covers the first non-emissive area; and/or the orthographic projection of the pixel-defining layer on the substrate covers the second non-emissive area.
  • one row of first auxiliary electrodes corresponds to one or more rows of first pixel units.
  • one sub-scan driving circuit corresponds to one or more columns of first pixel units.
  • the shape of the above-mentioned display substrate includes any one of a square, a rectangle, a polygon and a shape with an arc boundary.
  • a plurality of pixel units are respectively located in different display areas, and each display area has an exclusive sub-scan driving circuit.
  • a display substrate with a heart-shaped border includes a display area with a heart-shaped tip, two symmetrical display areas with a heart-shaped head, and the sub-scan driving circuits are arranged in a column direction.
  • the first electrode includes a multi-layer metal structure, and the cross-section of the multi-layer metal structure is I-shaped.
  • the first electrode includes a stacked indium tin oxide/aluminum/indium tin oxide layer.
  • the first non-light emitting region is an L-type region.
  • the light emitting layer includes an organic light emitting diode
  • the first electrode and the third electrode are anodes of the organic light emitting diode
  • the second electrode and the fourth electrode are cathodes of the organic light emitting diode
  • the scan driving circuit includes a gate driving circuit .
  • the cathode includes a transparent conductive material
  • the anode includes a metal material
  • Embodiments of the present disclosure provide a display panel including the above display substrate.
  • An embodiment of the present disclosure provides a method for manufacturing a display substrate, including: providing a substrate, the substrate includes a plurality of pixel units, the plurality of pixel units are arranged on the substrate in an array along a row direction and a column direction, and a plurality of pixel units are arranged on the substrate in an array.
  • the pixel unit includes at least a first pixel unit, and the first pixel unit includes a first light-emitting area and a first non-light-emitting area; a scan driving circuit is formed in the first non-light-emitting area; a first auxiliary circuit is formed on the side of the scan driving circuit away from the substrate electrode, the first auxiliary electrode is located in the first partial area of the first non-light-emitting area, wherein the first light-emitting area includes a first light-emitting element, the first light-emitting element includes a first electrode, a light-emitting layer and a second electrode, and the first auxiliary electrode Arranged along the row direction or the column direction; the scan driving circuit includes a plurality of sub-scanning driving circuits, the sub-scanning driving circuits are located in the second partial area of the first non-light-emitting area, and the sub-scanning driving circuits are arranged between the substrate and the first electrode;
  • the first auxiliary electrode is located on the same layer as the first electrode.
  • the first light-emitting element is prepared by: evaporating a metal layer stack, the metal layer stack includes an indium tin oxide layer/aluminum layer/indium tin oxide layer; etching, wherein the etching rate of the indium tin oxide layer is lower than the etching rate of the aluminum layer; vapor deposition of the light-emitting layer; The indium tin oxide layers of the substrates are in contact.
  • 1 is a plan view of a display substrate
  • FIG. 2 is a schematic diagram of a pixel unit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a non-light-emitting area compressed in a pixel unit provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a first pixel unit with GIA provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a first auxiliary electrode provided by an embodiment of the present disclosure.
  • Fig. 6 is the cross-sectional structure schematic diagram taken along line A-A in Fig. 5;
  • FIG. 7 is a schematic diagram of a second auxiliary electrode provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a second auxiliary electrode and a third auxiliary electrode provided by an embodiment of the present disclosure
  • Fig. 9 is the cross-sectional structure schematic diagram taken along the line C-C in Fig. 8;
  • Fig. 10 is another cross-sectional structural schematic diagram taken along line C-C in Fig. 8;
  • FIG. 11 is a schematic diagram of a second electrode bus according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a fourth electrode bus provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of simultaneously setting a second electrode bus line and a fourth electrode bus line according to an embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of a GIA of a heart-shaped display substrate provided by an embodiment of the present disclosure
  • FIG. 15 is a schematic cross-sectional view of an organic light emitting diode provided by an embodiment of the present disclosure.
  • 16 is a schematic diagram of a first auxiliary electrode provided by an embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of a third auxiliary electrode provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 19 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • FIG. 20 is a flowchart of a method for manufacturing a light-emitting element provided by an embodiment of the present disclosure.
  • FIG. 21 is a block diagram of a display device provided by an embodiment of the present disclosure.
  • the expression "the same layer” refers to the formation of a film layer for forming a specific pattern using the same film forming process, and then using the same mask to pattern the film layer through a patterning process.
  • layer structure Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or sections located on the "same layer” are composed of the same material and formed by the same patterning process, typically, multiple elements, components, structures and/or sections located on the "same layer” or parts with approximately the same thickness.
  • OLED display technology has gradually been widely used, and has become one of the most potential display technologies to replace LCD display. Compared with LCD display, OLED display technology has a better experience, such as advantages in picture quality, response speed, lightness and so on.
  • the preparation process of OLED is much more complicated than that of LCD, especially the panel circuit of OLED is complicated.
  • the various corresponding OLED technologies that appear for different application scenarios cannot be unified. For example, the IR Rise of the cathode of a larger size top-emitting OLED must be addressed.
  • OLED is a current-type light-emitting device, which requires a power supply to make the pixels emit light by themselves, and the design of the power supply line often needs to occupy a large frame area, resulting in poor appearance.
  • the embodiments of the present disclosure provide a technical solution for realizing a narrower frame based on the GIA technology, and solving the problem of poor display effect caused by a large cathode IR Rise.
  • GIA puts the gate drive circuit in the display area, and realizes the narrowing of the left and right borders of the display screen by not occupying the border.
  • GIA design will compress a certain pixel space (row direction and column direction) for setting the GIA circuit.
  • the GIA circuit does not use the layers after the source and drain layers, for example, the pixel definition layer (PLN), the anode (Anode), and the planarization layer (PDL).
  • PPN pixel definition layer
  • Anode anode
  • PDL planarization layer
  • the entire display area can be divided into two types of pixel units, one is a pixel unit provided with a GIA circuit. The other type is a pixel unit without a GIA circuit.
  • FIG. 1 is a plan view of a display substrate.
  • the display substrate 10 may be an array substrate for an OLED display panel.
  • the above-mentioned display substrate 10 may include a display area (eg, the area where a plurality of pixel units are located), and a non-display area (eg, the area where the cathode bus 200 is located).
  • the display substrate 10 in FIG. 1 may further include a driving circuit 31 and the like located in the non-display area.
  • the driving circuit 31 may be located on at least one side of the display area. In the embodiment shown in FIG. 1 , the driving circuit 31 is located on the lower side of the display area.
  • the above-mentioned "lower side" may be the lower side of the display panel (screen) viewed by human eyes during display.
  • the driving circuit 31 can be used to drive each pixel in the display substrate 10 to display.
  • the above-described driving circuit 31 may include a data driving circuit.
  • the data driving circuit is used to sequentially latch the input data according to the timing of the clock signal, convert the latched data into analog signals, and then input the data to each data line of the display substrate 10 .
  • the display substrate 10 may further include a gate driving circuit, which is usually implemented by a shift register, and the shift register converts the clock signal into an on/off voltage, which are respectively output to each gate line of the display substrate 10 .
  • FIG. 1 shows that the driving circuit 31 is located at the lower side of the display area, the embodiments of the present disclosure are not limited thereto, and the driving circuit 31 may be located at any suitable position in the non-display area.
  • a gate driver circuit (Gate Driver Integrate Array, GIA for short) that uses an active array region may also be provided in the display area.
  • the display area may include a GIA display area (W/O GIA) and a non-GIA display area (W/.GIA).
  • the GIA display area may include a plurality of first pixel units 12 provided with GIAs.
  • the non-GIA display area may include a plurality of second pixel units 11 without GIA.
  • the gate driving circuit 20 is directly disposed in the first display unit 12 on the array substrate, instead of an external driving chip.
  • the gate driving circuit 20 of each column can be used as a first-stage shift register, and each stage of the shift register is connected to a gate line, and the turn-on voltages are output in turn through the shift registers of each stage, so as to realize the column-by-column or row-by-row scanning of the pixels.
  • each stage of the shift register may also be connected to multiple gate lines. In this way, it can adapt to the development trend of high resolution and narrow borders of display substrates.
  • each pixel unit may include a light-emitting area 100 and a non-light-emitting area.
  • the light emitting area 100 may include a plurality of pixels, for example, a pixel unit may include red pixels, blue pixels and green pixels.
  • Each pixel is fan-out to the driving circuit 31 through signal lines, respectively, so as to supply the driving signal to each pixel.
  • the signal lines include, but are not limited to, scan lines, data lines, ELVDD power lines, and ELVSS power lines, etc., so as to provide various signals such as control signals, data signals, and power supply voltages for the pixel driving circuit in each sub-pixel.
  • Each pixel may include an anode, a light-emitting element and a cathode, respectively, and the cathode may be a transparent conductive electrode covering at least part of the display substrate 10 .
  • the electrical connection between the cathode and the cathode bus 200 can be realized, and the cathode can be connected to the cathode bus 200 through the cathode connection hole (VSS Connect Hole Integrate Array) 210 in the active array area. Since the cathode bus 200 needs to be electrically connected to the cathode through the cathode connection hole 210, the non-display area (eg, frame) needs to occupy a larger frame.
  • an auxiliary cathode may be fabricated in the anode (Anode) layer of the non-light-emitting area extending along the row direction, The auxiliary cathode is connected to the cathode through the opening of the pixel defining layer (PDL).
  • PDL pixel defining layer
  • an auxiliary cathode can also be fabricated in the area of the anode (Anode) layer extending in the row direction of the non-light-emitting area, and then the auxiliary cathode can be connected to the cathode through the pixel defining layer (PDL) opening. stand up.
  • An auxiliary cathode is formed in the metal layer where the source and drain electrodes of the non-light-emitting region extending in the column direction are located, and a via hole is designed at the overlap with the auxiliary electrode in the row direction extending region to realize the connection with the auxiliary cathode in the row direction.
  • both the non-GIA pixel unit and the GIA pixel unit have at least one auxiliary cathode (for example, disposed in the Anode layer and located in the row extension direction of the non-light-emitting area) and the cathode connect.
  • the pixel unit without GIA is also provided with an auxiliary cathode extending along the column direction, which is provided in the layer where the source and drain are located. All auxiliary cathode lines extending in the row direction and all auxiliary cathode lines extending in the column direction in the display area are connected through via holes.
  • the cathode bus located outside the display area can be connected to the auxiliary cathode extending along the column direction.
  • the peripheral cathode bus does not need to be connected to the cathode through the connection hole. Compared with the traditional design of increasing the contact hole with the cathode in the cathode bus, some borders can be reduced.
  • the display substrate will be exemplarily described below with reference to FIGS. 2 to 17 .
  • the display substrate 10 may include: a substrate, a pixel unit, a first light-emitting element, a scan driving circuit, and a first auxiliary electrode 30 .
  • a plurality of pixel units are arranged on the substrate, and the plurality of pixel units are arranged in an array along the row direction and the column direction on the substrate, and the plurality of pixel units at least include a first pixel unit 12, and the first pixel unit 12 includes The first light-emitting area 121 and the first non-light-emitting area.
  • the substrate can be prepared from various transparent materials, such as glass substrates, organic transparent substrates, and the like.
  • the first light-emitting element is disposed in the first light-emitting region 121, and the first light-emitting element includes a first electrode 1211 (eg, an anode), a light-emitting layer 141 and a second electrode (eg, a cathode).
  • the light-emitting layer 141 may be an organic light-emitting layer or an inorganic light-emitting layer. The light-emitting layer 141 emits light after being injected with current.
  • the scan driving circuit is arranged in the first non-light-emitting area.
  • the scan driving circuit may include a plurality of thin film transistors.
  • the first auxiliary electrode 30 is disposed on a side of the scan driving circuit away from the substrate, and the first auxiliary electrode 30 is located in a first partial area of the first non-light-emitting area.
  • the first auxiliary electrodes 30 are arranged in a row direction or a column direction.
  • the scan driving circuit includes a plurality of sub-scanning driving circuits 20, and the sub-scanning driving circuits are located in the second partial area of the first non-light-emitting area.
  • the orthographic projections of the first partial region in the first non-light-emitting region and the second partial region in the first non-light-emitting region on the substrate overlap, and the first auxiliary electrode 30 and the second electrode are electrically connected.
  • the first auxiliary electrode 30 and the first electrode 1211 are located in the same layer.
  • FIG. 2 is a schematic diagram of a pixel unit according to an embodiment of the present disclosure.
  • the pixel unit may include a light-emitting area 111 and a non-light-emitting area 112 .
  • a plurality of sub-pixels may be included in the light-emitting region 111 .
  • the light emitting area 111 may include a red sub-pixel 1112 , a green sub-pixel 1113 and a blue sub-pixel 1114 .
  • the pixel unit may emit yellow light.
  • Each of the red sub-pixel 1112, the green sub-pixel 1113 and the blue sub-pixel 1114 may respectively have multiple levels of luminous intensities to mix light of multiple colors.
  • Each sub-pixel may have its own anode 1111, light emitting element and cathode.
  • each sub-pixel may correspond to an anode, and a plurality of sub-pixels may share a cathode.
  • the light-emitting elements of each sub-pixel may emit light of the same color, or may emit light of different colors respectively.
  • the light-emitting element of the red sub-pixel 1112 emits red light
  • the light-emitting element of the green sub-pixel 1113 emits green light
  • the light-emitting element of the blue sub-pixel 1114 emits blue light.
  • the light-emitting elements of the red sub-pixel 1112, the green sub-pixel 1113, and the blue sub-pixel 1114 all emit white light, and then the white light emitted by the respective light-emitting elements is filtered through the red color film, the green color film, and the blue color film to obtain red color. light, green light and blue light.
  • the shape of the orthographic projection of the sub-pixel on the substrate may be a rectangle with rounded corners, but the embodiments of the present disclosure are not limited to this.
  • the shape of the orthographic projection of the sub-pixel on the substrate may be For rectangles, hexagons, pentagons, squares, circles and other shapes.
  • FIG. 3 is a schematic diagram of a non-light-emitting area compressed in a pixel unit according to an embodiment of the present disclosure.
  • each sub-pixel in the pixel unit may be changed so that there is a non-light-emitting area 112 in the pixel unit.
  • circuits such as driving circuits, auxiliary circuits, etc., can be provided in the non-light-emitting area 112 .
  • the provided circuit may occupy all the non-light-emitting areas 112 or occupy part of the non-light-emitting areas 112 .
  • the non-light emitting region 112 is an L-type region.
  • the non-light-emitting area 112 may also be an I-shaped area, a concave-shaped area, a crescent-shaped area, a ⁇ -shaped area, etc., which are not limited herein.
  • FIG. 4 is a schematic diagram of a first pixel unit with GIA according to an embodiment of the present disclosure.
  • the sub-scanning driving circuits 20 may be distributed in the entire non-light-emitting area.
  • the sub-scan driving circuit 20 may be a gate driving circuit.
  • the gate driving circuit is usually implemented by a shift register, and the shift register converts the clock signal into an on/off voltage, which is respectively output to each gate line of the display substrate 10 .
  • the first pixel unit 12 may include: a first light-emitting area 121 and a first non-light-emitting area.
  • the first light emitting area 121 may include a plurality of sub-pixels.
  • the first light emitting area 121 may include a red sub-pixel 1212 , a green sub-pixel 1213 and a blue sub-pixel 1214 .
  • Each sub-pixel may have its own anode 1211, light emitting element and cathode.
  • each sub-pixel may correspond to an anode, and multiple sub-pixels may share a cathode.
  • FIG. 5 is a schematic diagram of a first auxiliary electrode provided by an embodiment of the present disclosure.
  • the first auxiliary electrode 30 is located in a first partial region of the first non-light-emitting region, and the first partial region may be a region extending in the row direction in the first non-light-emitting region.
  • the first auxiliary electrode 30 may be electrically connected to the cathode located on the upper layer thereof through a via hole.
  • the material of the first auxiliary electrode 30 may be the same as that of the first electrode 1211 .
  • the first electrode 1211 may be a reflective anode, eg, it may be formed of a metal material.
  • the metal material may include alloys such as magnesium aluminum alloy (MgAl) and lithium aluminum alloy (LiAl), or single metals such as magnesium, aluminum, and lithium.
  • the first electrode 1211 may be a single-layer metal structure, such as a single-layer silver (Ag) metal electrode.
  • the first electrode 1211 may be a multi-layer metal electrode, such as a stack of indium tin oxide (ITO)/silver (Ag)/indium tin oxide (ITO), a stack of titanium (Ti)/silver (Al)/titanium (Ti) layer etc.
  • the cathode is a high-impedance transparent cathode, and its voltage rise (VSS IR Rise) is relatively large, that is, the cathode voltage value between the near end and the far end of the energy input (Power In) is relatively large.
  • a low-resistance material is provided in parallel with the transparent electrode, thereby reducing the impedance of the cathode current path, that is, increasing the auxiliary cathode.
  • the blank area of the pixel area without the GIA circuit can also be kept blank when the auxiliary cathode is not provided.
  • some dummy patterns are designed.
  • the light emitting layer 141 includes an organic light emitting diode
  • the first electrode 1211 and the third electrode 1111 are anodes of the organic light emitting diode
  • the second electrode and the fourth electrode are cathodes of the organic light emitting diode.
  • the scan driver circuit includes a gate driver circuit.
  • the light emitting layer 141 may be a multilayer structure, for example, it may include a multilayer structure formed by a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer.
  • the second electrode may directly cover the entire display substrate 10, for example, the second electrode may be prepared by means of evaporation, sputtering, or the like.
  • the second electrode may be a transparent electrode so that the light emitted by the OLED can be emitted from the top of the display substrate 10 without being totally absorbed or totally reflected by the second electrode.
  • the second electrode includes, but is not limited to, at least one of the following: ITO, indium zinc tin oxide ITZO, indium zinc oxide (IZO), nano-silver layer, and the like.
  • the first auxiliary electrode 30 and the second electrode may be separated by a dielectric layer.
  • the electrical connection between the first auxiliary electrode 30 and the second electrode can be made by opening holes in the dielectric layer.
  • the dielectric layer includes, but is not limited to, at least one of the following: a pixel definition layer, an insulating layer, a planarization layer, and the like.
  • the OLED device can be driven by active or passive.
  • the passively driven OLED array substrate is composed of a cathode and an anode, the intersection of the anode and the cathode can emit light, and the driving circuit can be externally mounted by connection methods such as a tape carrier package or a glass carrier chip.
  • the active driving OLED array substrate can be equipped with a pixel driving circuit for each pixel, and the pixel driving circuit can include a thin film transistor with switching function (ie switching transistor), a thin film transistor with driving function (ie driving transistor) and a charge storage capacitor ,
  • the pixel driving circuit may also include other types of thin film transistors with compensation functions. It should be understood that, in the embodiments of the present disclosure, the above-mentioned display panel may be equipped with various types of known pixel driving circuits, which will not be repeated here.
  • FIG. 6 is a schematic cross-sectional structure diagram taken along the line A-A in FIG. 5 .
  • the one or more dielectric layers or the like between the first auxiliary electrode 30 and the second electrode make the first auxiliary electrode 30 and the second electrode located in different layers between the first auxiliary electrode 30 and the second electrode. electrical insulation.
  • the openings 31 may be formed on the dielectric layer by processes such as photolithography, etching, etc., so as to realize the electrical connection between the first auxiliary electrode 30 and the second electrode located in different layers. For example, after the first auxiliary electrode 30 is formed, a dielectric layer is formed, then an opening 31 is formed on the dielectric layer through a process such as photolithography, etching, etc.
  • first auxiliary electrode 30 to expose the first auxiliary electrode 30, and then a second electrode is formed so as to be located in the opening There is an electrical connection between the second electrode at the first auxiliary electrode 30 and the exposed first auxiliary electrode 30 .
  • first auxiliary electrode 30 there may be other structures under the first auxiliary electrode 30 , such as GIA circuit, source-drain, data line, and the like.
  • the plurality of pixel units further include a second pixel unit 11, and the second pixel unit 11 includes a second light-emitting area 121 and a second non-light-emitting area, and no scan driving circuit is disposed in the second non-light-emitting area.
  • the second pixel unit 11 may refer to a plurality of pixel units included in the W/O GIA area in FIG. 1 , and no scan driving circuit is provided in these pixel units.
  • the above-mentioned display substrate 10 may further include: a second light-emitting element and a second auxiliary electrode 40 .
  • the second light-emitting element is disposed in the second light-emitting region, and the second light-emitting element includes: a third electrode 1111, a light-emitting layer 141 and a fourth electrode.
  • the third electrode 1111 may be in the same layer as the first electrode 1211 .
  • the arrangement of the first electrodes 1211 in the first light-emitting element may be the same as the arrangement of the third electrodes 1111 in the second light-emitting element.
  • the material of the third electrode 1111 may be the same as that of the first electrode 1211 .
  • the third electrode 1111 can be fabricated in the same process as the first electrode 1211 .
  • the second auxiliary electrode 40 may be located in the first partial region in the second non-light emitting region.
  • the first partial region in the second non-light-emitting region may be a region extending in the row direction in the second non-light-emitting region.
  • the second auxiliary electrode 40 and the third electrode 1111 may be located in the same layer, the third electrode 1111 and the first electrode 1211 may be located in the same layer, and the second auxiliary electrode 40 may be arranged in parallel with the first auxiliary electrode 30, such as the second auxiliary electrode 40 may be arranged in the row direction, and the second auxiliary electrode 40 and the fourth electrode are electrically connected.
  • the first auxiliary electrode 30, the second auxiliary electrode 40, the first electrode 1211 and the third electrode 1111 may be formed through the same thin film process, photolithography process and etching process.
  • FIG. 7 is a schematic diagram of a second auxiliary electrode provided by an embodiment of the present disclosure.
  • the schematic cross-sectional structure along the B-B direction in FIG. 7 can be referred to as shown in FIG. 6 .
  • the first auxiliary electrode 30 is replaced with the second auxiliary electrode 40
  • the via hole 31 is replaced with a via hole 41 , which will not be described in detail here.
  • other structures such as a dummy pattern, a source-drain, a data line, etc., may also be provided under the second auxiliary electrode 40 .
  • the second pixel unit 11 shown in FIG. 7 may further include a second light-emitting region 111 and a second non-light-emitting region.
  • the second light emitting area 111 includes a plurality of sub-pixels, such as a red sub-pixel 1112 , a green sub-pixel 1113 and a blue sub-pixel 1114 .
  • each sub-pixel has its own anode 1111, a light-emitting element and a common cathode.
  • the anode of each sub-pixel in the first pixel unit 12 and the anode of each sub-pixel in the second pixel unit 11 can be fabricated in the same process.
  • the above-mentioned display substrate 10 may further include: source and drain electrodes and a third auxiliary electrode 50 .
  • the source and drain are arranged on the side of the layer where the third electrode 1111 is located close to the substrate, and the source and drain are located in the second non-light-emitting region.
  • the metal layer where the source and drain are located may also be referred to as the SD layer for short, and the SD layer may be used to fabricate the source and drain as well as the third auxiliary electrode 50 and the data line and the like.
  • the third auxiliary electrode 50 is located in the second partial region in the second non-light emitting region.
  • FIG. 8 is a schematic diagram of a second auxiliary electrode and a third auxiliary electrode according to an embodiment of the present disclosure.
  • FIG. 8 further includes a third auxiliary electrode 50 and a via hole h for realizing electrical connection between the second auxiliary electrode 40 and the third auxiliary electrode 50 .
  • FIG. 9 is a schematic cross-sectional structure diagram taken along the line C-C in FIG. 8 .
  • FIG. 10 is another schematic cross-sectional structure diagram taken along the line C-C in FIG. 8 .
  • the extension direction of the third auxiliary electrode 50 is in contact with the orthographic projection of the extension direction of the second auxiliary electrode 40 on the substrate, and the source and drain electrodes and the second part of the second non-light-emitting region are on the substrate.
  • the orthographic projections are isolated from each other, and the third auxiliary electrode 50 and the source and drain electrodes are disposed on the same layer to avoid short circuit between the source and drain electrodes and the third auxiliary electrode 50 .
  • the source and drain may be located in the second light emitting region.
  • the third auxiliary electrode 50 and the second auxiliary electrode 40 are electrically connected.
  • the second auxiliary electrode 40 and the fourth electrode are electrically connected, so that the third auxiliary electrode 50 and the fourth electrode are electrically connected.
  • the second auxiliary electrode 40 and the third auxiliary electrode 50 may be connected through the second via hole h2 and the third via hole h3 .
  • the above-mentioned display substrate 10 may further include: a planarization layer 60 and an insulating layer 70 .
  • the planarization layer 60 and the insulating layer 70 are stacked and disposed together between the second auxiliary electrode 40 and the third auxiliary electrode 50, the planarization layer 60 includes a first via hole h1, and the insulating layer 70 includes a second via hole h1.
  • the hole h2 the orthographic projection of the first via hole h1 and the second via hole h2 on the substrate overlap.
  • the first auxiliary electrode 30 is electrically connected to the second auxiliary electrode 40 through the first via hole h1 and the second via hole h2.
  • the first via hole h1 and the second via hole h2 are polygonal via holes, and the diameter of the second via hole h2 is larger than the diameter of the first via hole h1 .
  • the first via hole h1 and the second via hole h2 are polygonal via holes, and the area of the second via hole h2 is larger than that of the first via hole h1 . This helps to improve the process window. Even if there is a certain error or deviation in the alignment, the contact area between the second auxiliary electrode 40 and the third auxiliary electrode 50 can be made not less than the area of the first via hole h1 as much as possible, so that The contact resistance between the second auxiliary electrode 40 and the third auxiliary electrode 50 is sufficiently small.
  • the above-mentioned display substrate 10 may further include: a pixel defining layer 80 .
  • the anode of the first light emitting element and/or the second light emitting element is at least partially exposed by the opening of the pixel defining layer 80 .
  • the orthographic projection of the pixel defining layer 80 on the substrate covers the first non-emitting area.
  • the orthographic projection of the pixel defining layer 80 on the substrate covers the second non-emitting area.
  • the pixel defining layer 80 is disposed between the second electrode and the first auxiliary electrode 30, the pixel defining layer 80 includes a third via hole h3, and the first auxiliary electrode 30 is electrically connected to the second electrode through the first via hole h1.
  • the pixel defining layer 80 is disposed between the fourth electrode 1010 and the second auxiliary electrode 40, the pixel defining layer 80 includes a third via h3, and the second auxiliary electrode 40 is electrically connected to the fourth electrode through the third via h3 .
  • the display substrate 10 further includes a pixel defining layer 80 and a fourth electrode 1010 , and the fourth electrode covers the pixel defining layer 80 .
  • the fourth electrode 1010 is electrically connected to the second auxiliary electrode 40 through the first via hole h1.
  • the fourth electrode may be formed by a process such as evaporation or sputtering.
  • the first via hole h1 is a polygonal via hole
  • the third via hole h3 is a strip-shaped via hole
  • the dimension of the strip-shaped via hole along the row direction is larger than the diameter of the first via hole h1 .
  • the orthographic projections of the first via hole h1 and the third via hole h3 on the substrate are spaced apart from each other. This avoids the formation of via holes with an excessively deep depth on the display substrate 10, resulting in a thin cathode on the sidewalls of the via holes. On the one hand, it is easy to increase the resistance of the cathode coming out of the side wall of the via hole, and on the other hand, a breakpoint is easy to occur, resulting in failure or poor aging performance. By arranging the first via hole h1 and the third via hole h3 at different positions, the depth of a single via hole is effectively reduced, and reliability and aging performance are improved without increasing the resistance of the cathode.
  • the first auxiliary electrode 30 is located in the non-light-emitting region, and is disposed in the same layer as the first electrode 1211 and isolated from each other. In this way, when the first electrode 1211 is fabricated, the first auxiliary electrode 30 can be fabricated at the same time, and there is no need to add a new film layer.
  • the second auxiliary electrode 40 is located in the non-light-emitting area, and is disposed in the same layer as the third electrode 1111 and isolated from each other, so that the first auxiliary electrode 30 can be simultaneously fabricated when the third electrode 1111 is fabricated, and no additional film layer is required.
  • the third auxiliary electrode 50 is located in the non-light-emitting region, and is disposed in the same layer as the second electrode and isolated from each other, so that the third auxiliary electrode 50 can be simultaneously fabricated when the source and drain electrodes are fabricated, and no additional film layer is needed.
  • the electrical connection between the transparent cathode, the first auxiliary electrode 30 , the second auxiliary electrode 40 and the third auxiliary electrode 50 can further reduce the impedance of the transparent cathode, thereby reducing the voltage drop more effectively, thereby improving the display effect.
  • one second auxiliary electrode 40 corresponds to one or more rows of second pixel units 11
  • one third auxiliary electrode 50 corresponds to one column or column row of second pixel units 11 .
  • auxiliary cathode extending in the column direction of the layer where the source and drain are located, or the auxiliary cathode extending in the row direction and located in the anode Anode layer
  • its design density can be 1:1 or 1:N with the pixel, that is, multiple rows or multiple Column pixels are designed with an auxiliary cathode.
  • N is a positive integer greater than 1.
  • one row of second pixel units 11 exclusively shares one second auxiliary electrode 40 arranged along the row direction, or, multiple rows of second pixel units 11 collectively correspond to one second auxiliary electrode 40 arranged along the row direction.
  • the arrangement of the second pixel unit 11 and the third auxiliary electrode 50 is similar to that of the second pixel unit 11 and the second auxiliary electrode 40 .
  • one row of the first auxiliary electrodes 30 corresponds to one or more rows of the first pixel units 12 .
  • a sub-scan driving circuit may correspond to a row of pixel units or a column of pixel units.
  • a signal output by a sub-scan driving circuit may be used as a scan signal of a row of pixels or a column of pixel units corresponding to the sub-scan driving circuit.
  • two-row driving or four-row driving can be adopted, that is, the output signal of one sub-scanning driving circuit can be used to drive two or four rows of pixels.
  • the distances between the plurality of first auxiliary electrodes 30 , the distances between the plurality of second auxiliary electrodes 40 and the distances between the plurality of third auxiliary electrodes 50 can be determined according to the conductivity of the cathode and each auxiliary electrode. The electrical conductivity and so on are determined. For example, if the width or thickness of the auxiliary electrode is large, resulting in excellent electrical conductivity of the auxiliary electrode, and the electrical conductivity of the cathode itself is also good, the distance between the plurality of first auxiliary electrodes 30, the distance between the plurality of second auxiliary electrodes The distances between 40 and the distances between the plurality of third auxiliary electrodes 50 are set to be larger to reduce the influence of signal crosstalk. On the contrary, the distances between the plurality of first auxiliary electrodes 30, the distances between the plurality of second auxiliary electrodes 40, and the distances between the plurality of third auxiliary electrodes 50 can be set smaller to reduce the cathode resistance.
  • the area of the display area is relatively large, and it may not be necessary to provide GIA circuits in all GIA pixel units, but only some GIA pixel units are provided with GIA circuits. For example, every three columns of pixel units share one sub-GIA circuit. Specifically, one sub-scanning driving circuit arranged along the column direction corresponds to one or more columns of the first pixel units 12 .
  • a cathode bus can be added outside the display area, and after digging holes in the cathode bus, the cathode bus can be connected to the cathode, so that the cathode bus can be powered to supply voltage to the cathode of the light-emitting element.
  • the data line (Data Line) drawn from the display area needs to bypass the cathode hole and extend the cathode bus line, and then perform the fan-out (Fan-Out) wiring.
  • the embodiments of the present disclosure provide a solution for supplying power to the cathode without the need for a cathode connection hole, so as to further reduce the frame size. Specifically, after the auxiliary cathode is drawn out from the display area, the Fan-Out wiring is directly performed, and the amount of reducing the frame is about the width of the cathode bus line.
  • the above-mentioned display substrate 10 may further include: a non-display area and a second electrode bus line 91 disposed in the non-display area.
  • the second electrode bus 91 is used for transmitting a reference voltage signal to the second electrode.
  • the above-mentioned display substrate 10 may further include: a non-display area and a fourth electrode bus 92 disposed in the non-display area, and the fourth electrode bus 92 is used for transmitting a reference voltage signal to the fourth electrode.
  • the first auxiliary electrode 30 and the second auxiliary electrode 40 and the second electrode bus line 91 are disposed on the same layer, the first auxiliary electrode 30 and the second electrode bus line 91 are connected, and the second auxiliary electrode 30 and the second electrode bus line 91 are connected.
  • the auxiliary electrode 40 is connected to the second electrode bus line 91 .
  • FIG. 11 is a schematic diagram of a second electrode bus line provided by an embodiment of the present disclosure.
  • the second electrode bus lines 91 can be arranged in the non-display area on one side of the display substrate 10 . Since the second electrode bus lines 91 and the second auxiliary electrodes 40 are located in the same layer, they can be patterned by thin films. The connected second electrode bus 91 and the second auxiliary electrode 40 are manufactured in the same way, and there is no need to connect the second electrode bus 91 and the second auxiliary electrode 40 through openings, which not only simplifies the process, but also does not need to reserve the area required for openings, effectively Reduce the occupation of the non-display area of the border and reduce the width of the border.
  • FIG. 12 is a schematic diagram of a fourth electrode bus according to an embodiment of the present disclosure.
  • the third auxiliary electrode 50 and the fourth electrode bus line 92 are disposed on the same layer, and the third auxiliary electrode 50 and the fourth electrode bus line 92 are connected.
  • the fourth electrode bus line 92 can be disposed in the non-display area on one side of the display substrate 10, such as at the bottom or the top of the display substrate 10. Since the fourth electrode bus line 92 and the third auxiliary electrode 50 are located in the same layer, So that the connected fourth electrode bus 92 and the third auxiliary electrode 50 can be manufactured by means of thin film patterning, and it is not necessary to connect the fourth electrode bus 92 and the third auxiliary electrode 50 through openings, which not only simplifies the process, but also does not need to reserve openings. The area required for the hole can effectively reduce the occupation of the non-display area of the frame and reduce the width of the frame. It should be noted that the third auxiliary cathode 50 may not be provided in the pixel unit provided with the GIA.
  • the bus blank area is placed on the SD layer (the layer where the source and drain are located) metal lines of the same layer as the data line (Data Line), and connected to the cathode bus outside the display area. (VSS Bus Line).
  • the metal line of the Anode layer is placed in the GIA area in the row direction, and is connected with the auxiliary cathode via located in the SD layer of the bus, so as to realize the auxiliary cathode mesh connection structure .
  • the way of opening the PDL on the auxiliary cathode of the Anode layer in the row direction makes the auxiliary cathode of the Anode layer overlap with the transparent cathode.
  • the above solution not only achieves the purpose of supplying voltage to the cathode of the pixel, but also arranges the auxiliary cathode in the existing space, which can effectively reduce the VSS IR Rise on the basis of realizing a narrow frame.
  • the first auxiliary electrode 30 and the third auxiliary electrode 50 form a mesh structure
  • the second auxiliary electrode 40 and the third auxiliary electrode 50 form a mesh structure, which can effectively reduce the voltage drop of the transparent cathode, and at the same time greatly reduce the voltage drop of the transparent cathode.
  • the problem of crosstalk (Cross Talk) is alleviated, thereby significantly improving the display effect and improving the display effect of the display substrate.
  • the display substrate 10 provided by the embodiment of the present disclosure can be provided with the first auxiliary electrode 30 , the second auxiliary electrode 40 and the third auxiliary electrode 50 without adding a new film layer, which can further reduce the impedance of the transparent cathode, thereby reducing the resistance of the transparent cathode more effectively. voltage drop, which further improves the display effect.
  • the embodiment of the present disclosure adopts the wire layers in the backplane process, and no new process layers are added, the complexity of the manufacturing process is not increased, and the production efficiency is improved.
  • the second electrode bus line 91 and the fourth electrode bus line 92 may also be provided at the same time.
  • FIG. 13 is a schematic diagram of simultaneously disposing a second electrode bus line and a fourth electrode bus line according to an embodiment of the present disclosure.
  • the second electrode bus lines 91 may be disposed in the non-display area on the left side of the display substrate 10
  • the fourth electrode bus lines 92 may be disposed in the non-display area at the bottom of the display substrate 10 .
  • the second electrode bus line 91 , the first auxiliary electrode 30 and the second auxiliary electrode 40 are formed by a patterning process for the layers where the first electrode 1211 and the third electrode 1111 are located.
  • the fourth electrode bus line 92 and the third auxiliary electrode 50 are formed by one patterning process for the layer where the source and drain electrodes are located.
  • the third auxiliary electrode 50 may be respectively connected with the first auxiliary electrode 30 and the second auxiliary electrode 40 through via holes to further reduce the cathode resistance. Alternatively, the ability of the auxiliary electrode to reduce the cathode resistance already meets the design requirements, and the third auxiliary electrode 50 is isolated from the first auxiliary electrode 30 and the second auxiliary electrode 40 respectively.
  • the display substrate 10 provided by the embodiment of the present disclosure is not only applicable to a rectangular display substrate, but also applicable to a special-shaped screen scene.
  • the shape of the above-mentioned display substrate 10 includes any one of a square, a rectangle, a polygon and a shape with an arc boundary.
  • a plurality of pixel units are located in different display areas, and each display area has an exclusive sub-scanning driving circuit.
  • FIG. 14 is a schematic diagram of a GIA of a heart-shaped display substrate according to an embodiment of the present disclosure.
  • the heart-shaped display substrate can be divided into three blocks, a heart-shaped tip region and a heart-shaped head region with a mirror image distribution.
  • Each area has its own sub-scanning driving circuit 20, respectively.
  • a data driving circuit and the like may be arranged at the position of the heart-shaped tip of the heart-shaped display substrate, and the sub-scanning driving circuit 20 (eg, a gate driving circuit) may be arranged in some pixel units.
  • the connection lines of the scan driving circuits of the heart-shaped head area may be introduced from the heart-shaped head area and connected to the sub-scan driving circuits of the heart-shaped head area.
  • a display substrate with a heart-shaped border includes a display area with a heart-shaped tip and two symmetrical display areas with a heart-shaped head, and the sub-scanning driving circuits are arranged along the column direction.
  • the display substrate 10 provided by the embodiment of the present disclosure is not limited to a rectangular OLED screen, but is also applicable to a special-shaped OLED screen.
  • the dotted frame in Figure 14 is the GIA circuit of the special-shaped screen. Except for these three areas, pixel units in other display area positions can be provided with auxiliary cathodes of mesh structure. For example, a pixel unit without GIA can be provided with a third auxiliary cathode extending in the column direction and in the same layer as the Data Line.
  • Both the pixel unit provided with GIA and the pixel unit not provided with GIA can be provided with an auxiliary cathode in the same layer as the anode along the row direction, and the PDL opening on the auxiliary cathode is used for connection with the cathode.
  • the conductive layer of gate material may be Mo or the like.
  • the conductive layer of the source and drain materials can be Ti/Al/Ti or the like.
  • the gate material may include metal materials, such as Mo, Al, Cu and other metals and their alloys.
  • the source and drain materials may include metal materials, such as Mo, Al, Cu and other metals and their alloys.
  • the semiconductor material constituting the active layer may include, for example, amorphous silicon, polysilicon, oxide semiconductor, and the like, and the oxide semiconductor material may include, for example, IGZO (indium gallium zinc oxide), ZnO (zinc oxide), and the like.
  • the cathode includes a transparent conductive material
  • the anode includes a metal material.
  • the metal material can be a material with high conductivity and high reflectivity, so that when the light emitted from the light-emitting layer 141 faces the substrate side, it is reflected by the anode to the top of the pixel unit for light output, which helps to improve the light output efficiency. ,Reduce energy consumption.
  • the first electrode 1211 may include a multi-layer metal structure, and the cross-section of the multi-layer metal structure is I-shaped.
  • the specific formation methods of the first electrode 1211, the first auxiliary electrode 30, the second electrode, the third electrode 1111, the second auxiliary electrode 40, the third auxiliary electrode 50, and the pixel defining layer 80 are not limited, and can be determined according to the actual situation. .
  • the above scheme can be directly used to print OLED or FMM (Fine Meta Mask) vapor deposition OLED.
  • the first electrode 1211 , the first auxiliary electrode 30 , the second electrode, the third electrode 1111 , the second auxiliary electrode 40 , the third auxiliary electrode 50 , and the pixel defining layer 80 can all be formed by a printing process, that is, the display substrate 10 It can be made by full printing process.
  • the display substrate 10 fabricated by the full printing process has the advantages of high lifespan, high PPI, and less process flow.
  • the solution shown above cannot be directly used for the entire surface of the vapor-deposited OLED (Opne Mask), but it can be further improved and used on the basis of the above solution, that is, some special processes can also be used to achieve the first
  • the auxiliary electrode 30 is connected to the first electrode 1211 , or the second auxiliary electrode 40 is connected to the third electrode 1111 .
  • the Anode layer with a special film structure such as an inverted trapezoid or an "I" structure
  • cuts off the vapor-deposited EL layer so that the Cathode can be connected to the Anode.
  • the first electrode 1211 includes a multi-layer metal structure, and the cross-section of the multi-layer metal structure is I-shaped. In this way, after the OLED is formed, the light-emitting layer 141 is automatically cut off, and the first auxiliary electrode 30 is connected with the first electrode 1211 , or the second auxiliary electrode 40 is connected with the third electrode 1111 .
  • FIG. 15 is a schematic cross-sectional view of an organic light emitting diode according to an embodiment of the present disclosure.
  • the first electrode 1211 includes a stacked indium tin oxide layer 12111/aluminum layer 12112/indium tin oxide layer 12113.
  • the first electrode 1211 may be formed by patterning, for example, a pattern of the first electrode 1211 may be formed by a photolithography and an etching process. Since the etching is carried out from the upper surface to the lower surface, the etching time of the upper surface film is longer than that of the lower surface film.
  • the size of the tin layer 12111 may be smaller than the size of the underlying indium tin oxide layer 12113 .
  • the thickness of the Al layer can be increased).
  • the thickness of the aluminum layer 12112 may be greater than the thickness of the indium tin oxide layer 12111
  • the thickness of the aluminum layer 12112 may be greater than the thickness of the indium tin oxide layer 12113 .
  • the ratio of the thickness of the aluminum layer 12112 to the thickness of the indium tin oxide layer 12111 is greater than 3:1.
  • the light-emitting layer 141 is then evaporated.
  • the movement directions of the atoms in the light-emitting layer 141 are highly consistent, and the movement direction is relatively the same as that on the first electrode 1211 .
  • the normal direction of the surface is relatively consistent, so that the protruding part of the indium tin oxide layer 12111 relative to the aluminum layer 12112 will block the atoms of the light emitting layer 141 from entering the I-shaped concave area, forming a cut off as shown in FIG. 15 .
  • the light-emitting layer 141 is exposed, so that part of the indium tin oxide layer 12113 and the sides of the aluminum layer 12112 will be exposed. Then, a cathode layer can be prepared by a sputtering process, and a cathode 131 is formed on the light emitting layer 141 located on the indium tin oxide layer 12111. In addition, due to the sputtering process, the moving direction of the atoms of the cathode material sputtered from the target is quite different from the normal direction of the surface of the aluminum layer 12112 in FIG.
  • a cathode layer is formed on at least part of the sidewall of the cathode (area C shown in the dashed box in the figure), so that the cathode can be conveniently connected to the metal wire located in the anode layer to improve the conductivity of the cathode.
  • the structure shown in Figure 15 does not need to prepare vias through lithography, etching and other processes, which simplifies the process and improves the manufacturing efficiency.
  • the auxiliary cathode can also be improved to reduce the interference of the signal in the signal line caused by the introduction of the auxiliary cathode.
  • the display substrate 10 further includes: a first signal line 1601 .
  • the first auxiliary electrode 30 includes: a first main body part 301 and a first narrowing part 302 .
  • the first narrowing portion 302 is connected to the first main body portion, and there is overlap between the orthographic projection of the first narrowing portion on the substrate and the orthographic projection of the first signal line on the substrate.
  • the second auxiliary electrode 40 includes: a second main body portion and a second narrowing portion.
  • the second narrowing portion is connected to the second main body portion, and the orthographic projection of the second narrowing portion on the substrate overlaps with the orthographic projection of the first signal line on the substrate.
  • FIG. 16 is a schematic diagram of a first auxiliary electrode provided by an embodiment of the present disclosure.
  • the line width of the auxiliary cathode is designed to maximize the space.
  • the auxiliary cathode overlaps with other high-frequency signal lines, it can be narrowed at the overlap, similar to a dumbbell shape, which can reduce the auxiliary electrode to the grid line.
  • FIG. 17 is a schematic diagram of a third auxiliary electrode provided by an embodiment of the present disclosure.
  • the above-mentioned display substrate 10 further includes: a second signal line 1701 .
  • the third auxiliary electrode 50 may include: a third main body part 501 and a third narrowing part 502 .
  • the third narrowed portion 502 is connected to the third main body portion 501, and the orthographic projection of the third narrowed portion 502 on the substrate overlaps with the orthographic projection of the second signal line on the substrate.
  • FIG. 17 it is a schematic diagram of an auxiliary cathode extending in the column direction and located in the layer where the source and drain are located (SD layer for short) and overlapping with the gate line extending in the row direction.
  • At least some embodiments of the present disclosure also provide a display panel including the above-mentioned display substrate 10 .
  • the above-mentioned display panel may be an OLED display panel.
  • FIG. 18 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 1 may include the display substrate 10 as shown above.
  • the cathode uses a transparent conductive material.
  • IR Drop voltage drop
  • the voltage drop of the cathode increases significantly, resulting in uneven brightness of the display. Therefore, a large-sized top-emission OLED display panel can use an auxiliary cathode to reduce the cathode impedance and meet the voltage drop requirement required for display.
  • the OLED display panel includes a cover plate and a back plate that are assembled together.
  • the cover plate includes a substrate 101 and a black matrix 102 , a color filter layer 103 , a flat layer 104 , and a black matrix 102 formed on the cover plate substrate 101 .
  • Film layers such as filling layer 108 and spacer 113.
  • the backplane includes a substrate 115 and film layers such as a pixel defining layer 114, a light-emitting layer 110 and a cathode 109 formed on the substrate 115 (of course, an anode, a first auxiliary cathode, a second auxiliary cathode, For other structures such as the third auxiliary cathode, please refer to the relevant parts of FIG. 2 to FIG. 10 ), the cover plate and the back plate are boxed together by the sealant 107 .
  • the auxiliary cathode of the pixel unit is overlapped with the transparent cathode, and the auxiliary cathode is designed using the existing space, without occupying too much frame area, and at the same time, the purpose of reducing the resistance of the pixel cathode is achieved, which can effectively reduce the problem of VSS IR Rise .
  • Embodiments of the present disclosure also provide a method for manufacturing a display substrate.
  • FIG. 19 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • the manufacturing method of the display substrate may include operations S191 to S193.
  • a substrate 100 is provided, the substrate includes a plurality of pixel units, the plurality of pixel units are arranged on the substrate in an array along a row direction and a column direction, the plurality of pixel units at least include a first pixel unit 12, a second pixel unit A pixel unit 12 includes a first light-emitting area 121 and a first non-light-emitting area.
  • a scan driving circuit is formed in the first non-light emitting area.
  • a first auxiliary electrode is formed on a side of the scan driving circuit away from the substrate, and the first auxiliary electrode is located in a first partial area of the first non-light emitting area.
  • the first light-emitting region 121 includes a first light-emitting element, the first light-emitting element includes a first electrode 1211, a light-emitting layer 141 and a second electrode, and the first auxiliary electrode 30 may be arranged in a row direction or a column direction;
  • the scan driving circuit includes A plurality of sub-scanning driving circuits, the sub-scanning driving circuits are located in the second partial area in the first non-light-emitting area, and the sub-scanning driving circuits are arranged between the substrate and the first electrode 1211;
  • the first auxiliary electrode 30 and the first electrode 1211 are located in the same layer.
  • the pixel unit the light-emitting area, the non-light-emitting area, the scan driving circuit, the light-emitting element, the first electrode, the light-emitting layer, the second electrode and the positional relationship between them, you can refer to the above related embodiments, and will not be described in detail here. .
  • FIG. 20 is a flowchart of a method for manufacturing a light-emitting element provided by an embodiment of the present disclosure.
  • the first light-emitting element is prepared through operations S201 to S204.
  • a metal layer stack is evaporated, and the metal layer stack includes an indium tin oxide layer/aluminum layer/indium tin oxide layer.
  • the metal layer stack is etched based on the patterned mask, wherein the etching rate of the indium tin oxide layer is lower than that of the aluminum layer.
  • an I-shaped first electrode 1211 (anode of the OLED) may be formed through an imaging process.
  • the light emitting layer 141 is evaporated.
  • the thickness of the light-emitting layer 141 is smaller than the thickness of the first electrode 1211, the light-emitting layer 141 will be automatically cut by the I-shaped structure, and part of the surface of the indium tin oxide layer 1113 and the sidewall of the aluminum layer 11112 will be exposed (the area shown in FIG. 15 ). C).
  • a second electrode layer is formed by sputtering so that the second electrode is in contact with the aluminum layer in the metal layer stack and the indium tin oxide layer close to the aforementioned substrate, respectively.
  • the cathode is in contact with the electrode wire in the region C, so that the electrode wire acts as an auxiliary cathode and reduces the resistance of the cathode.
  • Another aspect of the present disclosure provides a display device.
  • FIG. 21 is a block diagram of a display device provided by an embodiment of the present disclosure.
  • the display device 2100 includes one or more display panels 1 as shown above.
  • the above-mentioned display panel 1 includes a display area and a non-display area, and the non-display area has a smaller width, thereby realizing a display device with a narrow frame.
  • the display apparatus 2100 may include one or more processors 2110 and a computer-readable storage medium 2120 .
  • the processor 2110 may include, for example, a general-purpose microprocessor, an instruction set processor and/or a related chipset and/or a special-purpose microprocessor (eg, an application specific integrated circuit (ASIC)), and the like.
  • the processor 2110 may also include onboard memory for caching purposes.
  • the computer-readable storage medium 2120 can be, for example, a non-volatile computer-readable storage medium, and specific examples include but are not limited to: magnetic storage devices, such as magnetic tapes or hard disks (HDD); optical storage devices, such as compact disks (CD-ROMs) ; memory, such as random access memory (RAM) or flash memory, etc.
  • magnetic storage devices such as magnetic tapes or hard disks (HDD)
  • optical storage devices such as compact disks (CD-ROMs)
  • CD-ROMs compact disks
  • memory such as random access memory (RAM) or flash memory, etc.
  • the computer-readable storage medium 2120 may include a program 2121, which may include code/computer-executable instructions that, when executed by the processor 2110, cause the processor 2110 to perform image display data processing.
  • the code in program 2121 may include one or more program modules, including, for example, program module 2121A, program module 2121B, . . .
  • the above-mentioned display device may include any device or product having a display function.
  • the above-mentioned display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player devices, mobile medical devices, cameras, wearable devices (such as head-mounted devices, electronic apparel, electronic bracelets, electronic necklaces, electronic accessories, electronic tattoos, or smart watches), televisions, etc.

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Abstract

一种显示基板、显示面板和显示基板制造方法。该显示基板包括衬底；设置在衬底上的多个像素单元，多个像素单元沿行方向和列方向成阵列地排布在衬底上，多个像素单元至少包括第一像素单元，第一像素单元包括第一发光区域和第一非发光区域；设置在第一发光区域中的第一发光元件，第一发光元件包括第一电极、发光层和第二电极；设置在第一非发光区域的扫描驱动电路；设置在扫描驱动电路远离衬底一侧的第一辅助电极，第一辅助电极位于第一非发光区域中的第一部分区域，其中，第一辅助电极沿行方向或者列方向布置；扫描驱动电路包括多个子扫描驱动电路，子扫描驱动电路位于第一非发光区域中的第二部分区域；第一非发光区域中的第一部分区域和第一非发光区域中的第二部分区域在衬底上的正投影存在交叠，第一辅助电极和第二电极电连接。

Description

显示基板、显示面板和显示基板制造方法 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示面板和显示基板制造方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)显示技术逐渐被广泛应用，成为最有潜力替代液晶显示(Liquid Crystal Display，简称LCD)的显示技术。相对于LCD显示技术而言，OLED显示技术从画质，响应速度，轻薄度等方面具有更优体验。
然而，OLED显示技术无疑比LCD显示技术要复杂很多，尤其是OLED的面板电路复杂，为应对不同的应用场景出现各种对应的技术而无法实现统一。例如，较大尺寸顶发射OLED的阴极的电压升高(IR Rise)必须要解决。又例如，OLED为电流型器件，发光需要电源使像素自发光，给发光器件供电的电源线需要占居较大边框，导致外观不佳。
发明内容
有鉴于此，本公开实施例提供一种显示基板、显示面板和显示基板制造方法，用于在改善大尺寸顶发射OLED的阴极的压降升高的同时减小边框尺寸。
本公开的实施例提供了一种显示基板，包括：衬底；设置在衬底上的多个像素单元，多个像素单元沿行方向和列方向成阵列地排布在衬底上，多个像素单元至少包括第一像素单元，第一像素单元包括第一发光区域和第一非发光区域；设置在第一发光区域中的第一发光元件，第一发光元件包括第一电极、发光层和第二电极；设置在第一非发光区域的扫描驱动电路；设置在扫描驱动电路远离衬底一侧的第一辅助电极，第一辅助电极位于第一非发光区域中的第一部分区域，其中，第一辅助电极沿行方向或者列方向布置；扫描驱动电路包括多个子扫描驱动电路，子扫描驱动电路位于第一非发光区域中的第二部分区域；第一非发光区域中的第一部分区域和第一非发光区域中的第二部分区域在衬底上的正投影存在交叠，第一辅助电极和第二电极电连 接。
在某些实施例中，第一辅助电极与第一电极位于同一层。
在某些实施例中，多个像素单元还包括第二像素单元，第二像素单元包括第二发光区域和第二非发光区域，第二非发光区域中未设置扫描驱动电路。
在某些实施例中，上述显示基板还包括：设置在第二发光区域中的第二发光元件，第二发光元件包括：第三电极、发光层和第四电极；第二辅助电极，第二辅助电极位于第二非发光区域中的第一部分区域，其中，第二辅助电极与第三电极位于同一层，第三电极与第一电极位于同一层，第二辅助电极与第一辅助电极平行布置，第二辅助电极和第四电极电连接。
在某些实施例中，上述显示基板还包括：设置在第三电极所在层的靠近衬底一侧的源漏极，源漏极位于第二非发光区域；第三辅助电极，第三辅助电极位于第二非发光区域中的第二部分区域，第三辅助电极的延伸方向与第二辅助电极的延伸方向在衬底上的正投影相接，源漏极和第二非发光区域中的第二部分区域在衬底上的正投影相互隔离，第三辅助电极与源漏极设置在同一层，第三辅助电极和第二辅助电极电连接。
在某些实施例中，一条第二辅助电极对应一行或多行第二像素单元；和/或一条第三辅助电极对应一列或多列第二像素单元。
在某些实施例中，上述显示基板，还包括：第一信号线；第一辅助电极包括：第一主体部；与第一主体相连的第一收窄部，第一收窄部在衬底上的正投影与第一信号线在衬底上的正投影之间存在交叠。
在某些实施例中，上述显示基板，还包括：第一信号线；第二辅助电极包括：第二主体部；与第二主体相连的第二收窄部，第二收窄部在衬底上的正投影与第一信号线在衬底上的正投影之间存在交叠。
在某些实施例中，上述显示基板还包括第二信号线；第三辅助电极包括：第三主体部；与第三主体部相连的第三收窄部，第三收窄部在衬底上的正投影与第二信号线在衬底上的正投影之间存在交叠。
在某些实施例中，上述显示基板还包括：非显示区；以及设置在非显示区的第二电极总线，第二电极总线用于传输参考电压信号给第二电极和/或第四电极。
在某些实施例中，第一辅助电极和第二辅助电极与第二电极总线设置在 同一层，第一辅助电极和第二电极总线相连，并且第二辅助电极和第二电极总线相连；或者第三辅助电极与第四电极总线设置在同一层，第三辅助电极和第四电极总线相连。
在某些实施例中，上述显示基板还包括：叠层设置的平坦化层和绝缘层，设置在第二辅助电极和第三辅助电极之间，平坦化层包括第一过孔，绝缘层包括第二过孔，第一过孔与第二过孔在衬底上的正投影存在交叠；以及第一辅助电极通过第一过孔和第二过孔与第二辅助电极电连接。
在某些实施例中，第一过孔和第二过孔是圆形过孔，第二过孔的直径大于第一过孔的直径；或者第一过孔和第二过孔是多边形过孔，第二过孔的面积大于第一过孔的面积。
在某些实施例中，上述显示基板还包括：设置在第二电极和第一辅助电极之间的像素界定层，像素界定层包括第三过孔，第一辅助电极通过第一过孔和第二电极电连接。或者，设置在第四电极和第二辅助电极之间的像素界定层，像素界定层包括第三过孔；以及第二辅助电极通过第三过孔和第四电极电连接。
在某些实施例中，第一过孔是圆形过孔，第三过孔是条形过孔，条形过孔沿行方向的尺寸大于第一过孔的直径。
在某些实施例中，第一过孔与第三过孔在衬底上的正投影相互间隔。
在某些实施例中，像素界定层在衬底上的正投影覆盖第一非发光区域；和/或像素界定层在衬底上的正投影覆盖第二非发光区域。
在某些实施例中，一条第一辅助电极对应一行或多行第一像素单元。
在某些实施例中，一个子扫描驱动电路对应一列或多列第一像素单元。
在某些实施例中，上述显示基板的形状包括方形、长方形、多边形和具有弧线边界的形状中任意一种。
在某些实施例中，对于具有心形边界的显示基板，多个像素单元分别位于不同的显示区，每个显示区具有独享的子扫描驱动电路。
在某些实施例中，具有心形边界的显示基板包括心形尖部的显示区、心形头部的两个对称显示区，子扫描驱动电路沿列方向设置。
在某些实施例中，第一电极包括多层金属结构，多层金属结构的横截面为工字型。
在某些实施例中，第一电极包括堆叠的氧化铟锡层/铝层/氧化铟锡层。
在某些实施例中，第一非发光区域是L型区域。
在某些实施例中，发光层包括有机发光二极管，第一电极和第三电极为有机发光二极管的阳极，第二电极和第四电极为有机发光二极管的阴极；以及扫描驱动电路包括栅驱动电路。
在某些实施例中，阴极包括的材料为透明导电材料，阳极包括的材料为金属材料。
本公开实施例提供了一种显示面板，包括如上的显示基板。
本公开实施例提供了一种显示基板的制造方法，包括：提供衬底，衬底包括多个像素单元，多个像素单元沿行方向和列方向成阵列地排布在衬底上，多个像素单元至少包括第一像素单元，第一像素单元包括第一发光区域和第一非发光区域；在第一非发光区域中形成扫描驱动电路；在扫描驱动电路远离衬底一侧形成第一辅助电极，第一辅助电极位于第一非发光区域中第一部分区域，其中，第一发光区域中包括第一发光元件，第一发光元件包括第一电极、发光层和第二电极，第一辅助电极沿行方向或者列方向布置；扫描驱动电路包括多个子扫描驱动电路，子扫描驱动电路位于第一非发光区域中第二部分区域，子扫描驱动电路设置在衬底和第一电极之间；第一非发光区域中的第一部分区域和第一非发光区域中的第二部分区域在衬底上的正投影存在交叠，第一辅助电极和第二电极电连接。
在某些实施例中，第一辅助电极与第一电极位于同一层。
在某些实施例中，第一发光元件通过如下方式进行制备：蒸镀金属层堆叠，金属层堆叠包括氧化铟锡层/铝层/氧化铟锡层；基于图形化掩膜对金属层堆叠进行刻蚀，其中，氧化铟锡层的刻蚀速率小于铝层的刻蚀速率；蒸镀发光层；以及溅射形成第二电极层，使得第二电极分别与金属层堆叠中的铝层和靠近衬底的氧化铟锡层相接触。
本公开的附加方面的优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
为了更清楚地说明本公开文本的实施例的技术方案，下面将对实施例的 附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开文本的一些实施例，而非对本公开文本的限制，其中：
图1为一种显示基板的平面图；
图2为本公开实施例提供的像素单元的示意图；
图3为本公开实施例提供的像素单元中压缩出的非发光区域的示意图；
图4为本公开实施例提供的具有GIA的第一像素单元的示意图；
图5为本公开实施例提供的第一辅助电极的示意图；
图6为图5中沿线A-A截取的截面结构示意图；
图7为本公开实施例提供的第二辅助电极的示意图；
图8为本公开实施例提供的第二辅助电极和第三辅助电极的示意图；
图9为图8中沿线C-C截取的截面结构示意图；
图10为图8中沿线C-C截取的另一截面结构示意图；
图11为本公开实施例提供的第二电极总线的示意图；
图12为本公开实施例提供的第四电极总线的示意图；
图13为本公开实施例提供的同时设置第二电极总线和第四电极总线的示意图；
图14为本公开实施例提供的心形显示基板的GIA的示意图；
图15为本公开实施例提供的有机发光二极管的截面示意图；
图16为本公开实施例提供的第一辅助电极的示意图；
图17为本公开实施例提供的第三辅助电极的示意图；
图18为本公开实施例提供的显示面板的结构示意图；
图19为本公开实施例提供的显示基板的制造方法的流程图；
图20为本公开实施例提供的发光元件的制造方法的流程图；以及
图21为本公开实施例提供的显示装置的方框图。
具体实施方式
为更清楚地阐述本公开的目的、技术方案及优点，以下将结合附图对本公开的实施例进行详细的说明。应当理解，下文对于实施例的描述旨在对本公开的总体构思进行解释和说明，而不应当理解为是对本公开的限制。在说明书和附图中，相同或相似的附图标记指代相同或相似的部件或构件。为了 清晰起见，附图不一定按比例绘制，并且附图中可能省略了一些公知部件和结构。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。例如，本公开中使用的术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一区域和/或第一部分可以被称为第二部件、第二区域和/或第二部分，而不背离本公开的教导。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”“顶”或“底”等等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。当诸如层、膜、区域或衬底之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
需要说明的是，在本文中，表示“同一层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。即，位于“同一层”的多个元件、部件、结构和/或部分由相同的材料构成，并且通过同一次构图工艺形成，通常，位于“同一层”的多个元件、部件、结构和/或部分具有大致相同的厚度。
为了便于理解本公开的技术方案，首先对一种显示装置和该显示装置存在的问题及其产生的原因进行说明。
OLED显示技术逐渐被广泛应用，成为替代LCD显示的一种最有潜力的显示技术。相对LCD显示而言，OLED显示技术具有更优体验，如在画质，响应速度，轻薄度等等方面具有优势。但从技术方面而言，OLED的制备过程比LCD的制备过程要复杂很多，尤其是OLED的面板电路复杂。这导致针对不同的应用场景出现的各种对应的OLED技术无法实现统一。例如，较大尺寸顶发射OLED的阴极的IR Rise必须要解决。又例如，OLED为电流型发 光器件，需要电源使像素自发光，而电源线的设计往往需要占居较大的边框区域，导致外观不佳。
基于上述问题，本公开实施例提供了一种基于GIA技术来实现更窄边框，并且解决阴极IR Rise大造成显示效果差的问题的技术方案。GIA是将栅驱动电路放在显示区域内，通过不占边框而实现显示屏左右边框窄边化。
GIA设计时会压缩一定的像素空间(行方向和列方向)用于设置GIA电路。GIA电路不会使用源漏极所在膜层之后的膜层，例如，不会使用像素界定层(PLN)、阳极(Anode)、平坦化层(PDL)。整个显示区域可以分成两类像素单元，一类是设置了GIA电路的像素单元。另一类是没有设置GIA电路的像素单元。
图1为一种显示基板的平面图。
如图1所示，显示基板10可以是用于OLED显示面板的阵列基板。
参照图1，上述显示基板10可以包括显示区域(如多个像素单元所在的区域)，和非显示区域(如阴极总线200所在的区域)。图1中显示基板10还可以包括位于非显示区域内的驱动电路31等。例如，该驱动电路31可以位于显示区域的至少一侧。在图1所示的实施例中，驱动电路31位于显示区域的下侧。上述“下侧”可以为在显示时，人眼观看的显示面板(屏幕)的下侧。驱动电路31可以用于驱动显示基板10中的各个像素进行显示。例如，上述驱动电路31可以包括数据驱动电路。数据驱动电路用于依据时钟信号定时将输入的数据顺序锁存并将锁存的数据转换成模拟信号后输入到显示基板10的各条数据线上。需要说明的是，显示基板10还可以包括栅极驱动电路，其通常由移位寄存器实现，移位寄存器将时钟信号转换成开启/关断电压，分别输出到显示基板10的各条栅线上。
需要说明的是，虽然图1中示出驱动电路31位于显示区域的下侧，但是，本公开的实施例不局限于此，驱动电路31可以位于非显示区域任何合适的位置。
例如，显示区域中还可以设置：采用有源阵列区的栅驱动电路(Gate Driver Integrate Array，简称GIA)。具体地，显示区域可以包括GIA显示区域(W/O GIA)和非GIA显示区域(W/.GIA)。其中，GIA显示区域可以包括多个设置有GIA的第一像素单元12。非GIA显示区域可以包括多个不设 置GIA的第二像素单元11。将栅驱动电路20直接设置于阵列基板上的第一显示单元12中，以代替外接驱动芯片。每列栅驱动电路20可以作为一级移位寄存器，每级移位寄存器与一条栅线连接，通过各级移位寄存器依序轮流输出开启电压，实现像素的逐列或逐行扫描。在某些实施例中，每级移位寄存器也可以与多条栅线连接。这样，可以适应显示基板高分辨率、窄边框的发展趋势。
图1所示的显示基板10，各像素单元可以包括发光区域100和非发光区域。其中，发光区域100中可以包括多个像素，如一个像素单元可以包括红色像素、蓝色像素和绿色像素。各像素分别通过信号线扇出(Fan-out)至驱动电路31上，以供应驱动信号给各个像素。信号线包括但不限于：扫描线、数据线、ELVDD电源线和ELVSS电源线等，以便为每个子像素中的像素驱动电路提供控制信号、数据信号、电源电压等各种信号。
每个像素可以分别包括阳极、发光元件和阴极，阴极可以是透明导电电极，覆盖至少部分显示基板10。为了给阴极供电，可以实现阴极与阴极总线200之间的电连接，可以通过有源阵列区的阴极连接孔(VSS Connect Hole Integrate Array)210使得阴极与阴极总线200连接。由于阴极总线200需要通过阴极连接孔210与阴极电连接，使得非显示区域(如边框)需要占用较大的边框。
本公开实施例提供的一种显示基板，参考图1所示，针对有GIA电路的第一像素单元12，可以在非发光区域的沿行方向延伸区域的阳极(Anode)层中制作辅助阴极，再通过像素界定层(PDL)开口，使辅助阴极与阴极连接起来。
针对无GIA电路的第二像素单元11，同样可以在阳极(Anode)层在非发光区域的沿行方向延伸区域中制作辅助阴极，再通过像素界定层(PDL)开口，使辅助阴极与阴极连接起来。在非发光区域的沿列方向延伸区域的源漏极所在金属层制作辅助阴极，并在与行方向延伸区域的辅助电极交叠处设计过孔，实现与行方向辅助阴极连接起来。
本公开实施例在显示基板10的显示区域中，在无GIA像素单元和有GIA像素单元中都有至少一个辅助阴极(如设置在Anode层，且位于非发光区域的行延伸方向上)与阴极连接。此外，无GIA的像素单元内还设置有沿列方 向延伸的辅助阴极，其设置在源漏极所在的层。显示区域中所有沿行方向延伸的辅助阴极线和所有沿列方向延伸的辅助阴极通过过孔连接起来。因此只需通过位于显示区域外的阴极总线与辅助阴极连接即可，如位于显示基板10下方的阴极总线与沿列方向延伸的辅助阴极连接即可，外围阴极总线无需通过连接孔与阴极相连，相对传统在阴极总线增加与阴极接触孔的设计可减少一些边框。
以下结合图2～图17对显示基板进行示例性说明。
在某些实施例中，显示基板10可以包括：衬底、像素单元、第一发光元件、扫描驱动电路和第一辅助电极30。
其中，多个像素单元设置在衬底上，多个像素单元沿行方向和列方向成阵列地排布在衬底上，多个像素单元至少包括第一像素单元12，第一像素单元12包括第一发光区域121和第一非发光区域。例如，衬底可以采用多种透明材料制备而成，如玻璃衬底、有机透明衬底等。
第一发光元件设置在第一发光区域121中，第一发光元件包括第一电极1211(如阳极)、发光层141和第二电极(如阴极)。其中，发光层141可以有机发光层，也可以是无机发光层。发光层141在被注入电流后发光。
扫描驱动电路设置在第一非发光区域。扫描驱动电路可以包括多个薄膜晶体管。
第一辅助电极30设置在扫描驱动电路远离衬底的一侧，第一辅助电极30位于第一非发光区域中的第一部分区域。
具体地，第一辅助电极30沿行方向或者列方向布置。扫描驱动电路包括多个子扫描驱动电路20，子扫描驱动电路位于第一非发光区域中的第二部分区域。第一非发光区域中的第一部分区域和第一非发光区域中的第二部分区域在衬底上的正投影存在交叠，第一辅助电极30和第二电极电连接。例如，第一辅助电极30与第一电极1211位于同一层。
图2为本公开实施例提供的像素单元的示意图。
如图2所示，像素单元中可以包括发光区域111和非发光区域112。发光区域111中可以包括多个子像素。例如，发光区域111可以包括红色子像素1112、绿色子像素1113和蓝色子像素1114。通过调整红色子像素1112、绿色子像素1113和蓝色子像素1114各自的发光强度，可以调节该发光区域的发 光颜色。例如，红色子像素1112和绿色子像素1113发光，蓝色子像素1114不发光，则该像素单元可以发出黄色光。红色子像素1112、绿色子像素1113和蓝色子像素1114各自可以分别具有多级发光强度，以混合出多种颜色光。
每个子像素可以具有各自的阳极1111、发光元件和阴极。对于顶发射OLED，每个子像素可以分别对应一个阳极，多个子像素可以共用一个阴极。各子像素的的发光元件可以发出同色光，也可以分别发出不同颜色的光。例如，红色子像素1112的发光元件发出红色光，绿色子像素1113的发光元件发出绿色光，蓝色子像素1114的发光元件发出蓝色光。例如，红色子像素1112、绿色子像素1113和蓝色子像素1114的发光元件都发出白光，然后分别通过红色彩膜、绿色彩膜和蓝色彩膜对各自发光元件发出的白光进行过滤，得到红色光、绿色光和蓝色光。
还需要说明的是，子像素在衬底上的正投影的形状可以为圆角矩形，但是，本公开的实施例不局限于此，例如，子像素在衬底基板上的正投影的形状可以为矩形、六边形、五边形、正方形、圆形等其他形状。
图3为本公开实施例提供的像素单元中压缩出的非发光区域的示意图。
如图3所示，为了降低扫描驱动电路占用的显示基板10的边缘区域，可以改变像素单元中各子像素的设计样式，使得像素单元中存在非发光区域112。这样可以实现在该非发光区域112中设置电路，如驱动电路、辅助电路等。其中，被设置的电路可以占据所有非发光区域112，或者占用部分非发光区域112。
在某些实施例中，非发光区域112是L型区域。此外，非发光区域112还可以是I形区域、凹形区域、月牙形区域、□形区域等，在此不做限定。
图4为本公开实施例提供的具有GIA的第一像素单元的示意图。
如图4所示，子扫描驱动电路20可以分布在整个非发光区域。具体地，子扫描驱动电路20可以是栅极驱动电路。栅极驱动电路通常由移位寄存器实现，移位寄存器将时钟信号转换成开启/关断电压，分别输出到显示基板10的各条栅线上。第一像素单元12可以包括：第一发光区域121和第一非发光区域。第一发光区域121中可以包括多个子像素。例如，第一发光区域121可以包括红色子像素1212、绿色子像素1213和蓝色子像素1214。每个子像素可以具有各自的阳极1211、发光元件和阴极。对于顶发射OLED，每个子 像素可以分别对应一个阳极，多个子像素可以共用一个阴极。
图5为本公开实施例提供的第一辅助电极的示意图。
如图5所示，第一辅助电极30位于第一非发光区域中的第一部分区域，该第一部分区域可以是上述第一非发光区域中沿行方向延伸的区域。该第一辅助电极30可以通过过孔与位于其上层的阴极电连接。第一辅助电极30的材料可以同第一电极1211。
第一电极1211可以是反射阳极，例如它可由金属材料形成。金属材料可以包括镁铝合金(MgAl)、锂铝合金(LiAl)等合金或者镁、铝、锂等单金属。例如，第一电极1211可以是单层金属结构，如单层银(Ag)金属电极。第一电极1211可以是多层金属电极，如氧化铟锡(ITO)/银(Ag)/氧化铟锡(ITO)的叠层、钛(Ti)/银(Al)/钛(Ti)的叠层等。
对于中大尺寸的顶发射OLED，阴极为高阻抗的透明阴极，其压升(VSS IR Rise)比较大，即能量输入(Power In)近端与远端的阴极电压值差异较大。本公开实施例通过设置与透明电极并联的低电阻的材料，以此降低阴极电流路径的阻抗，即增加辅助阴极。
需要说明的是，无GIA电路的像素区域的空白区在不设置辅助阴极时，也可以保持空白。或者，为了使得显示基板10各处的均匀性保持一致，设计一些伪图案(dummy Pattern)。
在某些实施例中，发光层141包括有机发光二极管，第一电极1211和第三电极1111为有机发光二极管的阳极，第二电极和第四电极为有机发光二极管的阴极。扫描驱动电路包括栅驱动电路。
发光层141可以为多层结构，例如它可以包括空穴注入层、空穴传输层、有机发光层、电子传输层和电子注入层形成的多层结构。
第二电极可以直接覆盖整个显示基板10，如可以通过蒸镀、溅射等方式制备第二电极。第二电极可以是透明电极以实现OLED发出的光从显示基板10的顶部出射，而不会被第二电极全吸收或全反射。例如，第二电极包括但不限于以下至少一种：ITO、氧化铟锌锡ITZO、氧化铟锌(IZO)、纳米银层等。
在某些实施例中，第一辅助电极30和第二电极之间可以通过介质层隔离开。可以通过在介质层上开孔的方式使得第一辅助电极30和第二电极之间电 连接。介质层包括但不限于以下至少一种：像素界定层、绝缘层、平坦化层等。
需要说明的是，OLED器件可以采用有源驱动或无源驱动。无源驱动OLED阵列基板由阴极和阳极构成，阳极和阴极的交叉部分可以发光，驱动电路可由带载封装或玻璃载芯片等连接方式进行外装。有源驱动OLED阵列基板对每个像素可配备像素驱动电路，该像素驱动电路可以包括具有开关功能的薄膜晶体管(即开关晶体管)、具有驱动功能的薄膜晶体管(即驱动晶体管)和一个电荷存储电容，另外，像素驱动电路还可以包括具有补偿功能的其他类型的薄膜晶体管。应该理解，在本公开的实施例中，上述显示面板可以配备已知的各种类型的像素驱动电路，在此不再赘述。
图6为图5中沿线A-A截取的截面结构示意图。
如图6所示，第一辅助电极30和第二电极之间存在一层或多层介质层等，该一层或多层介质层使得位于不同层的第一辅助电极30和第二电极之间电绝缘。可以通过光刻、刻蚀等工艺在该介质层上形成开孔31，实现位于不同层的第一辅助电极30和第二电极之间电连接。例如，在形成第一辅助电极30之后，形成介质层，然后通过光刻、刻蚀等工艺在介质层上形成开孔31以暴露第一辅助电极30，然后形成第二电极，使得位于开孔处的第二电极与暴露的第一辅助电极30之间电连接。需要说明的是图6中第一辅助电极30之下还可以具有其他结构，如GIA电路、源漏极、数据线等。
在某些实施例中，多个像素单元还包括第二像素单元11，第二像素单元11包括第二发光区域121和第二非发光区域，第二非发光区域中未设置扫描驱动电路。具体地，第二像素单元11可以参考图1中W/O GIA区域中包括的多个像素单元，这些像素单元中没有设置扫描驱动电路。
在某些实施例中，上述显示基板10还可以包括：第二发光元件和第二辅助电极40。
其中，第二发光元件设置在第二发光区域中，第二发光元件包括：第三电极1111、发光层141和第四电极。第三电极1111可以和第一电极1211在同一层。第一电极1211在第一发光元件中的排布方式可以和第三电极1111在第二发光元件中的排布方式相同。第三电极1111的材料可以和第一电极1211的材料相同。第三电极1111可以和第一电极1211在相同的工序中制作。
第二辅助电极40可以位于第二非发光区域中的第一部分区域。上述第二非发光区域中的第一部分区域可以是第二非发光区域中沿行方向延伸的区域。
其中，第二辅助电极40可以与第三电极1111位于同一层，第三电极1111与第一电极1211位于同一层，第二辅助电极40可以与第一辅助电极30平行布置，如第二辅助电极40可以沿行方向布置，第二辅助电极40和第四电极电连接。第一辅助电极30、第二辅助电极40、第一电极1211和第三电极1111可以通过同一次薄膜工艺、光刻工艺和刻蚀工艺形成。
图7为本公开实施例提供的第二辅助电极的示意图。
图7中沿B-B方向的截面结构示意图可以参考图6所示，如将第一辅助电极30替换为第二辅助电极40，将过孔31替换为过孔41，在此不再详述。需要说明的是，第二辅助电极40之下还可以具有其他结构，如伪图案(dummy pattern)、源漏极、数据线等。
此外，图7所示的第二像素单元11还可以包括第二发光区域111和第二非发光区域。第二发光区域111中包括多个子像素，如红色子像素1112、绿色子像素1113和蓝色子像素1114。其中，每个子像素具有各自的阳极1111、发光元件和共用的阴极。其中，第一像素单元12中各子像素的阳极和第二像素单元11中各子像素的阳极可以在同一次工艺中完成制作。
在某些实施例中，上述显示基板10还可以包括：源漏极和第三辅助电极50。
其中，源漏极设置在第三电极1111所在层的靠近衬底的一侧，源漏极位于第二非发光区域。源漏极所在的金属层也可以简称为SD层，SD层可以用于制作源漏极之外，还可以制作第三辅助电极50和数据线等。
第三辅助电极50位于第二非发光区域中的第二部分区域。
图8为本公开实施例提供的第二辅助电极和第三辅助电极的示意图。
如图8所示，相对于图7而言，图8中还进一步包括第三辅助电极50，以及用于实现第二辅助电极40和第三辅助电极50电连接的过孔h。图9为图8中沿线C-C截取的截面结构示意图。图10为图8中沿线C-C截取的另一截面结构示意图。
图8中，第三辅助电极50的延伸方向与第二辅助电极40的延伸方向在衬底上的正投影相接，源漏极和第二非发光区域中的第二部分区域在衬底上 的正投影相互隔离，第三辅助电极50与源漏极设置在同一层以避免源漏极和第三辅助电极50之间短路。例如源漏极可以位于第二发光区域中。
第三辅助电极50和第二辅助电极40电连接。第二辅助电极40和第四电极电连接，使得第三辅助电极50和第四电极电连接。
如图9所示，第二辅助电极40和第三辅助电极50之间可以通过第二过孔h2和第三过孔h3连接。
在某些实施例中，上述显示基板10还可以包括：平坦化层60和绝缘层70。
其中，平坦化层60和绝缘层70叠层设置，并且共同设置在第二辅助电极40和第三辅助电极50之间，平坦化层60包括第一过孔h1，绝缘层70包括第二过孔h2，第一过孔h1与第二过孔h2在衬底上的正投影存在交叠。相应地，第一辅助电极30通过第一过孔h1和第二过孔h2与第二辅助电极40电连接。
在某些实施例中，第一过孔h1和第二过孔h2是多边形过孔，第二过孔h2的直径大于第一过孔h1的直径。或者第一过孔h1和第二过孔h2是多边形过孔，第二过孔h2的面积大于第一过孔h1的面积。这样有助于提升工艺窗口，即使在对位时存在一定误差或偏差，也可以尽量使得第二辅助电极40和第三辅助电极50之间的接触面积不小于第一过孔h1的面积，使得第二辅助电极40和第三辅助电极50之间的接触电阻足够小。
在某些实施例中，上述显示基板10还可以包括：像素界定层80。第一发光元件和/或第二发光元件的阳极至少部分被像素界定层80的开口暴露。例如，像素界定层80在衬底上的正投影覆盖第一非发光区域。又例如，像素界定层80在衬底上的正投影覆盖第二非发光区域。
例如，像素界定层80设置在第二电极和第一辅助电极30之间，像素界定层80包括第三过孔h3，第一辅助电极30通过第一过孔h1和第二电极电连接。
又例如，像素界定层80设置在第四电极1010和第二辅助电极40之间，像素界定层80包括第三过孔h3，第二辅助电极40通过第三过孔h3和第四电极电连接。
如图10所示，显示基板10还包括像素界定层80和第四电极1010，第 四电极覆盖在像素界定层80之上。第四电极1010通过第一过孔h1与第二辅助电极40电连接。例如，在形成图形化的像素界定层80之后，可以通过蒸镀或溅射等工艺形成第四电极。
在某些实施例中，第一过孔h1是多边形过孔，第三过孔h3是条形过孔，条形过孔沿行方向的尺寸大于第一过孔h1的直径。通过增加条形过孔沿行方向的尺寸，可以有效增加阴极与第一辅助电极30和/或第二辅助电极40之间的接触面积，降低接触电阻。
在某些实施例中，第一过孔h1与第三过孔h3在衬底上的正投影相互间隔。这样避免了在显示基板10上形成深度过大的过孔，导致过孔侧壁的阴极厚度较薄。一方面容易增大过孔侧壁出的阴极的电阻，一方面容易出现断点，导致失效或老化性能不好。通过在不同的位置设置第一过孔h1和第三过孔h3，有效减小了单个过孔的深度，在不增加阴极的电阻的前提下提升了可靠性和老化性能等。
本公开实施例中第一辅助电极30位于非发光区，与第一电极1211同层设置，并且相互隔离。这样在制作第一电极1211时可同时制作第一辅助电极30，不需要新增膜层。第二辅助电极40位于非发光区，与第三电极1111同层设置且相互隔离，这样在制作第三电极1111时可同时制作第一辅助电极30，不需要新增膜层。第三辅助电极50位于非发光区，与第二电极同层设置且相互隔离，这样在制作源漏极时可同时制作第三辅助电极50，同样也不需要新增膜层。透明阴极、第一辅助电极30、第二辅助电极40和第三辅助电极50之间实现电连接，可以更多地降低透明阴极的阻抗，从而更有效地降低压降，进而提升显示效果。
在某些实施例中，一条第二辅助电极40对应一行或多行第二像素单元11，和/或，一条第三辅助电极50对应一列或列行第二像素单元11。
无论是源漏极所在层的沿列方向延伸的辅助阴极，还是沿行方向延伸的位于阳极Anode层的辅助阴极，其设计密度可以与像素1：1也可以1：N，即多行或者多列像素设计一条辅助阴极。其中，N是大于1的正整数。
具体地，一行第二像素单元11独享一条沿行方向布置的第二辅助电极40，或者，多行第二像素单元11共同对应一条沿行方向布置的第二辅助电极40。第二像素单元11和第三辅助电极50的布置方式类似于第二像素单元11 和第二辅助电极40的布置方式相类似。在某些实施例中，一条第一辅助电极30对应一行或多行第一像素单元12。
例如，一个子扫描驱动电路可以对应一行像素单元或一列像素单元，此时，一个子扫描驱动电路输出的信号可以作为与该子扫描驱动电路对应的一行像素或一列像素单元的扫描信号。例如，可以采用两行驱动或四行驱动的方式，即，一个子扫描驱动电路的输出信号可以用于驱动两行或四行像素。
需要说明的是，多条第一辅助电极30之间的距离、多条第二辅助电极40之间的距离和多条第三辅助电极50之间的距离可以根据阴极的导电性能和各辅助电极的导电性能等来确定。例如，辅助电极的宽度或厚度较大，导致辅助电极的导电性能优异，并且阴极自身的导电性能也较好，则可以将多条第一辅助电极30之间的距离、多条第二辅助电极40之间的距离、多条第三辅助电极50之间的距离设置更大一些，降低信号串扰的影响。反之，则可以将多条第一辅助电极30之间的距离、多条第二辅助电极40之间的距离、多条第三辅助电极50之间的距离设置更小一些，降低阴极电阻。
在某些实施例中，显示区域的面积较大，可能无需在所有GIA像素单元中都设置GIA电路，而仅在部分GIA像素单元中设置GIA电路。例如，每三列像素单元共用一个子GIA电路。具体地，沿列方向布置的一个子扫描驱动电路对应一列或多列第一像素单元12。
为了实现给阴极供给电源，可以通过在显示区域外增加阴极总线，在阴极总线上挖孔后，使阴极总线与阴极连接，这样就可以实现通过给阴极总线供电来给发光元件的阴极提供电压。但从显示区域引出的数据线(Data Line)需要绕开阴极孔伸出阴极总线后，再进行扇出(Fan-Out)布线。本公开实施例提供了一种无需阴极连接孔即可实现给阴极供电的方案，来进一步减小边框。具体地，辅助阴极从显示区域引出后，直接进行Fan-Out布线，减少边框的量约为阴极总线的宽度。
在某些实施例中，上述显示基板10还可以包括：非显示区以及设置在非显示区的第二电极总线91。其中，第二电极总线91用于传输参考电压信号给第二电极。
在某些实施例中，上述显示基板10还可以包括：非显示区以及设置在非显示区的第四电极总线92，第四电极总线92用于传输参考电压信号给第四 电极。
具体地，为了减小工艺复杂度，例如，第一辅助电极30和第二辅助电极40与第二电极总线91设置在同一层，第一辅助电极30和第二电极总线91相连，并且第二辅助电极40和第二电极总线91相连。
图11为本公开实施例提供的第二电极总线的示意图。
如图11所示，第二电极总线91可以设置在显示基板10一侧的非显示区域中，由于第二电极总线91和第二辅助电极40是位于同层的，使得可以通过薄膜图形化的方式制造相连的第二电极总线91和第二辅助电极40，无需通过开孔连接第二电极总线91和第二辅助电极40，不但简化了工艺，还无需预留开孔所需的区域，有效减少对边框的非显示区域的占用，减小边框宽度。
图12为本公开实施例提供的第四电极总线的示意图。
如图12所示，第三辅助电极50与第四电极总线92设置在同一层，第三辅助电极50和第四电极总线92相连。图12中第四电极总线92可以设置在显示基板10一侧的非显示区域中，如位于显示基板10的底部或顶部，由于第四电极总线92和第三辅助电极50是位于同层的，使得可以通过薄膜图形化的方式制造相连的第四电极总线92和第三辅助电极50，无需通过开孔连接第四电极总线92和第三辅助电极50，不但简化了工艺，并且无需预留开孔所需的区域，有效减少对边框的非显示区域的占用，减小边框宽度。需要说明的是，设置有GIA的像素单元中可以不设置第三辅助阴极50。
具体地，如果利用无GIA的像素单元的空白区，把总线空白区放置与数据线(Data Line)同层的SD层(源漏极所在层)金属线，并连接到显示区域外的阴极总线(VSS Bus Line)上。而像素单元(包括有GIA和无GIA的像素单元)中，行方向GIA区域放置Anode层的金属线，并与位于总线SD层的辅助阴极过孔连接起来，就可实现辅助阴极网状连接结构。行方向Anode层的辅助阴极上的PDL开孔的方式，使该Anode层辅助阴极与透明阴极搭接。通过如上方案既实现给像素阴极供电压的目的，又在现有空间布置辅助阴极，在实现窄边框的基础上可以有效降低VSS IR Rise。
本公开实施例中，第一辅助电极30和第三辅助电极50形成网状结构，第二辅助电极40和第三辅助电极50形成网状结构，可以有效降低透明阴极 的压降，同时极大减轻串扰(Cross Talk)问题，从而显著提高了显示效果，提升了显示基板的显示效果。本公开实施例提供的显示基板10能够在不新增膜层的前提下设置第一辅助电极30、第二辅助电极40和第三辅助电极50，可以进一步降低透明阴极阻抗，从而更有效地降低压降，进而进一步提升显示效果。此外，本公开实施例采用背板工艺中的导线层别，没有新增工艺层别，不会增加制作工艺的复杂性，提高生产效率。
需要说明的是，也可以同时设置第二电极总线91和第四电极总线92。
图13为本公开实施例提供的同时设置第二电极总线和第四电极总线的示意图。
如图13所示，第二电极总线91可以设置在显示基板10左侧的非显示区域中，第四电极总线92可以设置在显示基板10底部的非显示区域中。通过一次针对第一电极1211和第三电极1111所在层的图形化工艺，形成第二电极总线91、第一辅助电极30和第二辅助电极40。通过一次针对源漏极所在层的图形化工艺形成第四电极总线92和第三辅助电极50。第三辅助电极50可以通过过孔分别与第一辅助电极30和第二辅助电极40相连以进一步降低阴极电阻。或者，辅助电极降低阴极电阻的能力已满足设计要求，第三辅助电极50分别与第一辅助电极30和第二辅助电极40之间相互隔离。
本公开实施例提供的显示基板10不仅仅能适用于矩形显示基板，还可以适用于异形屏场景。
在某些实施例中，上述显示基板10的形状包括方形、长方形、多边形和具有弧线边界的形状中任意一种。
例如，对于具有心形边界的显示基板10，多个像素单元分别位于不同的显示区，每个显示区具有独享的子扫描驱动电路。
图14为本公开实施例提供的心形显示基板的GIA的示意图。
如图14所示，以心形显示基板为例，可以将心形显示基板划分为三大块，心形尖部区域以及镜像分布的心形头部区域。每个区域分别具有各自的子扫描驱动电路20。具体地，可以在心形显示基板的心形尖部位置处设置数据驱动电路等，子扫描驱动电路20(如栅极驱动电路)可以设置在部分像素单元中。心形头部区域的扫描驱动电路的连接线可以从心形头部区域引入，并连接至心形头部区域的子扫描驱动电路。
具体地，具有心形边界的显示基板包括心形尖部的显示区、心形头部的两个对称显示区，子扫描驱动电路沿列方向设置。
本公开实施例提供的显示基板10，不仅局限为矩形的OLED屏，同样适用于异形OLED屏。图14中虚线框处为异形屏的GIA电路，除这三个区域外其他显示区域位置的像素单元，均可设置网状结构的辅助阴极。例如，没有设置GIA的像素单元可以设置沿列方向延伸且与Data Line同层的第三辅助阴极。设置有GIA的像素单元和没有设置GIA的像素单元，都可以在沿行方向设置与阳极同层的辅助阴极，且该辅助阴极上的PDL开口用于与阴极连接。
在某些实施例中，栅极材料的导电层可以是Mo等。源漏极材料的导电层可以是Ti/Al/Ti等。
具体地，栅极材料可以包括金属材料，例如Mo、Al、Cu等金属及其合金。源漏极材料可以包括金属材料，例如Mo、Al、Cu等金属及其合金。构成有源层的半导体材料例如可以包括非晶硅、多晶硅、氧化物半导体等，氧化物半导体材料例如可以包括IGZO(铟镓锌氧化物)、ZnO(氧化锌)等。
在某些实施例中，阴极包括的材料为透明导电材料，阳极包括的材料为金属材料。其中，金属材料可以采用导电率高，并且反射率高的材料，这样可以使得发光层141出射的光线朝向衬底一侧时，被阳极反射至像素单元的顶部以便出光，有助于提升出光效率，降低能耗。
第一电极1211可以包括多层金属结构，多层金属结构的横截面为工字型。
上述第一电极1211、第一辅助电极30、第二电极、第三电极1111、第二辅助电极40、第三辅助电极50、像素界定层80的具体形成方法不做限定，可以根据实际情况确定。打印OLED或者FMM(Fine Meta Mask)的蒸镀OLED可以直接使用上述方案。
例如，第一电极1211、第一辅助电极30、第二电极、第三电极1111、第二辅助电极40、第三辅助电极50、像素界定层80均可采用打印工艺形成，即该显示基板10可采用全打印工艺制作。通过全打印工艺制作的显示基板10具有高寿命，高PPI，工艺流程少等优点。
在某些实施例中，对于整面的蒸镀OLED(Opne Mask)不能直接使用如上所示的方案，但可在上述方案的基础上进一步改进使用，即还可以通过一 些特殊工艺来实现第一辅助电极30与第一电极1211相连，或者，实现第二辅助电极40与第三电极1111相连。比如特殊膜层结构的Anode层(如倒梯形或者”工“字结构)切断蒸镀的EL层，使得Cathode可以与Anode连接。例如，第一电极1211包括多层金属结构，多层金属结构的横截面为工字型。这样便于在形成OLED后，自动切断发光层141，并且使得第一辅助电极30与第一电极1211相连，或者，使得第二辅助电极40与第三电极1111相连。
图15为本公开实施例提供的有机发光二极管的截面示意图。
如图15所示，例如，第一电极1211包括堆叠的氧化铟锡层12111/铝层12112/氧化铟锡层12113。在形成上述堆叠之后，可以通过图形化的方式形成第一电极1211，如通过光刻和刻蚀工艺形成第一电极1211图形。由于刻蚀时是从上表面向下表面进行的，上表面薄膜经历刻蚀时间相对于下表面薄膜经历刻蚀时间长，图15中包括三层的第一电极1211中位于上表面的氧化铟锡层12111的尺寸会小于位于下方的氧化铟锡层12113的尺寸。此外，由于铝层12112的刻蚀速率大于氧化铟锡层12111、12113的刻蚀速率，使得出现如图15中的工字型结构(为了形成该工字型结构，可以将常用的银Ag层替换为Al层，为了使得工字型结构更加明显，可以增加Al层的厚度)。例如，铝层12112的厚度可以大于氧化铟锡层12111的厚度，铝层12112的厚度可以大于氧化铟锡层12113的厚度。例如，铝层12112的厚度与氧化铟锡层12111的厚度比大于3∶1。
在上述具有工字型结构第一电极1211的基础上，再蒸镀发光层141，蒸镀过程中发光层141的各原子的运动方向一致性较高，且运动方向相对于第一电极1211上表面的法线方向较一致，使得氧化铟锡层12111相对于铝层12112凸出的部分，会阻挡发光层141的原子进入工字型的凹形区域内，形成如图15所示的被切断的发光层141，这样会暴露出部分氧化铟锡层12113以及铝层12112的侧面。然后，可以通过溅射工艺制备阴极层，在位于氧化铟锡层12111之上的发光层141之上形成阴极131。此外，由于溅射工艺使得从靶材溅射出的阴极材料原子的运动方向和图15中铝层12112表面的法线方向相差较大，使得在上述氧化铟锡层12113的暴露部分和铝层12112的至少部分侧壁上形成阴极层(如图中虚线框所示的区域C)，这样就可以便捷地使得阴极和位于阳极层的金属线相连，提升阴极的导电能力。图15所示的结构 无需通过光刻、刻蚀等工艺制备过孔，简化了工艺，提升生产制造效率。
在某些实施例中，还可以通过对辅助阴极进行改进，以减小因引入辅助阴极对信号线中信号的干扰。
例如，的显示基板10，还包括：第一信号线1601。相应地，第一辅助电极30包括：第一主体部301和第一收窄部302。其中，第一收窄部302与第一主体部相连，第一收窄部在衬底上的正投影与第一信号线在衬底上的正投影之间存在交叠。
又例如，第二辅助电极40包括：第二主体部和第二收窄部。其中，第二收窄部与第二主体部相连，第二收窄部在衬底上的正投影与第一信号线在衬底上的正投影之间存在交叠。
图16为本公开实施例提供的第一辅助电极的示意图。
如图16所示，针对辅助阴极的线宽根据空间最大化设计，辅助阴极在与其它高频信号线交叠时，可在交叠处变窄，类似哑铃状，可降低辅助电极对栅线电容(Loading)。
图17为本公开实施例提供的第三辅助电极的示意图。
在某些实施例中，上述显示基板10还包括：第二信号线1701。相应地，第三辅助电极50可以包括：第三主体部501和第三收窄部502。其中，第三收窄部502与第三主体部501相连，第三收窄部502在衬底上的正投影与第二信号线在衬底上的正投影之间存在交叠。
如图17所示，为沿列方向延伸的位于源漏极所在层(简称SD层)的辅助阴极，与沿行方向延伸的栅线交叠处的示意图。
本公开的至少一些实施例还提供一种显示面板，上述显示面板包括如上的显示基板10。例如，上述显示面板可以是OLED显示面板。
图18为本公开实施例提供的显示面板的结构示意图。
如图18所示，该显示面板1可以包括如上所示的显示基板10。
顶发射OLED显示面板中，阴极采用透明导电材料。当电流流经阴极时，由于透明阴极本身的阻抗比较大，因而会产生比较大的压降(IR Drop)。而且，随着显示面板尺寸的增加，阴极的电压降显著增加，从而导致显示的亮度不均匀。因此，大尺寸的顶发射OLED显示面板可以采用辅助阴极，以降低阴极阻抗，满足显示所需的压降要求。
例如，OLED显示面板包括对盒的盖板和背板，参考图18所示，盖板包括衬底101以及形成在盖板衬底101上的黑矩阵102、彩膜层103、平坦层104、填充层108和隔垫物113等膜层。背板包括衬底115以及形成在衬底115上的像素界定层114、发光层110和阴极109等膜层(当然，衬底115上还形成有阳极、第一辅助阴极、第二辅助阴极、第三辅助阴极等其它结构，请参考图2～图10相关部分)，盖板和背板通过框胶107对盒在一起。
本公开实施例中，像素单元的辅助阴极与透明阴极搭接，利用现有空间设计辅助阴极，无需占用过多边框区域，同时实现给像素阴极降低电阻的目的，可有效降低VSS IR Rise的问题。
本公开实施例还提供了一种显示基板的制造方法。
图19为本公开实施例提供的显示基板的制造方法的流程图。
如图19所示，该显示基板的制造方法可以包括操作S191～操作S193。
在操作S191，提供衬底100，衬底包括多个像素单元，多个像素单元沿行方向和列方向成阵列地排布在衬底上，多个像素单元至少包括第一像素单元12，第一像素单元12包括第一发光区域121和第一非发光区域。
在操作S192，在第一非发光区域中形成扫描驱动电路。
在操作S193，在扫描驱动电路远离衬底一侧形成第一辅助电极，第一辅助电极位于第一非发光区域中第一部分区域。
其中，第一发光区域121中包括第一发光元件，第一发光元件包括第一电极1211、发光层141和第二电极，第一辅助电极30可以沿行方向或者列方向布置；扫描驱动电路包括多个子扫描驱动电路，子扫描驱动电路位于第一非发光区域中第二部分区域，子扫描驱动电路设置在衬底和第一电极1211之间；第一非发光区域中的第一部分区域和第一非发光区域中的第二部分区域在衬底上的正投影存在交叠，第一辅助电极30和第二电极电连接。例如，第一辅助电极30与第一电极1211位于同一层。
关于像素单元、发光区域、非发光区域、扫描驱动电路、发光元件、第一电极、发光层、第二电极及各自之间的位置关系等，可以参考如上相关实施例，在此不再详述。
图20为本公开实施例提供的发光元件的制造方法的流程图。
如图20所示，该第一发光元件通过操作S201～操作S204进行制备。
在操作S201，蒸镀金属层堆叠，金属层堆叠包括氧化铟锡层/铝层/氧化铟锡层。
在操作S202，基于图形化掩膜对金属层堆叠进行刻蚀，其中，氧化铟锡层的刻蚀速率小于铝层的刻蚀速率。
具体地，参考图15所示，在通过图像化过程可以形成工字型的第一电极1211(OLED的阳极)。
在操作S203，蒸镀发光层141。发光层141的厚度小于第一电极1211的厚度，发光层141会被工字型结构自动割断，同时会暴露出氧化铟锡层1113的部分表面和铝层11112的侧壁(如图15中区域C)。
在操作S204，溅射形成第二电极层，使得第二电极分别与金属层堆叠中的铝层和靠近上述衬底的氧化铟锡层相接触。
参考图15中，阴极会与区域C中的电极线相接触，使得电极线作为辅助阴极，降低阴极的电阻。
本公开的另一方面提供了一种显示装置。
图21为本公开实施例提供的显示装置的方框图。
如图21所示，该显示装置2100包括如上所示的一个或多个显示面板1。上述显示面板1包括显示区域和非显示区域，非显示区域具有较小的宽度，从而实现了窄边框的显示装置。
此外，该显示装置2100可以包括一个或多个处理器2110和计算机可读存储介质2120。
具体地，处理器2110例如可以包括通用微处理器、指令集处理器和/或相关芯片组和/或专用微处理器(例如，专用集成电路(ASIC))，等等。处理器2110还可以包括用于缓存用途的板载存储器。
计算机可读存储介质2120，例如可以是非易失性的计算机可读存储介质，具体示例包括但不限于：磁存储装置，如磁带或硬盘(HDD)；光存储装置，如光盘(CD-ROM)；存储器，如随机存取存储器(RAM)或闪存等等。
计算机可读存储介质2120可以包括程序2121，该程序2121可以包括代码/计算机可执行指令，其在由处理器2110执行时使得处理器2110进行图像显示数据处理。例如，在示例实施例中，程序2121中的代码可以包括一个或多个程序模块，例如包括程序模块2121A、程序模块2121B、……。
上述显示装置可以包括任何具有显示功能的设备或产品。例如，上述显示装置可以是智能电话、移动电话、电子书阅读器、台式电脑(PC)、膝上型PC、上网本PC、个人数字助理(PDA)、便携式多媒体播放器(PMP)、数字音频播放器、移动医疗设备、相机、可穿戴设备(例如头戴式设备、电子服饰、电子手环、电子项链、电子配饰、电子纹身、或智能手表)、电视机等。
虽然结合附图对本公开进行了说明，但是附图中公开的实施例旨在对本公开的实施例进行示例性说明，而不能理解为对本公开的一种限制。附图中的尺寸比例仅仅是示意性的，并不能理解为对本公开的限制。
上述实施例仅例示性的说明了本公开的原理及构造，而非用于限制本公开，本领域的技术人员应明白，在不偏离本公开的总体构思的情况下，对本公开所作的任何改变和改进都在本公开的范围内。本公开的保护范围，应如本公开的权利要求书所界定的范围为准。

Claims (29)

  1. 一种显示基板，包括：
    衬底；
    设置在所述衬底上的多个像素单元，所述多个像素单元沿行方向和列方向成阵列地排布在所述衬底上，所述多个像素单元至少包括第一像素单元，所述第一像素单元包括第一发光区域和第一非发光区域；
    设置在所述第一发光区域中的第一发光元件，所述第一发光元件包括第一电极、发光层和第二电极；
    设置在所述第一非发光区域的扫描驱动电路；以及
    设置在所述扫描驱动电路远离所述衬底一侧的第一辅助电极，所述第一辅助电极位于所述第一非发光区域中的第一部分区域，
    其中，所述第一辅助电极沿所述行方向或者所述列方向布置；所述扫描驱动电路包括多个子扫描驱动电路，所述子扫描驱动电路位于所述第一非发光区域中的第二部分区域；所述第一非发光区域中的所述第一部分区域和所述第一非发光区域中的第二部分区域在所述衬底上的正投影存在交叠，所述第一辅助电极和所述第二电极电连接。
  2. 根据权利要求1所述的显示基板，其中，所述第一辅助电极与所述第一电极位于同一层。
  3. 根据权利要求1所述的显示基板，其中，所述多个像素单元还包括第二像素单元，所述第二像素单元包括第二发光区域和第二非发光区域，所述第二非发光区域中未设置扫描驱动电路。
  4. 根据权利要求3所述的显示基板，还包括：
    设置在所述第二发光区域中的第二发光元件，所述第二发光元件包括：第三电极、发光层和第四电极；以及
    第二辅助电极，所述第二辅助电极位于所述第二非发光区域中的第一部分区域，
    其中，所述第二辅助电极与所述第三电极位于同一层，所述第三电极与所述第一电极位于同一层，所述第二辅助电极与所述第一辅助电极平行布置，所述第二辅助电极和所述第四电极电连接。
  5. 根据权利要求4所述的显示基板，还包括：
    设置在所述第三电极所在层的靠近所述衬底一侧的源漏极，所述源漏极位于所述第二非发光区域；以及
    第三辅助电极，所述第三辅助电极位于所述第二非发光区域中的第二部分区域，所述第三辅助电极的延伸方向与所述第二辅助电极的延伸方向在所述衬底上的正投影相接，所述源漏极和所述第二非发光区域中的第二部分区域在所述衬底上的正投影相互隔离，所述第三辅助电极与所述源漏极设置在同一层，所述第三辅助电极和所述第二辅助电极电连接。
  6. 根据权利要求5所述的显示基板，其中：
    一条第二辅助电极对应一行或多行第二像素单元；和/或
    一条第三辅助电极对应一列或多列第二像素单元。
  7. 根据权利要求5所述的显示基板，还包括：第一信号线；
    所述第一辅助电极包括：
    第一主体部；
    与所述第一主体部相连的第一收窄部，所述第一收窄部在所述衬底上的正投影与所述第一信号线在所述衬底上的正投影之间存在交叠；和/或
    所述第二辅助电极包括：
    第二主体部；
    与所述第二主体部相连的第二收窄部，所述第二收窄部在所述衬底上的正投影与所述第一信号线在所述衬底上的正投影之间存在交叠。
  8. 根据权利要求5所述的显示基板，还包括：第二信号线；
    所述第三辅助电极包括：
    第三主体部；
    与所述第三主体部相连的第三收窄部，所述第三收窄部在所述衬底上的正投影与所述第二信号线在所述衬底上的正投影之间存在交叠。
  9. 根据权利要求5所述的显示基板，还包括：
    非显示区；以及
    设置在所述非显示区的第二电极总线，所述第二电极总线用于传输参考电压信号给所述第二电极；和/或，设置在所述非显示区的第四电极总线，所述第四电极总线用于传输参考电压信号给所述第四电极。
  10. 根据权利要求9所述的显示基板，其中：
    所述第一辅助电极和所述第二辅助电极与所述第二电极总线设置在同一层，所述第一辅助电极和所述第二电极总线相连，并且所述第二辅助电极和所述第二电极总线相连；或者
    所述第三辅助电极与所述第四电极总线设置在同一层，所述第三辅助电极和所述第四电极总线相连。
  11. 根据权利要求5所述的显示基板，还包括：
    叠层设置的平坦化层和绝缘层，设置在所述第二辅助电极和所述第三辅助电极之间，所述平坦化层包括第一过孔，所述绝缘层包括第二过孔，所述第一过孔与所述第二过孔在所述衬底上的正投影存在交叠；以及
    所述第一辅助电极通过所述第一过孔和所述第二过孔与所述第二辅助电极电连接。
  12. 根据权利要求11所述的显示基板，其中，所述第一过孔和所述第二过孔是圆形过孔，所述第二过孔的直径大于所述第一过孔的直径；或者所述第一过孔和所述第二过孔是多边形过孔，所述第二过孔的面积大于所述第一过孔的面积。
  13. 根据权利要求11所述的显示基板，还包括：
    设置在所述第二电极和所述第一辅助电极之间的像素界定层，所述像素界定层包括第三过孔，所述第一辅助电极通过所述第一过孔和所述第二电极电连接；或者
    设置在所述第四电极和所述第二辅助电极之间的像素界定层，所述像素界定层包括第三过孔，所述第二辅助电极通过所述第三过孔和所述第四电极电连接。
  14. 根据权利要求13所述的显示基板，其中，所述第一过孔是多边形过孔，所述第三过孔是条形过孔，所述条形过孔的面积大于所述第一过孔的面积。
  15. 根据权利要求13所述的显示基板，其中，所述第一过孔与所述第三过孔在所述衬底上的正投影相互间隔。
  16. 根据权利要求13所述的显示基板，其中：
    所述像素界定层在所述衬底上的正投影覆盖所述第一非发光区域；和/或
    所述像素界定层在所述衬底上的正投影覆盖所述第二非发光区域。
  17. 根据权利要求1至16任一项所述的显示基板，其中：
    一条第一辅助电极对应一行或多行第一像素单元。
  18. 根据权利要求1至16任一项所述的显示基板，其中：
    一个子扫描驱动电路对应一列或多列第一像素单元。
  19. 根据权利要求1至16任一项所述的显示基板，其中，所述显示基板的形状包括方形、长方形、多边形和具有弧线边界的形状中任意一种。
  20. 根据权利要求1至16任一项所述的显示基板，其中，对于具有心形边界的显示基板，多个像素单元分别位于不同的显示区，每个显示区具有独享的子扫描驱动电路。
  21. 根据权利要求20所述的显示基板，其中，所述具有心形边界的显示基板包括心形尖部的显示区、心形头部的两个对称显示区，所述子扫描驱动电路沿所述列方向设置。
  22. 根据权利要求1至16任一项所述的显示基板，其中，所述第一电极包括多层金属结构，所述多层金属结构的横截面为工字型。
  23. 根据权利要求22所述的显示基板，其中，所述第一电极包括堆叠的氧化铟锡层/铝层/氧化铟锡层。
  24. 根据权利要求1至16任一项所述的显示基板，其中，所述第一非发光区域是L型区域。
  25. 根据权利要求1至16任一项所述的显示基板，其中，所述发光层包括有机发光二极管，所述第一电极和所述第三电极为所述有机发光二极管的阳极，所述第二电极和所述第四电极为所述有机发光二极管的阴极；以及
    所述扫描驱动电路包括栅驱动电路。
  26. 根据权利要求25所述的显示基板，其中，所述阴极包括的材料为透明导电材料，所述阳极包括的材料为金属材料。
  27. 一种显示面板，包括如权利要求1～26任一项所述的显示基板。
  28. 一种显示基板的制造方法，包括：
    提供衬底，所述衬底包括多个像素单元，所述多个像素单元沿行方向和列方向成阵列地排布在所述衬底上，所述多个像素单元至少包括第一像素单元，所述第一像素单元包括第一发光区域和第一非发光区域；
    在所述第一非发光区域中形成扫描驱动电路；以及
    在所述扫描驱动电路远离所述衬底一侧形成第一辅助电极，所述第一辅助电极位于所述第一非发光区域中第一部分区域，
    其中，所述第一发光区域中包括第一发光元件，所述第一发光元件包括第一电极、发光层和第二电极，所述第一辅助电极沿所述行方向或者所述列方向布置；所述扫描驱动电路包括多个子扫描驱动电路，所述子扫描驱动电路位于所述第一非发光区域中第二部分区域，所述子扫描驱动电路设置在所述衬底和所述第一电极之间；所述第一非发光区域中的第一部分区域和所述第一非发光区域中的第二部分区域在所述衬底上的正投影存在交叠，所述第一辅助电极和所述第二电极电连接。
  29. 根据权利要求28所述的方法，其中，所述第一发光元件通过如下方式进行制备：
    蒸镀金属层堆叠，所述金属层堆叠包括氧化铟锡层/铝层/氧化铟锡层；
    基于图形化掩膜对所述金属层堆叠进行刻蚀，其中，所述氧化铟锡层的刻蚀速率小于所述铝层的刻蚀速率；
    蒸镀发光层；以及
    溅射形成第二电极层，使得第二电极分别与所述金属层堆叠中的所述铝层和靠近所述衬底的氧化铟锡层相接触。
PCT/CN2021/090437 2021-04-28 2021-04-28 显示基板、显示面板和显示基板制造方法 Ceased WO2022226818A1 (zh)

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