WO2022227136A1 - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

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Publication number
WO2022227136A1
WO2022227136A1 PCT/CN2021/094410 CN2021094410W WO2022227136A1 WO 2022227136 A1 WO2022227136 A1 WO 2022227136A1 CN 2021094410 W CN2021094410 W CN 2021094410W WO 2022227136 A1 WO2022227136 A1 WO 2022227136A1
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WIPO (PCT)
Prior art keywords
transistor
electrode
electrode plate
array substrate
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/094410
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English (en)
French (fr)
Inventor
陆志涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to EP21730451.8A priority Critical patent/EP4332668A4/en
Priority to KR1020217020078A priority patent/KR102473484B1/ko
Priority to JP2021529050A priority patent/JP7372969B2/ja
Priority to US17/297,562 priority patent/US20240194699A1/en
Publication of WO2022227136A1 publication Critical patent/WO2022227136A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/103—Integrated devices the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F1/13318—Circuits comprising a photodetector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • the light control sensor mainly includes photosensitive thin film transistor (Thin Film Transistor, TFT), storage capacitor, etc.
  • TFT Thin Film Transistor
  • the photosensitive thin film transistor generates photocurrent after being exposed to light
  • the storage capacitor is used to temporarily store the amount of electricity generated by the photosensitive thin film transistor after being exposed to light.
  • the size of the storage capacitor needs to match the changed power, and in order to match the power, the area of the storage capacitor needs to be larger.
  • a larger storage capacitor occupies a larger display area, which reduces the aperture ratio of the display panel.
  • the present application provides an array substrate and a display panel to alleviate the technical problem of low aperture ratio of the existing display panel.
  • An embodiment of the present application provides an array substrate, which includes a base substrate and a pixel circuit disposed on the base substrate, the pixel circuit includes a driving circuit and a photosensitive circuit, and the photosensitive circuit includes a first transistor, a second Two transistors and a first capacitor;
  • the gate of the first transistor is connected to the first control signal line, the first electrode of the first transistor is connected to the first power supply line, and the second electrode of the first transistor is connected to the first power line of the second transistor pole connection;
  • the first capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate Connect with the public voltage signal line;
  • the first electrode plate and the second electrode plate are both transparent electrode plates, and the driving circuit and the photosensitive circuit share the common voltage signal line.
  • the photosensitive circuit further includes a readout circuit, the second electrode of the second transistor is connected to the readout circuit, and the gate of the second transistor is connected to the second electrode of the second transistor. Control signal line connection.
  • the array substrate further includes a photosensitive unit, the photosensitive circuit is arranged in the photosensitive unit, wherein the first transistor and the second transistor are arranged in the same layer , the first capacitor is disposed on a side of the first transistor and the second transistor away from the base substrate.
  • the array substrate further includes:
  • a first inorganic layer disposed on a side of the first transistor and the second transistor away from the base substrate;
  • the second inorganic layer is disposed on the side of the first inorganic layer away from the first transistor, and is located between the first electrode plate and the second electrode plate.
  • the array substrate further includes a display unit, the driving circuit is disposed in the display unit, and the display unit includes:
  • a third transistor arranged in the same layer as the first transistor
  • a pixel electrode arranged in the same layer as the first electrode plate or the second electrode plate;
  • the common electrode is reused as the second electrode plate.
  • the first electrode plate is disposed on the first inorganic layer
  • the second electrode plate is disposed on the second inorganic layer.
  • the second electrode plate is disposed on the first inorganic layer, and the first electrode plate is disposed on the second inorganic layer.
  • the materials of the first electrode plate, the common electrode and the pixel electrode are the same.
  • the array substrate further includes a display unit, the driving circuit is disposed in the display unit, and the display unit includes:
  • a third transistor arranged in the same layer as the first transistor
  • a pixel electrode disposed above the third transistor and electrically connected to the third transistor
  • the common electrode is reused as the second plate
  • the pixel electrode is arranged in a different layer from the first electrode plate and the second electrode plate.
  • the common voltage signal line and the gate electrode of the first transistor are provided in the same layer.
  • Embodiments of the present application further provide a display panel, which includes an array substrate, the array substrate includes a base substrate, and a pixel circuit disposed on the base substrate, the pixel circuit includes a driving circuit and a photosensitive circuit, and the The photosensitive circuit includes a first transistor, a second transistor and a first capacitor; wherein:
  • the gate of the first transistor is connected to the first control signal line, the first electrode of the first transistor is connected to the first power supply line, and the second electrode of the first transistor is connected to the first power line of the second transistor pole connection;
  • the first capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate Connect with the public voltage signal line;
  • the first electrode plate and the second electrode plate are both transparent electrode plates, and the driving circuit and the photosensitive circuit share the common voltage signal line.
  • the photosensitive circuit further includes a readout circuit, the second pole of the second transistor is connected to the readout circuit, and the gate of the second transistor is connected to the second Control signal line connection.
  • the array substrate further includes a photosensitive unit, the photosensitive circuit is arranged in the photosensitive unit, wherein the first transistor and the second transistor are arranged in the same layer , the first capacitor is disposed on a side of the first transistor and the second transistor away from the base substrate.
  • the array substrate further includes:
  • a first inorganic layer disposed on a side of the first transistor and the second transistor away from the base substrate;
  • the second inorganic layer is disposed on the side of the first inorganic layer away from the first transistor, and is located between the first electrode plate and the second electrode plate.
  • the array substrate further includes a display unit, the driving circuit is disposed in the display unit, and the display unit includes:
  • a third transistor arranged in the same layer as the first transistor
  • a pixel electrode arranged in the same layer as the first electrode plate or the second electrode plate;
  • the common electrode is reused as the second plate
  • the display panel is divided into a display stage and a light-sensing stage within a frame time, the display unit is used for working in the display stage, and the light-sensing unit is used for working in the light sensing stage.
  • the first electrode plate is disposed on the first inorganic layer
  • the second electrode plate is disposed on the second inorganic layer.
  • the second electrode plate is disposed on the first inorganic layer, and the first electrode plate is disposed on the second inorganic layer.
  • the materials of the first electrode plate, the common electrode and the pixel electrode are the same.
  • the array substrate further includes a display unit, the driving circuit is disposed in the display unit, and the display unit includes:
  • a third transistor arranged in the same layer as the first transistor
  • a pixel electrode disposed above the third transistor and electrically connected to the third transistor
  • the common electrode is reused as the second plate
  • the pixel electrode is arranged in a different layer from the first electrode plate and the second electrode plate.
  • the common voltage signal line and the gate electrode of the first transistor are arranged in the same layer.
  • the first electrode plate and the second electrode plate of the first capacitor in the array substrate and the display panel provided by the present application are both transparent electrode plates, the first electrode plate is formed by the newly added transparent conductive film layer, and the second electrode plate is formed by the display unit.
  • the common electrodes are multiplexed, and the display unit and the photosensitive unit work alternately in a time-sharing manner within a frame time, so that the first capacitor can transmit light, will not occupy additional display area, and will not affect the display panel display, improving the display.
  • the aperture ratio and display effect of the panel since the electrode plate of the first capacitor is a transparent electrode plate, it can be arranged in the display area without affecting the display, so a larger area of the first capacitor can be arranged, which improves the light sensing effect.
  • FIG. 1 is a schematic diagram of a frame structure of a pixel circuit provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a circuit structure of a photosensitive circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of a first film layer structure of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of a second film layer structure of the array substrate provided by the embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional view of a third film layer structure of the array substrate provided by the embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • FIG. 7 is a schematic time sequence diagram of time division multiplexing of a display panel according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a frame structure of a pixel circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of a circuit structure of a photosensitive circuit provided by an embodiment of the present application
  • FIG. 3 is provided by an embodiment of the present application.
  • the array substrate 100 includes a base substrate 10 and a pixel circuit PC disposed on the base substrate 10.
  • the pixel circuit PC includes a driving circuit DC and a photosensitive circuit LC.
  • the array substrate 100 further includes a display unit 20 and a photosensitive unit 30 disposed on the base substrate 10 , and the driving circuit DC is disposed in the display unit 20 for driving the pixels in the display unit 20
  • the light-sensing circuit LC is disposed in the light-sensing unit 30, and is used to enable the light-sensing unit 30 to realize functions such as touch control, fingerprint recognition, and long-distance optical interaction by sensing the change of light intensity.
  • the light sensing circuit LC includes a first transistor T1, a second transistor T2 and a first capacitor C1.
  • the gate M1 of the first transistor T1 is connected to the first control signal line SVGG
  • the first pole S1 of the first transistor T1 is connected to the first power supply line SVDD
  • the second pole D1 of the first transistor T1 is connected to the first power supply line SVDD.
  • the first pole S2 of the second transistor T2 is connected.
  • the first capacitor C1 includes a first electrode plate 11 and a second electrode plate 12, the first electrode plate 11 is connected with the second electrode D1 of the first transistor T1 and the first electrode S2 of the second transistor T2. connection, the second electrode plate 12 is connected to the common voltage signal line Vcom.
  • the first electrode plate 11 and the second electrode plate 12 are both transparent electrode plates, and the driving circuit DC and the photosensitive circuit LC share the common voltage signal line Vcom.
  • the photosensitive circuit LC further includes a readout circuit, the second pole D2 of the second transistor T2 is connected to the readout circuit, and the gate M2 of the second transistor T2 is connected to the second control signal line Gate connection.
  • the readout circuit includes an operational amplifier FD, a second capacitor C2, and a first switch Sr
  • the operational amplifier FD includes an inverting input terminal, a non-inverting input terminal, and an output terminal (as shown in the operational amplifier FD in FIG. 2 ).
  • the "-" marked in the symbol represents the inverting input terminal, and “+” represents the non-inverting input terminal)
  • the non-inverting input terminal is connected to the comparison voltage Vref
  • the inverting input terminal is connected to the second pole D2 of the second transistor T2.
  • Both the second capacitor C2 and the first switch Sr are connected in parallel with the operational amplifier FD.
  • one end of the second capacitor C2 and one end of the first switch Sr are both connected to the operational amplifier FD.
  • the other end of the second capacitor C2 and the other end of the first switch Sr are both connected to the output end of the operational amplifier FD.
  • the output end of the operational amplifier FD is also connected to a readout line Readout, and the readout line Readout is used to output a light sensing signal.
  • the first electrode of the transistor in the present application may be the source electrode of the transistor, and the second electrode of the transistor may be the drain electrode of the transistor.
  • the first electrode S1 of the first transistor T1 is the first electrode
  • the source of the transistor T1 and the second electrode D1 of the first transistor T1 are the drain of the first transistor T1, but the present application is not limited to this.
  • the first capacitor C1 in this application is a storage capacitor
  • the second capacitor C2 is an integrating capacitor
  • the first transistor T1 is a phototransistor
  • the second transistor T2 is a switching transistor.
  • the working process of the photosensitive circuit LC includes: the first control signal line SVGG provides a voltage to the gate M1 of the first transistor T1, so that the first electrode S1 of the first transistor T1 and the The second electrode D1 of the first transistor T1 is turned on, and the channel of the first transistor T1 is irradiated with light to generate a photo-generated leakage current, and different levels of leakage current are generated according to the intensity of the light.
  • the electrical signal of the first power supply line SVDD flows from the first electrode S1 of the first transistor T1 to the second electrode D1, and reaches the first electrode plate 11 of the first capacitor C1.
  • the photo-generated leakage current generated by T1 changes.
  • the second electrode plate 12 of the first capacitor C1 is connected to the common voltage signal line Vcom. At this time, the first capacitor C1 is in a charging state, and the charged electrical signal includes light-sensing information.
  • the first plate 11 of the first capacitor C1 is also connected to the first electrode S2 of the second transistor T2.
  • the second control signal line Gate provides a voltage to the gate M2 of the second transistor T2
  • the charge stored in the first capacitor C1 flows to the second transistor T2 through the first pole S2 of the second transistor T2 the second pole D2, so that the first capacitor C1 is discharged through the second transistor T2.
  • the second pole D2 of the second transistor T2 is connected to the readout circuit, and the readout circuit receives the electric charge from the second pole D2 of the second transistor T2 and converts the electric charge into a voltage signal for output.
  • the array substrate 100 includes a display unit 20 and a photosensitive unit 30 , the first transistor T1 and the second transistor T2 of the photosensitive unit 30 are provided in the same layer, and the first capacitor C1 is provided on the side of the first transistor T1 and the second transistor T2 away from the base substrate 10 .
  • the display unit 20 includes a third transistor T3, a pixel electrode 13 and a common electrode 14.
  • the third transistor T3 is arranged in the same layer as the first transistor T1 and the second transistor T2, and the pixel electrode 13 is arranged at the same layer.
  • the second electrode plate 12 that is, the pixel electrode 13 and the second electrode plate 12 of the first capacitor C1 are disposed in the same layer.
  • the base substrate 10 may be a rigid substrate or a flexible substrate; when the base substrate 10 is a rigid substrate, it may include a rigid substrate such as a glass substrate; when the base substrate 10 is a flexible substrate, it may include Flexible substrates such as polyimide (PI) films and ultra-thin glass films.
  • PI polyimide
  • the first transistor T1 , the second transistor T2 and the third transistor T3 are arranged in the same layer as the first transistor T1 , the second transistor T2 and the third transistor T3
  • the film layer formed of the same material is patterned to obtain at least two different features.
  • the pixel electrode 13 and the common electrode 14 are obtained by patterning the same transparent conductive layer, and the pixel electrode 13 and the common electrode 14 are provided in the same layer.
  • the array substrate 100 includes a first metal layer, a gate insulating layer 40 , a semiconductor layer and a second metal layer that are stacked on the base substrate 10 in sequence.
  • the patterning of the first metal layer forms the gate M1 of the first transistor T1, the gate M2 of the second transistor T2, the gate M3 of the third transistor T3 and the common voltage signal line Vcom; pattern;
  • the semiconductor layer is formed to form the active layer 21 of the first transistor T1, the active layer 22 of the second transistor T2 and the active layer 23 of the third transistor T3; pattern the second metal layer forming the first pole S1 and the second pole D1 of the first transistor T1, the first pole S2 and the second pole D2 of the second transistor T2, and the first pole S3 and the second pole of the third transistor T3 D3 and a connecting wire 24 for connecting the second pole D1 of the first transistor T1 and the first pole S2 of the second transistor T2.
  • the semiconductor layer and the second metal layer can be subjected to a yellow light process through the same mask to simultaneously form structures such as the first electrode, the second electrode, the connection wiring and the active layer pattern of the transistor.
  • the semiconductor layer and the second metal layer are sequentially stacked and deposited on the gate insulating layer, and then a half-tone mask is used.
  • mask, HTM) or grayscale tone mask (Gray Tone Mask, GTM) performs a yellow light process on the semiconductor layer and the second metal layer, and forms the required pattern structure through multiple exposures, development, etching and other processes.
  • the first electrode S1 and the second electrode D1 of the first transistor T1 are in direct contact with the active layer 21 of the first transistor T1, and between the first electrode S1 and the second electrode D2 of the first transistor T1 There is an interval, and the portion of the active layer 21 corresponding to the interval is the channel of the first transistor T1.
  • the first electrode S2 and the second electrode D2 of the second transistor T2 are in direct contact with the active layer 22 of the second transistor T2, and between the first electrode S2 and the second electrode D2 of the second transistor T2 There is an interval, and the portion of the active layer 22 corresponding to the interval is the channel of the second transistor T2.
  • the first electrode S3 and the second electrode D3 of the third transistor T3 are in direct contact with the active layer 23 of the third transistor T3, and between the first electrode S3 and the second electrode D3 of the third transistor T3 There is an interval, and the portion of the active layer 23 corresponding to the interval is the channel of the third transistor T3.
  • an ohmic contact layer may also be provided at the portion where the first electrode and the second electrode of the transistor are in contact with the active layer, so as to reduce the resistance.
  • the array substrate 100 further includes a first inorganic layer 50 and a second inorganic layer 60 , and the first inorganic layer 50 is disposed on the first transistor T1 and the second transistor T2 away from the base substrate 10 ; the second inorganic layer 60 is disposed on the side of the first inorganic layer 50 away from the first transistor T1 and between the first electrode plate 11 and the second electrode plate 12 .
  • the first inorganic layer 50 covers the first electrode S1 and the second electrode D1 of the first transistor T1 and the first electrode S2 and the second electrode D2 of the second transistor T2, and covers the first electrode S1 and the second electrode D1 of the second transistor T2 on the gate insulating layer 40 .
  • the first inorganic layer 50 is patterned to form first openings, and the first openings penetrate through the first inorganic layer 50 to the connection wires 24 so as to expose part of the connection wires 24 .
  • the material of the first inorganic layer 50 includes inorganic substances such as silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNO).
  • the first electrode plate 11 of the first capacitor C1 is disposed on the first inorganic layer 50
  • the second electrode plate 12 of the first capacitor C1 is disposed on the second inorganic layer 60
  • a first transparent conductive layer is disposed on the first inorganic layer 50
  • the first transparent conductive layer is patterned to form the first electrode plate 11 of the first capacitor C1
  • the first electrode plate 11 passes through the first electrode plate 11
  • the first via hole of the first inorganic layer 50 is connected to the connection trace, that is, the first electrode plate 11 is connected to the second electrode D1 of the first transistor T1 and the second electrode D1 of the second transistor T2.
  • the material of the first transparent conductive layer includes transparent conductive materials such as indium tin oxide (Indium Tin Oxide, ITO).
  • the second inorganic layer 60 covers the first electrode plate 11 and the first inorganic layer 50 .
  • the second inorganic layer 60 is patterned to form second openings and third openings. Two openings penetrate through the second inorganic layer 60 , the first inorganic layer 50 and the gate insulating layer 40 to the common voltage signal line Vcom to expose part of the common voltage signal line Vcom.
  • the third opening penetrates the second inorganic layer 60 and the first inorganic layer 50 to the second electrode D3 of the third transistor T3 to expose part of the second electrode D3 of the third transistor T3 .
  • the material of the first inorganic layer 50 includes inorganic substances such as silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNO).
  • a second transparent conductive layer is disposed on the second inorganic layer 60 , and the second transparent conductive layer is patterned to form the pixel electrode 13 and the common electrode 14 of the display unit 20 , and the common electrode 14 passes through
  • the second via hole is connected to the common voltage signal line Vcom, and the common electrode 14 is multiplexed as the second plate 12 of the first capacitor C1, wherein the common voltage signal line Vcom provides a constant stable voltage. voltage signal.
  • the pixel electrode 13 is connected to the second electrode D3 of the third transistor T3 through the third via hole.
  • the material of the second transparent conductive layer includes indium tin oxide (Indium Tin Oxide, ITO) and other transparent conductive materials.
  • a separate transparent conductive film is added on the array substrate 100 as the first electrode plate 11 of the first capacitor C1 of the photosensitive unit 30 , and the common electrode of the display unit 20 is 14 is multiplexed as the second plate 12 of the first capacitor C1, so that the first capacitor C1 can transmit light without additionally occupying the area of the display area, and will not affect the normal display of the display panel using the array substrate 100 , which improves the aperture ratio and display effect of the display panel.
  • the electrode plate of the first capacitor C1 is a transparent electrode plate, it can be arranged in the display area without affecting the display, so a larger area of the first capacitor C1 can be arranged to improve the light sensing effect.
  • FIG. 4 is a schematic diagram of a second cross-sectional structure of an array substrate provided by an embodiment of the present application.
  • the second electrode plate 12 of the first capacitor C1 is disposed on the first inorganic layer 50, and the The first electrode plate 11 is disposed on the second inorganic layer 60 .
  • the pixel electrode 13 of the display unit 20 and the first electrode plate 11 of the first capacitor C1 are disposed in the same layer, and the common electrode 14 is multiplexed as the second electrode plate 12 of the first capacitor C1.
  • the second electrode plate 12 is connected to the common voltage signal line Vcom through the via hole of the first inorganic layer 50
  • the first electrode plate 11 is connected to the common voltage signal line Vcom through the via hole of the second inorganic layer 60
  • the connection line 24 is connected
  • the pixel electrode 13 is connected to the second electrode D3 of the third transistor T3 through another via hole of the second inorganic layer 60 .
  • FIG. 5 is a schematic diagram of a third cross-sectional structure of the array substrate provided by the embodiment of the present application.
  • the pixel electrode 13 and the common electrode 14 are arranged in different layers, and the common electrode 14 is multiplexed as the first capacitor The second plate 12 of C1.
  • the array substrate 100 further includes a third inorganic layer 70 , the first electrode plate 11 of the first capacitor C1 is disposed on the first inorganic layer 50 , and the common electrode 14 is disposed on the second inorganic layer 50 .
  • the pixel electrode 13 is disposed on the third inorganic layer 70 , and the material of the third inorganic layer 70 may be the same as the material of the first inorganic material and/or the second inorganic layer 60 same.
  • the common electrode 14 can be set as a whole surface electrode, so that more pixel electrodes 13 can be set to improve the resolution.
  • An embodiment of the present application further provides a display panel, the display panel includes the array substrate of one of the above-mentioned embodiments, wherein the display panel is divided into a display stage and a light-sensing stage within a frame time, and the display unit 20 is used for The display stage works, and the light sensing unit 30 is used for working in the light sensing stage.
  • FIG. 6 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application
  • FIG. 7 is a timing sequence of time-division multiplexing of a display panel provided by an embodiment of the present application.
  • the display panel 1000 is a Liquid Crystal Display (LCD) panel, and the display panel 1000 includes an array substrate 100 , a color filter substrate 200 disposed opposite to the array substrate 100 , and a color filter substrate 200 disposed on the array substrate 100 and the array substrate 100 .
  • the liquid crystal layer 300 between the color filter substrates 200 is described.
  • the display panel 1000 including the array substrate 100 can realize functions such as touch control, fingerprint recognition, and long-distance optical interaction, and at the same time integrate the light sensing unit 30 into the In the display panel 1000, the overall thickness of the display panel 1000 can also be reduced.
  • the photosensitive unit 30 and the display unit 20 are integrated on the array substrate 100.
  • the photosensitive unit 30 and the display unit 20 can work alternately in time-sharing .
  • the display panel 1000 is divided into a display stage DD and a photosensitive stage SD.
  • the gate scanning lines sequentially provide scanning signals (G1 in FIG. 7 ). to Gn-2, Gn-1, Gn) to control the transistors of the display unit 20 to be turned on and off to realize the display function of the display panel 1000; in the photosensitive stage SD, the gate scanning line stops scanning, as G1 to Gn-2, Gn-1, and Gn in FIG.
  • Stage 7 are all set to low level in the light-sensing stage DD, so as to turn off the display function of the display panel 1000, so that the light-sensing unit 30 is in the light-sensing stage DD.
  • Stage SD work.
  • the display unit 20 and the photosensitive unit 30 of the display panel 1000 are operated alternately in time-sharing, so that the display panel 1000 can realize the touch control, fingerprint recognition, and long-distance optics of the display panel 1000 without affecting the normal display of the display panel 1000. interaction, etc.
  • An embodiment of the present application further provides a display device, which includes the display panel of one of the foregoing embodiments, a device such as a circuit board bound to the display panel, and a cover plate covering the display panel.
  • the display device includes electronic equipment such as a mobile phone, a TV, and a notebook computer.
  • the present application provides an array substrate and a display panel
  • the array substrate includes a display unit and a photosensitive unit
  • the photosensitive unit includes a first transistor, a second transistor and a first capacitor, the first transistor and the second transistor are arranged in the same layer, and the A capacitor is located above the first transistor and the second transistor;
  • the first electrode plate and the second electrode plate of the first capacitor are both transparent electrode plates, the first electrode plate is formed by a newly added transparent conductive film layer, and the second electrode plate is made of
  • the common electrodes of the display unit are multiplexed, and the display unit and the photosensitive unit work alternately in a time-sharing manner within a frame time, so that the first capacitor can transmit light without additionally occupying the display area, and it will not affect the display panel display.
  • the electrode plate of the first capacitor is a transparent electrode plate, it can be arranged in the display area without affecting the display, so a larger area of the first capacitor can be arranged, which improves the light sensing effect.

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Abstract

本申请提供一种阵列基板和显示面板；该阵列基板包括显示单元和光感单元，光感单元的第一电容的第一极板和第二极板均为透明电极板，第一极板由新增的透明导电膜层形成，第二极板由显示单元的公共电极复用，且在一帧时间内显示单元和光感单元分时交替工作，以缓解现有显示面板存在的开口率低的问题。

Description

阵列基板和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板和显示面板。
 背景技术
随着显示技术的发展，通过把光控传感器集成到显示面板中，并以激光作为操控源的远程交互技术被人们所关注。光控传感器主要包括光感薄膜晶体管（Thin Film Transistor，TFT）、存储电容等，光感薄膜晶体管感光后产生光电流，储存电容用于暂存光感薄膜晶体管感光后产生光电流的电量。其中存储电容的大小需要与这个改变的电量相匹配，而为了匹配这个电量，存储电容的面积需要做的比较大。同时由于存储电容的不透光性，导致较大的存储电容占用较大的显示面积，使显示面板的开口率降低。
因此，现有显示面板存在的开口率低的技术问题需要解决。
 技术问题
本申请提供一种阵列基板和显示面板，以缓解现有显示面板存在的开口率低的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种阵列基板，其包括衬底基板以及设置于所述衬底基板上的像素电路，所述像素电路包括驱动电路和光感电路，所述光感电路包括第一晶体管、第二晶体管和第一电容；其中：
所述第一晶体管的栅极与第一控制信号线连接，所述第一晶体管的第一极与第一电源线连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
所述第一电容包括第一极板和第二极板，所述第一极板与所述第一晶体管的第二极和所述第二晶体管的第一极连接，所述第二极板与公共电压信号线连接；
其中，所述第一极板和所述第二极板均为透明电极板，所述驱动电路和所述光感电路共用所述公共电压信号线。
在本申请实施例提供的阵列基板中，所述光感电路还包括读出电路，所述第二晶体管的第二极与所述读出电路连接，所述第二晶体管的栅极与第二控制信号线连接。
在本申请实施例提供的阵列基板中，所述阵列基板还包括光感单元，所述光感电路设置于所述光感单元内，其中所述第一晶体管和所述第二晶体管同层设置，所述第一电容设置于所述第一晶体管和所述第二晶体管远离所述衬底基板的一侧。
在本申请实施例提供的阵列基板中，所述阵列基板还包括：
第一无机层，设置于所述第一晶体管和所述第二晶体管远离所述衬底基板的一侧；
第二无机层，设置于所述第一无机层远离所述第一晶体管的一侧，且位于所述第一极板和所述第二极板之间。
在本申请实施例提供的阵列基板中，所述阵列基板还包括显示单元，所述驱动电路设置于所述显示单元内，所述显示单元包括：
第三晶体管，与所述第一晶体管同层设置；
像素电极，与所述第一极板或所述第二极板同层设置；
公共电极，复用为所述第二极板。
在本申请实施例提供的阵列基板中，所述第一极板设置于所述第一无机层上，所述第二极板设置于所述第二无机层上。
在本申请实施例提供的阵列基板中，所述第二极板设置于所述第一无机层上，所述第一极板设置于所述第二无机层上。
在本申请实施例提供的阵列基板中，所述第一极板、所述公共电极以及所述像素电极的材料相同。
在本申请实施例提供的阵列基板中，所述阵列基板还包括显示单元，所述驱动电路设置于所述显示单元内，所述显示单元包括：
第三晶体管，与所述第一晶体管同层设置；
像素电极，设置于所述第三晶体管上方，且与所述第三晶体管电连接；
公共电极，复用为所述第二极板；
其中，所述像素电极与所述第一极板和所述第二极板不同层设置。
在本申请实施例提供的阵列基板中，所述公共电压信号线与所述第一晶体管的栅极同层设置。
本申请实施例还提供一种显示面板，其包括阵列基板，所述阵列基板包括衬底基板以及设置于所述衬底基板上的像素电路，所述像素电路包括驱动电路和光感电路，所述光感电路包括第一晶体管、第二晶体管和第一电容；其中：
所述第一晶体管的栅极与第一控制信号线连接，所述第一晶体管的第一极与第一电源线连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
所述第一电容包括第一极板和第二极板，所述第一极板与所述第一晶体管的第二极和所述第二晶体管的第一极连接，所述第二极板与公共电压信号线连接；
其中，所述第一极板和所述第二极板均为透明电极板，所述驱动电路和所述光感电路共用所述公共电压信号线。
在本申请实施例提供的显示面板中，所述光感电路还包括读出电路，所述第二晶体管的第二极与所述读出电路连接，所述第二晶体管的栅极与第二控制信号线连接。
在本申请实施例提供的显示面板中，所述阵列基板还包括光感单元，所述光感电路设置于所述光感单元内，其中所述第一晶体管和所述第二晶体管同层设置，所述第一电容设置于所述第一晶体管和所述第二晶体管远离所述衬底基板的一侧。
在本申请实施例提供的显示面板中，所述阵列基板还包括：
第一无机层，设置于所述第一晶体管和所述第二晶体管远离所述衬底基板的一侧；
第二无机层，设置于所述第一无机层远离所述第一晶体管的一侧，且位于所述第一极板和所述第二极板之间。
在本申请实施例提供的显示面板中，所述阵列基板还包括显示单元，所述驱动电路设置于所述显示单元内，所述显示单元包括：
第三晶体管，与所述第一晶体管同层设置；
像素电极，与所述第一极板或所述第二极板同层设置；
公共电极，复用为所述第二极板；
其中所述显示面板在一帧时间内分为显示阶段和光感阶段，所述显示单元用于在所述显示阶段工作，所述光感单元用于在所述光感阶段工作。
在本申请实施例提供的显示面板中，所述第一极板设置于所述第一无机层上，所述第二极板设置于所述第二无机层上。
在本申请实施例提供的显示面板中，所述第二极板设置于所述第一无机层上，所述第一极板设置于所述第二无机层上。
在本申请实施例提供的显示面板中，所述第一极板、所述公共电极以及所述像素电极的材料相同。
在本申请实施例提供的显示面板中，所述阵列基板还包括显示单元，所述驱动电路设置于所述显示单元内，所述显示单元包括：
第三晶体管，与所述第一晶体管同层设置；
像素电极，设置于所述第三晶体管上方，且与所述第三晶体管电连接；
公共电极，复用为所述第二极板；
其中，所述像素电极与所述第一极板和所述第二极板不同层设置。
在本申请实施例提供的显示面板中，所述公共电压信号线与所述第一晶体管的栅极同层设置。
 有益效果
本申请提供的阵列基板和显示面板中第一电容的第一极板和第二极板均为透明电极板，第一极板由新增的透明导电膜层形成，第二极板由显示单元的公共电极复用，且在一帧时间内显示单元和光感单元分时交替工作，如此使得第一电容能够透光，不会额外占用显示区面积，还不会影响显示面板显示，提高了显示面板的开口率和显示效果。同时由于第一电容的极板为透明电极板，可以设置于显示区且不会影响显示，因此可以设置较大面积的第一电容，提高了光感效果。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素电路的框架结构示意图。
图2为本申请实施例提供的光感电路的电路结构示意图。
图3为本申请实施例提供的阵列基板的第一种膜层结构剖面示意图。
图4为本申请实施例提供的阵列基板的第二种膜层结构剖面示意图。
图5为本申请实施例提供的阵列基板的第三种膜层结构剖面示意图。
图6为本申请实施例提供的显示面板的一种剖面结构示意图。
图7为本申请实施例提供的显示面板分时多工的时序示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
请结合参照图1至图3，图1为本申请实施例提供的像素电路的框架结构示意图，图2为本申请实施例提供的光感电路的电路结构示意图，图3为本申请实施例提供的阵列基板的第一种膜层结构剖面示意图。所述阵列基板100包括衬底基板10以及设置于所述衬底基板10上像素电路PC，所述像素电路PC包括驱动电路DC和光感电路LC。所述阵列基板100还包括设置于所述衬底基板10上的显示单元20和光感单元30，所述驱动电路DC设置于所述显示单元20内，用于驱动所述显示单元20内的像素进行显示，所述光感电路LC设置于所述光感单元30内，用于通过感测光强的变化使所述光感单元30实现触控、指纹识别、远距离光学交互等功能。
可选地，所述光感电路LC包括第一晶体管T1、第二晶体管T2和第一电容C1。所述第一晶体管T1的栅极M1与第一控制信号线SVGG连接，所述第一晶体管T1的第一极S1与第一电源线SVDD连接，所述第一晶体管T1的第二极D1与所述第二晶体管T2的第一极S2连接。所述第一电容C1包括第一极板11和第二极板12，所述第一极板11与所述第一晶体管T1的第二极D1和所述第二晶体管T2的第一极S2连接，所述第二极板12与公共电压信号线Vcom连接。其中，所述第一极板11和所述第二极板12均为透明电极板，所述驱动电路DC和所述光感电路LC共用所述公共电压信号线Vcom。
进一步地，所述光感电路LC还包括读出电路，所述第二晶体管T2的第二极D2与所述读出电路连接，所述第二晶体管T2的栅极M2与第二控制信号线Gate连接。
可选地，所述读出电路包括运算放大器FD、第二电容C2、第一开关Sr，所述运算放大器FD包括反相输入端、同相输入端以及输出端（如图2中的运算放大器FD中标示的“-”表示反相输入端，“+”表示同相输入端），所述同相输入端连接比较电压Vref，所述反相输入端连接所述第二晶体管T2的第二极D2。所述第二电容C2和所述第一开关Sr均与所述运算放大器FD并联连接，具体地，所述第二电容C2的一端和所述第一开关Sr的一端均与所述运算放大器FD的反相输入端连接，所述第二电容C2的另一端和所述第一开关Sr的另一端均与所述运算放大器FD的输出端连接。所述运算放大器FD的输出端还连接读出线Readout，所述读出线Readout用于输出光感信号。
需要说明的是，本申请的晶体管的第一极可以为晶体管的源极，晶体管的第二极可以为晶体管的漏极，比如所述第一晶体管T1的第一极S1即为所述第一晶体管T1的源极，所述第一晶体管T1的第二极D1即为所述第一晶体管T1的漏极，但本申请不限于此。另外，本申请的所述第一电容C1为存储电容，所述第二电容C2为积分电容，所述第一晶体管T1为光敏晶体管，所述第二晶体管T2为开关晶体管。
所述光感电路LC的工作过程包括：所述第一控制信号线SVGG给所述第一晶体管T1的栅极M1提供电压，使所述第一晶体管T1的所述第一极S1和所述第一晶体管T1的所述第二极D1导通，所述第一晶体管T1的沟道因被光照射而产生光生漏电流，并依光强的程度产生不同程度的漏电流。所述第一电源线SVDD的电信号从所述第一晶体管T1的第一极S1流向第二极D1，并到达所述第一电容C1的第一极板11，并因所述第一晶体管T1产生的光生漏电流而产生变化。所述第一电容C1的第二极板12连接所述公共电压信号线Vcom，则此时所述第一电容C1处于充电状态，其充电的电信号包含光感的信息。
同时所述第一电容C1的第一极板11还与所述第二晶体管T2的第一极S2连接，当所述第二控制信号线Gate给所述第二晶体管T2的栅极M2提供电压使所述第二晶体管T2的第一极S2和第二极D2导通时，则所述第一电容C1存储的电荷通过所述第二晶体管T2的第一极S2流向所述第二晶体管T2的第二极D2，使得所述第一电容C1通过所述第二晶体管T2放电。
所述第二晶体管T2的第二极D2与所述读出电路连接，所述读出电路接收所述第二晶体管T2的第二极D2流出的电荷，并把该电荷转换成电压信号输出。
继续参照图3，所述阵列基板100包括显示单元20和光感单元30，所述光感单元30的所述第一晶体管T1和所述第二晶体管T2同层设置，所述第一电容C1设置于所述第一晶体管T1和所述第二晶体管T2远离所述衬底基板10的一侧。所述显示单元20包括第三晶体管T3、像素电极13和公共电极14，所述第三晶体管T3与所述第一晶体管T1和所述第二晶体管T2同层设置，所述像素电极13设置于所述第三晶体管T3上方，且与所述第三晶体管T3电连接，所述公共电极14与所述像素电极13同层设置，且所述公共电极14复用为所述第一电容C1的第二极板12，也即所述像素电极13与所述第一电容C1的第二极板12同层设置。
可选地，所述衬底基板10可以为刚性基板或柔性基板；所述衬底基板10为刚性基板时，可包括玻璃基板等硬性基板；所述衬底基板10为柔性基板时，可包括聚酰亚胺（Polyimide，PI）薄膜、超薄玻璃薄膜等柔性基板。
需要说明的是，所述第一晶体管T1、所述第二晶体管T2以及所述第三晶体管T3同层设置在指所述第一晶体管T1、所述第二晶体管T2以及所述第三晶体管T3的各膜层在制备工艺中，将相同材料形成的膜层进行图案化处理得到至少两个不同的特征。比如本实施例中的所述像素电极13与所述公共电极14经由同一透明导电层图案化处理后得到，则所述像素电极13与所述公共电极14同层设置。
可选地，所述阵列基板100包括依次层叠设置在所述衬底基板10上的第一金属层、栅极绝缘层40、半导体层以及第二金属层。其中图案化所述第一金属层形成所述第一晶体管T1的栅极M1、所述第二晶体管T2的栅极M2、所述第三晶体管T3的栅极M3以及公共电压信号线Vcom；图案化所述半导体层形成所述第一晶体管T1的有源层21、所述第二晶体管T2的有源层22以及所述第三晶体管T3的有源层23；图案化所述第二金属层形成所述第一晶体管T1的第一极S1和第二极D1、所述第二晶体管T2的第一极S2和第二极D2、所述第三晶体管T3的第一极S3和第二极D3以及用于连接所述第一晶体管T1的第二极D1与所述第二晶体管T2的第一极S2的连接走线24。
需要说明的是，所述半导体层和所述第二金属层可以通过同一光罩进行黄光工艺以同时形成晶体管的第一极、第二极、连接走线以及有源层图案等结构。具体地，在所述栅极绝缘层上依次层叠沉积所述半导体层、所述第二金属层，然后采用半色调掩膜光罩（Half-tone mask，HTM）或灰阶色调掩膜光罩（Gray Tone Mask，GTM）对所述半导体层、所述第二金属层进行黄光工艺，通过多次曝光、显影、蚀刻等工艺形成需要的图案结构。
所述第一晶体管T1的第一极S1和第二极D1与所述第一晶体管T1的有源层21直接接触，且所述第一晶体管T1的第一极S1和第二极D2之间具有间隔，对应该间隔的所述有源层21部分为所述第一晶体管T1的沟道。所述第二晶体管T2的第一极S2和第二极D2与所述第二晶体管T2的有源层22直接接触，且所述第二晶体管T2的第一极S2和第二极D2之间具有间隔，对应该间隔的所述有源层22部分为所述第二晶体管T2的沟道。所述第三晶体管T3的第一极S3和第二极D3与所述第三晶体管T3的有源层23直接接触，且所述第三晶体管T3的第一极S3和第二极D3之间具有间隔，对应该间隔的所述有源层23部分为所述第三晶体管T3的沟道。当然地，晶体管的第一极和第二极与有源层接触的部分还可设置欧姆接触层，以减小阻抗。
进一步地，所述阵列基板100还包括第一无机层50和第二无机层60，所述第一无机层50设置于所述第一晶体管T1和所述第二晶体管T2远离所述衬底基板10的一侧；第二无机层60设置于所述第一无机层50远离所述第一晶体管T1的一侧，且位于所述第一极板11和所述第二极板12之间。
具体地，所述第一无机层50覆盖在所述第一晶体管T1的第一极S1和第二极D1以及所述第二晶体管T2的第一极S2和第二极D2上，以及覆盖在所述栅极绝缘层40上。图案化所述第一无机层50形成第一开孔，所述第一开孔贯穿所述第一无机层50至所述连接走线24，以裸漏出部分所述连接走线24。所述第一无机层50的材料包括氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiNO）等无机物。
所述第一电容C1的所述第一极板11设置于所述第一无机层50上，所述第一电容C1的所述第二极板12设置于所述第二无机层60上。具体地，所述第一无机层50上设置有第一透明导电层，图案化所述第一透明导电层形成所述第一电容C1的第一极板11，所述第一极板11通过所述第一无机层50的第一过孔与所述连接走线连接，也即所述第一极板11与所述第一晶体管T1的第二极D1以及所述第二晶体管T2的第一极S2连接。所述第一透明导电层的材料包括氧化铟锡（Indium Tin Oxide，ITO）等透明导电材料。
所述第二无机层60覆盖在所述第一极板11以及所述第一无机层50上，图案化所述第二无机层60形成有第二开孔和第三开孔，所述第二开孔贯穿所述第二无机层60、所述第一无机层50以及所述栅极绝缘层40至所述公共电压信号线Vcom，以裸露出部分所述公共电压信号线Vcom。所述第三开孔贯穿所述第二无机层60和所述第一无机层50至所述第三晶体管T3的第二极D3，以裸露出部分所述第三晶体管T3的第二极D3。所述第一无机层50的材料包括氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiNO）等无机物。
所述第二无机层60上设置有第二透明导电层，图案化所述第二透明导电层形成所述显示单元20的所述像素电极13和所述公共电极14，所述公共电极14通过所述第二过孔与所述公共电压信号线Vcom连接，且所述公共电极14复用为所述第一电容C1的第二极板12，其中所述公共电压信号线Vcom提供恒定的稳压电压信号。所述像素电极13通过所述第三过孔与所述第三晶体管T3的第二极D3连接。所述第二透明导电层的材料包括氧化铟锡（Indium Tin Oxide，ITO）等透明导电材料。
在本实施例中，通过在所述阵列基板100上新增单独的透明导电膜作为所述光感单元30的第一电容C1的第一极板11，并把所述显示单元20的公共电极14复用为所述第一电容C1的第二极板12，如此使得第一电容C1能够透光，不会额外占用显示区面积，还不会影响使用该阵列基板100的显示面板的正常显示，提高了显示面板的开口率和显示效果。同时由于第一电容C1的极板为透明电极板，可以设置于显示区且不会影响显示，因此可以设置较大面积的第一电容C1，提高了光感效果。
在一种实施例中，请参照图4，图4为本申请实施例提供的阵列基板的第二种剖面结构示意图。与上述实施例不同的是，在所述阵列基板101的所述光感单元30内，所述第一电容C1的所述第二极板12设置于所述第一无机层50上，所述第一极板11设置于所述第二无机层60上。且所述显示单元20的所述像素电极13与所述第一电容C1的第一极板11同层设置，所述公共电极14复用为所述第一电容C1的第二极板12。
具体地，所述第二极板12通过所述第一无机层50的过孔与所述公共电压信号线Vcom连接，所述第一极板11通过所述第二无机层60的过孔与所述连接走线24连接，所述像素电极13通过所述第二无机层60的另一过孔与所述第三晶体管T3的第二极D3连接。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图5，图5为本申请实施例提供的阵列基板的第三种剖面结构示意图。与上述实施例不同的是，在所述阵列基板102的所述显示单元20内，所述像素电极13和所述公共电极14不同层设置，所述公共电极14复用为所述第一电容C1的第二极板12。
具体地，所述阵列基板100还包括第三无机层70，所述第一电容C1的第一极板11设置在所述第一无机层50上，所述公共电极14设置在所述第二无机层60上，所述像素电极13设置在所述第三无机层70上，所述第三无机层70的材料可以和所述第一无机材和/或所述第二无机层60的材料相同。所述公共电极14可以设置为整面的电极，如此可以设置更多的像素电极13，以提高分别率。其他说明请参照上述实施例，在此不再赘述。
本申请实施例还提供一种显示面板，所述显示面板包括上述实施例其中之一的阵列基板，其中所述显示面板在一帧时间内分为显示阶段和光感阶段，显示单元20用于在所述显示阶段工作，光感单元30用于在所述光感阶段工作。
具体地，请结合参照图3、图6及图7，图6为本申请实施例提供的显示面板的一种剖面结构示意图，图7为本申请实施例提供的显示面板分时多工的时序示意图。所述显示面板1000为液晶显示（Liquid Crystal Display，LCD）面板，所述显示面板1000包括阵列基板100、与所述阵列基板100相对设置的彩膜基板200以及设置在所述阵列基板100和所述彩膜基板200之间的液晶层300。
因所述阵列基板100上集成有光感单元30，则包含所述阵列基板100的显示面板1000能够实现触控、指纹识别、远距离光学交互等功能，同时把光感单元30集成到所述显示面板1000内，还可减薄所述显示面板1000的整体厚度。
把所述光感单元30与所述显示单元20一块集成到阵列基板100上，为了不影响所述显示面板1000的显示，所述光感单元30和所述显示单元20可采用分时交替工作。具体地，请参照图7，在一帧时间内，所述显示面板1000分为显示阶段DD和光感阶段SD，在所述显示阶段DD栅极扫描线依次提供扫描信号（如图7中的G1至Gn-2、Gn-1、Gn）以控制所述显示单元20的晶体管打开和关闭，实现所述显示面板1000的显示功能；在所述光感阶段SD，栅极扫描线停止扫描，如图7中的G1至Gn-2、Gn-1、Gn在所述光感阶段DD全部置于低电平，以关闭所述显示面板1000的显示功能，使光感单元30在所述光感阶段SD工作。如此把所述显示面板1000的显示单元20和光感单元30分时交替工作，可以在不影响所述显示面板1000正常显示的同时，实现所述显示面板1000的触控、指纹识别、远距离光学交互等功能。
本申请实施例还提供一种显示装置，其包括前述实施例其中之一的显示面板、绑定于所述显示面板的电路板等器件以及覆盖在所述显示面板上的盖板等。所述显示装置包括手机、电视机、笔记本电脑等电子设备。
根据上述实施例可知：
本申请提供一种阵列基板和显示面板，所述阵列基板包括显示单元和光感单元，光感单元包括第一晶体管、第二晶体管以及第一电容，第一晶体管和第二晶体管同层设置，第一电容位于第一晶体管和第二晶体管上方；第一电容的第一极板和第二极板均为透明电极板，第一极板由新增的透明导电膜层形成，第二极板由显示单元的公共电极复用，且在一帧时间内显示单元和光感单元分时交替工作，如此使得第一电容能够透光，不会额外占用显示区面积，还不会影响显示面板显示，提高了显示面板的开口率和显示效果。同时由于第一电容的极板为透明电极板，可以设置于显示区且不会影响显示，因此可以设置较大面积的第一电容，提高了光感效果。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其包括衬底基板以及设置于所述衬底基板上的像素电路，所述像素电路包括驱动电路和光感电路，所述光感电路包括第一晶体管、第二晶体管和第一电容；其中：
    所述第一晶体管的栅极与第一控制信号线连接，所述第一晶体管的第一极与第一电源线连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
    所述第一电容包括第一极板和第二极板，所述第一极板与所述第一晶体管的第二极和所述第二晶体管的第一极连接，所述第二极板与公共电压信号线连接；
    其中，所述第一极板和所述第二极板均为透明电极板，所述驱动电路和所述光感电路共用所述公共电压信号线。
  2. 根据权利要求1所述的阵列基板，其中，所述光感电路还包括读出电路，所述第二晶体管的第二极与所述读出电路连接，所述第二晶体管的栅极与第二控制信号线连接。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括光感单元，所述光感电路设置于所述光感单元内，其中所述第一晶体管和所述第二晶体管同层设置，所述第一电容设置于所述第一晶体管和所述第二晶体管远离所述衬底基板的一侧。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括：
    第一无机层，设置于所述第一晶体管和所述第二晶体管远离所述衬底基板的一侧；
    第二无机层，设置于所述第一无机层远离所述第一晶体管的一侧，且位于所述第一极板和所述第二极板之间。
  5. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括显示单元，所述驱动电路设置于所述显示单元内，所述显示单元包括：
    第三晶体管，与所述第一晶体管同层设置；
    像素电极，与所述第一极板或所述第二极板同层设置；
    公共电极，复用为所述第二极板。
  6. 根据权利要求5所述的阵列基板，其中，所述第一极板设置于所述第一无机层上，所述第二极板设置于所述第二无机层上。
  7. 根据权利要求5所述的阵列基板，其中，所述第二极板设置于所述第一无机层上，所述第一极板设置于所述第二无机层上。
  8. 根据权利要求5所述的阵列基板，其中，所述第一极板、所述公共电极以及所述像素电极的材料相同。
  9. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括显示单元，所述驱动电路设置于所述显示单元内，所述显示单元包括：
    第三晶体管，与所述第一晶体管同层设置；
    像素电极，设置于所述第三晶体管上方且与所述第三晶体管电连接；
    公共电极，复用为所述第二极板；
    其中所述像素电极与所述第一极板和所述第二极板不同层设置。
  10. 根据权利要求1所述的阵列基板，其中，所述公共电压信号线与所述第一晶体管的栅极同层设置。
  11. 一种显示面板，其包括阵列基板，所述阵列基板包括衬底基板以及设置于所述衬底基板上的像素电路，所述像素电路包括驱动电路和光感电路，所述光感电路包括第一晶体管、第二晶体管和第一电容；其中：
    所述第一晶体管的栅极与第一控制信号线连接，所述第一晶体管的第一极与第一电源线连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
    所述第一电容包括第一极板和第二极板，所述第一极板与所述第一晶体管的第二极和所述第二晶体管的第一极连接，所述第二极板与公共电压信号线连接；
    其中，所述第一极板和所述第二极板均为透明电极板，所述驱动电路和所述光感电路共用所述公共电压信号线。
  12. 根据权利要求11所述的显示面板，其中，所述光感电路还包括读出电路，所述第二晶体管的第二极与所述读出电路连接，所述第二晶体管的栅极与第二控制信号线连接。
  13. 根据权利要求11所述的显示面板，其中，所述阵列基板还包括光感单元，所述光感电路设置于所述光感单元内，其中所述第一晶体管和所述第二晶体管同层设置，所述第一电容设置于所述第一晶体管和所述第二晶体管远离所述衬底基板的一侧。
  14. 根据权利要求13所述的显示面板，其中，所述阵列基板还包括：
    第一无机层，设置于所述第一晶体管和所述第二晶体管远离所述衬底基板的一侧；
    第二无机层，设置于所述第一无机层远离所述第一晶体管的一侧，且位于所述第一极板和所述第二极板之间。
  15. 根据权利要求14所述的显示面板，其中，所述阵列基板还包括显示单元，所述驱动电路设置于所述显示单元内，所述显示单元包括：
    第三晶体管，与所述第一晶体管同层设置；
    像素电极，与所述第一极板或所述第二极板同层设置；
    公共电极，复用为所述第二极板；
    其中，所述显示面板在一帧时间内分为显示阶段和光感阶段，所述显示单元用于在所述显示阶段工作，所述光感单元用于在所述光感阶段工作。
  16. 根据权利要求15所述的显示面板，其中，所述第一极板设置于所述第一无机层上，所述第二极板设置于所述第二无机层上。
  17. 根据权利要求15所述的显示面板，其中，所述第二极板设置于所述第一无机层上，所述第一极板设置于所述第二无机层上。
  18. 根据权利要求15所述的显示面板，其中，所述第一极板、所述公共电极以及所述像素电极的材料相同。
  19. 根据权利要求14所述的显示面板，其中，所述阵列基板还包括显示单元，所述驱动电路设置于所述显示单元内，所述显示单元包括：
    第三晶体管，与所述第一晶体管同层设置；
    像素电极，设置于所述第三晶体管上方且与所述第三晶体管电连接；
    公共电极，复用为所述第二极板；
    其中所述像素电极与所述第一极板和所述第二极板不同层设置。
  20. 根据权利要求11所述的显示面板，其中，所述公共电压信号线与所述第一晶体管的栅极同层设置。
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