WO2022228281A1 - 一种三维存储器、芯片封装结构及电子设备 - Google Patents

一种三维存储器、芯片封装结构及电子设备 Download PDF

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Publication number
WO2022228281A1
WO2022228281A1 PCT/CN2022/088298 CN2022088298W WO2022228281A1 WO 2022228281 A1 WO2022228281 A1 WO 2022228281A1 CN 2022088298 W CN2022088298 W CN 2022088298W WO 2022228281 A1 WO2022228281 A1 WO 2022228281A1
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Prior art keywords
electrode
dimensional memory
substrate
layer
gate
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English (en)
French (fr)
Inventor
顾俊星
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP22794752.0A priority Critical patent/EP4333062A4/en
Priority to US18/558,079 priority patent/US20240222367A1/en
Priority to JP2023566628A priority patent/JP2024517175A/ja
Publication of WO2022228281A1 publication Critical patent/WO2022228281A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present application relates to the technical field of electronic devices, and in particular, to a three-dimensional memory, a chip packaging structure, and an electronic device.
  • the memory inside the terminal needs to have the characteristics of small size and large storage capacity.
  • the capacitor used in the storage unit in the existing DRAM can be a cylindrical capacitor 01 as shown in FIG. 1 .
  • the diameter of cylindrical capacitor 01 has approached the level of 2x nm process (second generation 10nm level process).
  • the thickness of the intermediate dielectric layer of the cylindrical capacitor 01 is already close to the physical limit of quantum tunneling. Therefore, the possibility of further miniaturization of the DRAM memory device is limited, and it is difficult for a memory with a large amount of storage to be arranged in a limited space.
  • the embodiments of the present application provide a three-dimensional memory, a chip packaging structure and an electronic device, which can improve the storage capacity of a DRAM chip within a limited layout space, and the manufacturing process of the capacitor in the three-dimensional memory is less difficult, and the product of the DRAM chip is less difficult.
  • the pass rate and reliability are high.
  • some embodiments of the present application provide a three-dimensional memory including a substrate and a memory array layer.
  • the storage array layer includes at least one storage structure, and the storage structure includes N capacitors arranged side by side on the substrate.
  • the capacitor includes a first electrode, a first dielectric layer and a second electrode that are sequentially stacked on the substrate along the direction away from the substrate; wherein, N ⁇ 2, and N is an integer.
  • the capacitor in the three-dimensional memory includes a first electrode, a first dielectric layer, and a second electrode that are sequentially stacked on the substrate in a direction away from the substrate.
  • the first electrode, the first dielectric layer, and the second electrode may be thin film layers sequentially laminated on the substrate using thin film, exposure, development, and etching processes.
  • This structural design can reduce the size of the capacitor in the direction perpendicular to the substrate.
  • the above storage structure includes N capacitors arranged side by side on the substrate, so that N capacitors can be arranged in a direction parallel to the bearing surface of the substrate.
  • the three-dimensional memory in the embodiments of the present application can superimpose multiple layers of the above-mentioned storage array layers on the substrate, that is, the capacitor is provided with multiple layers, so as to improve the storage capacity of the three-dimensional memory within the limited layout space, so that when entering 1 ⁇ nm ( After the first generation of 10nm-level process), the expansion in the DRAM chip can be realized.
  • the manufacturing process of the capacitor with the thin film layer structure is relatively low, so that the manufacturing process of the multi-layer storage array layer is also less difficult.
  • the multiple capacitors in the three-dimensional memory of the embodiment of the present application have good consistency and low defect states, so that the defective rate of electronic devices in the three-dimensional memory is low, and the reliability of the electronic devices is high.
  • the first dielectric layer covers a surface of the first electrode away from the substrate and at least one side surface of the first electrode
  • the second electrode covers a surface of the first dielectric layer away from the substrate, and at least one side surface of the first dielectric layer; wherein, the second electrodes of two adjacent capacitors are arranged at intervals. Since the first dielectric layer covers both the surface of the first electrode remote from the substrate and one or more sides of the first electrode, the second electrode covers simultaneously the surface of the first dielectric layer remote from the substrate and the first dielectric on one or more sides of the layer.
  • the facing area between the first electrode and the second electrode in the capacitor is large, and the volume of the capacitor can be small while ensuring that the capacitance of the capacitor meets the storage requirement, thereby improving the capacity of the capacitor in each storage array layer.
  • the number of distributions can further increase the capacity of the three-dimensional memory.
  • the first dielectric layers of the N capacitors are connected into an integrated structure, and the first dielectric layers of the N capacitors can be fabricated by one process (such as a thin film deposition process) at a time, The process is simple and the production cost is reduced.
  • the three-dimensional memory includes M-layers of memory array layers stacked in a direction perpendicular to the substrate. Among them, M ⁇ 2, M is an integer.
  • the three-dimensional memory also includes a second dielectric layer located between two adjacent memory array layers. For a three-dimensional memory in which more than two memory array layers are stacked, a second dielectric layer is fabricated to electrically isolate two adjacent memory array layers.
  • the N capacitors are arranged side by side along the first direction, and the first cross section of the first electrode is a trapezoid.
  • the first cross section is parallel to the first direction and perpendicular to the base. Since the corners at the corners of the first electrode are relatively smooth, the occurrence of defect states at the corners of the first electrode can be reduced, and the qualified rate of the capacitor is high.
  • the storage structure further includes N pass transistors, word lines and bit lines, a first electrode of a pass transistor is electrically connected to a first electrode of a capacitor, and the word line is electrically connected to the first electrode of a capacitor.
  • the gates of the N pass transistors are electrically connected, and the bit lines are electrically connected to the second poles of the N pass transistors, so as to realize data reading and writing of the capacitors.
  • the storage structure further includes N pass transistors and word lines, a first electrode of a pass transistor is electrically connected to a first electrode of a capacitor, and the word line is connected to the N select transistors.
  • the gate of the pass transistor is electrically connected.
  • the three-dimensional memory also includes M-layer memory array layers arranged in layers along a direction perpendicular to the substrate. Among them, M ⁇ 2, M is an integer.
  • the three-dimensional memory also includes N bit lines, which penetrate through the M-layer storage array layer and are electrically connected to the second electrodes of M pass transistors located at the same position in the M-layer storage array layer. The vertical projections of the M pass transistors at the same position on the substrate overlap. This solution can also realize the data reading and writing of the capacitor, and the length of the bit line is short.
  • the word line is disposed on the side of the active layer of the gate transistor away from the substrate, and the overlapping portion of the word line and the active layer is used as the gate of the gate transistor, which is convenient to use
  • the word lines and gates of the gate transistors are simultaneously fabricated in one patterning process, which simplifies the process steps.
  • the second cross section of the first electrode is a rectangle.
  • the second section is perpendicular to the first direction and the base.
  • the length direction of the rectangle is perpendicular to the first direction and parallel to the base.
  • the side surfaces of the first electrode include a first side surface and a second side surface that are both perpendicular to the first direction, and the first dielectric layer and the second electrode sequentially cover the first side surface and the second side surface.
  • the first dielectric layer and the second electrode sequentially cover the first side surface and the second side surface of the first electrode along the length direction, so that the facing area between the first electrode and the second electrode can be larger.
  • the side surface of the first electrode further includes a third side surface and a fourth side surface that are both parallel to the first direction, and the third side surface is disposed close to the gate transistor and is opposite to the gate transistor.
  • the first electrode is electrically connected, and the first dielectric layer and the second electrode also cover the fourth side surface in turn, further increasing the facing area of the first electrode and the second electrode, and further reducing the volume of the elongated first electrode.
  • the gate transistor is arranged close to the third side of the first electrode, and there is no need to reserve the position of the gate transistor between two adjacent capacitors, so that the distance between the two adjacent capacitors is small, and the single-layer storage is further improved. The number of capacitors that can be arranged in the array layer, thereby increasing the capacity of the three-dimensional memory.
  • the substrate is a silicon substrate
  • the first electrode, the second electrode and the active layer of the gate transistor are integrated in the silicon substrate
  • the first electrode of the gate transistor is electrically connected to
  • the first electrode of the capacitor and the gate of the gate transistor are in the same layer and the same material.
  • the first electrode of the capacitor and the gate of the gate transistor can be simultaneously fabricated by using the same patterning process, thereby reducing the process flow and the fabrication cost.
  • the storage array layer includes a plurality of the storage structures arranged in an array, which can further improve the storage capacity of the three-dimensional memory.
  • some embodiments of the present application provide a chip packaging structure including a packaging substrate and the three-dimensional memory described in the above embodiments.
  • the three-dimensional memory is arranged on the package substrate. Since the chip package structure provided by the embodiment of the present application includes the three-dimensional memory described in any of the above technical solutions, the two can solve the same technical problem and achieve the same technical effect, which will not be repeated here.
  • the chip packaging structure further includes a control chip, and the control chip is disposed on the packaging substrate and is located on the same plane as the three-dimensional memory.
  • the control chip and the three-dimensional memory are stacked on the package substrate, which can meet the size requirements of different end products.
  • some embodiments of the present application provide an electronic device, including a motherboard and the chip packaging structure described in the above embodiments.
  • the chip packaging structure is arranged on the main board and is electrically connected with the main board. Since the electronic device provided by the embodiment of the present application includes the chip packaging structure described in any of the above technical solutions, the two can solve the same technical problem and achieve the same technical effect.
  • FIG. 1 is a schematic diagram of the structure connection of a capacitor in a prior art DRAM
  • FIG. 2 is a schematic structural diagram of an electronic device provided by some embodiments of the present application.
  • Fig. 3 is an exploded view of the electronic device shown in Fig. 2;
  • FIG. 4 is a schematic structural diagram of a mainboard and a chip packaging structure in the electronic device shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of the chip package structure shown in FIG. 4 including one chip
  • FIG. 6 is a schematic structural diagram of the chip package structure shown in FIG. 4 including two stacked chips;
  • FIG. 7 is a schematic structural diagram of the chip package structure shown in FIG. 4 including two chips located on the same plane;
  • FIG. 8 is a schematic structural diagram of a three-dimensional memory in the chip packaging structure shown in FIG. 7;
  • Example 9 is a schematic diagram of the three-dimensional structure of the three-dimensional memory of Example 1.
  • FIG. 10 is a schematic cross-sectional view obtained by cutting the capacitor shown in FIG. 9 along a first plane;
  • FIG. 11 is a schematic cross-sectional view obtained by cutting the capacitor shown in the first type of FIG. 9 along a second plane;
  • FIG. 12 is a schematic cross-sectional view obtained by cutting the capacitor shown in the second type of FIG. 9 along a second plane;
  • Figure 13 is a schematic cross-sectional view of A-A in Figure 9;
  • FIG. 14 is a schematic structural diagram of the three-dimensional memory shown in FIG. 9;
  • FIG. 15 is a three-dimensional structural schematic diagram of a gate transistor in the three-dimensional memory shown in FIG. 9;
  • FIG. 16 is a schematic structural diagram of the first type of gate transistor and the first type of capacitor in the three-dimensional memory shown in FIG. 9;
  • 17 is a schematic structural diagram of the second type of gate transistor and the first type of capacitor in the three-dimensional memory shown in FIG. 9;
  • FIG. 18 is a schematic structural diagram of the second gate transistor located on the third side surface of the first electrode in the three-dimensional memory shown in FIG. 17;
  • FIG. 19 is a schematic structural diagram of the second gate transistor located on the fourth side of the first electrode in the three-dimensional memory shown in FIG. 17;
  • FIG. 20 is a schematic diagram of the connection of a memory cell, a word line, and a bit line in the three-dimensional memory shown in FIG. 9;
  • 21 is a schematic diagram of the connection of N memory cells, word lines, and bit lines in the three-dimensional memory shown in FIG. 9;
  • Figure 22 is a schematic cross-sectional view of B-B in Figure 9;
  • Example 23 is a schematic diagram of the three-dimensional structure of the three-dimensional memory of Example 2.
  • 24 is a schematic structural diagram of a chip stack structure with a memory function in the related art
  • Figure 25 is a schematic cross-sectional view of C-C in Figure 23;
  • 26 is a schematic structural diagram of the three-dimensional memory shown in FIG. 23 in which word lines and bit lines are located in the storage array layer;
  • FIG. 27 is a schematic structural diagram of the three-dimensional memory shown in FIG. 23;
  • Figure 28 is a schematic cross-sectional view of D-D in Figure 23;
  • FIG. 29 is a schematic diagram of the connection of N ⁇ M memory cells, M word lines, and N bit lines in the three-dimensional memory shown in FIG. 23 ;
  • FIG. 30 is a schematic diagram of the connection of the three-dimensional memory shown in FIG. 23 including peripheral circuits;
  • Example 31 is a schematic structural diagram of the three-dimensional memory of Example 3.
  • Example 32 is a schematic structural diagram of the three-dimensional memory of Example 4.
  • FIG. 33 is a schematic diagram of the three-dimensional structure of the three-dimensional memory shown in FIG. 32;
  • Figure 34 is a schematic cross-sectional view of E-E in Figure 33;
  • Figure 35 is a schematic cross-sectional view of F-F in Figure 33;
  • FIG. 36 is a schematic structural diagram of a chip stack structure in an electronic device of Example 5.
  • FIG. 36 is a schematic structural diagram of a chip stack structure in an electronic device of Example 5.
  • the present application provides an electronic device, which may include a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a camera, a personal computer, a notebook computer , vehicle devices, wearable devices, augmented reality (AR) glasses, AR helmets, virtual reality (VR) glasses or VR helmets and other devices that need to store data.
  • PDA personal digital assistant
  • AR augmented reality
  • VR virtual reality
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • the electronic device is a mobile phone as shown in FIG. 2 as an example for illustration.
  • FIG. 2 is a perspective view of an electronic device provided by some embodiments of the present application
  • FIG. 3 is an exploded view of the electronic device shown in FIG. 2
  • the electronic device 1000 is a mobile phone.
  • the electronic device 1000 may include a screen 100, a middle frame 200, a rear case 300, and a main board 400 fixed on the middle frame 200 as shown in FIG. 3 .
  • FIGS. 2 and 3 only schematically show some components included in the electronic device 1000 , and the actual shapes, actual sizes, actual positions and actual structures of these components are not limited by FIGS. 2 and 3 .
  • the electronic device 1000 may also not include the screen 100 .
  • the electronic device 1000 may further include the camera 500 as shown in FIG. 3 .
  • the electronic device 1000 may further include a chip package structure 600 as shown in FIG. 4 .
  • the chip package structure 600 is disposed on the mainboard 400 and is electrically connected to the mainboard 400 .
  • the chip package structure 600 may be electrically connected to the main board 400 through a ball grid array (BGA) or a plurality of copper pillar bumps (CPB) arranged in an array, so that the chip package structure 600 can Signal transmission with other chips on the main board 400 or a chip stacking structure is realized.
  • BGA ball grid array
  • CPB copper pillar bumps
  • mainboard 400 may be a printed circuit board (printed circuit board, PCB).
  • PCB printed circuit board
  • present application does not limit the number of chip packaging structures 600 on the mainboard 400 , which may be one, two, or more than two.
  • the chip package structure 600 may include a package substrate (SUB) 601 , a chip 602 disposed on the package substrate 601 , and a molding compound (molding) 603 for molding the chip 602 .
  • the chip 602 may be a bare chip (ie, a bare die), or may be a chip stack structure (ie, a plurality of bare dies are stacked).
  • the present application does not limit the number of chips 602 packaged in the chip package structure 600, which may be one as shown in FIG. 5, two as shown in FIG. 6 and FIG. 7, or more than two .
  • the chip package structure 600 shown in FIG. 6 and FIG. 7 is used as an example in which two chips 6021 and 6022 are packaged as an example.
  • One chip 6021 in the chip package structure 600 shown in FIG. 6 may be a processing chip with a data processing function, such as a central processing unit (CPU), a system on chip (SOC) or an image processing It is a chip that can process data, such as a graphics processing unit (GPU).
  • Another chip 6022 in the chip package structure 600 shown in FIG. 6 may be a chip having at least a memory function, and the chip may include a three-dimensional memory. Both the chip with three-dimensional memory and the processing chip can be electrically connected to the packaging substrate 601 , so that the chip with three-dimensional memory and the processing chip can transmit data through the packaging substrate 601 .
  • a chip having at least a storage function means that the chip may only have a storage function.
  • the chip is a memory chip.
  • the chip may have other functions, such as a data processing function, at the same time as having a storage function.
  • the chip is a multifunctional integrated chip.
  • the above-mentioned three-dimensional memory can be a DRAM storage device, such as double data rate synchronous dynamic random access memory (DDR), low power double data rate synchronous dynamic random access memory (low power double data rate synchronous dynamic random access memory, DDR) memory, LPDDR), etc.
  • DDR double data rate synchronous dynamic random access memory
  • DDR low power double data rate synchronous dynamic random access memory
  • LPDDR low power double data rate synchronous dynamic random access memory
  • the arrangement in which the two chips 6021 and 6022 are located on the same plane as shown in FIG. 7 is adopted. Specifically, an appropriate orientation arrangement relationship of two or more chips can be selected according to the actual needs of the electronic device.
  • the two chips shown in FIG. 6 and FIG. 7 are described by taking the chip 6021 as the three-dimensional memory and the chip 6022 as the control chip as an example.
  • one of the chips may be the above-mentioned processing chip with a data processing function, and the other two may be the above-mentioned chips with at least a storage function.
  • two of the three chips are the above-mentioned chips with at least a storage function, and the remaining one of the three chips is the above-mentioned processing chip with a data processing function.
  • the azimuthal arrangement of the plurality of chips on the package substrate 601 is the same as that described above, and will not be repeated here.
  • the three-dimensional memory 10 shown in FIG. 3 includes a substrate 101 and a storage array layer 102 , and the storage array layer 102 includes a storage structure 1020 .
  • the base 101 may also be called a substrate.
  • the substrate 101 may be located under the storage array layer 102 and used to carry the storage array layer 102 .
  • the substrate 101 may be a single-layer structure.
  • the material constituting the substrate 101 may include semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like.
  • the material of the substrate 101 may include a non-conductive material, such as glass, plastic, or sapphire, or the like.
  • the above-mentioned substrate 101 may be a multi-layer structure.
  • the layer farthest from the memory array layer 102 can use the above-mentioned semiconductor material or non-conductor material, and the rest of the film layers can be patterned as required to form other circuit structures.
  • the above patterning process may refer to a photolithography process, or a photolithography process and an etching step, and may also include other processes for forming predetermined patterns such as printing and inkjet. Corresponding patterning processes can be selected according to the structures formed in the embodiments of the present application.
  • the above-mentioned photolithography process refers to a process of forming a pattern by using photoresist, a mask, an exposure machine, etc., including process processes such as film formation, exposure, and development.
  • the plane where the substrate 101 is located may be the XY plane.
  • the X axis may be the length direction of the substrate 101
  • the Y axis may be the width direction of the substrate 101
  • the Z axis The axis is a direction that is perpendicular or approximately perpendicular to the substrate 101 within manufacturing tolerances. It can be understood that the dimension of the width of the substrate 101 is smaller than the dimension of the length of the substrate 101 .
  • the three-dimensional memory 10 shown in FIG. 9 is used.
  • the three-dimensional memory 10 includes a storage array layer 102 including a storage structure 1020 .
  • FIG. 10 is a cross-sectional view obtained by cutting the capacitor 1 shown in FIG. 9 with a first plane P parallel to the YZ plane.
  • the capacitor 1 shown in FIG. 10 may include a first electrode 11 , a first dielectric layer 12 and a second electrode 13 .
  • the first electrode 11 , the first dielectric layer 12 and the second electrode 13 are sequentially stacked on the substrate 101 along the direction away from the substrate 101 (the direction away from the substrate 101 is the Z-axis direction).
  • the capacitor 1 in the three-dimensional memory 10 provided in this example includes the first electrode 11 , the first dielectric layer 12 and the second electrode 13 that are stacked on the substrate 101 in sequence along the Z-axis direction.
  • the first electrode 11 , the first dielectric layer 12 , and the second electrode 13 may be thin film layers sequentially laminated on the substrate 101 through thin film, exposure, development, and etching processes. This structural design can reduce the size of the capacitor 1 in the direction perpendicular to the substrate 101 .
  • the above-mentioned storage structure 1020 includes N capacitors 1 arranged side by side on the substrate 101 , so that N capacitors 1 can be arranged in a direction parallel to the bearing surface (parallel to the XY plane) of the substrate 101 . .
  • the size of the capacitor 1 in the Z direction in this example is smaller.
  • the three-dimensional memory 10 can stack multiple layers of the above-mentioned memory array layers 102 on the substrate 101, that is, the capacitor 1 is provided with multiple layers, so as to improve the storage capacity of the three-dimensional memory 10 within the limited space of the fabric, so that when entering the After 1xnm (the first-generation 10nm-level process), the expansion in the DRAM chip can be realized.
  • the manufacturing process of the capacitor 1 with the thin film structure is relatively low, so the manufacturing process of the multi-layer memory array layer 102 is also less difficult.
  • the multiple capacitors 1 in the three-dimensional memory 10 have good consistency and low defect states, so that the defective rate of electronic devices in the three-dimensional memory 10 is low, and the reliability of the electronic devices is high.
  • the capacitor 1 in this example can be fabricated by a relatively advanced process of 14 nm, 10 nm, 7 nm and below (the minimum line width of a transistor in a chip), and a three-dimensional memory with smaller size and higher capacity can be obtained.
  • the material for making the first electrode 11 and the material for making the second electrode 13 may be the same or different.
  • the material of the first electrode 11 and the material of the second electrode 13 are any of cobalt (Co), titanium nitride (TiN), polysilicon, and other materials.
  • the material used for the first dielectric layer 12 of the capacitor 1 is a High-k (high dielectric constant) dielectric material.
  • high-k dielectric material aluminum oxide (Ai2O3), hafnium oxide (HfO2), or any one of a multilayer material composed of zirconium-aluminum, and the like.
  • the above-mentioned High-k dielectric material refers to a material with a dielectric constant K greater than 3.9.
  • the first cross-section of the first electrode 11 is a trapezoid. If the process steps such as etching and deposition are used on the substrate 101 In the production of the capacitor 1, since the corners at the four corners W of the first electrode 11 are relatively smooth, the occurrence of defect states at the corners W of the first electrode 11 can be reduced, and the yield of the capacitor 1 is high. It can be understood that the shape of the first electrode 11 can also be other shapes that are convenient to manufacture, for example, the first cross section of the first electrode 11 is a semi-cylindrical shape.
  • the capacitor 1 of this example adopts the structure shown in FIG. 10 , and the first dielectric layer 12 covers the surface of the first electrode 11 away from the substrate 101 (ie, the upper surface 111 of the first electrode 11 ) and the surface of the first electrode 11 . Side 112.
  • the second electrode 13 covers the surface of the first dielectric layer 12 away from the substrate 101 (ie, the upper surface 121 of the first dielectric layer 12 ) and the side surface 122 of the first dielectric layer 12 .
  • the facing area between the first electrode 11 and the second electrode 13 in the capacitor 1 shown in FIG. 10 is large.
  • this example does not limit the area covered by the first dielectric layer 12 and the second electrode 13 on the first electrode 11 , and the first dielectric layer 12 in the capacitor 1 can also be designed to cover only the first electrode 11 .
  • the upper surface 111 of the second electrode 13 only covers the upper surface 121 of the first dielectric layer 12 .
  • the capacitor 1 shown in FIG. 9 is an elongated protruding structure disposed on the substrate 101 , which may also be referred to as a horizontal fin-shaped structure.
  • the horizontal type refers to being arranged parallel to the plane where the substrate 101 is located; the N capacitors 1 on the substrate 101 can be regarded as a horizontal multi-fin structure arranged on the substrate 101 as shown in FIG. 9 .
  • FIG. 11 is a cross-sectional view obtained by cutting a horizontal fin capacitor shown in FIG. 9 with a second cross-section Q parallel to the X-Z plane.
  • FIG. 12 is a cross-sectional view obtained by cutting another horizontal fin-shaped capacitor shown in FIG. 9 with a second cross-section Q parallel to the X-Z plane.
  • the second cross section Q of the first electrode 11 of the capacitor 1 shown in FIGS. 11 and 12 is both rectangular.
  • the sides 112 of the first electrode 11 are all four, and the four sides 112 of the first electrode 11 can be respectively along the X axis
  • the first side surface 112a and the second side surface 112b extending in the direction
  • the third side surface 112c and the fourth side surface 112d both extending in the Y-axis direction.
  • there are also four side surfaces 122 of the first dielectric layer 12, and the four side surfaces 122 of the first dielectric layer 12 are respectively the fifth side surface 122a and the sixth side surface 122b extending along the X-axis direction, and the fourth side surface 122b both extending along the Y-axis direction.
  • the seventh side surface 122c and the eighth side surface 122d extending in the axial direction.
  • the first dielectric layer 12 covers the upper surface 111 of the first electrode 11 , the first side surface 112 a of the first electrode 11 and the second side of the first electrode 11 .
  • the second electrode 13 covers the upper surface 121 of the first dielectric layer 12 , the fifth side surface 122 a of the first dielectric layer 12 and the sixth side surface 122 b of the first dielectric layer 12 . Since the first dielectric layer 12 and the second electrode 13 can cover the first side surface 112 a and the second side surface 112 b of the horizontal fin capacitor extending in the length direction, the first electrode 11 and the second electrode 13 are directly opposite to each other. Larger area.
  • the third side 112c and the fourth side 112d of the first electrode 11 are both exposed, which can facilitate the electrical connection from the third side 112c of the first electrode 11 to other devices in the storage structure 1020, or from the third side 112c of the first electrode 11.
  • the fourth side 112d is electrically connected to other devices in the memory structure 1020 .
  • the first dielectric layer 12 covers the upper surface 111 of the first electrode 11 , the first side surface 112 a of the first electrode 11 , and the second side of the first electrode 11 .
  • the side surface 112 b and the fourth side surface 112 d of the first electrode 11 , the second electrode 13 covers the fifth side surface 122 a of the first dielectric layer 12 , the sixth side surface 122 b of the first dielectric layer 12 and the first side surface 122 b of the first dielectric layer 12 .
  • the first dielectric layer 12 and the second electrode 13 can sequentially cover the first side 112 a and the second side 112 b extending in the length direction and the fourth side 112 d extending in the width direction of the long capacitor 1 , the first dielectric layer The electrical layer 12 and the second electrode 13 can cover a large number of side surfaces and a large area of the long capacitor 1 , so that the facing area between the first electrode 11 and the second electrode 13 is large.
  • the third side surface 112c of the first electrode 11 is all exposed, which can facilitate electrical connection with other devices in the storage structure 1020 from the third side surface 112c of the first electrode 11 .
  • FIG. 13 is a cross-sectional view taken along line A-A of FIG. 9 .
  • the first dielectric layers 12 of the N capacitors 1 in the storage structure 1020 of this example adopt a structure that is connected as a whole as shown in FIG. 13 .
  • the first dielectric layers 12 of the N capacitors 1 can be fabricated by one process (eg, a thin film deposition process), the process is simple, and the fabrication cost is reduced.
  • the above-mentioned storage structure 1020 may further include a gate transistor 2 as shown in FIG. 14 , and the gate transistor 2 is electrically connected to the capacitor 1 .
  • the gate transistor 2 When the gate transistor 2 is gated, data is written in the capacitor 1 or data is read from the capacitor 1 .
  • the strobe transistor 2 When the strobe transistor 2 is turned off, the reading of data from the capacitor 1 is stopped.
  • the gate transistor 2 in this example may be a metal-oxide-semiconductor field-effect transistor (metal-oxide-semiconductor field-effect transistor, MOSFET, MOS tube is the abbreviation of MOSFET).
  • the MOS transistor may include a first electrode 21 , a second electrode 22 and a gate electrode 23 as shown in FIG. 15 .
  • the first electrode 21 of the gate transistor 2 is electrically connected to the first electrode 11 of the capacitor 1, as shown in FIG. 16 .
  • the gate signal provided to the gate 23 of the MOS transistor is an effective signal, the MOS transistor is in a conducting state, and the first electrode 21 and the second electrode 22 of the MOS transistor are electrically connected at this time.
  • the gate transistor 2 shown in FIG. 15 is a fin field-effect transistor (FinFET).
  • the above-mentioned MOS transistor may be an N-type transistor.
  • the strobe signal may be a high level for an active signal, and a low level for an inactive signal.
  • the above-mentioned MOS transistor can be a P-type transistor, and at this time, the strobe signal can be a low level when the active signal is active, and a high level can be used for an inactive signal.
  • the first electrode 21 of the above-mentioned gate transistor 2 may be a source electrode (source, S), and at this time, the second electrode 22 of the gate transistor 2 may be a drain electrode (drain, D).
  • the first electrode 21 of the above-mentioned gate transistor 2 may be the drain electrode, and in this case, the second electrode 22 of the gate transistor 2 may be the source electrode.
  • the whole or part of the gate transistor 2 in the three-dimensional memory 10 of the present example is formed in the substrate 101 , as shown in FIG. 16 .
  • the entirety of the gate transistor 2 is directly formed on the substrate 101 .
  • the substrate 101 is a silicon substrate
  • the source, drain and active layers of the gate transistor 2 are integrated in the substrate 101
  • the gate 23 of the gate transistor 2 is formed on the substrate 101 , as shown in FIG. 16 .
  • the gate transistor 2 can be formed by a number of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing, and any other suitable process.
  • doped regions are formed in the silicon substrate by ion implantation and/or thermal diffusion, which serve, for example, as source and/or drain regions of the gate transistor 2 .
  • the gate 23 of the gate transistor 2 shown in FIG. 16 is arranged in the same layer as the first electrode 11 of the capacitor 1, and the first electrode 11 of the capacitor 1 may be in the same layer and the same material as the gate 23 of the gate transistor 2, for example Any one of materials such as cobalt (Co), titanium nitride (TiN) or polysilicon, so that the gate 23 of the gate transistor 2 and the first electrode 11 of the capacitor 1 can use the same patterning process to simultaneously fabricate the first electrode of the capacitor 1.
  • An electrode 11 and a gate 23 of the gate transistor 2 Therefore, the number of technological processes is reduced, and the manufacturing cost is reduced.
  • the material of the gate 23 of the gate transistor 2 and the material of the first electrode 11 of the capacitor 1 may also be different, which is not limited here, and can be selected according to actual needs.
  • the "same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process.
  • the same patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the one patterning process in this example is described by taking an example of forming different exposure areas through a single mask exposure process, and then performing multiple etching, ashing and other removal processes on different exposure areas to finally obtain the desired pattern. .
  • the entire gate transistor 2 can be formed on the substrate 101 , and the entire capacitor 1 and the gate transistor 2 can be disposed in the same layer, as shown in FIG. 17 .
  • the gate transistors 2 can be arranged in different mounting positions on the substrate.
  • the first electrode 21 of the gate transistor 2 may be disposed close to the third side surface 112 c of the first electrode 11 . Since the gate transistor 2 is arranged on the side where the broad side of the first electrode 11 of the horizontal fin capacitor is located, there is no need to reserve the position of the gate transistor 2 between two adjacent capacitors 1, so that the adjacent The distance between the two capacitors 1 is small. And the number of capacitors 1 that can be arranged in the memory array layer 102 is further increased, thereby increasing the storage capacity of the three-dimensional memory 10 .
  • the third side 112 c and the fourth side 112 d of the four side surfaces of the first electrode 11 are both exposed.
  • the first electrode 21 of the gate transistor 2 shown in FIG. 18 is disposed close to the third side surface 112c of the first electrode 11 of the horizontal fin capacitor.
  • the first electrode 21 of the gate transistor 2 shown in FIG. 19 is disposed close to the fourth side surface 112d of the first electrode 11 of the horizontal fin capacitor.
  • the gate transistor 2 is also arranged on the side where the broad side of the first electrode 11 of the horizontal fin capacitor is located. Therefore, the number of capacitors 1 that can be arranged in the memory array layer 102 can also be increased, thereby increasing the storage capacity of the three-dimensional memory 10 .
  • the three-dimensional memory 10 in this example further includes a word line (wordline, WL) 3 and a bit line (bitline, BL) 4 as shown in FIG. 20 , the word line 3 is electrically connected to the gate 23 of the pass transistor 2 , and the bit line 4 is electrically connected to the second pole 22 of the gate transistor 2 .
  • the word line 3 is used to input a gate signal to the gate 23 of the gate transistor 2, and the bit line 4 is used to read the stored data in the capacitor 1 or write the stored data into the capacitor 1 when the gate transistor 22 is gated. .
  • the number of pass transistors 2 in the memory structure 1020 of this example is also N, and the first electrodes 21 of the N pass transistors 2 are electrically connected to the first electrodes 11 of the N capacitors 1 in a one-to-one correspondence, so as to form N pieces of FIG. 21 Storage unit 1021 is shown.
  • word line 3 and N bit lines 4 there are one word line 3 and N bit lines 4 in the memory structure 1020 of this example.
  • the word lines 3 are all electrically connected to the gates 23 of the N pass transistors 2
  • the N bit lines 4 are respectively electrically connected to the second electrodes 22 of the N pass transistors 2 in a one-to-one correspondence.
  • the word line 3 and the bit line 4 are arranged near the pass transistor 2 so as to shorten the length of the word line 3 and the bit line 4 .
  • FIG. 22 is a B-B cross-sectional view of FIG. 9 .
  • the word line 3 is disposed on the side of the active layer of the pass transistor 2 away from the substrate 101 , and the overlapping portion of the word line 3 and the active layer serves as the gate 23 of the pass transistor 2 , As shown in FIG. 22 , it is convenient to use one patterning process to simultaneously manufacture the word lines 3 and the gates 23 of the N gate transistors 2 , thereby simplifying the process steps.
  • the word line 3 and the gate electrode 23 of the gate transistor 2 are made of the same material.
  • the word line 3 can also be fabricated independently, which is not limited in this example.
  • the gate 23 of the gate transistor 2 and the first electrode 21 of the capacitor 1 are in the same layer and the same material, if the overlapping part of the word line 3 and the active layer is used as the gate 23 of the gate transistor 2 , the gate 23 of the gate transistor 2 , the first electrode 21 of the capacitor 1 and the word line 3 can be simultaneously fabricated by one patterning process.
  • This example is a three-dimensional memory 10 in which M layers of memory array layers 102 as shown in FIG. 9 are stacked along the Z-axis direction. Among them, M ⁇ 2, M is an integer.
  • the capacitor 1 in the three-dimensional memory 10 in this example has multiple layers (eg, more than one hundred layers) , more data can be stored in the limited space of the cloth, so that the capacity of the three-dimensional memory 10 is larger.
  • the manufacturing process difficulty of the capacitor 1 with the thin film layer structure is relatively low, which reduces the manufacturing process difficulty of manufacturing the multi-layer memory array layer 102. Therefore, the plurality of capacitors 1 in the fabricated three-dimensional memory 10 have good consistency and low defect states. Therefore, the defective rate of electronic devices in the three-dimensional memory 10 is also low, and the reliability of the electronic devices is high.
  • this technology is a high bandwidth memory (HBM) obtained by directly stacking and bonding a plurality of thinned memory chips (bare die) 02 .
  • HBM high bandwidth memory
  • the three-dimensional memory 10 in this example can realize the fabrication of a multi-layer storage array layer structure in the same bare die, so that the capacity of the three-dimensional memory 10 can be increased through the three-dimensional stacking of the storage structures in the bare die.
  • FIG. 25 is a schematic cross-sectional view along C-C in FIG. 23 .
  • the three-dimensional memory 10 of this example further includes the second dielectric layer 103 shown in FIG. 25 , the second dielectric layer 103 is located between two adjacent memory array layers 102 , and the second dielectric layer 103 can realize the phase The two adjacent memory array layers 102 are electrically isolated.
  • the second dielectric layer 103 may be an inter-metal-dielectric (IMD) dielectric material, such as silicon dioxide (SiO 2 ).
  • IMD inter-metal-dielectric
  • a layer of storage array layer 102 may be formed on the substrate 101 through process steps such as upward growth, epitaxy, etching, deposition, etc., and then a second dielectric layer may be formed on the layer of storage array layer 102. Step 103 , and then another layer of memory array layer 102 is formed on the second dielectric layer 103 , and the process is repeated, so that more than one hundred layers of memory array layers 102 are formed on each substrate 101 . Since the same mask can be used to form the multi-layer memory array layer 102, the process cost of the three-dimensional memory 10 can be reduced.
  • the placement positions of the word lines 3 and the bit lines 4 in the three-dimensional memory 10 of the present example may adopt the solution in which the word lines 3 and the bit lines 4 are both located in the memory array layer 102 as shown in FIG. 26 .
  • the word lines 3 in the memory array layer 102 of each layer are electrically connected to the pass transistors 2 in that layer.
  • the bit lines 4 in the memory array layer 102 of each layer are electrically connected to the pass transistors 2 in that layer.
  • any memory array layer 102 in the three-dimensional memory 10 of this example includes word lines 3 electrically connected to the gates 23 of the N gate transistors 2 on the layer, and adopts the bit line 4 structure shown in FIG. 27 .
  • the number of bit lines 4 in the three-dimensional memory 10 is N, and the N bit lines 4 respectively pass through the M-layer storage array layer 102 and are located at the same position as the second poles of the M gate transistors 2 in the M-layer storage array layer 102 22 Electrical connections.
  • the vertical projections of the M pass transistors 2 at the same position on the substrate 101 are overlapped, and the bit line 4 is as shown in FIG.
  • the via structure of the second electrode 13 of the capacitor 1 The length of the required bit line 4 can be shortened due to the short spacing of the gate transistors 2 between the different layers.
  • Each memory array layer 102 includes N pass transistors 2 and N capacitors 1 , and the first electrodes 21 of the N pass transistors 2 are electrically connected to the first electrodes 11 of the N capacitors 1 in a one-to-one correspondence, so as to form N M ⁇ N memory cells 1021 shown in FIG. 29 .
  • the three-dimensional memory 10 of this example further includes the peripheral circuit 104 shown in FIG. 30 .
  • the peripheral circuit 104 includes a read and write strobe circuit 1041 (eg, a word line strobe circuit sub-word-line, SWL), an address decoder (eg, a row decoder and a column decoder) 1042, a signal amplification circuit (sense- amplitute, S/A) 1043, etc.
  • the address decoder 1042 is electrically connected to the read/write gate circuit 1041
  • the read/write gate circuit 1041 is electrically connected to the word line 3
  • the signal amplifier circuit 1043 is electrically connected to the bit line 4 .
  • the address decoder 1042 selects the word line 3 corresponding to the address through the read and write gating circuit 1041 according to the address information contained in the read command. After that, the bit line 4 reads out the data contained in the corresponding capacitor 1 of the word line 3 strobe, and amplifies the data signal through the signal amplifying circuit 1043. After the address decoder 1042 receives the write command, according to the address information contained in the write command, the word line 3 corresponding to the address is gated by the read and write gating circuit 1041, and then the bit line 4 is sent to the corresponding capacitor 1 write data inside.
  • the above-mentioned peripheral circuit 104 may be formed on the substrate 101 and may be located at an edge position of the substrate 101 .
  • the peripheral circuit 104 may be disposed in the same layer as the bottommost memory array layer 102 .
  • the fabrication process of the peripheral circuit 104 can also be formed by various processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing, and any other suitable process.
  • the above-mentioned word lines 3 and bit lines 4 may be electrically connected to the peripheral circuit 104 on the substrate 101 through the via interconnect structure.
  • This example is a three-dimensional memory 10 as shown in FIG. 31 .
  • the three-dimensional memory 10 is similar in structure to the three-dimensional memory in Example 1, except that the storage array layer 102 includes S storage structures 1020, and the S storage structures 1020 are arranged. Among them, S ⁇ 2, S is an integer.
  • each storage array layer 102 includes the above-mentioned S storage structures 1020 arranged in arrays, that is, the more capacitors 1 included in each storage array layer 102, the larger the size parallel to the XY plane can be. of end products to increase storage capacity needs.
  • the number of storage structures 1020 on the storage array layer 102 is not limited herein.
  • the S memory structures 1020 on the memory array layer 102 may also be arranged along a circular array.
  • This example is a three-dimensional memory 10 in which M layers of memory array layers 102 as shown in FIG. 31 are stacked along the Z-axis direction.
  • FIG. 34 is a schematic cross-sectional view taken along lines E-E of FIG. 33
  • FIG. 35 is a schematic cross-sectional view taken along lines F-F of FIG. 33 . 32, 33 and 34, it can be seen that since this example includes the same structure as that of the third example, the same technical effect as that of the third example can be obtained.
  • the capacitor 1 in the three-dimensional memory 10 of the present example has multiple layers, which can store more data, so that the capacity of the three-dimensional memory 10 is further improved.
  • This example is an electronic device provided with a chip stacking structure as shown in FIG. 36 , and the chip stacking structure may be located on a main board in the electronic device.
  • the chip stacking structure a plurality of three-dimensional memories 10 (bare die) as shown in FIG. 32 are stacked and arranged, and the plurality of three-dimensional memories 10 can be electrically connected by means of through-hole bonding, thereby further improving the storage capacity of the electronic device, And realize high-bandwidth storage of electronic devices.
  • FIG. 36 is an example in which there are four bare chips in the chip stack structure.
  • the chip stack structure of this example can also be included in the chip package structure.

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Abstract

本申请提供一种三维存储器、芯片封装结构及电子设备，涉及电子设备技术领域。本申请的三维存储器能够在有限的布件空间内，提高DRAM芯片的存储能力，并且三维存储器中电容器的制作工艺难度较小，DRAM芯片的产品合格率和可靠性较高。本申请实施例提供一种包括基底和存储阵列层的三维存储器。其中，存储阵列层包括至少一个存储结构，存储结构包括并排设置于基底上的N个电容器。电容器包括沿远离基底的方向、依次层叠设置于基底上的第一电极、第一介电层以及第二电极；其中，N≥2，N为整数。本申请实施例提供的三维存储器用于存储数据。

Description

一种三维存储器、芯片封装结构及电子设备
本申请要求于2021年04月30日提交国家知识产权局、申请号为202110485941.9、申请名称为“一种三维存储器、芯片封装结构及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子设备技术领域，尤其涉及一种三维存储器、芯片封装结构及电子设备。
背景技术
为了满足半导体集成电路的小型化和高集成度的要求，终端内部的存储器需要兼具体积小、存储量大的特点。
以动态随机存取存储器(dynamic random access memory,DRAM)为例，现有DRAM中的存储单元所采用的电容器可以为如图1所示的圆柱形电容器01。为了减小DRAM的体积，圆柱形电容器01的直径已经逼近2x nm工艺(第二代10nm级工艺)级别。并且，圆柱形电容器01的中间介电层的厚度已经接近量子隧穿的物理极限值。因此限制了DRAM存储器件进一步微缩的可能性，使得存储量较大的存储器很难设置于有限的布件空间内。
发明内容
本申请的实施例提供一种三维存储器、芯片封装结构及电子设备，能够在有限的布件空间内，提高DRAM芯片的存储能力，并且三维存储器中电容器的制作工艺难度较小，DRAM芯片的产品合格率和可靠性较高。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请一些实施例提供一种包括基底和存储阵列层的三维存储器。其中，存储阵列层包括至少一个存储结构，存储结构包括并排设置于基底上的N个电容器。电容器包括沿远离基底的方向、依次层叠设置于基底上的第一电极、第一介电层以及第二电极；其中，N≥2，N为整数。
由于本申请实施例提供的三维存储器中的电容器包括在基底上、沿远离基底的方向依次层叠设置的第一电极、第一介电层以及第二电极。在此情况下，上述第一电极、第一介电层以及第二电极可以为采用薄膜、曝光、显影、刻蚀工艺依次层叠于基底上的薄膜层。这种结构设计能够减小电容器在垂直于基底的方向上的尺寸。在此基础上，上述存储结构包括并排设置于基底上的N个电容器，这样一来，在与基底的承载面平行的方向上，能够设置N个电容器。在此情况下，相对于圆柱形电容器而言，由于该电容器在垂直于基底的方向上的尺寸较大，而本申请实施例中电容器在垂直于基底的方向上的尺寸较小。因此，本申请实施例中的三维存储器能够在基底上叠加多层上述存储阵列层，即电容器设置有多层，从而在有限的布件空间内，提高三维存储器的存储容量，使得在进入1xnm(第一代10nm级工艺)之后能够实现DRAM芯片内的扩容。并且薄膜层结构的电容器的制作工艺难度较低，从而制作多层存储阵列层的制作工艺难度也较低。基于以上，本申请实施例三维存储器中的多个电容器一致性较好、 缺陷态低，使得三维存储器中的电子器件不良率较低，电子器件的可靠性较高。
在第一方面的一种可能的实现方式中，第一介电层覆盖第一电极远离基底的表面、以及第一电极的至少一个侧面，第二电极覆盖第一介电层远离基底的表面、以及第一介电层的至少一个侧面；其中，相邻的两个电容器的第二电极间隔设置。由于第一介电层同时覆盖在第一电极远离基底的表面以及第一电极的一个或多个侧面上，第二电极覆盖同时覆盖在第一介电层远离基底的表面、以及第一介电层的一个或多个侧面上。所以，电容器中的第一电极与第二电极之间的正对面积较大，能够在保证电容器的电容量满足存储需求的情况下，电容器的体积较小，从而提高每层存储阵列层中电容器的分布数量，进一步提高三维存储器的容量。
在第一方面的一种可能的实现方式中，N个电容器的第一介电层相连接为一体结构，能够一次采用一道工艺(如薄膜沉积工艺)制作N个电容器的第一介电层，工艺简单，降低了制作成本。
在第一方面的一种可能的实现方式中，三维存储器包括沿垂直于基底的方向、层叠设置的M层存储阵列层。其中，M≥2，M为整数。三维存储器还包括第二介电层，第二介电层位于相邻的两层存储阵列层之间。对于堆叠有两层以上的存储阵列层的三维存储器，制作第二介电层将相邻的两层存储阵列电隔离开。
在第一方面的一种可能的实现方式中，N个电容器沿第一方向并排设置，第一电极的第一截面为梯形。其中，第一截面与第一方向平行、且与基底垂直。由于第一电极的边角处的拐角较为平滑，所以，能够减少第一电极的边角处出现缺陷态，电容器的合格率较高。
在第一方面的一种可能的实现方式中，存储结构还包括N个选通晶体管、字线及位线，一个选通晶体管的第一极与一个电容器的第一电极电连接，字线与N个选通晶体管的栅极电连接，位线与N个选通晶体管的第二极电连接，以实现电容器的数据读取和写入。
在第一方面的一种可能的实现方式中，存储结构还包括N个选通晶体管和字线，一个选通晶体管的第一极与一个电容器的第一电极电连接，字线与N个选通晶体管的栅极电连接。三维存储器还包括沿垂直于基底的方向、层叠设置的M层存储阵列层。其中，M≥2，M为整数。三维存储器还包括N条位线，位线贯穿M层存储阵列层、且与M层存储阵列层中位于同一位置的M个选通晶体管的第二极电连接。其中，同一位置的M个选通晶体管在基底上的垂直投影重叠。该方案同样能够实现电容器的数据读取和写入，并且位线的长度较短。
在第一方面的一种可能的实现方式中，字线设置于选通晶体管的有源层远离基底的一侧，字线与有源层搭接的部分作为选通晶体管的栅极，便于采用一次构图工艺同时制作字线和选通晶体管的栅极，简化工艺步骤。
在第一方面的一种可能的实现方式中，第一电极的第二截面为长方形。其中，第二截面与第一方向、基底均垂直。长方形的长度方向与第一方向垂直、且与基底平行。第一电极的侧面包括与第一方向均垂直的第一侧面和第二侧面，第一介电层和第二电极依次覆盖第一侧面和第二侧面。对于长条形的第一电极，第一介电层和第二电极依次覆盖第一电极沿长度方向的第一侧面和第二侧面，能够使得第一电极和第二电极之 间的正对面积较大。基于以上，该方案能够缩小长条形第一电极的体积，在有限的布件空间内，该方案能够增大每层存储阵列层所能排布的电容器的数量，从而增大三维存储器的容量。
在第一方面的一种可能的实现方式中，第一电极的侧面还包括与第一方向均平行的第三侧面和第四侧面，第三侧面靠近选通晶体管设置、且与选通晶体管的第一极电连接，第一介电层和第二电极还依次覆盖第四侧面，进一步增加第一电极和第二电极的正对面积，进一步缩小长条形第一电极的体积。并且将选通晶体管靠近第一电极的第三侧面设置，不需相邻两个电容器之间预留选通晶体管的位置，使得相邻两个电容器之间的间距较小，进一步提高单层存储阵列层所能排布的电容器的数量，从而增大三维存储器的容量。
在第一方面的一种可能的实现方式中，基底为硅基底，选通晶体管的第一极、第二极以及有源层集成于硅基底内，选通晶体管的第一极所电连接的电容器的第一电极与选通晶体管的栅极同层同材料。该方案能够采用同一次构图工艺同时制作电容器的第一电极与选通晶体管的栅极，减少工艺流程，降低制作成本。
在第一方面的一种可能的实现方式中，所述存储阵列层包括多个阵列排布的所述存储结构，能够进一步提高三维存储器的存储容量。
第二方面，本申请一些实施例提供一种芯片封装结构包括封装基板和上述实施例所述的三维存储器。三维存储器设置于封装基板上。由于本申请实施例提供的芯片封装结构包括如上任一技术方案所述的三维存储器，因此二者能够解决相同的技术问题，并达到相同的技术效果，此处不再赘述。
在第二方面的一种可能的实现方式中，芯片封装结构还包括控制芯片，控制芯片设置于封装基板上、且与三维存储器位于同一平面上。或者，控制芯片与三维存储器层叠设置在封装基板上，能够满足不同终端产品的尺寸需求。
第三方面，本申请一些实施例提供一种电子设备，包括主板和上述实施例所述的芯片封装结构。芯片封装结构设置在主板上、且与主板电连接。由于本申请实施例提供的电子设备包括如上任一技术方案所述的芯片封装结构，因此二者能够解决相同的技术问题，并达到相同的技术效果。
附图说明
图1为现有技术DRAM中电容器的结构连接示意图；
图2为本申请一些实施例提供的电子设备的结构示意图；
图3为图2所示电子设备的爆炸图；
图4为图3所示电子设备内主板和芯片封装结构的结构示意图；
图5为图4中所示的芯片封装结构中包括一个芯片的结构示意图；
图6为图4所示的芯片封装结构中包括堆叠设置的两个芯片的结构示意图；
图7为图4所示的芯片封装结构中包括位于同一平面的两个芯片的结构示意图；
图8为图7所示的芯片封装结构中三维存储器的结构示意图；
图9为示例一的三维存储器的三维结构示意图；
图10为对图9中示出的电容器沿第一平面进行剖切得到的剖面示意图；
图11为对第一种图9中示出的电容器沿第二平面进行剖切得到的剖面示意图；
图12为对第二种图9中示出的电容器沿第二平面进行剖切得到的剖面示意图；
图13为图9中A-A的截面示意图；
图14为图9所示的三维存储器的结构示意图；
图15为图9所示的三维存储器中选通晶体管的三维结构示意图；
图16为图9所示的三维存储器中第一种选通晶体管和第一种电容器的结构示意图；
图17为图9所示的三维存储器中第二种选通晶体管和第一种电容器的结构示意图；
图18为图17所示的三维存储器中第二选通晶体管位于第一电极的第三侧面的结构示意图；
图19为图17所示的三维存储器中第二选通晶体管位于第一电极的第四侧面的结构示意图；
图20为图9所示的三维存储器中一个存储单元、字线、位线的连接示意图；
图21为图9所示的三维存储器中N个存储单元、字线、位线的连接示意图；
图22为图9中B-B的截面示意图；
图23为示例二的三维存储器的三维结构示意图；
图24为相关技术中具有存储功能的芯片堆叠结构的结构示意图；
图25为图23中C-C的截面示意图；
图26为图23所示的三维存储器中字线和位线均位于存储阵列层内的结构示意图；
图27为图23所示的三维存储器的结构示意图；
图28为图23中D-D的截面示意图；
图29为图23中所示的三维存储器中N×M个存储单元、M条字线、N条位线的连接示意图；
图30为图23中所示的三维存储器包含有外围电路的连接示意图；
图31为示例三的三维存储器的结构示意图；
图32为示例四的三维存储器的结构示意图；
图33为图32所示的三维存储器的三维结构示意图；
图34为图33中E-E的截面示意图；
图35为图33中F-F的截面示意图；
图36为示例五的电子设备中芯片堆叠结构的结构示意图。
具体实施方式
本申请提供一种电子设备，该电子设备可以包括手机、平板电脑(tablet personal computer)、膝上型电脑(laptop computer)、个人数码助理(personal digital assistant，PDA)、照相机、个人计算机、笔记本电脑、车载设备、可穿戴设备、增强现实(augmented reality，AR)眼镜、AR头盔、虚拟现实(virtual reality，VR)眼镜或者VR头盔等需要存储数据的设备。本申请实施例对上述电子设备的具体形式不做特殊限制。以下为了方便说明，均是以该电子设备为如图2所示的手机为例进行的举例说明。
请参照图2和图3，图2为本申请一些实施例提供的电子设备的立体图，图3为图2所示电子设备的爆炸图。由上述可知，在本实施例中，电子设备1000为手机。电 子设备1000可以包括如图3所示的屏幕100、中框200、后壳300及固定在中框200上的主板400。
可以理解的是，图2和图3仅示意性的示出了电子设备1000包括的一些部件，这些部件的实际形状、实际大小、实际位置和实际构造不受图2和图3的限制。在其他一些示例中，电子设备1000也可以不包括屏幕100。或者，电子设备1000还可以包括如图3所示的摄像头500。
在本申请的一些实施例中，电子设备1000还可以包括如图4所示的芯片封装结构600。该芯片封装结构600设置于该主板400上、且与主板400电连接。例如，芯片封装结构600可以通过焊球阵列(ball grid array，BGA)、或者多个阵列排布的铜柱凸块(copper pillar bump,CPB)与主板400电连接，从而使得芯片封装结构600能够与主板400上其他芯片或者芯片堆叠结构实现信号传输。
需要说明的是，上述主板400可以为印刷电路板(printed circuit board，PCB)。本申请对主板400上的芯片封装结构600的数量不做限制，可以一个、两个或两个以上。
以下对上述芯片封装结构600的结构进行举例说明。请参照图5，芯片封装结构600可以包括封装基板(substrate，SUB)601、设置在封装基板601上的芯片602以及用于塑封芯片602的塑封料(molding)603。该芯片602可以为裸芯片(即裸die)，也可以为芯片堆叠结构(即多个裸die层叠设置)。本申请对封装于芯片封装结构600内的芯片602数量不做限制，可为如图5所示的一个，也可为如图6和图7所示的两个，或者还可以为两个以上。
以下为了方便说明，以如图6和图7所示的芯片封装结构600内封装有两个芯片6021、6022为例进行举例说明。
图6中示出的芯片封装结构600中的一个芯片6021可以为具有数据处理功能的处理芯片，例如为中央处理器(central processing unit，CPU)、片上系统(system on chip，SOC)或者图像处理器(graphics processing unit，GPU)等能够对数据进行处理的芯片。图6中示出的芯片封装结构600中的另一个芯片6022可以为至少具有存储功能的芯片，该芯片可以包括三维存储器。上述具有三维存储器的芯片、上述处理芯片均可以与封装基板601电连接，从而使得上述具有三维存储器的芯片与上述处理芯片可以通过封装基板601进行数据传输。
需要说明的是，至少具有存储功能的芯片是指该芯片可以仅具有存储功能。此时，该芯片为存储芯片。或者，该芯片可以在具有存储功能的同时，还具有其他功能，例如数据处理功能，此时，该芯片为多功能集成芯片。上述三维存储器可为DRAM存储器件，例如双倍速率同步动态随机存储器(double data rate synchronous dynamic random access memory，DDR)、低功耗双倍速率同步动态随机存储器(low power double data rate synchronous dynamic random access memory，LPDDR)等。
在封装基板601上布置两个芯片6021、6022的安装位置时，可以采用如图6中示出的芯片封装结构600中的两个芯片6021、6022堆叠在封装基板601上的布置方式，也可以采用图7示出的两个芯片6021、6022位于同一平面上的布置方式。具体可根据电子设备实际需要，选择两个或两个以上芯片合适的方位布置关系。
需要说明的是，图6和图7中示出的两个芯片是以芯片6021为三维存储器、芯片6022为控制芯片为例进行的说明。当芯片封装结构600中封装有三个芯片602时，其中一个芯片可以为上述具有数据处理功能的处理芯片，另外两个可以均为上述至少具有存储功能的芯片。或者，三个芯片中的两个为上述至少具有存储功能的芯片，三个芯片中的剩余一个为上述具有数据处理功能的处理芯片。多个芯片在封装基板601上的方位布置方式同上所述，此处不再赘述。
以下对上述三维存储器的结构进行进一步的说明。图3所示的三维存储器10包括基底101和存储阵列层102，存储阵列层102包括存储结构1020。其中，基底101，也可以称衬底。基底101可以位于存储阵列层102下方、且用于承载该存储阵列层102。示例的，该基底101可以为单层结构。在此情况下，构成该基底101的材料可以包括半导体材料，诸如硅、锗、砷化镓、磷化铟等。或者，基底101的材料可以包括非导电材料，诸如玻璃、塑料或蓝宝石等。又示例的，上述基底101可以为多层结构。其中，最远离存储阵列层102的一层可以采用上述半导体材料或非导体材料，其余的膜层可以根据需要进行构图工艺，以应用构成其他电路结构。
需要说明的是，上述构图工艺，可指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺。可根据本申请实施例中所形成的结构选择相应的构图工艺。上述光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。
为了方便下文对描述，可以在部分附图中建立X、Y、Z坐标系。如图8所示基底101的所在平面可以为XY平面，以图8中示出的基底101为长方形为例，X轴可以为基底101的长度方向，Y轴可以为基底101的宽度方向，Z轴为垂直于或在制作公差范围内近似垂直于基底101的方向。可以理解的是，基底101的宽度的尺寸小于基底101长度的尺寸。
以下结合不同的示例对本申请实施例中三维存储器10的结构进行详细的说明。
示例一
本示例为采用如图9所示的三维存储器10。该三维存储器10包括一层存储阵列层102，该存储阵列层102包括一个存储结构1020。本示例中的三维存储器10为DRAM，该存储结构1020包括设置于基底101上的N个(图8中以N＝6为例)电容器1，N个电容器1沿第一方向(第一方向为Y轴方向)并排设置，其中，N≥2，N为整数。
图10为采用平行于YZ平面的第一平面P对图9中示出的电容器1进行剖切得到的剖视图。图10中示出的电容器1可以包括第一电极11、第一介电层12以及第二电极13。第一电极11、第一介电层12以及第二电极13沿远离基底101的方向(远离基底101的方向为Z轴方向)依次层叠设置于基底101上。
综上所述，由于本示例提供的三维存储器10中的电容器1包括在基底101上、沿Z轴方向依次层叠设置的第一电极11、第一介电层12以及第二电极13。在此情况下，上述第一电极11、第一介电层12以及第二电极13可以为采用薄膜、曝光、显影、刻蚀工艺依次层叠于基底101上的薄膜层。这种结构设计能够减小电容器1在垂直于基底101的方向上的尺寸。在此基础上，上述存储结构1020包括并排设置于基底101上 的N个电容器1，这样一来，在与基底101的承载面(与XY面平行)平行的方向上，能够设置N个电容器1。在此情况下，相对于图1所示的圆柱形电容器01而言，由于该电容器1沿Z方向的尺寸较大，而本示例中电容器1在Z方向的尺寸较小。因此，本示例中三维存储器10能够在基底101上叠加多层上述存储阵列层102，即电容器1设置有多层，从而在有限的布件空间内，提高三维存储器10的存储容量，使得在进入1xnm(第一代10nm级工艺)之后能够实现DRAM芯片内的扩容。并且薄膜结构的电容器1的制作工艺难度较低，从而制作多层存储阵列层102的制作工艺难度也较低。三维存储器10中的多个电容器1一致性较好、且缺陷态低，使得三维存储器10中的电子器件不良率较低，电子器件的可靠性较高。
并且，本示例中的电容器1可以采用14nm、10nm、7nm及以下(芯片中晶体管的最小线宽)的较为先进的工艺制备，能够获得尺寸较小、容量较高的三维存储器。
需要说明的是，本示例的电容器1中的第一电极11的制作材料与第二电极13的制作材料可相同，也可或不同。例如，第一电极11的制作材料和第二电极13的制作材料均为钴(Co)、氮化钛(TiN)或多晶硅等材料中的任一种。而本示例中电容器1的第一介电层12所采用的材料为High-k(高介电常数)介电材料。例如，氧化铝(Ai2O3)、氧化铪(HfO2)、或锆-铝组成的多层材料中的任一种等。其中，上述High-k介电材料是指介电常数K大于3.9的材料。
在设计电容器11的形状时，同样考虑到半导体制作工艺因素的影响，继续参照图10，本示例中第一电极11的第一截面为梯形，若在基底101上采用刻蚀及沉积等工艺步骤制作电容器1，由于第一电极11的四个边角W处的拐角较为平滑，所以，能够减少第一电极11的边角W处出现缺陷态，电容器1的合格率较高。可以理解的是，第一电极11的形状也可以为其他方便制作的形状，如第一电极11的第一截面为半圆柱形。
由于电容器1中第一介电层12和第二电极13覆盖第一电极11的面积应尽可能较大，才能够增加第一电极11与第二电极13之间的正对面积。从而，在保证电容器1的电容量满足存储数据需求，电容器1的体积较小，能够增加存储阵列层102上可分布的电容器1的数量。因此，本示例的电容器1采用如图10所示的结构，第一介电层12覆盖第一电极11远离基底101的表面(即第一电极11的上表面111)、以及第一电极11的侧面112。第二电极13覆盖在第一介电层12远离基底101的表面(即第一介电层12的上表面121)、以及第一介电层12的侧面122。图10示出的电容器1中第一电极11与第二电极13之间的正对面积较大。
需要说明的是，本示例对第一介电层12和第二电极13覆盖第一电极11的面积不做限制，也可设计电容器1中的第一介电层12仅覆盖在第一电极11的上表面111，第二电极13仅覆盖第一介电层12的上表面121。
可以理解的是，第一介电层12和第二电极13覆盖在第一电极11的侧面112面积越大，第一电极11和第二电极13之间的正对面积越大，电容器1的体积可制作的越小，存储阵列层102上所能分布的电容器1的数量越多。
对于不同形状的电容器1，电容器1中第一电极11的侧面数量不同。图9示出的电容器1为设置在基底101上的长条形凸起结构，也可称为横卧式鳍形结构。其中， 横卧式是指沿平行于基底101所在平面设置；上述基底101上的N个电容器1可看作为如图9所示的设置在基底101上的横卧式多鳍结构。
图11为采用平行于X-Z平面的第二截面Q对图9所示的一种横卧式鳍形电容器进行剖切得到的剖视图。图12为采用平行于X-Z平面的第二截面Q对图9所示的另一种横卧式鳍形的电容器进行剖切得到的剖视图。图11和图12中示出的电容器1的第一电极11的第二截面Q均为长方形。
结合图10、图11和图12所示的两种横卧式鳍形电容器中的第一电极11的112侧面均为4个，第一电极11的4个侧面112可以分别为均沿X轴方向延伸的第一侧面112a和第二侧面112b、以及均沿Y轴方向延伸的第三侧面112c和第四侧面112d。相应地，第一介电层12的侧面122也有4个，第一介电层12的4个侧面122分别为均沿X轴方向延伸的第五侧面122a和第六侧面122b、以及均沿Y轴方向延伸的第七侧面122c和第八侧面122d。
在图10和图11所示的横卧式鳍形电容器中，第一介电层12覆盖第一电极11的上表面111、第一电极11的第一侧面112a和第一电极11的第二侧面112b。第二电极13覆盖第一介电层12的的上表面121、第一介电层12的第五侧面122a和第一介电层12的第六侧面122b。由于第一介电层12和第二电极13能够覆盖横卧式鳍形电容器沿长度方向延伸的第一侧面112a和第二侧面112b，使得第一电极11与第二电极13之间的正对面积较大。而第一电极11的第三侧面112c和第四侧面112d均处于裸露状态，能够便于从第一电极11的第三侧面112c与存储结构1020中的其他器件电连接，或从第一电极11的第四侧面112d与存储结构1020中的其他器件电连接。
在图10和图12所示的横卧式鳍形电容器中，第一介电层12覆盖第一电极11的上表面111、第一电极11的第一侧面112a、第一电极11的第二侧面112b及第一电极11的第四侧面112d，第二电极13覆盖第一介电层12的第五侧面122a、第一介电层12的第六侧面122b和第一介电层12的第八侧面122d。由于第一介电层12和第二电极13能够依次覆盖长条形的电容器1沿长度方向延伸的第一侧面112a和第二侧面112b、以及沿宽度方向延伸的第四侧面112d，第一介电层12和第二电极13能够覆盖长条形的电容器1的侧面数量多、且面积大，使得第一电极11与第二电极13之间的正对面积较大。并且第一电极11的第三侧面112c均处于裸露状态，能够便于从第一电极11的第三侧面112c与存储结构1020中的其他器件电连接。
图13为图9的A-A截面图。为了便于制作，本示例的存储结构1020中的N个电容器1的第一介电层12采用如图13所示的相连接为一体的结构。N个电容器1的第一介电层12能够采用一道工艺(如薄膜沉积工艺)制作，工艺简单，降低了制作成本。
基于此，为了能够向电容器1内写入数据，或者，从电容器1中读取数据，上述存储结构1020可以还包括如图14所示的选通晶体管2，选通晶体管2与电容器1电连接。当选通晶体管2选通时，在电容器1内写入数据或者从电容器1读出数据。当选通晶体管2截止时，停止从电容器1读出数据。
需要说明的是，本示例中的选通晶体管2可为金属-氧化物-半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET，MOS管是MOSFET的简称)。该MOS管可以包括如图15所示的第一极21、第二极22以及栅极23。选通晶 体管2的第一极21与电容器1的第一电极11电连接，如图16所示。其中，当向该MOS管的栅极23提供的选通信号为有效信号时，该MOS管处于导通状态，此时MOS管的第一极21和第二极22电连接。当向该MOS管的栅极23提供的选通信号为非有效信号时，该MOS管处于截止状态，此时MOS管的第一极21和第二极22断开。图15示出的选通晶体管2为鳍式场效应晶体管(fin field-effect transistor，FinFET)。
本示例对上述MOS管的类型不做限定，上述MOS管可以为N型管，此时选通信号为有效信号可以为高电平，非有效信号可以为低电平。反之，上述MOS管可以为P型管，此时选通信号为有效信号可以为低电平，非有效信号可以为高电平。此外，上述选通晶体管2的第一极21可以为源极(source，S)，此时，选通晶体管2的第二极22可以为漏极(drain，D)。或者，上述选通晶体管2的第一极21可以为漏极，此时，选通晶体管2的第二极22可以为源极。
根据基底101材料的不同，本示例三维存储器10中的选通晶体管2的整体或部分被形成在基底101中，如图16所示。或者，选通晶体管2的整体直接被形成在基底101上。例如，基底101为硅基底，选通晶体管2的源极、漏极及有源层被集成在基底101内，选通晶体管2的栅极23被形成在基底101上，如图16所示。选通晶体管2能够通过多个过程来形成，包括但不限于:光刻、干/湿蚀刻、薄膜沉积、热生长、注入、化学机械抛光、以及任何其他合适的过程。例如，通过离子注入和/或热扩散在硅基底中形成掺杂区域，其例如用作选通晶体管2的源极区域和/或漏极区域。
并且，图16示出的选通晶体管2的栅极23与电容器1的第一电极11同层设置，电容器1的第一电极11可以与选通晶体管2的栅极23同层同材料，例如钴(Co)、氮化钛(TiN)或多晶硅等材料中的任一种，使得选通晶体管2的栅极23和电容器1的第一电极11能够采用同一次构图工艺同时制作电容器1的第一电极11与选通晶体管2的栅极23。从而，减少了工艺流程次数，降低了制作成本。当然，选通晶体管2的栅极23的材料与电容器1的第一电极11的材料也可不同，在此不做限制，具体可根据实际需要选择。
需要说明的是，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，同一构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。其中，本示例中的一次构图工艺，是以通过一次掩膜曝光工艺形成不同的曝光区域，然后对不同的曝光区域进行多次刻蚀、灰化等去除工艺最终得到预期图案为例进行的说明。
对于基底101为非金属材料，整个选通晶体管2可以被形成在基底101上，并且整个电容器1可以与选通晶体管2均同层设置，如图17所示。
根据不同形状的电容器1，可将选通晶体管2设置在基板上不同的安装位置。
在图16和图17示出的电容器1中第一电极11的4个侧面中，仅第三侧面112c处于裸露状态的方案。因此，将选通晶体管2的第一极21可以靠近第一电极11的第三侧面112c设置。由于选通晶体管2设置在横卧式鳍形电容器的第一电极11宽边所在的一侧，所以，不需在相邻两个电容器1之间预留选通晶体管2的位置，使得相邻 两个电容器1之间的间距较小。并且进一步提高了存储阵列层102能够布置的电容器1的数量，从而提高了三维存储器10的存储容量。
在图18和图19示出的横卧式鳍形电容器中，第一电极11的4个侧面中第三侧面112c和第四侧面112d均处于裸露状态的方案。图18示出的选通晶体管2的第一极21靠近横卧式鳍形电容器的第一电极11的第三侧面112c设置。图19示出的选通晶体管2的第一极21靠近横卧式鳍形电容器的第一电极11的第四侧面112d设置。同理，图18和图19所示的方案也将选通晶体管2设置在横卧式鳍形电容器的第一电极11宽边所在的一侧。因此，同样能够提高存储阵列层102能够布置的电容器1的数量，进而提高三维存储器10的存储容量。
本示例中的三维存储器10还包括如图20所示的字线(wordline,WL)3和位线(bitline,BL)4，字线3与选通晶体管2的栅极23电连接，位线4与选通晶体管2的第二极22电连接。字线3用于给选通晶体管2的栅极23输入选通信号，位线4用于当选通晶体管22选通时，读取电容器1中的存储数据，或给电容器1内写入存储数据。
基于此，为了让一个选通晶体管2对应一个电容器1，从而可以对每个电容器1独立进行读取和写入数据。本示例存储结构1020中的选通晶体管2也为N个，N个选通晶体管2的第一极21分别与N个电容器1的第一电极11一一对应电连接，以形成N个图21所示的存储单元1021。
相应地，本示例存储结构1020中的字线3为一条，位线4为N条。字线3与N个选通晶体管2的栅极23均电连接，N个位线4分别与N个选通晶体管2的第二极22一一对应电连接。相应地，字线3、位线4设置在靠近选通晶体管2的位置，以便于缩短字线3、位线4的长度。
上述位线4的制作材料为钨制作，位线4也能够采用蚀刻、沉积或增长等工艺制作。图22为图9的B-B截面图。基于以上，在本示例中，字线3设置于选通晶体管2的有源层远离基底101的一侧，并且字线3与有源层搭接的部分作为选通晶体管2的栅极23，如图22所示，便于采用一次构图工艺同时制作字线3和N个选通晶体管2的栅极23，简化工艺步骤。并且，字线3与选通晶体管2的栅极23的制作材料相同。当然，字线3也可单独制作，本示例对此不做限制。
可以理解的是，对于选通晶体管2的栅极23与电容器1的第一极21同层同材料的方案，若字线3与有源层搭接的部分作为选通晶体管2的栅极23，则能够采用一次构图工艺同时制作选通晶体管2的栅极23、电容器1的第一极21及字线3。
示例二
本示例为将如图9所示的一层存储阵列层102沿Z轴方向层叠M层的三维存储器10。其中，M≥2，M为整数。图23示出的三维存储器10层叠有4层(即M＝4)上述存储阵列层102。
相较于采用图1所示的圆柱形电容器01的三维存储器，该三维存储器中仅可设置单层电容器，而本示例中的三维存储器10中的电容器1具有多层(如一百层以上)，能够在有限布件空间内，存储更多的数据，使得三维存储器10的容量较大。并且薄膜层结构的电容器1的制作工艺难度较低，降低了制作多层存储阵列层102的制作工艺 难度。因此，所制作的三维存储器10中的多个电容器1一致性较好、且缺陷态低。从而，三维存储器10中的电子器件不良率也较低，电子器件的可靠性较高。
并且相较于如图24所示的相关技术，该技术为直接将多个减薄后的存储芯片(裸die)02堆叠键合得到的高带宽存储器(high bandwidth memory，HBM)。而本示例中的三维存储器10能够实现在同一裸die里面制作多层存储阵列层结构，实现了通过在裸die内的存储结构的三维堆叠，提高三维存储器10的容量。
图25为图23中的C-C截面示意图。对于具有M层存储阵列层102的方案，将相邻的两层存储阵列层102电隔离，如将上层电容器中的第一电极11与下层电容器中的第二电极13电隔离开。因此，本示例的三维存储器10还包括图25所示的第二介电层103，第二介电层103位于相邻的两层存储阵列层102之间，第二介电层103能够实现相邻的两层存储阵列层102电隔离。需要说明的是，上述第二介电层103可采用金属间介电层(inter-metal-dielectric，IMD)介电材料，如二氧化硅(SiO2)等材料。
在制作三维存储器10时，可以先在基底101上通过向上生长、外延、刻蚀、沉积等工艺步骤形成一层存储阵列层102后，再在该层存储阵列层102上形成第二介电层103，之后在第二介电层103上形成另一层存储阵列层102，如此往复进行，从而在每个基底101上形成一百层以上的存储阵列层102。由于上述形成多层存储阵列层102可采用相同的光罩，能够降低三维存储器10的工艺成本。
本示例的三维存储器10中的字线3和位线4的设置位置，可采用如图26所示的字线3、位线4均位于存储阵列层102内的方案。每一层存储阵列层102中的字线3与该层内的选通晶体管2电连接。每一层存储阵列层102中的位线4与该层内的选通晶体管2电连接。
或者，本示例三维存储器10中的任一存储阵列层102包括与该层上的N个选通晶体管2的栅极23电连接的字线3，而采用如图27所示的位线4结构。该三维存储器10中的位线4为N个，N个位线4分别贯穿M层存储阵列层102、且与M层存储阵列层102中位于同一位置的M个选通晶体管2的第二极22电连接。其中，同一位置的M个选通晶体管2在基底101上的垂直投影重叠，位线4为如图28所示的贯穿M层(图28中M＝4)存储阵列层102来连接不同层的电容器1的第二电极13的通孔结构。由于不同层之间的选通晶体管2间距较短，所以，能够缩短所需位线4的长度。
图29所示的三维存储器10中字线3为M条，位线4为N条。每层存储阵列层102包括N个选通晶体管2和N个电容器1，N个选通晶体管2的第一极21分别与N个电容器1的第一电极11一一对应电连接，以形成N个图29所示的M×N个存储单元1021。
本示例的三维存储器10还包括图30所示的外围电路104。外围电路104包括读写选通电路1041(例如，字线选通电路sub-word-line，SWL)、地址译码器(例如，行解码器和列解码器)1042、信号放大电路(sense-amplitute，S/A)1043等。地址译码器1042与读写选通电路1041电连接，读写选通电路1041与字线3电连接，信号放大电路1043与位线4电连接。
地址译码器1042接收到读取指令后，根据读取指令中包含的地址信息，通过读写选通电路1041对该地址对应的字线3进行选通。之后位线4读出字线3选通对应的电 容器1中包含的数据，并通过信号放大电路1043将数据信号进行放大。地址译码器1042接收到写入指令后，根据写入指令中包含的地址信息，通过读写选通电路1041对该地址对应的字线3进行选通，之后位线4给对应的电容器1内写入数据。
需要说明的是，上述外围电路104可以形成在基底101上，并且可以位于基底101的边沿位置。外围电路104可以与最底层的存储阵列层102同层设置。外围电路104的制作工艺同样能够通过多个过程来形成，包括但不限于：光刻、干/湿蚀刻、薄膜沉积、热生长、注入、化学机械抛光、以及任何其他合适的过程。上述字线3和位线4可以通过通孔互联结构与基底101上外围电路104电连接。
示例三
本示例为如图31示出的三维存储器10。该三维存储器10与示例一中的三维存储器结构类似，区别在于：存储阵列层102上包括S个存储结构1020，S个存储结构1020排列排布。其中，S≥2，S为整数。
由于本示例包含与示例一相同的结构，所以，能够获得与示例一相同的技术效果。并且，本示例中每层存储阵列层102包括上述S个阵列排布的存储结构1020，即每层存储阵列层102所包含的电容器1数量越多，能够满足在平行于XY平面上尺寸较大的终端产品提高存储容量的需求。
需要说明的是，本示例中存储阵列层102上的存储结构1020的数量在此不做限制。图31示出的三维存储器10中存储阵列层102包括4个(S＝4)存储结构1020，4个存储结构1020沿矩形阵列排布。当然，存储阵列层102上的S个存储结构1020也可沿圆形阵列排布。
示例四
本示例为将如图31所示的一层存储阵列层102沿Z轴方向层叠M层的三维存储器10。图32和图33是以三维存储器10层叠有4层(M＝4)存储阵列层102为例。
图34为图33的E-E截面示意图，图35为图33的F-F的截面示意图。结合图32、图33和图34可知，由于本示例包含与示例三相同的结构，所以，能够获得与示例三相同的技术效果。并且，本示例三维存储器10中的电容器1具有多层，能够存储更多的数据，使得三维存储器10的容量进一步提高。
示例五
本示例为设置有如图36所示的芯片堆叠结构的电子设备，芯片堆叠结构可以位于该电子设备内的主板上。该芯片堆叠结构为将多个如图32所示的三维存储器10(裸die)堆叠设置，并且多个三维存储器10之间可以通过通孔键合的方式电连接，从而进一步提高电子设备的存储容量，并实现电子设备的高带宽存储。图36是以芯片堆叠结构中的裸芯片有4个为例。当然，本示例的芯片堆叠结构也可包含在芯片封装结构内。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技 术方案的精神和范围。

Claims (15)

  1. 一种三维存储器，其特征在于，包括：
    基底；
    存储阵列层，所述存储阵列层包括至少一个存储结构，所述存储结构包括并排设置于所述基底上的N个电容器，所述电容器包括沿远离所述基底的方向、依次层叠设置于所述基底上的第一电极、第一介电层以及第二电极；其中，N≥2，N为整数。
  2. 根据权利要求1所述的三维存储器，其特征在于，所述第一介电层覆盖所述第一电极远离所述基底的表面、以及所述第一电极的至少一个侧面；
    所述第二电极覆盖所述第一介电层远离所述基底的表面、以及所述第一介电层的至少一个侧面；其中，相邻的两个所述电容器的第二电极间隔设置。
  3. 根据权利要求2所述的三维存储器，其特征在于，所述N个电容器的第一介电层相连接为一体结构。
  4. 根据权利要求1所述的三维存储器，其特征在于，所述三维存储器包括沿垂直于所述基底的方向、层叠设置的M层所述存储阵列层；其中，M≥2，M为整数；
    所述三维存储器还包括第二介电层，所述第二介电层位于相邻的两层所述存储阵列层之间。
  5. 根据权利要求2-4任一项所述的三维存储器，其特征在于，所述N个电容器沿第一方向并排设置，所述第一电极的第一截面为梯形，其中，所述第一截面与所述第一方向平行、且与所述基底垂直。
  6. 根据权利要求5所述的三维存储器，其特征在于，所述存储结构还包括：
    N个选通晶体管，一个所述选通晶体管的第一极与一个所述电容器的第一电极电连接；
    字线，与所述N个选通晶体管的栅极电连接；
    位线，与所述N个选通晶体管的第二极电连接。
  7. 根据权利要求5所述的三维存储器，其特征在于，所述存储结构还包括：
    N个选通晶体管，一个所述选通晶体管的第一极与一个所述电容器的第一电极电连接；
    字线，与所述N个选通晶体管的栅极电连接；
    所述三维存储器还包括沿垂直于所述基底的方向、层叠设置的M层所述存储阵列层，其中，M≥2，M为整数；所述三维存储器还包括：
    N条位线，所述位线贯穿所述M层所述存储阵列层、且与所述M层存储阵列层中位于同一位置的M个所述选通晶体管的第二极电连接；其中，同一位置的M个所述选通晶体管在所述基底上的垂直投影重叠。
  8. 根据权利要求6或7所述的三维存储器，其特征在于，所述字线设置于所述选通晶体管的有源层远离所述基底的一侧，所述字线与所述有源层搭接的部分作为所述选通晶体管的栅极。
  9. 根据权利要求6或7所述的三维存储器，其特征在于，所述第一电极的第二截面为长方形；其中，所述第二截面与所述第一方向、所述基底均垂直，所述长方形的 长度方向与所述第一方向垂直、且与所述基底平行；
    所述第一电极的侧面包括与第二方向平行的第一侧面和第二侧面，其中，所述第二方向与所述第一方向垂直；
    所述第一介电层和所述第二电极依次覆盖所述第一侧面和所述第二侧面。
  10. 根据权利要求9所述的三维存储器，其特征在于，所述第一电极的侧面还包括与所述第一方向均平行的第三侧面和第四侧面，所述第三侧面靠近所述选通晶体管设置、且与所述选通晶体管的第一极电连接，所述第一介电层和所述第二电极还依次覆盖所述第四侧面。
  11. 根据权利要求6-10中任一项所述的三维存储器，其特征在于，所述基底为硅基底；
    所述选通晶体管的第一极、第二极以及有源层集成于所述硅基底内，所述选通晶体管的第一极所电连接的电容器的第一电极与所述选通晶体管的栅极同层同材料。
  12. 根据权利要求1-7中任一项所述的三维存储器，其特征在于，所述存储阵列层包括多个阵列排布的所述存储结构。
  13. 一种芯片封装结构，其特征在于，包括：
    封装基板；
    如权利要求1-12中任一项所述的三维存储器，所述三维存储器设置于所述封装基板上。
  14. 根据权利要求13所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：
    控制芯片，所述控制芯片设置于所述封装基板上、且与所述三维存储器位于同一平面上，或者，所述控制芯片与所述三维存储器层叠设置在所述封装基板上。
  15. 一种电子设备，其特征在于，包括：
    主板；
    如权利要求13或14所述的芯片封装结构，所述芯片封装结构设置在所述主板上、且与所述主板电连接。
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