WO2022267008A1 - 显示基板、拼接显示面板和显示装置 - Google Patents

显示基板、拼接显示面板和显示装置 Download PDF

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Publication number
WO2022267008A1
WO2022267008A1 PCT/CN2021/102386 CN2021102386W WO2022267008A1 WO 2022267008 A1 WO2022267008 A1 WO 2022267008A1 CN 2021102386 W CN2021102386 W CN 2021102386W WO 2022267008 A1 WO2022267008 A1 WO 2022267008A1
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Prior art keywords
light emitting
pixel unit
emitting diode
diode chip
display
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Ceased
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PCT/CN2021/102386
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English (en)
French (fr)
Inventor
李伟
王灿
张粲
肖丽
玄明花
袁丽君
牛晋飞
张晶晶
袁广才
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/778,540 priority Critical patent/US12237316B2/en
Priority to PCT/CN2021/102386 priority patent/WO2022267008A1/zh
Priority to CN202180001624.3A priority patent/CN115735433B/zh
Priority to EP21946502.8A priority patent/EP4207302B1/en
Publication of WO2022267008A1 publication Critical patent/WO2022267008A1/zh
Anticipated expiration legal-status Critical
Priority to US19/012,172 priority patent/US20250149522A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/352—Active-matrix LED displays characterised by differences in geometry or arrangement of elements, subpixels or pixels in different regions of the display, e.g. at the central and peripheral regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/80—Constructional details
    • H10H29/832—Electrodes
    • H10H29/8321—Electrodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01551—Changing the shapes of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
    • H10W72/07304—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H10W72/07307—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating the auxiliary member being a temporary substrate, e.g. a removable substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07502—Connecting or disconnecting of bond wires using an auxiliary member
    • H10W72/07504—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H10W72/07507—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating the auxiliary member being a temporary substrate, e.g. a removable substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347—Dispositions of multiple die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5366—Shapes of wire connectors the bond wires having kinks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/755—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a laterally-adjacent insulating package substrate, interpose or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a spliced display panel and a display device.
  • the light emitting diode (Light Emitting Diode, English abbreviation is LED) technology has been developed for nearly 30 years, and its application range is continuously expanding. For example, it can be used in the display field, as a backlight source for a display device or as an LED display.
  • the sub-millimeter light-emitting diode (Mini Light Emitting Diode, English abbreviation is Mini LED) display technology and micro light-emitting diode (Micro Light Emitting Diode, English abbreviation is Micro LED) display technology has gradually become a hot spot for display devices.
  • LED has the advantages of self-illumination, wide viewing angle, fast response, simple structure, and long life.
  • Mini LED/Micro LED displays can be spliced to achieve large-size displays, so they have good market prospects.
  • the structure and manufacturing process of Mini LED/Micro LED display devices are one of the important topics that researchers are concerned about.
  • a display substrate including: a base substrate, the base substrate includes at least one side edge and a display area; a plurality of pixel units arranged in the display area, the plurality of pixel units include The first pixel unit, the second pixel unit and the third pixel unit located in the display area, wherein the plurality of second pixel units are located on the side of the plurality of first pixel units close to the side edge, so The edges of the plurality of second pixel units include the side edges, the third pixel unit is located between the first pixel unit and the second pixel unit, and the third pixel unit is adjacent to the second pixel unit; and a plurality of light emitting diode chips arranged on the base substrate, the plurality of light emitting diode chips including a first light emitting diode chip and a second light emitting diode chip, wherein the first light emitting diode chip is located on the In the first pixel unit, a part of the second light emitting diode chip is located in the second
  • the shortest distance between the second light emitting diode chip and the boundary near the side edge of the second pixel unit where a part of the second light emitting diode chip is located is greater than that of the first light emitting diode chip The shortest distance from the edge of the first pixel unit where the first LED chip is located.
  • the area of the orthographic projection of the part of the second light emitting diode chip located in the second pixel unit on the substrate is smaller than that of the first light emitting diode chip on the substrate The area of the orthographic projection on the substrate.
  • the area of the orthographic projection of the second light emitting diode chip on the base substrate is larger than the area of the orthographic projection of the first light emitting diode chip on the base substrate, and the The area of the orthographic projection of the second light emitting diode chip on the base substrate is less than twice the area of the orthographic projection of the first light emitting diode chip on the base substrate.
  • the plurality of pixel units further include a fourth pixel unit, a fifth pixel unit, a sixth pixel unit, and a seventh pixel unit located in the display area, and the fourth pixel unit
  • the edge includes a first side edge and a second side edge intersecting each other, and the fifth pixel unit, the sixth pixel unit and the seventh pixel unit are respectively adjacent to the fourth pixel unit;
  • the plurality of light emitting diode chips further include A third light emitting diode chip, a part of the third light emitting diode chip is located in the fourth pixel unit, and other parts of the third light emitting diode chip are respectively located in the fifth pixel unit, the sixth pixel unit and the seventh pixel unit.
  • the shortest distance between the third light emitting diode chip and the boundary near the side edge of the third pixel unit where a part of the third light emitting diode chip is located is greater than that of the first light emitting diode chip The shortest distance from the edge of the first pixel unit where the first LED chip is located.
  • the area of the orthographic projection of the part of the third light emitting diode chip located in the fourth pixel unit on the substrate is smaller than the area of the first light emitting diode chip on the substrate. The area of the orthographic projection on the substrate.
  • the area of the orthographic projection of the third light emitting diode chip on the base substrate is larger than the area of the orthographic projection of the first light emitting diode chip on the base substrate, and the The area of the orthographic projection of the third light emitting diode chip on the base substrate is less than four times the area of the orthographic projection of the first light emitting diode chip on the base substrate.
  • the light emitting diode chip includes a substrate, a plurality of light emitting regions, a plurality of anodes and a cathode disposed on the substrate, the plurality of light emitting regions correspond to the plurality of anodes one by one, The plurality of light emitting regions are arranged at intervals from each other.
  • the light emitting diode chip further includes a cathode pad electrically connected to the cathode, and the cathode pad and the plurality of light emitting regions are spaced apart from each other.
  • some of the plurality of light emitting regions of the second light emitting diode chip are located in the second pixel unit, and some of the plurality of light emitting regions are located in the third pixel unit , the number of light emitting regions of the second light emitting diode chip is greater than the number of light emitting regions of the first light emitting diode chip.
  • some of the plurality of light emitting regions of the third light emitting diode chip are located in the fourth pixel unit, and others of the plurality of light emitting regions are respectively located in the five pixel unit, In the sixth pixel unit and the seventh pixel unit, the number of light emitting regions of the third light emitting diode chip is greater than the number of light emitting regions of the second light emitting diode chip.
  • the orthographic projection of the cathode pad of the second LED chip on the substrate is located at the junction of the second pixel unit and the third pixel unit.
  • the orthographic projection of the cathode pad of the third light emitting diode chip on the substrate is located at the fourth pixel unit, the fifth pixel unit, the sixth pixel unit and the The junction of the seventh pixel unit.
  • the distance between the plurality of light emitting regions of the light emitting diode chip is greater than 8 microns.
  • the display substrate further includes a wiring area located at least one of the side edges; the display substrate further includes a plurality of wires located in the wiring area, the plurality of The wires are used to respectively provide electrical signals to the plurality of light emitting diode chips.
  • the display substrate further includes a plurality of light conversion parts, and the orthographic projections of the plurality of light conversion parts on the base substrate are the same as those of the plurality of light emitting regions on the base substrate.
  • the orthographic projections on are at least partially overlapping.
  • a spliced display device including: a plurality of first display substrates and a plurality of second display substrates, wherein the plurality of first display substrates and the plurality of second display substrates are respectively as described above
  • the display substrate wherein, the side edge of the first display substrate is spliced with the side edge of the second display substrate along the first direction, and/or, the side edge of the first display substrate is joined with the side edge of the second display substrate along the second direction
  • the side edges of the second display substrate are spliced together, and the first direction intersects with the second direction.
  • the first display substrate and the second display substrate are distributed axially symmetrically along the joint, and the joint includes the side edge of the first display substrate close to the second substrate and the second display substrate.
  • the display substrate is close to the side edge of the first display substrate.
  • a display device comprising: the above-mentioned spliced display panel; and a driving circuit for driving the spliced display panel.
  • FIG. 1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 2 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 3 is a partially enlarged view of a first light emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 4 is a partially enlarged view of a second light emitting diode chip or a fourth light emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 5 is a partially enlarged view of a third light emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 6 is a cross-sectional view of the display substrate taken along line AA' in FIG. 3 , FIG. 4 or FIG. 5 according to some exemplary embodiments of the present disclosure
  • FIG. 7 is a cross-sectional view of a display substrate taken along line BB' in FIG. 2 according to some exemplary embodiments of the present disclosure
  • 8A to 8G are cross-sectional views schematically illustrating the structure formed after some steps of the manufacturing method of the display substrate are performed;
  • FIG. 9 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure.
  • FIG. 10 is a cross-sectional view of a display panel taken along line CC' in FIG. 5 according to some exemplary embodiments of the present disclosure
  • 11A and 11B are partial plan views of display panels according to other exemplary embodiments of the present disclosure, respectively;
  • FIG. 12 is a partially enlarged view of a display substrate at part I in FIG. 2 according to some exemplary embodiments of the present disclosure.
  • Fig. 13 schematically shows a schematic plan view of a third light emitting diode chip according to some exemplary embodiments of the present disclosure.
  • connection may refer to a physical connection, an electrical connection, a communicative connection, and/or a fluid connection.
  • the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a wider sense.
  • the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • X, Y, and Z and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as meaning only X, only Y, only Z, or Any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • an inorganic light-emitting diode refers to a light-emitting element made of inorganic materials, wherein an LED means an inorganic light-emitting element different from an OLED.
  • the inorganic light emitting element may include a submillimeter light emitting diode (Mini Light Emitting Diode, English abbreviation is Mini LED) and a micro light emitting diode (Micro Light Emitting Diode, English abbreviation is Micro LED).
  • Mini LED Mini Light Emitting Diode
  • Micro LED Micro Light Emitting Diode
  • Micro LED refer to ultra-small light-emitting diodes with a grain size below 100 microns
  • sub-millimeter light-emitting diodes i.e. Mini LEDs
  • the grain size of Mini LED can be between 100 and 300 microns
  • the grain size of Micro LED can be between 10 and 100 microns.
  • a display substrate includes: a base substrate including at least one side edge and a display area; a plurality of pixel units arranged in the display area, the plurality of pixel units including the The first pixel unit, the second pixel unit and the third pixel unit of the display area, wherein the plurality of second pixel units are located on the side of the plurality of first pixel units close to the side edge, and the plurality of The edge of the second pixel unit includes the side edge, the third pixel unit is located between the first pixel unit and the second pixel unit, the third pixel unit is adjacent to the second pixel unit; and A plurality of light emitting diode chips arranged on the base substrate, the plurality of light emitting diode chips include a first light emitting diode chip and a second light emitting diode chip, wherein the first light emitting diode chip is located in the first pixel
  • a plurality of light emitting diode chips include a first light emitting diode chip and a second light emitting dio
  • some embodiments of the present disclosure provide a display substrate, including: a base substrate, the base substrate includes a first side edge and a first region away from the first side edge; A plurality of pixel units on the base substrate, the plurality of pixel units include a first pixel unit located in the first region and a second pixel unit near the first side edge, the first pixel unit located in the The side of the second pixel unit away from the edge of the first side; a plurality of light-emitting diode chips arranged on the base substrate, the plurality of light-emitting diode chips include a first light-emitting diode chip and a second light-emitting diode chip, Wherein, the first light emitting diode chip is located in the first pixel unit, at least a part of the second light emitting diode chip is located in the second pixel unit, wherein the second pixel unit includes The boundary of the second pixel unit on one side edge, the second light emitting diode chip includes a second chip
  • a larger splicing distance can be reserved at the side edges of the display substrates, which is beneficial to the splicing of multiple display substrates.
  • Wire bonding is a process that uses heat, pressure or ultrasonic energy to tightly bond metal bonding wires to substrate pads.
  • wire bonding can be used to connect the pads of the semiconductor chip with the I/O bonding wires of the microelectronic package or the metal wiring pads on the substrate with metal filaments.
  • the principle of wire bonding is to destroy the oxide layer and pollution on the surface to be welded by means of heating, pressure or ultrasonic waves, and produce plastic deformation, so that the metal bonding wire is in close contact with the surface to be welded, reaching the range of gravitational force between atoms and causing the interface Interatomic diffusion to form a solder joint.
  • FIG. 1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure.
  • the display substrate may include: a base substrate 1 ; a plurality of pixel units PX disposed on the base substrate 1 ; and a plurality of light emitting diode chips 5 disposed on the base substrate 1 .
  • the plurality of LED chips 5 includes a first LED chip 51 and a second LED chip 52 .
  • the second light emitting diode chip 52 is disposed in the pixel unit close to the side edge of the display substrate, and the first light emitting diode chip 51 is disposed in the pixel unit far from the side edge of the display substrate.
  • the display substrate may be used as a display substrate of a spliced display panel.
  • the splice region PJ is schematically shown on the upper side, the right side and the lower side of the display substrate.
  • the second light emitting diode chip 52 may be disposed in the pixel unit PX near the junction area PJ.
  • the plurality of LED chips 5 includes a second LED chip 52 and a fourth LED chip 53 .
  • the second LED chip 52 can be arranged in the pixel unit near the splicing area of the right edge
  • the fourth LED chip 53 can be arranged in the pixel unit of the splicing area near the upper edge and the lower edge.
  • references such as specifications and dimensions of the second light emitting diode chip 52 and the fourth light emitting diode chip 53 may be basically the same, but when placed on the base substrate 1, the second light emitting diode chip 52 may be compared to the fourth light emitting diode chip 53
  • the light emitting diode chip 53 is rotated by a certain angle, for example, by 90°.
  • references such as specifications and sizes of the second light emitting diode chip 52 and the fourth light emitting diode chip 53 may be basically the same, therefore, in other parts, for the convenience of description, the second light emitting diode chip 52 and the fourth light emitting diode chip
  • the four LED chips 53 may be collectively referred to as the second LED chips.
  • the plurality of LED chips 5 includes a third LED chip 54 .
  • the third light emitting diode chips 54 may be disposed in pixel units close to the stitching area and close to each corner of the display substrate. In the embodiment shown in FIG. 1 , the third light emitting diode chips 54 may be respectively disposed at the upper right corner and the lower right corner of the display substrate.
  • FIG. 2 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 3 is a partially enlarged view of a first light emitting diode chip included in the display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 4 is a partially enlarged view of a second light emitting diode chip or a fourth light emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 5 is a partially enlarged view of a third light emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 6 is a cross-sectional view of the display substrate taken along line AA' in FIG. 3 , FIG. 4 or FIG. 5 according to some exemplary embodiments of the present disclosure.
  • the display substrate may include: a base substrate 1, the base substrate 1 includes a first side edge 11 and a first area AA away from the first side edge 11; A plurality of pixel units PX on the base substrate 1, the plurality of pixel units PX include a first pixel unit PX1 located in the first area AA and a second pixel unit PX2 near the first side edge 11 , the first pixel unit PX1 is located on the side of the second pixel unit PX2 away from the first side edge 11; a plurality of light-emitting diode chips 5 arranged on the base substrate 1, the plurality of light-emitting diode chips 5
  • the diode chip 5 includes a first light emitting diode chip 51 and a second light emitting diode chip 52, wherein the first light emitting diode chip 51 is located in the first pixel unit PX1, and at least a part of the second light emitting diode chip 52 is located in Inside the second pixel unit PX2.
  • side edge means a side surface of a substrate, part or element, and in the plan view of, for example, Fig. 1 or Fig. 2, "side edge” is shown as a line, For example, the first side edge 11 is the leftmost line.
  • the second pixel unit PX2 includes a second pixel unit boundary PX21 close to the first side edge 11
  • the second LED chip 52 includes a second pixel unit boundary PX21 close to the first side edge 11.
  • Chip side portion 521, the vertical distance between the orthographic projection of the second chip side portion 521 on the base substrate 1 and the orthographic projection of the second pixel unit boundary PX21 on the base substrate 1 ( For example, L2) in Figure 2 is greater than or equal to the specified distance.
  • the “prescribed distance” here may be a splicing distance capable of splicing display panels, and the “prescribed distance” and the “splicing distance” will be described in more detail below.
  • the first pixel unit PX1 includes a first pixel unit boundary PX11 parallel to the first side edge 11, and the first LED chip 51 has a first chip side close to the first pixel unit boundary PX11.
  • the vertical distance between the orthographic projection of the first chip side portion 511 on the base substrate 1 and the orthographic projection of the first pixel unit boundary PX11 on the base substrate 1 is smaller than the vertical distance between the orthographic projection of the second chip side portion 521 on the base substrate 1 and the orthographic projection of the second pixel unit boundary PX21 on the base substrate 1 (eg L2 in Figure 2). That is, the shortest distance between the second LED chip 52 and the border near the side edge of the corresponding second pixel unit PX2 is greater than the shortest distance between the first LED chip 51 and the edge of the corresponding pixel unit PX1 .
  • the first direction X and the second direction Y are schematically shown.
  • a plurality of pixel units PX may be arranged in an array along the first direction X and the second direction Y.
  • the first The direction X may correspond to the row direction in which the pixel units are arranged
  • the second direction Y may correspond to the column direction in which the pixel units are arranged. It should be noted that the embodiments of the present disclosure are not limited thereto.
  • the base substrate 1 may have a shape such as a rectangle, a rounded rectangle, or a quadrangle, and the first side edge 11 may be one of the four side edges of the base substrate 1 extending along the second direction Y. As shown in FIG. 2 , the first side edge 11 may be the right edge of the base substrate 1 .
  • the second pixel unit PX2 may be a certain pixel unit in a column of pixel units closest to the first side edge 11 .
  • the light-emitting diode chips in a column of pixel units closest to the first side edge 11 are arranged away from the first side edge 11, so that a larger splicing distance can be reserved at the side edge of the display substrate , which is beneficial to the splicing of multiple display substrates.
  • the point of "splicing" will be described in more detail below.
  • the area of the orthographic projection of the second light emitting diode chip 52 on the base substrate 1 is larger than the area of the orthographic projection of the first light emitting diode chip 51 on the base substrate 1, and the The area of the orthographic projection of the second light emitting diode chip 52 on the base substrate 1 is smaller than twice the area of the orthographic projection of the first light emitting diode chip 51 on the base substrate 1 .
  • the area of the orthographic projection of the part of the second light emitting diode chip 52 located in the second pixel unit PX2 on the base substrate 1 is smaller than that of the first light emitting diode chip 51 on the base substrate 1 The area of the orthographic projection on .
  • the base substrate 1 may further include a second side edge 12 , and the second side edge 12 is connected to the first side edge 11 .
  • the second side edge 12 may be one side edge extending along the first direction X among the four side edges of the base substrate 1 .
  • the second side edge 12 may be the lower side edge of the base substrate 1 .
  • the plurality of pixel units PX may further include an eighth pixel unit PX3 close to the second side edge 12, and the plurality of light emitting diode chips 5 further include a fourth light emitting diode chip 53, and the fourth light emitting diode chip 53 At least a part of is located in the eighth pixel unit PX3.
  • the eighth pixel unit PX3 includes an eighth pixel unit boundary PX31 close to the second side edge 12, and the fourth LED chip 53 includes a third chip side portion 531 close to the second side edge 12, so The vertical distance between the orthographic projection of the third chip side portion 531 on the base substrate 1 and the orthographic projection of the eighth pixel unit boundary PX31 on the base substrate 1 (such as L3 in FIG. 2 ) is greater than or equal to the prescribed distance.
  • the area of the orthographic projection of the fourth light emitting diode chip 53 on the base substrate 1 is larger than the area of the orthographic projection of the first light emitting diode chip 51 on the base substrate 1, and the The area of the orthographic projection of the fourth light emitting diode chip 53 on the base substrate 1 is smaller than twice the area of the orthographic projection of the first light emitting diode chip 51 on the base substrate 1 .
  • the area of the orthographic projection of the fourth light emitting diode chip 53 on the base substrate 1 may be substantially equal to the area of the orthographic projection of the second light emitting diode chip 52 on the base substrate 1 .
  • the area of the orthographic projection of the part of the fourth light emitting diode chip 53 located in the eighth pixel unit PX3 on the base substrate 1 is smaller than that of the first light emitting diode chip 51 on the base substrate 1 The area of the orthographic projection on .
  • the plurality of pixel units PX further includes a third pixel unit PX4, the third pixel unit PX4 is adjacent to the second pixel unit PX2, and the third pixel unit PX4 is perpendicular to the first pixel unit PX4.
  • the direction of the side edge 11 (for example, the first direction X) is located between the first pixel unit PX1 and the second pixel unit PX2, and the third pixel unit PX4 and the second pixel unit PX2 are perpendicular to The direction of the first side edges is located in the same row.
  • the second pixel unit PX2 and the third pixel unit PX4 may share the second light emitting diode chip 52 .
  • a part of the second light emitting diode chip 52 is located in the second pixel unit PX2, and another part of the second light emitting diode chip 52 is located in the third pixel unit PX4.
  • the part of the second light emitting diode chip 52 located in the second pixel unit PX2 may be called the first part
  • the part of the second light emitting diode chip 52 located in the third pixel unit PX4 may be called the second part. part.
  • the area of the orthographic projection of the first part of the second light emitting diode chip 52 on the base substrate 1 may be substantially equal to the area of the orthographic projection of the second part of the second light emitting diode chip 52 on the base substrate 1 .
  • embodiments of the present disclosure are not limited thereto.
  • the plurality of pixel units PX further includes a ninth pixel unit PX5, the ninth pixel unit PX5 is adjacent to the eighth pixel unit PX3, and the ninth pixel unit PX5 is perpendicular to the second side
  • the direction of the edge 12 (that is, the second direction Y) is located between the first pixel unit PX1 and the eighth pixel unit PX3, and the ninth pixel unit PX5 and the eighth pixel unit PX3 are perpendicular to the They are located in the same column in the direction of the second side edge 12.
  • the eighth pixel unit PX3 and the ninth pixel unit PX5 may share the fourth light emitting diode chip 53 .
  • a part of the fourth LED chip 53 is located in the eighth pixel unit PX3, and another part of the fourth LED chip 53 is located in the ninth pixel unit PX5.
  • the part of the fourth light emitting diode chip 53 located in the eighth pixel unit PX3 may be called the first part
  • the part of the fourth light emitting diode chip 53 located in the ninth pixel unit PX5 may be called the first part. for the second part.
  • the area of the orthographic projection of the first part of the fourth light emitting diode chip 53 on the base substrate 1 may be substantially equal to the area of the orthographic projection of the second part of the fourth light emitting diode chip 53 on the base substrate 1 .
  • embodiments of the present disclosure are not limited thereto.
  • the plurality of pixel units PX may further include a fourth pixel unit PX6 , a fifth pixel unit PX7 , a sixth pixel unit PX8 and a seventh pixel unit PX9 .
  • the fourth pixel unit PX6 is adjacent to the connecting position of the first side edge 11 and the second side edge 12, for example, the connecting position of the first side edge 11 and the second side edge 12 may correspond to the lining The corners of the base substrate 1.
  • the fifth pixel unit PX7 adjoins the fourth pixel unit PX6 in a direction parallel to the first side edge 11, and the sixth pixel unit PX8 adjoins in a direction parallel to the second side edge 12.
  • the fourth pixel unit PX6 and the seventh pixel unit PX9 are adjacent to the fifth pixel unit PX7 and the sixth pixel unit PX8.
  • the plurality of LED chips 5 further include a third LED chip 54, and the fourth pixel unit PX6, the fifth pixel unit PX7, the sixth pixel unit PX8, and the seventh pixel unit PX9 can share The third LED chip 54 .
  • the third LED chip 54 includes four parts (such as a first part, a second part, a third part and a fourth part), wherein the first part of the third LED chip 54 is located in the In the fourth pixel unit PX6, the second part of the third LED chip 54 is located in the fifth pixel unit PX7, and the third part of the third LED chip 54 is located in the sixth pixel unit PX8.
  • the fourth part of the third LED chip 54 is located in the seventh pixel unit PX9.
  • the areas of the orthographic projections of the first part, the second part, the third part and the fourth part of the third LED chip 54 on the base substrate 1 may be substantially equal to each other.
  • embodiments of the present disclosure are not limited thereto.
  • the edges of the fourth pixel unit PX6 include first and second side edges intersecting each other.
  • a part of the third light emitting diode chip 54 is located in the fourth pixel unit PX6, and other parts of the third light emitting diode chip 54 are located in the pixel units adjacent to the fourth pixel unit PX6 (for example, the fifth pixel unit PX7, In the sixth pixel unit PX8 and the seventh pixel unit PX9 ), the third LED chip 54 is located in four adjacent pixel units.
  • the orthographic projection of the side close to the first side edge 11 of the third LED chip 54 on the base substrate 1 is the same as that of the first side edge 11 on the base substrate 1
  • the vertical distance between the orthographic projections is greater than or equal to a specified distance
  • the orthographic projection of the side of the third LED chip 54 close to the second side edge 12 on the base substrate 1 is the same as the second side
  • the vertical distance between the orthographic projections of the edges 12 on the base substrate 1 is greater than or equal to a specified distance.
  • the shortest distance between the third light emitting diode chip 54 and the border of the corresponding fourth pixel unit PX6 near the side edge is greater than the distance between the first light emitting diode chip 51 and the edge of the corresponding first pixel unit PX1 shortest distance.
  • the area of the orthographic projection of the second light emitting diode chip 52 or the fourth light emitting diode chip 53 on the base substrate 1 is smaller than the area of the third light emitting diode chip 54 on the base substrate 1 The area of the orthographic projection.
  • the area of the orthographic projection of the part of the third light emitting diode chip 54 located in the fourth pixel unit PX6 on the base substrate is smaller than the orthographic projection of the first light emitting diode chip 51 on the base substrate area.
  • the area of the orthographic projection of the third light emitting diode chip 54 on the base substrate is larger than the area of the orthographic projection of the first light emitting diode chip 51 on the base substrate, and the third light emitting diode chip
  • the area of the orthographic projection of 54 on the base substrate is less than four times the area of the orthographic projection of the first light emitting diode chip 51 on the base substrate.
  • the light emitting diode chips in a column of pixel units and a row of pixel units closest to the side edge of the display substrate can be kept away from the side edge in the first direction or the second direction setting, the pixel unit closest to the corner of the display substrate can also be set away from the corner in the first direction and the second direction, so as to ensure that the display substrate has a sufficient splicing distance, which is conducive to the realization of spliced display panels and video walls.
  • the structure of the eighth pixel unit PX3 and the second pixel unit PX2 may be basically the same, and the two are only arranged in different directions. Therefore, in other parts, for the convenience of description, the eighth pixel unit PX3 and the second pixel unit The second pixel unit PX2 can be collectively referred to as the second pixel unit; similarly, the structure of the ninth pixel unit PX5 and the third pixel unit PX3 can be basically the same, and the two are only arranged in different directions. Therefore, in other parts, for the convenience of description, the first The nine pixel unit PX5 and the third pixel unit PX3 may be collectively referred to as a third pixel unit.
  • FIG. 12 is a partially enlarged view of a display substrate at part I in FIG. 2 according to some exemplary embodiments of the present disclosure.
  • a plurality of boundaries are schematically shown with a plurality of rectangular boxes, for example, a rectangular box R1 represents a boundary of a pixel unit, a rectangular box R2 represents a boundary of a light-emitting diode chip, and a rectangular box R2 represents a boundary of a light-emitting diode chip.
  • Box R3 represents the boundary of the protective layer, and rectangular box R4 represents the boundary of multiple light emitting regions or PADs of the light emitting diode chip.
  • certain positional deviations may occur.
  • the positional deviation there is a certain distance between the rectangular frame R1 and the rectangular frame R2 along the first direction X and the second direction Y, and the distance is designed to avoid the generation of two adjacent light-emitting diode chips. put one's oar in.
  • the distance takes into account the process error generated during laser cutting of chips.
  • there is a certain distance between the rectangular frame R2 and the rectangular frame R3 along the first direction X and the second direction Y and the distance takes into account the process error generated when forming the protective layer.
  • the substrate 5S may be a sapphire substrate.
  • the light emitting diode chip 5 can have a flip-chip structure.
  • the light emitting region 5A is interposed between the cathode 5C and the anode 5B.
  • One light emitting diode chip 5 may include multiple light emitting regions 5A, and each light emitting region 5A corresponds to an anode 5B.
  • Each anode 5B is electrically connected to a corresponding anode pad (ie, anode pad) 5P1.
  • One LED chip 5 may have a common cathode 5C, which is electrically connected to the cathode pad (ie cathode pad) 5P2. Through the anode pad 5P1 and the cathode pad 5P2 , prescribed electric signals can be supplied to the anode 5B and the cathode 5C, respectively.
  • the plurality of light emitting regions 5A correspond to the plurality of anodes 5B one by one
  • the plurality of light emitting regions 5C are spaced apart from each other
  • the cathode pad 5P2 and the plurality of anodes The light emitting regions 5C are spaced apart from each other.
  • the first LED chip 51 may include three light emitting regions 5A, and correspondingly, the first LED chip 51 may include three anodes 5B and one common cathode 5C.
  • the three light emitting regions 5A correspond to the three anodes 5B respectively.
  • the three anodes 5B are electrically connected to the three anode pads 5P1, respectively, and one common cathode 5C is electrically connected to the cathode pad 5P2.
  • the three light emitting areas 5A can be configured to emit red light, green light and blue light respectively.
  • the light-emitting area that emits red light is called the first light-emitting area 5A1
  • the light-emitting area that emits green light is called the second light-emitting area 5A2
  • the light-emitting area that emits blue light is called the third light-emitting area 5A3 .
  • the area of the orthographic projection of the first luminescent region 5A1 on the substrate 5S is larger than the area of the orthographic projection of the second luminescent region 5A2 on the substrate 5S, and the area of the orthographic projection of the second luminescent region 5A2 on the substrate 5S is larger than that of the third luminescent region 5A2.
  • the orthographic projections of the first light emitting region 5A1 , the second light emitting region 5A2 , the third light emitting region 5A3 and the cathode pad 5P2 of the first light emitting diode chip 51 on the substrate 5S of the first light emitting diode chip 51 are arranged at intervals from each other. , for example, they are respectively located at the 4 corners of the substrate 5S.
  • the orthographic projections of the first light-emitting region 5A1, the second light-emitting region 5A2, and the third light-emitting region 5A3 of the first light-emitting diode chip 51 on the substrate 5S of the first light-emitting diode chip 51 can respectively cover the corresponding anode pads 5P1 Orthographic projection on the substrate 5S of the first LED chip 51 .
  • the second LED chip 52 or the fourth LED chip 53 may include six light emitting regions 5A, and accordingly, the second LED chip 52 or the fourth LED chip 53 may include 6 anodes 5B and 1 common cathode 5C.
  • the three light emitting regions 5A correspond to the six anodes 5B respectively.
  • the six anodes 5B are electrically connected to the six anode pads 5P1, respectively, and one common cathode 5C is electrically connected to the cathode pad 5P2.
  • three light emitting regions 5A form a group and can be respectively configured to emit red light, green light and blue light.
  • the light-emitting area that emits red light is called the first light-emitting area 5A1
  • the light-emitting area that emits green light is called the second light-emitting area 5A2
  • the light-emitting area that emits blue light is called the third light-emitting area 5A3 .
  • some of the plurality of light emitting regions 5A of the second light emitting diode chip 52 or the fourth light emitting diode chip 53 are located in the second pixel unit, and some of the plurality of light emitting regions 5A are located in the first pixel unit.
  • the number of light emitting regions 5A of the second LED chip 52 or the fourth LED chip 53 is greater than the number of light emitting regions of the first LED chip 51 .
  • the area of the orthographic projection of the first luminescent region 5A1 on the substrate 5S is larger than the area of the orthographic projection of the second luminescent region 5A2 on the substrate 5S, and the area of the orthographic projection of the second luminescent region 5A2 on the substrate 5S is larger than that of the third luminescent region 5A2.
  • a group of light emitting regions 5A1, 5A2, 5A3 are located in a pixel unit sharing the second light emitting diode chip 52 or the fourth light emitting diode chip 53, and another group of light emitting regions 5A1, 5A2, 5A3 are located in the same pixel unit of the second light emitting diode chip 53. chip 52 or another pixel unit of the fourth LED chip 53 .
  • the six light emitting regions of the second LED chip 52 and the orthographic projections of the cathode pads 5P2 on the substrate 5S of the second LED chip 52 are arranged at intervals from each other.
  • the orthographic projections of the two first light emitting regions 5A1 of the second light emitting diode chip 52 on the substrate 5S are respectively located at two opposite corners of the substrate 5S.
  • Orthographic projections of the two second light emitting regions 5A2 of the second light emitting diode chip 52 on the substrate 5S are respectively located at two opposite corners of the substrate 5S.
  • Orthographic projections of the two third light emitting regions 5A3 of the second light emitting diode chip 52 on the substrate 5S are respectively located at two opposite sides of the substrate 5S.
  • the orthographic projection of one third light-emitting region 5A3 of the second light-emitting diode chip 52 on its substrate 5S is located in the middle of the orthographic projection of one first light-emitting region 5A1 and one second light-emitting region 5A2 on its substrate 5S location.
  • the orthographic projection of the cathode pad 5P2 of the second LED chip 52 on its substrate 5S may be approximately located at the geometric center of its substrate 5S.
  • the orthographic projection of the cathode pad 5P2 of the second LED chip 52 on the substrate 5S is roughly located at the intersection of two diagonal lines of the substrate 5S.
  • the orthographic projection of the cathode pad 5P2 of the second LED chip 52 on the substrate 5S is located at the junction of the first pixel unit and the second pixel unit.
  • the orthographic projections of the first light-emitting region 5A1, the second light-emitting region 5A2, and the third light-emitting region 5A3 of the second light-emitting diode chip 52 on the substrate 5S of the second light-emitting diode chip 52 can respectively cover the corresponding anode pads 5P1 Orthographic projection on the substrate 5S of the second LED chip 52 .
  • the third LED chip 54 may include 12 light emitting regions 5A, and correspondingly, the third LED chip 54 may include 12 anodes 5B and 1 common cathode 5C.
  • the 12 light emitting regions 5A correspond to the 12 anodes 5B respectively.
  • the 12 anodes 5B are electrically connected to the 12 anode pads 5P1, respectively, and one common cathode 5C is electrically connected to the cathode pad 5P2.
  • three light-emitting areas 5A form a group and can be respectively configured to emit red light, green light and blue light.
  • the light-emitting area that emits red light is called the first light-emitting area 5A1
  • the light-emitting area that emits green light is called the second light-emitting area 5A2
  • the light-emitting area that emits blue light is called the third light-emitting area 5A3.
  • the plurality of light emitting regions 5A of the third light emitting diode chip 54 are located in the third pixel unit, and others of the plurality of light emitting regions 5A are located in the first pixel unit and the second pixel unit.
  • the number of light-emitting regions 5A of the third LED chip 54 is greater than the number of light-emitting regions 5A of the second LED chip 52 .
  • the area of the orthographic projection of the first luminescent region 5A1 on the substrate 5S is larger than the area of the orthographic projection of the second luminescent region 5A2 on the substrate 5S, and the area of the orthographic projection of the second luminescent region 5A2 on the substrate 5S is larger than that of the third luminescent region 5A2.
  • each group of light emitting regions 5A1 , 5A2 , 5A3 is located in one pixel unit among the four pixel units sharing the third light emitting diode chip 54 .
  • the 12 light emitting regions of the third LED chip 54 and the orthographic projections of the cathode pads 5P2 on the substrate 5S of the third LED chip 54 are arranged at intervals from each other.
  • the orthographic projection of the cathode pad 5P2 of the third LED chip 54 on its substrate 5S may be approximately located at the geometric center of its substrate 5S.
  • the orthographic projection of the cathode pad 5P2 of the third LED chip 54 on the substrate 5S is roughly located at the intersection of two diagonal lines of the substrate 5S.
  • the orthographic projection of the cathode pad 5P2 of the third LED chip 54 on the substrate 5S is located at the junction of the first pixel unit, the second pixel unit and the third pixel unit.
  • the orthographic projections of the first light-emitting region 5A1, the second light-emitting region 5A2, and the third light-emitting region 5A3 of the third light-emitting diode chip 54 on the substrate 5S of the third light-emitting diode chip 54 can respectively cover the corresponding anode pads 5P1 Orthographic projection on the substrate 5S of the third LED chip 54 .
  • the second light emitting diode chip 52 may include a plurality of light emitting regions 5A, a plurality of anodes 5B and a cathode 5C, the plurality of light emitting regions 5A correspond to the plurality of anodes 5B one by one, the A plurality of light emitting regions 5A are spaced apart from each other, some of the plurality of light emitting regions 5A are located in the second pixel unit PX2, and others of the plurality of light emitting regions 5A are located in the third pixel unit PX4.
  • the plurality of light emitting regions 5A correspond to the plurality of anodes 5B one by one
  • the A plurality of light emitting regions 5A are spaced apart from each other
  • some of the plurality of light emitting regions 5A are located in the second pixel unit PX2
  • others of the plurality of light emitting regions 5A are located in the third pixel unit PX4.
  • the second LED chip 52 may include six light emitting regions 5A, six anodes 5B and one cathode 5C, wherein three light emitting regions 5A are located in the second pixel In the unit PX2, the other three light emitting regions 5A are located in the third pixel unit PX4.
  • the fourth light emitting diode chip 53 includes a plurality of light emitting regions 5A, a plurality of anodes 5B and a cathode 5C, the plurality of light emitting regions 5A of the fourth light emitting diode chip 53 and the fourth light emitting diode chip 53
  • the multiple anodes 5B of the fourth light emitting diode chip 53 are in one-to-one correspondence, the multiple light emitting regions 5A of the fourth light emitting diode chip 53 are arranged at intervals, and some of the multiple light emitting regions 5A of the fourth light emitting diode chip 53 are located in the eighth pixel In the unit PX3, some of the plurality of light emitting regions 5A of the fourth LED chip 53 are located in the ninth pixel unit PX5.
  • the fourth LED chip 53 may include six light emitting regions 5A, six anodes 5B and one cathode 5C, wherein three light emitting regions 5A are located in the eighth pixel In the unit PX3, the other three light emitting regions 5A are located in the ninth pixel unit PX5.
  • the third light emitting diode chip 54 may include a plurality of light emitting regions 5A, a plurality of anodes 5B and a cathode 5C, the plurality of light emitting regions 5A of the third light emitting diode chip 54 and the plurality of light emitting regions of the third light emitting diode chip 54
  • the anodes 5B are in one-to-one correspondence, the plurality of light emitting regions 5A of the third light emitting diode chip 54 are spaced apart from each other, and the first part of the plurality of light emitting regions 5A of the third light emitting diode chip 54 is located in the fourth pixel unit In PX6, the second part of the plurality of light emitting regions 5A of the third light emitting diode chip 54 is located in the fifth pixel unit PX7, and the third part of the plurality of light emitting regions 5A of the third light emitting diode chip 54 is located in the fifth pixel unit PX7.
  • a part is located in the sixth pixel unit PX8, and a fourth part of the plurality of light emitting regions 5A of the third LED chip 54 is located in the seventh pixel unit PX9.
  • three light emitting regions 5A are respectively disposed in the fourth pixel unit PX6 , the fifth pixel unit PX7 , the sixth pixel unit PX8 and the seventh pixel unit PX9 .
  • the display substrate adopts a light emitting diode chip 5 and a light converting part 600 to realize color display.
  • the light conversion part may include a light conversion material such as quantum dots, for converting light of the first wavelength into light of the second wavelength.
  • the light-emitting diode chip is an LED chip that emits blue light
  • the light converting portion includes a first light converting portion for converting blue light into red light; and a second light for converting blue light into filtered light conversion department.
  • the light converting portion 600 is disposed on the side of the substrate 5S away from the light emitting region 5A, that is, the light converting portion 600 and the light emitting region 5A are respectively disposed on two sides of the substrate 5S.
  • the plurality of light conversion parts 600 correspond to the plurality of light emitting regions 5A respectively.
  • the orthographic projections of the plurality of light converting portions 600 on the base substrate 1 and the orthographic projections of the plurality of light emitting regions 5A on the base substrate 1 are at least partially overlapped respectively.
  • a light shielding portion 400 is disposed between adjacent light conversion portions 600 .
  • the width of the light shielding portion 400 can be calculated, that is, the distance between adjacent light converting portions 600 can be calculated.
  • the inventors have found through research that the distance between adjacent light converting portions 600 is greater than 8 microns.
  • the distance between the plurality of light emitting regions of the second light emitting diode chip 52 is more than 8 microns.
  • the distance between the plurality of light emitting regions of the fourth light emitting diode chip 53 is more than 8 microns.
  • the distance between the plurality of light emitting regions of the third light emitting diode chip 54 is more than 8 microns. In this way, while reducing the area of the light-emitting diode chip, cross-color generation between adjacent sub-pixels can be avoided.
  • FIG. 7 is a cross-sectional view of the display substrate taken along line BB' in FIG. 2 according to some exemplary embodiments of the present disclosure.
  • a substrate carrying a circuit board or an integrated circuit hereinafter referred to as a second base substrate
  • the bonding wires electrically connect the terminals of the light emitting diode chip (ie, PAD) on the front side of the base substrate with the circuit on the back side of the base substrate.
  • 8A to 8G are cross-sectional views schematically illustrating a structure formed after some steps of the manufacturing method of the display substrate are performed. With reference to FIG. 7 and FIG. 8A to FIG. 8G , the manufacturing method of the display substrate may be performed according to the following steps.
  • step S101 a first substrate 100 is provided.
  • the first substrate 100 may include a base substrate 1 and a plurality of first electrodes 2 and a plurality of first terminals 3 disposed on the base substrate 1 .
  • a plurality of first terminals 3 are located on the edge of the first substrate 100 .
  • a plurality of first terminals 3 are located in the fan-out area (ie, fan-out area) of the first substrate 100, and are used to electrically connect the signal lines on the first substrate 100 (for example, the signal lines to Terminals of each light emitting diode) are electrically connected to an external driving circuit.
  • the material of the base substrate 1 may include but not limited to glass, quartz, plastic, silicon, polyimide and the like.
  • the first electrode 2 and the first terminal 3 may be columnar structures.
  • the materials of the first electrode 2 and the first terminal 3 may include conductive materials, such as metal materials, specifically, gold, silver, copper, aluminum, molybdenum, gold alloys, silver alloys, copper alloys, aluminum alloys, molybdenum alloys etc., or a combination of at least two of them, which are not limited in the embodiments of the present disclosure.
  • the first substrate 100 may further include a driving circuit 4 electrically connected to the plurality of first electrodes 2 , and the driving circuit 4 is disposed on the base substrate 1 .
  • the drive circuit 4 can be used to provide electrical signals to the LED chips subsequently formed on the plurality of first electrodes 2 to control their luminance.
  • the drive circuit 4 may be a plurality of pixel drive circuits connected one-to-one with each light-emitting diode chip, or a plurality of micro-integrated circuit chips connected one-to-one with each light-emitting diode chip, etc.
  • the structure can control each light-emitting diode chip to emit different gray scales of brightness.
  • the specific circuit structure of the driving circuit 4 on the first substrate 100 can be set according to actual needs, which is not limited in the embodiments of the present disclosure. In the following, the driving circuit 4 will be illustrated with reference to the accompanying drawings.
  • step S102 a plurality of LED chips 5 are transferred and bonded to the first substrate 100 .
  • each of the plurality of LED chips 5 includes N electrodes and P electrodes, and the N electrodes and P electrodes of the LED chips 5 are respectively connected to the corresponding first electrodes 2, and the plurality of LED chips 5 are respectively connected to the corresponding first electrodes 2.
  • the surface of a terminal 3 is exposed.
  • a plurality of light emitting diode chips are arranged in an array along a first direction X and a second direction Y.
  • the first direction X is the row direction and the second direction Y is the column direction.
  • the embodiments of the present disclosure are not limited thereto, and the first direction and the second direction may be any directions, as long as the first direction and the second direction intersect.
  • the plurality of light emitting diode chips are not limited to be arranged in a straight line, but may also be arranged in a curved line, in a ring or in any manner, which may be determined according to actual requirements, which is not limited by the embodiments of the present disclosure.
  • the light emitting diode chip may include a micro light emitting diode (Micro LED) or a submillimeter light emitting diode (Mini LED).
  • Micro LED micro light emitting diode
  • Mini LED submillimeter light emitting diode
  • step S103 the second substrate 200 is provided, and the first substrate 100 and the second substrate 200 are placed on the carrier 300 .
  • the second substrate 200 can be a circuit board, for example, PCB (Printed Circuit Board, ie printed circuit board), FPC (Flexible Printed Circuit, ie flexible circuit board) or COF (Chip On Film, ie chip on film).
  • PCB Printed Circuit Board, ie printed circuit board
  • FPC Flexible Printed Circuit, ie flexible circuit board
  • COF Chip On Film, ie chip on film
  • the second substrate 200 may include a second base substrate 6 and a plurality of second terminals 7 disposed on the second base substrate 6 .
  • the plurality of second terminals 7 may be arranged along the first direction X (the direction perpendicular to the paper in FIG. 8C ), that is, the plurality of second terminals 7 constitute a second terminal row.
  • multiple second terminals 7 may correspond to multiple first terminals 3 one-to-one. That is, the arrangement period of the second terminals 7 is the same as that of the first terminals 3 .
  • the second substrate 200 may also include an external driving circuit disposed on the second base substrate 6 , for example, an integrated circuit chip, but the embodiments of the present disclosure are not limited thereto.
  • the carrier 300 is used to space and fix the first substrate 100 and the second substrate 200 so as to maintain a relative positional relationship between them.
  • the first terminal 3 provided on the first substrate 100 has a first surface 31 (shown as an upper surface) away from the base substrate 1
  • the second terminal 7 provided on the second substrate 200 has a first surface 31 away from the base substrate 1.
  • the second surface 71 of the second base substrate 6 (shown as the upper surface in the figure).
  • step S104 referring to FIG. 8C and FIG. 8D in conjunction, the first protective adhesive layer 8 is formed in the gap 400 between the first terminal row where the first terminal 3 is located and the second terminal row where the second terminal 7 is located.
  • a certain thickness of protective glue can be coated in the gap 400, the protective glue at least fills the gap 400, and, due to the limitation of coating accuracy, the protective glue may also cover the first terminal 3 and the second terminal located on both sides of the gap 400. At least a part of the surface of the second terminal 7, but the part of the protective glue covering the first terminal 3 and the second terminal 7 can be removed later by laser ablation or film removal, so as not to affect the subsequent process, so that only the gap can be filled 400 of the first protective adhesive layer 8 . It can be understood that the orthographic projection of the first protective adhesive layer 8 on the carrier 300 covers the orthographic projection of the gap 400 on the carrier 300 .
  • the first protective adhesive layer 8 contacts the first terminal 3 near the sidewall of the first substrate 100 , and the first protective adhesive layer 8 contacts the second terminal 7 near the sidewall of the second substrate 100 .
  • the first protective adhesive layer 8 includes a third surface 81 away from the carrier 300 .
  • the third surface 81 , the first surface 31 and the second surface 71 are substantially at the same level, so as to ensure that subsequent bonding wires are formed on a relatively flat surface.
  • the thickness of the first protective adhesive layer 8 is in the range of 5-500 microns, and the specific value is the same as the thickness of the first terminal 3 and/or the second terminal 7.
  • the material used for the first protective adhesive layer 8 has a Young's The modulus can be between 0.1Mpa-80Gpa, for example, the material can be silica gel or polydimethylsiloxane (ie PDMS).
  • step S105 the bonding wire 9 is formed such that the bonding wire 9 electrically connects the first terminal 3 and the second terminal 7 .
  • the bonding wire 9 is formed such that one end 91 of the bonding wire 9 is connected to the first terminal 3 and the other end 92 is connected to the second terminal 7 . That is, one end 91 of the bonding wire 9 is soldered to the first terminal 3 , and the other end 92 is soldered to the second terminal 7 .
  • the welding spot where the end 91 is welded on the first terminal 3 is called a first welding spot 911
  • the welding spot where the end 92 is welded on the second terminal 7 is called a second welding spot 921 , referring to FIG. 7 .
  • the bonding wire 9 basically extends in the plane where the first terminal 3 and the second terminal 7 are located, which facilitates the subsequent bending process.
  • the first soldering point 911 may be a wedge-shaped soldering point, that is, the shape of the orthographic projection of the first soldering point 911 on the base substrate 1 is a wedge.
  • the height of the first welding spot 911 on the first terminal 3 can be controlled within 1-10 microns.
  • the diameter of the bonding wire 9 may be between 10-500 microns.
  • the height of the first welding spot 911 on the first terminal 3 is smaller than the diameter of the bonding wire 9 , so that the bonding wire 9 basically extends in the plane where the first terminal 3 and the second terminal 7 are located.
  • metals such as Cu, Al, Au, Ag or alloys thereof can be used for the bonding wire 9 .
  • each bonding wire 9 is electrically connected to a first terminal 3 and its corresponding second terminal 7 respectively. Since the plurality of first terminals 3 are arranged at equal intervals along the first direction X, the plurality of bonding wires 9 are also arranged at equal intervals along the first direction X.
  • a second protective adhesive layer 110 is formed on the surface of each of the first terminal 3 , the second terminal 7 and the bonding wire 9 away from the base substrate 1 and the second base substrate 6 .
  • the orthographic projection of the second protective adhesive layer 110 in the direction perpendicular to the first surface 31 covers each of the first terminal 3, the second terminal 7 and the bonding wire 9 in a direction perpendicular to the first surface 31. Orthographic projection in the direction of a surface 31. In this way, the bonding wire 9 and the solder joints of each of the first terminal 3 and the second terminal 7 and the bonding wire 9 can be protected.
  • the thickness of the second protective adhesive layer 110 is in the range of 5-500 microns, and the Young's modulus of the material used for the second protective adhesive layer 110 can be between 0.1Mpa-80Gpa, for example, the material can be silica gel Or polydimethylsiloxane (ie PDMS).
  • the material can be silica gel Or polydimethylsiloxane (ie PDMS).
  • the thickness of the second protective adhesive layer 110 may be substantially equal to the thickness of the first protective adhesive layer 8 . In this way, it can be ensured that the bonding wire 9 is at the neutral layer of the upper and lower protective adhesive layers.
  • a back glue 120 is pasted on any one of the surface of the base substrate 1 away from the first terminal 3 and the surface of the second base substrate 6 away from the second terminal 7 .
  • adhesive backing 120 is pasted on the surface of the base substrate 1 away from the first terminals 3 .
  • step S108 with reference to FIG. 8G and FIG. 7 , the second substrate 200 is turned over toward the first substrate 100 , so that the surface of the second base substrate 6 away from the second terminal 7 is attached to the back adhesive 120 .
  • the second substrate 200 can be bent to the back of the first substrate 100 , and the two substrates 100 and 200 can be attached together through the adhesive 120 .
  • the second substrate 200 can be rotated to the lower surface of the first substrate 100 through the carrier 300 with a fixed rotation track, so as to ensure the stability of the flipping process and lower the bonding wire 9. risk of breakage.
  • step S108 the second substrate 200 is turned over, and the surface of the first protective adhesive layer 8 away from the bonding wire 9 contacts the first substrate 100 , the back adhesive 120 and the second substrate 200 .
  • the surface of the first protective adhesive layer 8 away from the bonding wire 9 contacts the sidewall of the first substrate 100 , the sidewall of the back glue 120 and the sidewall of the second substrate 200 .
  • the sidewalls of the first substrate 100, the sidewalls of the adhesive 120 and the sidewalls of the second substrate 200 completely support the first protective adhesive layer 8, thereby completely supporting the bonding wire 9, so as to improve reliability. .
  • the bonding wires are manufactured by using the wire bonding process, and the substrate is turned over to realize the stacked structure of the upper and lower substrates, which can reduce the complexity of the process and reduce the manufacturing cost.
  • the specified distance D may include a first distance D1, a second distance D2, and a third distance D3.
  • the first distance D1 may correspond to the length of the bonding wire 9 at the side edge
  • the second distance D2 may correspond to the minimum bending distance that the bonding wire 9 needs to be bent to the back
  • the third distance D3 may correspond to the protective glue layer thickness.
  • the display panel may be a spliced display substrate.
  • the display panel may be formed by splicing two above-mentioned display substrates. In order to arrange the bonding wire 9 and the protective adhesive layer and make the bonding wire 9 have a sufficient bending radius to be bent to the back of the display substrate, it is necessary to reserve sufficient splicing distance at the splicing position.
  • the splicing distance may be more than twice the predetermined distance D above.
  • a sufficient distance can be reserved at the side edge of the display substrate, which is beneficial for forming a spliced display panel.
  • the light effect at the spliced position is less affected, which is beneficial to improve the display effect of the display panel.
  • FIG. 9 it schematically shows the situation that four display substrates with the same structure and specifications are spliced together to form a display panel.
  • FIG. 11A and FIG. 11B schematically illustrate a plan view of a display panel according to an embodiment of the present disclosure.
  • FIG. 11A two display substrates with the same structure and specifications are spliced together to form a display panel, that is, the two display substrates can be distributed axially symmetrically along the boundary line.
  • FIG. 11A two display substrates with the same structure and specifications are spliced together to form a display panel, that is, the two display substrates can be distributed axially symmetrically along the boundary line.
  • a side edge of one display substrate may be spliced with a side edge of another display substrate along a first direction.
  • the side edge of one display substrate can be spliced with the side edge of the other display substrate along the second direction.
  • the shape of the orthographic projection of each light emitting diode chip on the base substrate 1 is a rectangle, but the embodiments of the present disclosure are not limited thereto, for example, the light emitting diode chips on the base substrate 1
  • the shape of the orthographic projection on can be a circle, an ellipse or other shapes. For example, FIG.
  • FIG. 13 schematically shows a schematic plan view of a third light emitting diode chip according to some exemplary embodiments of the present disclosure.
  • the shape of the orthographic projection of the third LED chip on the base substrate 1 is a circle.
  • the driving circuit 4 may include a thin film transistor array layer.
  • the thin film transistor array layer may specifically include an active layer, a gate insulating layer, a gate, a source, a drain, a planar layer, and the like.
  • the specific film layer structure of the driving circuit 4 can refer to the film layer structure used in the existing array substrate, and will not be repeated here.
  • the display device includes at least two display substrates as described above. At least two display substrates as described above are spliced to form a display device. Since the LED chip in the pixel unit closest to the side edge of the display substrate is arranged away from the side edge, a sufficient splicing distance can be reserved at the splicing position, for example, the splicing distance can be the specified distance D 2 times. In this way, it is beneficial to form the spliced display device.
  • the display device has all the features and advantages of the above-mentioned display substrate. For these features and advantages, reference can be made to the description of the display substrate above, and details will not be repeated here.

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Abstract

一种显示基板，包括：衬底基板，所述衬底基板包括至少一个侧边缘和显示区域；设置在所述显示区域中的多个像素单元，所述多个像素单元包括位于所述显示区域的第一像素单元、第二像素单元和第三像素单元，其中，所述多个第二像素单元位于所述多个第一像素单元靠近所述侧边缘的一侧，所述多个第二像素单元的边缘包括所述侧边缘，所述第三像素单元位于所述第一像素单元和所述第二像素单元之间，所述第三像素单元邻接所述第二像素单元；以及设置在所述衬底基板上的多个发光二极管芯片，所述多个发光二极管芯片包括第一发光二极管芯片和第二发光二极管芯片，其中，所述第一发光二极管芯片位于所述第一像素单元内，所述第二发光二极管芯片的一部分位于第二像素单元内，所述第二发光二极管芯片的其他部分位于所述第三像素单元内。

Description

显示基板、拼接显示面板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、拼接显示面板和显示装置。
背景技术
发光二极管(Light Emitting Diode，英文缩写为LED)技术发展了近三十年，其应用范围不断扩展，例如，其可以应用于显示领域，用作显示装置的背光源或用作LED显示屏。随着技术的发展，次毫米发光二极管(Mini Light Emitting Diode，英文缩写为Mini LED)显示技术和微型发光二极管(Micro Light Emitting Diode，英文缩写为Micro LED)显示技术逐渐成为显示装置的一个热点。LED具有自发光、广视角、快速响应、结构简单、寿命长等优点，而且，Mini LED/Micro LED显示屏可以通过拼接方式实现大尺寸显示，所以，它们具有较好的市场前景。目前，Mini LED/Micro LED显示装置的结构及其制造工艺，是研发人员关注的重要课题之一。
在本部分中公开的以上信息仅用于对本公开的发明构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
在一个方面，提供一种显示基板，包括：衬底基板，所述衬底基板包括至少一个侧边缘和显示区域；设置在所述显示区域中的多个像素单元，所述多个像素单元包括位于所述显示区域的第一像素单元、第二像素单元和第三像素单元，其中，所述多个第二像素单元位于所述多个第一像素单元靠近所述侧边缘的一侧，所述多个第二像素单元的边缘包括所述侧边缘，所述第三像素单元位于所述第一像素单元和所述第二像素单元之间，所述第三像素单元邻接所述第二像素单元；以及设置在所述衬底基板上的多个发光二极管芯片，所述多个发光二极管芯片包括第一发光二极管芯片和第二发光二极管芯片，其中，所述第一发光二极管芯片位于所述第一像素单元内，所述第二发光二极管芯片的一部分位于第二像素单元内，所述第二发光二极管芯片的其他部分位于所述第三像素单元内。
根据一些示例性的实施例，所述第二发光二极管芯片与该第二发光二极管芯片的一部分所在的所述第二像素单元靠近侧边缘的边界之间的最短距离大于所述第一发光二极管芯片与该第一发光二极管芯片所在的第一像素单元的边缘之间的最短距离。
根据一些示例性的实施例，所述第二发光二极管芯片位于所述第二像素单元内的部分在所述衬底基板上的正投影的面积小于所述第一发光二极管芯片在所述衬底基板上的正投影的面积。
根据一些示例性的实施例，所述第二发光二极管芯片在所述衬底基板上的正投影的面积大于所述第一发光二极管芯片在所述衬底基板上的正投影的面积，且所述第二发光二极管芯片在所述衬底基板上的正投影的面积小于2倍的所述第一发光二极管芯片在所述衬底基板上的正投影的面积。
根据一些示例性的实施例，所述多个像素单元还包括位于所述显示区域中的第四像素单元、第五像素单元、第六像素单元和第七像素单元，所述第四像素单元的边缘包括彼此相交的第一侧边缘和第二侧边缘，所述第五像素单元、第六像素单元和第七像素单元分别与所述第四像素单元邻接；所述多个发光二极管芯片还包括第三发光二极管芯片，所述第三发光二极管芯片的一部分位于第四像素单元内，所述第三发光二极管芯片的其他部分分别位于第五像素单元、第六像素单元和第七像素单元内。
根据一些示例性的实施例，所述第三发光二极管芯片与该第三发光二极管芯片的一部分所在的所述第三像素单元靠近侧边缘的边界之间的最短距离大于所述第一发光二极管芯片与该第一发光二极管芯片所在的第一像素单元的边缘之间的最短距离。
根据一些示例性的实施例，所述第三发光二极管芯片位于所述第四像素单元内的部分在所述衬底基板上的正投影的面积小于所述第一发光二极管芯片在所述衬底基板上的正投影的面积。
根据一些示例性的实施例，所述第三发光二极管芯片在所述衬底基板上的正投影的面积大于所述第一发光二极管芯片在所述衬底基板上的正投影的面积，且所述第三发光二极管芯片在所述衬底基板上的正投影的面积小于4倍的所述第一发光二极管芯片在所述衬底基板上的正投影的面积。
根据一些示例性的实施例，所述发光二极管芯片包括基底和设置于所述基底的多个发光区、多个阳极和一个阴极，所述多个发光区和所述多个阳极一一对应，所述多个发光区彼此间隔设置。
根据一些示例性的实施例，所述发光二极管芯片还包括与所述阴极电连接的阴极衬垫，所述阴极衬垫和所述多个发光区彼此间隔设置。
根据一些示例性的实施例，所述第二发光二极管芯片的多个发光区中的一些位于所述第二像素单元内，所述多个发光区中的另一些位于所述第三像素单元内，所述第二发光二极管芯片的发光区的数量大于所述第一发光二极管芯片的发光区的数量。
根据一些示例性的实施例，所述第三发光二极管芯片的多个发光区中的一些位于所述第四像素单元内，所述多个发光区中的另一些分别位于所述五像素单元、所述第六像素单元和所述第七像素单元内，所述第三发光二极管芯片的发光区的数量大于所述第二发光二极管芯片的发光区的数量。
根据一些示例性的实施例，所述第二发光二极管芯片的阴极衬垫在所述基底上的正投影位于所述第二像素单元与所述第三像素单元的交界处。
根据一些示例性的实施例，所述第三发光二极管芯片的阴极衬垫在所述基底上的正投影位于所述第四像素单元、所述第五像素单元、所述第六像素单元和所述第七像素单元的交界处。
根据一些示例性的实施例，所述发光二极管芯片的多个发光区彼此之间的间隔距离在8微米以上。
根据一些示例性的实施例，所述显示基板还包括布线区，所述布线区位于至少一个所述侧边缘；所述显示基板还包括位于所述布线区中的多条走线，所述多条走线用于分别给所述多个发光二极管芯片提供电信号。
根据一些示例性的实施例，所述显示基板还包括多个光转换部，所述多个光转换部在所述衬底基板上的正投影与所述多个发光区在所述衬底基板上的正投影分别至少部分重叠。
在另一方面，提供一种拼接显示装置，包括：多个第一显示基板和多个第二显示基板，其中，所述多个第一显示基板和多个第二显示基板分别为如上所述的显示基板，其中，所述第一显示基板的侧边缘沿第一方向与所述第二显示基板的侧边缘拼接，和/或，所述第一显示基板的侧边缘沿第二方向与所述第二显示基板的侧边缘拼接，所述第一方向和所述第二方向相交。
根据一些示例性的实施例，所述第一显示基板和所述第二显示基板沿拼接处成轴对称分布，所述拼接处包括所述第一显示基板靠近第二基板的侧边缘和第二显示基板 靠近第一显示基板的侧边缘。
在又一方面，提供一种显示装置，包括：如上所述的拼接显示面板；以及，驱动电路，所述驱动电路用于驱动所述拼接显示面板。
附图说明
通过下文中参照附图对本公开所作的描述，本公开的其它目的和优点将显而易见，并可帮助对本公开有全面的理解。
图1是根据本公开的一些示例性实施例的显示基板的平面示意图；
图2是根据本公开的一些示例性实施例的显示基板的部分平面图；
图3是根据本公开的一些示例性实施例的显示基板包括的第一发光二极管芯片的局部放大图；
图4是根据本公开的一些示例性实施例的显示基板包括的第二发光二极管芯片或第四发光二极管芯片的局部放大图；
图5是根据本公开的一些示例性实施例的显示基板包括的第三发光二极管芯片的局部放大图；
图6是根据本公开的一些示例性实施例的显示基板沿图3、图4或图5中的线AA’截取的截面图；
图7是根据本公开的一些示例性实施例的显示基板沿图2中的线BB’截取的截面图；
图8A至图8G是示意性示出所述显示基板的制造方法的一些步骤被执行后形成的结构的截面图；
图9是根据本公开的一些示例性实施例的显示面板的部分平面图；
图10是根据本公开的一些示例性实施例的显示面板沿图5中的线CC’截取的截面图；
图11A和图11B分别是根据本公开的另一些示例性实施例的显示面板的部分平面图；
图12是根据本公开的一些示例性实施例的显示基板在图2中的部分I处的局部放大图；以及
图13示意性示出了根据本公开的一些示例性实施例的第三发光二极管芯片的平 面示意图。
需要注意的是，为了清晰起见，在用于描述本公开的实施例的附图中，层、结构或区域的尺寸可能被放大或缩小，即这些附图并非按照实际的比例绘制。
具体实施方式
在下面的描述中，出于解释的目的，阐述了许多具体细节以提供对各种示例性实施例的全面的理解。然而，明显的是，在不具有这些具体细节或者具有一个或多个等同布置的情况下，可以实施各种示例性实施例。在其它情况下，以框图形式示出了公知的结构和装置，以避免使各种示例性实施例不必要地模糊。此外，各种示例性实施例可以是不同的，但不必是排他的。例如，在不脱离发明构思的情况下，可以在另一示例性实施例中使用或实施示例性实施例的具体形状、配置和特性。
在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。当可以不同地实施示例性实施例时，可以与描述的顺序不同地执行具体的工艺顺序。例如，可以基本上同时执行或者以与描述的顺序相反的顺序执行两个连续描述的工艺。此外，同样的附图标记表示同样的元件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在……之间”对“直接在……之间”、“相邻”对“直接相邻”或“在……上”对“直接在……上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XYY、YZ和ZZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
应该理解的是，尽管在这里可使用术语第一、第二等来描述不同的元件，但是这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件区分开来。例如，在不脱离示例实施例的范围的情况下，第一元件可以被命名为第二元件，类似地，第二元件可以被命名为第一元件。
在本文中，无机发光二极管是指利用无机材料制成的发光元件，其中，LED表示有别于OLED的无机发光元件。具体地，无机发光元件可以包括次毫米发光二极管(Mini Light Emitting Diode，英文缩写为Mini LED)和微型发光二极管(Micro Light Emitting Diode，英文缩写为Micro LED)。其中，微型发光二极管(即Micro LED)指的是晶粒尺寸在100微米以下的超小型发光二极管，次毫米发光二极管(即Mini LED)是指晶粒尺寸在Micro LED与传统LED之间的小型发光二极管，例如，Mini LED的晶粒尺寸可以在100～300微米之间，Micro LED的晶粒尺寸可以在10～100微米之间。
本公开的一些示例性实施例提供了一种显示基板和包括所述显示基板的显示面板和显示装置。例如，一种显示基板，包括：衬底基板，所述衬底基板包括至少一个侧边缘和显示区域；设置在所述显示区域中的多个像素单元，所述多个像素单元包括位于所述显示区域的第一像素单元、第二像素单元和第三像素单元，其中，所述多个第二像素单元位于所述多个第一像素单元靠近所述侧边缘的一侧，所述多个第二像素单元的边缘包括所述侧边缘，所述第三像素单元位于所述第一像素单元和所述第二像素单元之间，所述第三像素单元邻接所述第二像素单元；以及设置在所述衬底基板上的多个发光二极管芯片，所述多个发光二极管芯片包括第一发光二极管芯片和第二发光二极管芯片，其中，所述第一发光二极管芯片位于所述第一像素单元内，所述第二发光二极管芯片的一部分位于第二像素单元内，所述第二发光二极管芯片的其他部分位于所述第三像素单元内。
再例如，本公开的一些实施例提供了一种显示基板，包括：衬底基板，所述衬底基板包括第一侧边缘和远离所述第一侧边缘的第一区域；设置在所述衬底基板上的多个像素单元，所述多个像素单元包括位于所述第一区域的第一像素单元和靠近所述第一侧边缘的第二像素单元，所述第一像素单元位于所述第二像素单元远离所述第一侧边缘的一侧；设置在所述衬底基板上的多个发光二极管芯片，所述多个发光二极管芯片包括第一发光二极管芯片和第二发光二极管芯片，其中，所述第一发光二极管芯片位于所述第一像素单元内，所述第二发光二极管芯片的至少一部分位于所述第二像素 单元内，其中，所述第二像素单元包括靠近所述第一侧边缘的第二像素单元边界，所述第二发光二极管芯片包括靠近所述第一侧边缘的第二芯片侧部，所述第二芯片侧部在所述衬底基板上的正投影与所述第二像素单元边界在所述衬底基板上的正投影之间的垂直距离大于等于规定距离；以及所述第一像素单元包括平行于所述第一侧边缘的第一像素单元边界，所述第一发光二极管芯片具有靠近所述第一像素单元边界的第一芯片侧部，所述第一芯片侧部在所述衬底基板上的正投影与所述第一像素单元边界在所述衬底基板上的正投影之间的垂直距离小于所述第二芯片侧部在所述衬底基板上的正投影与所述第二像素单元边界在所述衬底基板上的正投影之间的垂直距离。
这样，在本公开的实施例中，可以在显示基板的侧边缘处预留出较大的拼接距离，有利于多个显示基板的拼接。
引线键合(Wire Bonding)是一种利用热、压力或超声波能量使金属键合引线与基板焊盘紧密焊合的工艺。例如，在IC封装中，可以利用引线键合，将半导体芯片焊区与微电子封装的I/O键合引线或基板上的金属布线焊区用金属细丝连接起来。引线键合的原理是采用加热、加压或超声波等方式破坏被焊表面的氧化层和污染，产生塑性变形，使得金属键合引线与被焊面亲密接触，达到原子间的引力范围并导致界面间原子扩散而形成焊合点。
图1是根据本公开的一些示例性实施例的显示基板的平面示意图。结合参照图1，所述显示基板可以包括：衬底基板1；设置在所述衬底基板1上的多个像素单元PX；设置在所述衬底基板1上的多个发光二极管芯片5。在本公开的实施例中，所述多个发光二极管芯片5包括第一发光二极管芯片51和第二发光二极管芯片52。例如，第二发光二极管芯片52设置在靠近显示基板的侧边缘的像素单元中，第一发光二极管芯片51设置在远离显示基板的侧边缘的像素单元中。在本公开的实施例中，所述显示基板可以作为拼接显示面板的一块显示基板使用。例如，在图1的实施例中，在显示基板的上侧、右侧和下侧都示意性示出了拼接区域PJ。第二发光二极管芯片52可以设置在靠近拼接区域PJ的像素单元PX中。
继续参照图1，所述多个发光二极管芯片5包括第二发光二极管芯片52和第四发光二极管芯片53。例如，第二发光二极管芯片52可以设置在靠近右侧边缘的拼接区域的像素单元中，第四发光二极管芯片53可以设置在靠近上侧边缘和下侧边缘的拼接区域的像素单元中。可选地，第二发光二极管芯片52和第四发光二极管芯片53的规 格和尺寸等参考可以基本相同，但是，在设置到衬底基板1上时，第二发光二极管芯片52可以相对于第四发光二极管芯片53旋转一定的角度，例如，旋转90°。
需要说明的是，在本文中，第二发光二极管芯片52和第四发光二极管芯片53的规格和尺寸等参考可以基本相同，因此，在其他部分，为了方便描述，第二发光二极管芯片52和第四发光二极管芯片53可以统称为第二发光二极管芯片。
继续参照图1，所述多个发光二极管芯片5包括第三发光二极管芯片54。例如，第三发光二极管芯片54可以设置在靠近拼接区域且靠近显示基板的各个拐角的像素单元中。在图1所示的实施例中，第三发光二极管芯片54可以分别设置在显示基板的右上角和右下角。
图2是根据本公开的一些示例性实施例的显示基板的部分平面图，图3是根据本公开的一些示例性实施例的显示基板包括的第一发光二极管芯片的局部放大图。图4是根据本公开的一些示例性实施例的显示基板包括的第二发光二极管芯片或第四发光二极管芯片的局部放大图。图5是根据本公开的一些示例性实施例的显示基板包括的第三发光二极管芯片的局部放大图。图6是根据本公开的一些示例性实施例的显示基板沿图3、图4或图5中的线AA’截取的截面图。
结合参照图1至图6，所述显示基板可以包括：衬底基板1，所述衬底基板1包括第一侧边缘11和远离所述第一侧边缘11的第一区域AA；设置在所述衬底基板1上的多个像素单元PX，所述多个像素单元PX包括位于所述第一区域AA中的第一像素单元PX1和靠近所述第一侧边缘11的第二像素单元PX2，所述第一像素单元PX1位于所述第二像素单元PX2远离所述第一侧边缘11的一侧；设置在所述衬底基板1上的多个发光二极管芯片5，所述多个发光二极管芯片5包括第一发光二极管芯片51和第二发光二极管芯片52，其中，所述第一发光二极管芯片51位于所述第一像素单元PX1内，所述第二发光二极管芯片52的至少一部分位于所述第二像素单元PX2内。
需要说明的是，在本文中，除非另有说明，表述“侧边缘”表示基板、部件或元件的侧表面，在例如图1或图2的平面图中，“侧边缘”示出为一条线，例如，第一侧边缘11为最左侧的一条线。
如图2所示，所述第二像素单元PX2包括靠近所述第一侧边缘11的第二像素单元边界PX21，所述第二发光二极管芯片52包括靠近所述第一侧边缘11的第二芯片侧部521，所述第二芯片侧部521在所述衬底基板1上的正投影与所述第二像素单元边 界PX21在所述衬底基板1上的正投影之间的垂直距离(例如图2中的L2)大于等于规定距离。需要说明的是，此处的“规定距离”可以是能够实现拼接显示面板的拼接距离，关于“规定距离”和“拼接距离”，将在下文中更详细地描述。
例如，所述第一像素单元PX1包括平行于所述第一侧边缘11的第一像素单元边界PX11，所述第一发光二极管芯片51具有靠近所述第一像素单元边界PX11的第一芯片侧部511，所述第一芯片侧部511在所述衬底基板1上的正投影与所述第一像素单元边界PX11在所述衬底基板1上的正投影之间的垂直距离(例如图2中的L1)小于所述第二芯片侧部521在所述衬底基板1上的正投影与所述第二像素单元边界PX21在所述衬底基板1上的正投影之间的垂直距离(例如图2中的L2)。即，所述第二发光二极管芯片52与对应的第二像素单元PX2靠近侧边缘的边界之间的最短距离大于所述第一发光二极管芯片51与对应的像素单元PX1的边缘之间的最短距离。
在图2的示例性实施例中，示意性示出了第一方向X和第二方向Y，例如，多个像素单元PX可以沿第一方向X和第二方向Y成阵列排布，第一方向X可以对应像素单元排列的行方向，第二方向Y可以对应像素单元排列的列方向。需要说明的是，本公开的实施例并不局限于此。
例如，衬底基板1可以具有矩形、圆角矩形、四边形等形状，第一侧边缘11可以是衬底基板1的4个侧边缘中沿第二方向Y延伸的一个侧边缘。如图2所示，第一侧边缘11可以是衬底基板1的右侧边缘。第二像素单元PX2可以是最靠近第一侧边缘11的一列像素单元中的某一个像素单元。
在本公开的实施例中，最靠近第一侧边缘11的一列像素单元中的发光二极管芯片远离第一侧边缘11设置，这样，可以在显示基板的侧边缘处预留出较大的拼接距离，有利于多个显示基板的拼接。关于“拼接”这一点，将在下文中更详细描述。
例如，所述第二发光二极管芯片52在所述衬底基板1上的正投影的面积大于所述第一发光二极管芯片51在所述衬底基板1上的正投影的面积，并且，所述第二发光二极管芯片52在所述衬底基板1上的正投影的面积小于2倍的所述第一发光二极管芯片51在所述衬底基板1上的正投影的面积。
例如，所述第二发光二极管芯片52位于所述第二像素单元PX2内的部分在所述衬底基板1上的正投影的面积小于所述第一发光二极管芯片51在所述衬底基板1上的正投影的面积。通过这样的设置，有利于最靠近第一侧边缘11的一列像素单元中的发 光二极管芯片远离第一侧边缘11设置，从而有利于实现显示基板的拼接。
继续参照图2，所述衬底基板1还可以包括第二侧边缘12，所述第二侧边缘12与所述第一侧边缘11相连接。示例性地，第二侧边缘12可以是衬底基板1的4个侧边缘中沿第一方向X延伸的一个侧边缘。例如，第二侧边缘12可以是衬底基板1的下侧边缘。
所述多个像素单元PX还可以包括靠近所述第二侧边缘12的第八像素单元PX3，所述多个发光二极管芯片5还包括第四发光二极管芯片53，所述第四发光二极管芯片53的至少一部分位于所述第八像素单元PX3内。
所述第八像素单元PX3包括靠近所述第二侧边缘12的第八像素单元边界PX31，所述第四发光二极管芯片53包括靠近所述第二侧边缘12的第三芯片侧部531，所述第三芯片侧部531在所述衬底基板1上的正投影与所述第八像素单元边界PX31在所述衬底基板1上的正投影之间的垂直距离(例如图2中的L3)大于等于所述规定距离。
例如，所述第四发光二极管芯片53在所述衬底基板1上的正投影的面积大于所述第一发光二极管芯片51在所述衬底基板1上的正投影的面积，并且，所述第四发光二极管芯片53在所述衬底基板1上的正投影的面积小于2倍的所述第一发光二极管芯片51在所述衬底基板1上的正投影的面积。
例如，所述第四发光二极管芯片53在所述衬底基板1上的正投影的面积可以基本等于所述第二发光二极管芯片52在所述衬底基板1上的正投影的面积。
例如，所述第四发光二极管芯片53位于所述第八像素单元PX3内的部分在所述衬底基板1上的正投影的面积小于所述第一发光二极管芯片51在所述衬底基板1上的正投影的面积。
继续参照图2，所述多个像素单元PX还包括第三像素单元PX4，所述第三像素单元PX4邻接所述第二像素单元PX2，所述第三像素单元PX4在垂直于所述第一侧边缘11的方向(例如第一方向X)上位于所述第一像素单元PX1与所述第二像素单元PX2之间，所述第三像素单元PX4和所述第二像素单元PX2在垂直于所述第一侧边缘的方向上位于同一行。
在本公开的实施例中，所述第二像素单元PX2和所述第三像素单元PX4可以共用所述第二发光二极管芯片52。参照图2，所述第二发光二极管芯片52的一部分位于所述第二像素单元PX2中，所述第二发光二极管芯片52的另一部分位于所述第三像素 单元PX4中。
为了描述方便，可以将所述第二发光二极管芯片52位于第二像素单元PX2中的部分称为第一部分，将所述第二发光二极管芯片52位于第三像素单元PX4中的部分称为第二部分。例如，所述第二发光二极管芯片52的第一部分在衬底基板1上的正投影的面积可以基本等于所述第二发光二极管芯片52的第二部分在衬底基板1上的正投影的面积。但是，本公开的实施例不局限于此。
参照图2，所述多个像素单元PX还包括第九像素单元PX5，所述第九像素单元PX5邻接所述第八像素单元PX3，所述第九像素单元PX5在垂直于所述第二侧边缘12的方向(即第二方向Y)上位于所述第一像素单元PX1与所述第八像素单元PX3之间，所述第九像素单元PX5和所述第八像素单元PX3在垂直于所述第二侧边缘12的方向上位于同一列。
在本公开的实施例中，所述第八像素单元PX3和所述第九像素单元PX5可以共用所述第四发光二极管芯片53。参照图2，所述第四发光二极管芯片53的一部分位于所述第八像素单元PX3中，所述第四发光二极管芯片53的另一部分位于所述第九像素单元PX5中。
同样地，为了描述方便，可以将所述第四发光二极管芯片53位于第八像素单元PX3中的部分称为第一部分，将所述第四发光二极管芯片53位于第九像素单元PX5中的部分称为第二部分。例如，所述第四发光二极管芯片53的第一部分在衬底基板1上的正投影的面积可以基本等于所述第四发光二极管芯片53的第二部分在衬底基板1上的正投影的面积。但是，本公开的实施例不局限于此。
继续参照图2，所述多个像素单元PX还可以包括第四像素单元PX6、第五像素单元PX7、第六像素单元PX8和第七像素单元PX9。所述第四像素单元PX6邻接所述第一侧边缘11和所述第二侧边缘12的连接位置，例如，所述第一侧边缘11和所述第二侧边缘12的连接位置可以对应衬底基板1的拐角。所述第五像素单元PX7在平行于所述第一侧边缘11的方向上邻接所述第四像素单元PX6，所述第六像素单元PX8在平行于所述第二侧边缘12的方向上邻接所述第四像素单元PX6，所述第七像素单元PX9邻接所述第五像素单元PX7和第六像素单元PX8。
在本公开的实施例中，所述多个发光二极管芯片5还包括第三发光二极管芯片54，第四像素单元PX6、第五像素单元PX7、第六像素单元PX8和第七像素单元PX9可以 共用所述第三发光二极管芯片54。参照图2，所述第三发光二极管芯片54包括四个部分(例如第一部分、第二部分、第三部分和第四部分)，其中，所述第三发光二极管芯片54的第一部分位于所述第四像素单元PX6中，所述第三发光二极管芯片54的第二部分位于所述第五像素单元PX7中，所述第三发光二极管芯片54的第三部分位于所述第六像素单元PX8中，所述第三发光二极管芯片54的第四部分位于所述第七像素单元PX9中。例如，所述第三发光二极管芯片54的第一部分、第二部分、第三部分和第四部分在衬底基板1上的正投影的面积可以彼此基本相等。但是，本公开的实施例不局限于此。
换句话说，第四像素单元PX6的边缘包括彼此相交的第一侧边缘和第二侧边缘。第三发光二极管芯片54的一部分位于第四像素单元PX6内，所述第三发光二极管芯片54的其他部分位于与所述第四像素单元PX6相邻的像素单元(例如，第五像素单元PX7、第六像素单元PX8、第七像素单元PX9)内，所述第三发光二极管芯片54位于四个相邻的像素单元内。
例如，所述第三发光二极管芯片54的靠近所述第一侧边缘11的侧边在所述衬底基板1上的正投影与所述第一侧边缘11在所述衬底基板1上的正投影之间的垂直距离大于等于规定距离，且所述第三发光二极管芯片54的靠近所述第二侧边缘12的侧边在所述衬底基板1上的正投影与所述第二侧边缘12在所述衬底基板1上的正投影之间的垂直距离大于等于规定距离。即，所述第三发光二极管芯片54与对应的第四像素单元PX6靠近侧边缘的边界之间的最短距离大于所述第一发光二极管芯片51与对应的第一像素单元PX1的边缘之间的最短距离。
例如，所述第二发光二极管芯片52或所述第四发光二极管芯片53在所述衬底基板1上的正投影的面积小于所述第三发光二极管芯片54在所述衬底基板1上的正投影的面积。
所述第三发光二极管芯片54位于所述第四像素单元PX6内的部分在所述衬底基板上的正投影的面积小于所述第一发光二极管芯片51在所述衬底基板上的正投影的面积。
所述第三发光二极管芯片54在所述衬底基板上的正投影的面积大于所述第一发光二极管芯片51在所述衬底基板上的正投影的面积，且所述第三发光二极管芯片54在所述衬底基板上的正投影的面积小于4倍的所述第一发光二极管芯片51在所述衬底 基板上的正投影的面积。
在本公开的实施例中，通过上述设置方式，可以使最靠近显示基板的侧边缘的一列像素单元和一行像素单元中的发光二极管芯片在第一方向或第二方向上均远离所述侧边缘设置，还可以使最靠近显示基板的拐角处的像素单元在第一方向和第二方向上均远离所述拐角设置，从而有利于保证所述显示基板具有足够的拼接距离，有利于实现拼接显示面板和拼接显示装置。
需要说明的是，在本文中，第八像素单元PX3与第二像素单元PX2的结构可以基本相同，二者仅设置方向不同，所以，在其他部分，为了方便描述，第八像素单元PX3与第二像素单元PX2可以统称为第二像素单元；类似地，第九像素单元PX5与第三像素单元PX3的结构可以基本相同，二者仅设置方向不同，所以，在其他部分，为了方便描述，第九像素单元PX5与第三像素单元PX3可以统称为第三像素单元。
图12是根据本公开的一些示例性实施例的显示基板在图2中的部分I处的局部放大图。结合参照图2、图4和图12，用多个矩形方框示意性示出了多个边界，例如，矩形方框R1表示像素单元的边界，矩形方框R2表示发光二极管芯片的边界，矩形方框R3表示保护层的边界，矩形方框R4表示发光二极管芯片的多个发光区或PAD的边界。例如，在将多个发光二极管芯片转移到衬底基板上的过程中，受限于转移工艺的精度，可能产生一定的位置偏差。考虑到该位置偏差，矩形方框R1与矩形方框R2之间沿第一方向X和第二方向Y均存在一定的间隔距离，该间隔距离被设计为避免相邻的2个发光二极管芯片产生干涉。再例如，矩形方框R2与矩形方框R3之间沿第一方向X和第二方向Y均存在一定的间隔距离，该间隔距离考虑在激光切割芯片时产生的工艺误差。再例如，矩形方框R2与矩形方框R3之间沿第一方向X和第二方向Y均存在一定的间隔距离，该间隔距离考虑在形成保护层时产生的工艺误差。
在本公开的实施例中，结合参照图2至图6，发光二极管芯片5(可以是第一发光二极管芯片51、第二发光二极管芯片52、第四发光二极管芯片53或第三发光二极管芯片54)可以包括基底5S、发光区5A、阴极5C和阳极5B。例如，基底5S可以为蓝宝石基底。发光二极管芯片5可以具有倒装芯片结构。发光区5A被夹设在阴极5C和阳极5B之间。一个发光二极管芯片5可以包括多个发光区5A，每一个发光区5A分别对应一个阳极5B。每一个阳极5B与对应的阳极衬垫(即阳极pad)5P1电连接。一个发光二极管芯片5可以具有一个共同的阴极5C，该阴极5C与阴极衬垫(即阴极 pad)5P2电连接。通过阳极衬垫5P1和阴极衬垫5P2，可以分别给阳极5B和阴极5C供应指定的电信号。例如，在一个发光二极管芯片5内，所述多个发光区5A和所述多个阳极5B一一对应，所述多个发光区5C彼此间隔设置，所述阴极衬垫5P2和所述多个发光区5C彼此间隔设置。
结合参照图3和图6，第一发光二极管芯片51可以包括3个发光区5A，相应地，第一发光二极管芯片51可以包括3个阳极5B和1个共同的阴极5C。3个发光区5A分别与3个阳极5B一一对应。3个阳极5B分别与3个阳极衬垫5P1电连接，1个共同的阴极5C与阴极衬垫5P2电连接。例如，3个发光区5A可以分别被配置为发出红光、绿光和蓝光。为了描述方便，将发出红光的发光区称为第一发光区5A1，发出绿光的发光区称为第二发光区5A2，发出蓝光的发光区称为第三发光区5A3。
例如，第一发光区5A1在基底5S上的正投影的面积大于第二发光区5A2在基底5S上的正投影的面积，第二发光区5A2在基底5S上的正投影的面积大于第三发光区5A3在基底5S上的正投影的面积。
参照图3，第一发光二极管芯片51的第一发光区5A1、第二发光区5A2、第三发光区5A3和阴极衬垫5P2在第一发光二极管芯片51的基底5S上的正投影彼此间隔布置，例如，它们分别位于基底5S的4个拐角处。
例如，第一发光二极管芯片51的第一发光区5A1、第二发光区5A2、第三发光区5A3在第一发光二极管芯片51的基底5S上的正投影可以分别覆盖各自对应的阳极衬垫5P1在第一发光二极管芯片51的基底5S上的正投影。
结合参照图2、图4和图6，第二发光二极管芯片52或第四发光二极管芯片53可以包括6个发光区5A，相应地，第二发光二极管芯片52或第四发光二极管芯片53可以包括6个阳极5B和1个共同的阴极5C。3个发光区5A分别与6个阳极5B一一对应。6个阳极5B分别与6个阳极衬垫5P1电连接，1个共同的阴极5C与阴极衬垫5P2电连接。例如，在6个发光区中，3个发光区5A为一组，可以分别被配置为发出红光、绿光和蓝光。为了描述方便，将发出红光的发光区称为第一发光区5A1，发出绿光的发光区称为第二发光区5A2，发出蓝光的发光区称为第三发光区5A3。
例如，第二发光二极管芯片52或第四发光二极管芯片53的多个发光区5A中的一些位于所述第二像素单元内，所述多个发光区5A中的另一些位于所述第一像素单元内，所述第二发光二极管芯片52或第四发光二极管芯片53的发光区5A的数量大 于所述第一发光二极管芯片51的发光区的数量。
例如，第一发光区5A1在基底5S上的正投影的面积大于第二发光区5A2在基底5S上的正投影的面积，第二发光区5A2在基底5S上的正投影的面积大于第三发光区5A3在基底5S上的正投影的面积。
参照图2，一组发光区5A1、5A2、5A3位于共用第二发光二极管芯片52或第四发光二极管芯片53的一个像素单元中，另一组发光区5A1、5A2、5A3位于共用第二发光二极管芯片52或第四发光二极管芯片53的另一个像素单元中。
第二发光二极管芯片52的6个发光区和阴极衬垫5P2在第二发光二极管芯片52的基底5S上的正投影彼此间隔布置。例如，第二发光二极管芯片52的2个第一发光区5A1在其基底5S上的正投影分别位于基底5S的相对的2个拐角处。第二发光二极管芯片52的2个第二发光区5A2在其基底5S上的正投影分别位于基底5S的相对的2个拐角处。第二发光二极管芯片52的2个第三发光区5A3在其基底5S上的正投影分别位于基底5S的相对的2条侧边处。例如，第二发光二极管芯片52的1个第三发光区5A3在其基底5S上的正投影位于1个第一发光区5A1与1个第二发光区5A2在其基底5S上的正投影的中间位置处。
例如，第二发光二极管芯片52的阴极衬垫5P2在其基底5S上的正投影可以大致位于其基底5S的几何中心处。例如，第二发光二极管芯片52的阴极衬垫5P2在其基底5S上的正投影大致位于其基底5S的两条对角线相交的位置。或者，所述第二发光二极管芯片52的阴极衬垫5P2在其基底5S上的正投影位于所述第一像素单元与所述第二像素单元的交界处。
例如，第二发光二极管芯片52的第一发光区5A1、第二发光区5A2、第三发光区5A3在第二发光二极管芯片52的基底5S上的正投影可以分别覆盖各自对应的阳极衬垫5P1在第二发光二极管芯片52的基底5S上的正投影。
结合参照图2、图5和图6，第三发光二极管芯片54可以包括12个发光区5A，相应地，第三发光二极管芯片54可以包括12个阳极5B和1个共同的阴极5C。12个发光区5A分别与12个阳极5B一一对应。12个阳极5B分别与12个阳极衬垫5P1电连接，1个共同的阴极5C与阴极衬垫5P2电连接。例如，在12个发光区中，3个发光区5A为一组，可以分别被配置为发出红光、绿光和蓝光。为了描述方便，将发出红光的发光区称为第一发光区5A1，发出绿光的发光区称为第二发光区5A2，发出蓝 光的发光区称为第三发光区5A3。
例如，所述第三发光二极管芯片54的多个发光区5A中的一些位于所述第三像素单元内，所述多个发光区中5A的另一些位于所述第一像素单元和所述第二像素单元内，所述第三发光二极管芯片54的发光区5A的数量大于所述第二发光二极管芯片52的发光区5A的数量。
例如，第一发光区5A1在基底5S上的正投影的面积大于第二发光区5A2在基底5S上的正投影的面积，第二发光区5A2在基底5S上的正投影的面积大于第三发光区5A3在基底5S上的正投影的面积。
参照图2，每一组发光区5A1、5A2、5A3位于共用第三发光二极管芯片54的4个像素单元中的1个像素单元中。
第三发光二极管芯片54的12个发光区和阴极衬垫5P2在第三发光二极管芯片54的基底5S上的正投影彼此间隔布置。
例如，第三发光二极管芯片54的阴极衬垫5P2在其基底5S上的正投影可以大致位于其基底5S的几何中心处。例如，第三发光二极管芯片54的阴极衬垫5P2在其基底5S上的正投影大致位于其基底5S的两条对角线相交的位置。或二者，所述第三发光二极管芯片54的阴极衬垫5P2在其基底5S上的正投影位于所述第一像素单元、所述第二像素单元和所述第三像素单元的交界处。
例如，第三发光二极管芯片54的第一发光区5A1、第二发光区5A2、第三发光区5A3在第三发光二极管芯片54的基底5S上的正投影可以分别覆盖各自对应的阳极衬垫5P1在第三发光二极管芯片54的基底5S上的正投影。
继续参照图2，所述第二发光二极管芯片52可以包括多个发光区5A、多个阳极5B和一个阴极5C，所述多个发光区5A和所述多个阳极5B一一对应，所述多个发光区5A彼此间隔设置，所述多个发光区5A中的一些位于所述第二像素单元PX2内，所述多个发光区5A中的另一些位于所述第三像素单元PX4内。例如，在图2所示的实施例中，所述第二发光二极管芯片52可以包括6个发光区5A、6个阳极5B和一个阴极5C，其中，3个发光区5A位于所述第二像素单元PX2内，另外3个发光区5A位于所述第三像素单元PX4内。
类似地，所述第四发光二极管芯片53包括多个发光区5A、多个阳极5B和一个阴极5C，所述第四发光二极管芯片53的多个发光区5A和所述第四发光二极管芯片53 的多个阳极5B一一对应，所述第四发光二极管芯片53的多个发光区5A彼此间隔设置，所述第四发光二极管芯片53的多个发光区5A中的一些位于所述第八像素单元PX3内，所述第四发光二极管芯片53的多个发光区5A中的另一些位于所述第九像素单元PX5内。例如，在图2所示的实施例中，所述第四发光二极管芯片53可以包括6个发光区5A、6个阳极5B和一个阴极5C，其中，3个发光区5A位于所述第八像素单元PX3内，另外3个发光区5A位于所述第九像素单元PX5内。
所述第三发光二极管芯片54可以包括多个发光区5A、多个阳极5B和一个阴极5C，所述第三发光二极管芯片54的多个发光区5A和所述第三发光二极管芯片54的多个阳极5B一一对应，所述第三发光二极管芯片54的多个发光区5A彼此间隔设置，所述第三发光二极管芯片54的多个发光区5A中的第一部分位于所述第四像素单元PX6内，所述第三发光二极管芯片54的多个发光区5A中的第二部分位于所述第五像素单元PX7内，所述第三发光二极管芯片54的多个发光区5A中的第三部分位于所述第六像素单元PX8内，所述第三发光二极管芯片54的多个发光区5A中的第四部分位于所述第七像素单元PX9内。例如，分别有3个发光区5A设置在第四像素单元PX6、第五像素单元PX7、第六像素单元PX8和第七像素单元PX9内。
结合参照图2至图6，在本公开的实施例中，所述显示基板采用发光二极管芯片5和光转换部600的方式，以实现彩色显示。例如，所述光转换部可以包括量子点等光转换材料，用于将第一波长的光转换成第二波长的光。示例性地，所述发光二极管芯片为发射蓝光的LED芯片，所述光转换部包括用于将蓝光转换成红光的第一光转换部；和用于将蓝光转换成滤光的第二光转换部。
如图6所示，示意性示出了发光二极管芯片和光转换部的部分结构。在图6所示的实施例中，光转换部600设置在基底5S远离发光区5A的一侧，即，光转换部600和发光区5A分别设置在基底5S的两侧。多个光转换部600分别与多个发光区5A一一对应。例如，所述多个光转换部600在所述衬底基板1上的正投影与所述多个发光区5A在所述衬底基板1上的正投影分别至少部分重叠。
为了避免相邻的子像素之间产生串色，在相邻的光转换部600之间设置有遮光部400。如图6所示，根据从发光区5A发射的光的光路，可以计算出遮光部400的宽度，即，计算出相邻的光转换部600之间的间隔距离。例如，发明人经研究发现，相邻的光转换部600之间的间隔距离在8微米以上。具体地，在本公开的实施例中，所述第 二发光二极管芯片52的多个发光区彼此之间的间隔距离在8微米以上。所述第四发光二极管芯片53的多个发光区彼此之间的间隔距离在8微米以上。所述第三发光二极管芯片54的多个发光区彼此之间的间隔距离在8微米以上。这样，可以在缩小发光二极管芯片的面积的同时，避免相邻的子像素之间产生串色。
图7是根据本公开的一些示例性实施例的显示基板沿图2中的线BB’截取的截面图。在制造根据本公开的实施例的显示基板的过程中，通常需要将承载有电路板或集成电路的基板(下文中称为第二衬底基板)折叠或翻转到衬底基板的背面，并通过键合引线电连接位于衬底基板正面的发光二极管芯片的端子(即PAD)和位于衬底基板背面的电路。图8A至图8G是示意性示出所述显示基板的制造方法的一些步骤被执行后形成的结构的截面图。结合参照图7以及图8A至图8G，所述显示基板的制造方法可以按照以下步骤执行。
在步骤S101中，提供第一基板100。
参照图2和图8A，第一基板100可以包括衬底基板1以及设置在衬底基板1上的多个第一电极2和多个第一端子3。多个第一端子3位于所述第一基板100的边缘位置。例如，多个第一端子3位于所述第一基板100的扇出区(即fan-out区)，用于将位于所述第一基板100上的信号线(例如，该信号线电连接至各个发光二极管的端子)电连接至外部驱动电路。
例如，衬底基板1的材料可以包括但不限于玻璃，石英，塑料，硅，聚酰亚胺等。第一电极2和第一端子3可以为柱状结构。第一电极2和第一端子3的材料可以包括导电材料，例如金属材料等，具体地，可以为金、银、铜、铝、钼、金合金、银合金、铜合金、铝合金、钼合金等中选择的至少一种或者至少两种的组合，本公开的实施例对此不作限制。
例如，所述第一基板100还可以包括与多个第一电极2电连接的驱动电路4，该驱动电路4设置在衬底基板1上。该驱动电路4可以用于向后续形成在多个第一电极2上的发光二极管芯片提供电信号，控制其发光亮度。例如，在一些示例中，该驱动电路4可以为与每个发光二极管芯片一一对应连接的多个像素驱动电路，或者是与每个发光二极管芯片一一对应连接的多个微型集成电路芯片等结构，可以控制每个发光二极管芯片发出不同的亮度灰阶。需要说明的是，第一基板100上的驱动电路4的具体电路结构可以根据实际需要进行设置，本公开的实施例对此不作限制。在下文中， 将结合附图对驱动电路4进行示例性说明。
在步骤S102中，将多个发光二极管芯片5转移并绑定至所述第一基板100上。
参照图2和图8B，将多个发光二极管芯片5中的每个都包括N电极和P电极，发光二极管芯片5的N电极和P电极分别连接到对应的第一电极2，而多个第一端子3的表面裸露在外。
参照图2，多个发光二极管芯片沿第一方向X和第二方向Y成阵列地排列。例如，第一方向X为行方向且第二方向Y为列方向。当然，本公开的实施例不限于此，第一方向和第二方向可以为任意的方向，只需使第一方向和第二方向交叉即可。并且，多个发光二极管芯片也不限于沿直线排列，也可以沿曲线排列、沿环形排列或按照任意的方式排列，这可以根据实际需求而定，本公开的实施例对此不作限制。
例如，所述发光二极管芯片可以包括微型发光二极管(Micro LED)或次毫米发光二极管(Mini LED)。
在步骤S103中，提供第二基板200，并将所述第一基板100和第二基板200置于载具300上。
例如，第二基板200可以为电路板，例如，PCB(Printed Circuit Board，即印刷电路板)、FPC(Flexible Printed Circuit，即柔性电路板)或COF(Chip On Film，即膜上芯片)等。
参照图8C，第二基板200可以包括第二衬底基板6和设置在第二衬底基板6上的多个第二端子7。例如，多个第二端子7可以沿第一方向X(在图8C中为垂直于纸面的方向)排列，即，多个第二端子7构成第二端子行。例如，多个第二端子7可以与多个第一端子3一一对应。即，第二端子7的排列周期与第一端子3的排列周期相同。
当然，第二基板200还可以包括设置在第二衬底基板6上的外部驱动电路，例如，集成电路芯片，但本公开的实施例不局限于此。
载具300用于间隔并固定第一基板100和第二基板200，以保持二者的相对位置关系。参照图8C，第一基板100上设置的第一端子3具有远离衬底基板1的第一表面31(图中示出为上表面)，第二基板200上设置的第二端子7具有远离第二衬底基板6的第二表面71(图中示出为上表面)。
在步骤S104中，结合参照图8C和图8D，在第一端子3所在的第一端子行与第二端子7所在的第二端子行之间的间隙400内形成第一保护胶层8。
例如，可以在间隙400内涂布一定厚度的保护胶，该保护胶至少充满间隙400，并且，由于涂布精度的限制，保护胶还可能会覆盖位于间隙400两侧的第一端子3和第二端子7的表面的至少一部分，但之后可以通过激光烧蚀或去膜的方式去除该保护胶覆盖第一端子3和第二端子7的部分，以免影响后续的工艺，从而得到只填充在间隙400的第一保护胶层8。可以理解，第一保护胶层8在载具300上的正投影覆盖间隙400在载具300上的正投影。
参照图8D，第一保护胶层8靠近第一基板100的侧壁接触第一端子3，第一保护胶层8靠近第二基板100的侧壁接触第二端子7。
例如，第一保护胶层8包括远离载具300的第三表面81。第三表面81、第一表面31和第二表面71基本处于同一水平面，以保证后续的键合引线形成在较为平整的表面上。
例如，第一保护胶层8的厚度在5～500微米的范围内，具体取值与第一端子3和/或第二端子7的厚度相同，第一保护胶层8的所用材料的杨氏模量可以在0.1Mpa～80Gpa之间，例如，所述材料可以为硅胶或聚二甲基硅氧烷(即PDMS)。
在步骤S105中，形成键合引线9，使得所述键合引线9电连接第一端子3与第二端子7。
参照图8E，形成键合引线9，使得键合引线9的一端91连接第一端子3，另一端92连接第二端子7。即，键合引线9的一端91焊接在第一端子3上，另一端92焊接在第二端子7上。端91焊接在第一端子3上的焊点称为第一焊点911，端92在第二端子7上的焊点称为第二焊点921，参照图7。
在图8E所示的实施例中，键合引线9基本在第一端子3和第二端子7所在的平面内延伸，利于后续的弯折工艺。
例如，第一焊点911可以为楔形焊点，即，第一焊点911在衬底基板1上的正投影的形状为楔形。在该情况下，第一焊点911在第一端子3上的高度可以控制在1～10微米之间。键合引线9的直径可以在10～500微米之间。第一焊点911在第一端子3上的高度比键合引线9的直径小，这样，可以实现键合引线9基本在第一端子3和第二端子7所在的平面内延伸。
例如，键合引线9可以采用Cu、Al、Au、Ag等金属或其合金。
结合参照图8E，每一根键合引线9分别电连接一个第一端子3和与它对应的第二 端子7。由于多个第一端子3沿所述第一方向X等间距地布置，所以，多根键合引线9也沿第一方向X等间距地排列。
在步骤S106中，在第一端子3、第二端子7和键合引线9中的每一个远离衬底基板1和第二衬底基板6的表面上形成第二保护胶层110。
参照图8F，第二保护胶层110在垂直于所述第一表面31的方向上的正投影覆盖第一端子3、第二端子7和键合引线9中的每一个在垂直于所述第一表面31的方向上的正投影。这样，可以保护键合引线9以及第一端子3和第二端子7中的每一个与键合引线9的焊点。
例如，第二保护胶层110的厚度在5～500微米的范围内，第二保护胶层110所用的材料的杨氏模量可以在0.1Mpa～80Gpa之间，例如，所述材料可以为硅胶或聚二甲基硅氧烷(即PDMS)。
在一些示例中，第二保护胶层110的厚度可以基本等于第一保护胶层8的厚度。这样，可以确保键合引线9处于上下两个保护胶层的中性层处。
在步骤S107中，在衬底基板1远离第一端子3的表面和第二衬底基板6远离第二端子7的表面中的任一个上贴附背胶120。例如，参照图8G，在衬底基板1远离第一端子3的表面上贴附背胶120。
在步骤S108中，结合参照图8G和图7，朝着第一基板100翻转第二基板200，使得第二衬底基板6远离第二端子7的表面贴附至所述背胶120。
以此方式，可以将第二基板200弯折至第一基板100的背面，并且两个基板100和200可以通过背胶120贴附在一起。
例如，在翻转第二基板200的过程中，可通过具有固定旋转轨迹的载具300将第二基板200旋转至第一基板100的下表面，以确保翻转过程的稳定性，降低键合引线9断裂的风险。
参照图7，在步骤S108中，翻转第二基板200，还使得第一保护胶层8远离键合引线9的表面接触第一基板100、背胶120和第二基板200。具体地，第一保护胶层8远离键合引线9的表面接触第一基板100的侧壁、背胶120的侧壁和第二基板200的侧壁。通过这样的方式，第一基板100的侧壁、背胶120的侧壁和第二基板200的侧壁完整地支撑第一保护胶层8，从而完整地支撑键合引线9，以提高信赖性。在根据本公开实施例的显示基板的制造方法中，利用引线键合工艺制作键合引线，并翻转基板 实现上下基板叠层结构，能够降低工艺复杂度，并且降低制造成本。
结合参照图1至图7，在所述显示基板的侧边缘处，需要预留出规定距离D，以设置键合引线9和保护胶层等并使得键合引线9有足够的弯折半径能够弯折到显示基板的背面。具体地，所述规定距离D可以包括第一距离D1、第二距离D2和第三距离D3。例如，第一距离D1可以对应键合引线9在侧边缘处的长度，第二距离D2可以对应键合引线9需要弯折到背面的最小弯折距离，第三距离D3可以对应所述保护胶层的厚度。发明人经研究发现，在目前的工艺条件下，所述规定距离D在150微米以上。
图9是根据本公开的一些示例性实施例的显示面板的部分平面图，图10是根据本公开的一些示例性实施例的显示面板沿图9中的线CC’截取的截面图。结合参照图9和图10，所述显示面板可以为拼接显示基板。例如，所述显示面板可以由2个上述的显示基板拼接而成。为了设置键合引线9和保护胶层等并使得键合引线9有足够的弯折半径能够弯折到显示基板的背面，需要在拼接位置处预留足够的拼接距离。例如，所述拼接距离可以为上述规定距离D的2倍以上。在本公开的实施例中，可以在显示基板的侧边缘处预留出足够的距离，有利于形成拼接显示面板。同时，通过本公开的实施例提供的拼接显示面板，拼接位置处的光效受影响程度较小，有利于提高显示面板的显示效果。
在图9的实施例中，示意性示出了4个结构和规格相同的显示基板拼接在一起形成显示面板的情况。但是，本公开的实施例不局限于此。图11A和图11B分别示意性示出了根据本公开实施例的显示面板的平面示意图。如图11A所示，2个结构和规格相同的显示基板拼接在一起形成显示面板，即，2个显示基板可以沿边界线成轴对称地分布。如图11B所示，4个显示基板拼接在一起形成显示面板，其中，2个相邻显示基板的第二发光二极管芯片或第四发光二极管芯片所在侧边缘相互靠近。
在本公开的实施例中，一个显示基板的侧边缘可以沿第一方向与另一个显示基板的侧边缘拼接。一个显示基板的侧边缘可以沿第二方向与另一个显示基板的侧边缘拼接。
第二像素单元第三像素单元第四发光二极管芯片第四发光二极管芯片第四发光二极管芯片第四发光二极管芯片第八像素单元第九像素单元第四发光二极管芯片第二像素单元第八像素单元在上面的实施例中，各个发光二极管芯片在所述衬底基板1上的 正投影的形状为矩形，但是，本公开的实施例不局限于此，例如，发光二极管芯片在所述衬底基板1上的正投影的形状可以为圆形、椭圆形等其他形状。例如，图13示意性示出了根据本公开的一些示例性实施例的第三发光二极管芯片的平面示意图。在图13所示的实施例中，第三发光二极管芯片在所述衬底基板1上的正投影的形状为圆形。
例如，所述驱动电路4可以包括薄膜晶体管阵列层。该薄膜晶体管阵列层可具体包括有源层、栅极绝缘层、栅极、源极、漏极和平坦层等。驱动电路4的具体膜层结构可以参照已有的阵列基板中应用的膜层结构，在此不再赘述。
本公开的一些示例性实施例还提供一种显示装置。参照图10、图11A和图11B，所述显示装置包括至少2个如上所述的显示基板。至少2个如上所述的显示基板拼接形成显示装置。由于最靠近显示基板的侧边缘的像素单元中的发光二极管芯片远离所述侧边缘设置，所以，在拼接位置处可以预留出足够的拼接距离，例如，该拼接距离可以为所述规定距离D的2倍。这样，有利于形成所述拼接显示装置。
需要说明的是，上述制造方法的一些步骤可以单独执行或组合执行，以及可以并行执行或顺序执行，并不局限于图中所示的具体操作顺序。
应该理解，根据本公开的一些示例性实施例的显示装置具有上述显示基板的所有特点和优点，这些特点和优点可以参照上文针对显示基板的描述，在此不再赘述。
如这里所使用的，术语“基本上”、“大约”、“近似”和其它类似的术语用作近似的术语而不是用作程度的术语，并且它们意图解释将由本领域普通技术人员认识到的测量值或计算值的固有偏差。考虑到工艺波动、测量问题和与特定量的测量有关的误差(即，测量系统的局限性)等因素，如这里所使用的“大约”或“近似”包括所陈述的值，并表示对于本领域普通技术人员所确定的特定值在可接受的偏差范围内。例如，“大约”可以表示在一个或更多个标准偏差内，或者在所陈述的值的±10％或±5％内。
虽然根据本公开的总体发明构思的一些实施例已被图示和说明，本领域普通技术人员将理解，在不远离本公开的总体发明构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，所述衬底基板包括至少一个侧边缘和显示区域；
    设置在所述显示区域中的多个像素单元，所述多个像素单元包括位于所述显示区域的第一像素单元、第二像素单元和第三像素单元，其中，所述多个第二像素单元位于所述多个第一像素单元靠近所述侧边缘的一侧，所述多个第二像素单元的边缘包括所述侧边缘，所述第三像素单元位于所述第一像素单元和所述第二像素单元之间，所述第三像素单元邻接所述第二像素单元；以及
    设置在所述衬底基板上的多个发光二极管芯片，所述多个发光二极管芯片包括第一发光二极管芯片和第二发光二极管芯片，其中，所述第一发光二极管芯片位于所述第一像素单元内，所述第二发光二极管芯片的一部分位于第二像素单元内，所述第二发光二极管芯片的其他部分位于所述第三像素单元内。
  2. 根据权利要求1所述的显示基板，其中，所述第二发光二极管芯片与该第二发光二极管芯片的一部分所在的所述第二像素单元靠近侧边缘的边界之间的最短距离大于所述第一发光二极管芯片与该第一发光二极管芯片所在的第一像素单元的边缘之间的最短距离。
  3. 根据权利要求1或2所述的显示基板，其中，所述第二发光二极管芯片位于所述第二像素单元内的部分在所述衬底基板上的正投影的面积小于所述第一发光二极管芯片在所述衬底基板上的正投影的面积。
  4. 根据权利要求3所述的显示基板，其中，所述第二发光二极管芯片在所述衬底基板上的正投影的面积大于所述第一发光二极管芯片在所述衬底基板上的正投影的面积，且所述第二发光二极管芯片在所述衬底基板上的正投影的面积小于2倍的所述第一发光二极管芯片在所述衬底基板上的正投影的面积。
  5. 根据权利要求1所述的显示基板，其中，所述多个像素单元还包括位于所述显示区域中的第四像素单元、第五像素单元、第六像素单元和第七像素单元，所述第四 像素单元的边缘包括彼此相交的第一侧边缘和第二侧边缘，所述第五像素单元、第六像素单元和第七像素单元分别与所述第四像素单元邻接；
    所述多个发光二极管芯片还包括第三发光二极管芯片，所述第三发光二极管芯片的一部分位于第四像素单元内，所述第三发光二极管芯片的其他部分分别位于第五像素单元、第六像素单元和第七像素单元内。
  6. 根据权利要求5所述的显示基板，其中，所述第三发光二极管芯片与该第三发光二极管芯片的一部分所在的所述第三像素单元靠近侧边缘的边界之间的最短距离大于所述第一发光二极管芯片与该第一发光二极管芯片所在的第一像素单元的边缘之间的最短距离。
  7. 根据权利要求5或6所述的显示基板，其中，所述第三发光二极管芯片位于所述第四像素单元内的部分在所述衬底基板上的正投影的面积小于所述第一发光二极管芯片在所述衬底基板上的正投影的面积。
  8. 根据权利要求7所述的显示基板，其中，所述第三发光二极管芯片在所述衬底基板上的正投影的面积大于所述第一发光二极管芯片在所述衬底基板上的正投影的面积，且所述第三发光二极管芯片在所述衬底基板上的正投影的面积小于4倍的所述第一发光二极管芯片在所述衬底基板上的正投影的面积。
  9. 根据权利要求1或5所述的显示基板，其中，所述发光二极管芯片包括基底和设置于所述基底的多个发光区、多个阳极和一个阴极，所述多个发光区和所述多个阳极一一对应，所述多个发光区彼此间隔设置。
  10. 根据权利要求9所述的显示基板，其中，所述发光二极管芯片还包括与所述阴极电连接的阴极衬垫，所述阴极衬垫和所述多个发光区彼此间隔设置。
  11. 根据权利要求10所述的显示基板，其中，所述第二发光二极管芯片的多个发光区中的一些位于所述第二像素单元内，所述多个发光区中的另一些位于所述第三像素单元内，所述第二发光二极管芯片的发光区的数量大于所述第一发光二极管芯片的 发光区的数量。
  12. 根据权利要求10所述的显示基板，其中，所述第三发光二极管芯片的多个发光区中的一些位于所述第四像素单元内，所述多个发光区中的另一些分别位于所述五像素单元、所述第六像素单元和所述第七像素单元内，所述第三发光二极管芯片的发光区的数量大于所述第二发光二极管芯片的发光区的数量。
  13. 根据权利要求11所述的显示基板，其中，所述第二发光二极管芯片的阴极衬垫在所述基底上的正投影位于所述第二像素单元与所述第三像素单元的交界处。
  14. 根据权利要求13所述的显示基板，其中，所述第三发光二极管芯片的阴极衬垫在所述基底上的正投影位于所述第四像素单元、所述第五像素单元、所述第六像素单元和所述第七像素单元的交界处。
  15. 根据权利要求9所述的显示基板，其中，所述发光二极管芯片的多个发光区彼此之间的间隔距离在8微米以上。
  16. 根据权利要求1或5所述的显示基板，其中，所述显示基板还包括布线区，所述布线区位于至少一个所述侧边缘；
    所述显示基板还包括位于所述布线区中的多条走线，所述多条走线用于分别给所述多个发光二极管芯片提供电信号。
  17. 根据权利要求9所述的显示基板，其中，所述显示基板还包括多个光转换部，所述多个光转换部在所述衬底基板上的正投影与所述多个发光区在所述衬底基板上的正投影分别至少部分重叠。
  18. 一种拼接显示装置，包括：
    多个第一显示基板和多个第二显示基板，其中，所述多个第一显示基板和多个第二显示基板分别为根据权利要求1-17中任一项所述的显示基板，
    其中，所述第一显示基板的侧边缘沿第一方向与所述第二显示基板的侧边缘拼接， 和/或，所述第一显示基板的侧边缘沿第二方向与所述第二显示基板的侧边缘拼接，所述第一方向和所述第二方向相交。
  19. 根据权利要求18所述的拼接显示装置，其中，所述第一显示基板和所述第二显示基板沿拼接处成轴对称分布，所述拼接处包括所述第一显示基板靠近第二基板的侧边缘和第二显示基板靠近第一显示基板的侧边缘。
  20. 一种显示装置，包括：如权利要求18或19所述的拼接显示面板；以及，驱动电路，所述驱动电路用于驱动所述拼接显示面板。
PCT/CN2021/102386 2021-06-25 2021-06-25 显示基板、拼接显示面板和显示装置 Ceased WO2022267008A1 (zh)

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