WO2023000128A1 - 一种光电模块、通信方法及相关设备 - Google Patents

一种光电模块、通信方法及相关设备 Download PDF

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Publication number
WO2023000128A1
WO2023000128A1 PCT/CN2021/107037 CN2021107037W WO2023000128A1 WO 2023000128 A1 WO2023000128 A1 WO 2023000128A1 CN 2021107037 W CN2021107037 W CN 2021107037W WO 2023000128 A1 WO2023000128 A1 WO 2023000128A1
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WIPO (PCT)
Prior art keywords
electrical signal
signal
equalizer
analog
photoelectric
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Ceased
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PCT/CN2021/107037
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English (en)
French (fr)
Inventor
苏长征
赵磊
周轶刚
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to PCT/CN2021/107037 priority Critical patent/WO2023000128A1/zh
Priority to EP21950395.0A priority patent/EP4358438A4/en
Priority to CN202180099575.1A priority patent/CN117501642A/zh
Publication of WO2023000128A1 publication Critical patent/WO2023000128A1/zh
Priority to US18/416,436 priority patent/US20240154699A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25—Arrangements specific to fibre transmission
    • H04B10/2507—Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/27—Arrangements for networking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H04B10/69—Electrical arrangements in the receiver
    • H04B10/697—Arrangements for reducing noise and distortion
    • H04B10/6971—Arrangements for reducing noise and distortion using equalisation
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/02—Optical fibres with cladding with or without a coating
    • G02B6/02295—Microstructured optical fibre
    • G02B6/02314—Plurality of longitudinal structures extending along optical fibre axis, e.g. holes
    • G02B6/02319—Plurality of longitudinal structures extending along optical fibre axis, e.g. holes characterised by core or core-cladding interface features
    • G02B6/02323—Core having lower refractive index than cladding, e.g. photonic band gap guiding
    • G02B6/02328—Hollow or gas filled core
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2210/00—Indexing scheme relating to optical transmission systems
    • H04B2210/006—Devices for generating or processing an RF signal by optical means

Definitions

  • the embodiments of the present application relate to the technical field of communication, and in particular, to a photoelectric module, a communication method, and related equipment.
  • a high performance computing (high performance computing, HPC) cluster usually includes multi-level switches and multiple servers.
  • a high-speed cable or optical fiber can be used for data transmission between the switch and the server, between the switch and the switch, so as to reduce the transmission delay.
  • the data rate of a single port is getting higher and higher, and the mainstream of the server interface has evolved from 4 ⁇ 10Gbps to 4 ⁇ 25Gbps.
  • the higher the port rate means the greater the bandwidth, and the greater the loss coefficient of electrical signals transmitted in media such as printed circuit boards (printed circuit boards, PCBs) and cables. Therefore, in order to solve the signal attenuation and signal distortion caused by electrical or optical signal transmission and optical/electrical conversion, most of the market uses a clock and data recovery (CDR) inside the switch or server. unit to regenerate, retime and reamplify the received electrical signal.
  • CDR clock and data recovery
  • the additional CDR unit can solve the problem caused by the large loss coefficient of the electrical signal during transmission to a certain extent, in the process of regenerating, retiming and re-amplifying the received electrical signal using CDR, it is necessary
  • the received high-speed electrical signals are serially converted into low-speed electrical signals and processed with digital logic, and then parallel-serially converted into high-speed electrical signals.
  • digital logic processing and serial-to-parallel conversion will bring large delays, which will increase the calculation waiting time and reduce the overall computing power of the HPC cluster. Therefore, how to reduce the transmission delay under the premise of ensuring the signal transmission quality is an urgent problem to be solved.
  • Embodiments of the present application provide a photoelectric module, a communication method, and related equipment, which can reduce transmission delay while ensuring signal transmission quality.
  • the embodiment of the present application provides a photoelectric module, including an analog equalizer and a photoelectric conversion unit, the analog equalizer is connected to the photoelectric conversion unit; the analog equalizer is used to correct the first electrical signal performing equalization processing on the first analog signal to obtain a second electrical signal, and sending the second electrical signal to the photoelectric conversion unit, or receiving a third electrical signal from the photoelectric conversion unit, to the third electrical signal
  • the electrical signal is subjected to a second analog signal equalization process to obtain a fourth electrical signal;
  • the photoelectric conversion unit is configured to receive the second electrical signal from the analog equalizer and convert the second electrical signal into a first optical signal signal, or for converting the second optical signal into the third electrical signal and sending the third electrical signal to the analog equalizer.
  • an analog equalizer may be used in the photoelectric module to replace the original CDR.
  • the input electrical signal can be directly input in the analog domain through the analog equalizer (for example, the first electrical signal can be an electrical signal input to the analog equalizer when the device sends a signal to other devices; another example is the third electrical signal, which can be When sending signals to this device for other devices, the photoelectric conversion unit of this device receives and outputs the electrical signal to the analog equalizer) to perform analog signal equalization processing, compensate for the loss of the electrical signal during transmission, and efficiently and quickly An electrical signal with better quality and less intersymbol interference (for example, the second electrical signal or the fourth electrical signal) is output.
  • the photoelectric conversion unit includes: a first photoelectric converter, configured to receive the second electrical signal from the analog equalizer and convert the second electrical signal into the first An optical signal;
  • the analog equalizer includes: a sending equalizer, configured to perform the first analog signal equalization process on the first electrical signal to obtain the second electrical signal, and send the second electrical signal to the first photoelectric converter.
  • the analog equalizer in this application can equalize the received electrical signal in the analog domain, compensate for the loss of the electrical signal in the early transmission process, and efficiently and quickly output better quality
  • the electrical signal with less intersymbol interference (for example, the second electrical signal) is sent to the photoelectric conversion unit in the photoelectric module.
  • the photoelectric conversion unit can convert the received electrical signal into a corresponding optical signal, so that the signal can be quickly transmitted to other devices through the optical fiber to ensure that other devices can quickly receive better quality signals.
  • the analog equalizer can also adjust the The electrical signal is pre-equalized to compensate for losses during subsequent transmissions and further ensure the quality of signals received by other devices, which is not specifically limited in this embodiment of the present application.
  • the transmit equalizer includes at least one of a first continuous time linear equalizer CTLE, a first low frequency equalizer LFEQ, and a first level mismatch compensation circuit.
  • the analog equalizer can compensate the high-frequency part and/or low-frequency part of the received signal (such as the first electrical signal) to be sent by the device in the sending direction, and reduce the noise of the high-frequency part and/or low-frequency part. Inter-symbol interference, so that compared with the received electrical signal, a high-quality electrical signal with less inter-symbol interference can be obtained and output.
  • the transmit equalizer includes: the first CTLE, the first LFEQ, and the first level mismatch compensation circuit connected in series.
  • the analog equalizer can be used to compensate all frequency bands of the signal, so as to obtain higher-quality electrical signals, and more reliably ensure the quality of signals received by other devices.
  • the photoelectric conversion unit includes: a second photoelectric converter, configured to convert the second optical signal into the third electrical signal and send the first electrical signal to the analog equalizer.
  • the analog equalizer includes: a receiving equalizer, configured to receive the third electrical signal from the second photoelectric converter, and perform the second analog signal equalization process on the third electrical signal to The fourth electrical signal is obtained.
  • the photoelectric conversion unit in the device can receive the optical signals output by other devices and convert them into corresponding electrical signals (for example, the third electrical signal signal) to the analog equalizer.
  • the analog equalizer in this application can equalize the received electrical signal in the analog domain, Compensate the loss of the electrical signal in the early transmission process, and efficiently and quickly output an electrical signal with better quality and less intersymbol interference (such as the fourth electrical signal), so as to ensure that the equipment is finally received and used for corresponding calculations or Analyze the quality of the electrical signal, etc.
  • the receiving equalizer includes at least one of a second CTLE, a second LFEQ, and a second level mismatch compensation circuit.
  • the analog equalizer can compensate the high-frequency part and/or low-frequency part of the received signal (such as the third electrical signal) to be sent by other devices in the receiving direction, and reduce its high-frequency part and/or low-frequency part. Inter-symbol interference, so that compared with the received electrical signal, a high-quality electrical signal with less inter-symbol interference can be obtained and output.
  • the receiving equalizer includes: the second CTLE, the second LFEQ, and the second level mismatch compensation circuit connected in series.
  • all frequency bands of the signal can be compensated by an analog equalizer to obtain a higher-quality electrical signal, and more reliably ensure the quality of the signal received by the device.
  • the embodiment of the present application provides a communication device, including a digital signal interface unit, and the optoelectronic module according to any one of the first aspect; the digital signal interface unit is used to receive the first digital electrical signal, converting the first digital electrical signal into the first electrical signal, and sending the first electrical signal to the analog equalizer, or for receiving the first electrical signal from the analog equalizer Four electrical signals, converting the fourth electrical signal into a second digital electrical signal, and sending the second digital electrical signal to the processing device.
  • the digital signal interface unit in the device can send a processing device (such as a central processing unit (CPU) or a graphics processing unit (graphics processing unit) unit, GPU) etc.) to convert the digital electrical signal output into an analog electrical signal (such as the first electrical signal), and input the analog electrical signal to the analog equalizer, so that the subsequent analog equalizer can be directly used in the analog domain.
  • a processing device such as a central processing unit (CPU) or a graphics processing unit (graphics processing unit) unit, GPU) etc.
  • the analog electrical signal is equalized, so as to efficiently and quickly obtain and output a high-quality analog electrical signal (such as a second electrical signal) with less intersymbol interference, so as to ensure the quality of the signal received by other devices and greatly reduce the Signal transmission delay.
  • the analog equalizer directly performs equalization processing on the analog electrical signal in the analog domain based on the received analog electrical signal (such as the third electrical signal) sent by the photoelectric conversion unit , efficiently and quickly obtain and output a high-quality analog electrical signal (such as the fourth electrical signal) with less intersymbol interference to the digital signal interface unit, and then the digital signal interface unit can convert the analog electrical signal into a corresponding high-quality
  • the digital electrical signal is output to the above-mentioned processing equipment, so as to ensure that the subsequent processing equipment can perform reliable and accurate calculation or analysis based on the received digital electrical signal, and greatly reduce the waiting time for the equipment to receive the signal.
  • the device further includes: a high-speed passive component, configured to connect the digital signal interface unit and the analog equalizer.
  • the digital signal interface unit of the present application and the equalizer can also be connected through high-speed passive components, thereby providing a low-loss high-speed transmission channel for the signal, further reducing inter-symbol interference and ensuring signal quality. At the same time, the transmission delay is reduced.
  • the high-speed passive components include a first high-speed connector, a second high-speed connector, and a high-speed cable, and the first high-speed connector and the second high-speed connector pass through the high-speed Cable connection; the first high-speed connector is connected to the digital signal interface unit, and the second high-speed connector is connected to the analog equalizer.
  • the distance between the digital signal interface unit and the analog equalizer (or photoelectric module) in the device is relatively long, and the transmitted signal rate is relatively high, the signal will be transmitted during this period. Severe transmission loss and large transmission delay.
  • the high-speed passive components in the embodiment of the present application may include two high-speed connectors, and a section of high-speed cable for connecting the two high-speed connectors. Connect with the digital signal interface unit and the analog equalizer respectively through two high-speed connectors, and then provide a low-loss high-speed transmission channel through the high-speed cable in the middle to ensure that the signal is transmitted over a long distance in the device and reduce the signal transmission loss. and transmission delay, thereby ensuring that the subsequent analog equalizer can quickly and effectively compensate for the transmission loss of the electrical signal.
  • the high-speed passive component includes a first high-speed connector, and the first high-speed connector is connected between the digital signal interface unit and the analog equalizer; the device further Including: a first hollow-core optical fiber and a hollow-core optical fiber connector; the first hollow-core optical fiber is connected to the photoelectric conversion unit for sending the first optical signal or receiving the second optical signal; the empty A core fiber connector, configured to send the first optical signal to a second hollow-core optical fiber or receive the second optical signal from the second hollow-core optical fiber.
  • the device and other devices may be connected through a hollow-core optical fiber (for example, a second hollow-core optical fiber), thereby reducing the transmission delay of signals between devices.
  • the high-speed passive components in this device may only include a high-speed connector used to connect between the digital signal interface unit and the analog equalizer, so that the analog equalizer (or photoelectric module) is located at a distance from the digital signal interface.
  • the unit is closer to the position, and correspondingly, the photoelectric conversion unit in the photoelectric module is located farther away from the hollow-core optical fiber between the devices, that is, the optical signal output by the photoelectric conversion unit needs to go through a longer distance before it can be transmitted to the device.
  • the optical signal output by the hollow-core optical fiber between devices, or the hollow-core optical fiber between devices needs to go through a long distance before being transmitted to the photoelectric conversion unit.
  • the device may also include a section of hollow-core optical fiber (for example, the first hollow-core optical fiber) connected to the photoelectric conversion unit, and a connector for connecting the hollow-core optical fiber in the device and the hollow-core optical fiber between devices.
  • the connector can carry out high-speed optical signal transmission via hollow-core optical fiber inside and outside the device.
  • the embodiment of the present application provides an active optical cable, including at least two photoelectric modules according to any one of the first aspect, and a hollow-core optical fiber; the at least two photoelectric modules pass through the hollow core fiber optic connection.
  • an embodiment of the present application provides a communication system, which is characterized in that it includes a plurality of communication devices, and the plurality of communication devices are connected through the active optical cable described in the third aspect.
  • the multiple communication devices include at least one device according to any one of the foregoing second aspects.
  • the embodiment of the present application provides a communication method using a photoelectric module, including: performing a first analog signal equalization process on a first electrical signal through an analog equalizer in the photoelectric module to obtain a second electrical signal , and send the second electrical signal to the photoelectric conversion unit, or receive a third electrical signal from the photoelectric conversion unit through the analog equalizer, and perform a second analog signal equalization process on the third electrical signal to obtain A fourth electrical signal; receiving the second electrical signal from the analog equalizer and converting the second electrical signal into a first optical signal through the photoelectric conversion unit in the photoelectric module, or, passing through the The photoelectric conversion unit converts the second optical signal into the third electrical signal and sends the third electrical signal to the analog equalizer.
  • the embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the photoelectric module based on the above-mentioned fifth aspect is implemented. communication method flow.
  • the processor may be one or more processors.
  • an embodiment of the present application provides a computer program, the computer program includes instructions, and when the computer program is executed by a computer, the computer can execute the photoelectric module-based communication method described in the fifth aspect above.
  • the embodiment of the present application provides a chip, the chip includes a processor and a communication interface, the processor is used to call and run instructions from the communication interface, and when the processor executes the instructions, the chip executes The flow of the photoelectric module-based communication method described in the fifth aspect above.
  • the embodiment of the present application provides a chip system, which can include the photoelectric module described in any one of the above first aspects, and is used to realize the communication based on the photoelectric module described in the above fifth aspect The functions involved in the method flow.
  • the chip system further includes a memory, and the memory is used for storing necessary program instructions and data of the adjustment method.
  • the chip system may include a chip, or may include a chip and other discrete devices.
  • FIG. 1 is a schematic diagram of an architecture of a high-performance computing cluster provided by an embodiment of the present application.
  • Fig. 2 is a schematic diagram of an HPC data transmission link provided by an embodiment of the present application.
  • Fig. 3 is a schematic diagram of a group of hollow-core optical fibers provided by an embodiment of the present application.
  • Fig. 4 is a schematic diagram of a data link between nodes.
  • Fig. 5 is a schematic diagram of another inter-node data link.
  • FIG. 6 is a schematic diagram of a system architecture provided by an embodiment of the present application.
  • Fig. 7 is a schematic structural diagram of a photoelectric module provided by an embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another communication system provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of an internal connection structure of a group of communication devices provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of an analog equalizer provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a CTLE circuit structure and gain curve adjustment provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a circuit structure of an LFEQ provided by an embodiment of the present application.
  • FIG. 14 is a set of single-bit response curves provided by the embodiment of the present application.
  • Fig. 15 is a schematic diagram of a time domain compensation range provided by an embodiment of the present application.
  • Fig. 16 is a schematic structural diagram of a photoelectric module provided by an embodiment of the present application.
  • Fig. 17 is a schematic structural diagram of a group of photoelectric modules provided by an embodiment of the present application.
  • Fig. 18 is a schematic structural diagram of an active optical cable provided by an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of another communication system provided by an embodiment of the present application.
  • Fig. 20 is a schematic structural diagram of a group of active optical cables provided by an embodiment of the present application.
  • Fig. 21 is a schematic structural diagram of another active optical cable provided by an embodiment of the present application.
  • Fig. 22 is a schematic flowchart of a communication method using a photoelectric module provided by an embodiment of the present application.
  • High performance computing refers to computing that usually uses multiple processors (as part of a single server) or multiple servers in a cluster (operating as a single computing resource) and its switching network system and environment.
  • FIG. 1 is a schematic diagram of an architecture of a high-performance computing cluster provided by an embodiment of the present application.
  • a large-scale high-performance computing cluster can include multi-level switches (such as level-1 switches, level-2 switches, and level-3 switches, each level can include multiple switches) and multiple server arrays, each server Arrays can each include multiple servers.
  • FIG. 1 is only a schematic example, and there may be different configurations according to the size of the HPC cluster. For example, a small-scale HPC cluster may use only one level of switches, a medium-scale HPC cluster may use two levels of switches, and a large-scale HPC cluster may use three or more levels of switches for data exchange.
  • HPC systems In order to reduce the delay of data (or signal) transmission between different servers or switches, reduce computing waiting time, and improve overall computing power, HPC systems usually use high-performance network interconnection, such as low-latency "unlimited bandwidth” technology (infiniband, IB) switches.
  • IB low-latency "unlimited bandwidth” technology
  • IB infiniband
  • Infiniband is a computer network communication standard for high-performance computing, which has extremely high throughput and extremely low delay, and is used for data interconnection between computers.
  • Infiniband is also used as a direct or switched interconnect between servers and storage systems, and as an interconnect between storage systems.
  • High-speed cables or optical fibers can be used for data transmission between the infiniband switch, the server, and the infiniband switch, so as to further reduce the transmission delay.
  • FIG. 2 is a schematic diagram of an HPC data transmission link provided by an embodiment of the present application.
  • node A and node E may be servers, and node B, node C and node D may be switches.
  • node B, node C and node D may be switches.
  • a photoelectric module is required for optical transmission.
  • electrical conversion for example, photoelectric modules in nodes A, B, C, and D in Figure 2).
  • the distance between switch nodes is usually more than 5 meters, so most of them can only use optical fiber for signal transmission, and the signal rate and the distance between nodes can be considered comprehensively between the switch and the server, and optical fiber can also be used.
  • Use cables for signal transmission As shown in FIG. 2 , the link between node A and node B is shown as using optical fibers for signal transmission, and the link between node D and node E is shown as using cables for signal transmission, which is not specifically limited in this embodiment of the present application.
  • a signal is sent from node A, passes through node B, node C, and node D, and then reaches node E.
  • the main time delay involved may include: the signal processing time delay of the network processing interface unit of node A, the time delay of A node Link transmission delay between node-B node, signal processing delay of node B data exchange unit, link transmission delay between node B-node C, signal processing delay of node C data exchange unit, node C- The link transmission delay between D nodes, the signal processing delay of the D node data exchange unit, the link transmission delay between D nodes and E nodes, and the signal processing delay of the E node network processing interface unit.
  • Insertion loss that is, insertion loss, is generally the loss of energy or gain when certain devices or branch circuits (filters, impedance matchers, adapters, etc.) are added to a certain circuit.
  • the insertion loss when the optical signal is transmitted between two nodes can generally be divided into three parts.
  • the insertion loss when the optical signal is transmitted between node A and node B The loss can include: the insertion loss at the connection between the photoelectric module of node A and the optical fiber (generally, the photoelectric module can be connected to the optical fiber through an adapter and other devices), the insertion loss (or transmission loss) inside the optical fiber during the optical fiber transmission process, the optical fiber Insertion loss at the connection to the photoelectric module at node B.
  • Hollow-core fiber which is different from the principle of total reflection of conventional fiber-optic waveguide light, the core of the hollow-core fiber is air, so it brings benefits such as low delay, ultra-low nonlinearity, and low dispersion.
  • the hollow core fiber initially had a problem of very large insertion loss.
  • a variety of hollow core fibers based on the principle of anti-resonance have been proposed on the market, that is, anti-resonance based on the resonant cavity in the cladding.
  • the mechanism traps the light beam in the air hole as the core. Please refer to FIG. 3 .
  • FIG. 3 FIG.
  • FIG. 3 is a schematic diagram of a group of hollow-core optical fibers provided by an embodiment of the present application.
  • the hollow core fiber based on the anti-resonance principle mainly uses the coherent reflection of light back and forth between the tubular glass films in the fiber to confine the light in the
  • the air core is transported near and along the axis. Its processing and manufacturing process is extremely complicated, and it is often necessary to precisely control the diameter (um level) and film thickness (nm level) of the tubular glass in the hollow core fiber during the processing and manufacturing process.
  • the length of a single anti-resonant hollow-core fiber can only reach several kilometers on the market, and the typical value of its actual insertion loss coefficient is 1-10dB/km, which is still far greater than the existing solid-core single-mode fiber by about 0.2dB/km.
  • the insertion loss coefficient of km As mentioned above, the existing anti-resonant hollow-core optical fiber still has the disadvantages of short length and large insertion loss, making it difficult to be used on a large scale.
  • CDR Clock and data recovery
  • the mainstream of the server interface has evolved from 4 ⁇ 10Gbps to 4 ⁇ 25Gbps.
  • the higher the port rate the larger the bandwidth, and the larger the loss coefficient of electrical signals transmitted in media such as printed circuit boards (PCB), cables, etc.
  • the signal to be sent by the node undergoes a series of processing to compensate for the inevitable loss of the signal during transmission, to ensure the quality of the signal, and to ensure that the node can perform reliable and accurate calculations based on the received signal.
  • node A and node B may be two devices in the HPC cluster that perform data transmission through optical fibers. Both the node A and the node B may include a digital signal interface unit and a photoelectric module. Optionally, the digital signal interface unit and the photoelectric module may be deployed on a PCB. As shown in FIG. 4 , both the photoelectric modules of node A and node B may include an electro-optical conversion unit, a photoelectric conversion unit and a CDR.
  • the device types of node A and node B shown in FIG. 4 may include but not limited to: servers, switches, storage resource pools, and memory resource pools.
  • the digital signal interface units in Node A and Node B may include but not limited to: a network processing interface unit, a data exchange unit, a storage interface unit, a memory interface unit, and the like.
  • the digital signal interface unit can be used to realize the logical processing of digital signals, and output or receive one or more electrical signals.
  • the electrical signals can be high-speed electrical signals for transmission between nodes data.
  • the electro-optical conversion unit in node A can be connected to the photoelectric conversion unit in node B through an optical fiber, so that the electrical signal output by the digital signal interface unit of node A It can be converted into a corresponding optical signal by the electro-optical conversion unit of node A, and transmitted to the photoelectric conversion unit of node B via optical fiber, and then the optical signal is converted into a corresponding electrical signal by the photoelectric conversion unit of node B, and input to The digital signal interface unit of node B, finally, the digital signal interface unit of node B can perform a series of logical calculations on the input electrical signal and so on.
  • the electro-optical conversion unit in node B can be connected to the photoelectric conversion unit in node A through an optical fiber, and the same is true for sending signals from node B to node A, which will not be repeated here.
  • the electrical signal output by the network processing interface unit of node A is due to the loss during transmission on a medium such as a PCB (or Distortion, such as changes in the amplitude, frequency and phase of the signal, loss generally refers to the reduction of the signal amplitude), so that there is a certain degree of attenuation and distortion, so it is difficult to directly drive the electro-optical conversion unit of the A node; correspondingly, The electrical signal output by the photoelectric conversion unit of node A will also suffer loss during transmission, resulting in signal attenuation and distortion.
  • a medium such as a PCB (or Distortion, such as changes in the amplitude, frequency and phase of the signal, loss generally refers to the reduction of the signal amplitude)
  • the network processing interface unit of node A cannot accurately receive the electrical signal output from the photoelectric conversion unit of node A.
  • the optical signal will also have a certain degree of attenuation and distortion when it is transmitted in the optical fiber, and the photoelectric conversion unit and the electro-optical conversion unit will also have a certain degree of attenuation in the process of converting optical signals and electrical signals. and distortion, etc.
  • a CDR can be added to the respective photoelectric modules of node A and node B to The received electrical signal is regenerated, retimed and re-amplified, and then input to the electro-optical conversion unit or digital signal interface unit.
  • the added CDR can ensure that the electrical signal finally input to the digital signal interface unit of node B is consistent with the electrical signal originally output by the digital signal interface unit of node A.
  • the link transmission delay between node A and node B includes:
  • Delay in the sending direction of node A CDR that is, the time delay required for signal regeneration, timing and re-amplification after the node A CDR receives the signal sent by the digital signal interface unit
  • the delay in the receiving direction of the node B CDR That is, after the Node B CDR receives the signal sent by the photoelectric conversion unit, it performs signal regeneration, timing and time delay required for re-amplification.
  • the sum of the above two delays is generally between tens of nanoseconds (ns) and hundreds of nanoseconds, and a typical value is 100 ns.
  • optical fiber transmission time delay between the output of the photoelectric module of node A and the photoelectric module of node B.
  • the transmission delay coefficient of the optical fiber is about 4.8ns/m, and a length of 50 meters
  • the fiber transmission delay is 240 ns in total.
  • the routing delay of the electrical signals of node A and node B on their respective PCBs for example, the routing delay between the output electrical signal of the digital signal interface unit of node A and the CDR of node A, and the output electrical signal of node A CDR
  • the PCB transmission delay coefficient is about 5-10ns/m.
  • the length of traces at each node is usually less than 0.5 meters, that is, node A 1.
  • the total time delay of electrical signal traces at node B is usually less than 10 ns.
  • the trace delay of electrical signals on the PCB is a very small value.
  • PAM4 pulse amplitude modulation
  • NRZ non-return-to-zero
  • FIG. 5 is a schematic diagram of another data link between nodes.
  • FIG. 5 is a schematic diagram of another data link between nodes.
  • a relay CDR is added to both nodes C and D in Figure 5, and the two ends of the relay CDR are respectively connected to the digital
  • the signal interface unit is connected to the CDR in the photoelectric module.
  • the following takes data transmission from node C to node D as an example.
  • the link transmission delay between node C and node D includes:
  • CDR transmission direction delay in the photoelectric module of node C and CDR reception direction delay in the photoelectric module of node D.
  • the sum of the above two delays is generally between tens of nanoseconds and hundreds of nanoseconds, and a typical value is 100 ns.
  • the optical fiber transmission delay between the output of the photoelectric module at node C and the photoelectric module at node D is still taken as an example of the SMF or MMF with the currently used optical fiber as a solid core.
  • the transmission delay coefficient of the optical fiber is 4.8ns/m. Taking a 50-meter optical fiber as an example, the fiber transmission delay is 240 ns in total.
  • Fig. 4 and Fig. 5 are only exemplary illustrations of a possible inter-node data link.
  • each node may include more or more There are fewer or even different components, etc., which are not specifically limited in this embodiment of the present application.
  • the additional CDR can solve the problems caused by the loss of electrical and optical signals due to transmission and photoelectric conversion to a certain extent, but in the process of regenerating, retiming and re-amplifying the received electrical signal using CDR, it needs
  • the received high-speed electrical signals are serially converted into low-speed electrical signals and processed with digital logic, and then parallel-serially converted into high-speed electrical signals.
  • operations such as digital logic processing and serial-to-parallel conversion are complex and time-consuming, which will bring a large delay.
  • the link between node C and node D in the above figure is taken as an example.
  • the fiber transmission delay is 240 ns
  • the CDR delay in the photoelectric module is 100 ns
  • the relay CDR delay on the motherboard is 100 ns
  • the PCB wiring delay is about 10 ns.
  • the delay is 450ns, among which, the sum of the CDR delay in the photoelectric module and the relay CDR delay (200ns) is even equivalent to the transmission delay of a 50-meter optical fiber, accounting for almost half of the total delay, which greatly increases
  • the transmission delay of the entire link increases the computing waiting time, thereby reducing the overall computing capability of the HPC cluster.
  • the actual technical problems to be solved in this application include the following aspects: through reasonable device selection and layout, on the premise of ensuring the quality of signal transmission, reduce the signal between communication devices Transmission delay to reduce computing waiting time and improve overall computing power.
  • the aforementioned communication between devices includes, but is not limited to: between any two devices such as servers, switches, storage resource pools, and memory resource pools.
  • the aforementioned communication between devices includes, but is not limited to: between any two devices such as servers, switches, storage resource pools, and memory resource pools.
  • any two devices such as servers, switches, storage resource pools, and memory resource pools.
  • FIG. 6 is a schematic diagram of a system architecture provided by an embodiment of the present application.
  • the technical solutions of the embodiments of the present application may be specifically implemented in the system architecture shown in FIG. 6 or a similar system architecture.
  • the system architecture may include an HPC cluster, and the HPC cluster may include multiple nodes, specifically, multiple primary switches (such as switches 100a, 100b, and 100c, etc.), multiple secondary switches (such as switches 200a, 200b, and 200c, etc.), multiple three-level switches (such as switches 300a, 300b, and 300c, etc.), server array 400, memory resource pool 500, storage resource pool 600, and so on.
  • the server array 400 may include multiple servers, the memory resource pool 500 may include multiple memories, the storage resource pool 600 may include multiple memories, etc., which will not be described in detail here.
  • any devices in the plurality of switches, the server array 400 , the memory resource pool 500 and the storage resource pool 600 may be connected by optical fibers for signal transmission.
  • the plurality of switches, the server array 400, the memory resource pool 500 and the storage resource pool 600 may all include a digital signal interface unit and a photoelectric module.
  • the photoelectric modules in the multiple switches, the server array 400 , the memory resource pool 500 and the storage resource pool 600 can all use analog equalizers to replace the original CDR.
  • each of the above-mentioned nodes can directly compare the received high-speed electrical signal in the analog domain through the analog equalizer in each node (it can be the electrical signal output from the digital signal interface unit of the current node to the analog equalizer, or it can be the electrical signal output by the digital signal interface unit of the current node.
  • the photoelectric conversion unit converts the optical signals output by other nodes and then outputs the electrical signals to the analog equalizer) to perform analog signal equalization processing to compensate for the loss generated during transmission, so as to efficiently and quickly output electrical signals with better quality , while ensuring the quality of signal transmission, avoiding the above-mentioned complex and time-consuming processing processes such as digital logic processing and serial-to-parallel conversion, greatly reducing the signal transmission delay, thereby reducing the calculation waiting time of each node, and improving the The computing power of the HPC cluster as a whole.
  • the baud rate of the electrical signal is generally greater than 25G baud rate (Baud/s). For example, if the NRZ encoding format is used, the rate of each electrical signal is greater than 25Gbps. If the PAM4 encoding format is used, The rate of each electrical signal is greater than 50Gbps. If the PAM8 encoding format is used, the rate of each high-speed electrical signal is greater than 75Gbps, etc.
  • the rates of other encoding formats are analogous, and will not be described in detail here.
  • the analog equalizer in the embodiment of the present application can be suitable for processing high-speed electrical signals with a very high rate (for example, high-speed electrical signals with a baud rate greater than 25G baud rate, or even greater than 50G baud rate).
  • the above-mentioned optical fiber may be a solid-core optical fiber or a hollow-core optical fiber.
  • a hollow-core fiber can be used instead of a solid-core fiber such as SMF or MMF.
  • the refractive index of the core material used in the solid-core fiber is about 1.45
  • the air in the hollow-core fiber is used as the transmission medium, and its refractive index is about 1, so the transmission speed of the optical signal in the hollow-core fiber is higher than that in the real world.
  • the transmission speed in the core fiber is about 300000km/s and 207000km/s respectively.
  • the time delay required for optical signal transmission through 1-meter hollow-core fiber and 1-meter solid-core fiber is 3.3 ns and 4.8 ns respectively.
  • the core fiber is generally only 69% of the solid core fiber.
  • the optical fiber transmission distance is relatively short, ranging from 5 to 2,000 meters, with a typical value of about 10 to 100 meters.
  • the embodiment of the present application may preferably use a hollow-core optical fiber to further reduce transmission delay.
  • the system architecture shown in Figure 6 is only a schematic example, and it is a preferred system architecture or application scenario in the embodiment of the present application.
  • the photoelectric module provided in the embodiment of the application can be applied to In other scenarios other than the HPC cluster, this embodiment of the present application does not specifically limit this.
  • the foregoing nodes may also be mobile terminals such as mobile phones, notebook computers, and desktop computers, etc., which are not specifically limited in this embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a photoelectric module provided by an embodiment of the present application.
  • the photoelectric module 102 can be applied in a communication device 10, and the communication device 10 can be a photoelectric communication device, such as a switch (such as a switch 100a, 100b, 100c, 200a , 200b, 200c and 300a, etc.), server, memory resource pool, storage resource pool and other nodes.
  • a switch such as a switch 100a, 100b, 100c, 200a , 200b, 200c and 300a, etc.
  • server memory resource pool, storage resource pool and other nodes.
  • the photoelectric module 102 may include an analog equalizer 103 and a photoelectric conversion unit 104 connected to the analog equalizer 103 .
  • the photoelectric module 102 shown in FIG. 7 will be described in detail by taking the sending signal and receiving signal of the communication device 10 as examples respectively.
  • the analog equalizer 103 is configured to receive the first electrical signal, perform first analog signal equalization processing on the first electrical signal to obtain a second electrical signal, and send the second electrical signal to the photoelectric conversion unit 104 .
  • the first electrical signal and the second electrical signal may be analog electrical signals, and the inter-symbol interference of the second electrical signal obtained after equalization processing may be smaller than the inter-symbol interference of the first electrical signal.
  • the photoelectric conversion unit 104 is configured to receive the second electrical signal, and convert the second electrical signal into a corresponding first optical signal.
  • the first optical signal may be subsequently transmitted to other devices via an optical fiber (for example, a hollow-core optical fiber) connected between the communication device 10 and other devices.
  • transmission loss or distortion, such as changes in the amplitude, frequency and phase of the signal, etc.
  • the loss is generally can refer to the reduction of the signal amplitude
  • the first electrical signal received by the analog equalizer 103 will have a certain degree of signal attenuation and Distortion (for example, at least one of the amplitude, frequency and phase of the first electrical signal will change, typically the amplitude will decrease, etc.), resulting in serious intersymbol interference of the first electrical signal received by the analog equalizer 103 .
  • severe inter-symbol interference will significantly increase the bit error rate. If it is not dealt with, the signal received by other devices may be completely wrong or completely invalid, seriously affecting other devices and The computing power of the communication system as a whole.
  • the analog equalizer 103 added in the photoelectric module 102 can directly perform efficient and fast analog signal equalization processing on the received first electrical signal in the analog domain, and compensate for the transmission generated in the previous transmission process. Loss, without digital logic processing and serial-to-parallel conversion, the second electrical signal with better signal quality and less interference between signal symbols can be output.
  • the second electrical signal can be as close as possible to the original first electrical signal, even the same as the original first electrical signal, and can also have smaller intersymbol interference than the original first electrical signal, etc., this The embodiment of the application does not specifically limit this.
  • the photoelectric module provided by the embodiment of the present application can greatly shorten the time it takes to compensate for signal transmission loss before sending, thus greatly reducing the signal quality while ensuring the signal quality.
  • the transmission delay from the communication device 10 to other devices reduces the computing waiting time of other devices.
  • the photoelectric conversion unit 104 is configured to receive the second optical signal, convert the second optical signal into a corresponding third electrical signal, and send the third electrical signal to the analog equalizer 103 .
  • the second optical signal may be a signal sent by other devices to the photoelectric conversion unit 104 through an optical fiber.
  • the analog equalizer 103 is configured to receive the third electrical signal, and perform second analog signal equalization processing on the third electrical signal to obtain a fourth electrical signal.
  • the third electrical signal and the fourth electrical signal may be analog electrical signals, and the inter-symbol interference of the fourth electrical signal obtained after equalization processing may be smaller than the inter-symbol interference of the third electrical signal.
  • the communication device 10 may subsequently perform a series of calculations or analyzes based on the fourth electrical signal.
  • the above-mentioned first electrical signal, second electrical signal, third electrical signal and fourth electrical signal may be high-speed electrical signals with a baud rate greater than 25G baud rate, or even greater than 50G baud rate, etc.
  • the embodiment of the application does not specifically limit this.
  • the analog equalizer 103 added in the photoelectric module 102 can directly perform efficient and fast analog signal equalization processing on the received third electrical signal in the analog domain, so that the output signal quality is better and the signal code is better.
  • the fourth electrical signal with less interference between them.
  • the fourth electrical signal may be as close as possible to the third electrical signal originally output by the photoelectric conversion unit 104, or as close as possible to the electrical signal originally output by other devices, or even be the same as the electrical signal originally output by other devices, Intersymbol interference may also be smaller than that of electrical signals originally output by other devices, etc., which are not specifically limited in this embodiment of the present application.
  • the photoelectric module provided by the embodiment of the present application can greatly shorten the time it takes for the device (that is, the communication device 10) to perform signal transmission loss compensation before calculation, thereby ensuring signal quality.
  • the transmission delay of signals from other devices to the communication device 10 is greatly reduced, the computing waiting time of the communication device 10 is reduced, and the overall computing capability is improved.
  • the communication device 10 can also be used only for sending signals or only for receiving signals, that is, the analog equalizer 103 and the photoelectric conversion unit 104 in the photoelectric module 102 are only used to realize the or, the analog equalizer 103 and the photoelectric conversion unit 104 are only used to implement the functions described in the above embodiment (2), which are not specifically limited in this embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • the communication system may include a communication device 10 (for example, a first communication device) and a communication device 20 (for example, a second communication device), wherein the communication device 10 and the communication device 20 may pass through the Optical fiber 30 and optical fiber 40 are connected.
  • the communication device 10 and the communication device 20 may be any one of nodes such as a switch, a server, a memory resource pool, and a storage resource pool in the system architecture shown in FIG. 6 above.
  • the communication device 10 may include a digital signal interface unit 101 and a photoelectric module 102, the photoelectric module 102 may include an analog equalizer 103 and a photoelectric conversion unit 104, wherein the analog equalizer 103 may include a transmission equalizer 103a 1.
  • a receiving equalizer 103b; the photoelectric conversion unit 104 may include a first photoelectric converter 105 and a second photoelectric converter 106 .
  • the sending equalizer 103a can be connected with the digital signal interface unit 101 and the first photoelectric converter 105 respectively;
  • the receiving equalizer 103b can be connected with the digital signal interface unit 101 and the second photoelectric converter 106 respectively.
  • the analog equalizer 103 involved in the embodiment of the present application may only include the sending equalizer 103a.
  • the photoelectric conversion unit involved in the embodiment of the present application 104 may only include the first photoelectric converter 105; or, the analog equalizer 103 may only include the receiving equalizer 103b, correspondingly, the photoelectric conversion unit 104 may only include the second photoelectric converter 106, etc., this application The embodiment does not specifically limit this.
  • the communication device 20 may include a digital signal interface unit 201 and a photoelectric module 202, and the photoelectric module 202 may include an analog equalizer 203 and a photoelectric conversion unit 204, wherein the analog equalizer 203 may include a sending The equalizer 203 a , the receiving equalizer 203 b ; the photoelectric conversion unit 204 may include a first photoelectric converter 205 and a second photoelectric converter 206 .
  • the sending equalizer 203a can be connected with the digital signal interface unit 201 and the first photoelectric converter 205 respectively;
  • the receiving equalizer 203b can be connected with the digital signal interface unit 201 and the second photoelectric converter 206 respectively.
  • the digital signal interface unit 101 and the digital signal interface unit 201 may be any one of a network processing interface unit, a data exchange unit, a storage interface unit, and a memory interface unit, which are not specifically limited in this embodiment of the present application.
  • the first photoelectric converter 105 is connected to the second photoelectric converter 206 through an optical fiber 30, thereby providing a transmission channel for the communication device 10 to send signals to the communication device 20; the second photoelectric converter 106 and the second photoelectric converter A photoelectric converter 205 is connected through an optical fiber 40 to provide a transmission channel for the communication device 20 to send signals to the communication device 10 .
  • the optical fiber 30 and the optical fiber 40 may be solid-core optical fibers or hollow-core optical fibers, preferably hollow-core optical fibers, so as to provide a low-latency transmission channel for the transmission of optical signals.
  • the optical fiber 30 is a hollow-core optical fiber, it may also mean that the optical fiber 30 includes at least one section of hollow-core optical fiber. The example does not specifically limit this.
  • a photoelectric module provided by the embodiment of the present application will be further described in detail in combination with the communication device 10 and the communication device 20 shown in FIG. 8 , taking the communication device 10 sending a signal to the communication device 20 as an example.
  • the communication device 10 sending a signal to the communication device 20 as an example, the possible distortion of the signal may roughly include but not limited to the following points:
  • Digital signal interface unit 101 receiving a first digital electrical signal from a processing device (not shown in FIG. 8 ), converting the first digital electrical signal into a corresponding analog electrical signal (such as a first electrical signal), and sending the first digital electrical signal An electrical signal is sent to the equalizer 103a.
  • the processing device may be connected to the digital signal interface unit 101, and may be, for example, a CPU, a GPU, or a memory.
  • Sending equalizer 103a receiving the first electrical signal, and performing analog signal equalization processing on the first electrical signal in the analog domain, compensating the distortion of the first electrical signal in the early transmission process (for example, including the above-mentioned distortion (1)), reducing The inter-symbol interference is used to obtain a second electrical signal, and then the second electrical signal is sent to the first photoelectric converter 105 .
  • the transmitting equalizer 103a also Pre-equalization processing may be performed on the first electrical signal.
  • the low-frequency part of the first electrical signal can be appropriately attenuated, so that compared with the case where no pre-equalization processing is performed, the high-frequency part of the electrical signal received by the receiving equalizer 203b in the subsequent communication device 20 and The amplitude difference of the low frequency part becomes smaller, which reduces the intersymbol interference of the electrical signal received by the receiving equalizer 203b, etc., which are not specifically limited in this embodiment of the present application.
  • the first photoelectric converter 105 receives the second electrical signal, converts the second electrical signal into a corresponding first optical signal and inputs it to the optical fiber 30 .
  • Optical fiber 30 receiving the first optical signal, and then sending the first optical signal to the second optical-to-electrical converter 206 in the communication device 20 .
  • the second photoelectric converter 206 receives the first optical signal, converts the first optical signal into a corresponding electrical signal (for example, a third electrical signal), and sends the third electrical signal to the receiving equalizer 203b.
  • a corresponding electrical signal for example, a third electrical signal
  • the first optical signal received by the communication device 20 is equivalent to the reception of the first optical signal by the communication device 10 described in the embodiment of FIG. 7
  • the received second optical signals are optical signals received by the device and sent by other devices. Therefore, the third electrical signal here may only be used to represent the electrical signal converted from the optical signal received by the device, and does not specifically refer to the electrical signal converted from the second optical signal.
  • Receiving equalizer 203b receiving the third electrical signal, and performing analog signal equalization processing on the third electrical signal in the analog domain, compensating the distortion of the third electrical signal in the early transmission process (for example, including the above-mentioned distortion (2), (3 ), (4), (5), (6), (7), (8)), reduce the intersymbol interference, thereby obtaining a fourth electrical signal, and then send the fourth electrical signal to the digital signal interface unit 201.
  • the receiving The equalizer 203b may also perform pre-equalization processing on the third electrical signal, etc., which is not specifically limited in this embodiment of the present application.
  • Digital signal interface unit 201 receive the fourth electrical signal, convert the fourth electrical signal into a corresponding digital electrical signal (such as a second digital electrical signal), and send the second digital electrical signal to the processing device in the communication device 20 , so that the processing device in the communication device 20 can perform a series of calculations or analyzes based on the second digital electrical signal.
  • a corresponding digital electrical signal such as a second digital electrical signal
  • the equalization process by the analog equalizer can make the fourth electrical signal or the second digital electrical signal finally received by the communication device 20 as close as possible to the first electrical signal or the first digital electrical signal initially output by the communication device 10 , even the same as the first electrical signal or the first digital electrical signal, ensuring effective and reliable signal transmission.
  • the process of the communication device 20 sending a signal to the communication device 10 can refer to the above-mentioned process of the communication device 10 sending a signal to the communication device 20, which is not repeated here. to repeat.
  • the embodiment of this application uses an analog equalizer to replace the original CDR.
  • the analog equalizer does not have a large time delay caused by digital logic processing and serial-to-parallel conversion.
  • the wiring delay in the analog equalizer, and the analog equalizer is an integrated circuit chip, the length of the internal wiring is extremely short, and the delay caused by it is negligible, almost zero, thus saving about 100ns delay.
  • the hollow-core optical fiber is used to replace the original solid-core optical fiber (SMF, MMF, etc.) as the transmission channel between communication devices (or nodes).
  • SMF solid-core optical fiber
  • MMF solid-core optical fiber
  • the embodiment of the present application saves about 75 ns of time delay.
  • the specific time delay and ratio can refer to the content in Table 1 below, and will not be described in detail here.
  • FIG. 9 is a schematic structural diagram of another communication system provided by an embodiment of the present application.
  • the communication device 10 and the communication device 20 may further include a high-speed passive component 107 and a high-speed passive component 207 respectively.
  • the high-speed passive component 107 is used to connect the digital signal interface unit 101 and the analog equalizer 103 (for example, including the sending equalizer 103a and the receiving equalizer 103b); correspondingly, the high-speed passive component 207 is used to connect the digital signal interface unit 201 and an analog equalizer 203 (for example, including a transmit equalizer 203a and a receive equalizer 203b).
  • the two ends of the high-speed passive component 107 are respectively connected with the analog equalizer 103 in the digital signal interface unit 101 and the photoelectric module 102, thereby providing A high-speed electrical signal transmission channel with low delay, low insertion loss, and low distortion has almost zero transmission delay.
  • the analog equalizer 103 can reduce the transmission process of high-speed electrical signals (such as the first electrical signal or the fourth electrical signal) between the digital signal interface unit 101 and the analog equalizer 103.
  • the transmission delay as well as transmission loss and distortion in . Therefore, compared with the communication system shown in Figure 8, the communication system shown in Figure 9 can further reduce the transmission delay of the signal and ensure the transmission quality of the signal by using the high-speed passive components in the communication device, thereby further improving the communication The overall computing power of the system.
  • FIG. 10 is a schematic diagram of an internal connection structure of a group of communication devices provided by an embodiment of the present application.
  • the communication device 10 shown in FIG. 9 is taken as an example. It can be understood that the connection structure shown in FIG.
  • the communication device 10 may specifically include a digital signal interface unit 101 , a high-speed connector 01 , a high-speed connector 02 , a high-speed cable 03 and a photoelectric module 102 .
  • the digital signal interface unit 101 may be included in a packaged integrated circuit chip, as shown in (a) of FIG. 10 , and the integrated circuit chip may be deployed on a PCB. As shown in (a) of FIG. 10 , the digital signal interface unit 101 (or the integrated circuit chip) can be welded on the PCB through several welding points.
  • the high-speed connector 01 may be deployed on the PCB closer to the digital signal interface unit 101 (or closer to the integrated circuit chip). Wherein, the high-speed connector 01 and the high-speed connector 02 are connected by a high-speed cable 03, and the high-speed passive component 107 shown in FIG. Plug-in 01, high-speed connector 02 and high-speed cable 03. Optionally, the distance between the high-speed connector 01 and the high-speed connector 02 may be relatively long.
  • the high-speed connector 02 and the photoelectric module 103 can be connected on a panel as shown in FIG. 10 .
  • the photoelectric module 102 is connected to the optical fiber 30 for inputting/outputting optical signals and performing corresponding optical/electrical conversion, etc., which will not be repeated here.
  • the communication device 10 may specifically include a digital signal interface unit 101 , a high-speed connector 01 , a high-speed connector 02 , a high-speed cable 03 and a photoelectric module 102 .
  • the digital signal interface unit 101 may be included in an integrated circuit chip (the integrated circuit chip may be unpackaged), as shown in (b) in FIG. 10 , the integrated circuit chip may be deployed on a substrate ( substrate), the substrate can be deployed on the PCB. As shown in (b) of FIG. 10 , the substrate can be welded on the substrate through several welding points.
  • the high-speed connector 01 may be deployed on the substrate at a position closer to the digital signal interface unit 101 (or in other words, closer to the integrated circuit chip).
  • high-speed connector 02 and photoelectric module 102 To sum up, still taking the communication device 10 sending a signal to the communication device 20 as an example, as shown in (b) in FIG. , high-speed connector 02 and photoelectric module 102.
  • the photoelectric module 102 After analog signal equalization processing and electro-optical conversion, corresponding optical signals are output to the optical fiber 30 .
  • the optical fiber 30 outputs an optical signal to the photoelectric module 202 of the communication device 20, and after photoelectric conversion and analog signal equalization processing in the photoelectric module 202, the corresponding high-speed electrical signal is output and passed through the communication device 20 in turn.
  • the communication device 10 may specifically include a digital signal interface unit 101 , a high-speed connector 01 , a photoelectric module 102 , an optical fiber 04 and a hollow-core optical fiber connector 05 .
  • the digital signal interface unit 101 may be included in a packaged integrated circuit chip, as shown in (c) of FIG. 10 , and the integrated circuit chip may be deployed on a PCB. As shown in (c) of FIG. 10 , the digital signal interface unit 101 (or the integrated circuit chip) can be soldered on the PCB based on several soldering points.
  • the high-speed connector 01 can be deployed on the PCB at a position closer to the digital signal interface unit 101 (or closer to the integrated circuit chip) for connecting the digital signal interface unit 101 and the photoelectric module 102, specifically It is used to connect the digital signal interface unit 101 and the analog equalizer 103 in the photoelectric module 102 .
  • the high-speed passive component 107 or the high-speed passive component 207 shown in FIG. 9 may only include the high-speed connector 01 .
  • the photoelectric module 102 itself may include a section of optical fiber 04, and the optical fiber 04 may be connected to the photoelectric conversion unit 104 in the photoelectric module 102 (that is, the first photoelectric converter 105 and the second photoelectric converter 105).
  • Two photoelectric converters (106) are connected for inputting/outputting optical signals, for example, may be used for sending the above-mentioned first optical signal, or for receiving the above-mentioned second optical signal.
  • the optical fiber 04 may be a hollow-core optical fiber or a solid-core optical fiber converted to a hollow-core optical fiber
  • the optical fiber 30 may be a hollow-core optical fiber (or include at least a section of hollow-core optical fiber).
  • the optical fiber 04 may be connected to the optical fiber 30 through a hollow-core optical fiber connector 05 on the panel of the communication device 10 .
  • the hollow-core optical fiber connector 05 can be used to input/output optical signals between the optical fiber 04 and the optical fiber 30, for example, can be used to receive the above-mentioned first optical signal from the optical fiber 04, and send the first optical signal to the optical fiber 30 , or receive the second optical signal from the optical fiber 30, and send the second optical signal to the optical fiber 04.
  • a low-loss, high-speed transmission channel can be provided for the transmission of optical signals inside and outside the device, thereby further reducing transmission loss, ensuring signal quality, and reducing transmission delay.
  • the output optical signal passes through the optical fiber 04 , the hollow-core optical fiber connector 05 and the optical fiber 30 in sequence. Subsequently, through the transmission of the optical fiber 30 , the optical fiber 30 outputs an optical signal to the photoelectric module 202 in the communication device 20 .
  • the communication device 20 may also include a hollow-core optical fiber connector and a section of hollow-core optical fiber or a solid-core optical fiber-to-hollow-core optical fiber, so that the optical signal output by the optical fiber 30 can be sequentially passed through the hollow-core optical fiber
  • the optical fiber or the solid-core fiber-to-hollow-core fiber is input to the photoelectric module 202 .
  • the corresponding high-speed electrical signal is output and passed through the high-speed connector 01 and PCB in the communication device 20 in turn, and finally input to the digital signal interface unit 201 .
  • the communication device 10 may specifically include a digital signal interface unit 101 , a high-speed connector 01 , a photoelectric module 102 , an optical fiber 04 and a hollow-core optical fiber connector 05 .
  • the digital signal interface unit 101 may be included in an integrated circuit chip (the integrated circuit chip may be unpackaged), as shown in (d) in FIG. 10 , the integrated circuit chip may be deployed on a substrate ( substrate), the substrate can be deployed on the PCB. As shown in (d) of FIG. 10 , the substrate may be welded on the substrate based on several welding points.
  • the high-speed connector 01 may be deployed on the substrate at a position closer to the digital signal interface unit 101 (or in other words, closer to the integrated circuit chip).
  • the communication device 20 may also include a hollow-core optical fiber connector and a section of hollow-core optical fiber or a solid-core optical fiber converted to a hollow-core optical fiber.
  • the optical fiber or a section of solid-core fiber-to-hollow-core fiber is input to the photoelectric module 202 . Then, after photoelectric conversion and analog signal equalization processing in the photoelectric module 202 , the corresponding high-speed electrical signal is output and passed through the high-speed connector 01 and the substrate in the communication device 20 in turn, and finally input to the digital signal interface unit 201 .
  • the embodiment of the present application uses a high-speed passive component combination to replace the original relay CDR for connecting the digital signal interface unit and the photoelectric module, thereby saving about 100 ns of delay;
  • the embodiment of the present application uses an analog equalizer to replace the original CDR, avoiding complex digital logic processing and serial-to-parallel conversion, thereby saving about 100 ns of delay;
  • the hollow-core optical fiber is used to replace the original solid-core optical fiber (SMF, MMF, etc.) as the transmission channel between communication devices (or nodes).
  • SMF solid-core optical fiber
  • MMF solid-core optical fiber
  • the embodiment of the present application saves about 75 ns of time delay.
  • the specific time delay and ratio can refer to the content in Table 2 below, and will not be described in detail here.
  • the digital signal interface unit 101 and the photoelectric conversion between the units 104) to eliminate them by adding an equalizer to compensate for uneven changes caused by devices and channels, so as to achieve the purpose of reducing signal distortion.
  • the analog equalizer used in the embodiment of the present application mainly corrects the amplitude, frequency characteristic, phase frequency characteristic and the like of the transmission signal.
  • analysis and design may be performed on the amplitude equalizer and the phase equalizer to obtain the analog equalizer in the embodiment of the present application.
  • the design index of the analog equalizer may mainly involve equalization bandwidth, equalization amount, etc., which are not specifically limited in this embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of an analog equalizer provided by an embodiment of the present application.
  • the analog equalizer 103 may include a sending equalizer 103 a and a receiving equalizer 103 b.
  • the transmitting equalizer 103a may include an input amplifier circuit 1030, a continuous time linear analog equalizer (CTLE) 1031, a low frequency analog equalizer (low frequency equalizer, LFEQ) 1032, A level mismatch compensation circuit 1033 and an output amplifier circuit 1034 .
  • CTLE continuous time linear analog equalizer
  • LFEQ low frequency equalizer
  • the receiving equalizer 103b may include an input amplifier circuit 1035 , a continuous-time linear analog equalizer 1036 , a low-frequency analog equalizer 1037 , a level mismatch compensation circuit 1038 , and an output amplifier circuit 1039 sequentially connected in series.
  • the structure of the analog equalizer shown in FIG. 11 may also be applied to the analog equalizer 203 in the communication device 20, or to an analog equalizer of any other communication device.
  • the input terminal of the input amplification circuit 1030 can be connected with the digital signal interface unit 101 (or connected with the high-speed passive component 107), for receiving the high-speed electrical signal (such as the first electrical signal) output by the digital signal interface unit 101, for The first electrical signal is amplified to obtain a first electrical signal-A, and the first electrical signal-A is sent to the continuous-time linear analog equalizer 1031 .
  • a continuous-time linear analog equalizer 1031 configured to receive the first electrical signal-A, and compensate the signal transmission loss of the high-frequency part (or high-frequency component) of the first electrical signal-A, so as to reduce the first electrical signal-A - Intersymbol interference of the high frequency part of A to obtain a first electrical signal -B, and then send the first electrical signal -B to the low frequency analog equalizer 1032 .
  • FIG. 12 is a schematic diagram of a CTLE circuit structure and gain curve adjustment provided by an embodiment of the present application.
  • the peak value can be adjusted by adjusting Rs1 (series equivalent circuit) and Cs1 (series equivalent capacitance) in the CTLE circuit, and frequency compensation can be targeted to achieve a relatively flat gain curve (that is, adjust the voltage amplitude-frequency characteristics of the signal).
  • Rs1 series equivalent circuit
  • Cs1 series equivalent capacitance
  • the low-frequency analog equalizer 1032 is configured to receive the first electrical signal-B, and compensate the signal transmission loss of the low-frequency part (or low-frequency component) of the first electrical signal-B, so as to reduce the low-frequency part of the first electrical signal-B Intersymbol interference, obtain the first electrical signal -C, and then send the first electrical signal -C to the level mismatch compensation circuit 1033.
  • FIG. 13 is a schematic diagram of a circuit structure of an LFEQ provided by an embodiment of the present application.
  • LFEQ can adjust the slope of the low-frequency loss part of the channel based on negative feedback technology, and can also adjust the signal gain to achieve balanced control of the low-frequency part of the signal, thereby reducing intersymbol interference in the low-frequency part of the signal.
  • the circuit structure shown in FIG. 13 is only a schematic example.
  • the LFEQ circuit may include more or fewer components than those shown in FIG. 13 , which is not specifically limited in this embodiment of the present application. .
  • the level mismatch compensation circuit 1033 may include a decision feedback equalizer (decision feedback equalizer, DFE), configured to receive the first electrical signal-C, and compensate the signal transmission of the high-frequency part of the first electrical signal-C through the DFE Loss, to reduce the intersymbol interference of the high-frequency part of the first electrical signal-C, obtain the first electrical signal-D, and then send the first electrical signal-D to the output amplifier circuit 1034.
  • DFE decision feedback equalizer
  • FIG. 14 is a set of single-bit response curves provided by the embodiment of the present application.
  • the intersymbol interference in the high frequency part of the signal can be made to tend to zero, which greatly reduces the The intersymbol interference in the high frequency part of the signal ensures the signal quality.
  • the output end of the output amplification circuit 1034 can be connected with the first photoelectric converter 105, for receiving and amplifying the first electrical signal-D to obtain a second electrical signal, and then sending the second electrical signal to the first photoelectric converter 105 .
  • the output amplifying circuit 1034 may also include a feed forward equalizer (feed forward equalizer, FFE).
  • FFE feed forward equalizer
  • the FFE can also be used to pre-equalize the first electrical signal-D, properly attenuate the low-frequency part of the first electrical signal-D, and then Obtain a second electrical signal.
  • the pre-equalization process it can ensure that the amplitude difference between the high-frequency part and the low-frequency part of the electrical signal received by other devices becomes smaller, that is, it can ensure that the intersymbol interference of the electrical signal received by other devices is small.
  • FIG. 15 is a schematic diagram of a time domain compensation range provided by an embodiment of the present application.
  • the continuous-time linear analog equalizer 1031 is mainly used to compensate the loss of the high-frequency part of the electrical signal, thereby reducing the intersymbol interference of the high-frequency part;
  • the low-frequency analog equalizer 1032 is mainly used to compensate the loss of the low-frequency part of the electrical signal.
  • the DEF in the level mismatch compensation circuit 1033 is mainly used to compensate the loss of the high frequency part of the electrical signal, thereby reducing the intersymbol interference of its high frequency part; in the output amplifier circuit 1034 The FEF is mainly used to attenuate the low-frequency part of the signal before outputting the signal to other devices, so as to reduce the intersymbol interference of the signal received by the equalizer in other communication devices.
  • the loss compensation in the full frequency band is jointly realized, thereby reducing the inter-symbol interference of the signal (or reducing the inter-symbol interference in the channel), and improving the signal-to-noise ratio (signal-to-noise ratio) of channel transmission.
  • noise ratio, SNR effectively guarantee the quality of signal transmission.
  • the high-speed electrical signal (such as the third electrical signal) output by the second photoelectric converter 106 is first received and amplified by the input amplifier circuit 1035 in the receiving equalizer 103b, and the amplified third electrical signal is then sequentially passed through continuous time linear analog equalization. 1036, low-frequency analog equalizer 1037, and level mismatch compensation circuit 1038, to respectively compensate the high-frequency part and low-frequency part of the third electrical signal to reduce the intersymbol interference, and finally amplify it through the output amplifier circuit 1039
  • a high-speed electrical signal (such as a fourth electrical signal) with better quality and less intersymbol interference is output.
  • the transmitting equalizer 103a and the receiving equalizer 103b may only include some devices or circuits in FIG. 11, for example, the transmitting equalizer 103a may only include an input amplifier circuit 1030, a continuous time linear analog equalizer 1031, a level mismatch compensation circuit 1033, and an output amplifier circuit 1034; or, the sending equalizer 103a may only include an input amplifier circuit 1030, a continuous time linear analog equalizer 1031 and an output amplifier circuit 1034; or, the transmit equalizer 103a may only include a continuous-time linear analog equalizer 1031, a low-frequency analog equalizer 1032, and a level mismatch compensation circuit 1033.
  • the receiving equalizer 103b may only include the input amplifier circuit 1035, the level mismatch compensation circuit 1038 and the output amplifier circuit 1039; or, the receiving equalizer 103b may only include the continuous time linear analog equalizer 1036, the low frequency analog equalizer 1037 , the level mismatch compensation circuit 1038, etc., which are not specifically limited in this embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of a photoelectric module provided by an embodiment of the present application.
  • the optoelectronic module 102 in the communication device 10 shown in FIG. 8 or FIG. 9 is taken as an example. It can be understood that the structure shown in FIG. In the module, details will not be repeated here.
  • the photoelectric module 102 may include a transmitting channel (transmitter, TX)) and a receiving channel (receiver, RX). Specifically, as shown by the dotted line box in FIG.
  • TX may include a transmitting equalizer 103 a and a first photoelectric converter 105
  • RX may include a receiving equalizer 103 b and a second photoelectric converter 106 .
  • Both TX and RX mentioned in the following embodiments may adopt the above structure.
  • one end of the photoelectric module 102 is used for inputting/outputting electrical signals (such as inputting a first electrical signal and outputting a fourth electrical signal), and the other end is used for inputting/outputting an optical signal (eg inputting a fourth electrical signal). second optical signal and outputting the first optical signal), which will not be repeated here.
  • FIG. 17 is a schematic structural diagram of a group of photoelectric modules provided by an embodiment of the present application.
  • a photoelectric module provided by the embodiment of the present application may be the photoelectric module (a), photoelectric module (b), photoelectric module (c) and photoelectric module (d) in Fig. 17 , photoelectric module (e), photoelectric module (f), etc., or a combination of the above various structures, or any other possible structure, which is not specifically limited in this embodiment of the present application.
  • the optical fiber shown in FIG. 17 (for example, including optical fiber 1, optical fiber 2, optical fiber 3, and optical fiber 4, etc.) may be a hollow core optical fiber.
  • the photoelectric module (a) may be a transmitting module and may only include one TX; the photoelectric module (b) may be a receiving module and may only include one RX.
  • the photoelectric module (a) and the photoelectric module (b) can be respectively arranged in two communication devices and connected by optical fiber to realize the transmission of signals from the photoelectric module (a) to the photoelectric module (b).
  • the photoelectric module (c) can be a single-channel transceiver module, which can include one TX and one RX.
  • TX is connected with the optical fiber 1, and is used to convert the electrical signal of the device into an optical signal and output it to other devices through the optical fiber 1.
  • the RX is connected to the optical fiber 2, and is used to receive the optical signal sent by other devices through the optical fiber 2 and convert it into an electrical signal for input to the device.
  • the photoelectric module (d) may be a multi-channel parallel module, and may include multiple TXs (such as TX1 and TX2 ) and multiple RXs (such as RX1 and RX2 ).
  • TX1 is connected to optical fiber 1
  • TX2 is connected to optical fiber 2, which can be used to convert two electrical signals into corresponding two optical signals in parallel and output them to other devices through optical fiber 1 and optical fiber 2.
  • RX1 is connected with optical fiber 3
  • RX2 is connected with optical fiber 4, which are used to receive two optical signals sent by other devices in parallel through optical fiber 3 and optical fiber 4 and convert them into corresponding two electrical signals for input to the device.
  • the photoelectric module (e) can be a single-fiber bidirectional photoelectric module, and can include a TX, an RX and a wavelength division multiplexing component (wave division multiplexing, WDM).
  • TX and RX are respectively connected to WDM
  • WDM is connected to an optical fiber, so that both the optical signal sent by TX and the optical signal received by RX can be transmitted through the same optical fiber through WDM.
  • the photoelectric module (f) can be a wavelength division multiplexing photoelectric module, which can include multiple TXs (such as TX1 and TX2), multiple RXs (such as RX1 and RX2) and multiple WDMs (such as WDM1 and WDM2) .
  • TX1 and TX2 are respectively connected to WDM1, and WDM1 is then connected to optical fiber 1, so that the two optical signals output in parallel by TX1 and TX2 can be combined by WDM1 and then input to optical fiber 1, and then output to other devices through optical fiber 1.
  • RX1 and RX2 are respectively connected to WDM2, and WDM2 is connected to optical fiber 2.
  • WDM2 is used to receive the combined signal from optical fiber 2 and perform demultiplexing. After demultiplexing, two optical signals are obtained and input to RX1 and RX2 respectively.
  • FIG. 18 is a schematic structural diagram of an active optical cable provided by an embodiment of the present application. As shown in FIG.
  • the active optical cable 50 may include two photoelectric modules (such as a photoelectric module 102 and a photoelectric module 202 ) and a hollow-core optical fiber 107 connecting the two photoelectric modules, wherein the photoelectric module 102 and the photoelectric module 202 can be connected to the air
  • the two ends of the core fiber 107 are directly coupled (for example, the photoelectric module 102 can be directly coupled with one end of the hollow-core fiber 107, and the photoelectric module 202 can be directly coupled with the other end of the hollow-core fiber 107), so as to reduce or even avoid the connection between the photoelectric module and the optical fiber. insertion loss.
  • the photoelectric module 102 may include an analog equalizer 103 (such as including a transmitting equalizer 103a and a receiving equalizer 103b), a photoelectric conversion unit 104 (such as including a first photoelectric converter 105 and a second photoelectric converter 106), and here Let me repeat.
  • the photoelectric module 202 may include an analog equalizer 203 (such as including a sending equalizer 203a and a receiving equalizer 203b), a photoelectric conversion unit 204 (such as including a first photoelectric converter 205 and a second photoelectric converter 206), and here Let me repeat.
  • the hollow-core optical fiber 107 may include a single or multiple hollow-core optical fibers, and each hollow-core optical fiber may include at least one section of hollow-core optical fiber, etc., or, in some possible embodiments, considering actual requirements and cost etc. can also use a solid core optical fiber, which is not specifically limited in this embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of another communication system provided by an embodiment of the present application.
  • the active optical cable 50 as a whole can be used to connect two communication devices, for example, the photoelectric module 102 in the active optical cable 50 can be connected with the high-speed passive component 107 in the communication device 10, the active optical cable
  • the photoelectric module 202 in 50 can be connected with the high-speed passive component 107 in the communication device 20 , so as to provide a high-speed and low-latency transmission channel for the communication device 10 and the communication device 20 .
  • the relevant descriptions in the above embodiments corresponding to FIGS. 8-11 and details are not repeated here.
  • a high-speed and low-latency active optical cable (active optical cable, AOC) provided by the embodiment of the present application can connect two photoelectric modules through one or more hollow-core optical fibers.
  • the package is coupled into an integral part. In actual use, only the two ends of the active optical cable need to be inserted into the two devices, which can achieve an effect similar to that of a network cable.
  • the operation is complicated and brings additional optical link loss (that is, the insertion loss between the two ends of the fiber and the photoelectric module in the two devices)
  • the two photoelectric modules in the active optical cable provided by the embodiment of the present application can be directly coupled with the optical fiber, and the active optical cable can be used as an external whole to connect two devices, which has the advantages of being easy to use and low insertion loss .
  • the communication device 10 and the communication device 20 only include the transmission of electrical signals, and no longer involve the conversion of optical signals.
  • the signal transmission efficiency in the communication device can be greatly improved. And reduce the manufacturing cost of the communication equipment.
  • the connection selection of optical cable or cable can also be used, so that the communication equipment can be applied to all aspects of scenarios such as electrical communication or optoelectronic communication.
  • FIG. 20 is a schematic structural diagram of a group of active optical cables provided by an embodiment of the present application.
  • a photoelectric module provided by the embodiment of the present application can be an active optical cable (a), an active optical cable (b), an active optical cable (c), an active optical
  • the various structures shown in the optical cable (d) may be a combination of the above-mentioned various structures, or may be any other possible structures, which are not specifically limited in this embodiment of the present application.
  • the active optical cable (a) may be a single-channel active optical cable, and may include a photoelectric module A and a photoelectric module B, wherein the photoelectric module A and the photoelectric module B both include single-channel TX and RX.
  • the photoelectric module A includes TX-A and RX-A
  • the photoelectric module B includes TX-B and RX-B.
  • the active optical cable (a) may also include a hollow-core fiber 1 and a hollow-core fiber 2 for connecting TX-A and RX-B, and RX-A and TX-B, respectively.
  • the optical signal output by TX-A in photoelectric module A can be input to RX-B in photoelectric module B through hollow-core fiber 1;
  • the optical signal output by -B can be input to the RX-A in the photoelectric module A through the hollow-core optical fiber 2, and so on, which will not be described in detail here.
  • the active optical cable (b) can be a single-fiber bidirectional active optical cable, and can include a photoelectric module A and a photoelectric module B, wherein, the photoelectric module A and the photoelectric module B not only include single-channel TX and RX, but also Each includes a wavelength division multiplexing component.
  • the photoelectric module A includes TX-A, RX-A and WDM-A
  • the photoelectric module B includes TX-B, RX-B and WDM-B.
  • the active optical cable (b) also includes a hollow-core optical fiber 1 for connecting the photoelectric module A and the photoelectric module B, specifically for connecting WDM-A and WDM-B.
  • the wavelength of the optical signal output by TX-A of photoelectric module A is generally different from the wavelength of the optical signal output by TX-B of photoelectric module B, which can be ⁇ a and ⁇ b respectively.
  • the ⁇ a optical signal output by the TX-A of the photoelectric module A is multiplexed by the WDM-A and then input to the hollow-core fiber 1, and then the WDM-B of the photoelectric module B receives
  • the ⁇ a optical signal from the hollow-core fiber 1 is demultiplexed and input to the RX-B of the photoelectric module B.
  • the ⁇ b optical signal output by the TX-B of the photoelectric module B is combined by the WDM-B and then input to the hollow-core fiber 1.
  • the WDM-A of the photoelectric module A receives the ⁇ b optical signal from the hollow-core fiber 1 and demultiplexes it.
  • the active optical cable (c) may be a multi-channel active optical cable, and may include a photoelectric module A and a photoelectric module B, wherein the photoelectric module A and the photoelectric module B may both include four channels of TX and RX.
  • the photoelectric module A includes TX-A1, TX-A2, TX-A3, TX-A4, and RX-A1, RX-A2, RX-A3 , RX-A4
  • photoelectric module B includes TX-B1, TX-B2, TX-B3, TX-B4, and RX-B1, RX-B2, RX-B3, RX-B4.
  • the active optical cable (c) also includes eight-core hollow-core optical fibers, specifically including hollow-core optical fiber 1, hollow-core optical fiber 2, hollow-core optical fiber 3, hollow-core optical fiber 4, hollow-core optical fiber 5, hollow-core optical fiber Optical fiber 6, hollow-core optical fiber 7 and hollow-core optical fiber 8 are respectively used to connect TX-A1 and RX-B1, TX-A2 and RX-B2, TX-A3 and RX-B3, TX-A4 and RX-B4, RX -A1 and TX-B1, RX-A2 and TX-B2, RX-A3 and TX-B3, RX-A4 and TX-B4.
  • hollow-core optical fibers specifically including hollow-core optical fiber 1, hollow-core optical fiber 2, hollow-core optical fiber 3, hollow-core optical fiber 4, hollow-core optical fiber 5, hollow-core optical fiber Optical fiber 6, hollow-core optical fiber 7 and hollow-core optical fiber 8 are respectively used to connect TX-A1 and RX-B1, TX-A2 and R
  • the optical signals output by TX-A1, TX-A2, TX-A3, and TX-A4 of the photoelectric module A are respectively input into hollow-core optical fiber 1, hollow-core optical fiber 2, Hollow-core fiber 3, hollow-core fiber 4, and then, RX-B1, RX-B2, RX-B3, RX-B4 of photoelectric module B receive signals from hollow-core fiber 1, hollow-core fiber 2, hollow-core fiber 3, hollow-core fiber The optical signal of the core fiber 4.
  • the optical signals output by TX-B1, TX-B2, TX-B3, and TX-B4 of the photoelectric module B are respectively input into the hollow-core optical fiber 5, the hollow-core optical fiber 6, and the hollow-core optical fiber 7. Hollow-core optical fiber 8.
  • RX-A1, RX-A2, RX-A3, and RX-A4 of photoelectric module A respectively receive signals from hollow-core optical fiber 5, hollow-core optical fiber 6, hollow-core optical fiber 7, and hollow-core optical fiber 8. light signal.
  • a 4-channel multi-channel active cable is taken as an example.
  • the number of channels of the multi-channel active cable can be greater than or Any integer equal to 2, which is not specifically limited in the embodiment of the present application, for example, it can be 2, 4, 6, 8, 16 channels, etc., correspondingly, the number of cores (or the number of roots) of the required hollow-core optical fiber Can be 4, 8, 12, 16, 32.
  • the active optical cable (d) can be a wavelength division multiplexed active optical cable and can include a photoelectric module A and a photoelectric module B, wherein the photoelectric module A and the photoelectric module B can both include four channels of TX and RX, And TX direction WDM and RX direction WDM.
  • the photoelectric module A includes TX-A1, TX-A2, TX-A3, TX-A4 and WDM-TXA, and RX-A1, RX-A2 , RX-A3, RX-A4 and WDM-RXA;
  • photoelectric module B includes TX-B1, TX-B2, TX-B3, TX-B4 and WDM-TXB, and RX-B1, RX-B2, RX-B3, RX-B4 and WDM-RXB.
  • the active optical cable (d) also includes a hollow-core fiber 1 for connecting WDM-TXA in photoelectric module A and WDM-RXB in photoelectric module B, and a hollow-core fiber 2 for connecting WDM-RXA in photoelectric module A and WDM-TXB in photoelectric module B.
  • the wavelengths of the optical signals output by the four channels TX in the photoelectric module A are generally different, which can be ⁇ a1, ⁇ a2, ⁇ a3, and ⁇ a4 respectively; correspondingly, the wavelengths of the four channels TX in the photoelectric module B
  • the wavelengths of the optical signals output by the channel TX will also be different, which may be ⁇ b1, ⁇ b2, ⁇ b3, and ⁇ b4 respectively.
  • the ⁇ a1 optical signal, ⁇ a2 optical signal, ⁇ a3 optical signal and ⁇ a4 optical signal respectively output by TX-A1, TX-A2, TX-A3 and TX-A4 of photoelectric module A
  • the optical signal is combined by WDM-TXA and then input to hollow-core fiber 1.
  • WDM-RXB of photoelectric module B receives the combined optical signal from hollow-core fiber 1, and the ⁇ a1 optical signal, ⁇ a2 optical signal, and ⁇ a3 optical signal are obtained after demultiplexing.
  • signal and ⁇ a4 optical signal are input to RX-B1, RX-B2, RX-B3 and RX-B4 of photoelectric module B respectively.
  • the ⁇ b1 optical signal, ⁇ b2 optical signal, ⁇ b3 optical signal, and ⁇ b4 optical signal output by TX-B1, TX-B2, TX-B3, and TX-B4 of the photoelectric module B are combined by WDM-TXB and input to the hollow core Optical fiber 2, then WDM-RXA of photoelectric module A receives the multiplexed optical signal from hollow core fiber 2, and the ⁇ b1 optical signal, ⁇ b2 optical signal, ⁇ b3 optical signal and ⁇ b4 optical signal obtained after demultiplexing are respectively input to the optical module A RX-A1, RX-A2, RX-A3 and RX-A4, etc., will not be described in detail here.
  • a 4-channel wavelength division multiplexing active cable is taken as an example.
  • the number of channels of the wavelength division multiplexing active optical cable It can be any integer greater than or equal to 2, such as 4, 6, 8 or 16 channels, etc.
  • the transmission in hollow-core fiber 1 and hollow-core fiber 2 can be 4, 6, 8 or 16-wave multiplexing optical signals, etc., which are not specifically limited in this embodiment of the present application.
  • the sending channels of photoelectric module A can include TX-A1, TX-A2, TX-A3, TX-A4, TX-A5, TX-A6, TX-A7, and TX-A8, and the receiving channels of photoelectric module A can include RX-A1, RX-A2, RX-A3, RX-A4, RX-A5, RX-A6, RX-A7, RX-A8, and photoelectric module B are the same, and will not be repeated here.
  • FIG. 21 is a schematic structural diagram of another active optical cable provided by an embodiment of the present application.
  • the active optical cable (e) may be a multi-channel parallel wavelength division multiplexing active optical cable, which is a more complicated active optical cable structure.
  • the active optical cable (e) includes a photoelectric module A and a photoelectric module B, wherein both the photoelectric module A and the photoelectric module B include two sets of four-channel wavelength division multiplexing as in the active optical cable (d).
  • both photoelectric module A and photoelectric module B include 8-channel TX and 8-channel RX, and corresponding 4 wavelength division multiplexing components (such as WDM-TX1-A, WDM-TX2-A, WDM-RX1-A and WDM-RX2-A, and WDM-TX1-B, WDM-TX2-B, WDM-RX1-B and WDM-RX2-B).
  • the active optical cable (e) can also include a hollow-core fiber 1, a hollow-core fiber 2, a hollow-core fiber 3, and a hollow-core fiber 4, which are respectively used to connect WDM-TX1-A and WDM-RX1-B , WDM-TX2-A and WDM-RX2-B, WDM-RX1-A and WDM-TX1-B, WDM-RX2-A and WDM-TX2-B.
  • a hollow-core fiber 1 a hollow-core fiber 2
  • a hollow-core fiber 3 a hollow-core fiber 4 which are respectively used to connect WDM-TX1-A and WDM-RX1-B , WDM-TX2-A and WDM-RX2-B, WDM-RX1-A and WDM-TX1-B, WDM-RX2-A and WDM-TX2-B.
  • the active optical cable (e) in Figure 21 it is an example of a parallel wavelength division multiplexing active optical cable with 2 groups of 4 channels.
  • the multi-channel parallel wavelength division multiplexing has
  • the source optical cable can also be 4 sets of 4-channel parallel wavelength division multiplexing active optical cables, or 4 sets of 6-channel parallel wavelength division multiplexing active optical cables, or 6 sets of 2-channel parallel wavelength division multiplexing active optical cables , etc., and each group may be interconnected through two hollow-core optical fibers, which is not specifically limited in this embodiment of the present application.
  • both photoelectric module A and photoelectric module B can contain: 16 channels TX and 16 channels RX, 4 transmission directions WDM, 4 reception directions WDM , where wavelength division multiplexing/demultiplexing is performed every 4 channels, and are interconnected through 8-core hollow-core optical fibers, etc., which will not be described in detail here.
  • the embodiment of the present application provides a photoelectric module.
  • an analog equalizer in the photoelectric module to replace the original CDR method, the received electrical signal can be directly equalized in the analog domain, reducing the code of the signal.
  • analog equalizers can directly avoid complex and time-consuming processes such as digital logic processing and multiple serial-to-parallel conversions. In this way, while ensuring signal quality, the transmission time of signals in the photoelectric module is greatly reduced. delay, thereby reducing the computing waiting time of the device and improving the overall computing capability.
  • the embodiment of the present application also replaces the original relay CDR with high-speed passive components. In the scenario of transmitting high-speed electrical signals, it can further reduce the signal transmission loss and signal transmission loss from the digital signal interface unit to the photoelectric module. transmission delay.
  • the embodiment of the present application further reduces the transmission time delay of signals in the optical fiber by replacing the original solid-core optical fiber with a hollow-core optical fiber.
  • the embodiment of the present application can minimize the transmission delay of a signal from one device to another device while ensuring the quality of signal transmission. In short, it can effectively ensure that a certain Communication equipment can receive high-quality signals in a very short time, which can greatly improve the computing power of the entire communication system.
  • the embodiment of the present application also provides an active optical cable, which can directly couple the two photoelectric modules with both ends of the hollow-core optical fiber and package them as a whole, thus, Compared with the solution in the prior art, where the photoelectric module is located inside the communication device and needs to be connected to the optical fiber through an adapter, resulting in a large insertion loss, the active optical cable provided by the embodiment of the present application can well reduce or even avoid the photoelectric module.
  • the insertion loss between the module and the optical fiber is equivalent to the insertion loss of the optical signal. Only the loss generated when the optical signal is transmitted inside the optical fiber remains, so that the quality of signal transmission can be further guaranteed.
  • only two ends of the active optical cable need to be respectively connected to two communication devices, and the operation is convenient.
  • FIG. 22 is a schematic flowchart of a communication method using a photoelectric module provided by an embodiment of the present application.
  • the communication method can be applied to communication devices (for example, communication device 10 and communication device 20, any one of switches, servers, memory resource pools and storage resource pools as described above in FIG. 6 ).
  • the communication device may include a photoelectric module; the photoelectric module includes an analog equalizer and a photoelectric conversion unit; the analog equalizer is connected to the photoelectric conversion unit.
  • the communication method may be applied to the system architecture described above in FIG. 6 or a similar system architecture, and the communication method may include the following steps S301-S302.
  • Step S301 through the analog equalizer in the photoelectric module, perform first analog signal equalization processing on the first electrical signal to obtain a second electrical signal, and send the second electrical signal to the photoelectric conversion unit, or, through the analog
  • the equalizer receives a third electrical signal from the photoelectric conversion unit, and performs a second analog signal equalization process on the third electrical signal to obtain a fourth electrical signal;
  • step S302 through the photoelectric conversion unit in the photoelectric module, from the The analog equalizer receives the second electrical signal and converts the second electrical signal into a first optical signal, or converts the second optical signal into the third electrical signal through the photoelectric conversion unit and transmits the second electrical signal to the An analog equalizer sends the third electrical signal.
  • the method may specifically include: using the first photoelectric converter in the photoelectric conversion unit, receiving the second electrical signal from the analog equalizer and converting the second electrical signal into the The first optical signal; through the sending equalizer in the analog equalizer, perform the first analog signal equalization process on the first electrical signal to obtain the second electrical signal, and send the second electrical signal to the first photoelectric converter.
  • the method may specifically include: using a second photoelectric converter in the photoelectric conversion unit, converting the second optical signal into the third electrical signal and sending the third electrical signal to the analog equalizer The third electrical signal; through the receiving equalizer in the analog equalizer, the third electrical signal is received from the second photoelectric converter, and the second analog signal equalization process is performed on the third electrical signal to obtain the fourth electrical signal.
  • each method procedure in the communication method using a photoelectric module described in the embodiments of the present application may be specifically implemented in a software-based, hardware-based, or a combination thereof.
  • the way of implementing by hardware may include logic circuit, arithmetic circuit or analog circuit and so on.
  • a software implementation may include program instructions, which may be regarded as a software product, which is stored in a memory and can be executed by a processor to implement related functions.
  • An embodiment of the present application also provides a computer-readable storage medium, wherein the computer-readable storage medium can store a program, and when the program is executed by a processor, the processor can execute any of the methods described in the above-mentioned method embodiments. Some or all of the steps of one.
  • the embodiment of the present application also provides a computer program, the computer program includes instructions, when the computer program is executed by a multi-core processor, the processor can perform some or all of the steps described in any one of the above method embodiments .
  • the disclosed device can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the above units is only a logical function division.
  • there may be other division methods for example, multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical or other forms.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the above integrated units are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, server, or network device, etc., specifically, a processor in the computer device) execute all or part of the steps of the above-mentioned methods in various embodiments of the present application.
  • the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disc, read-only memory (read-only memory, ROM), double data rate synchronous dynamic random access memory (double data rate, DDR), flash memory ( flash) or random access memory (random access memory, RAM) and other media that can store program code.

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Abstract

本申请实施例公开了一种光电模块、通信方法及相关设备，该光电模块包括模拟均衡器和光电转换单元，模拟均衡器和光电转换单元连接；模拟均衡器，用于对第一电信号进行第一模拟信号均衡处理以得到第二电信号，并发送所述第二电信号至所述光电转换单元，或，用于从光电转换单元接收第三电信号，对所述第三电信号进行第二模拟信号均衡处理以得到第四电信号；光电转换单元，用于从模拟均衡器接收所述第二电信号并将所述第二电信号转换为第一光信号，或，用于将第二光信号转换为所述第三电信号并向模拟均衡器发送所述第三电信号。采用本申请实施例可以通过在模拟域对电信号进行均衡处理，从而在保证信号传输质量的同时，降低信号传输时延。

Description

一种光电模块、通信方法及相关设备 技术领域
本申请实施例涉及通信技术领域，尤其涉及一种光电模块、通信方法及相关设备。
背景技术
一个高性能计算(high performance computing，HPC)集群通常包括有多级交换机和多台服务器等。在交换机与服务器、交换机与交换机之间可以采用高速电缆或者光纤进行数据传输，以降低传输时延。
随着传输数据量的增大，单端口的数据速率越来越高，服务器接口主流已经从4×10Gbps演进到4×25Gbps。其中，端口速率越高意味着带宽越大，电信号在印刷电路板(printed circuit board，PCB)、电缆等介质中传输的损耗系数越大。因此，为了解决电信号或者光信号在传输和光/电转换过程中带来的信号衰减和信号失真，市面上大多采用在交换机或者服务器等内部增加一个时钟与数据恢复(clock and data recovery，CDR)单元的方式，以对接收到电信号进行再生、再定时和再放大。
然而，额外增加的CDR单元虽然可以在一定程度上解决电信号在传输过程中因损耗系数大带来的问题，但是采用CDR对接收到电信号进行再生、再定时和再放大的过程中，需要将接收到的高速电信号通过串并转换为低速电信号并进行数字逻辑处理，然后再并串转换为高速电信号。其中，数字逻辑处理和串并转换等都会带来较大的时延，反而又增加了计算等待时间，降低了HPC集群整体的计算能力。因此，如何在保证信号传输质量的前提下，降低传输时延是亟待解决的问题。
发明内容
本申请实施例提供一种光电模块、通信方法及相关设备，可以在保证信号传输质量的同时，降低传输时延。
第一方面，本申请实施例提供了一种光电模块，包括模拟均衡器和光电转换单元，所述模拟均衡器和所述光电转换单元连接；所述模拟均衡器，用于对第一电信号进行第一模拟信号均衡处理以得到第二电信号，并发送所述第二电信号至所述光电转换单元，或，用于从所述光电转换单元接收第三电信号，对所述第三电信号进行第二模拟信号均衡处理以得到第四电信号；所述光电转换单元，用于从所述模拟均衡器接收所述第二电信号并将所述第二电信号转换为第一光信号，或，用于将第二光信号转换为所述第三电信号并向所述模拟均衡器发送所述第三电信号。
在本申请实施例中，光电模块内可以采用模拟均衡器替代原有的CDR。如此，可以通过模拟均衡器直接在模拟域对输入的电信号(例如第一电信号，可以为本设备向其他设备发送信号时，输入模拟均衡器的电信号；又例如第三电信号，可以为其他设备向本设备发送信号时，本设备的光电转换单元接收到并输出至模拟均衡器的电信号)进行模拟信号均衡处理，补偿该电信号在传输过程中产生的损耗，并高效、快速地输出质量更优、码间干扰更小的电信号(例如第二电信号或者第四电信号)。如此，实现在保证信号传输质量的同时，避免了上述CDR中数字逻辑处理和串并转换等复杂且耗时长的处理过程，大大降低了通信设备间的信号传输时延，进而降低了各通信设备的计算等待时间，提高了整体的计算能力。
在一种可能的实现方式中，所述光电转换单元包括：第一光电转换器，用于从所述模拟均衡器接收所述第二电信号并将所述第二电信号转换为所述第一光信号；所述模拟均衡器包括：发送均衡器，用于对所述第一电信号进行所述第一模拟信号均衡处理以得到所述第二电信号，并发送所述第二电信号至所述第一光电转换器。在本申请实施例中，在本设备向其他设备发送信号的情况下，本设备中待发送的电信号(例如第一电信号)在输入至该模拟均衡器之前的传输过程中存在传输损耗，因此，模拟均衡器接收到的电信号往往会存在一定程度的信号失真和衰减，从而导致其码间干扰大于原始输出的电信号的码间干扰。基于此，在发送方向上，本申请中的模拟均衡器可以在模拟域对接收到的电信号进行均衡处理，补偿该电信号前期传输过程中的损耗，并高效、快速地输出质量更优、码间干扰更小的电信号(例如第二电信号)至光电模块中的光电转换单元。然后，光电转换单元可以将接收到的电信号转换成相应的光信号，以便后续通过光纤将信号快速传输至其他设备，保证其他设备能够快速接收到质量更优的信号。在一些可能的实施例中，如上所述，由于模拟均衡器输出的电信号后续还要进行电光转换并传输至其他设备，因此该模拟均衡器还可以基于后续传输过程中可能产生的传输损耗对该电信号进行预均衡处理，以弥补后续传输过程中的损耗，进一步保证其他设备接收到的信号质量等，本申请实施例对此不作具体限定。
在一种可能的实现方式中，所述发送均衡器包括第一连续时间线性均衡器CTLE、第一低频均衡器LFEQ、第一电平失配补偿电路中的至少一种。如此，模拟均衡器在发送方向上可以对接收到的本设备待发送的信号(例如第一电信号)的高频部分和/或低频部分进行补偿，减少其高频部分和/或低频部分的码间干扰，从而较之接收到的电信号，可以得到并输出码间干扰更小的优质电信号。
在一种可能的实现方式中，所述发送均衡器包括：串联的所述第一CTLE、所述第一LFEQ和所述第一电平失配补偿电路。在本申请实施例中，可以通过模拟均衡器对信号的全部频段进行补偿，得到更高质量的电信号，更加可靠地保证其他设备接收到的信号质量。
在一种可能的实现方式中，所述光电转换单元包括：第二光电转换器，用于将所述第二光信号转换为所述第三电信号并向所述模拟均衡器发送所述第三电信号；所述模拟均衡器包括：接收均衡器，用于从所述第二光电转换器接收所述第三电信号，对所述第三电信号进行所述第二模拟信号均衡处理以得到所述第四电信号。在本申请实施例中，在本设备接收其他设备发送的信号的情况下，本设备中的光电转换单元可以接收其他设备输出的光信号，并将其转换成相应的电信号(例如第三电信号)输出至模拟均衡器。相应的，该电信号在输入至该模拟均衡器之前的传输过程中存在损耗，基于此，在接收方向上，本申请中的模拟均衡器可以在模拟域对接收到的电信号进行均衡处理，补偿该电信号前期传输过程中的损耗，并高效、快速地输出质量更优、码间干扰更小的电信号(例如第四电信号)，从而保证本设备最后接收到并用于进行相应计算或者分析等的电信号的质量。
在一种可能的实现方式中，所述接收均衡器包括第二CTLE、第二LFEQ、第二电平失配补偿电路中的至少一种。如此，模拟均衡器在接收方向上可以对接收到的其他设备待发送的信号(例如第三电信号)的高频部分和/或低频部分进行补偿，减少其高频部分和/或低频部分的码间干扰，从而较之接收到的电信号，可以得到并输出码间干扰更小的优质电信号。
在一种可能的实现方式中，所述接收均衡器包括：串联的所述第二CTLE、所述第二LFEQ和所述第二电平失配补偿电路。在本申请实施例中，可以通过模拟均衡器对信号的全部频段进行补偿，得到更高质量的电信号，更加可靠地保证本设备接收到的信号质量。
第二方面，本申请实施例提供了一种通信设备，包括数字信号接口单元，以及第一方面中任意一项所述的光电模块；所述数字信号接口单元，用于从处理设备接收第一数字电信号，将所述第一数字电信号转换为所述第一电信号，并发送所述第一电信号至所述模拟均衡器，或，用于从所述模拟均衡器接收所述第四电信号，将所述第四电信号转换为第二数字电信号，并发送所述第二数字电信号至所述处理设备。
在本申请实施例中，在本设备向其他设备发送信号的情况下，本设备中的数字信号接口单元可以将处理设备(例如中央处理器(central processing unit，CPU)或者图形处理器(graphics processing unit，GPU)等等)输出的数字电信号转换为模拟电信号(例如第一电信号)，并将该模拟电信号输入至模拟均衡器，以便后续可以通过该模拟均衡器直接在模拟域对该模拟电信号进行均衡处理，从而高效、快速地得到并输出码间干扰更小的高质量模拟电信号(例如第二电信号)，以保证其他设备接收到的信号的质量，并且大大降低了信号传输时延。或者，在本设备接收其他设备发送的信号的情况下，模拟均衡器基于接收到的光电转换单元发送的模拟电信号(例如第三电信号)，直接在模拟域对该模拟电信号进行均衡处理，高效、快速地得到并输出码间干扰更小的高质量模拟电信号(例如第四电信号)至该数字信号接口单元，然后数字信号接口单元可以将该模拟电信号转换成相应的高质量的数字电信号并输出至上述处理设备，从而保证后续处理设备可以基于接收到的数字电信号进行可靠、准确的计算或者分析等等，并且大大降低了本设备等待接收信号的时间。
在一种可能的实现方式中，所述设备还包括：高速无源部件，用于连接所述数字信号接口单元与所述模拟均衡器。在本申请实施例中，本申请的数字信号接口单元和均衡器之间还可以通过高速无源部件连接，从而为信号提供低损耗的高速传输通道，在进一步降低码间干扰，保证信号质量的同时，降低传输时延。
在一种可能的实现方式中，所述高速无源部件包括第一高速接插件、第二高速接插件和高速电缆，所述第一高速接插件与所述第二高速接插件通过所述高速电缆连接；所述第一高速接插件与所述数字信号接口单元连接，所述第二高速接插件与所述模拟均衡器连接。在本申请实施例中，若设备中的数字信号接口单元与模拟均衡器(或者说光电模块)之间的距离较远，且传输的信号速率较高，则信号在此期间传输时会产生较为严重的传输损耗以及较大的传输时延。基于此，本申请实施例中的高速无源部件可以包括两个高速接插件，以及用于连接两个高速接插件的一段高速电缆。通过两个高速接插件分别与数字信号接口单元和模拟均衡器连接，然后通过中间的高速电缆提供低损耗的高速传输通道，保证信号在设备内进行较长距离传输的情况下，降低信号传输损耗和传输时延，进而可以确保后续模拟均衡器可以快速且有效地补偿电信号的传输损耗。
在一种可能的实现方式中，所述高速无源部件包括第一高速接插件，所述第一高速接插件连接在所述数字信号接口单元与所述模拟均衡器之间；所述设备还包括：第一空芯光纤和空芯光纤连接器；所述第一空芯光纤与所述光电转换单元连接，用于发送所述第一光信号或接收所述第二光信号；所述空芯光纤连接器，用于将所述第一光信号发送至第二空芯光纤或从所述第二空芯光纤接收所述第二光信号。在本申请实施例中，本设备与其他设备之间可以通过空芯光纤(例如第二空芯光纤)连接，从而降低信号在设备之间的传输时延。另外，本设备中的高速无源部件可以仅包括一个用于连接在数字信号接口单元与模拟均衡器之间的高速接插件，如此，模拟均衡器(或者说光电模块)则位于距离数字信号接口单元较近的位置， 相应的，光电模块内的光电转换单元则位于距离设备之间的空芯光纤较远的位置，也即光电转换单元输出的光信号需要经过较长的距离才能传输至设备之间的空芯光纤，或者设备之间的空芯光纤输出的光信号需要经过较长的距离才能传输至光电转换单元。基于此，本设备还可以包括一段与光电转换单元的空芯光纤(例如第一空芯光纤)，以及用于连接设备内的空芯光纤以及设备之间的空芯光纤的连接器，通过该连接器可以经由设备内外的空芯光纤进行高速的光信号传输。
第三方面，本申请实施例提供了一种有源光缆，包括至少两个第一方面中任意一项所述的光电模块，以及空芯光纤；所述至少两个光电模块通过所述空芯光纤连接。
第四方面，本申请实施例提供了一种通信系统，其特征在于，包括多个通信设备，所述多个通信设备之间通过第三方面中所述的有源光缆连接。在一种可能的实现方式中，所述多个通信设备包括至少一个上述第二方面中任一项所述的设备。
第五方面，本申请实施例提供了一种利用光电模块的通信方法，包括：通过所述光电模块内的模拟均衡器，对第一电信号进行第一模拟信号均衡处理以得到第二电信号，并发送所述第二电信号至光电转换单元，或，通过所述模拟均衡器从所述光电转换单元接收第三电信号，对所述第三电信号进行第二模拟信号均衡处理以得到第四电信号；通过所述光电模块内的所述光电转换单元，从所述模拟均衡器接收所述第二电信号并将所述第二电信号转换为第一光信号，或，通过所述光电转换单元将第二光信号转换为所述第三电信号并向所述模拟均衡器发送所述第三电信号。
第六方面，本申请实施例提供了一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，该计算机程序被处理器执行时实现上述第五方面中所述的基于光电模块的通信方法流程。其中，该处理器可以为一个或多个处理器。
第七方面，本申请实施例提供了一种计算机程序，该计算机程序包括指令，当该计算机程序被计算机执行时，使得计算机可以执行上述第五方面中所述的基于光电模块的通信方法流程。
第八方面，本申请实施例提供一种芯片，该芯片包括处理器和通信接口，所述处理器用于从该通信接口调用并运行指令，当该处理器执行所述指令时，使得该芯片执行上述第五方面中所述的基于光电模块的通信方法流程。
第九方面，本本申请实施例提供了一种芯片系统，该芯片系统可以包括上述第一方面中任意一项所述的光电模块，用于实现上述第五方面中所述的基于光电模块的通信方法流程所涉及的功能。在一种可能的设计中，所述芯片系统还包括存储器，所述存储器，用于保存调整方法必要的程序指令和数据。该芯片系统，可以包括芯片，也可以包含芯片和其他分立器件。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。
图1是本申请实施例提供的一种高性能计算集群的架构示意图。
图2是本申请实施例提供的一种HPC数据传输链路的示意图。
图3是本申请实施例提供的一组空芯光纤的示意图。
图4是一种节点间数据链路的示意图。
图5是另一种节点间数据链路的示意图。
图6是本申请实施例提供的一种系统架构示意图。
图7是本申请实施例提供的一种光电模块的结构示意图。
图8是本申请实施例提供的一种通信系统的结构示意图。
图9是本申请实施例提供的另一种通信系统的结构示意图。
图10是本申请实施例提供的一组通信设备的内部连接结构示意图。
图11是本申请实施例提供的一种模拟均衡器的结构示意图。
图12是本申请实施例提供的一种CTLE的电路结构以及增益曲线调节示意图。
图13是本申请实施例提供的一种LFEQ的电路结构示意图。
图14是本申请实施例提供的一组单比特响应曲线图。
图15是本申请实施例提供的一种时域补偿范围示意图。
图16是本申请实施例提供的一种光电模块的结构示意图。
图17是本申请实施例提供的一组光电模块的结构示意图。
图18是本申请实施例提供的一种有源光缆的结构示意图。
图19是本申请实施例提供的又一种通信系统的结构示意图。
图20是本申请实施例提供的一组有源光缆的结构示意图。
图21是本申请实施例提供的另一种有源光缆的结构示意图。
图22是本申请实施例提供的一种利用光电模块的通信方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例进行描述。本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”，以及“第一个”、“第二个”、“第三个”和“第四个”等均是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
首先，对本申请中的部分用语进行解释说明，以便于本领域技术人员理解。
(1)高性能计算(high performance computing，HPC)，指通常使用多个处理器(作为单 个服务器的一部分)或者某一集群中的多台服务器(作为单个计算资源操作)及其交换网络的计算系统和环境。
请参阅图1，图1是本申请实施例提供的一种高性能计算集群的架构示意图。如图1所示，一个大型的高性能计算集群可以包括多级交换机(例如一级交换机、二级交换机和三级交换机，每级均可以包括多个交换机)和多个服务器阵列，每个服务器阵列均可以包括多个服务器。应理解，图1仅为示意性举例，根据HPC集群规模大小可以有不同的配置。例如，较小规模的HPC集群可以仅使用一级交换机，中等规模的HPC集群可能使用两级交换机，大规模HPC集群可能使用三级或者更多级交换机进行数据交换。
为了降低数据(或者说信号)在不同服务器或者交换机之间传输的时延，减少计算等待时间，提高整体的计算能力，HPC系统通常使用高性能网络互连，比如采用低时延"无限带宽"技术(infiniband，IB)交换机。其中，"无限带宽"技术是一个用于高性能计算的计算机网络通信标准，它具有极高的吞吐量和极低的延迟，用于计算机与计算机之间的数据互连。infiniband也用作服务器与存储系统之间的直接或交换互连，以及存储系统之间的互连。在infiniband交换机与服务器、infiniband交换机之间可以采用高速电缆或者光纤进行数据传输，以进一步降低传输时延。
请参阅图2，图2是本申请实施例提供的一种HPC数据传输链路的示意图。如图2所示，A节点和E节点可以为服务器，B节点、C节点和D节点可以为交换机。需要说明的是，由于高速率电信号在电缆中传输的损耗系数较大，因此当两个节点之间的距离超过5米时，通常都需要使用光纤进行传输，同时需要一个光电模块来进行光/电转换(例如图2中A、B、C、D节点内的光电模块)。在一个实际的HPC集群中，交换机节点间的距离通常都超过5米，因此大多只能使用光纤进行信号传送，而交换机与服务器之间可以综合考虑信号速率与节点间距离，可以使用光纤也可以使用电缆进行信号传送。如图2所示，A节点-B节点间链路示意为采用光纤进行信号传输，而D节点-E节点间链路示意为采用电缆进行信号传输，本申请实施例对此不作具体限定。
如图2所示，一个信号从A节点发出，经过B节点、C节点、D节点，然后到达E节点，其中涉及的主要时延可以包括：A节点网络处理接口单元的信号处理时延、A节点-B节点间的链路传输时延、B节点数据交换单元的信号处理时延、B节点-C节点间的链路传输时延、C节点数据交换单元的信号处理时延、C节点-D节点间的链路传输时延、D节点数据交换单元的信号处理时延、D节点-E节点间的链路传输时延、E节点网络处理接口单元的信号处理时延。
(2)插损，即插入损耗，一般为将某些器件或分支电路(滤波器、阻抗匹配器、适配器等)加进某一电路时，能量或增益的损耗。其中，光信号在两个节点之间进行传输时的插入损耗一般可以分为三部分，以图2中的A节点和B节点为例，光信号在A节点和B节点之间传输时的插入损耗可以包括：A节点的光电模块与光纤连接处的插入损耗(一般可以通过适配器等器件将光电模块与光纤进行连接)，光纤传输过程中光纤内部存在的插入损耗(或者说传输损耗)，光纤与B节点的光电模块连接处的插入损耗。
(3)空芯光纤，与常规的光纤波导导光的全反射原理不同，空芯光纤的纤芯是空气，因 此带来低时延、超低非线性、低色散等好处。然而，空芯光纤起初存在插损非常大的问题，为了克服空芯光纤插损大的问题，市面上提出了多种基于反谐振原理的空芯光纤，即基于包层中谐振腔的反谐振机理将光束缚在作为核心的空气孔中。请参阅图3，图3是本申请实施例提供的一组空芯光纤的示意图。如图3中的(a)、(b)、(c)和(d)所示，基于反谐振原理的空芯光纤主要是利用光在光纤内的管状玻璃薄膜间来回相干反射将光限制在空气芯附近并沿轴线传输。其加工制造工艺极其复杂，往往需要在加工制造过程中对空芯光纤内的管状玻璃的直径(um级别)和薄膜厚度(nm级别)进行精确控制。目前市面上仅能做到单根反谐振空芯光纤的长度到达数公里，其实际插损系数的典型值为1～10dB/km，仍然远大于现有的实芯单模光纤约0.2dB/km的插损系数。如上所述，现有的反谐振空芯光纤仍存在长度短、插损大的缺点，导致其很难被大规模使用。
(4)时钟与数据恢复(clock and data recovery，CDR)，其主要作用是让接收端的信号与发射端信号保持一致。因为电信号或者光信号传输至一定距离的时候，通常是长距离传输，其波形会出现一定程度的失真，接收端接收到的信号是一个个长短不一的脉冲信号，无法满足实际需求。在上述情况下，可以通过CDR进行信号的再生，再放大和再定时，等等，从而得到符合需求的信号。一般情况下，会使用到CDR的光电模块，多数都是一些高速率、长距离传输的光电模块。
如上所述，随着信息社会的快速发展，需要传输的数据量越来越大，单端口的数据速率越来越高，服务器接口主流已经从4×10Gbps演进到4×25Gbps。其中，端口速率越高意味着带宽越大，电信号在印刷电路板(printed circuit board，PCB)、电缆等介质中传输的损耗系数越大，因此，往往需要对本节点接收到的信号，或者本节点待发送的信号进行一系列处理，从而弥补信号在传输过程中不可避免的损耗，以保证信号的质量，确保节点可以基于接收到的信号进行可靠、准确的计算等。
综上，为了便于理解本申请实施例，进一步分析并提出本申请所具体要解决的技术问题。在现有技术中，为了解决在传输速率越来越快的情况下，产生的信号损耗严重的问题，包括多种技术方案，以下示例性的例举如下常用的方案。
请参阅图4，图4是一种节点间数据链路的示意图。如图4所示，A节点和B节点可以为HPC集群中通过光纤进行数据传输的两个设备。A节点和B节点内均可以包括数字信号接口单元和光电模块，可选地，该数字信号接口单元和光电模块可以部署在PCB上。如图4所示，A节点和B节点的光电模块均可以包括电光转换单元、光电转换单元和CDR。
可选地，图4所示的A节点、B节点的设备类型可以包括但不限于：服务器、交换机、存储资源池和内存资源池等。相应的，A节点、B节点内的数字信号接口单元可以包括但不限于：网络处理接口单元、数据交换单元、存储接口单元、内存接口单元等。如上所述，该数字信号接口单元可以用于实现对数字信号的逻辑处理，并输出或接收一路(lane)或多路的电信号，该电信号可以为高速电信号，用于在节点间传输数据。
如图4所示，以A节点向B节点发送信号为例，A节点中的电光转换单元可以通过光纤与B节点中的光电转换单元连接，如此，A节点的数字信号接口单元输出的电信号可以通过A节点的电光转换单元转换成相应的光信号，并经由光纤传输至B节点的光电转换单元，然后，通过B节点的光电转换单元将该光信号换成相应的电信号，并输入至B节点的数字信号 接口单元，最后，B节点的数字信号接口单元可以对输入的电信号进行一系列逻辑计算等等。相应的，如图4所示，B节点中的电光转换单元可以通过光纤与A节点中的光电转换单元连接，B节点向A节点发送信号同理，此处不再进行赘述。
结合图4所示的节点结构可知，在上述损耗系数较大的情况下，以A节点为例，A节点的网络处理接口单元输出的电信号由于在PCB等介质上传输时的损耗(或者说畸变，比如信号的幅度、频率和相位等发生改变，损耗一般可以指信号幅度的降低)，使其存在一定程度的衰减和失真，从而已经很难直接驱动A节点的电光转换单元；相应的，A节点的光电转换单元输出的电信号在传输过程中也会存在损耗，导致信号衰减和失真，因此A节点的网络处理接口单元也无法准确接收来自A节点的光电转换单元输出的电信号。此外，通常情况下，光信号在光纤中传输时也会存在一定程度的衰减和失真，并且光电转换单元和电光转换单元在进行光信号和电信号的互相转换的过程中也会存在一定的衰减和失真，等等。
如此，为了解决电信号或者光信号在传输以及光/电转换过程中带来的信号衰减和信号失真，如图4所示，可以在A节点和B节点各自的光电模块中增加一个CDR，以对接收到电信号进行再生、再定时和再放大，然后再输入至电光转换单元或者数字信号接口单元。以A节点向B节点发送信号为例，增加的CDR可以尽可能的保证最终输入至B节点的数字信号接口单元的电信号与A节点的数字信号接口单元最初输出的电信号一致。
进一步地，如图4所示，信号从一个节点的数字信号接口单元输出至另一个节点的数据接口单元的所有时延之和，在本申请实施例中可以定义为两个节点间(或者说两个通信设备间)的链路传输时延。下面，仍以信号从A节点传输到B节点传输为例，A节点-B节点间的链路传输时延包括：
(1)A节点CDR发送方向时延(即A节点CDR接收到数字信号接口单元发送的信号后，进行信号的再生、在定时和再放大所需的时延)、B节点CDR接收方向时延(即B节点CDR接收到光电转换单元发送的信号后，进行信号的再生、在定时和再放大所需的时延)。可选地，根据不同速率、不同编码格式以及不同的设计方案，上述这两项时延之和一般为几十纳秒(ns)到几百纳秒之间，一个典型值为100ns。
(2)A节点光电模块输出到B节点光电模块之间的光纤传输时延。以当前使用的光纤为实芯的单模光纤(single mode fiber，SMF)或者多模光纤(multi mode fiber，MMF)为例，光纤的传输时延系数约为4.8ns/m，以50米长的光纤为例，光纤传输时延总计为240ns。
(3)A节点、B节点的电信号在各自的PCB上的走线时延，例如A节点数字信号接口单元输出电信号到A节点CDR之间的走线时延，A节点CDR输出电信号到A节点电光转换单元之间的走线时延，等等，此处不再详述。受PCB使用材料的介电常数不同的影响，PCB传输时延系数约在5～10ns/m，然而由于PCB走线长度较短，通常在每个节点的走线长度小于0.5米，即A节点、B节点的电信号走线时延总和通常小于10ns。显然，相比上述CDR时延和光纤传输时延来说，电信号在PCB上的走线时延是一个很小的数值。
进一步地，当端口速率继续增加，比如增加到4×50Gbps，业界开始采用4电平脉冲幅度调制(4levels pulse amplitude modulation，PAM4)编码格式来替代非归零(non-return-to-zero，NRZ)编码格式以降低信号的波特率，从而避免信号带宽增大导致的PCB和电缆等介质传输的损耗系数增大。然而，由于多电平信号对信号失真更加敏感，并且能够容忍的信号衰减更小，当数字信号接口单元距离光电模块较远时，为了避免信号失真和信号衰减过大，需要在 主板PCB上再增加一个CDR单元。
请参阅图5，图5是另一种节点间数据链路的示意图。有关图5的介绍可以参考上述图4中的描述，此处不再进行赘述。其中，例如在上述端口速率继续增加至4×50Gbps的情况下，相较于图4，图5中的C节点和D节点中均增设了中继CDR，该中继CDR的两端分别与数字信号接口单元和光电模块中的CDR连接。同理，下面以数据从C节点到D节点传输为例，C节点-D节点间的链路传输时延包括：
(1)C节点光电模块内CDR发送方向时延、D节点光电模块内CDR接收方向时延。可选地，根据不同速率、不同编码格式以及不同的设计方案，上述这两项时延之和一般为几十纳秒到几百纳秒之间，一个典型值为100ns。
(2)C节点中继CDR发送方向时延、D节点中继CDR接收方向时延。可选地，根据不同速率、不同编码格式以及不同的设计方案，上述这两项时延之和一般为几十纳秒到几百纳秒之间，一个典型值为100ns。
(3)C节点光电模块输出到D节点光电模块之间的光纤传输时延，仍以当前使用的光纤为实芯的SMF或MMF为例，光纤的传输时延系数均为4.8ns/m，以50米光纤为例，光纤传输时延总计为240ns。
(4)C节点、D节点的电信号在各自的PCB上的走线时延。同理，C节点、D节点的电信号走线时延总和一般小于10ns。显然，相比上述光电模块内CDR时延、中继CDR时延和光纤传输时延来说，电信号在PCB上的走线时延是一个很小的数值。
需要说明的是，图4和图5仅为示例性的说明一种可能的节点间数据链路，在一些可能的实施方式中，每个节点内均可以包括比图4或者图5更多或者更少，甚至不同的部件，等等，本申请实施例对此不作具体限定。
综上，增设的CDR虽然可以在一定程度上解决电信号和光信号因传输以及光电转换等损耗带来的问题，但是采用CDR对接收到电信号进行再生、再定时和再放大的过程中，需要将接收到的高速电信号通过串并转换为低速电信号并进行数字逻辑处理，然后再并串转换为高速电信号。其中，数字逻辑处理和串并转换等操作复杂、耗时长，都会带来较大的时延。以上图C节点-D节点间的链路为例，光纤传输时延为240ns，光电模块内CDR时延为100ns，主板上中继CDR时延为100ns，PCB走线时延约为10ns，总时延为450ns，其中，光电模块内的CDR时延以及中继CDR时延的总和(200ns)甚至与50米长的光纤传输时延相当，几乎占了总时延的一半，这大大增加了整个链路的传输时延，也即增加了计算等待时间，进而降低了HPC集群整体的计算能力。
因此，为了解决当前技术中不满足实际业务需求的问题，本申请实际要解决的技术问题包括如下方面：通过合理的器件选择和布局，在保证信号传输质量的前提下，降低通信设备间的信号传输时延，以减少计算等待时间，提高整体的计算能力。可选地，上述通信设备间包括但不限于：服务器、交换机、存储资源池、内存资源池等任意两个设备之间。比如，两台服务器之间，两台交换机之间，服务器与交换机之间，服务器与内存资源池之间，交换机与存储资源池之间等，本申请实施例对此不作具体限定。
请参阅图6，图6是本申请实施例提供的一种系统架构示意图。本申请实施例的技术方案可以在图6举例所示的系统架构或类似的系统架构中具体实施。如图6所示，该系统架构 可以包括一个HPC集群，该HPC集群可以包括多个节点，具体可以包括多个一级交换机(比如交换机100a、100b和100c等)、多个二级交换机(比如交换机200a、200b和200c等)、多个三级交换机(比如交换机300a、300b和300c等)、服务器阵列400、内存资源池500和存储资源池600等等。其中，服务器阵列400中可以包括多个服务器，内存资源池500中可以包括多个内存，存储资源池600中可以包括多个存储器，等等，此处不再详述。如图6所示，该多个交换机、服务器阵列400、内存资源池500和存储资源池600任意设备之间可以通过光纤连接以进行信号传输。
其中，该多个交换机、服务器阵列400、内存资源池500和存储资源池600中均可以包括数字信号接口单元和光电模块。在本申请实施例中，该多个交换机、服务器阵列400、内存资源池500和存储资源池600中的光电模块内均可以采用模拟均衡器替代原有的CDR。如此，上述各个节点可以通过各自节点内的模拟均衡器直接在模拟域对接收到的高速电信号(可以为本节点的数字信号接口单元输出至模拟均衡器的电信号，也可以为本节点的光电转换单元基于其他节点输出的光信号进行转换后输出至模拟均衡器的电信号)进行模拟信号均衡处理，补偿其在传输过程中产生的损耗，从而高效、快速地输出质量更优的电信号，实现在保证信号传输质量的同时，避免了上述数字逻辑处理和串并转换等等复杂且耗时长的处理过程，大大降低了信号传输时延，继而降低了各节点的计算等待时间，提高了该HPC集群整体的计算能力。
其中，在HPC集群的场景中，电信号的波特率一般大于25G波特率(Baud/s)，例如若采用NRZ编码格式，其每路电信号的速率大于25Gbps，若采用PAM4编码格式，其每路电信号的速率大于50Gbps，若采用PAM8编码格式，其每路高速电信号的速率大于75Gbps，等等，其它编码格式的速率以此类推，此处不再详述。如上所述，本申请实施例中的模拟均衡器可以适用于处理速率非常高的高速电信号(例如为波特率大于25G波特率，甚至大于50G波特率的高速电信号)。
进一步地，上述光纤可以采用实芯光纤，也可以采用空芯光纤。优选地，可以采用空芯光纤替代SMF、MMF等实芯光纤。
首先，由于实芯光纤采用纤芯材料的折射率约为1.45，而空芯光纤采用空气做为传输介质，其折射率约为1，因此光信号在空芯光纤中的传输速度高于在实芯光纤中的传输速度，分别约为300000km/s和207000km/s。光信号传输经过1米空芯光纤和1米实芯光纤所需的时延分别为3.3ns和4.8ns，显然，光信号经过相同距离的光纤，空芯光纤所需的时延远远小于实芯光纤，一般仅为实芯光纤的69％。
其次，在图6所示的系统架构中，也即在HPC集群的场景中，光纤传输距离较短，其范围介于5～2000米之间，典型值约为10～100米。参考上述对空芯光纤的解释说明可知，现有空芯光纤的插损较大，单段空芯光纤长度较短等缺点对该场景的整体性能以及成本影响很小。因此本申请实施例可以优选采用空芯光纤，以进一步降低传输时延。
需要说明的是，图6所示的系统架构仅为示意性举例，为本申请实施例中较为优选的系统架构或者应用场景，本申请实施例提供的光电模块等可以应用于除图6所示的HPC集群外的其他场景中，本申请实施例对此不作具体限定。此外，在一些可能的实施方式中，上述节点还可以是手机、笔记本电脑和台式电脑等移动终端，等等，本申请实施例对此不作具体限定。
请参阅图7，图7是本申请实施例提供的一种光电模块的结构示意图。如图7所示，该光电模块102可以应用于通信设备10中，该通信设备10可以为光电通信设备，例如为上述图6所示系统架构中的交换机(例如交换机100a、100b、100c、200a、200b、200c和300a等等)、服务器、内存资源池和存储资源池等节点中的任意一个。
如图7所示，光电模块102可以包括模拟均衡器103，以及与该模拟均衡器103连接的光电转换单元104。下面，分别以通信设备10发送信号和接收信号为例，对图7所示的光电模块102进行详细阐述。
(1)以通信设备10向其他设备发送信号为例。
模拟均衡器103，用于接收第一电信号，对第一电信号进行第一模拟信号均衡处理，得到第二电信号，并发送该第二电信号至光电转换单元104。可选地，该第一电信号、第二电信号可以为模拟电信号，并且均衡处理后得到的第二电信号的码间干扰可以小于第一电信号的码间干扰。
光电转换单元104，用于接收第二电信号，将该第二电信号转换成对应的第一光信号。可选地，该第一光信号后续可以经由通信设备10与其他设备之间连接的光纤(例如空芯光纤)传输至其他设备。
如上所述，应理解，第一电信号在输入至该模拟均衡器103之前的传输过程中不可避免的会产生传输损耗(或者说畸变，比如信号的幅度、频率和相位等发生改变，损耗一般可以指信号幅度的降低)，因此模拟均衡器103接收到的第一电信号相较于原始的第一电信号(或者说刚开始传输时的第一电信号)会存在一定程度的信号衰减和失真(例如第一电信号的幅度、频率和相位中的至少一项会发生改变，较为典型地情况为幅度降低等)，导致模拟均衡器103接收到的第一电信号的码间干扰严重。需要说明的是，码间干扰严重会使误码率显著增加，若不加以处理，则其他设备最终接收到的信号则很有可能是完全错误的，或者是完全无效的，严重影响其他设备以及通信系统整体的计算能力。
如此，本申请实施例可以通过在光电模块102中增设的模拟均衡器103直接在模拟域对接收到的第一电信号进行高效、快速的模拟信号均衡处理，补偿其前期传输过程中产生的传输损耗，无需数字逻辑处理和串并转换等便可以输出信号质量更优、信号码间干扰更小的第二电信号。可选地，该第二电信号可以尽可能地接近原始的第一电信号，甚至与原始的第一电信号相同，还可以比原始第一电信号的码间干扰更小，等等，本申请实施例对此不作具体限定。
综上，在向其他设备发送信号时，本申请实施例提供的光电模块可以大大缩短在发送前进行信号传输损耗补偿所要耗费的时间，从而在保证信号质量的同时，极大程度上降低了信号从通信设备10传输到其他设备的传输时延，降低了其他设备的计算等待时间。
(2)以通信设备10接收其他设备发送的信号为例。
光电转换单元104，用于接收第二光信号，将第二光信号转换为相应的第三电信号，并发送该第三电信号至模拟均衡器103。可选地，该第二光信号可以是其他设备通过光纤发送到光电转换单元104中的信号。
模拟均衡器103，用于接收第三电信号，对第三电信号进行第二模拟信号均衡处理，得到第四电信号。可选地，该第三电信号、第四电信号可以为模拟电信号，并且均衡处理后得到的第四电信号的码间干扰可以小于第三电信号的码间干扰。可选地，通信设备10后续可以基于该第四电信号进行一系列计算或者分析等。
可选地，上述第一电信号、第二电信号、第三电信号和第四电信号可以为波特率大于25G波特率，甚至大于50G波特率的高速电信号，等等，本申请实施例对此不作具体限定。
如上所述，相应的，第三电信号在输入至该模拟均衡器之前的传输过程中不可避免的会产生传输损耗(或者说畸变)，因此模拟均衡器103接收到的第三电信号往往会存在一定程度的信号衰减和失真，导致模拟均衡器103接收到的第三电信号的码间干扰严重，使得通信设备10最终接收到的信号则很有可能是完全错误的，或者是完全无效的，严重影响通信设备10以及通信系统整体的计算能力。
如此，本申请实施例可以通过在光电模块102中增设的模拟均衡器103直接在模拟域对接收到的第三电信号进行高效、快速的模拟信号均衡处理，从而输出信号质量更优、信号码间干扰更小的第四电信号。可选地，该第四电信号可以尽可能地接近光电转换单元104原始输出的第三电信号，或者尽可能的接近其他设备原始输出的电信号，甚至与其他设备原始输出的电信号相同，还可以比其他设备原始输出的电信号的码间干扰更小，等等，本申请实施例对此不作具体限定。
综上，在接收其他设备发送的信号时，本申请实施例提供的光电模块可以大大缩短本设备(即通信设备10)在计算前进行信号传输损耗补偿所要耗费的时间，从而在保证信号质量的同时，极大程度上降低了信号从其他设备传输到通信设备10的传输时延，降低了通信设备10的计算等待时间，提高了整体的计算能力。
可选地，通信设备10也可以仅用于发送信号或者仅用于接收信号，也即光电模块102内的模拟均衡器103、光电转换单元104仅用于实现上述实施例(1)中所述的功能，或者，模拟均衡器103、光电转换单元104仅用于实现上述实施例(2)中所述的功能，本申请实施例对此不作具体限定。
请参阅图8，图8是本申请实施例提供的一种通信系统的结构示意图。如图8所示，该通信系统可以包括通信设备10(例如第一通信设备)和通信设备20(例如第二通信设备)，其中，通信设备10和通信设备20可以通过如图8所示的光纤30和光纤40连接。该通信设备10和通信设备20可以为上述图6所示系统架构中的交换机、服务器、内存资源池和存储资源池等节点中的任意一个。
如图8所示，通信设备10中可以包括数字信号接口单元101和光电模块102，该光电模块102可以包括模拟均衡器103和光电转换单元104，其中，模拟均衡器103可以包括发送均衡器103a、接收均衡器103b；光电转换单元104可以包括第一光电转换器105和第二光电转换器106。其中，发送均衡器103a可以分别与数字信号接口单元101、第一光电转换器105连接；接收均衡器103b可以分别与数字信号接口单元101、第二光电转换器106连接。
可选地，请一并参阅上述图7对应的实施例可知，本申请实施例中涉及的模拟均衡器103可以仅包括该发送均衡器103a，相应的，本申请实施例中涉及的光电转换单元104可以仅包括该第一光电转换器105；或者，模拟均衡器103可以仅包括该接收均衡器103b，相应的，光电转换单元104可以仅包括该第二光电转换器106，等等，本申请实施例对此不作具体限定。
如图8所示，同理，通信设备20中可以包括数字信号接口单元201和光电模块202，该光电模块202可以包括模拟均衡器203和光电转换单元204，其中，模拟均衡器203可以包括发送均衡器203a、接收均衡器203b；光电转换单元204可以包括第一光电转换器205和第 二光电转换器206。其中，发送均衡器203a可以分别与数字信号接口单元201、第一光电转换器205连接；接收均衡器203b可以分别与数字信号接口单元201、第二光电转换器206连接。
可选地，数字信号接口单元101和数字信号接口单元201可以为网络处理接口单元、数据交换单元、存储接口单元、内存接口单元等中的任意一种，本申请实施例对此不作具体限定。
进一步地，如图8所示，第一光电转换器105与第二光电转换器206通过光纤30连接，从而为通信设备10向通信设备20发送信号提供传输通道；第二光电转换器106与第一光电转换器205通过光纤40连接，从而为通信设备20向通信设备10发送信号提供传输通道。其中，光纤30和光纤40可以为实芯光纤或者空芯光纤，优选空芯光纤，从而为光信号的传输提供低时延的传输通道，具体可参考上述图6对应实施例中的描述，此处不再进行赘述。其中，例如光纤30为空芯光纤时，也可以表示该光纤30中至少包括一段空芯光纤，例如光纤30总长为100m，其中可以包括长度为40m的一段空芯光纤，等等，本申请实施例对此不作具体限定。
下面，将结合图8所示的通信设备10和通信设备20，以通信设备10向通信设备20发送信号为例，对本申请实施例提供的一种光电模块进行进一步详细阐述。
首先，需要说明的是，信号在两个通信设备之间进行传输时，器件的传输参数和信道传输参数的不平坦特性均会使得信号产生畸变，造成信号幅频特性的不平坦与群时延特性的波动等，从而使信号的码间干扰非常严重。以通信设备10向通信设备20发送信号为例，信号可能产生的畸变大致可以包括但不限于如下几点：
(1)数字信号接口单元101至发送均衡器103a之间的传输；
(2)发送均衡器103a至第一光电转换器105之间的传输；
(3)第一光电转换器105在将电信号转换成光信号时；
(4)第一光电转换器105与光纤30之间的连接；
(5)光信号在光纤30中的传输；
(6)光纤30与第二光电转换器206之间的连接；
(7)第二光电转换器206在将光信号转换成电信号时；
(8)第二光电转换器206至接收均衡器203b之间的传输；
(9)接收均衡器203b至数字信号接口单元201之间的传输。
其次，以通信设备10向通信设备20发送信号为例，对该过程中各个结构的功能进行详细阐述，具体如下。
数字信号接口单元101：接收来自处理设备(图8中未示出)的第一数字电信号，将第一数字电信号转换成相应的模拟电信号(例如第一电信号)，并发送该第一电信号至发送均衡器103a。可选地，该处理设备可以与数字信号接口单元101连接，例如可以为CPU、GPU或者存储器等等。
发送均衡器103a：接收第一电信号，并在模拟域对第一电信号进行模拟信号均衡处理，补偿该第一电信号在前期传输过程中的畸变(例如包括上述畸变(1))，降低其码间干扰，从而得到第二电信号，然后发送该第二电信号至第一光电转换器105。
可选地，考虑到电信号后续传输过程中可能存在的大量畸变(例如上述畸变(2)、(3)、(4)、(5)、(6)、(7)、(8)等中的至少一项)，且容易导致电信号的高频部分严重衰减，因此，为了保证通信设备20中的接收均衡器203b接收到的电信号不至于存在严重的码间干扰，发送均衡器103a还可以对该第一电信号进行预均衡处理。例如，可以将该第一电信号的低频部分进行适当衰减，从而相较于未进行预均衡处理的情况，可以使得后续通信设备20中的接收均衡器203b接收到的电信号的高频部分和低频部分的幅度差异变小，降低了接收均衡器203b接收到的电信号的码间干扰，等等，本申请实施例对此不作具体限定。
第一光电转换器105：接收第二电信号，将该第二电信号转换成对应的第一光信号并输入至光纤30。
光纤30：接收第一光信号，然后发送该第一光信号至通信设备20中的第二光电转换器206。
第二光电转换器206：接收第一光信号，将第一光信号转换成对应的电信号(例如第三电信号)，并发送第三电信号至接收均衡器203b。可以理解的是，由于通信设备10与通信设备20中的结构相似，发送与接收相对称，因此通信设备20接收到的第一光信号，相当于图7实施例中所述的通信设备10接收到的第二光信号，均为本设备接收到的其他设备发送的光信号。因此，此处的第三电信号可以仅用于表示由本设备接收到光信号转换得到的电信号，而不特指由第二光信号转换得到的电信号。
接收均衡器203b：接收第三电信号，并在模拟域对第三电信号进行模拟信号均衡处理，补偿该第三电信号在前期传输过程中的畸变(例如包括上述畸变(2)、(3)、(4)、(5)、(6)、(7)、(8))，降低其码间干扰，从而得到第四电信号，然后发送该第四电信号至数字信号接口单元201。可选地，相应的，考虑到信号后续传输至数字信号接口单元201过程中可能存在的畸变，因此为了保证数字信号接口单元201接收到的电信号的码间干扰仍然较低甚至为零，接收均衡器203b还可以对第三电信号进行预均衡处理，等等，本申请实施例对此不作具体限定。
数字信号接口单元201：接收第四电信号，将该第四电信号转换成相应的数字电信号(例如第二数字电信号)，并发送该第二数字电信号至通信设备20中的处理设备，以使得通信设备20中的处理设备可以基于该第二数字电信号进行一系列的计算或者分析等等。
至此，完成了通信设备10向通信设备20发送信号的全部过程，可以理解的是，本申请旨在通过在光电模块内设置模拟均衡器，实现直接在模拟域对信号进行均衡处理，以补偿信号传输过程中产生的畸变，达到耗时较短，且能够有效保证通信设备20最终接收到的第四电信号甚至第二数字电信号的质量的目的。可选地，通过模拟均衡器的均衡处理可以使得通信设备20最终接收到的该第四电信号或者第二数字电信号尽可能接近通信设备10最初输出的第一电信号或者第一数字电信号，甚至与该第一电信号或者第一数字电信号相同，保证信号传输的有效、可靠。
可以理解的是，由于通信设备20与通信设备10的结构相似，同理，通信设备20向通信设备10发送信号的过程可参考上述通信设备10向通信设备20发送信号的过程，此处不再进行赘述。
请参阅如下所示的表1，并结合前述图4、图7和图8所述的实施例可知，本申请实施例在采用模拟均衡器以及空芯光纤的情况下信号的传输时延显著下降。如表1所示，本申请图 8所示实施例中的通信设备10与通信设备20之间的传输总时延仅为175ns，而图4所示实施例中的节点A和节点B之间的传输时延长达350ns，本申请实施例的信号传输时延仅为现有技术的50％。具体差异如下：
(1)本申请实施例采用模拟均衡器替代原有的CDR，相较于原本的CDR，模拟均衡器不存在数字逻辑处理和串并转换等带来的较大时延，仅存在电信号在模拟均衡器内的走线时延，而模拟均衡器作为一种集成电路芯片，其内部走线的长度是极短的，带来的时延可以忽略不计，几乎为零，从而节省了约100ns时延。
(2)本申请实施例采用空芯光纤替代原有的实芯光纤(SMF和MMF等)作为通信设备(或者说节点)之间的传输通道。例如，以长度均为50m的光纤传输为例，本申请实施例节省了约75ns时延。
具体时延以及比值可参阅如下表1中的内容，此处不再详述。
表1
Figure PCTCN2021107037-appb-000001
可选地，请参阅图9，图9是本申请实施例提供的另一种通信系统的结构示意图。有关图9的介绍可以参考上述图7和图8对应实施例中的描述，此处不再进行赘述。如图9所示，通信设备10和通信设备20中分别还可以包括高速无源部件107和高速无源部件207。其中，高速无源部件107用于连接数字信号接口单元101和模拟均衡器103(例如包括发送均衡器103a和接收均衡器103b)；相应的，高速无源部件207用于连接数字信号接口单元201和模拟均衡器203(例如包括发送均衡器203a和接收均衡器203b)。
以通信设备10为例，高速无源部件107的两端分别与数字信号接口单元101和光电模块102内的模拟均衡器103连接，从而可以在数字信号接口单元101和模拟均衡器103之间提供低时延、低插损、低畸变的高速电信号传输通道，其传输时延几乎为零。如此，即使模拟均衡器103部署在距离数字信号接口单元较远的位置，也可以降低高速电信号(例如第一电信号或者第四电信号)在数字信号接口单元101和模拟均衡器103传输过程中的传输时延以及传输损耗和畸变。因此，相较于图8所示的通信系统，图9所示的通信系统可以利用通信设备内的高速无源部件，进一步减少信号的传输时延，并保证信号的传输质量，从而进一步提升通信系统的整体计算能力。
请参阅图10，图10是本申请实施例提供的一组通信设备的内部连接结构示意图。图10中以图9所示的通信设备10为例，可以理解的是，图10所示的连接结构也可以应用于通信 设备20或者其他任意一个通信设备内，此处不再进行赘述。
如图10中的(a)所示，该通信设备10具体可以包括数字信号接口单元101、高速接插件01、高速接插件02、高速电缆03和光电模块102。
可选地，数字信号接口单元101可以包含于某个封装好的集成电路芯片内部，如图10中的(a)所示，该集成电路芯片可以部署在PCB上。如图10中的(a)所示，数字信号接口单元101(或者说该集成电路芯片)可以通过若干个焊接点焊接在PCB上。
可选地，高速接插件01可以部署在PCB上距离该数字信号接口单元101较近(或者说距离该集成电路芯片较近)的位置。其中，高速接插件01与高速接插件02通过高速电缆03连接，可以形成上述图9所示的高速无源部件107，相应的，通信设备20中的高速无源部件207也可以包括该高速接插件01、高速接插件02和高速电缆03。可选地，高速接插件01与高速接插件02之间的距离可以较远。
可选地，高速接插件02与光电模块103可以在如图10所示的面板上进行连接。
可选地，光电模块102与光纤30连接，用于输入/输出光信号，并进行相应的光/电转换等等，此处不再赘述。
综上，以通信设备10向通信设备20发送信号为例，如图10中的(a)所示，数字信号接口单元101输出的高速电信号(例如第一电信号)依次经过PCB、高速接插件01、高速电缆03、高速接插件02和光电模块102。在光电模块102中，经过模拟信号均衡处理和电光转换后，输出相应的光信号至光纤30。随后，经过光纤30的传输，光纤30输出光信号至通信设备20的光电模块202，在光电模块202中经过光电转换和模拟信号均衡处理后，输出相应的高速电信号并依次经过通信设备20中的高速接插件02、高速电缆03、高速接插件01、PCB，最后输入到数字信号接口单元201。
如图10中的(b)所示，该通信设备10具体可以包括数字信号接口单元101、高速接插件01、高速接插件02、高速电缆03和光电模块102。
可选地，数字信号接口单元101可以包含于某个集成电路芯片内部(该集成电路芯片可以是未封装的)，如图10中的(b)所示，该集成电路芯片可以部署在基板(substrate)上，该基板可以部署在PCB上。如图10中的(b)所示，基板可以通过若干个焊接点焊接在该基板上。
可选地，高速接插件01可以部署在该基板上距离该数字信号接口单元101较近(或者说距离该集成电路芯片较近)的位置。
可选地，有关图10中的(b)的介绍可以参考上述图10中的(a)的描述，此处不再进行赘述。
综上，仍以通信设备10向通信设备20发送信号为例，如图10中的(b)所示，数字信号接口单元101输出的高速电信号依次经过基板、高速接插件01、高速电缆03、高速接插件02和光电模块102。在光电模块102中，经过模拟信号均衡处理和电光转换后，输出相应的光信号至光纤30。随后，经过光纤30的传输，光纤30输出光信号至通信设备20的光电模块202，在光电模块202中经过光电转换和模拟信号均衡处理后，输出相应的高速电信号并依次经过通信设备20中的高速接插件02、高速电缆03、高速接插件01、基板，最后输入到数字信号接口单元201。
如图10中的(c)所示，该通信设备10具体可以包括数字信号接口单元101、高速接插件01、光电模块102、光纤04和空芯光纤连接器05。
可选地，数字信号接口单元101可以包含于某个封装好的集成电路芯片内部，如图10中的(c)所示，该集成电路芯片可以部署在PCB上。如图10中的(c)所示，数字信号接口单元101(或者说该集成电路芯片)可以基于若干个焊接点焊接在PCB上。
可选地，高速接插件01可以部署在PCB上距离该数字信号接口单元101较近(或者说距离该集成电路芯片较近)的位置，用于连接数字信号接口单元101和光电模块102，具体用于连接数字信号接口单元101和光电模块102中的模拟均衡器103。可选地，图9所示的高速无源部件107或者高速无源部件207可以仅包括该高速接插件01。
可选地，如图10中的(c)所示，该光电模块102自身可以包括一段光纤04，该光纤04可以与光电模块102中的光电转换单元104(即第一光电转换器105和第二光电转换器106)连接，用于输入/输出光信号，例如可以用于发送上述第一光信号，或者用于接收上述第二光信号。可选地，该光纤04可以为空芯光纤或者实芯光纤转空芯光纤，相应的，光纤30可以为空芯光纤(或者说至少包括一段空芯光纤)。
可选地，如图10中的(c)所示，该光纤04可以在通信设备10的面板上通过空芯光纤连接器05与光纤30连接。其中，空芯光纤连接器05可以用于在光纤04和光纤30之间输入/输出光信号，例如，可以用于从光纤04接收上述第一光信号，并发送该第一光信号至光纤30，或者从光纤30接收上述第二光信号，并发送该第二光信号至光纤04。如此，基于通信设备10内增设的光纤04和空芯光纤连接器05，可以为光信号在设备内外的传输提供低损耗、高速率的传输通道，从而进一步降低传输损耗，保证信号质量，并降低传输时延。
综上，仍以通信设备10向通信设备20发送信号为例，如图10中的(c)所示，数字信号接口单元101输出的高速电信号依次经过PCB、高速接插件01、光电模块102。在光电模块102中，经过模拟信号均衡处理和电光转换后，输出的光信号依次经过光纤04、空芯光纤连接器05和光纤30。随后，经过光纤30的传输，光纤30输出光信号至通信设备20中的光电模块202。可选地，通信设备20中也可以包括空芯光纤连接器和一段空芯光纤或者实芯光纤转空芯光纤，如此，光纤30输出的光信号可以依次经由空芯光纤连接器和一段空芯光纤或者实芯光纤转空芯光纤输入至光电模块202。然后，在光电模块202中经过光电转换和模拟信号均衡处理后，输出相应的高速电信号并依次经过通信设备20中的高速接插件01、PCB，最后输入到数字信号接口单元201。
如图10中的(d)所示，该通信设备10具体可以包括数字信号接口单元101、高速接插件01、光电模块102、光纤04和空芯光纤连接器05。
可选地，数字信号接口单元101可以包含于某个集成电路芯片内部(该集成电路芯片可以是未封装的)，如图10中的(d)所示，该集成电路芯片可以部署在基板(substrate)上，该基板可以部署在PCB上。如图10中的(d)所示，基板可以基于若干个焊接点焊接在该基板上。
可选地，高速接插件01可以部署在该基板上距离该数字信号接口单元101较近(或者说距离该集成电路芯片较近)的位置。
可选地，有关图10中的(d)的介绍可以参考上述图10中的(c)的描述，此处不再进行赘述。
综上，仍以通信设备10向通信设备20发送信号为例，如图10中的(d)所示，数字信号接口单元101输出的高速电信号依次经过基板、高速接插件01、光电模块102。在光电模块102中，经过模拟信号均衡处理和电光转换后，输出的光信号依次经过光纤04、空芯光纤连接器05和光纤30。随后，经过光纤30的传输，光纤30输出光信号至通信设备20中的光电模块202。可选地，通信设备20中也可以包括空芯光纤连接器和一段空芯光纤或者实芯光纤转空芯光纤，如此，光纤30输出的光信号可以依次经由空芯光纤连接器、一段空芯光纤或者一段实芯光纤转空芯光纤输入至光电模块202。然后，在光电模块202中经过光电转换和模拟信号均衡处理后，输出相应的高速电信号并依次经过通信设备20中的高速接插件01、基板，最后输入到数字信号接口单元201。
请参阅如下所示的表2，并结合前述图5、图9和图10对应的实施例可知，本申请实施例在采用高速无源部件、模拟均衡以及空芯光纤的情况下，信号的传输时延显著下降。如下表2所示，本申请图9所示实施例中的通信设备10与通信设备20之间的传输总时延仅为175ns，而图5所示实施例中的节点C和节点D之间的传输时延长达450ns，本申请实施例的信号传输时延仅为现有技术的39％。具体差异如下：
(1)本申请实施例采用高速无源部件组合替代原有的中继CDR，用于连接数字信号接口单元和光电模块，从而节省了约100ns时延；
(2)本申请实施例采用模拟均衡器替代原有的CDR，避免了复杂的数字逻辑处理和串并转换等，从而节省了约100ns时延；
(3)本申请实施例采用空芯光纤替代原有的实芯光纤(SMF和MMF等)做为通信设备(或者说节点)之间的传输通道。例如，以长度均为50m的光纤传输为例，本申请实施例节省了约75ns时延。
具体时延以及比值可参阅如下表2中的内容，此处不再详述。
表2
Figure PCTCN2021107037-appb-000002
进一步地，如上所述，为了克服器件与信道(即信号在设备间传输过程中经过的通道)的不平坦特性带来的信号畸变，需要在必要的地方(例如数字信号接口单元101和光电转换 单元104之间)增加均衡器予以消除，以补偿器件和信道带来的不平坦变化，从而达到减少信号畸变的目的。本申请实施例中采用的模拟均衡器主要是校正传输信号的幅度、频率特性和相位频率特性等。可选地，可以针对幅度均衡器和相位均衡器进行分析与设计，以获得本申请实施例中的模拟均衡器。其中，模拟均衡器的设计指标可以主要涉及均衡带宽、均衡量等，本申请实施例对此不作具体限定。
基于此，请参阅图11，图11是本申请实施例提供的一种模拟均衡器的结构示意图。如图11所示，以图7、图8或者图9所示的通信设备10中的模拟均衡器103为例，模拟均衡器103可以包括发送均衡器103a和接收均衡器103b。如图11所示，发送均衡器103a可以包括依次串联的输入放大电路1030、连续时间线性模拟均衡器(continuous time linear equalizer，CTLE)1031、低频模拟均衡器(low frequency equalizer，LFEQ)1032、电平失配补偿电路1033、输出放大电路1034。相应的，如图11所示，接收均衡器103b可以包括依次串联的输入放大电路1035、连续时间线性模拟均衡器1036、低频模拟均衡器1037、电平失配补偿电路1038、输出放大电路1039。可选地，图11所示的模拟均衡器的结构还可以应用于通信设备20内的模拟均衡器203，或者其他任意一个通信设备的模拟均衡器中。
首先，以发送均衡器103a为例，对模拟均衡器103执行模拟信号均衡处理的过程进行详细阐述。
其中，输入放大电路1030的输入端可以与数字信号接口单元101连接(或者与高速无源部件107连接)，用于接收数字信号接口单元101输出的高速电信号(例如第一电信号)，对该第一电信号进行放大，得到第一电信号-A，并发送该第一电信号-A出至连续时间线性模拟均衡器1031。
连续时间线性模拟均衡器1031，用于接收第一电信号-A，并补偿该第一电信号-A的高频部分(或者说高频分量)的信号传输损耗，以降低该第一电信号-A的高频部分的码间干扰，得到第一电信号-B，然后发送该第一电信号-B至低频模拟均衡器1032。请参阅图12，图12是本申请实施例提供的一种CTLE的电路结构以及增益曲线调节示意图。如图12所示，可以通过调节CTLE电路中的Rs1(串联等效电路)和Cs1(串联等效电容)来调节峰值，针对性地进行频率补偿以实现较平坦的增益曲线(也即调节电信号的幅频特性)。应理解，图12所示的电路结构仅为示意性举例，在一些可能的实施例中，CTLE电路可以包括比图12所示更多或者更少的部件，本申请实施例对此不作具体限定。
低频模拟均衡器1032，用于接收第一电信号-B，并补偿该第一电信号-B的低频部分(或者说低频分量)的信号传输损耗，以降低第一电信号-B的低频部分的码间干扰，得到第一电信号-C，然后发送该第一电信号-C至电平失配补偿电路1033。请参阅图13，图13是本申请实施例提供的一种LFEQ的电路结构示意图。如图13所示，LFEQ可以基于负反馈技术，调节信道低频损耗部分的斜率，还可以调节信号增益，实现对信号低频部分的均衡控制，从而降低信号低频部分的码间干扰。应理解，图13所示的电路结构仅为示意性举例，在一些可能的实施例中，LFEQ电路可以包括比图13所示更多或者更少的部件，本申请实施例对此不作具体限定。
电平失配补偿电路1033，可以包括判决反馈均衡器(decision feedback equalizer，DFE)，用于接收第一电信号-C，并通过DFE补偿该第一电信号-C的高频部分的信号传输损耗，以降低该第一电信号-C的高频部分的码间干扰，得到第一电信号-D，然后发送该第一电信号-D至 输出放大电路1034。可选地，请参阅图14，图14是本申请实施例提供的一组单比特响应曲线图。如图14中左侧的单比特响应(single bit response，SBR)曲线所示，在没有DFE进行钳制的情况下，信号经过信号传输损耗后，导致码间干扰变严重。如图14中右侧的单比特响应(single bit response，SBR)曲线所示，在经过3拍(tap)的DFE后，可以使得信号高频部分的码间干扰趋于零，这大大降低了信号高频部分的码间干扰，保证了信号质量。
输出放大电路1034的输出端可以与第一光电转换器105连接，用于接收第一电信号-D并进行放大，得到第二电信号，然后发送该第二电信号至第一光电转换器105。可选地，输出放大电路1034还可以包括前向反馈均衡器(feed forward equalizer，FFE)。如上所述，考虑到信号再后续传输过程中存在的损耗，还可以通过该FFE对该第一电信号-D进行预均衡处理，对该第一电信号-D的低频部分进行适当衰减，再得到第二电信号。如上所述，预均衡处理后可以保证后续其他设备接收到的电信号的高频部分和低频部分的幅度差异变小，也即保证其他设备接收到的电信号的码间干扰较小。
综上，请参阅图15，图15是本申请实施例提供的一种时域补偿范围示意图。如图15所示，连续时间线性模拟均衡器1031主要用于补偿电信号高频部分的损失，从而降低其高频部分的码间干扰；低频模拟均衡器1032主要用于补偿电信号低频部分的损失，从而降低其低频部分的码间干扰；电平失配补偿电路1033中的DEF主要用于补偿电信号高频部分的损失，从而降低其高频部分的码间干扰；输出放大电路1034中的FEF主要用于在向其他设备输出信号前，事先对信号的低频部分进行衰减，从而降低其他通信设备中的均衡器接收到的信号的码间干扰。如此，通过上述CTLE、LFEQ、DFE、FFE联合实现了全频带内的损耗补偿，从而降低信号的码间干扰(或者说降低了信道内的码间干扰)，提升信道传输的信噪比(signal noise ratio，SNR)，有效保证信号传输质量。
其次，由于发送均衡器103a和接收均衡器103b的结构相似，下面将结合图11所示的发送均衡器103b的结构对其执行模拟信号均衡处理的过程进行简单介绍。
第二光电转换器106输出的高速电信号(例如第三电信号)首先经由接收均衡器103b中的输入放大电路1035进行接收并放大，放大后的第三电信号再依次通过连续时间线性模拟均衡器1036、低频模拟均衡器1037、电平失配补偿电路1038，以分别对该第三电信号的高频部分以及低频部分进行补偿，降低其码间干扰，最后通过输出放大电路1039进行放大后输出质量更优、码间干扰更小的高速电信号(例如第四电信号)。
可选地，有关接收均衡器103b的详细介绍可以参考上述发送均衡器103a的描述，此处不再进行赘述。
应理解，图11所示的结构仅为示意性举例，在一些可能的实施例中，发送均衡器103a以及接收均衡器103b也可以仅包括图11中的部分器件或电路，例如，发送均衡器103a可以仅包括输入放大电路1030、连续时间线性模拟均衡器1031、电平失配补偿电路1033和输出放大电路1034；或者，发送均衡器103a可以仅包括输入放大电路1030、连续时间线性模拟均衡器1031和输出放大电路1034；或者，发送均衡器103a可以仅包括连续时间线性模拟均衡器1031、低频模拟均衡器1032、电平失配补偿电路1033。又例如，接收均衡器103b可以仅包括输入放大电路1035、电平失配补偿电路1038和输出放大电路1039；或者，接收均衡器103b可以仅包括连续时间线性模拟均衡器1036、低频模拟均衡器1037、电平失配补偿电 路1038，等等，本申请实施例对此不作具体限定。
结合图11所示的模拟均衡器103，下面将进一步对本申请实施例中的光电模块进行详细阐述。请参阅图16，图16是本申请实施例提供的一种光电模块的结构示意图。图16中以图8或者图9所示的通信设备10中的光电模块102为例，可以理解的是，图16所示的结构还可以应用于光电模块202或者其他任意一个通信设备内的光电模块内，此处不再进行赘述。如图16所示，光电模块102可以包括一个发送通道(transmitter，TX))和一个接收通道(receiver，RX)。具体地，如图16中的虚线框所示，TX可以包括发送均衡器103a以及第一光电转换器105，RX可以包括接收均衡器103b以及第二光电转换器106。下述实施例中提及的TX和RX均可以采用上述结构。如图16所示，光电模块102的一端用于进行电信号的输入/输出(例如输入第一电信号和输出第四电信号)，另一端用于进行光信号的输入/输出(例如输入第二光信号和输出第一光信号)，此处不再进行赘述。
请参阅图17，图17是本申请实施例提供的一组光电模块的结构示意图。如图17所示，在实际应用中，本申请实施例提供的一种光电模块可以是图17中的光电模块(a)、光电模块(b)、光电模块(c)、光电模块(d)、光电模块(e)、光电模块(f)等所示的各类结构，或者上述各种结构的组合，又或者还可以是其他任何可能的结构，本申请实施例对此不作具体限定。可选地，图17所示的光纤(例如包括光纤1、光纤2、光纤3和光纤4等)可以为空芯光纤。
如图17所示，光电模块(a)可以为发送模块，可以仅包括一个TX；光电模块(b)可以为接收模块，可以仅包括一个RX。如图17所示，光电模块(a)和光电模块(b)可以分别设置于两个通信设备中，并通过光纤连接，以实现信号从光电模块(a)到光电模块(b)的传输。
如图17所示，光电模块(c)可以为单通道收发模块，可以包括一个TX和一个RX。其中，TX与光纤1连接，用于将本设备的电信号转换成光信号并通过光纤1输出至其他设备。其中，RX与光纤2连接，用于通过光纤2接收其他设备发送的光信号并转换成电信号输入至本设备。
如图17所示，光电模块(d)可以为多通道并行模块，可以包括多个TX(例如TX1和TX2)和多个RX(例如RX1和RX2)。其中，TX1与光纤1连接，TX2与光纤2连接，可以用于并行地将两路电信号转换成对应的两路光信号并通过光纤1和光纤2输出至其他设备。其中，RX1与光纤3连接，RX2与光纤4连接，用于通过光纤3和光纤4并行地接收其他设备发送两路光信号并转换成对应的两路电信号输入至本设备。
如图17所示，光电模块(e)可以为单纤双向光电模块，可以包括一个TX、一个RX以及波分复用部件(wave division multiplexing，WDM)。其中，TX和RX分别与WDM连接，WDM再与光纤连接，使得TX发送的光信号和RX接收的光信号均可以通过WDM经由同一根光纤进行传输。
如图17所示，光电模块(f)可以为波分复用光电模块，可以包括多个TX例如TX1和TX2)、多个RX(例如RX1和RX2)和多个WDM(例如WDM1和WDM2)。其中，TX1和TX2分别与WDM1连接，WDM1再与光纤1连接，使得TX1和TX2并行输出的两路光信号可以通过WDM1进行合波后输入至光纤1，随后通过光纤1输出至其他设备。其中，RX1 和RX2分别与WDM2连接，WDM2再与光纤2连接，WDM2用于接收来自光纤2的合波信号并进行分波，分波后得到两路光信号分别输入至RX1和RX2。
进一步地，结合上述实施例中描述的光电模块，本申请实施例还提供了一种有源光缆。请参阅图18，图18是本申请实施例提供的一种有源光缆的结构示意图。如图18所示，有源光缆50可以包括两个光电模块(例如光电模块102和光电模块202)以及连接两个光电模块的空芯光纤107，其中，光电模块102和光电模块202可以与空芯光纤107的两端直接耦合(例如光电模块102可以与空芯光纤107的一端直接耦合，光电模块202可以与空芯光纤107的另一端直接耦合)，以减少甚至避免光电模块与光纤连接处的插入损耗。其中，光电模块102可以包括模拟均衡器103(例如包括发送均衡器103a和接收均衡器103b)、光电转换单元104(例如包括第一光电转换器105和第二光电转换器106)，此处不再进行赘述。其中，光电模块202可以包括模拟均衡器203(例如包括发送均衡器203a和接收均衡器203b)、光电转换单元204(例如包括第一光电转换器205和第二光电转换器206)，此处不再进行赘述。其中，空芯光纤107可以包括单根或者多根空芯光纤，每根空芯光纤可以为包括至少一段空芯光纤，等等，或者，在一些可能的实施例中，考虑到实际需求以及成本等也可以采用实芯光纤，本申请实施例对此不作具体限定。
请参阅图19，图19是本申请实施例提供的又一种通信系统的结构示意图。如图19所示，有源光缆50作为一个整体可以用于连接两个通信设备，例如，有源光缆50中的光电模块102可以与通信设备10中的高速无源部件107连接，有源光缆50中的光电模块202可以与通信设备20中的高速无源部件107连接，从而为通信设备10和通信设备20提供高速低时延的传输通道。有关通过有源光缆50进行信号传输的详细过程可以参考上述图8-图11对应实施例中的相关描述，此处不再进行赘述。
请一并参阅图18和图19，本申请实施例提供的一种高速低时延有源光缆(active optical cable，AOC)可以将两个光电模块通过一根或多根空芯光纤连接起来，封装耦合成一个整体部件，在实际使用中仅需要将有源光缆的两头插入到两台设备中，可以启到类似于网线的效果。显然，相较于前述光纤需要通过适配器与设备内的光电模块进行插接，操作复杂且带来额外的光链路损耗(即光纤两端与两个设备中的光电模块之间的插入损耗)的方案而言，本申请实施例提供的有源光缆内的两个光电模块可以与光纤直接耦合，有源光缆可以作为一个外部整体去连接两个设备，具有简单易用，插损低的好处。并且，在将光电模块整合到有源光缆内部后，通信设备10和通信设备20中仅包括电信号的传输，不再涉及光信号的转换，如此，可以大大提升通信设备内的信号传输效率，并降低通信设备的制造成本，与此同时，还可以通过光缆或者电缆的连接选择，使得通信设备可以适用于电通信或者光电通信等全方面的场景中。
结合图17所示的各类光电模块，以及图18和图19所示的有源光缆，本申请实施例还提供了相应的各类有源光缆。请参阅图20，图20是本申请实施例提供的一组有源光缆的结构示意图。如图20所示，在实际应用中，本申请实施例提供的一种光电模块可以是图20中的有源光缆(a)、有源光缆(b)、有源光缆(c)、有源光缆(d)所示的各类结构，或者可以是上述各种结构的组合，又或者还可以是其他任何可能的结构，本申请实施例对此不作具体限 定。
如图20所示，有源光缆(a)可以为单通道有源光缆，可以包括光电模块A和光电模块B，其中，光电模块A和光电模块B均包括单路TX和RX。具体地，如图20所示，在有源光缆(a)中，光电模块A包括TX-A和RX-A，光电模块B包括TX-B和RX-B。如图20所示，该有源光缆(a)还可以包括空芯光纤1和空芯光纤2，分别用于连接TX-A和RX-B，以及RX-A和TX-B。
如图20所示，在有源光缆(a)中，光电模块A中的TX-A输出的光信号可以通过空芯光纤1输入到光电模块B中的RX-B；光电模块B中的TX-B输出的光信号可以通过空芯光纤2输入到光电模块A中的RX-A，等等，此处不再详述。
如图20所示，有源光缆(b)可以为单纤双向有源光缆，可以包括光电模块A和光电模块B，其中，光电模块A和光电模块B中不仅包含单路TX和RX，还分别包括一个波分复用部件。具体地，如图20所示，在有源光缆(b)中，光电模块A包括TX-A、RX-A和WDM-A，光电模块B包括TX-B、RX-B和WDM-B。如图20所示，该有源光缆(b)还包括空芯光纤1，用于连接光电模块A和光电模块B，具体用于连接WDM-A和WDM-B。
如图20所示，在有源光缆(b)中，光电模块A的TX-A输出的光信号波长与光电模块B的TX-B输出的光信号波长一般不同，可以分别为λa和λb。
如图20所示，在有源光缆(b)中，光电模块A的TX-A输出的λa光信号通过WDM-A合波后输入空芯光纤1，随后，光电模块B的WDM-B接收来自空芯光纤1的λa光信号，分波后输入到光电模块B的RX-B。相应的，光电模块B的TX-B输出的λb光信号通过WDM-B合波后输入空芯光纤1，随后，光电模块A的WDM-A接收来自空芯光纤1的λb光信号，分波后输入到光电模块A的RX-A，等等，此处不再详述。
如图20所示，有源光缆(c)可以为多通道有源光缆，可以包括光电模块A和光电模块B，其中，光电模块A和光电模块B可以均包括四路TX和RX。具体地，如图20所示，在有源光缆(c)中，光电模块A包括TX-A1、TX-A2、TX-A3、TX-A4，以及RX-A1、RX-A2、RX-A3、RX-A4；光电模块B包括TX-B1、TX-B2、TX-B3、TX-B4，以及RX-B1、RX-B2、RX-B3、RX-B4。
如图20所示，该有源光缆(c)还包括八芯空芯光纤，具体包括空芯光纤1、空芯光纤2、空芯光纤3、空芯光纤4、空芯光纤5、空芯光纤6、空芯光纤7和空芯光纤8，分别用于连接TX-A1和RX-B1、TX-A2和RX-B2、TX-A3和RX-B3、TX-A4和RX-B4、RX-A1和TX-B1、RX-A2和TX-B2、RX-A3和TX-B3、RX-A4和TX-B4。
如图20所示，在有源光缆(c)中，光电模块A的TX-A1、TX-A2、TX-A3、TX-A4输出的光信号分别输入空芯光纤1、空芯光纤2、空芯光纤3、空芯光纤4，随后，光电模块B的RX-B1、RX-B2、RX-B3、RX-B4分别接收来自空芯光纤1、空芯光纤2、空芯光纤3、空芯光纤4的光信号。
相应的，在有源光缆(c)中，光电模块B的TX-B1、TX-B2、TX-B3、TX-B4输出的光信号分别输入空芯光纤5、空芯光纤6、空芯光纤7、空芯光纤8，随后，光电模块A的RX-A1、RX-A2、RX-A3、RX-A4分别接收来自空芯光纤5、空芯光纤6、空芯光纤7、空芯光纤8的光信号。
需要说明的是，如图20中的有源光缆(c)所示，是以4通道的多通道有源电缆为例，在实际应用中，该多通道有源电缆的通道数量可以是大于或者等于2的任何整数，本申请实施例对此不作具体限定，比如可以是2、4、6、8、16个通道等，相应的，所需的空芯光纤的芯数(或者说根数)可以是4、8、12、16、32。
如图20所示，有源光缆(d)可以为波分复用有源光缆，可以包括光电模块A和光电模块B，其中，光电模块A和光电模块B可以均包括四路TX和RX，以及TX方向WDM和RX方向WDM。具体地，如图20所示，在有源光缆(d)中，光电模块A包括TX-A1、TX-A2、TX-A3、TX-A4和WDM-TXA，以及RX-A1、RX-A2、RX-A3、RX-A4和WDM-RXA；光电模块B包括TX-B1、TX-B2、TX-B3、TX-B4和WDM-TXB，以及RX-B1、RX-B2、RX-B3、RX-B4和WDM-RXB。
如图20所示，该有源光缆(d)还包括空芯光纤1，用于连接光电模块A中的WDM-TXA和光电模块B中的WDM-RXB，以及空芯光纤2，用于连接光电模块A中的WDM-RXA和光电模块B中的WDM-TXB。
如图20所示，在有源光缆(d)中，光电模块A中四通道TX输出的光信号波长一般会不同，可以分别为λa1、λa2、λa3和λa4；相应的，光电模块B中四通道TX输出的光信号波长也会有所不同，可以分别为λb1、λb2、λb3和λb4。
如图20所示，在有源光缆(d)中，光电模块A的TX-A1、TX-A2、TX-A3和TX-A4各自输出的λa1光信号、λa2光信号、λa3光信号和λa4光信号通过WDM-TXA合波后输入空芯光纤1，随后，光电模块B的WDM-RXB接收来自空芯光纤1的合波光信号，分波后得到的λa1光信号、λa2光信号、λa3光信号和λa4光信号分别输入到光电模块B的RX-B1、RX-B2、RX-B3和RX-B4。
相应的，光电模块B的TX-B1、TX-B2、TX-B3和TX-B4各自输出的λb1光信号、λb2光信号、λb3光信号和λb4光信号通过WDM-TXB合波后输入空芯光纤2，随后，光电模块A的WDM-RXA接收来自空芯光纤2的合波光信号，分波后得到的λb1光信号、λb2光信号、λb3光信号和λb4光信号分别输入到光电模块A的RX-A1、RX-A2、RX-A3和RX-A4，等等，此处不再详述。
需要说明的是，如图20中的有源光缆(d)所示，是以4通道的波分复用有源电缆为例，在实际应用中，该波分复用有源光缆的通道数量可以是大于或者等于2的任何整数，比如4、6、8或者16个通道等，相应的，在空芯光纤1和空芯光纤2中传输的可以是4、6、8或者16波复用的光信号，等等，本申请实施例对此不作具体限定。例如，光电模块A的发送通道可以包括TX-A1、TX-A2、TX-A3、TX-A4、TX-A5、TX-A6、TX-A7和TX-A8，光电模块A的接收通道可以包括RX-A1、RX-A2、RX-A3、RX-A4、RX-A5、RX-A6、RX-A7和RX-A8，光电模块B同理，此处不再进行赘述。
结合图20中所示的有源光缆(d)，进一步地，请参阅图21，图21是本申请实施例提供的另一种有源光缆的结构示意图。如图21所示，该有源光缆(e)可以是多通道并行波分复用有源光缆，是一种更复杂的有源光缆结构。
如图21所示，有源光缆(e)包括光电模块A和光电模块B，其中，光电模块A和光电模块B内均包括两组如有源光缆(d)中的四通道波分复用。具体地，如图21所示，光电模 块A和光电模块B均包括8通道TX和8通道RX，以及相应的4个波分复用部件(例如WDM-TX1-A、WDM-TX2-A、WDM-RX1-A和WDM-RX2-A，以及WDM-TX1-B、WDM-TX2-B、WDM-RX1-B和WDM-RX2-B)。如图21所示，有源光缆(e)还可以包括空芯光纤1、空芯光纤2、空芯光纤3、空芯光纤4，分别用于连接WDM-TX1-A和WDM-RX1-B、WDM-TX2-A和WDM-RX2-B、WDM-RX1-A和WDM-TX1-B、WDM-RX2-A和WDM-TX2-B。具体地，有关有源光缆(e)的详细介绍可参考上述图20中对有源光缆(d)的描述，此处不再进行赘述。
可选地，如图21中的有源光缆(e)所示，是以2组4通道的并行波分复用有源光缆为例，在实际应用中，该多通道并行波分复用有源光缆的也可以是4组4通道的并行波分复用有源光缆，或者4组6通道的并行波分复用有源光缆，又或者6组2通道的并行波分复用有源光缆，等等，每组均可以通过两芯空芯光纤互连，本申请实施例对此不作具体限定。例如，以4组，每组4波长为例(也即4通道)，光电模块A和光电模块B内均可以包含：16通道TX和16通道RX，4个发送方向WDM，4个接收方向WDM，其中，每4个通道做一次波分复用/解复用，并通过8芯空芯光纤互连，等等，此处不再详述。
综上，本申请实施例提供了一种光电模块，通过在光电模块内采用模拟均衡器替代原有的CDR的方法，实现直接在模拟域对接收到的电信号进行均衡处理，降低信号的码间干扰，显然，采用模拟均衡器可以直接避免数字逻辑处理和多次串并转换等操作复杂、耗时长的过程，如此，在保证信号质量的同时，大大减少了信号在光电模块内的传输时延，进而减少了设备的计算等待时间，提升了整体的计算能力。
另外，本申请实施例还通过采用高速无源部件替代原有中继CDR的方法，在传输高速电信号的场景中，可以进一步减少了信号在数字信号接口单元至光电模块的信号传输损耗和信号传输时延。
另外，本申请实施例还通过采用空芯光纤替代原有实芯光纤的方法，进一步减少信号在光纤中的传输时延。如上所述，采用本申请实施例可以在保证信号传输质量的同时，最大化的缩短信号从一个设备传输到另一设备的传输时延，简言之，可以有效保证一个通信系统内的某一通信设备可以在极短的时间内接收到高质量的信号，从而可以极大程度上提升整个通信系统的计算能力。
进一步地，结合本申请实施例提供的光电模块，本申请实施例还提供了一种有源光缆，可以将两个光电模块分别与空芯光纤的两端直接耦合并封装成一个整体，如此，相较于原有技术中，光电模块位于通信设备内部，需要通过适配器才能与光纤连接，从而导致插损大的方案而言，本申请实施例提供的有源光缆可以很好的降低甚至避免光电模块与光纤之间的插损，相当于光信号的插损可以仅剩余光信号在光纤内部传输时产生的损耗，从而可以进一步保证信号传输时的质量。并且，在实际应用时，只需将有源光缆的两端分别接入两个通信设备，操作便捷。
请参阅图22，图22是本申请实施例提供的一种利用光电模块的通信方法的流程示意图。该通信方法可以应用于通信设备(例如通信设备10和通信设备20，如上述图6所述的交换机、服务器，内存资源池和存储资源池等中的任意一个)。该通信设备可以包括光电模块；所述光电模块包括模拟均衡器和光电转换单元；所述模拟均衡器与光电转换单元连接。可选地， 该通信方法可以应用于上述图6所述的系统架构或者类似的系统架构中，该通信方法可以包括以下步骤S301-步骤S302。
步骤S301，通过光电模块内的模拟均衡器，对第一电信号进行第一模拟信号均衡处理以得到第二电信号，并发送所述第二电信号至光电转换单元，或，通过所述模拟均衡器从所述光电转换单元接收第三电信号，对所述第三电信号进行第二模拟信号均衡处理以得到第四电信号；步骤S302，通过光电模块内的光电转换单元，从所述模拟均衡器接收所述第二电信号并将所述第二电信号转换为第一光信号，或，通过所述光电转换单元将第二光信号转换为所述第三电信号并向所述模拟均衡器发送所述第三电信号。
在一些可能的实施方式中，该方法具体可以包括：通过光电转换单元中的第一光电转换器，从所述模拟均衡器接收所述第二电信号并将所述第二电信号转换为所述第一光信号；通过模拟均衡器中的发送均衡器，对所述第一电信号进行所述第一模拟信号均衡处理以得到所述第二电信号，并发送所述第二电信号至所述第一光电转换器。
在一些可能的实施方式中，该方法具体可以包括：通过光电转换单元中的第二光电转换器，将所述第二光信号转换为所述第三电信号并向所述模拟均衡器发送所述第三电信号；通过模拟均衡器中的接收均衡器，从所述第二光电转换器接收所述第三电信号，对所述第三电信号进行所述第二模拟信号均衡处理以得到所述第四电信号。
可选地，该利用光电模块的通信方法具体可参考上述图7-图11对应实施例的描述，此处不再进行赘述。
可选地，本申请实施例中所描述的该利用光电模块的通信方法中的各方法流程具体可以基于件、硬件、或其结合的方式实现。其中，以硬件实现的方式可以包括逻辑电路、算法电路或模拟电路等。以软件实现的方式可以包括程序指令，可以被视为是一种软件产品，被存储于存储器中，并可以被处理器运行以实现相关功能。
本申请实施例还提供一种计算机可读存储介质，其中，该计算机可读存储介质可存储有程序，该程序被处理器执行时，使得所述处理器可以执行上述方法实施例中记载的任意一种的部分或全部步骤。
本申请实施例还提供一种计算机程序，该计算机程序包括指令，当该计算机程序被多核处理器执行时，使得所述处理器可以执行上述方法实施例中记载的任意一种的部分或全部步骤。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其它实施例的相关描述。需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可能可以采用其它顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到 另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以为个人计算机、服务器或者网络设备等，具体可以是计算机设备中的处理器)执行本申请各个实施例上述方法的全部或部分步骤。其中，而前述的存储介质可包括：U盘、移动硬盘、磁碟、光盘、只读存储器(read-only memory，ROM)、双倍速率同步动态随机存储器(double data rate，DDR)、闪存(flash)或者随机存取存储器(random access memory，RAM)等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (15)

  1. 一种光电模块，其特征在于，包括模拟均衡器和光电转换单元，所述模拟均衡器和所述光电转换单元连接；
    所述模拟均衡器，用于对第一电信号进行第一模拟信号均衡处理以得到第二电信号，并发送所述第二电信号至所述光电转换单元，或，用于从所述光电转换单元接收第三电信号，对所述第三电信号进行第二模拟信号均衡处理以得到第四电信号；
    所述光电转换单元，用于从所述模拟均衡器接收所述第二电信号并将所述第二电信号转换为第一光信号，或，用于将第二光信号转换为所述第三电信号并向所述模拟均衡器发送所述第三电信号。
  2. 根据权利要求1所述的光电模块，其特征在于，所述光电转换单元包括：第一光电转换器，用于从所述模拟均衡器接收所述第二电信号并将所述第二电信号转换为所述第一光信号；
    所述模拟均衡器包括：发送均衡器，用于对所述第一电信号进行所述第一模拟信号均衡处理以得到所述第二电信号，并发送所述第二电信号至所述第一光电转换器。
  3. 根据权利要求2所述的光电模块，其特征在于，所述发送均衡器包括第一连续时间线性均衡器CTLE、第一低频均衡器LFEQ、第一电平失配补偿电路中的至少一种。
  4. 根据权利要求3所述的光电模块，其特征在于，所述发送均衡器包括：串联的所述第一CTLE、所述第一LFEQ和所述第一电平失配补偿电路。
  5. 根据权利要求1-4任一项所述的光电模块，其特征在于，所述光电转换单元包括：第二光电转换器，用于将所述第二光信号转换为所述第三电信号并向所述模拟均衡器发送所述第三电信号；
    所述模拟均衡器包括：接收均衡器，用于从所述第二光电转换器接收所述第三电信号，对所述第三电信号进行所述第二模拟信号均衡处理以得到所述第四电信号。
  6. 根据权利要求5所述的光电模块，其特征在于，所述接收均衡器包括第二CTLE、第二LFEQ、第二电平失配补偿电路中的至少一种。
  7. 根据权利要求6所述的光电模块，其特征在于，所述接收均衡器包括：串联的所述第二CTLE、所述第二LFEQ和所述第二电平失配补偿电路。
  8. 一种通信设备，其特征在于，包括数字信号接口单元，以及如权利要求1-7任意一项所述的光电模块；
    所述数字信号接口单元，用于从处理设备接收第一数字电信号，将所述第一数字电信号转换为所述第一电信号，并发送所述第一电信号至所述模拟均衡器，或，用于从所述模拟均衡器接收所述第四电信号，将所述第四电信号转换为第二数字电信号，并发送所述第二数字 电信号至所述处理设备。
  9. 根据权利要求8所述的设备，其特征在于，所述设备还包括：高速无源部件，用于连接所述数字信号接口单元与所述模拟均衡器。
  10. 根据权利要求9所述的设备，其特征在于，所述高速无源部件包括第一高速接插件、第二高速接插件和高速电缆，所述第一高速接插件与所述第二高速接插件通过所述高速电缆连接；所述第一高速接插件与所述数字信号接口单元连接，所述第二高速接插件与所述模拟均衡器连接。
  11. 根据权利要求9所述的设备，其特征在于，所述高速无源部件包括第一高速接插件，所述第一高速接插件连接在所述数字信号接口单元与所述模拟均衡器之间；
    所述设备还包括：第一空芯光纤和空芯光纤连接器；
    所述第一空芯光纤与所述光电转换单元连接，用于发送所述第一光信号或接收所述第二光信号；
    所述空芯光纤连接器，用于将所述第一光信号发送至第二空芯光纤或从所述第二空芯光纤接收所述第二光信号。
  12. 一种有源光缆，其特征在于，包括至少两个如权利要求1-7任一项所述的光电模块，以及空芯光纤；所述至少两个光电模块通过所述空芯光纤连接。
  13. 一种通信系统，其特征在于，包括多个通信设备，所述多个通信设备之间通过如权利要求12所述的有源光缆连接。
  14. 根据权利要求13所述的通信系统，其特征在于，所述多个通信设备包括至少一个如权利要求8至11中任一项所述的设备。
  15. 一种利用光电模块的通信方法，其特征在于，包括：
    通过所述光电模块内的模拟均衡器，对第一电信号进行第一模拟信号均衡处理以得到第二电信号，并发送所述第二电信号至光电转换单元，或，通过所述模拟均衡器从所述光电转换单元接收第三电信号，对所述第三电信号进行第二模拟信号均衡处理以得到第四电信号；
    通过所述光电模块内的所述光电转换单元，从所述模拟均衡器接收所述第二电信号并将所述第二电信号转换为第一光信号，或，通过所述光电转换单元将第二光信号转换为所述第三电信号并向所述模拟均衡器发送所述第三电信号。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117375538A (zh) * 2023-10-09 2024-01-09 新港海岸(北京)科技有限公司 一种衰减补偿方法和衰减补偿电路
WO2024198138A1 (zh) * 2023-03-31 2024-10-03 昂纳科技(深圳)集团股份有限公司 一种无线通信系统
WO2025228122A1 (zh) * 2024-04-28 2025-11-06 华为技术有限公司 一种光设备、单板以及光网络
CN120957045A (zh) * 2025-10-15 2025-11-14 摩尔线程智能科技(北京)股份有限公司 计算系统及互联方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250141583A1 (en) * 2023-10-25 2025-05-01 Cisco Technology, Inc. Monitor channel for multiple transmission channels

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101662326A (zh) * 2008-08-28 2010-03-03 华为技术有限公司 一种光信号电均衡处理方法、装置和光纤通信系统
WO2012075902A1 (zh) * 2010-12-10 2012-06-14 华为技术有限公司 一种检测光信噪比的方法和装置
CN106961309A (zh) * 2017-05-31 2017-07-18 中国科学技术大学 一种可见光通信收发器与可见光通信系统
CN109218235A (zh) * 2018-09-21 2019-01-15 武汉邮电科学研究院有限公司 基于预均衡正交双二进制的光信号的传输方法及系统
CN113067786A (zh) * 2020-01-02 2021-07-02 上海诺基亚贝尔股份有限公司 用于均衡信号的设备、方法、装置及计算机可读介质

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9306780B2 (en) * 2013-03-11 2016-04-05 Semtech Corporation Optical transmission for binary and duobinary modulation formats
US10298330B2 (en) * 2016-03-30 2019-05-21 Finisar Corporation Host-equalized optical inks
CN111224718B (zh) * 2018-11-23 2023-06-20 阿里巴巴集团控股有限公司 光模块以及光模块信号处理方法
KR102665186B1 (ko) * 2019-09-05 2024-05-10 주식회사 퀄리타스반도체 단방향 ａｏｃ 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101662326A (zh) * 2008-08-28 2010-03-03 华为技术有限公司 一种光信号电均衡处理方法、装置和光纤通信系统
WO2012075902A1 (zh) * 2010-12-10 2012-06-14 华为技术有限公司 一种检测光信噪比的方法和装置
CN106961309A (zh) * 2017-05-31 2017-07-18 中国科学技术大学 一种可见光通信收发器与可见光通信系统
CN109218235A (zh) * 2018-09-21 2019-01-15 武汉邮电科学研究院有限公司 基于预均衡正交双二进制的光信号的传输方法及系统
CN113067786A (zh) * 2020-01-02 2021-07-02 上海诺基亚贝尔股份有限公司 用于均衡信号的设备、方法、装置及计算机可读介质

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4358438A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024198138A1 (zh) * 2023-03-31 2024-10-03 昂纳科技(深圳)集团股份有限公司 一种无线通信系统
CN117375538A (zh) * 2023-10-09 2024-01-09 新港海岸(北京)科技有限公司 一种衰减补偿方法和衰减补偿电路
WO2025228122A1 (zh) * 2024-04-28 2025-11-06 华为技术有限公司 一种光设备、单板以及光网络
CN120957045A (zh) * 2025-10-15 2025-11-14 摩尔线程智能科技(北京)股份有限公司 计算系统及互联方法

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