WO2023011275A1 - 显示面板和电子设备 - Google Patents

显示面板和电子设备 Download PDF

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Publication number
WO2023011275A1
WO2023011275A1 PCT/CN2022/108154 CN2022108154W WO2023011275A1 WO 2023011275 A1 WO2023011275 A1 WO 2023011275A1 CN 2022108154 W CN2022108154 W CN 2022108154W WO 2023011275 A1 WO2023011275 A1 WO 2023011275A1
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WIPO (PCT)
Prior art keywords
layer
substrate
display panel
shielding
shielding structure
Prior art date
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Ceased
Application number
PCT/CN2022/108154
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English (en)
French (fr)
Inventor
唐涛
方建平
李旭
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP22851989.8A priority Critical patent/EP4358116A4/en
Publication of WO2023011275A1 publication Critical patent/WO2023011275A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application belongs to the field of display technology, and more specifically relates to a display panel and electronic equipment.
  • OLED Organic Light Emitting Diode
  • the present application provides a display panel and an electronic device to solve the problem of poor display under the action of an external electric field and improve the reliability of display performance.
  • an embodiment of the present application provides a display panel, and the display panel includes:
  • the display layer is located on one side of the substrate; the display layer includes a plurality of light emitting devices, and each light emitting device includes a stacked first electrode, a light emitting layer and a second electrode; a plurality of first electrodes are connected to each other to form a first electrode layer, The first electrode layer extends from the display area to the non-display area;
  • the array layer is located between the substrate and the display layer; the array layer includes peripheral circuits located in the non-display area;
  • the shielding structure is located in the non-display area; the orthographic projection of the shielding structure on the substrate overlaps with the orthographic projection of the first electrode layer on the substrate; and, the orthographic projection of the shielding structure on the substrate is a first projection, the first The orthographic projection of the part of the electrode layer located in the non-display area on the substrate is the second projection, and the set of the first projection and the second projection covers the orthographic projection of the peripheral circuit on the substrate.
  • the peripheral circuit includes a gate driving circuit, and the set of the first projection and the second projection covers an orthographic projection of the gate driving circuit on the substrate.
  • the peripheral circuit includes a gate driving circuit and a light emitting driving circuit, and the set of the first projection and the second projection covers the orthographic projection of the gate driving circuit and the light emitting driving circuit on the substrate.
  • the display panel provided by the embodiment of the present application is provided with a shielding structure in the non-display area, and the orthographic projection of the shielding structure on the substrate overlaps with the part of the first electrode layer in the non-display area on the orthographic projection of the substrate.
  • a certain voltage is usually applied to the first electrode layer, and after a certain voltage is also connected to the shielding structure, it is equivalent to lengthening the structure with a constant voltage potential in the non-display area towards the edge of the display panel. , the shielding structure will have a greater impact on the potential at the edge of the display panel.
  • the shielding structure can be used to dissipate the display panel after a certain voltage is connected.
  • the charge on the edge prevents the electrostatic charge from affecting the channel of the transistor in the peripheral circuit.
  • the shielding structure in the embodiment of the present application can serve as an electrostatic shielding function, reducing the risk of circuit failure caused by characteristic deviation of transistors in peripheral circuits due to static electricity, thereby reducing the risk of poor display under the action of an external electric field.
  • the peripheral circuit includes a plurality of transistors, and the transistor includes a channel; the shielding structure is located on a side of the channel away from the substrate. In the embodiment of the present application, the shielding structure is arranged on the side of the channel away from the substrate.
  • the shielding structure is located on the same layer as the second electrode.
  • the shielding structure includes a first shielding layer and a second shielding layer; the orthographic projection of the end of the first shielding layer close to the display area on the substrate overlaps with the orthographic projection of the first electrode layer on the substrate ; The orthographic projection of the end of the first shielding layer away from the display area on the substrate overlaps with the orthographic projection of the second shielding layer on the substrate, and the first shielding layer and the second shielding layer are connected through via holes.
  • the two shielding layers together form a shielding structure, and the second shielding layer is farther away from the display area than the first shielding layer.
  • the first shielding layer is located on the same layer as the second electrode, and the second shielding layer is located in the metal layer closest to the display layer in the array layer.
  • both the first shielding layer and the second shielding layer are manufactured by reusing the original film layers in the display panel, and no new process is added.
  • the first shielding layer is set to overlap the edge of the first electrode layer, and the first shielding layer extends away from the display area and then overlaps and is electrically connected to the second shielding layer located in the array layer.
  • the first shielding layer and the second electrode are located on the same layer, so the setting of the first shielding layer will not affect the normal circuit wiring in the array layer.
  • the shielding structure is located on a side of the trench near the substrate.
  • the charge induced by the back film material can be evacuated by the shielding structure, thereby blocking the conduction of static electricity to the film layer where the channel is located, so as to prevent static electricity from affecting the characteristics of transistors in peripheral circuits.
  • the display panel further includes a light-shielding layer located in the display area, and the shielding structure and the light-shielding layer are located on the same layer.
  • the shielding structure and the light-shielding layer can be manufactured in the same process, and the manufacturing of the shielding structure does not add a new process, and the process is simple.
  • the display panel also includes voltage terminals located in the non-display area, and the shielding structure is electrically connected to the voltage terminals.
  • the voltage terminal is multiplexed as a ground terminal or multiplexed as a voltage terminal for supplying voltage to the first electrode layer.
  • the embodiment of the present application further provides an electronic device, including the display panel provided in any embodiment of the present application.
  • the display panel and electronic equipment provided by the present application have the following beneficial effects: a shielding structure is provided in the non-display area of the display panel, and the orthographic projection of the shielding structure on the substrate and the part of the first electrode layer in the non-display area are on the substrate The orthographic projections of are partially overlapping.
  • a certain voltage is usually applied to the first electrode layer, and after a certain voltage is also connected to the shielding structure, it is equivalent to lengthening the structure with a constant voltage potential in the non-display area towards the edge of the display panel. , the shielding structure will have a greater impact on the potential at the edge of the display panel.
  • the shielding structure can be used to dissipate the display panel after a certain voltage is connected.
  • the charge on the edge prevents the electrostatic charge from affecting the channel of the transistor in the peripheral circuit.
  • the shielding structure in the embodiment of the present application can serve as an electrostatic shielding function, reducing the risk of circuit failure caused by characteristic deviation of transistors in peripheral circuits due to static electricity, thereby reducing the risk of poor display under the action of an external electric field.
  • FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present application.
  • Fig. 2 is a schematic cross-sectional view at the position of tangent line A-A' in Fig. 1;
  • FIG. 3 is a partially simplified schematic diagram of another display panel provided by an embodiment of the present application.
  • FIG. 4 is a partially simplified schematic diagram of another display panel provided by an embodiment of the present application.
  • Fig. 5 is another schematic cross-sectional view at the position of tangent line A-A' in Fig. 1;
  • Fig. 6 is another schematic cross-sectional view at the position of tangent line A-A' in Fig. 1;
  • Fig. 7 is another schematic cross-sectional view at the position of tangent line A-A' in Fig. 1;
  • FIG. 8 is a schematic top view of another display panel provided by the embodiment of the present application.
  • FIG. 9 is a schematic top view of another display panel provided by an embodiment of the present application.
  • FIG. 10 is a schematic partial top view of another display panel provided by the embodiment of the present application.
  • Fig. 11 is another schematic cross-sectional view at the position of tangent line A-A' in Fig. 1;
  • FIG. 12 is a schematic diagram of an electronic device provided by an embodiment of the present application.
  • an anti-fingerprint coating is provided on the surface of the display panel.
  • the anti-fingerprint coating contains a relatively high concentration of fluorine, which leads to the accumulation of negative charges due to friction during the use of electronic products, which in turn makes the back of the display panel.
  • the mask material induces an electric charge.
  • the film layer where the transistor channel is located is relatively close to the back film material, the charge in the back film material will cause the characteristics of the transistor in the peripheral circuit to shift, which will affect the driving performance of the peripheral circuit to the light-emitting diode, resulting in display failure.
  • an embodiment of the present application provides a display panel, in which a shielding structure is provided in a non-display area, and the shielding structure is used to dissipate electrostatic charges, so as to solve the problem of failure of peripheral circuits caused by static electricity not being dissipated in time.
  • FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional diagram at the position of tangent line A-A' in FIG. 1 .
  • the display panel includes a display area 1 and a non-display area 2 around the display area 1, a binding area 3 is also arranged in the non-display area 2, and a plurality of connection terminals are arranged in the binding area 3 (Fig. 1 not shown).
  • a driver chip is provided on the non-display area 2 of the display panel, and the connection terminals are connected to the pins on the driver chip in a one-to-one correspondence.
  • a flexible circuit board is fixed on the non-display area 2 of the display panel, and the connection terminals are connected to the pins on the flexible circuit board in one-to-one correspondence.
  • the display panel includes a substrate 10 , an array layer 20 and a display layer 30 .
  • the substrate 10 is a flexible substrate, such as a PI (polyimide) substrate.
  • the display layer 30 is located on one side of the substrate 10 .
  • the display layer 30 may include a pixel definition layer 31 and a plurality of light emitting devices 32, and each light emitting device 32 includes a stacked first electrode 321, a light emitting layer 322 and a second electrode 323, wherein the first electrode 321 is located at the edge of the second electrode 323 away from the side of the substrate 10.
  • the light emitting device 32 is an organic light emitting diode; in another embodiment, the light emitting device 32 is an inorganic light emitting diode.
  • a plurality of first electrodes 321 are interconnected to form a first electrode layer 34 , and the first electrode layer 34 extends from the display area 1 to the non-display area 2 .
  • the first electrode layer 34 is a whole layer structure covering the display area 1 and extending to the non-display area 2 , wherein the first electrode layer 34 is equivalent to a common electrode layer.
  • the first electrode 321 is a cathode
  • the second electrode 323 is an anode
  • the first electrode layer 34 is a cathode layer.
  • the array layer 20 is located between the substrate 10 and the display layer 30 .
  • the array layer 20 includes a peripheral circuit 21 located in the non-display area 2 and a pixel circuit 22 located in the display area 1 .
  • the pixel circuit 22 is electrically connected to the light emitting device 32 .
  • the output terminal of the pixel circuit 22 is electrically connected to the second electrode 323 of the light emitting device 32 .
  • the pixel circuit 22 provides a voltage signal to the second electrode 323 and at the same time applies a common voltage signal to the first electrode 321 , so that the light emitting device 32 emits light under the control of the first electrode 321 and the second electrode 323 .
  • the pixel circuit 22 in FIG. 2 is only for simplified illustration.
  • the peripheral circuit 21 includes a plurality of transistors 23 , the transistor 23 includes a channel 24 , and the transistor 23 includes a gate, a source and a drain, wherein the conductive semiconductor between the source and the drain is the channel 24 .
  • the array layer 20 may further include a semiconductor layer 25 on the substrate 10 , and the channel 24 is located on the semiconductor layer 25 .
  • the working cycle of the pixel circuit 22 includes at least a data writing phase and a light-emitting phase.
  • the data writing phase the data signal provided on the data line is written into the gate of the driving transistor in the pixel circuit 22;
  • the drive current is generated under the control of the gate voltage.
  • the peripheral circuit 21 may also include a gate drive circuit, the gate drive circuit includes a plurality of cascaded first shift registers, the display panel further includes a plurality of scan lines, and the scan lines are connected to the first shift registers.
  • the output terminal of the register is electrically connected, and the pixel circuit 22 includes a scanning control terminal, and the scanning control terminal is electrically connected to the scanning line.
  • the cascaded multiple first shift registers sequentially provide scan signals to multiple scan lines, and then input scan signals to the scan control terminal through the scan lines to control the pixel circuit 22 to work in the data writing phase.
  • the peripheral circuit 21 further includes a gate drive circuit and a light-emitting drive circuit
  • the light-emitting drive circuit includes a plurality of second shift registers cascaded
  • the display panel further includes a plurality of light-emitting control lines
  • the light-emitting control lines It is electrically connected to the output end of the second shift register
  • the pixel circuit 22 also includes a light emission control end, which is electrically connected to the light emission control line.
  • the cascaded multiple second shift registers sequentially provide light-emitting control signals to multiple light-emitting control lines, and then provide the light-emitting control signals to the light-emitting control terminal through the light-emitting control lines to control the pixel circuit 22 to work in the light-emitting stage.
  • the output terminal of the pixel circuit 22 provides a voltage signal to the second electrode 323 .
  • the display panel may further include an encapsulation layer 50 for encapsulating and protecting the light emitting device 32 .
  • the encapsulation layer 50 may include a stacked first inorganic layer 51 , an organic layer 52 and a second inorganic layer 53 .
  • Fig. 2 also shows the barrier wall 33 located in the non-display area 2, the barrier wall 33 is used to limit the edge of the encapsulation layer 50, and can prevent the edge crack of the encapsulation layer 50 from propagating to the display area.
  • structures such as crack detection lines and crack retaining walls may also be provided in the non-display area 2 . Wherein, the crack detection line is used to detect cracks in the non-display area before the display panel leaves the factory. The crack retaining wall is used to stop the cracks in the non-display area 2, preventing the cracks from extending to the display area 1.
  • the display panel may further include a shielding structure 40 located in the non-display area 2 . It can be seen from the position of the area Q circled in FIG. 2 that, in the direction e perpendicular to the plane of the substrate 10 , the shielding structure 40 at least partially overlaps the edge of the first electrode layer 34 .
  • FIG. 2 shows a direction e perpendicular to the substrate 10 . It can be understood that the direction e perpendicular to the plane of the substrate 10 is the same as the projection direction of the orthographic projection onto the substrate 10 .
  • the shielding structure 40 overlaps the edge of the first electrode layer 34 , that is, the orthographic projection of the shielding structure 40 on the substrate 10 partially coincides with the orthographic projection of the first electrode layer 34 on the substrate 10 .
  • the position of the peripheral circuit 21 is simplified in FIG. 2 , the orthographic projection of the shielding structure 40 on the substrate 10 is the first projection, and the orthographic projection of the first electrode layer 34 on the substrate 10 in the non-display area 2 is the second projection. , it can be seen that the set of the first projection and the second projection covers the orthographic projection of the peripheral circuit 21 on the substrate 10 .
  • FIG. 3 is a partial simplified schematic diagram of another display panel provided by the embodiment of the present application.
  • the gate driving circuit 211 includes a plurality of first shift registers 71 connected in cascade
  • the light-emitting driving circuit 212 includes a plurality of second shift registers 72 connected in cascade.
  • the pixel circuit 22 is connected to the first shift register 71 through the scan line 73
  • the pixel circuit 22 is also connected to the second shift register 72 through the light emission control line 74 .
  • the first electrode layer 34 extends from the display area 1 to the non-display area 2 .
  • the combination of the orthographic projection of the shielding structure 40 on the substrate 10 and the orthographic projection of the portion of the first electrode layer 34 located in the non-display area 2 on the substrate covers the orthographic projection of the gate driving circuit 211 on the substrate 10 .
  • FIG. 4 is a partially simplified schematic diagram of another display panel provided in the embodiment of the present application. As shown in FIG. A collection of the orthographic projections of the non-display area 2 on the substrate, the orthographic projection of the covering gate driving circuit 211 on the substrate 10 , and the orthographic projection of the light-emitting driving circuit 212 on the substrate 10 .
  • the display panel provided by the above embodiments of the present application is provided with a shielding structure 40 in the non-display area, and the orthographic projection of the shielding structure 40 on the substrate 10 is perpendicular to the orthographic projection of the part of the first electrode layer 34 in the non-display area 2 on the substrate 10. stack.
  • the shielding structure 40 When the display panel is displayed, a certain voltage is usually applied to the first electrode layer 34, and after a certain voltage is also connected to the shielding structure 40 (wherein, the shielding structure 40 can be grounded, or the shielding structure 40 and the first electrode layer 34 can be arranged connected to the same voltage signal), which is equivalent to lengthening the structure with a constant voltage potential in the non-display area 2 toward the edge of the display panel, and the shielding structure 40 will have a greater impact on the potential of the edge of the display panel.
  • the shielding structure 40 is connected to a certain voltage Afterwards, it can be used to dissipate the charge on the edge of the display panel to prevent the electrostatic charge from affecting the channel of the transistor in the peripheral circuit 21 .
  • the shielding structure 40 can serve as an electrostatic shielding function, reducing the risk of circuit failure caused by characteristic deviation of transistors in peripheral circuits due to static electricity, thereby reducing the risk of poor display under the action of an external electric field.
  • the shielding structure 40 may be located between the substrate 10 and the first electrode layer 34 . Then the shielding structure 40 is manufactured before the process of the encapsulation layer 50 of the display panel, and the shielding structure 40 can be manufactured by reusing the process in the array layer 20 or the display layer 30 . Moreover, the voltage terminal for supplying voltage to the shielding structure 40 is generally arranged on the array layer 20, the shielding structure 40 is arranged between the substrate 10 and the first electrode layer 34, and the connection between the shielding structure 40 and the voltage terminal for supplying the voltage thereto Easier to implement.
  • a polarizing layer, a protective layer, an anti-fingerprint layer, an anti-glare layer and other film layers may also be disposed on the encapsulation layer 50 .
  • the shielding structure 40 is located on a side of the trench 24 away from the substrate 10 .
  • negative charges will be generated on the side of the display surface of the display panel due to friction, wherein the display surface is also the light-emitting surface.
  • the negative electricity generated on the side of the display surface will in turn lead to the induction of charges on the back film of the display panel.
  • the channel of the transistor is closer to the substrate 10 (that is, the back side of the display panel) than other circuit structures.
  • the electrostatic charge generated by the panel When the electrostatic charge generated by the panel is conducted from the display facing the back film material, it is first evacuated by the shielding structure 40 after being transmitted to the shielding structure 40, thereby blocking the conduction of the static electricity to the back film material, so as to prevent static electricity from affecting the transistor characteristics in the peripheral circuit. make an impact.
  • the shielding structure 40 includes a first shielding layer 41 and a second shielding layer 42; in the direction e perpendicular to the plane where the substrate 10 is located, one end of the first shielding layer 41 close to the display area 1 is connected to the first shielding layer 41. Edges of the electrode layer 34 overlap; an end of the first shielding layer 41 away from the display area 1 overlaps the second shielding layer 42 .
  • the orthographic projection of the end of the first shielding layer 41 close to the display area 1 on the substrate 10 overlaps the orthographic projection of the first electrode layer 34 on the substrate 10, and the end of the first shielding layer 41 far away from the display area 1
  • the orthographic projection of one end on the substrate 10 overlaps with the orthographic projection of the second shielding layer 42 on the substrate 10 .
  • the first shielding layer 41 is connected to the second shielding layer 42 through via holes. After a certain voltage is applied to the shielding structure 40 , the first shielding layer 41 and the second shielding layer 42 have the same potential.
  • the two shielding layers together form the shielding structure 40
  • the second shielding layer 42 is farther away from the display area 1 than the first shielding layer 41 .
  • the first shielding layer 41 is located on the same layer as the second electrode 323
  • the second shielding layer 42 is located in the metal layer closest to the display layer 30 in the array layer 20 .
  • both the first shielding layer 41 and the second shielding layer 42 are manufactured by reusing the original film layers in the display panel, and no new process is added.
  • the non-display area 2 is provided with structures such as a common voltage bus and peripheral circuits 21 .
  • the metal layer in the array layer 20 is used to make the pixel circuit in the display area 1 , and is also used to make the peripheral circuit in the non-display area 2 .
  • the common voltage bus is electrically connected to the first electrode layer 34 for providing voltage signals to the first electrode layer 34 .
  • the shielding structure 40 made of the metal layer may affect the normal wiring in the non-display area 2 .
  • the first shielding layer 41 is set to overlap the edge of the first electrode layer 34 , and the first shielding layer 41 extends away from the display area 1 and then connects with the second shielding layer 42 located in the array layer 20 overlapping and electrically connected. The setting of the first shielding layer 41 will not affect the normal circuit wiring in the array layer 20 .
  • the display panel includes a semiconductor layer 25 , a first metal layer 26 , a second metal layer 27 , a third metal layer 28 and a first metal layer 25 located on the substrate 10 and away from the substrate 10 in sequence.
  • Four metal layers 29 .
  • the fourth metal layer 29 is the closest metal layer to the display layer 30 in this embodiment.
  • the second shielding layer 42 is located in the fourth metal layer 29 .
  • the pixel circuit 22 may further include a storage capacitor. As shown in FIG. 2 , one plate of the storage capacitor 80 is located on the first metal layer 26 , and the other plate is located on the second metal layer 27 .
  • the display panel also includes scan lines, data lines, light control lines, power lines, and the like. Wherein, the scanning line is electrically connected to the gate driving circuit, and the light emitting control line is electrically connected to the light emitting driving circuit.
  • the scanning lines, data lines, light-emitting control lines, and power lines are respectively wired in four metal layers.
  • the scan lines are located on the first metal layer 26, the light emission control lines are located on the second metal layer 27, the data lines and power lines are located on the third metal layer 28, and an auxiliary power supply is also provided in the fourth metal layer 29. line, the auxiliary power line is connected in parallel with the power line to reduce the voltage drop on the power line.
  • the first metal layer 26 and the second metal layer 27 are made of the same material, and the materials of the first metal layer 26 and the second metal layer 27 include molybdenum.
  • the third metal layer 28 is made of titanium and aluminum. In one embodiment, the third metal layer 28 is a three-layer structure of titanium/aluminum/titanium. In other embodiments, the fourth metal layer 29 and the third metal layer 28 are made of the same material.
  • the orthographic projection of the encapsulation layer 50 on the substrate 10 covers the orthographic projection of the first shielding layer 41 on the substrate 10 , and the first shielding layer 41 is located on the same layer as the second electrode 323 in the light emitting device 32 .
  • Such an arrangement can ensure that the first shielding layer 41 is covered by the encapsulation layer 50 , avoiding defects caused by the first shielding layer 41 being exposed outside.
  • FIG. 5 is another schematic cross-sectional view at the position of tangent line A-A' in FIG. 1 . As shown in FIG. 5 , the shielding structure 40 and the second electrode 323 are located on the same layer.
  • FIG. 6 is another schematic cross-sectional view at the position of tangent line A-A' in FIG. 1 .
  • the display panel includes a semiconductor layer 25 , a first metal layer 26 , a second metal layer 27 , and a third metal layer 28 located on the substrate 10 and away from the substrate 10 in sequence.
  • the shielding structure 40 is located on the same layer as the second electrode 323 in the light emitting device 32 .
  • the channel 24 of the transistor is located on the semiconductor layer 25; one plate of the storage capacitor 80 is located on the first metal layer 26, and the other plate is located on the second metal layer 27; the scanning line is located on the first metal layer 26, and the light emitting
  • the control lines are located on the second metal layer 27 , and the data lines and power lines are located on the third metal layer 28 .
  • FIG. 7 is another schematic cross-sectional view at the position of tangent line A-A' in FIG. 1 .
  • the shielding structure 40 overlaps the edge of the first electrode layer 34 in a direction e perpendicular to the plane of the substrate 10 , and the shielding structure 40 is located on a side of the channel 24 close to the substrate 10 .
  • the charges induced by the back film material can be evacuated by the shielding structure 40, thereby blocking the conduction of the static electricity to the film layer where the channel is located, so as to prevent the static electricity from affecting the characteristics of the transistors in the peripheral circuits.
  • a barrier layer 11 and a buffer layer 12 are further disposed between the substrate 10 and the array layer 20 , wherein the barrier layer 11 is located on a side of the buffer layer 12 close to the substrate 10 .
  • the shielding structure 40 is located between the barrier layer 11 and the buffer layer 12 .
  • the shielding structure 40 is located between the substrate 10 and the barrier layer 11 .
  • the display panel includes two barrier layers, and the shielding structure 40 is located between the two barrier layers.
  • the display panel further includes a light-shielding layer 13 located in the display area 1 , and the orthographic projection of the substrate 10 of the light-shielding layer 13 covers the orthographic projection of the substrate 10 of the channel of the transistor in the display area 1 .
  • the shielding structure 40 is located on the same layer as the light shielding layer 13 . That is to say, the shielding structure 40 and the light-shielding layer 13 can be produced in the same process, and the fabrication of the shielding structure does not add a new process, and the process is simple.
  • the array layer 20 includes four metal layers for illustration (refer to related description in FIG. 2 ).
  • the array layer 20 includes three metal layers as shown in FIG. 6 , and the shielding structure 40 is located on the side of the trench 24 close to the substrate 10 , which is not shown in the drawings here.
  • the distance between the edge of the shielding structure 40 on the side away from the display area 1 and the edge of the display panel is d. d ⁇ 0, and d is between several microns and tens of microns.
  • the shielding structure 40 is not exposed at the side edges of the display panel, so as to avoid defects caused by exposing the conductive structures at the side edges.
  • the edge of the shielding structure 40 on the side away from the display area 1 is substantially flush with the edge of the display panel, which is not shown in the drawings here.
  • FIG. 8 is a schematic top view of another display panel provided in the embodiment of the present application.
  • the first electrode layer 34 extends from the display area 1 to the non-display area 2, and the shielding structure 40 Arranged on both sides of the display area 1 , the shielding structure 40 overlaps at least part of the edge of the first electrode layer 34 in the non-display area 2 .
  • FIG. 9 is a schematic top view of another display panel provided in the embodiment of the present application.
  • the first electrode layer 34 extends from the display area 1 to the non-display area 2, and the shielding structure 40 is disposed half around the display area 1 , and the shielding structure 40 overlaps at least part of the edge of the first electrode layer 34 in the non-display area 2 .
  • FIG. 9 also schematically shows a plurality of connection terminals located in the bonding area 3 , the connection terminals include at least one voltage terminal 4 , and the shielding structure 40 is electrically connected to the voltage terminal 4 .
  • FIG. 9 schematically shows that the shielding structure 40 is connected to the voltage terminal 4 through the connecting wires on the display panel.
  • the display panel is provided with a driver chip or a flexible circuit board, a certain voltage signal is provided to the voltage terminal 4 through the driver chip or the flexible circuit board, and then the shielding structure 40 is connected to a certain voltage.
  • the voltage value of the voltage signal connected to the shielding structure 40 can be set according to specific requirements.
  • the voltage terminal 4 is multiplexed as a ground terminal or as a voltage terminal for supplying voltage to the first electrode layer 34 .
  • FIG. 10 is a schematic partial top view of another display panel provided in the embodiment of the present application.
  • An electrode layer 34 is electrically connected to provide a voltage signal to the first electrode layer 34 .
  • the common voltage bus 5 extends to the binding area 3 and is electrically connected to the voltage terminal 4 .
  • the shielding structure 40 is connected to the common voltage bus 5 through the connecting wire 6 , so that the shielding structure 40 is connected to the voltage terminal 4 .
  • the shielding structure 40 and the first electrode layer 34 have the same potential.
  • the position of the film layer where the common voltage bus 5 is located there is no limitation on the position of the film layer where the common voltage bus 5 is located, and the relative position between the common voltage bus 5 and the peripheral circuit 21 .
  • the circuit wiring in the non-display area 2 is also relatively complicated.
  • the connecting line 6 used to connect the shielding structure 40 and the common voltage bus 5 may need to avoid the existing circuit wiring during design.
  • the position of the film layer where 5 is located, the position of the film layer where the shielding structure 40 is located, and the surrounding circuit wiring conditions are designed for the connection line 6 .
  • the manufacturing material of the shielding structure in the embodiment of the present application includes a metal material, a metal oxide, or a metal alloy.
  • the metal material includes any one or more of molybdenum, titanium, aluminum, cadmium and other metals
  • the metal oxide is, for example, indium tin oxide.
  • the shielding structure may also be made of an organic polymer material with certain electrical conductivity.
  • FIG. 11 is another schematic cross-sectional view at the position of tangent line A-A' in FIG. 1 .
  • the display panel further includes a support layer 60 and a heat dissipation layer 70 located on a side of the substrate 10 away from the array layer 20 .
  • the support layer 60 is used to support and protect the overall structural layer on the back of the display panel, so as to ensure the impact resistance of the back side of the display panel.
  • the heat dissipation layer 70 can play a role of heat dissipation, so as to prevent components from working abnormally due to excessive temperature of the display panel during operation.
  • the heat dissipation layer 70 includes a copper foil layer and foam.
  • FIG. 12 is a schematic diagram of the electronic device provided in the embodiment of the present application.
  • the electronic device includes the display panel 100 provided in any embodiment of the present application.
  • the structure of the display panel 100 has been described in the above-mentioned embodiment of the display panel, and will not be repeated here.
  • the electronic device provided in the embodiment of the present application may be a mobile phone, a tablet, a notebook computer, a TV, a smart wearable device, and other electronic devices.

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Abstract

本申请提供一种显示面板和电子设备。显示面板包括衬底、阵列层、显示层和屏蔽结构。显示层包括多个发光器件，每个发光器件包括第一电极、发光层和第二电极；多个第一电极相互连接形成面状的第一电极层，第一电极层由显示区延伸到非显示区；阵列层包括位于非显示区的驱动电路；屏蔽结构位于非显示区；屏蔽结构在衬底的正投影与第一电极层在衬底的正投影部分交叠；屏蔽结构在衬底的正投影与第一电极层位于非显示区的部分在衬底的正投影的合集覆盖周边电路在衬底的正投影。在屏蔽结构相当于将非显示区内具有恒定电位的结构向靠近面板边缘的方向加长，屏蔽结构能够消散显示面板边缘的电荷，防止静电电荷对周边电路中晶体管的沟道产生影响。

Description

显示面板和电子设备
本申请要求于2021年8月03日提交中国专利局、申请号为202110884190.8、申请名称为“显示面板和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于显示技术领域，更具体的涉及一种显示面板和电子设备。
背景技术
有机发光二极管(OLED)由于其低功耗、高对比度、广色域、高响应速度、以及自发光等特性，成为新一代主流的显示技术。而且由于其自发光特性能够制作薄型化的显示面板，使得折叠、卷曲等柔性产品的制作成为可能。现有的产品在外加电场的影响下存在闪屏、灰斑或者发绿等显示不良的问题。
发明内容
有鉴于此，本申请提供一种显示面板和电子设备，以解决在外加电场作用下显示不良的问题，提升显示性能可靠性。
第一方面，本申请一实施例提供一种显示面板，显示面板包括：
衬底；
显示层，位于衬底的一侧；显示层包括多个发光器件，每个发光器件包括堆叠设置的第一电极、发光层和第二电极；多个第一电极相互连接形成第一电极层，第一电极层由显示区延伸到非显示区；
阵列层，位于衬底和显示层之间；阵列层包括位于非显示区的周边电路；
屏蔽结构，屏蔽结构位于非显示区；屏蔽结构在衬底的正投影与第一电极层在衬底的正投影部分交叠；且，屏蔽结构在衬底的正投影为第一投影，第一电极层位于非显示区的部分在衬底的正投影为第二投影，第一投影和第二投影的合集覆盖周边电路在衬底的正投影。
在一种实施例中，周边电路包括栅极驱动电路，第一投影和第二投影的合集覆盖栅极驱动电路在衬底的正投影。在另一种实施例中，周边电路包括栅极驱动电路和发光驱动电路，第一投影和第二投影的合集覆盖栅极驱动电路和发光驱动电路在衬底的正投影。
本申请实施例提供的显示面板在非显示区设置有屏蔽结构，屏蔽结构在衬底的正投影与第一电极层在非显示区内的部分在衬底的正投影部分交叠。显示面板显示时在第一电极层上通常会施加一定的电压，而在屏蔽结构上也接通一定电压之后，相当于将非显示区内具有恒定电压电位的结构向靠近显示面板边缘的方向加长，则屏蔽结构 会对显示面板边缘的电势产生较大影响。设置屏蔽结构在衬底的正投影与第一电极层在非显示区中的部分的正投影的合集覆盖周边电路在衬底的正投影，则屏蔽结构接通一定电压之后能够用于消散显示面板边缘的电荷，防止静电电荷对周边电路中晶体管的沟道产生影响。本申请实施例中屏蔽结构能够起到静电屏蔽作用，降低周边电路中晶体管由于静电导致特性偏移进而引起电路失效的风险，从而降低在外加电场作用下显示不良的风险。
在一些实施方式中，周边电路包括多个晶体管，晶体管包括沟道；屏蔽结构位于沟道的远离衬底的一侧。本申请实施例将屏蔽结构设置在沟道的远离衬底的一侧，在显示面板产生的静电电荷由显示面向背面膜材传导时，在传递到屏蔽结构之后就首先被屏蔽结构疏散，从而能够阻断了静电向背面膜材的传导，以防止静电对周边电路中晶体管特性产生影响。
在另一些实施方式中，屏蔽结构与第二电极位于同一层。
在另一些实施方式中，屏蔽结构包括第一屏蔽层和第二屏蔽层；第一屏蔽层的靠近显示区的一端在衬底的正投影与第一电极层在衬底的正投影部分交叠；第一屏蔽层的远离显示区的一端在衬底的正投影与第二屏蔽层在衬底的正投影交叠、且第一屏蔽层与第二屏蔽层通过过孔相连接。该实施方式中，两层屏蔽层共同组成屏蔽结构，第二屏蔽层相对于第一屏蔽层远离显示区。在采用显示面板中现有的膜层制作屏蔽层时，能够通过对第一屏蔽层和第二屏蔽层分别所在的膜层位置进行设计，以对非显示区中现有的电路进行避让。
在一些实施方式中，第一屏蔽层与第二电极位于同一层，第二屏蔽层位于阵列层中距离显示层最近的金属层中。该实施方式中，第一屏蔽层和第二屏蔽层均复用显示面板中原有的膜层制作，不增加新的工艺制程。首先设置第一屏蔽层与第一电极层的边缘交叠，第一屏蔽层向远离显示区的方向延伸后与位于阵列层中的第二屏蔽层交叠且电连接。第一屏蔽层与第二电极位于同一层，则第一屏蔽层的设置不会影响阵列层中正常的电路布线。
在一些实施方式中，屏蔽结构位于沟道的靠近衬底的一侧。在显示面板应用过程中，背面膜材感生出电荷能够被屏蔽结构疏散，从而能够阻断了静电向沟道所在膜层的传导，以防止静电对周边电路中晶体管特性产生影响。
在一些实施方式中，显示面板还包括位于显示区的遮光层，屏蔽结构与遮光层位于同一层。屏蔽结构能够与遮光层在同一工艺制程中制作，屏蔽结构的制作不增加新的工艺制程，工艺简单。
显示面板还包括位于非显示区的电压端子，屏蔽结构与电压端子电连接。电压端子复用为接地端子或者复用为向第一电极层提供电压的电压端子。
第二方面，本申请实施例还提供一种电子设备，包括本申请任意实施例提供的显示面板。
本申请提供的显示面板和电子设备，具有如下有益效果：在显示面板的非显示区设置有屏蔽结构，屏蔽结构在衬底的正投影与第一电极层在非显示区内的部分在衬底的正投影部分交叠。显示面板显示时在第一电极层上通常会施加一定的电压，而在屏蔽结构上也接通一定电压之后，相当于将非显示区内具有恒定电压电位的结构向靠近 显示面板边缘的方向加长，则屏蔽结构会对显示面板边缘的电势产生较大影响。设置屏蔽结构在衬底的正投影与第一电极层在非显示区中的部分的正投影的合集覆盖驱动电路在衬底的正投影，则屏蔽结构接通一定电压之后能够用于消散显示面板边缘的电荷，防止静电电荷对周边电路中晶体管的沟道产生影响。本申请实施例中屏蔽结构能够起到静电屏蔽作用，降低周边电路中晶体管由于静电导致特性偏移进而引起电路失效的风险，从而降低在外加电场作用下显示不良的风险。
附图说明
图1为本申请一实施例提供的一种显示面板示意图；
图2为图1中切线A-A＇位置处一种截面示意图；
图3为本申请实施例提供的另一种显示面板的局部简化示意图；
图4为本申请实施例提供的另一种显示面板的局部简化示意图；
图5为图1中切线A-A＇位置处另一种截面示意图；
图6为图1中切线A-A＇位置处另一种截面示意图；
图7为图1中切线A-A＇位置处另一种截面示意图；
图8为本申请实施例提供的另一种显示面板的俯视示意图；
图9为本申请实施例提供的另一种显示面板的俯视示意图；
图10为本申请实施例提供的另一种显示面板的局部俯视示意图；
图11为图1中切线A-A＇位置处另一种截面示意图；
图12为本申请实施例提供的电子设备示意图。
具体实施方式
在现有技术中，在显示面板的表面设置有抗指纹涂层，抗指纹涂层含有较高浓度的氟元素，导致电子产品在使用过程中会由于摩擦积累负电荷，进而使得显示面板的背面膜材感生出电荷。又由于晶体管沟道所在膜层距背面膜材距离较近，则背面膜材中的电荷会导致周边电路中晶体管的特性出现偏移，进而影响周边电路对发光二极管的驱动性能，导致显示失效。基于此，本申请实施例提供一种显示面板，在非显示区设置屏蔽结构，利用屏蔽结构消散静电电荷，以解决静电无法及时消散导致的周边电路失效的问题。
图1为本申请一实施例提供的一种显示面板示意图，图2为图1中切线A-A＇位置处一种截面示意图。
如图1所示，显示面板包括显示区1和围绕显示区1的非显示区2，在非显示区2还设置有绑定区3，在绑定区3设置有多个连接端子(图1中未示出)。在一种实施例中，显示面板的非显示区2上设置有驱动芯片，则连接端子与驱动芯片上的引脚一一对应连接。在另一种实施例中，显示面板的非显示区2上固定有柔性电路板，则连接端子与柔性电路板上的引脚一一对应连接。
如图2所示，显示面板包括衬底10、阵列层20和显示层30。可选的，衬底10为柔性衬底，比如PI(聚酰亚胺)衬底。
显示层30位于衬底10的一侧。显示层30可以包括像素定义层31和多个发光器件32，每个发光器件32包括堆叠的第一电极321、发光层322和第二电极323，其中，第一电极321位于第二电极323的远离衬底10的一侧。在一种实施例中，发光器件32为有机发光二极管；在另一种实施例中，发光器件32为无机发光二极管。多个第一电极321相互连接形成第一电极层34，第一电极层34由显示区1延伸到非显示区2。也就是说，第一电极层34为覆盖显示区1并延伸到非显示区2的一整层结构，其中，第一电极层34相当于公共电极层。在一种实施例中，第一电极321为阴极，第二电极323为阳极，则第一电极层34为阴极层。
阵列层20位于衬底10和显示层30之间，阵列层20包括位于非显示区2的周边电路21，还包括位于显示区1的像素电路22，像素电路22与发光器件32电连接。像素电路22的输出端与发光器件32的第二电极323电连接。像素电路22向第二电极323提供电压信号，同时在第一电极321上施加公共电压信号，则在第一电极321和第二电极323的控制下使得发光器件32发光。图2中像素电路22仅做简化示意。
周边电路21包括多个晶体管23，晶体管23包括沟道24，晶体管23包括栅极、源极和漏极，其中，源极和漏极之间的导电半导体即为沟道24。在一些实施例中，阵列层20还可以包括位于衬底10之上的半导体层25，沟道24位于半导体层25。在显示面板制作时，制作出图案化的半导体层25之后，在预设形成沟道的区域采用沟道掺杂技术注入离子，以最终形成沟道24。
像素电路22的工作周期至少包括数据写入阶段和发光阶段，在数据写入阶段将数据线上提供的数据信号写入到像素电路22中驱动晶体管的栅极；在发光阶段，驱动晶体管在其栅极电压的控制下产生驱动电流。
在另一些实施例中，周边电路21还可以包括栅极驱动电路，栅极驱动电路包括级联的多个第一移位寄存器，显示面板还包括多条扫描线，扫描线与第一移位寄存器的输出端电连接，像素电路22包括扫描控制端，扫描控制端与扫描线电连接。级联的多个第一移位寄存器依次向多条扫描线提供扫描信号，再通过扫描线向扫描控制端输入扫描信号、以控制像素电路22工作在数据写入阶段。
在另一种实施例中，周边电路21还包括栅极驱动电路和发光驱动电路，发光驱动电路包括级联的多个第二移位寄存器，显示面板还包括多条发光控制线，发光控制线与第二移位寄存器的输出端电连接，像素电路22还包括发光控制端，发光控制端与发光控制线电连接。级联的多个第二移位寄存器依次向多条发光控制线提供发光控制信号，再通过发光控制线将发光控制信号提供给发光控制端、以控制像素电路22工作在发光阶段。在栅极驱动电路和发光驱动电路的配合控制下，像素电路22的输出端向第二电极323提供电压信号。
在一些实施例中，如图2所示的，显示面板还可以包括封装层50，封装层50用于对发光器件32进行封装保护。在一些实施例中，封装层50可以包括堆叠的第一无机层51、有机层52和第二无机层53。图2中还示出了位于非显示区2的挡墙33，挡墙33用于限定封装层50的边缘，并能够防止封装层50的边缘裂纹向显示区传递。在一些实施例中，在非显示区2还可以设置有裂纹检测线、裂纹挡墙等结构。其中，裂纹检测线用于在显示面板出厂之前对非显示区的裂纹情况进行检测。裂纹挡墙用于对 非显示区2内的裂纹进行阻挡，防止裂纹向显示区1内延伸。
在另一些实施例中，如图2所示，显示面板还可以包括屏蔽结构40，屏蔽结构40位于非显示区2。由图2中圈出的区域Q位置可以看出，在垂直于衬底10所在平面的方向e上，屏蔽结构40与第一电极层34的边缘至少部分交叠。图2中示意了垂直于衬底10的方向e，可以理解垂直于衬底10所在平面的方向e与向衬底10做正投影的投影方向相同。屏蔽结构40与第一电极层34的边缘交叠，也就是说，屏蔽结构40在衬底10的正投影与第一电极层34在衬底10的正投影部分重合。
图2中简化出了周边电路21所在位置，屏蔽结构40在衬底10的正投影为第一投影，第一电极层34在非显示区2的部分在衬底10的正投影为第二投影，可以看出第一投影和第二投影的合集覆盖周边电路21在衬底10的正投影。
在一种实施例中，图3为本申请实施例提供的另一种显示面板的局部简化示意图，如图3中示意出了位于显示区1的像素电路22、位于非显示区2的栅极驱动电路211和发光驱动电路212。栅极驱动电路211包括级联的多个第一移位寄存器71，发光驱动电路212包括级联的多个第二移位寄存器72。像素电路22通过扫描线73与第一移位寄存器71连接，像素电路22还通过发光控制线74与第二移位寄存器72连接。第一电极层34由显示区1延伸到非显示区2。屏蔽结构40在衬底10的正投影与第一电极层34位于非显示区2的部分在衬底的正投影的合集，覆盖栅极驱动电路211在衬底10的正投影。
在另一种实施例中，图4为本申请实施例提供的另一种显示面板的局部简化示意图，如图4所示，屏蔽结构40在衬底10的正投影与第一电极层34位于非显示区2的部分在衬底的正投影的合集、覆盖栅极驱动电路211在衬底10的正投影以及发光驱动电路212在衬底10的正投影。
本申请上述实施例提供的显示面板在非显示区设置有屏蔽结构40，屏蔽结构40在衬底10的正投影与第一电极层34在非显示区2的部分在衬底10的正投影交叠。显示面板显示时在第一电极层34上通常会施加一定的电压，在屏蔽结构40上也接通一定电压之后(其中，可以将屏蔽结构40接地，或者设置屏蔽结构40与第一电极层34连接相同电压信号)，相当于将非显示区2内具有恒定电压电位的结构向靠近显示面板边缘的方向加长，则屏蔽结构40会对显示面板边缘的电势产生较大影响。设置屏蔽结构40在衬底10的正投影与第一电极层34在非显示区2中的部分的正投影的合集覆盖周边电路21在衬底10的正投影，则屏蔽结构40接通一定电压之后能够用于消散显示面板边缘的电荷，防止静电电荷对周边电路21中晶体管的沟道产生影响。本申请实施例中屏蔽结构40能够起到静电屏蔽作用，降低周边电路中晶体管由于静电导致特性偏移进而引起电路失效的风险，从而降低在外加电场作用下显示不良的风险。
在本申请另一些实施例中，屏蔽结构40可以位于衬底10和第一电极层34之间。则屏蔽结构40在显示面板的封装层50的工艺之前制作，屏蔽结构40能够复用阵列层20或者显示层30中的工艺制程制作。而且向屏蔽结构40提供电压的电压端子通常设置在阵列层20，将屏蔽结构40设置在衬底10和第一电极层34之间，屏蔽结构40和向其提供电压的电压端子之间的连接更容易实现。
在另一些实施方式中，在封装层50之上还可以设置有偏光层、保护层、抗指纹层、 防眩光层等膜层。
如图2所示的，屏蔽结构40位于沟道24的远离衬底10的一侧。在显示面板应用过程中，由于摩擦会在显示面板的显示面一侧产生负电电荷，其中，显示面也即出光表面。在显示面一侧产生的负电进而会导致显示面板的背面膜材感生出电荷。而晶体管的沟道相比于其他电路结构更加靠近衬底10(即显示面板的背面一侧)，本申请实施例将屏蔽结构40设置在沟道24的远离衬底10的一侧，在显示面板产生的静电电荷由显示面向背面膜材传导时，在传递到屏蔽结构40之后就首先被屏蔽结构40疏散，从而能够阻断了静电向背面膜材的传导，以防止静电对周边电路中晶体管特性产生影响。
如图2所示的，屏蔽结构40包括第一屏蔽层41和第二屏蔽层42；在垂直于衬底10所在平面方向e上，第一屏蔽层41的靠近显示区1的一端与第一电极层34的边缘交叠；第一屏蔽层41的远离显示区1的一端与第二屏蔽层42交叠。换句话说，第一屏蔽层41的靠近显示区1的一端在衬底10的正投影与第一电极层34在衬底10的正投影交叠，第一屏蔽层41的远离显示区1的一端在衬底10的正投影与第二屏蔽层42在衬底10的正投影交叠。并且第一屏蔽层41与第二屏蔽层42通过过孔相连接。在屏蔽结构40上通入一定电压之后，第一屏蔽层41和第二屏蔽层42上具有相同电位。该实施方式中，两层屏蔽层共同组成屏蔽结构40，第二屏蔽层42相对于第一屏蔽层41远离显示区1。在采用显示面板中现有的膜层制作屏蔽层时，能够通过对第一屏蔽层41和第二屏蔽层42分别所在的膜层位置进行设计，以对非显示区中现有的周边电路进行避让。
在一些实施方式中，第一屏蔽层41与第二电极323位于同一层，第二屏蔽层42位于阵列层20中距离显示层30最近的金属层中。该实施方式中，第一屏蔽层41和第二屏蔽层42均复用显示面板中原有的膜层制作，不增加新的工艺制程。在非显示区2设置有公共电压总线、周边电路21等结构。阵列层20中的金属层用于制作显示区1内的像素电路，还用于制作非显示区2的周边电路。其中，公共电压总线与第一电极层34电连接，用于给第一电极层34提供电压信号。在复用显示面板中原有的膜层制作屏蔽结构40时，为了保证在垂直于衬底10所在平面方向e上屏蔽结构40与第一电极层34的边缘交叠，如果单独使用阵列层20中的金属层制作屏蔽结构40，可能会影响非显示区2中的正常布线。本申请实施例中，首先设置第一屏蔽层41与第一电极层34的边缘交叠，第一屏蔽层41向远离显示区1的方向延伸后与位于阵列层20中的第二屏蔽层42交叠且电连接。第一屏蔽层41的设置不会影响阵列层20中正常的电路布线。
在一些实施例中，如图2所示，显示面板包括位于衬底10之上依次远离衬底10的半导体层25、第一金属层26、第二金属层27、第三金属层28和第四金属层29。其中，第四金属层29为该实施例中距显示层30最近的金属层。可选的，第二屏蔽层42位于第四金属层29中。
在另一些实施例中，像素电路22还可以包括存储电容，如图2所示，存储电容80的一个极板位于第一金属层26，另一个极板位于第二金属层27。显示面板中还包括扫描线、数据线、发光控制线、电源线等。其中，扫描线与栅极驱动电路电连接， 发光控制线与发光驱动电路电连接。扫描线、数据线、发光控制线、电源线分别在四个金属层中进行布线。在一种实施例中，扫描线位于第一金属层26、发光控制线位于第二金属层27、数据线和电源线位于第三金属层28，在第四金属层29中还设置有辅助电源线，辅助电源线与电源线并联连接，以降低电源线上的压降。
在一些实施例中，第一金属层26和第二金属层27采用相同材料制作，第一金属层26和第二金属层27的制作材料包括钼。在一些实施例中，第三金属层28的制作材料包括钛和铝，在一种实施例中第三金属层28为钛/铝/钛三层结构。在另一些实施例中，第四金属层29和第三金属层28采用相同材料制作。
另外，本申请实施例中封装层50在衬底10的正投影覆盖第一屏蔽层41在衬底10的正投影，第一屏蔽层41与发光器件32中的第二电极323位于同一层。如此设置能够保证第一屏蔽层41被封装层50覆盖，避免第一屏蔽层41裸露在外引起不良。
在另一种实施例中，图5为图1中切线A-A＇位置处另一种截面示意图。如图5所示，屏蔽结构40与第二电极323位于同一层。
在另一种实施例中，图6为图1中切线A-A＇位置处另一种截面示意图。如图6所示，显示面板包括位于衬底10之上依次远离衬底10的半导体层25、第一金属层26、第二金属层27、第三金属层28。屏蔽结构40与发光器件32中的第二电极323位于同一层。该实施方式中，晶体管的沟道24位于半导体层25；存储电容80的一个极板位于第一金属层26，另一个极板位于第二金属层27；扫描线位于第一金属层26、发光控制线位于第二金属层27、数据线和电源线位于第三金属层28。
在一些实施方式中，图7为图1中切线A-A＇位置处另一种截面示意图。如图7所示，在垂直于衬底10所在平面的方向e上屏蔽结构40与第一电极层34的边缘交叠，屏蔽结构40位于沟道24的靠近衬底10的一侧。在显示面板应用过程中，背面膜材感生出电荷能够被屏蔽结构40疏散，从而能够阻断了静电向沟道所在膜层的传导，以防止静电对周边电路中晶体管特性产生影响。
如图7所示的，在衬底10和阵列层20之间还设置有阻隔层11和缓冲层12，其中，阻隔层11位于缓冲层12的靠近衬底10的一侧。在一种实施例中，屏蔽结构40位于阻隔层11和缓冲层12之间。在另一种实施例中，屏蔽结构40位于衬底10和阻隔层11之间。在另一种实施例中，显示面板包括两层阻隔层，屏蔽结构40位于两层阻隔层之间。
如图7所示的，显示面板还包括位于显示区1的遮光层13，遮光层13的衬底10的正投影覆盖显示区1内晶体管的沟道的衬底10的正投影。
在一种实施例中，屏蔽结构40与遮光层13位于同一层。也就是说，屏蔽结构40能够与遮光层13在同一工艺制程中制作，屏蔽结构的制作不增加新的工艺制程，工艺简单。
另外，图7实施例中以阵列层20包括四个金属层进行示意(可参见图2中相关说明)。在另一种实施例中，阵列层20包括如图6中示意的三个金属层，且屏蔽结构40位于沟道24的靠近衬底10的一侧，在此不再附图示意。
在一些实施例方式中，如图7所示的，屏蔽结构40的远离显示区1一侧的边缘距显示面板的边缘之间的间距为d。d≠0，d介于几微米至几十微米之间。在显示面板 的侧面边缘不会暴露屏蔽结构40，避免侧面边缘暴露导电结构引起不良。
在一些实施例方式中，屏蔽结构40的远离显示区1一侧的边缘与显示面板的边缘基本平齐，在此不再附图示意。
在一种实施例中，图8为本申请实施例提供的另一种显示面板的俯视示意图，如图8所示，第一电极层34由显示区1延伸到非显示区2，屏蔽结构40设置在显示区1的两侧，屏蔽结构40与第一电极层34在非显示区2的至少部分边缘交叠。
在另一种实施例中，图9为本申请实施例提供的另一种显示面板的俯视示意图，如图9所示，第一电极层34由显示区1延伸到非显示区2，屏蔽结构40半环绕显示区1设置，屏蔽结构40与第一电极层34在非显示区2的至少部分边缘交叠。
图9中还示意出了位于绑定区3的多个连接端子，连接端子中至少包括一个电压端子4，屏蔽结构40与电压端子4电连接。图9中示意屏蔽结构40通过显示面板上的连接线连接到电压端子4。在应用中显示面板上设置有驱动芯片或者柔性电路板，则通过驱动芯片或者柔性电路板向电压端子4提供一定的电压信号，进而将屏蔽结构40接通一定电压。其中，屏蔽结构40接通的电压信号的电压值可以根据具体需求进行设定。
在一些实施方式中，电压端子4复用为接地端子或者复用为向第一电极层34提供电压的电压端子。
在一种实施例中，图10为本申请实施例提供的另一种显示面板的局部俯视示意图，如图10所示，非显示区2还设置有公共电压总线5，公共电压总线5与第一电极层34电连接用于给第一电极层34提供电压信号。其中，公共电压总线5延伸到绑定区3与电压端子4电连接。屏蔽结构40通过连接线6连接到公共电压总线5，实现屏蔽结构40连接到电压端子4。该实施方式中，屏蔽结构40与第一电极层34上具有相同的电位。
本申请中对于公共电压总线5所在的膜层位置、以及公共电压总线5与周边电路21之间的相关位置均不做限定。在非显示区2的电路布线也相对复杂，用于连接屏蔽结构40与公共电压总线5的连接线6在设计时可能需要会对现有的电路布线进行避让，具体的，可根据公共电压总线5所在的膜层位置、屏蔽结构40所在膜层位置、以及周围相关电路布线情况对连接线6进行设计。
可选的，本申请实施例中屏蔽结构的制作材料包括金属材料、金属氧化物、或者包括金属合金。其中，金属材料包括钼、钛、铝、镉等金属中任意一种或多种，金属氧化物比如为铟锡氧化物。
在一些实施方式中，屏蔽结构的制作材料也可以为具有一定导电性能的有机聚合物材料。
在另一种实施例中，图11为图1中切线A-A＇位置处另一种截面示意图。如图11所示，显示面板还包括位于衬底10远离阵列层20一侧的支撑层60和散热层70。其中，支撑层60用于在显示面板的背面对整体的结构层进行支撑保护，保证显示面板背面一侧的抗冲击性能。散热层70能够起到散热作用，避免显示面板工作时温度过高导致元器件工作异常。在一些实施方式中，散热层70包括铜箔层和泡棉。
本申请实施例还提供一种电子设备，图12为本申请实施例提供的电子设备示意图， 如图12所示，电子设备包括本申请任意实施例提供的显示面板100。对于显示面板100的结构已经在上述显示面板实施例中进行说明，在此不再赘述。本申请实施例提供的电子设备可以为手机、平板、笔记本电脑、电视、智能穿戴设备等电子设备。

Claims (10)

  1. 一种显示面板，其特征在于，所述显示面板包括：
    衬底；
    显示层，位于所述衬底的一侧；所述显示层包括多个发光器件，每个所述发光器件包括堆叠设置的第一电极、发光层和第二电极；多个所述第一电极相互连接形成第一电极层，所述第一电极层由显示区延伸到非显示区；
    阵列层，位于所述衬底和所述显示层之间；所述阵列层包括位于所述非显示区的周边电路；
    屏蔽结构，所述屏蔽结构位于所述非显示区；所述屏蔽结构在所述衬底的正投影与所述第一电极层在所述衬底的正投影部分交叠；且，所述屏蔽结构在所述衬底的正投影为第一投影，所述第一电极层位于所述非显示区的部分在所述衬底的正投影为第二投影，所述第一投影和所述第二投影的合集覆盖所述周边电路在所述衬底的正投影。
  2. 根据权利要求1所述的显示面板，其特征在于，
    所述周边电路包括多个晶体管，所述晶体管包括沟道；
    所述屏蔽结构位于所述沟道的远离所述衬底的一侧。
  3. 根据权利要求2所述的显示面板，其特征在于，
    所述屏蔽结构与所述第二电极位于同一层。
  4. 根据权利要求2所述的显示面板，其特征在于，
    所述屏蔽结构包括第一屏蔽层和第二屏蔽层；
    所述第一屏蔽层的靠近所述显示区的一端在所述衬底的正投影与所述第一电极层在所述衬底的正投影部分交叠；所述第一屏蔽层的远离所述显示区的一端在所述衬底的正投影与所述第二屏蔽层在所述衬底的正投影交叠；且所述第一屏蔽层与所述第二屏蔽层通过过孔相连接。
  5. 根据权利要求4所述的显示面板，其特征在于，
    所述第一屏蔽层与所述第二电极位于同一层，
    所述第二屏蔽层位于所述阵列层中距离所述显示层最近的金属层中。
  6. 根据权利要求1所述的显示面板，其特征在于，
    所述周边电路包括多个晶体管，所述晶体管包括沟道；
    所述屏蔽结构位于所述沟道的靠近所述衬底的一侧。
  7. 根据权利要求6所述的显示面板，其特征在于，
    所述显示面板还包括位于所述显示区的遮光层，所述屏蔽结构与所述遮光层位于同一层。
  8. 根据权利要求1所述的显示面板，其特征在于，
    所述显示面板还包括位于所述非显示区的电压端子，所述屏蔽结构与所述电压端子电连接。
  9. 根据权利要求8所述的显示面板，其特征在于，所述电压端子复用为接地端子或者复用为向所述第一电极层提供电压的电压端子。
  10. 一种电子设备，其特征在于，包括权利要求1至9任一项所述的显示面板。
PCT/CN2022/108154 2021-08-03 2022-07-27 显示面板和电子设备 Ceased WO2023011275A1 (zh)

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