WO2023035155A1 - 半导体结构及其制备方法、射频电路 - Google Patents

半导体结构及其制备方法、射频电路 Download PDF

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Publication number
WO2023035155A1
WO2023035155A1 PCT/CN2021/117293 CN2021117293W WO2023035155A1 WO 2023035155 A1 WO2023035155 A1 WO 2023035155A1 CN 2021117293 W CN2021117293 W CN 2021117293W WO 2023035155 A1 WO2023035155 A1 WO 2023035155A1
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region
base region
contact
semiconductor structure
substrate
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French (fr)
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徐向明
简中祥
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN202180102025.0A priority Critical patent/CN117941040A/zh
Priority to PCT/CN2021/117293 priority patent/WO2023035155A1/zh
Priority to EP21956343.4A priority patent/EP4391027A4/en
Publication of WO2023035155A1 publication Critical patent/WO2023035155A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
    • H10D10/891—Vertical heterojunction BJTs comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof, and a radio frequency circuit.
  • CMOS complementary metal oxide semiconductor
  • TCAD Technical Computer Aided Design
  • GaAs gallium arsenide
  • InP indium phosphide
  • III-V group materials have much higher electron and hole mobility than silicon, and have excellent high-frequency characteristics. At the same time, because of their high band gap, they have Compared with SiGe HBT, it has a higher breakdown voltage and is also suitable for high frequency and high power applications.
  • III-V materials have disadvantages such as high cost, high environmental protection cost, poor thermal conductivity, and poor mechanical properties.
  • CMOS+SiGe, SiGe BiCMOS Integrating CMOS and SiGe HBT on the same chip
  • the advantages of SiGe HBT such as high frequency, high speed, high gain, and low noise are suitable for analog circuit design, while the low power consumption of CMOS is suitable for digital logic circuits.
  • the integration of the latter meets the design requirements of digital-analog hybrid circuits, making SiGe BiCMOS have the advantages of low cost and high integration compared with III-V materials.
  • SiGe BiCMOS is playing an increasingly important role in applications in the fields of photoelectric high-speed transmission, microwave high frequency, radar, imaging and sensing.
  • SiGe HBT can be used to make photoelectric transimpedance amplifiers, drivers, and clock data recovery. (clock data recovery, CDR), microwave low noise amplifier, mixer, power amplifier and other different RF circuits.
  • Embodiments of the present application provide a semiconductor structure, a manufacturing method thereof, and a radio frequency circuit, which are used to solve the problems of complex manufacturing process and high cost of high-performance HBT.
  • a semiconductor structure including: a substrate, including a collector region buried in the substrate; an intrinsic base region, arranged on the surface of the substrate, and the collector region on the substrate
  • the surface contact of the extrinsic base area is arranged on the surface of the substrate, located on the periphery of the intrinsic base area, and is in contact with the intrinsic base area; the auxiliary layer has an opening; the auxiliary layer is arranged on the outer base area; the emission area is arranged on the auxiliary
  • the upper layer is in contact with the intrinsic base region through the opening; the inner wall is arranged between the extrinsic base region and the emission region.
  • both the intrinsic base region and the extrinsic base region are arranged on the surface of the substrate, the collector region is arranged inside the substrate, and there is no raised epitaxial collector region located on the substrate surface. Therefore.
  • the intrinsic base region and the extrinsic base region are directly formed on the surface of the known substrate, and whether the two are in contact is directly controllable through its own preparation process. Compared with setting an epitaxial collector region on the surface of the substrate and then setting an intrinsic base region on the epitaxial collector region.
  • the embodiment of the present application directly sets the intrinsic base region on the surface of the substrate, which will not affect the contact between the intrinsic base region and the extrinsic base region due to parameters such as the thickness of the raised collector region, and can improve the intrinsic base region and the extrinsic base region.
  • the contact yield of the area thereby improving the yield of the semiconductor structure.
  • the collector region is obtained by doping, and one step of epitaxial process (preparation of the collector region) is omitted, which saves the processing cost.
  • the substrate further includes a shallow trench isolation region disposed on the periphery of the active region below the intrinsic base region; the collector region is located in the active region. Both the collector region and the shallow trench isolation region are located in the substrate, there is no raised epitaxial collector region, and the contact between the intrinsic base region and the extrinsic base region will not be affected by parameters such as the thickness of the collector region, which can improve The contact yield of the intrinsic base area and the extrinsic base area, thereby improving the yield rate of the semiconductor structure.
  • the substrate further includes an auxiliary extrinsic base region disposed in the shallow trench isolation region; the extrinsic base region and the auxiliary extrinsic base region are in contact with the surface of the substrate.
  • An auxiliary extrinsic base region is set in the substrate, and the auxiliary extrinsic base region is used as a seed layer for the epitaxial growth of the extrinsic base region. The purpose of base resistance.
  • the extrinsic base region includes a bridging region and an effective extrinsic base region, and the bridging region is in contact with the intrinsic base region and the effective extrinsic base region, respectively.
  • the effective extrinsic base region is in contact with the bridging region
  • the bridging region is in contact with the intrinsic base region, so that the extrinsic base region is in contact with the intrinsic base region. Since the material of the bridge region is quasi-single crystal silicon, the activation rate of the dopant ions is greater than that of the dopant ions in the effective extrinsic base region (the material is polysilicon). Therefore, realizing the contact between the effective extrinsic base region and the intrinsic base region through the bridging region can reduce the contact resistance between the extrinsic base region and the intrinsic base region.
  • the bridging region overlaps the intrinsic base region and/or the effective extrinsic base region. Realizing the contact by overlapping can reduce the requirements for process precision and reduce process difficulty.
  • the semiconductor structure further includes an outer wall; the outer wall wraps the side of the emission region for protecting the emission region.
  • the outer wall can protect the emission region during the preparation of the semiconductor structure, and prevent other epitaxial steps from affecting the emission region.
  • the semiconductor structure further includes a capping layer, and the capping layer covers the surface of the emitting region away from the substrate for protecting the emitting region.
  • the outer wall can protect the emission region during the preparation of the semiconductor structure, and prevent other epitaxial steps from affecting the emission region.
  • the inner wall includes an inner wall disposed on the surface of the outer base region facing the emission region; the inner wall is L-shaped.
  • the L-shaped inner wall has a wide coverage, which can improve the isolation effect between the outer base area and the launch area.
  • the semiconductor structure further includes an emitter, a base, and a collector disposed on the substrate; the emitter is in contact with the emitter region, the base is in contact with the extrinsic base region, and the collector is in contact with the collector region.
  • the substrate further includes a lead-out region and a buried layer collector region, the lead-out region and the shallow trench isolation region are located above the buried layer collector region, and the lead-out region is located on the side of the shallow trench isolation region away from the collector region ;
  • the lead-out region and the collector region are respectively in contact with the buried layer collector region;
  • the collector is in contact with the lead-out region through the connection hole and the collector region;
  • the emitter passes through the connection hole that passes through the cap layer and contacts the emitter region, and the emitter region Contact;
  • the base is in contact with the extrinsic base through a connection hole in contact with the extrinsic base.
  • the semiconductor structure further includes a complementary metal-oxide-semiconductor field-effect transistor disposed on the substrate.
  • the semiconductor structure is a CMOS+SiGe HBT device, and CMOS and SiGe HBT can be integrated on the same chip, which can take advantage of both.
  • a second aspect of the embodiments of the present application provides a radio frequency circuit, including a transistor circuit including the semiconductor structure of the first aspect.
  • a method for preparing a semiconductor structure including: forming a base, the base includes an active region and a shallow trench isolation region; For the second sacrificial film and the auxiliary film, a second opening is formed on the second sacrificial film, a third opening is formed on the auxiliary film, and the second opening communicates with the third opening as an emission area window; a first inner wall is formed, and the first inner The wall is arranged around the surface of the second sacrificial film facing the window of the emission region; a collector region is formed, and the collector region is located in the active region directly below the window of the emission region; a first opening is formed on the first sacrificial film, and the first opening Communicating with the second opening; forming an intrinsic base region in the first opening; forming an emission region film in contact with the intrinsic base region at the emission region window, patterning the emission region film and the auxiliary film, forming the emission region and the auxiliary layer; remove the first
  • the method for preparing a semiconductor structure uses the first sacrificial film, the second sacrificial film and the auxiliary film as the self-alignment structure, which can be used to realize the self-alignment of the collector junction and the self-alignment of the emitter junction.
  • the prepared collector junction and emitter junction have an axisymmetric structure, and there will be no deviation like photolithography and etching processes, resulting in asymmetry of the collector junction and emitter junction.
  • the asymmetry of the emitter junction leads to the difference between the parasitic collector junction capacitance and the base region resistance on both sides of the emitter junction midline, which cannot share the current on both sides, resulting in the inability to minimize the total resistance and capacitance.
  • the preparation of each film layer can be realized by using conventional techniques.
  • the formation of the collector region is also achieved by defining the position of the self-aligned structure, and then performing ion implantation in the substrate. Both the intrinsic base region and the extrinsic base region are set on the surface of the substrate, and there is no raised epitaxial collector region, so the contact between the intrinsic base region and the extrinsic base region will not be affected by parameters such as the thickness of the collector region. , reduce the requirements for process precision and reduce process difficulty. And one less epitaxy process is needed, which saves processing cost.
  • forming the substrate further includes: forming an auxiliary extrinsic base region in the shallow trench isolation region, and the extrinsic base region and the auxiliary extrinsic base region are in contact with the surface of the substrate.
  • An auxiliary extrinsic base region is set in the substrate, and the auxiliary extrinsic base region is used as a seed layer for the epitaxial growth of the extrinsic base region. The purpose of base resistance.
  • removing the second sacrificial film and the first sacrificial film and forming the extrinsic base region at corresponding positions includes: removing the second sacrificial film and forming a bridge region under the auxiliary layer; the bridge region and the intrinsic base region Contacting: removing the first sacrificial film, forming an effective exogenous base region at the corresponding position, and the effective exogenous base region is in contact with the bridging region. In this way, the effective extrinsic base region is in contact with the bridging region, and the bridging region is in contact with the intrinsic base region, so that the extrinsic base region is in contact with the intrinsic base region.
  • the activation rate of the dopant ions is greater than that of the dopant ions in the effective extrinsic base region (the material is polysilicon). Therefore, realizing the contact between the effective extrinsic base region and the intrinsic base region through the bridging region can reduce the contact resistance between the extrinsic base region and the intrinsic base region.
  • the contour of the second opening falls within the contour of the first opening.
  • the subsequently formed bridging region overlaps with the intrinsic base region and/or the effective extrinsic base region to achieve contact in an overlapping manner, which can reduce requirements on process precision and reduce process difficulty.
  • the manufacturing method before forming the emission region contacting the intrinsic base region at the emission region window, the manufacturing method further includes: removing the first inner wall to form a second inner wall.
  • ions will be implanted into the first inner wall when ion implantation forms the collector region, thereby affecting the isolation effect between the subsequently formed outer base region and the emitter region. Therefore, after the first inner wall is removed and the second inner wall is re-formed, the above problems can be solved and the isolation effect between the outer base region and the emission region can be improved.
  • the part of the first inner wall in contact with the first sacrificial film will be removed simultaneously, that is, the cross section of the first inner wall is strip-shaped. As a result, the first inner wall cannot play an isolation role in this area.
  • the third inner wall included in it is L-shaped and covers a wide range, which can improve the isolation effect between the outer base area and the launch area.
  • the manufacturing method further includes: cleaning the surface of the intrinsic base region to remove the intrinsic oxide layer.
  • the step of removing the first inner wall and forming the second inner wall is also performed, which causes the exposed surface of the intrinsic base region to be easily oxidized to produce SiO2, which affects the subsequent formation of the emitter region and the original inner wall.
  • the electrical contact effect in the base region leads to a higher resistance in the emitter region.
  • Cleaning the surface of the intrinsic base region can remove the SiO2 on the surface of the intrinsic base region, thereby improving the electrical contact effect between the subsequently formed emitter region and the intrinsic base region, and facilitating the epitaxial growth of single crystal material in the emitter region, which can effectively reduce the emitter resistance.
  • the manufacturing method further includes: forming a CMOS field effect transistor on the substrate.
  • the prepared semiconductor structure is a CMOS+SiGe HBT device, and CMOS and SiGe HBT can be integrated on the same chip, which can take advantage of both.
  • FIG. 1 is a diagram of the preparation process of a semiconductor structure provided in the embodiment of the present application.
  • FIG. 2 is a flowchart of the preparation of a semiconductor structure provided in the embodiment of the present application.
  • 3A-3M are diagrams of the preparation process of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 4A is a schematic structural diagram of a semiconductor structure provided in an embodiment of the present application.
  • FIG. 4B is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 5A is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 5B is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present application.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the term “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • SiGe heterojunction bipolar transistor (SiGe HBT) has better thermal conductivity and good mechanical properties of the substrate, which better solves the heat dissipation problem of semiconductor structures. Moreover, SiGe HBT also has better linearity, higher integration, and good compatibility with complementary metal oxide semiconductor (CMOS) technology. Therefore, it is widely used in the fields of optoelectronics, radio frequency, microwave, etc., especially in high-frequency devices in the above-mentioned fields. For example, some high-frequency analog devices using photoelectric high-speed transmission technology and microwave high-frequency technology, the high-frequency analog devices obtained by using SiGe BiCMOS structure have both the speed block of SiGe HBT structure, high gain, low noise, and low power consumption of CMOS devices. Advantage.
  • a method for preparing a semiconductor structure is provided. First, the window of the emission region is defined; A collector region is formed in the collector region; then, a selective epitaxial process is used on the collector region to form an intrinsic base region and an emitter region film in the emission region window; and then subsequent structures such as the emitter region and the outer base region are prepared. As shown in FIG. 1 , in the semiconductor structure prepared by the above preparation method, the collector region, the intrinsic base region and the emitter region are all arranged above the substrate.
  • the above method is used to prepare a semiconductor structure, and a fully self-aligned process is adopted in which the collector region, the intrinsic base region and the emitter region are grown in the same emission region window, and the prepared semiconductor structure has the advantage of a self-aligned structure.
  • the collector region also adopts a selective epitaxy process, the manufacturing cost increases.
  • the height control of the collector region determines the relative position of the intrinsic base region and the extrinsic base region. As shown in Figure 1, the intrinsic base region and the extrinsic base region are in contact through the bridge region. If the height of the collector region is not suitable, the intrinsic base region on the collector region will have too little or no contact with the bridge region.
  • connection resistance between the intrinsic base region and the extrinsic base region thus affecting the connection resistance between the intrinsic base region and the extrinsic base region. That is to say, the height of the collector region determines the relative position of the intrinsic base region and the bridge region, directly affects the connection resistance of the intrinsic base region and the extrinsic base region, thereby affecting the performance of the device. This leads to higher requirements on process precision in the process of preparing the semiconductor structure. If the process precision cannot be achieved, the performance of the prepared semiconductor structure will be greatly affected.
  • the embodiment of the present application also provides a method for preparing a semiconductor structure, as shown in FIG. 2 , including:
  • the method for forming the substrate 11, as shown in FIG. 3A includes:
  • the ion implantation of the buried layer collector region 15 is completed before the opening of the STI, and can be implanted before forming the epitaxial layer, and then diffused into the epitaxial layer by high temperature. It can also be obtained by performing ion implantation after forming the epitaxial layer.
  • the above-mentioned sequence of forming the buried collector region 15 is only an illustration, without any limitation.
  • a screen oxide may be formed before forming the buried collector region 15 and the lead-out region 16.
  • the shielding oxide layer can protect the crystal lattice of the silicon substrate 12 from being damaged.
  • the shielding oxide layer can be removed, and then subsequent steps can be performed.
  • the buried collector region 15 and the lead-out region 16 are located in the silicon base 12 .
  • the formation of an epitaxial layer on the silicon substrate 12 is taken as an example for illustration.
  • SiO2 silicon dioxide
  • Si3N4 silicon nitride
  • STI openings are formed by photolithography and dry etching. Of course, other processes are also possible.
  • the dielectric material is, for example, SiO2 or other field effect oxides.
  • the dielectric material may or may not cover the Si3N4 film, but must fill the STI opening.
  • CMP chemical mechanical polishing
  • the Si3N4 film can be removed by wet etching.
  • the region filled with SiO 2 in the epitaxial layer is the STI region 13 , and the remaining regions are the active region 14 of the substrate 11 .
  • step S17 the preparation of the substrate 11 is basically completed, and then S18 ′ can be performed to remove excess SiO2 film and expose the silicon surface of the substrate 11 .
  • the substrate 11 includes a silicon substrate 12 and an epitaxial layer disposed on the silicon substrate 12.
  • the epitaxial layer is divided into an STI region 13, an active region 14, and a buried layer collector region 15.
  • the lead-out region 16 , the lead-out region 16 and the STI region 13 are located above the buried layer collector region 15 , and the lead-out region 16 is in contact with the buried layer collector region 15 .
  • the step of forming the substrate 11 further includes: forming an auxiliary extrinsic base region 21 in the STI region 13 .
  • the step of forming the auxiliary extrinsic base region 21 in the STI region 13 includes:
  • grooves are formed in the STI region 13 by photolithography and dry etching.
  • the polysilicon film can be formed through an epitaxial process, or a chemical vapor deposition (chemical vapor deposition, CVD) process can be used to form the polysilicon film.
  • CVD chemical vapor deposition
  • the material of the polysilicon film may be polysilicon or polysilicon silicide or the like.
  • the polysilicon film may also be doped after the polysilicon film is formed.
  • the polysilicon film can be doped in situ, or the polysilicon film can be formed first and then doped by ion implantation.
  • the SiO2 film can be used as a barrier layer, and the polysilicon film can be ground by using a CMP process to remove the polysilicon film located outside the groove.
  • the excess SiO2 film can be removed by wet etching or dry etching.
  • the surface of the auxiliary extrinsic base region 17 is higher than the surface of the STI region 13 .
  • the surface of the auxiliary extrinsic base region 17 is flush with the surface of the STI region 13 .
  • the substrate 11 may be ground by a CMP process, so that the surface of the auxiliary extrinsic base region 17 is flush with the surface of the STI region 13 .
  • it is equivalent to the STI region 13 filling the auxiliary extrinsic base region 17 .
  • the manner of forming the emission region window includes:
  • the materials of the first sacrificial film 31 and the auxiliary film 51 are the same, and the materials of the first sacrificial film 31 and the second sacrificial film 41 are different.
  • the materials of the first sacrificial film 31 , the second sacrificial film 41 and the auxiliary film 51 may all be silicide, for example.
  • the material of the first sacrificial film 31 and the auxiliary film 51 is silicon-containing oxide.
  • the materials of the first sacrificial film 31 and the auxiliary film 51 are SiO2, silicon oxynitride, or oxygen-rich silicon dioxide.
  • the material of the second sacrificial film 41 is silicon nitride.
  • the material of the second sacrificial film 41 is Si3N4.
  • the method of forming the first sacrificial film 31 , the second sacrificial film 41 and the auxiliary film 51 can be, for example, a chemical vapor deposition (CVD) process to form the first sacrificial film 31 , the second sacrificial film 41 and the auxiliary film 51 .
  • CVD chemical vapor deposition
  • the third opening 52 may be formed on the auxiliary film 51 through photolithography and etching processes.
  • the second opening 42 may be formed on the second sacrificial film 41 through photolithography and etching processes.
  • forming the third opening 52 and the second opening 42 may be completed in two processes, or may be completed in the same process, which is not limited in this embodiment of the present application.
  • the formed second opening 42 and third opening 52 communicate with each other as the window of the emission area, and the first sacrificial film 31 remains at the bottom of the window of the emission area, which is not directly connected to the substrate 11 .
  • the second opening 42 and the third opening 52 are located opposite each other and have the same size. Or it can be understood that the orthographic projection of the second opening 42 on the base 11 coincides with the orthographic projection of the third opening 52 on the base 11 .
  • the formed first inner wall 60 is arranged around the surface of the second sacrificial film 41 facing the second opening 42 (the emission area window).
  • the formed first inner wall 60 also extends to the surface of the auxiliary film 51 facing the third opening 52 .
  • the manner of forming the first inner wall 60 includes:
  • the material of the first dielectric film 61 may be a dielectric material, and the material of the first dielectric film 61 is, for example, silicide.
  • the material of the first dielectric film 61 is SiO2, Si3N4, silicon oxynitride or oxygen-rich silicon dioxide.
  • the material of the first dielectric film 61 is different from that of the second sacrificial film 41 .
  • the material of the first dielectric film 61 is SiO2
  • the material of the second sacrificial film 41 is Si3N4.
  • the method of forming the first dielectric film 61 may be, for example, a CVD process to form the first dielectric film 61 .
  • the method of forming the second dielectric film 62 may be, for example, a CVD process to form the second dielectric film 62 .
  • the material of the second dielectric film 62 may be a dielectric material, and the material of the second dielectric film 62 is, for example, silicide.
  • the material of the second dielectric film 62 is SiO2, Si3N4, silicon oxynitride or oxygen-rich silicon dioxide.
  • the material of the first dielectric film 61 and the material of the second dielectric film 62 are different.
  • the material of the first dielectric film 61 is SiO2
  • the material of the second dielectric film 62 is Si3N4.
  • the material of the second sacrificial film 41 is Si3N4
  • the material of the first dielectric film 61 is SiO2
  • the material of the second dielectric film 62 is Si3N4.
  • the side surface of the second sacrificial film 41 is blocked by the first dielectric film 61 , which can avoid damage to the second sacrificial film 41 when the second dielectric film 62 is patterned.
  • a dry etching process may be used to pattern the second dielectric film 62 to form the second inner wall 63 .
  • a dry etching process may be used to pattern the first dielectric film 61 to form the first inner wall 64 .
  • the first inner wall 60 of the semiconductor structure includes an inner wall 1 64 and an inner wall 2 63 .
  • the first inner wall 60 exposes the first sacrificial film 31 .
  • the above-mentioned step S34 may not be performed, and the first dielectric film 61 and the first sacrificial film 31 are jointly used as a shielding oxide layer when the collector region 18 is subsequently formed.
  • the substrate 10 of the semiconductor structure is prepared.
  • the collector region 18 is located in the area enclosed by the STI region 13 , and the collector region 18 is in contact with the buried layer collector region 15 .
  • the emitter window is used as the self-alignment window
  • the first sacrificial film 31 is used as the screen oxide
  • the ion implantation process is used to form the collector area (collector) 18 through selective implantation.
  • the shielding oxide layer can protect the crystal lattice of the substrate 11 from being damaged, and the prepared collector region 18 and the window of the emitter region have a good positive effect.
  • the alignment effect between the emission region and the collector region 18 is good.
  • wet etching is used to remove the first sacrificial film 31 located under the second opening 42 to form the first opening 32 . Because wet etching is isotropic, if the material of the first inner wall 64 is the same as that of the first sacrificial film 31 (for example, both are SiO2), in the process of forming the first opening 32, the The first inner wall 64 below the second inner wall 63 will also be removed.
  • the etching amount of the first sacrificial film 31 can be controlled. That is to say, by controlling the etching time, the size of the first opening 32 can be controlled.
  • the contour of the second opening 42 falls within the contour of the first opening 32 .
  • the orthographic projection of the second opening 42 on the substrate 10 falls within the orthographic projection of the first opening 32 on the substrate 10 . That is, the first opening 32 is larger than the second opening 42 , and there is a cavity under the second sacrificial film 41 .
  • a selective epitaxy process may be used to selectively epitaxially grow the intrinsic base region 21 on the surface of the substrate 10 .
  • the material of the intrinsic base region 21 may include, for example, SiGe (silicon germanium), SiGe:C (silicon germanium carbon) alloy and the like.
  • the intrinsic base region 21 fills up the void.
  • the method for forming the second inner wall 70 may be the same as the above-mentioned method for forming the first inner wall 60 , and reference may be made to the above description of step S30 , which will not be repeated here.
  • the formed second inner wall 70 includes a third inner wall 71 and a fourth inner wall 72 .
  • the third inner wall 71 is arranged around the surface of the second sacrificial film 41 facing the second opening 42 and the surface of the auxiliary film 51 facing the third opening 52 , and the third inner wall 71 is L-shaped.
  • the fourth inner wall 72 is disposed on the third inner wall 71 and is not in direct contact with the intrinsic base 21 .
  • the material of the third inner wall 71 is the same as that of the above-mentioned first inner wall 64 , for example, the material of the third inner wall 71 is SiO2.
  • the material of the fourth inner wall 72 is the same as that of the above-mentioned second inner wall 63 , for example, the material of the fourth inner wall 72 is Si3N4.
  • the formed second inner wall 70 includes a third inner wall 71 . That is to say, after the third inner wall body 71 and the fourth inner wall body 72 are prepared by the same process as step S30, a step of removing the fourth inner wall body 72 is also included.
  • the opening of the emission area window is relatively large, and the finally formed emission area has a large area and low resistance.
  • step S40 is performed after the first inner wall 60 is formed, and when the ion implantation forms the collector region 18, ions will be implanted into the first inner wall 60, thereby affecting the isolation between the subsequently formed outer base region and the emitter region. Effect. Therefore, after the first inner wall 60 is removed and the second inner wall 70 is re-formed, the above problems can be solved and the isolation effect between the outer base region and the emission region can be improved.
  • the portion of the first inner wall 64 in contact with the first sacrificial film 31 is removed simultaneously, that is, the cross section of the first inner wall 64 is strip-shaped. As a result, the first inner wall body 64 cannot play an isolation role in this area.
  • the re-formed second inner wall 70 includes a third inner wall 71 that is L-shaped and covers a wide range, which can improve the isolation effect between the outer base area and the emission area.
  • wet etching may be used to clean the surface of the intrinsic base region 21 to remove the intrinsic oxide layer produced after the surface of the intrinsic base region 21 is oxidized.
  • step S70 is also performed, which causes the exposed surface of the intrinsic base region 21 to be easily oxidized to produce SiO2, which affects the electrical contact effect between the subsequently formed emitter region and the intrinsic base region 21 , leading to a higher resistance in the emitter region.
  • Cleaning the surface of the intrinsic base region 21 can remove the SiO2 on the surface of the intrinsic base region 21, thereby improving the electrical contact effect between the subsequently formed emitter region and the intrinsic base region 21, and facilitating the epitaxial growth of a single crystal material in the emitter region, It can effectively reduce the resistance of the emission area.
  • the material of the emitting region 80 can be, for example, doped epitaxial single crystal silicon or polycrystalline silicon, and the emitting region 80 can also be doped in situ to increase the doping concentration.
  • the semiconductor structure does not include a capping layer, or the capping layer is not formed simultaneously with the emitter region 80 . Then, forming the emission region 80 includes:
  • An emission region film 81 is formed, and the emission region film 81 covers the auxiliary film 51 and the second inner side wall 70 .
  • the emitter film 81 is then patterned to form the emitter region 80 .
  • the auxiliary film 51 may be patterned synchronously when the emitting region film 81 is patterned (the portion of the auxiliary film 51 not covered by the emitting region 80 is removed). That is, the emission region 80 and the auxiliary layer 50 are formed simultaneously.
  • the auxiliary film 51 may be patterned to form the auxiliary layer 50 by using a photolithography+dry etching process.
  • the emission region 80 and the capping layer 90 are formed simultaneously. Then, forming the emission region 80 includes:
  • the emitter region film 81 may be formed by using an epitaxial growth process.
  • the material of the emitter film 81 can be, for example, doped epitaxial monocrystalline silicon or polycrystalline silicon.
  • the material of the capping film 91 may be a dielectric material, and the material of the capping film 91 is, for example, silicide.
  • the material of the capping film 91 is silicon oxide, silicon nitride, silicon oxynitride, or oxygen-rich silicon dioxide.
  • a CVD process can be used to form the capping film 91 , and the capping film 91 covers the emission region film 81 .
  • the auxiliary film 51 , the emitter film 81 and the capping film 91 are patterned through photolithography and etching processes to expose the second sacrificial film 41 .
  • the patterning of the auxiliary film 51 , the emission region film 81 and the capping film 91 may be completed in multiple processes, or may be completed in the same process.
  • the specific patterns of the structures remaining after the auxiliary film 51 , the emitting region film 81 and the capping film 91 are patterned are not limited, and can be reasonably set as required.
  • first outer wall body 103 is arranged between the second outer wall body 104 and the launch area 80 , and the first outer wall body 103 and the second outer wall body 104 at least wrap around the sides of the launch area 80 .
  • the first outer wall body 103 and the second outer wall body 104 wrap side surfaces of the auxiliary layer 50 , the emitting area 80 and the capping layer 90 .
  • the method for forming the first outer wall 103 and the second outer wall 104 includes:
  • the way of forming the third dielectric film 101 can be formed by CVD process.
  • the material of the third dielectric film 101 may be a dielectric material, and the material of the third dielectric film 101 is, for example, silicide.
  • the material of the third dielectric film 101 is SiO2, Si3N4, silicon oxynitride, or oxygen-rich silicon dioxide.
  • the material of the third dielectric film 101 is different from that of the first sacrificial film 31 .
  • the material of the third dielectric film 101 is Si3N4, and the material of the first sacrificial film 31 is SiO2.
  • the first outer wall 103 formed by the third dielectric film 101 will not be removed, so as to ensure that the outer wall protects the emission region 21 .
  • the way of forming the fourth dielectric film 102 can be formed by CVD process.
  • the material of the fourth dielectric film 102 may be a dielectric material, and the material of the fourth dielectric film 102 is, for example, silicide.
  • the material of the fourth dielectric film 102 is SiO2, Si3N4, silicon oxynitride, or oxygen-rich silicon dioxide.
  • the material of the fourth dielectric film 102 is different from that of the second sacrificial film 41 .
  • the material of the fourth dielectric film 102 is SiO2
  • the material of the second sacrificial film 41 is Si3N4.
  • an etching process may be used to pattern the third dielectric film 101 and the fourth dielectric film 102 to form the first outer wall 103 and the second outer wall 104 .
  • the process of patterning the third dielectric film 101 and the fourth dielectric film 102 can be completed in the same process, or can be completed in multiple processes respectively.
  • the method for forming the extrinsic base region 22 includes:
  • an etching process may be used to remove the second sacrificial film 41 .
  • the two ends of the intrinsic base region 21 are exposed as seeds for forming the bridging region 221 .
  • a selective epitaxial process may be used to form the bridging region 221 .
  • the embodiment of the present application does not limit the size of the bridging region 221 , as long as the bridging region 221 is in contact with the intrinsic base region 21 .
  • the structure of the bridging region 221 shown in FIG. 3K is only a schematic, without any limitation.
  • the material of the bridging region 221 may include, for example, heavily doped monocrystalline silicon, and may also include a small amount of polycrystalline silicon.
  • an etching process may be used to remove the first sacrificial film 31 .
  • the surface of the substrate 10 is exposed, and the auxiliary extrinsic base region 17 is exposed.
  • the second outer wall 104 when the material of the second outer wall 104 is the same as that of the first sacrificial film 31 , the second outer wall 104 will be removed when the first sacrificial film 31 is removed.
  • the remaining first outer wall body 103 serves as the outer wall 100 of the semiconductor structure, and the outer wall 100 is used to protect the emission region 80 .
  • the extrinsic base film 222 can be formed at the position corresponding to the original first sacrificial film 31 by using a selective epitaxy process. That is, the extrinsic base film 222 is formed on the surface of the substrate 10 , and the extrinsic base film 222 directly contacts the auxiliary extrinsic base region 17 .
  • the material of the extrinsic base film 222 can be, for example, polysilicon or polysilicon silicide. In some embodiments, in-situ doping can also be performed on the outer base film 222 .
  • the formed extrinsic base film 222 may or may not be in contact with the intrinsic base region 21 . That is to say, the effective extrinsic base region 223 formed by the extrinsic base region film 222 may or may not be in contact with the intrinsic base region 21 .
  • the outer base film 222 can be patterned by using photolithography and etching processes.
  • the method for forming the extrinsic base region 22 includes: the auxiliary extrinsic base region 17 also serves as a seed layer of the extrinsic base region film 222 , and the extrinsic base region 22 is directly epitaxially produced on the auxiliary extrinsic base region 17 . Covering a layer of dielectric protection layer on the lead-out region 16 can ensure that the epitaxial growth of the outer base region 22 only grows on the auxiliary outer base region 17, and directly obtain the structure of S115, so that patterning such as lithography and etching of the outer base region can be omitted step.
  • the extrinsic base region 22 formed by the above method includes an effective extrinsic base region 223 and a bridging region 221, the effective extrinsic base region 223 is in contact with the bridging region 221, and the bridging region 221 is in contact with the intrinsic base region 21. , so that the extrinsic base region 22 is in contact with the intrinsic base region 21 . Since the material of the bridging region 221 is quasi-single crystal silicon, the activation rate of the dopant ions is greater than that of the effective extrinsic base region 223 (the material is polysilicon). Therefore, realizing the contact between the effective extrinsic base region 223 and the intrinsic base region 21 through the bridging region 221 can reduce the contact resistance between the extrinsic base region 22 and the intrinsic base region 21 .
  • the effective extrinsic base region 223 is in contact with the auxiliary extrinsic base region 17 on the surface of the substrate 10 .
  • the effective extrinsic base region 223 is in contact with the auxiliary extrinsic base region 17 , which is equivalent to increasing the thickness of the effective extrinsic base region 223 , which can be used as the elevation of the extrinsic base region 22 to reduce the resistance of the extrinsic base region 22 .
  • the method for forming the extrinsic base region 22 includes:
  • the formed extrinsic base region 22 directly overlaps the intrinsic base region 21, and the extrinsic base region 22 is in contact with the auxiliary extrinsic base region 17 on the surface of the substrate 10, which can be raised as the extrinsic base region 22, The extrinsic base region 22 resistance is reduced.
  • Heat treatment (such as annealing) is performed on the structure obtained in FIG. 3K or FIG. 3L to adjust the doping distribution in the emitter region 80 , the intrinsic base region 21 , the extrinsic base region 22 and the collector region 18 to activate dopant ions.
  • the emitter E is in contact with the emission region 80 through a contact hole (contact) 110 disposed on the surface of the emission region 80 .
  • the base B is in contact with the extrinsic base region 22 through the connection hole 110 provided on the surface of the extrinsic base region 22 .
  • the lead-out region 16 is in contact with the collector region 18 through the buried layer collector region 15
  • the collector C is in contact with the lead-out region 16 through the connection hole 110 provided on the surface of the lead-out region 16 , so that the collector C is in contact with the collector region 18 .
  • the communication hole 100 penetrates through the dielectric layer and contacts the emission region 80 , the extrinsic base region and the extraction region 16 .
  • the method for preparing a semiconductor structure provided in the embodiment of the present application is not limited to the above-mentioned steps, and other steps may be added or some of the above-mentioned steps may be reduced as required.
  • the order of the steps in the above preparation method is only an illustration, and can be adjusted and changed as needed.
  • the semiconductor structure obtained through the above steps S10-S130 is the HBT device. As shown in Figure 4A, the semiconductor structure includes:
  • Substrate 10 includes shallow trench isolation regions 13 and active regions 14 .
  • the active region 14 includes a buried collector region 15 , a lead-out region 16 and a collector region 18 .
  • the collector region 18 is embedded in the substrate 10 , and the surface of the collector region 18 is flush with the surface of the substrate 10 .
  • the collector region 18 is located in the active region 14 below the intrinsic base region 21 , and the trench isolation region 13 is disposed on the periphery of the active region 14 below the intrinsic base region 21 .
  • the lead-out region 16 is located on the side of the shallow trench isolation region 13 away from the collector region 18, the lead-out region 16 and the shallow trench isolation region 13 are located above the buried layer collector region 15, and the lead-out region 16 and the collector region 18 are respectively connected to the buried layer The collector area 15 contacts.
  • the substrate 10 when steps S18 , S19 - 1 and S19 - 2 are performed during the fabrication process, as shown in FIG. 3M , the substrate 10 further includes an auxiliary extrinsic base region 17 .
  • the auxiliary extrinsic base region 17 is disposed in the shallow trench isolation region 13 , and the surface of the auxiliary extrinsic base region 17 serves as a part of the surface of the substrate 10 .
  • the intrinsic base region 21 is disposed on the surface of the substrate 10 and is in contact with the collector region 18 on the surface of the substrate 10 to form a collector junction (C-B).
  • the material of the intrinsic base region 21 may be, for example, SiGe or SiGe:C.
  • the extrinsic base region 22 is disposed on the surface of the substrate 10 and is in contact with the auxiliary extrinsic base region 17 on the surface of the substrate 10 .
  • the extrinsic base region 22 is located on the periphery of the intrinsic base region 21 and is in contact with the intrinsic base region 21.
  • the material of the extrinsic base region 22 may be, for example, polysilicon.
  • step S111 to step S115 are performed to form the extrinsic base region 22 .
  • the extrinsic base region 22 includes a bridging region 221 and an effective extrinsic base region 223 , and the bridging region 221 is in contact with the intrinsic base region 21 and the effective extrinsic base region 223 respectively.
  • the bridging region 221 overlaps the intrinsic base region 21 , and the bridging region 221 overlaps the effective extrinsic base region 223 .
  • the bridging region 221 is disposed on the intrinsic base region 21 , and the bridging region 221 is spliced with the effective extrinsic base region 223 .
  • the contact modes of the bridge region 221 with the intrinsic base region 21 and the effective extrinsic base region 223 are also different.
  • the above is only an illustration, without any limitation.
  • the effective extrinsic base region 223 may not be in contact with the intrinsic base region 21 .
  • the effective extrinsic base region 223 may also be in contact with the intrinsic base region 21 .
  • step S111 ′ to step S114 ′ are performed to form the extrinsic base region 22 .
  • the extrinsic base region 22 does not include a bridging region, and the material of each part of the extrinsic base region 22 is the same.
  • the auxiliary layer 50 has an opening, and the auxiliary layer 50 is disposed on the extrinsic base region 22 .
  • the opening on the auxiliary layer 50 can be understood as the third opening 52 on the auxiliary film 51 during the above-mentioned manufacturing process.
  • the material of the auxiliary layer 50 can be, for example, SiO2.
  • the emitter region 80 is disposed on the auxiliary layer 50 and contacts the intrinsic base region 21 through the opening to form an emitter junction (E-B).
  • the material of the emitter region 80 can be, for example, doped epitaxial monocrystalline silicon or polycrystalline silicon.
  • the inner wall is arranged between the extrinsic base region 22 and the emitting region 80 , and can also extend to between the auxiliary layer 50 and the emitting region 80 , for isolating the extrinsic base region 22 and the emitting region 80 .
  • the above step S70 is performed during the preparation of the semiconductor structure. Then, the inner wall in the semiconductor structure may be the above-mentioned second inner wall 70 .
  • the second inner wall 70 may include a third inner wall 71 and a fourth inner wall 72 .
  • the second inner wall 70 may also only include the third inner wall 71 .
  • the inner wall includes an L-shaped portion (third inner wall body 71 ).
  • the material of the third inner wall 71 can be, for example, SiO2
  • the material of the fourth inner wall 72 can be, for example, Si3N4.
  • the above step S70 is not performed during the preparation of the semiconductor structure.
  • the inner wall in the semiconductor structure may be the above-mentioned first inner wall 60 .
  • first inner wall 60 may include a first inner wall 64 and a second inner wall 63 .
  • the first inner wall 60 may also only include the first inner wall 64 .
  • the material of the first inner wall 64 can be, for example, SiO2, and the material of the second inner wall 63 can be, for example, Si3N4.
  • the capping layer 90 covers the surface of the emission region 80 away from the substrate 10 for protecting the emission region 80 .
  • the material of the capping layer 90 may be SiO2, for example.
  • the outer wall 100 wraps the side of the launch area 80 for protecting the launch area 80 .
  • the outer wall 100 can be the first outer wall body 103 in the above preparation process.
  • the material of the outer wall 100 may be, for example, Si3N4.
  • the collector electrode C is in contact with the lead-out region 16 , the buried layer collector region 15 and the collector region 18 through the connection hole 100 in contact with the lead-out region 16 .
  • the connection hole 100 may be directly disposed on the surface of the lead-out region 16 , and a metal silicide layer may also be disposed between the connection hole 100 and the lead-out region 16 to realize the contact between the connection hole 100 and the lead-out region 16 .
  • the emitter electrode E is in contact with the emitter region 80 through the connection hole 100 passing through the cap layer 90 and in contact with the emitter region 80 .
  • the connection hole 100 may be directly disposed on the surface of the emission region 80 , and a metal silicide layer may also be disposed between the connection hole 100 and the emission region 80 to realize the contact between the connection hole 100 and the emission region 80 .
  • the base B is in contact with the extrinsic base region 22 through the connection hole 100 in contact with the extrinsic base region 22 .
  • the connection hole 100 can be directly disposed on the surface of the extrinsic base region 22 , and a metal silicide layer can also be disposed between the connection hole 100 and the extrinsic base region 22 to realize the contact between the connection hole 100 and the extrinsic base region 22 .
  • connection hole 100 must pass through the dielectric layer.
  • the emitter E is used to emit electrons
  • the base B is used to control electrons (the current flowing to the collector C is controlled by the input signal of the base B)
  • the collector C is used to collect electrons.
  • the SiGe HBT transistor in the above-mentioned semiconductor structure can be an NPN transistor (the intrinsic base region 21 is a P region, that is, a P-type semiconductor; the emitter region 80 and the collector region 18 are both N regions, that is, an N region. type semiconductor) or PNP transistor (the intrinsic base region 21 is an N region, that is, an N-type semiconductor; the emitter region 80 and the collector region 18 are both P regions, that is, a P-type semiconductor).
  • the structure, position, and quantity of the emitter E, base B, and collector C shown in the schematic diagram of the embodiment of the present application are only for illustration. There may be only one emitter E, base B, and collector C, and there may be one base B and one collector C on the left and right sides of the emitter E.
  • the material of the film layer in FIG. 3M is only an illustration, without any limitation.
  • the working principle of the SiGe HBT device provided in the embodiment of the present application is described: power is applied to the emitter junction, the emitter junction is forward-biased, and the majority carriers (free electrons) in the emitter region 80 continuously Across the emitter junction and into the intrinsic base region 21, an emitter current is formed. After electrons enter the intrinsic base region 21, they are densely concentrated near the emitter junction, and gradually form an electron concentration difference. The junction electric field pulls into the collector region 18 creating a collector current.
  • the method for preparing a semiconductor structure uses the first sacrificial film 31, the second sacrificial film 41 and the auxiliary film 51 as a self-aligned structure, which can be used to realize the self-alignment of the collector junction (C-B) and the emitter junction (E-B) Self-alignment.
  • the prepared collector junction and emitter junction have an axisymmetric structure, and there will be no deviation like photolithography and etching processes, resulting in asymmetry of the collector junction and emitter junction.
  • the asymmetry of the emitter junction leads to the difference between the parasitic collector junction capacitance and the base region resistance on both sides of the emitter junction midline, which cannot share the current on both sides, resulting in the inability to minimize the total resistance and capacitance. Symmetry on both sides can minimize the base resistance and collector junction capacitance, thereby increasing the highest oscillation frequency of the device.
  • the asymmetry of the collector junction leads to different parasitic collector resistances on both sides, which also fails to minimize the collector resistance.
  • the preparation of each film layer can be realized by using conventional techniques.
  • the formation of the collector region 18 is also realized by defining the position of the self-aligned structure, and then performing ion implantation in the substrate 10 .
  • both the intrinsic base region 21 and the extrinsic base region 22 are disposed on the surface of the substrate 10 , the collector region 18 is disposed inside the substrate 10 , and there is no raised epitaxial collector region, therefore.
  • the intrinsic base region 21 and the extrinsic base region 22 are directly formed on the known surface of the substrate 10 , and whether the two are in contact is directly controllable through its own preparation process. Compared with setting an epitaxial collector region on the surface of the substrate 10 and then setting an intrinsic base region on the epitaxial collector region.
  • the intrinsic base region 21 is directly provided on the surface of the substrate 10, and the contact between the intrinsic base region 21 and the extrinsic base region 22 will not be affected by parameters such as the thickness of the raised epitaxial collector region, and the intrinsic base region 21 can be improved.
  • the contact yield of the base region 21 and the outer base region 22 is improved, thereby improving the yield of the semiconductor structure.
  • the collector region 18 is obtained by doping, and one step of epitaxial process (preparation of the collector region 18 ) is omitted, which saves processing cost.
  • an auxiliary extrinsic base region 17 is set in the substrate 10, and the auxiliary extrinsic base region 17 is used as a seed layer for the epitaxial growth of the extrinsic base region 22, and after the extrinsic base region 22 is grown, it contacts with the extrinsic base region 22 to realize the extrinsic base region 22, so that the purpose of reducing the resistance of the extrinsic base region can be achieved.
  • the semiconductor structure further includes a complementary metal oxide semiconductor field-effect transistor (complementary metal oxide semiconductor field-effect transistor, CMOSFET).
  • CMOSFET complementary metal oxide semiconductor field-effect transistor
  • the manufacturing method of the semiconductor structure further includes: S140 , forming a CMOSFET on the substrate 11 .
  • step of forming a CMOSFET on the substrate 11 may be performed before step S10, or may be performed after step S130.
  • the SiGe HBT structure and the CMOSFET structure are isolated by a deep trench isolation region 19 in the substrate 10 .
  • CMOSFETs can be NMOS transistors or PMOS transistors.
  • the semiconductor structure prepared by the semiconductor structure preparation method is a CMOS+SiGe HBT device, and CMOS and SiGe HBT can be integrated on the same chip.
  • the transistor circuit can be directly packaged with a package body to form a packaged device (such as a chip). It can also be packaged together with other chips to form a packaged device.
  • a packaged device such as a chip
  • This embodiment of the present application does not limit it.
  • a transistor circuit including any one of the above-mentioned semiconductor structures can be applied to a radio frequency circuit.
  • radio frequency circuits can be used in microwave systems, optoelectronic systems, radar, imaging and sensing fields, etc.
  • the radio frequency circuit can be, for example, a power amplifier (power amplifier, PA), a variable gain amplifier (variable gain amplifier, VGA), a low noise amplifier (low noise amplifier, LNA), a transimpedance amplifier (trans-impedance amplifier, TIA), a driver (driver), mixer, clock data recovery (clock data recovery, CDR) circuit, etc.
  • the embodiment of the present application does not limit the scope of application of the above semiconductor structure, for example, it may be applied to any communication device, and the communication device may be a network device or a terminal.

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Abstract

本申请实施例提供一种半导体结构及其制备方法、射频电路，涉及半导体技术领域，旨在提供一种工艺相对简单并具有较大潜力实现高性能的SiGe HBT器件结构。半导体结构包括：衬底，包括埋藏于衬底内的集电区；本征基区，设置在衬底的表面，与集电区在衬底的表面接触；外基区，设置在衬底的表面，位于本征基区的外围，与本征基区接触；辅助层，具有开口；辅助层设置在外基区上；发射区，设置在辅助层上，通过开口与本征基区接触；内侧墙，设置在外基区与发射区之间。

Description

半导体结构及其制备方法、射频电路 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法、射频电路。
背景技术
传统的硅基互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)工艺成本低，且通过先进的工艺节点，CMOS器件可以达到较高的频率响应，适合高频应用。但是同样频率响应的器件，CMOS器件击穿电压小，而硅锗异质结双极晶体管(SiGe heterojunction bipolar transistor，SiGe HBT)则拥有较高的击穿电压，适合较高输出功率应用。同时SiGe HBT相比CMOS器件具有更高的跨导，按照最新的半导体模拟工具(Technology Computer Aided Design，TCAD)仿真预测，SiGe HBT器件电流增益截止频率极限为1THz，功率增益截止频率极限为2THz，使其很长一段时间内能满足高频高速的应用需求。而GaAs(砷化镓)、InP(磷化铟)等Ⅲ-Ⅴ族材料的电子与空穴迁移率比硅高得多，具有极佳的高频特性，同时因其禁带宽度高，具有相比于SiGe HBT更高的击穿电压，同样适合用于高频，高功率应用。但是Ⅲ-Ⅴ族材料存在着造价高、环保成本高、热传导性差，机械性能差等缺点。
将CMOS和SiGe HBT集成在同一芯片上(CMOS+SiGe，SiGe BiCMOS)，SiGe HBT高频、高速、高增益、低噪声等优势适合模拟电路设计，而CMOS低功耗优势适合数字逻辑电路，两者的整合满足数模混合电路设计要求，使得SiGe BiCMOS相比于Ⅲ-Ⅴ族材料具有成本低，高集成度优点。
随着5G通信逐渐普及，SiGe BiCMOS在光电高速传输、微波高频、雷达、影像和传感领域应用中发挥越来越重要的作用，SiGe HBT可用于制作光电跨阻放大器、驱动器、时钟数据恢复(clock data recovery，CDR)、微波低噪声放大器、混频器、功率放大器等不同的射频电路。
如何采用相对简单的工艺实现更高频率响应的SiGe HBT器件，成为当下SiGe工艺工程师持续追求的目标。
发明内容
本申请实施例提供一种半导体结构及其制备方法、射频电路，用于解决高性能HBT制备工艺复杂、成本高的问题。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种半导体结构，包括：衬底，包括埋藏于衬底内的集电区；本征基区，设置在衬底的表面，与集电区在衬底的表面接触；外基区，设置在衬底的表面，位于本征基区的外围，与本征基区接触；辅助层，具有开口；辅助层设置在外基区上；发射区，设置在辅助层上，通过开口与本征基区接触；内侧墙，设置在外基区与发射区之间。
本申请实施例提供的半导体结构，本征基区和外基区均设置在衬底的表面，集电 区设置在衬底的内部，不存在位于衬底表面的抬高外延集电区。因此。在已知的衬底表面直接形成本征基区和外基区，二者是否接触是通过自身的制备工艺直接可控的。与衬底表面设置外延集电区，然后在外延集电区上设置本征基区相比。本申请实施例直接在衬底表面设置本征基区，不会因为抬高的集电区的厚度等参数而影响本征基区和外基区的接触，可提高本征基区和外基区的接触良率，从而提高半导体结构的良率。另外，由于无需考虑集电区厚度对本征基区和外基区接触效果的影响。因此，可降低对制作集电区时工艺精度的要求，降低工艺难度。且集电区是掺杂得到的，少了一步外延工艺(制备集电区)，节省加工成本。
在一些实施例中，衬底还包括浅沟槽隔离区，浅沟槽隔离区设置在本征基区下方的有源区的外围；集电区位于有源区内。集电区和浅沟槽隔离区均位于衬底内，不存在抬高的外延集电区，不会因为集电区的厚度等参数而影响本征基区和外基区的接触，可提高本征基区和外基区的接触良率，从而提高半导体结构的良率。
在一些实施例中，衬底还包括辅助外基区，辅助外基区设置在浅沟槽隔离区内；外基区与辅助外基区在衬底的表面接触。在衬底中设置辅助外基区，辅助外基区作为外基区外延生长的种子层，在外基区长成后，与外基区接触，实现外基区的增厚，从而可以实现降低外基区电阻的目的。
在一些实施例中，外基区包括桥接区和有效外基区，桥接区与本征基区和有效外基区分别接触。这样一来，有效外基区与桥接区接触，桥接区与本征基区接触，从而实现外基区与本征基区接触。由于桥接区材料为准单晶硅，其掺杂离子的激活率大于有效外基区(材料为多晶硅)掺杂离子的激活率。因此，通过桥接区实现有效外基区与本征基区的接触，可减小外基区与本征基区的接触电阻。
在一些实施例中，桥接区与本征基区和/或有效外基区搭接。以搭接的方式实现接触，可降低对工艺精度的要求，减小工艺难度。
在一些实施例中，半导体结构还包括外侧墙；外侧墙包裹发射区的侧面，用于保护发射区。外侧墙在半导体结构制备过程中可以对发射区起到保护作用，避免其他外延步骤对发射区产生影响。
在一些实施例中，半导体结构还包括盖帽层，盖帽层覆盖发射区远离衬底的表面，用于保护发射区。外侧墙在半导体结构制备过程中可以对发射区起到保护作用，避免其他外延步骤对发射区产生影响。
在一些实施例中，内侧墙包括内墙体，内墙体设置在外基区朝向发射区的表面上；内墙体为L状。L状的内墙体，覆盖范围广，可提高外基区和发射区之间的隔离效果。
在一些实施例中，半导体结构还包括设置在衬底上的发射极、基极以及集电极；发射极与发射区接触，基极与外基区接触，集电极与集电区接触。
在一些实施例中，衬底还包括引出区和埋层集电区，引出区和浅沟槽隔离区位于埋层集电区的上方，引出区位于浅沟槽隔离区远离集电区一侧；引出区和集电区分别与埋层集电区接触；集电极通过与引出区接触连接孔和集电区接触；发射极通过穿过盖帽层且与发射区接触的连接孔，和发射区接触；基极通过与外基区接触的连接孔和外基区接触。
在一些实施例中，半导体结构还包括互补金属氧化物半导体场效应晶体管，互补 金属氧化物半导体场效应晶体管设置在衬底上。这样一来，半导体结构为CMOS+SiGe HBT器件，可将CMOS和SiGe HBT集成在同一芯片上，可兼得二者的优势。
本申请实施例的第二方面，提供一种射频电路，包括包含第一方面半导体结构的晶体管电路。
本申请实施例的第三方面，提供一种半导体结构的制备方法，包括：形成基底，基底包括有源区和浅沟槽隔离区；在基底的表面上形成依次层叠设置的第一牺牲膜、第二牺牲膜以及辅助膜，在第二牺牲膜上形成第二开口，在辅助膜上形成第三开口，第二开口和第三开口连通作为发射区窗口；形成第一内侧墙，第一内侧墙绕第二牺牲膜朝向发射区窗口的表面一圈设置；形成集电区，集电区位于发射区窗口正下方的有源区内；在第一牺牲膜上形成第一开口，第一开口与第二开口连通；在第一开口内形成本征基区；在发射区窗口处形成与本征基区接触的发射区膜，对发射区膜和辅助膜进行图案化，形成发射区和辅助层；去除第一牺牲膜和第二牺牲膜，在对应位置处形成外基区；外基区与本征基区接触。
本申请实施例提供的半导体结构的制备方法，采用第一牺牲膜、第二牺牲膜以及辅助膜作为自对准结构，可用于实现集电结的自对准和发射结的自对准。这样一来，制备得到的集电结和发射结为轴对称结构，不会像采用光刻和刻蚀工艺那样会有偏差，导致集电结和发射结不对称。而发射结不对称，导致发射结中线两侧的寄生集电结电容和基区电阻不同，起不到两边均分电流的作用，导致总电阻和电容不能最小化。而两边对称，则可以起到最小化基区电阻和集电结电容作用，从而提高器件的最高振荡频率。集电结不对称，导致两侧寄生集电极电阻不同，同样无法起到最小化集电极电阻的目的。而且，本申请实施例中，每层膜层的制备，采用常规技术即可实现。集电区的形成，也是通过自对准结构限定位置，然后在衬底中进行离子注入来实现的。本征基区和外基区均设置在衬底的表面，不存在抬高的外延集电区，因而也不会因为集电区的厚度等参数而影响本征基区和外基区的接触，降低对工艺精度的要求，降低工艺难度。且少了一步外延工艺，节省加工成本。
在一些实施例中，形成基底，还包括：在浅沟槽隔离区内形成辅助外基区，外基区与辅助外基区在基底的表面接触。在衬底中设置辅助外基区，辅助外基区作为外基区外延生长的种子层，在外基区长成后，与外基区接触，实现外基区的增厚，从而可以实现降低外基区电阻的目的。
在一些实施例中，去除第二牺牲膜和第一牺牲膜，在对应位置处形成外基区，包括：去除第二牺牲膜，并在辅助层下方形成桥接区；桥接区与本征基区接触；去除第一牺牲膜，在对应位置处形成有效外基区，有效外基区与桥接区接触。这样一来，有效外基区与桥接区接触，桥接区与本征基区接触，从而实现外基区与本征基区接触。由于桥接区材料为准单晶硅，其掺杂离子的激活率大于有效外基区(材料为多晶硅)掺杂离子的激活率。因此，通过桥接区实现有效外基区与本征基区的接触，可减小外基区与本征基区的接触电阻。
在一些实施例中，第二开口的轮廓落在第一开口的轮廓内。这样一来，后续形成的桥接区与本征基区和/或有效外基区搭接，以搭接的方式实现接触，可降低对工艺精度的要求，减小工艺难度。
在一些实施例中，在发射区窗口处形成与本征基区接触的发射区之前，制备方法还包括：去除第一内侧墙，形成第二内侧墙。由于形成第一内侧墙后，离子注入形成集电区时，会有离子注入第一内侧墙内，从而影响后续形成的外基区和发射区之间的隔离效果。因此，去除第一内侧墙，重新形成第二内侧墙后，可解决上述问题，提高外基区和发射区之间的隔离效果。此外，在形成第一开口的过程中，会同步去掉第一内墙体与第一牺牲膜接触的部分，也就是说，第一内墙体的截面为条状。这就导致第一内墙体在该区域无法起到隔离作用。而重新形成的第二内墙体，其所包括的第三内墙体为L状，覆盖范围广，可提高外基区和发射区之间的隔离效果。
在一些实施例中，形成第二内侧墙后，制备方法还包括：对本征基区进行表面清洗，去除本征氧化层。由于形成本征基区后，还执行了去除第一内侧墙，形成第二内侧墙的步骤，这就导致本征基区的暴露面容易被氧化产生SiO2，而影响后续形成的发射区与本征基区的电性接触效果，导致发射区电阻较高。对本征基区进行表面清洗，可去除本征基区表面的SiO2，从而提高后续形成的发射区与本征基区的电性接触效果，并有利于发射区外延出单晶材质，可有效降低发射区电阻。
在一些实施例中，制备方法还包括：在基底上形成互补金属氧化物半导体场效应晶体管。这样一来，制备得到的半导体结构为CMOS+SiGe HBT器件，可将CMOS和SiGe HBT集成在同一芯片上，可兼得二者的优势。
附图说明
图1为本申请实施例提供的一种半导体结构的制备过程图；
图2为本申请实施例提供的一种半导体结构的制备流程图；
图3A-图3M为本申请实施例提供的另一种半导体结构的制备过程图；
图4A为本申请实施例提供的一种半导体结构的结构示意图；
图4B为本申请实施例提供的另一种半导体结构的结构示意图；
图5A为本申请实施例提供的又一种半导体结构的结构示意图；
图5B为本申请实施例提供的又一种半导体结构的结构示意图；
图6为本申请实施例提供的又一种半导体结构的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或 “一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在本申请实施例中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
硅锗异质结双极晶体管(SiGe heterojunction bipolar transistor，SiGe HBT)因其具有更好的热导率和良好的衬底机械性能，较好地解决了半导体结构的散热问题。而且SiGe HBT还具有更好的线性度、更高集成度，和互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)技术有良好的兼容性。因此，广泛的应用于光电、射频、微波等领域中，尤其在上述领域的高频器件中的应用更为凸显。例如，一些利用光电高速传输技术和微波高频技术的高频模拟器件，采用SiGe BiCMOS结构得到的高频模拟器件兼具了SiGe HBT结构速度块、增益高、噪声低，CMOS器件功耗低的优势。
然而，如何采用简单的工艺制备得到高性能的SiGe HBT结构，成为本领域技术人员持续研究的技术问题。
在一些实施例中，如图1所示，提供一种半导体结构的制备方法，先限定发射区窗口；然后在衬底10上采用选择性外延(selective epitaxy growth，SEG)工艺，在发射区窗口内形成集电区；然后在集电区上采用选择性外延工艺，在发射区窗口内形成本征基区以及发射区膜；然后进行后续发射区和外基区等结构的制备。如图1所示，通过上述制备方法制备得到的半导体结构，集电区、本征基区和发射区均设置在衬底上方。
采用上述方法制备半导体结构，采用将集电区、本征基区和发射区生长于同一发射区窗口内的全自对准工艺，制备得到的半导体结构具有自对准结构的优点。但是， 由于其集电区采用的也是选择性外延工艺，导致制备成本增加。而且，在外延形成集电区的过程中，集电区的高度控制决定本征基区与外基区的相对位置。如图1所示，本征基区和外基区是通过桥接区接触的，若集电区高度不合适，会导致设置在集电区上的本征基区与桥接区接触太少或者接触不上，从而影响本征基区与外基区的连接电阻。也就是说，集电区的高度，决定本征基区与桥接区的相对位置，直接影响本征基区和外基区的连接电阻，从而影响器件的性能。这就导致制备半导体结构的过程中，对工艺精度的要求较高。若工艺精度达不到，制备出的半导体结构的性能会受到很大的影响。
基于此，本申请实施例还提供一种半导体结构的制备方法，如图2所示，包括：
S10、如图3A所示，形成基底11。
在一些实施例中，关于基底11的形成方法，如图3A所示，包括：
S11、在硅底12上形成外延层，对外延层进行离子注入，形成埋层集电区15和引出区(sinker)16。
其中，埋层集电区15的离子注入是在STI开口前完成的，可以在形成外延层之前植入，然后通过高温扩散到外延层。也可以是形成外延层之后，进行离子注入得到。上述形成埋层集电区15的顺序仅为一种示意，不做任何限定。
当然，在形成埋层集电区15和引出区16之前，可以形成屏蔽氧化层(screen oxide)。这样一来，屏蔽氧化层可保护硅底12的晶格不被破坏。在形成埋层集电区15和引出区16之后，可以去除屏蔽氧化层，再进行后续步骤。
当然，硅底12上也可以不形成外延层，那么埋层集电区15和引出区16位于硅底12中。本申请实施例中以在硅底12上形成外延层为例进行示意。
S12、在外延层上形成二氧化硅(SiO2)膜和氮化硅(Si3N4)膜。
S13、在外延层上形成浅沟槽隔离(shallow trench isolation，STI)开口。
例如，通过光刻和干法蚀刻形成STI开口。当然，也可以是其他工艺。S14、氧化和修复STI开口的表面，形成二氧化硅界面。
S15、在STI开口内填充电介质材料，形成填充层。
其中，电介质材料例如是SiO2或其它场效氧化物。电介质材料可以覆盖Si3N4膜，也可以不覆盖Si3N4膜，但必须填满STI开口。
S16、对填充层进行处理，形成浅沟槽隔离(shallow trench isolation，STI)区13。
例如，可以利用化学机械抛光(chemical mechanical polishing，CMP)工艺，对填充层进行研磨，停留在Si3N4膜层。
S17、去除Si3N4膜，形成基底11。
例如，可以采用湿法刻蚀去除Si3N4膜。这样一来，外延层中填充有SiO2的区域为STI区13，其余区域为基底11的有源区14。
在一些实施例中，执行完步骤S17后，基底11的制备基本完成，之后可以执行S18＇、去除多余的SiO2膜，暴露出基底11的硅表面。
基于此，得到的基底11如图3A所示，基底11包括硅底12、设置在硅底12上的外延层，外延层中划分有STI区13、有源区14、埋层集电区15以及引出区16，引出区16和STI区13位于埋层集电区15的上方，引出区16与埋层集电区15接触。
在另一些实施例中，如图3B所示，执行完步骤S17后，形成基底11的步骤还包括：在STI区13内形成辅助外基区21。
示例的，在STI区13内形成辅助外基区21的步骤包括：
S18、在待形成外基区区域下方的STI区13内形成凹槽。
例如，通过光刻和干法蚀刻在STI区13内形成凹槽。
S19-1、在基底11的表面形成多晶硅膜。
例如，可以通过外延工艺形成多晶硅膜，也可以使用化学气相沉积(chemical vapor deposition，CVD)工艺形成多晶硅膜。
其中，多晶硅膜的材料可以是多晶硅或多晶硅硅化物等。
在一些实施例中，还可以在形成多晶硅膜后，对多晶硅膜进行掺杂。可以对多晶硅膜进行原位掺杂，也可以是先形成多晶硅膜后用离子注入实现掺杂。
S19-2、对多晶硅膜进行图案化，并去除基底11表面多余的SiO2膜，形成位于STI区13中凹槽内的辅助外基区17。
例如，可以以SiO2膜为阻挡层，采用CMP工艺，对多晶硅膜进行研磨，去除位于凹槽外的多晶硅膜。可以用湿法刻蚀，也可以用干法刻蚀去除多余的SiO2膜。
在一些实施例中，辅助外基区17的表面高于STI区13的表面。
在另一些实施例中，如图3B所示，辅助外基区17的表面与STI区13的表面平齐。
例如，可以利用CMP工艺对基底11进行研磨，实现辅助外基区17的表面与STI区13的表面平齐。视觉效果上等效于STI区13填埋辅助外基区17。当然，工艺误差范围内的高度差，均属于本申请实施例的保护范围。
S20、如图3C所示，形成发射区窗口。
在一些实施例中，形成发射区窗口的方式，包括：
S21、如图3C所示，在基底11的表面上形成依次层叠设置的第一牺牲膜31、第二牺牲膜41以及辅助膜51。
其中，第一牺牲膜31和辅助膜51的材料相同，第一牺牲膜31和第二牺牲膜41的材料不同。
例如，第一牺牲膜31、第二牺牲膜41以及辅助膜51的材料例如均可以为硅化物。
示例的，第一牺牲膜31和辅助膜51的材料为含硅氧化物。例如，第一牺牲膜31和辅助膜51的材料为SiO2、氮氧化硅或富氧二氧化硅等。
示例的，第二牺牲膜41的材料为含硅氮化物。例如，第二牺牲膜41的材料为Si3N4。
形成第一牺牲膜31、第二牺牲膜41以及辅助膜51的方式，例如可以采用化学气相沉积(chemical vapor deposition，CVD)工艺形成第一牺牲膜31、第二牺牲膜41以及辅助膜51。
S22、如图3C所示，在辅助膜51上形成第三开口52；在第二牺牲膜41上形成第二开口42。
例如，可以通过光刻和刻蚀工艺在辅助膜51上形成第三开口52。可以通过光刻和刻蚀工艺在第二牺牲膜41上形成第二开口42。
其中，形成第三开口52和第二开口42可以是分两次工艺完成，也可以是在同一 次工艺中完成，本申请实施例对此不做限定。
如图3C所示，形成的第二开口42和第三开口52连通作为发射区窗口，发射区窗口底部还保留有第一牺牲膜31，未直接与基底11连通。
在一些实施例中，如图3C所示，第二开口42和第三开口52正对设置，且大小相同。或者理解为，第二开口42在基底11上的正投影和第三开口52在基底11上的正投影重合。
S30、如图3D所示，形成第一内侧墙60。
其中，形成的第一内侧墙60绕第二牺牲膜41朝向第二开口42(发射区窗口)的表面一圈设置。
在一些实施例中，如图3D所示，形成的第一内侧墙60还延伸至辅助膜51朝向第三开口52的表面上。
在一些实施例中，形成第一内侧墙60的方式，包括：
S31、如图3D所示，在辅助膜51的表面形成第一介质膜61，第一介质膜61在发射区窗口处形成凹槽U。
其中，第一介质膜61的材料可以是介质材料，第一介质膜61的材料例如为硅化物。示例的，第一介质膜61的材料为SiO2、Si3N4、氮氧化硅或富氧二氧化硅等。
在一些实施例中，第一介质膜61的材料与第二牺牲膜41的材料不同。例如，第一介质膜61的材料为SiO2，第二牺牲膜41的材料为Si3N4。
形成第一介质膜61的方式，例如可以采用CVD工艺形成第一介质膜61。
S32、如图3D所示，在第一介质膜61上形成第二介质膜62。
形成第二介质膜62的方式，例如可以采用CVD工艺形成第二介质膜62。
其中，第二介质膜62的材料可以是介质材料，第二介质膜62的材料例如为硅化物。示例的，第二介质膜62的材料为SiO2、Si3N4、氮氧化硅或富氧二氧化硅等。
在一些实施例中，第一介质膜61的材料和第二介质膜62的材料不同。例如，第一介质膜61的材料为SiO2，第二介质膜62的材料为Si3N4。
也就是说，在一些实施例中，第二牺牲膜41的材料为Si3N4，第一介质膜61的材料为SiO2，第二介质膜62的材料为Si3N4。
这样一来，有第一介质膜61对第二牺牲膜41的侧面进行阻隔，可以避免在对第二介质膜62进行图案化时，对第二牺牲膜41进行损坏。
S33、如图3D所示，对第二介质膜62进行图案化，形成第二内墙体63，第二内墙体63覆盖凹槽U的侧面。
例如，可以采用干法刻蚀工艺，对第二介质膜62进行图案化，形成第二内墙体63。
S34、如图3D所示，去除第一介质膜61的未被第二内墙体63覆盖的部分，形成第一内墙体64。
例如，可以采用干法刻蚀工艺，对第一介质膜61进行图案化，形成第一内墙体64。
基于此，如图3D所示，半导体结构的第一内侧墙60包括内墙体一64和内墙体二63。第一内侧墙60露出第一牺牲膜31。
当然，也可以不执行上述步骤S34，在后续形成集电区18时，使第一介质膜61和第一牺牲膜31共同作为屏蔽氧化层。
S40、如图3E所示，形成集电区18，集电区18位于发射区窗口下方的有源区14内。
如图3E所示，执行步骤S40后，半导体结构的衬底10制备完成。集电区18位于STI区13围成的区域内，集电区18与埋层集电区15接触。
以发射区窗口作为自对准窗口，以第一牺牲膜31作为屏蔽氧化层(screen oxide)，采用离子注入工艺，选择性注入(selected implanted)形成集电区(collector)18。这样一来，屏蔽氧化层可保护基底11的晶格不被破坏，而且制备得到的集电区18与发射区窗口正对效果好。后续在发射区窗口形成发射区后，发射区与集电区18的对准效果好。
S50、如图3F所示，在第一牺牲膜31上形成第一开口32，第一开口32与第二开口42连通。
例如，利用湿法刻蚀去除位于第二开口42下方的第一牺牲膜31，形成第一开口32。因湿法刻蚀是各向同性，若第一内墙体64的材料与第一牺牲膜31的材料相同(例如均为SiO2)的情况下，在形成第一开口32的过程中，位于第二内墙体63下方的第一内墙体64也会被去除。
应当明白的是，通过控制刻蚀时间，可以控制对第一牺牲膜31的刻蚀量。也就是说，通过控制刻蚀时间，可以控制第一开口32的大小。
在一些实施例中，为了提高后续制备出的外基区和本征基区的接触效果，如图3F所示，第二开口42的轮廓落在第一开口32的轮廓内。或者理解为，第二开口42在衬底10上的正投影落在第一开口32在衬底10上的正投影内。也就是说，第一开口32比第二开口42大，第二牺牲膜41下方具有空洞。
S60、如图3G所示，在第一开口32内形成本征基区21。
例如，可以采用选择性外延工艺，在衬底10的表面选择性外延生长本征基区21。本征基区21的材料，例如可以包括SiGe(硅锗)、SiGe:C(硅锗碳)合金等。
其中，如图3G所示，在第二牺牲膜41下方具有空洞的情况下，本征基区21填满上述空洞。
S70、如图3H所示，去除第一内侧墙60，形成第二内侧墙70。
形成第二内侧墙70的方法，可以与上述形成第一内侧墙60的方法相同，可参考上述关于步骤S30的描述，此处不再赘述。
在一些实施例中，如图3H中的(a)图所示，形成的第二内侧墙70包括第三内墙体71和第四内墙体72。第三内墙体71绕第二牺牲膜41朝向第二开口42的表面和辅助膜51朝向第三开口52的表面一圈设置，且第三内墙体71为L状。第四内墙体72设置在第三内墙体71上，未直接与本征基区21接触。
示例的，第三内墙体71的材料与上述第一内墙体64的材料相同，例如第三内墙体71的材料为SiO2。第四内墙体72的材料与上述第二内墙体63的材料相同，例如第四内墙体72的材料为Si3N4。
在另一些实施例中，如图3H中的(b)图所示，形成的第二内侧墙70包括第三 内墙体71。也就是说，在采用与步骤S30相同的工艺制备得到第三内墙体71和第四内墙体72后，还包括去除第四内墙体72的步骤。
第二内侧墙70仅包括单层内墙体的情况下，发射区窗口的开口较大，最终形成的发射区的面积大，电阻小。
由于形成第一内侧墙60后，执行了步骤S40，而离子注入形成集电区18时，会有离子注入第一内侧墙60内，从而影响后续形成的外基区和发射区之间的隔离效果。因此，去除第一内侧墙60，重新形成第二内侧墙70后，可解决上述问题，提高外基区和发射区之间的隔离效果。此外，在形成第一开口32的过程中，会同步去掉第一内墙体64与第一牺牲膜31接触的部分，也就是说，第一内墙体64的截面为条状。这就导致第一内墙体64在该区域无法起到隔离作用。而重新形成的第二内墙体70，其所包括的第三内墙体71为L状，覆盖范围广，可提高外基区和发射区之间的隔离效果。
S80、对本征基区21进行表面清洗。
例如，可以采用湿法刻蚀，对本征基区21进行表面清洗，去除本征基区21表面被氧化后所产生的本征氧化层。
由于形成本征基区21后，还执行了步骤S70，这就导致本征基区21的暴露面容易被氧化产生SiO2，而影响后续形成的发射区与本征基区21的电性接触效果，导致发射区电阻较高。对本征基区21进行表面清洗，可去除本征基区21表面的SiO2，从而提高后续形成的发射区与本征基区21的电性接触效果，并有利于发射区外延出单晶材质，可有效降低发射区电阻。
S90、如图3I所示，在发射区窗口处形成与本征基区21接触的发射区膜81，并对发射区膜81和辅助膜51进行图案化，形成发射区80和辅助层50。
其中，发射区80的材料，例如可以是掺杂的外延单晶硅或者多晶硅，还可以对发射区80进行原位掺杂，以提高掺杂浓度。
在一些实施例中，半导体结构不包括盖帽层，或者盖帽层不和发射区80同步形成。那么，形成发射区80包括：
形成发射区膜81，发射区膜81覆盖辅助膜51和第二内侧墙70。然后对发射区膜81进行图案化，形成发射区80。
其中，可以是在对发射区膜81进行图案化时，同步对辅助膜51进行图案化(去除辅助膜51的未被发射区80覆盖的部分)。也就是说，同步形成发射区80和辅助层50。
例如，可以是采用光刻+干法刻蚀工艺，对辅助膜51进行图案化，形成辅助层50。
在另一些实施例中，如图3I所示，发射区80和盖帽层90同步形成。那么，形成发射区80包括：
S91、在辅助膜51上形成发射区膜81。
例如，可以采用外延生长工艺，形成发射区膜81。发射区膜81的材料，例如可以为掺杂的外延单晶硅或者多晶硅。
S92、在发射区膜81上形成盖帽膜91。
其中，盖帽膜91的材料可以是介质材料，盖帽膜91的材料例如为硅化物。示例的，盖帽膜91的材料为氧化硅、氮化硅、氮氧化硅或富氧二氧化硅等。
例如，可以采用CVD工艺形成盖帽膜91，盖帽膜91覆盖发射区膜81。
S93、对第二牺牲膜41远离衬底10一侧的膜(例如，辅助膜51、发射区膜81以及盖帽膜91)进行图案化，形成辅助层50、发射区80以及盖帽层90。
例如，通过光刻和刻蚀工艺，对辅助膜51、发射区膜81以及盖帽膜91进行图案化，露出第二牺牲膜41。
其中，对辅助膜51、发射区膜81以及盖帽膜91的图案化，可以是分多次工艺完成的，也可以是同一次工艺中完成的。对辅助膜51、发射区膜81以及盖帽膜91图案化后保留的结构的具体图案不做限定，根据需要合理设置即可。
S100、如图3J所示，形成第一外墙体103和第二外墙体104。
其中，第一外墙体103设置在第二外墙体104与发射区80之间，第一外墙体103和第二外墙体104至少包裹发射区80的侧面。
在一些实施例中，如图3J所示，第一外墙体103和第二外墙体104包裹辅助层50、发射区80以及盖帽层90的侧面。
如图3J所示，在一些实施例中，形成第一外墙体103和第二外墙体104的方法包括：
S101、在形成有盖帽层90的衬底10上形成第三介质膜101。
形成第三介质膜101的方式，例如可以采用CVD工艺形成第三介质膜101。
其中，第三介质膜101的材料可以是介质材料，第三介质膜101的材料例如为硅化物。示例的，第三介质膜101的材料为SiO2、Si3N4、氮氧化硅或富氧二氧化硅等。
在一些实施例中，第三介质膜101的材料与第一牺牲膜31的材料不同。例如，第三介质膜101的材料为Si3N4，第一牺牲膜31的材料为SiO2。
这样一来，在后续去除第一牺牲膜31时，不会去除到由第三介质膜101形成的第一外侧墙103，以确保外侧墙对发射区21起到保护作用。
S102、在第三介质膜101上形成第四介质膜102。
形成第四介质膜102的方式，例如可以采用CVD工艺形成第四介质膜102。
其中，第四介质膜102的材料可以是介质材料，第四介质膜102的材料例如为硅化物。示例的，第四介质膜102的材料为SiO2、Si3N4、氮氧化硅或富氧二氧化硅等。
在一些实施例中，第四介质膜102的材料与第二牺牲膜41的材料不同。例如，第四介质膜102的材料为SiO2，第二牺牲膜41的材料为Si3N4。
这样一来，在后续去除第二牺牲膜41时，不会去除掉第四介质膜102形成的第二外侧墙104，以对发射区21起到保护作用。
S103、对第三介质膜101和第四介质膜102进行图案化，形成第一外墙体103和第二外墙体104。
例如，可以采用刻蚀工艺，第三介质膜101和第四介质膜102进行图案化，形成第一外墙体103和第二外墙体104。
其中，对第三介质膜101和第四介质膜102进行图案化的过程，可以是在同一次工艺中完成的，也可以是在多次工艺中分别完成的。
S110、如图3K所示，去除第一牺牲膜31和第二牺牲膜41，在对应位置处形成外基区22。
在一些实施例中，如图3K所示，形成外基区22的方法包括：
S111、去除第二牺牲膜41。
例如，可以采用刻蚀工艺去除第二牺牲膜41。将本征基区21的两端暴露出来，作为形成桥接区221的晶种。
S112、在辅助层50下方形成桥接区221。
例如，可以采用选择性外延工艺，形成桥接区221。
其中，本申请实施例对桥接区221的大小不做限定，桥接区221与本征基区21接触即可。图3K中示意的桥接区221的结构仅为一种示意，不做任何限定。
桥接区221的材料，例如可以包括重掺杂的单晶硅，还可以包括少量的多晶硅。
S113、去除第一牺牲膜31。
例如，可以采用刻蚀工艺去除第一牺牲膜31。露出衬底10的表面，露出辅助外基区17。
其中，在第二外墙体104的材料与第一牺牲膜31的材料相同的情况下，去除第一牺牲膜31的同时，会去除第二外墙体104。保留下来的第一外墙体103作为半导体结构的外侧墙100，外侧墙100用于保护发射区80。
S114、在第一牺牲膜31对应位置处形成外基区膜222。
例如，可以采用选择性外延工艺，在原来第一牺牲膜31对应位置处形成外基区膜222。也就是说，在衬底10的表面上形成外基区膜222，外基区膜222直接与辅助外基区17接触。
外基区膜222的材料，例如可以多晶硅或多晶硅硅化物等。在一些实施例中，还可以对外基区膜222进行原位掺杂。
其中，形成的外基区膜222可以和本征基区21接触，也可以不和本征基区21接触。也就是说，通过外基区膜222形成的有效外基区223，可以和本征基区21接触，也可以不和本征基区21接触。
S115、对外基区膜222进行图案化，形成有效外基区223。
例如，可以采用光刻和刻蚀工艺，对外基区膜222进行图案化。
另一些实施例中，形成外基区22的方法包括：辅助外基区17还起到作为外基区膜222的种子层，在辅助外基区17上直接外延生产外基区22。在引出区16上覆盖一层介质保护层，可以确保外基区22外延只在辅助外基区17上生长，而直接获得S115的结构，从而可以省去外基区光刻和蚀刻等图案化步骤。
基于此，如图3K所示，通过上述方法形成的外基区22包括有效外基区223和桥接区221，有效外基区223与桥接区221接触，桥接区221与本征基区21接触，从而实现外基区22与本征基区21接触。由于桥接区221材料为准单晶硅，其掺杂离子的激活率大于有效外基区223(材料为多晶硅)掺杂离子的激活率。因此，通过桥接区221实现有效外基区223与本征基区21的接触，可减小外基区22与本征基区21的接触电阻。
另外，在衬底10内还设置有辅助外基区17的情况下，如图3K所示，有效外基区223在衬底10的表面与辅助外基区17接触。有效外基区223与辅助外基区17接触，相当于增加了有效外基区223的厚度，可以作为外基区22抬高，减小外基区22电阻。
在另一些实施例中，如图3L所示，形成外基区22的方法包括：
S111＇、去除第二牺牲膜41。
S112＇、去除第一牺牲膜31。
当然，去除第二牺牲膜41和去除第一牺牲膜31的过程，可以是在同一次工艺中完成的，也可以是在不同工艺中完成的。
S113＇、在第一牺牲膜31和第二牺牲膜41对应位置处形成外基区膜222。
S114＇、对外基区膜222进行图案化，形成外基区22。
如图3L所示，形成的外基区22直接与本征基区21搭接，且外基区22在衬底10的表面与辅助外基区17接触，可以作为外基区22抬高，减小外基区22电阻。
S120、对半导体结构进行热处理。
对图3K或图3L所得到的结构进行热处理(例如退火)，调节发射区80、本征基区21、外基区22以及集电区18中的掺杂分布，以激活掺杂离子。
S130、如图3M所示，通过从发射区80引出发射极(emitter electrode，E)、从外基区22引出基极(base electrode，B)以及从集电区18引出集电极(collector electrode，C)。
其中，发射极E通过设置在发射区80表面的连接孔(contact)110与发射区80接触。基极B通过设置在外基区22表面的连接孔110与外基区22接触。引出区16通过埋层集电区15与集电区18接触，集电极C通过设置在引出区16表面的连接孔110与引出区16接触，从而实现集电极C与集电区18接触。
当然，可以理解的是，在发射区80、外基区、引出区16的表面覆盖有介质层的情况下，连通孔100贯穿介质层与发射区80、外基区、引出区16接触。
需要说明的是，本申请实施例提供的半导体结构的制备方法，并不限定为由上述步骤构成，可以根据需要增加其他步骤或减少上述部分步骤。另外，上述制备方法中的步骤顺序仅为一种示意，可以根据需要调整变换。
通过上述步骤S10-S130得到的半导体结构即为HBT器件。如图4A所示，半导体结构包括：
衬底10包括浅沟槽隔离区13和有源区14。有源区14内包括埋层集电区15、引出区16以及集电区18。
集电区18埋藏于衬底10内，集电区18的表面与衬底10的表面平齐。集电区18位于本征基区21下方的有源区14内，沟槽隔离区13设置在本征基区21下方的有源区14的外围。
引出区16位于浅沟槽隔离区13远离集电区18一侧，引出区16和浅沟槽隔离区13位于埋层集电区15的上方，引出区16和集电区18分别与埋层集电区15接触。
在一些实施例中，在制备过程中执行步骤S18、S19-1以及S19-2的情况下，如图3M所示，衬底10还包括辅助外基区17。辅助外基区17设置在浅沟槽隔离区13内，辅助外基区17的表面作为衬底10的表面的一部分。
本征基区21设置在衬底10的表面，与集电区18在衬底10的表面接触，构成集电结(C-B)。本征基区21的材料，例如可以为SiGe或者SiGe:C。
外基区22设置在衬底10的表面，与辅助外基区17在衬底10的表面接触。外基 区22位于本征基区21的外围，与本征基区21接触。外基区22的材料，例如可以为多晶硅。
采用上述不同的方法，制备得到的外基区22的结构不同。在一些实施例中，在制备半导体结构的过程中，执行步骤S111-步骤S115来形成外基区22。
如图3M和图4A所示，外基区22包括桥接区221和有效外基区223，桥接区221与本征基区21和有效外基区223分别接触。
在一些实施例中，图4A所示，桥接区221与本征基区21搭接，桥接区221与有效外基区223搭接。
在另一些实施例中，图4B所示，桥接区221设置在本征基区21上，桥接区221与有效外基区223拼接。
根据桥接区221结构的不同，桥接区221与本征基区21和有效外基区223的接触方式也不同。上述仅为一种示意，不做任何限定。
另外，如图4A所示，有效外基区223与本征基区21可以不接触。如图4B所示，有效外基区223与本征基区21也可以接触。
在另一些实施例中，在制备半导体结构的过程中，执行步骤S111＇-步骤S114＇来形成外基区22。
如图5A和图5B所示，外基区22不包括桥接区，外基区22各部分的材料相同。
辅助层50，具有开口，辅助层50设置在外基区22上。其中，辅助层50上的开口可以理解为是上述制备过程中辅助膜51上的第三开口52。辅助层50的材料，例如可以为SiO2。
发射区80设置在辅助层50上，通过开口与本征基区21接触，构成发射结(E-B)。发射区80的材料，例如可以为掺杂的外延单晶硅或者多晶硅。
内侧墙，设置在外基区22与发射区80之间，还可以延伸至辅助层50与发射区80之间，用于隔离外基区22和发射区80。
在一些实施例中，半导体结构制备过程中执行上述步骤S70。那么，半导体结构中的内侧墙可以是上述第二内侧墙70。
当然，第二内侧墙70可以包括第三内墙体71和第四内墙体72。第二内墙体70也可以仅包括第三内墙体71。无论哪种情况，内侧墙包括形状为L状的部分(第三内墙体71)。第三内墙体71的材料例如可以为SiO2，第四内墙体72的材料例如可以为Si3N4。
在另一些实施例中，半导体结构制备过程中不执行上述步骤S70。那么，半导体结构中的内侧墙可以是上述第一内侧墙60。
当然，第一内侧墙60可以包括第一内墙体64和第二内墙体63。第一内侧墙60也可以仅包括第一内墙体64。第一内墙体64的材料例如可以为SiO2，第二内墙体63的材料例如可以为Si3N4。
盖帽层90覆盖发射区80远离衬底10的表面，用于保护发射区80。盖帽层90的材料例如可以为SiO2。
外侧墙100包裹发射区80的侧面，用于保护发射区80。其中，外侧墙100可以上述制备过程中的第一外墙体103。外侧墙100的材料例如可以为Si3N4。
集电极C通过与引出区16接触的连接孔100经引出区16、埋层集电区15和集电区18接触。连接孔100可以直接设置在引出区16的表面，连接孔100与引出区16之间也可以设置有金属硅化物层，以实现连接孔100与引出区16的接触。
发射极E通过穿过盖帽层90，且与发射区80接触的连接孔100，和发射区80接触。连接孔100可以直接设置在发射区80的表面，连接孔100与发射区80之间也可以设置有金属硅化物层，以实现连接孔100与发射区80的接触。
基极B通过与外基区22接触的连接孔100和外基区22接触。连接孔100可以直接设置在外基区22的表面，连接孔100与外基区22之间也可以设置有金属硅化物层，以实现连接孔100与外基区22的接触。
应当明白的是，在发射区80、外基区22以及引出区16上覆盖有介质层的情况下，连接孔100必然穿过介质层。
以NPN型的HBT器件为例，发射极E用于发射电子，基极B用于控制电子(使流向集电极C的电流受基极B输入信号的控制)，集电极C用于收集电子。
需要说明的是，上述半导体结构中的SiGe HBT晶体管可以为NPN型晶体管(本征基区21是P区，也就是P型半导体；发射区80和集电区18都是N区，也就是N型半导体)或PNP型晶体管(本征基区21是N区，也就是N型半导体；发射区80和集电区18都是P区，也就是P型半导体)。
另外，本申请实施例示意图中示意的发射极E、基极B、以及集电极C的结构、位置、数量仅为一种示意。发射极E、基极B、以及集电极C可以各只有一个，基极B和集电极C也可以是在发射极E的左右两侧各有一个。
其中，图3M中膜层的材料仅为一种示意，不做任何限定。
以NPN型的HBT器件为例，对本申请实施例提供的SiGe HBT器件的工作原理进行说明：向发射结上施加电源，发射结正偏，发射区80的多数载流子(自由电子)不断地越过发射结进入本征基区21，形成发射极电流。电子进入本征基区21后，先在靠近发射结的附近密集，渐渐形成电子浓度差，在浓度差的作用下，促使电子流在本征基区21中向集电结扩散，被集电结电场拉入集电区18形成集电极电流。也有很小一部分电子(因为本征基区21很薄)与本征基区21的空穴复合，扩散的电子流与复合电子流之比例决定了三极管的放大能力。由于集电结外加反向电压很大，这个反向电压产生的电场力将阻止集电区18电子向本征基区21扩散，同时将扩散到集电结附近的电子拉入集电区18从而形成集电极主电流。另外集电区18的少数载流子(空穴)也会产生漂移运动，流向本征基区21形成反向饱和电流。
本申请实施例提供的半导体结构的制备方法，采用第一牺牲膜31、第二牺牲膜41以及辅助膜51作为自对准结构，可用于实现集电结(C-B)的自对准和发射结(E-B)的自对准。这样一来，制备得到的集电结和发射结为轴对称结构，不会像采用光刻和刻蚀工艺那样会有偏差，导致集电结和发射结不对称。而发射结不对称，导致发射结中线两侧的寄生集电结电容和基区电阻不同，起不到两边均分电流的作用，导致总电阻和电容不能最小化。而两边对称，则可以起到最小化基区电阻和集电结电容作用，从而提高器件的最高振荡频率。集电结不对称，导致两侧寄生集电极电阻不同，同样无法起到最小化集电极电阻的目的。而且，本申请实施例中，每层膜层的制备，采用 常规技术即可实现。集电区18的形成，也是通过自对准结构限定位置，然后在衬底10中进行离子注入来实现的。
另外，本征基区21和外基区22均设置在衬底10的表面，集电区18设置在衬底10的内部，不存在抬高的外延集电区，因此。在已知的衬底10表面直接形成本征基区21和外基区22，二者是否接触是通过自身的制备工艺直接可控的。与衬底10表面设置外延集电区，然后在外延集电区上设置本征基区相比。本申请实施例直接在衬底10表面设置本征基区21，不会因为抬高的外延集电区的厚度等参数而影响本征基区21和外基区22的接触，可提高本征基区21和外基区22的接触良率，从而提高半导体结构的良率。另外，由于无需考虑集电区18厚度对本征基区21和外基区22接触效果的影响。因此，可降低对制作集电区18时工艺精度的要求，降低工艺难度。且集电区18是掺杂得到的，少了一步外延工艺(制备集电区18)，节省加工成本。
再者，在衬底10中设置辅助外基区17，辅助外基区17作为外基区22外延生长的种子层，在外基区22长成后，与外基区22接触，实现外基区22的增厚，从而可以实现降低外基区电阻的目的。
在一些实施例中，半导体结构还包括互补金属氧化物半导体场效应晶体管(complementary metal oxide semiconductor field-effect transistor，CMOSFET)。
如图6所示，半导体结构的制备方法还包括：S140、在基底11上形成CMOSFET。
其中，在基底11上形成CMOSFET的步骤可以在步骤S10之前执行，也可以在步骤S130之后执行。
如图6所示，SiGe HBT结构和CMOSFET结构之间通过衬底10中的深沟槽隔离区19隔离。
另外，本申请实施例对CMOSFET的结构不做限定，图6中的CMOSFET仅为一种示意。CMOSFET可以为NMOS晶体管或PMOS晶体管。
这样一来，半导体结构的制备方法制备得到的半导体结构为CMOS+SiGe HBT器件，可将CMOS和SiGe HBT集成在同一芯片上。
本申请实施例提供的制备方法制备得到的半导体结构，应用于晶体管电路中后，可以直接采用封装体对晶体管电路进行封装，形成封装器件(例如芯片)。也可以和其他芯片共同封装，形成封装器件。本申请实施例对此不作限定。
基于此，在一些实施例中，可将包括上述任一种半导体结构的晶体管电路应用于射频电路中。
射频电路例如可以应用于微波系统、光电系统、雷达、影像和传感领域等。射频电路例如可以是功率放大器(power amplifier，PA)、可变增益放大器(variable gain amplifier，VGA)、低噪声放大器(low noise amplifier，LNA)、跨阻放大器(trans-impedance amplifier，TIA)、驱动器(driver)、混频器、时钟数据恢复(clock data recovery，CDR)电路等。
当然，本申请实施例对上述半导体结构的应用范围不做任何限定，例如可以应用于任一种通信装置中，通信装置可以是网络设备，也可以是终端。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换， 都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种半导体结构，其特征在于，包括：
    衬底，包括埋藏于所述衬底内的集电区；
    本征基区，设置在所述衬底的表面，与所述集电区在所述衬底的表面接触；
    外基区，设置在所述衬底的表面，位于所述本征基区的外围，与所述本征基区接触；
    辅助层，具有开口；所述辅助层设置在所述外基区上；
    发射区，设置在所述辅助层上，通过所述开口与所述本征基区接触；
    内侧墙，设置在所述外基区与所述发射区之间。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述衬底还包括浅沟槽隔离区，所述浅沟槽隔离区设置在所述本征基区下方的有源区的外围；所述集电区位于所述有源区内。
  3. 根据权利要求1所述的半导体结构，其特征在于，所述衬底还包括辅助外基区，所述辅助外基区设置在所述浅沟槽隔离区内；所述外基区与所述辅助外基区在所述衬底的表面接触。
  4. 根据权利要求1-3任一项所述的半导体结构，其特征在于，所述外基区包括桥接区和有效外基区，所述桥接区与所述本征基区和所述有效外基区分别接触。
  5. 根据权利要求4所述的半导体结构，其特征在于，所述桥接区与所述本征基区和/或所述有效外基区搭接。
  6. 根据权利要求1-5任一项所述的半导体结构，其特征在于，所述半导体结构还包括外侧墙；
    所述外侧墙包裹所述发射区的侧面，用于保护所述发射区。
  7. 根据权利要求1-6任一项所述的半导体结构，其特征在于，所述半导体结构还包括盖帽层，所述盖帽层覆盖所述发射区远离所述衬底的表面，用于保护所述发射区。
  8. 根据权利要求1-7任一项所述的半导体结构，其特征在于，所述内侧墙包括内墙体，所述内墙体设置在所述外基区朝向所述发射区的表面上；所述内墙体为L状。
  9. 根据权利要求1-8任一项所述的半导体结构，其特征在于，所述半导体结构还包括设置在所述衬底上的发射极、基极以及集电极；
    所述发射极与所述发射区接触，所述基极与所述外基区接触，所述集电极与所述集电区接触。
  10. 根据权利要求9所述的半导体结构，其特征在于，所述衬底还包括引出区和埋层集电区，所述引出区和浅沟槽隔离区位于所述埋层集电区的上方，所述引出区位于所述浅沟槽隔离区远离所述集电区一侧；所述引出区和所述集电区分别与所述埋层集电区接触；
    所述集电极通过与所述引出区接触连接孔和所述集电区接触；
    所述发射极通过穿过盖帽层且与所述发射区接触的连接孔，和所述发射区接触；
    所述基极通过与所述外基区接触的连接孔和所述外基区接触。
  11. 根据权利要求1-10任一项所述的半导体结构，其特征在于，所述半导体结构还包括互补金属氧化物半导体场效应晶体管，所述互补金属氧化物半导体场效应晶体 管设置在所述衬底上。
  12. 一种射频电路，其特征在于，包括包含权利要求1-11任一项所述的半导体结构的晶体管电路。
  13. 一种半导体结构的制备方法，其特征在于，包括：
    形成基底，所述基底包括有源区和浅沟槽隔离区；
    在所述基底的表面上形成依次层叠设置的第一牺牲膜、第二牺牲膜以及辅助膜，在所述第二牺牲膜上形成第二开口，在所述辅助膜上形成第三开口，所述第二开口和所述第三开口连通作为发射区窗口；
    形成第一内侧墙，所述第一内侧墙绕所述第二牺牲膜朝向所述发射区窗口的表面一圈设置；
    形成集电区，所述集电区位于所述发射区窗口正下方的有源区内；
    在所述第一牺牲膜上形成第一开口，所述第一开口与所述第二开口连通；
    在所述第一开口内形成本征基区；
    在所述发射区窗口处形成与所述本征基区接触的发射区膜，并对所述发射区膜和所述辅助膜进行图案化，形成发射区和辅助层；
    去除所述第一牺牲膜和所述第二牺牲膜，在对应位置处形成外基区；所述外基区与所述本征基区接触。
  14. 根据权利要求13所述的半导体结构的制备方法，其特征在于，形成基底，还包括：
    在所述浅沟槽隔离区内形成辅助外基区，所述外基区与所述辅助外基区在所述基底的表面接触。
  15. 根据权利要求13或14所述的半导体结构的制备方法，其特征在于，去除所述第二牺牲膜和所述第一牺牲膜，在对应位置处形成外基区，包括：
    去除所述第二牺牲膜，并在所述辅助层下方形成桥接区；所述桥接区与所述本征基区接触；
    去除所述第一牺牲膜，在对应位置处形成有效外基区，所述有效外基区与所述桥接区接触。
  16. 根据权利要求13-15任一项所述的半导体结构的制备方法，其特征在于，所述第二开口的轮廓落在所述第一开口的轮廓内。
  17. 根据权利要求13-16任一项所述的半导体结构的制备方法，其特征在于，在所述发射区窗口处形成与所述本征基区接触的发射区之前，所述制备方法还包括：
    去除所述第一内侧墙，形成第二内侧墙。
  18. 根据权利要求17所述的半导体结构的制备方法，其特征在于，形成第二内侧墙后，所述制备方法还包括：对所述本征基区进行表面清洗。
  19. 根据权利要求13-18任一项所述的制备方法，其特征在于，所述制备方法还包括：
    在所述基底上形成互补金属氧化物半导体场效应晶体管。
PCT/CN2021/117293 2021-09-08 2021-09-08 半导体结构及其制备方法、射频电路 Ceased WO2023035155A1 (zh)

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