WO2023035714A1 - 场效应管、其制备方法及电子电路 - Google Patents

场效应管、其制备方法及电子电路 Download PDF

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Publication number
WO2023035714A1
WO2023035714A1 PCT/CN2022/098891 CN2022098891W WO2023035714A1 WO 2023035714 A1 WO2023035714 A1 WO 2023035714A1 CN 2022098891 W CN2022098891 W CN 2022098891W WO 2023035714 A1 WO2023035714 A1 WO 2023035714A1
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Prior art keywords
layer
mask pattern
gate
hard mask
metal gate
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French (fr)
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易洪昇
孙辉
胡浩林
高彪
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP22866189.8A priority Critical patent/EP4379809A4/en
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Priority to US18/599,374 priority patent/US20240213322A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a field effect transistor, its preparation method and electronic circuit.
  • GaN gallium nitride
  • HEMT High Electron Mobility Transistor
  • metal gates including single layers such as TiN/W/Ni or one or more of them
  • control gates including pGaN
  • gate structure When the device with this structure is in operation, there will be a leakage channel on the side wall between the metal gate and the control gate, which will affect electrical parameters such as gate leakage (Igleak).
  • the industry usually uses the hard mask (hard mask) humidification method to laterally etch the metal gate, or uses the spacer etching method, or uses a three-time mask patterning process to shrink the size of the metal gate inward.
  • a stepped structure is formed with the lower control gate, thereby cutting off the sidewall channel between the metal gate and the control gate, and improving leakage.
  • the process stability of the method of laterally etching the metal gate by the hard mask humidification method is poor, and the blocking etching method and the three-time mask patterning process will cause etching damage to the control gate, resulting in increased leakage, and the three-time mask
  • the molding process is complicated and the production cost is high.
  • the present application provides a field effect transistor, its preparation method and electronic circuit, which are used to improve the problems of electric leakage and high process cost in the gate structure of the field effect transistor.
  • the present application provides a gate structure of a field effect transistor, comprising: a control gate located on the channel layer of the field effect transistor, and a metal gate located on the control gate; wherein, the control gate has a top surface and a sidewall connected to the top surface, the sidewall has a stepped surface parallel to the top surface, and the orthographic projection of the metal grid on the channel layer falls into the region where the orthographic projection of the top surface on the channel layer is located.
  • the channel layer is used as a functional layer of the field effect transistor to form a two-dimensional electron gas of the field effect transistor.
  • the channel layer may include a stacked GaN layer and an AlGaN barrier layer, and the GaN layer is located between the AlGaN barrier layer and the substrate.
  • a channel can be formed at the contact surface of the GaN layer and the AlGaN barrier layer, and the two-dimensional electron gas is located at the contact surface of the GaN layer and the AlGaN barrier layer.
  • the source and drain in the field effect transistor can form ohmic contact with the GaN layer.
  • the gate structure controls the conduction of the channel, the electrons are located in the channel, and the source and drain can be conducted through the electrons in the channel; in the gate structure When the control channel is off, there are no free electrons in the channel and the source and drain are disconnected.
  • the stepped surface for blocking the sidewall channel is formed on the sidewall of the control grid, and the stepped surface formed by the inward contraction of the sidewall of the control grid can improve the metal gate structure.
  • the problem of sidewall leakage between the electrode and the control electrode Compared with the gate structure in the prior art where the stepped surface for blocking the sidewall channel is located at the interface between the control gate and the metal gate, in the process of forming the gate structure provided by the present application, the control stepped surface is located at the control gate
  • the sidewall of the electrode can form the pattern of the control electrode and the metal gate through a mask patterning process, which reduces the process complexity and industrial cost.
  • dry etching can be used in the process of forming the step surface, reducing the etching time. damage.
  • the width of the step surface is generally greater than 50 nm, so that the step surface can effectively block the leakage of sidewall channels.
  • the size of the step surface can be controlled, so that the height of the step surface is equal to the thickness of the control grid.
  • the ratio is any value between 0 and 1, so that the step surface can stay at any position required to control the sidewall of the gate, so as to obtain ladder gate structures of different sizes.
  • it further includes a hard mask on the metal gate, and the orthographic projection of the hard mask on the channel layer falls into where the orthographic projection of the metal gate on the channel layer is. within the area.
  • the present application provides a field effect transistor, including: a channel layer on the substrate, a control gate on the channel layer, a metal gate on the control gate, and a metal gate on the metal gate.
  • the passivation layer covering the control gate and the metal gate is located on the source and drain on the channel layer; wherein, the source and drain are respectively located on both sides of the control gate, and the control gate has a top surface and a The sidewall connected to the top surface has a stepped surface parallel to the top surface, and the orthographic projection of the metal grid on the substrate falls within the area where the orthographic projection of the top surface on the substrate is located.
  • the channel layer is used as a functional layer of the field effect transistor to form a two-dimensional electron gas of the field effect transistor.
  • the channel layer may include a stacked GaN layer and an AlGaN barrier layer, and the GaN layer is located between the AlGaN barrier layer and the substrate.
  • a channel can be formed at the contact surface of the GaN layer and the AlGaN barrier layer, and the two-dimensional electron gas is located at the contact surface of the GaN layer and the AlGaN barrier layer.
  • the source and drain in the field effect transistor can form ohmic contact with the GaN layer.
  • the gate structure controls the conduction of the channel, the electrons are located in the channel, and the source and drain can be conducted through the electrons in the channel; in the gate structure When the control channel is off, there are no free electrons in the channel and the source and drain are disconnected.
  • the stepped surface for blocking the sidewall channel is formed on the sidewall of the control grid, and the stepped surface formed by the inward contraction of the sidewall of the control grid can improve the metal grid and control.
  • the problem of side wall leakage between electrodes. Compared with the gate structure in the prior art where the stepped surface for blocking the sidewall channel is located at the interface between the control gate and the metal gate, in the process of forming the field effect transistor provided by the present application, the stepped surface of the control gate is located at the control gate
  • the sidewall of the gate can form the pattern of the control electrode and the metal gate through a mask patterning process, which reduces the process complexity and industrial cost.
  • dry etching can be used in the process of forming the step surface, which reduces the etching cost. corrosion damage.
  • the width of the step surface is generally greater than 50 nm, so that the step surface can effectively block the leakage of sidewall channels.
  • the size of the step surface can be controlled, so that the height of the step surface is equal to the thickness of the control grid.
  • the ratio is any value between 0 and 1, so that the step surface can stay at any position required to control the sidewall of the gate, so as to obtain ladder gate structures of different sizes.
  • it further includes a hard mask located between the metal gate and the passivation layer, and the orthographic projection of the hard mask on the substrate falls into the positive projection of the metal gate on the substrate. within the projection area.
  • the present application provides an electronic circuit, which includes a circuit board and field effect transistors provided in various implementations of the second aspect of the present application provided on the circuit board.
  • the present application provides a method for manufacturing a field effect transistor, comprising: first, sequentially forming a channel layer, a control gate layer, a metal gate layer, a hard mask layer and a photoresist on a substrate Afterwards, the photoresist layer is patterned using a mask to form a first photoresist mask pattern; then, the hard mask layer is dry-etched using the first photoresist mask pattern , forming a first hard mask pattern; then, shrinking the first photoresist mask pattern to form a second photoresist mask pattern, the second photoresist mask pattern exposes the first hard mask pattern The part of the mask pattern forms a stepped surface; then, using the shielding of the second photoresist mask pattern, the first hard mask pattern, the metal gate layer and the control gate layer are sequentially dry-etched to form the second Two hard mask patterns, metal grids and control grids, the orthographic projections of the second hard mask pattern and the metal grids on the substrate fall into the area where the orthographic
  • the step surface for blocking the sidewall channel of the control grid is formed on the sidewall of the control grid, and the sidewall of the control grid shrinks inward to form
  • the stepped surface can improve the sidewall leakage problem between the metal gate and the control electrode.
  • the preparation method of the present application can prepare a stepped gate structure by using a mask patterning process, which reduces process complexity and industrial cost.
  • only dry etching is used in the process of forming the stepped surface, which reduces the etching cost. corrosion damage.
  • the manufacturing method may further include: removing the second photoresist mask pattern and the second hard mask pattern.
  • the original mask also called the original mask
  • the first photoresist mask pattern also called the second exposure and development
  • the second A photoresist mask pattern is subjected to ashing treatment (also called a dry stripping method) to shrink the size of the first photoresist mask pattern to form a second photoresist mask pattern.
  • the thickness of the second photoresist mask pattern needs to be greater than 0.1um, so as to meet the requirements of the second photoresist mask pattern in the subsequent etching process. Minimum requirements for mask patterns.
  • the etching control gate layer after the hard mask layer is dry-etched to form the first hard mask pattern by using the shielding of the first photoresist mask pattern, the etching control gate layer.
  • the width of the step surface is generally greater than 50 nm, so that the step surface can effectively block the leakage of sidewall channels.
  • the size of the step surface can be controlled, so that the height of the step surface is equal to the thickness of the control grid.
  • the ratio is any value between 0 and 1, so that the step surface can stay at any position required to control the sidewall of the gate, so as to obtain ladder gate structures of different sizes.
  • Fig. 1 is the schematic diagram of the structure after the completion of each step in the preparation process of the method of laterally etching the metal grid by the hard mask humidification method;
  • FIG. 2 is a structural schematic diagram after each step is completed in the process of preparing a stepped gate structure by a barrier etching method
  • FIG. 3 is a schematic diagram of the structure after the completion of each step in the process of manufacturing the metal gate size shrinkage by using the three-time mask patterning process;
  • FIG. 4 is a schematic flow diagram of a method for preparing a field effect transistor provided in an embodiment of the present application
  • Fig. 5 is a schematic structural diagram after each step of the preparation method provided by the embodiment of the present application.
  • Fig. 6 is another schematic structural view after each step is completed in the preparation method provided by the embodiment of the present application.
  • Fig. 7a is a schematic cross-sectional structure diagram of a gate structure of a field effect transistor provided in an embodiment of the present application.
  • Fig. 7b is a schematic cross-sectional structure diagram of another field effect transistor gate structure provided by the embodiment of the present application.
  • Fig. 7c is a schematic cross-sectional structure diagram of another field effect transistor gate structure provided by the embodiment of the present application.
  • Fig. 7d is a schematic cross-sectional structure diagram of another field effect transistor gate structure provided by the embodiment of the present application.
  • Fig. 8a is a schematic cross-sectional structure diagram of a field effect transistor provided in the embodiment of the present application.
  • Fig. 8b is a schematic cross-sectional structure diagram of another field effect transistor provided in the embodiment of the present application.
  • Fig. 8c is a schematic cross-sectional structure diagram of another field effect transistor provided in the embodiment of the present application.
  • Fig. 8d is a schematic cross-sectional structure diagram of another field effect transistor provided by the embodiment of the present application.
  • the AlGaN/GaN heterojunction HEMT structure based on GaN materials has excellent characteristics such as high electron mobility, high 2DEG surface density, high chemical stability, high frequency, high power, etc., making GaN material devices in the field of radio frequency and power electronics. obvious advantage. Therefore, the field effect transistor provided by the embodiment of the present application can be widely used in various scenarios as a component of an electronic circuit, for example, it is widely used in the fifth generation of wireless communications technologies (5th generation of wireless communications technologies, 5G) wireless communication Base stations, power electronic devices and other information transmission and reception, energy conversion, high-frequency switching and other fields.
  • 5G wireless communications technologies
  • the stacked structure of metal gate and control gate is the most common gate structure.
  • the industry usually uses the hard mask (hard mask) wet method to etch the metal gate laterally, or uses the spacer etching method to make the size of the metal gate shrink inward, forming a pattern that is in the same shape as the control gate below.
  • the stepped structure cuts off the sidewall channels of the metal gate and the control gate, improving leakage.
  • the process flow of the commonly used hard mask humidification method for laterally etching metal gates includes: referring to a in Figure 1, the sequentially stacked substrate 1, buffer layer 2, GaN layer 3, and AlGaN layer 4.
  • the pGaN layer is used as the control gate layer 5 to grow a metal gate layer 6, a hard mask layer 7 and a photoresist layer 8 on the surface of the wafer, and then perform gate photolithography; refer to b in Figure 1, etch successively Hard mask layer 7, metal grid layer 6 and control grid layer 5, obtain the first hard mask pattern 71, the pattern of metal grid 61 and control grid 51; Referring to c in Fig. 1, remove light Resist layer 8; referring to d in FIG.
  • the metal gate 61 is retracted by using a method of wet lateral etching of the metal gate, thereby blocking the leakage channel of the side wall between the metal gate 61 and the control gate 51; Referring to e in FIG. 1 , the first hard mask pattern 71 is removed.
  • the sidewall of the metal gate 61 is easy to form a thin degenerated layer during the process of wet etching and photoresist removal, the external wet etching has a loading effect, causing the metal gate 61 to shrink inward and have a jagged sidewall abnormality , and the lateral etching depths of the metal gate 61 are inconsistent in patterns of different sizes, and wet etching is prone to produce undercuts, which will affect the subsequent film deposition process. Therefore, the morphology and process stability of the metal grid ladder structure prepared by the method of laterally etching the metal grid by the hard mask humidification method are poor.
  • the current process flow for preparing a stepped gate structure using a barrier etching method includes: a substrate 1, a buffer layer 2, a GaN layer 3, an AlGaN layer 4, and a pGaN layer stacked in sequence as a control gate layer 5.
  • a metal gate layer 6 After growing a metal gate layer 6, a hard mask layer 7 and a photoresist layer 8 on the wafer surface, gate photolithography is performed; referring to a in FIG. 2, the hard mask layer 7 and the metal gate layer are etched successively 6.
  • a dielectric layer 9 as a blocking sacrificial layer; refer to In d in Fig. 2, the dielectric layer 9 is etched in a large area by using the barrier etching method, and the dielectric 91 on both sides of the metal gate 61 is retained due to etching anisotropy; referring to e in Fig. 2, the control gate is etched Layer 5, since the remaining dielectric 91 serves as a mask (mask), the line width of the control gate 51 larger than that of the metal gate 61 can be defined, thereby realizing the stepped gate of the metal gate 61 and the control gate 51 structure; finally remove the first hard mask pattern 71 and the medium 91 .
  • the uniformity and stability of the film layer obtained by depositing the dielectric layer and the barrier etching method are better, so the side wall of the metal gate 61 can be straight and smooth.
  • Step gate structure with uniform shrinkage depth, but the over-etching step of the metal gate etching will damage the surface of the control gate layer 5, resulting in etching damage to the part of the final control gate 51 protruding from the metal gate 61 , resulting in larger leakage.
  • the current process flow for manufacturing metal gate size shrinkage using three mask patterning techniques includes: referring to a to c in FIG. 3.
  • the three-time mask patterning process has greatly enhanced the controllability of the process.
  • shrinkage structures and asymmetric structures of different sizes can be processed, but when the passivation layer 10 is opened It will cause damage to the surface of the control grid 51 and affect the ion channel.
  • the process complexity and cost of the three-pass mask method are greatly increased.
  • the embodiment of the present application provides a gate structure of a field effect transistor that improves the problems of gate leakage and high process cost, its preparation method, a field effect transistor, and an electronic circuit. Describe in detail.
  • references to "one embodiment” or “some embodiments” or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically stated otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.
  • FIG. 4 exemplarily shows a schematic flowchart of a method for manufacturing a field effect transistor provided in an embodiment of the present application.
  • the preparation method mainly includes the following steps:
  • the step surface for blocking the sidewall channel of the control grid is formed on the sidewall of the control grid, and the sidewall of the control grid shrinks inward to form
  • the stepped surface can improve the sidewall leakage problem between the metal gate and the control electrode.
  • the preparation method of the present application can prepare a stepped gate structure by using a mask patterning process, which reduces process complexity and industrial cost.
  • only dry etching is used in the process of forming the stepped surface, which reduces the etching cost. corrosion damage.
  • the preparation method may further include the following steps:
  • a passivation layer covering the metal gate and the control gate may be formed subsequently, and a source and a drain respectively located on both sides of the control gate may be formed on the channel layer.
  • Fig. 5 exemplarily shows the structural schematic diagram after each step in the preparation process is completed.
  • the preparation method includes the following steps:
  • a channel layer 31, a control gate layer 5, a metal gate layer 6, a hard mask layer 7 and a photoresist layer are sequentially formed on the substrate 1, and a mask ( After exposing and developing the photoresist layer, the excess photoresist is removed to form the first photoresist mask pattern 81 .
  • the substrate 1 can be made of semiconductor materials such as III-V compounds, silicon, sapphire or silicon carbide.
  • the channel layer 31 serves as a functional layer of the field effect transistor and is used to form a two-dimensional electron gas of the field effect transistor.
  • the channel layer 31 may include a stacked GaN layer and an AlGaN barrier layer, and the GaN layer is located between the AlGaN barrier layer and the substrate 1 .
  • a channel can be formed at the contact surface of the GaN layer and the AlGaN barrier layer, and the two-dimensional electron gas is located at the contact surface of the GaN layer and the AlGaN barrier layer.
  • the source and drain in the field effect transistor can form ohmic contact with the GaN layer.
  • the gate structure controls the conduction of the channel, the electrons are located in the channel, and the source and drain can be conducted through the electrons in the channel; in the gate structure When the control channel is off, there are no free electrons in the channel and the source and drain are disconnected.
  • a buffer layer may also be formed on the substrate 1 .
  • the buffer layer can be formed on the surface of the substrate 1 through processes such as chemical vapor deposition and epitaxial growth.
  • the buffer layer acts as an optional structural layer.
  • the buffer layer can be set as required during setup. For example, when the substrate 1 can directly carry the channel layer 31, no buffer layer can be provided, and the channel layer 31 can be directly formed on the substrate 1; when the channel layer 31 conflicts with the material of the substrate 1, the channel layer 31 If it cannot be directly formed on the substrate 1 , a buffer layer is provided to isolate the substrate 1 from the channel layer 31 .
  • the material of the buffer layer needs to be selected according to the material of the substrate 1 , which is not limited here.
  • the material of the control gate layer 5 may include pGaN.
  • the material of the metal gate layer 6 includes but not limited to TiN, W, Ta, TaN, Pd, WSi and other metals or metal compounds.
  • the material of the hard mask layer 7 includes but not limited to SiO2, Si3N4, AlO, AlN and the like.
  • the hard mask layer 7 is dry-etched by using the first photoresist mask pattern 81 to expose the metal gate layer 6 to form the first hard mask Pattern 71.
  • an over-etching process may be used to make the etched area stay on the surface of the metal gate layer 6 .
  • wet cleaning can be performed to remove the etching residues.
  • the original mask also called the original mask
  • secondary patterning also called secondary exposure and development
  • the resist mask pattern is subjected to ashing treatment (also referred to as a dry stripping method), so that the size of the first photoresist mask pattern is shrunk to form a second photoresist mask pattern 82, and the second photoresist mask pattern 82 is formed.
  • a portion of the mold pattern 82 exposing the first hard mask pattern 71 forms a stepped surface 51c.
  • the shrunk size can be controlled by adjusting the focal length/energy of the exposure machine.
  • a dry stripper (asher) can be used to remove part of the first photoresist mask pattern, and the thickness of the first photoresist mask pattern becomes While being thin, its width dimension is also reduced inward.
  • the thickness of the second photoresist mask pattern 82 needs to be greater than 0.1um to meet the minimum requirements for the subsequent etching process as a mask pattern .
  • the part of the first hard mask pattern 71 exposed by the second photoresist mask pattern 82 forms a stepped surface 51c, and the width a of the stepped surface 51c is preferably greater than 50nm, so that it will eventually stay on the control electrode side
  • the stepped surface 51c of the wall can effectively block the leakage of the side wall channel.
  • the stepped surface 51c will pass through the metal gate layer 6, and the 6 Form the first intermediate metal gate pattern 62, and then the stepped surface 51c passes down, and finally rests on the sidewall 51b of the control gate 51.
  • the second photoresist mask pattern 82 will be etched slowly, such as d in FIG. 5 , therefore, when etching the metal gate layer 6 and the control gate layer 5 Actually, the second hard mask pattern 72 is used for shielding.
  • the remaining second photoresist mask pattern 82 and second hard mask pattern 72 may be removed by a wet method to obtain a final stepped gate structure.
  • the second hard mask pattern 72 may also remain, which is not limited here.
  • the size of the step surface can be controlled, so that the step surface 51c can stay at Any desired position of the sidewall 51b of the gate 51 can be controlled, so that ladder gate structures of different sizes can be obtained.
  • FIG. 6 exemplarily shows a structural schematic view of another gate structure after each step is completed.
  • the preparation method includes the following steps:
  • a channel layer 31, a control gate layer 5, a metal gate layer 6, a hard mask layer 7 and a photoresist layer are sequentially formed on the substrate 1, and a mask plate (also After exposing and developing the photoresist layer, the excess photoresist is removed to form the first photoresist mask pattern 81 .
  • the specific process and parameters are the same as a in FIG. 5 , and will not be repeated here.
  • the hard mask layer 7 and the metal gate layer 6 are dry-etched by using the first photoresist mask pattern 81 to expose the control gate layer 5 to form The first hard mask pattern 71 and the second intermediate metal gate pattern 63 .
  • control gate layer 5 is also etched after the hard mask layer 7 is etched.
  • an over-etching process may be used to make the etched area stay on the surface of the control gate layer 5 . After the etching is completed, wet cleaning can be performed to remove the etching residues.
  • ashing treatment also referred to as a dry stripping method
  • a portion of the mold pattern 82 exposing the first hard mask pattern 71 forms a stepped surface 51c.
  • the stepped surface 51c will pass through the second intermediate metal gate pattern 63 , the first intermediate metal gate pattern 62 is formed on the second intermediate metal gate pattern 63 , and then the stepped surface 51 c passes downwards and finally stays on the sidewall 51 b of the control gate 51 .
  • the second photoresist mask pattern 82 will be etched slowly, such as d in FIG. Layer 5 is actually shielded by the second hard mask pattern 72 .
  • the remaining second photoresist mask pattern 82 and second hard mask pattern 72 may be removed by wet method to obtain the final stepped gate structure.
  • the second hard mask pattern 72 may also remain, which is not limited here.
  • FIG. 7a to FIG. 7c schematically show a schematic cross-sectional structure of a gate structure of a field effect transistor provided by an embodiment of the present application.
  • the gate structure of the field effect transistor may include: a control gate 51 located on the channel layer 31 of the field effect transistor, a metal gate located on the control gate 51 61; wherein, the control grid 51 has a top surface 51a and a sidewall 51b connected to the top surface 51a, the sidewall 51b has a stepped surface 51c parallel to the top surface 51a, and the metal grid 61 falls on the orthographic projection of the channel layer 31
  • the top surface 51a is in the region where the orthographic projection of the channel layer 31 is located.
  • the gate structure of the field effect transistor provided in the embodiment of the present application is prepared by the above-mentioned preparation method, and the stepped surface 51c used to block the sidewall channel is formed on the sidewall 51b of the control grid 51, and the sidewall 51b of the control grid 51 faces inward.
  • the contracted stepped surface 51 c can improve the sidewall leakage problem between the metal gate 61 and the control electrode 51 .
  • the control stepped surface 51c is located at the control gate
  • the side wall 51b of the gate 51 can form the pattern of the control electrode 51 and the metal gate 61 through a mask patterning process, which reduces the process complexity and industrial cost, and can be dry etched in the process of forming the stepped surface 51c. etch, reducing etch damage.
  • the width a of the stepped surface 51 c is generally greater than 50 nm, so that the stepped surface 51 c can effectively block the leakage of sidewall channels.
  • the step surface 51c can be controlled. size, so that the ratio of the height b of the stepped surface 51c to the thickness c of the control grid 51 is any value between 0-1, so that the stepped surface 51c can stay in any position required by the side wall 51b of the control grid 51, for example Referring to FIG. 7a, the stepped surface 51c is located in the middle of the side wall 51b. Referring to FIG. 7b, the stepped surface 51c is located at the bottom of the side wall 51b. Referring to FIG.
  • Fig. 7d exemplarily shows a schematic cross-sectional structure diagram of another field effect transistor gate structure provided by the embodiment of the present application.
  • the second hard mask pattern 72 is retained, that is, the gate structure also includes a hard mask located on the metal gate 61, The orthographic projection of the hard mask on the channel layer 31 falls within the region where the orthographic projection of the metal gate 61 on the channel layer 31 is located.
  • Fig. 8a to Fig. 8d exemplarily show the schematic cross-sectional structure of a field effect transistor provided by the embodiment of the present application.
  • the field effect transistor may include: a channel layer 31 located on the substrate 1, a control gate 51 located on the channel layer 31, and a control gate 51 located on the control gate 51.
  • the poles 12 are respectively located on both sides of the control grid 51, the control grid 51 has a top surface 51a and a side wall 51b connected to the top surface 51a, the side wall 51b has a stepped surface 51c parallel to the top surface 51a, and the metal grid 61 is
  • the orthographic projection on the substrate 1 falls within the area where the orthographic projection of the top surface 51 a on the substrate 1 is located.
  • the field effect transistor provided in the embodiment of the present application is prepared by the above-mentioned preparation method.
  • the stepped surface 51c for blocking the sidewall channel is formed on the sidewall 51b of the control grid 51, and the sidewall 51b of the control grid 51 is formed by shrinking inward.
  • the stepped surface 51c can improve the sidewall leakage problem between the metal gate 61 and the control electrode 51 .
  • the control stepped surface 51c is located at the control gate
  • the side wall 51b of the gate 51 can form the pattern of the control electrode 51 and the metal gate 61 through a mask patterning process, which reduces the process complexity and industrial cost, and can be dry etched in the process of forming the stepped surface 51c. etch, reducing etch damage.
  • the implementation of the field effect transistor can refer to the implementation of the gate structure of the aforementioned field effect transistor, and repeated descriptions will not be repeated.
  • the present application does not limit the specific implementation manners of the source 11 and the drain 12 , and may be any structure capable of realizing the function of a field effect transistor.
  • the source 11 and the drain 12 are respectively used to connect to external circuits, and the gate structure is used to control the on-off of the channel.
  • the gate structure controls the conduction of the channel, the field effect transistor is in the closed state, and the circuit connected to the source 11 and the drain 12 can be conducted; when the gate structure controls the channel to be turned off, the field effect transistor is in the off state, and the source The circuit connecting the pole 11 and the drain 12 is in an open state.
  • the source electrode 11 and the drain electrode 12 can be formed of metal materials arranged in the same layer, so that the source electrode 11 and the drain electrode 12 can be formed by etching the same conductive layer, thereby reducing process steps and saving production costs.
  • the source electrode 11 and the drain electrode 12 may be formed of metal, and the source electrode 11 and the drain electrode 12 are respectively electrically connected to the channel layer 31 .
  • the source 11 and the drain 12 may be formed after the passivation layer 10 .
  • the source electrode 11 and the drain electrode 12 may also be formed before the passivation layer 10, which is not limited here.
  • the embodiment of the present application also provides an electronic circuit, which may include a circuit board and any field effect transistor in the above embodiments provided in the present application, and the field effect transistor is arranged on the circuit board. Since the problem-solving principle of the electronic circuit is similar to that of the above-mentioned field effect tube, the implementation of the electronic circuit can refer to the implementation of the above-mentioned field effect tube, and the repetition will not be repeated.

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种场效应管、其制备方法及电子电路，在制备时，在衬底（1）上依次形成沟道层（31）、控制栅极层（5）、金属栅极层（6）、硬质掩膜层（7）和光刻胶层后，形成第一光刻胶掩膜图案（81），对硬质掩膜层（7）进行干法刻蚀，形成第一硬质掩膜图案（71），对第一光刻胶掩膜图案（81）进行尺寸收缩处理，形成第二光刻胶掩膜图案（82），第二光刻胶掩膜图案（82）暴露出第一硬质掩膜图案（71）的部分形成台阶面（51c），依次对第一硬质掩膜图案（71）、金属栅极层（6）和控制栅极层（5）进行干法刻蚀，在干法刻蚀的过程中台阶面（51c）向下传递并停留在控制栅极（51）的侧壁（51b）。

Description

场效应管、其制备方法及电子电路
相关申请的交叉引用
本申请要求在2021年09月10日提交中国专利局、申请号为202111062320.6、申请名称为“场效应管、其制备方法及电子电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及到半导体技术领域，尤其涉及到一种场效应管、其制备方法及电子电路。
背景技术
由于氮化镓(GaN)的禁带宽度大、迁移率高等优点，GaN广泛用于功率器件领域的衬底材料。其中，最广泛的应用是高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)。在HEMT器件中，金属栅极(包括TiN/W/Ni等单层或其中一种或多种的叠层)与控制栅极(包括pGaN)的叠层结构是最常见的栅极叠层结构(也可以称为栅结构)。这种结构的器件在工作时，金属栅极与控制栅极之间侧壁会有一个漏电通道，使得栅极漏电(gate leakage，Igleak)等电性参数受到影响。
目前业界通常利用硬质掩膜(hard mask)加湿法横向腐蚀金属栅极的方法，或使用阻挡(spacer)刻蚀方法，或使用三次掩模构图工艺，使金属栅极的尺寸向内收缩，形成与下方的控制栅极呈阶梯型的结构，从而切断金属栅极与控制栅极的侧壁通道，改善漏电。但是，硬质掩膜加湿法横向腐蚀金属栅极方法的工艺稳定性较差，而阻挡刻蚀方法和三次掩模构图工艺会对控制栅极有刻蚀损伤，导致漏电变大，且三次掩模构图工艺复杂，制作成本高。
发明内容
本申请提供了一种场效应管、其制备方法及电子电路，用以改善场效应管的栅结构中的漏电以及工艺成本高的问题。
第一方面，本申请提供了一种场效应管的栅结构，包括：位于场效应管的沟道层上的控制栅极，位于控制栅极上的金属栅极；其中，控制栅极具有顶面和与顶面连接的侧壁，侧壁具有平行于顶面的台阶面，金属栅极在沟道层的正投影与落入顶面在沟道层的正投影所在区域内。具体地，沟道层作为场效应管的功能层，用于形成场效应管的二维电子气。沟道层可以包括层叠设置的GaN层和AlGaN势垒层，GaN层位于AlGaN势垒层和衬底之间。在GaN层和AlGaN势垒层的接触面可形成沟道，二维电子气位于GaN层和AlGaN势垒层的接触面。场效应管中的源极和漏极可以与GaN层形成欧姆接触，当栅结构控制沟道导通时，电子位于沟道中，源极和漏极可通过沟道中的电子导通；在栅结构控制沟道断开时，沟道中没有自由电子，源极和漏极断开。本申请实施例提供的场效应管的栅结构中，用于阻断侧壁通道的台阶面在控制栅极的侧壁形成，控制栅极的侧壁向内收缩形成的台阶面可以改善金属栅极和控制电极之间侧壁漏电问题。相较于现有技术中用于阻断侧壁通道 的台阶面位于控制栅极和金属栅极之间界面的栅结构，在形成本申请提供的栅结构的过程中，控制台阶面位于控制栅极的侧壁，可以通过一次掩模构图工艺形成控制电极和金属栅极的图案，减少了工艺复杂度和工业成本，并且，在形成台阶面的过程可以采用干法刻蚀，减少了刻蚀损伤。
在本申请一个可能的实现方式中，台阶面的宽度一般大于50nm，以便台阶面可以有效阻断侧壁通道的漏电。
在本申请一个可能的实现方式中，通过搭配各膜层的厚度、光刻胶的收缩尺寸和干法刻蚀深度，可以控制台阶面的尺寸，使台阶面的高度与控制栅极的厚度的比值为0-1之间的任意值，这样台阶面可以停留在控制栅极侧壁所需的任意位置，得到不同尺寸的阶梯型栅结构。
在本申请一个可能的实现方式中，还包括位于金属栅极之上的硬质掩膜，硬质掩膜在沟道层上的正投影落入金属栅极在沟道层上的正投影所在区域内。
第二方面，本申请提供了一种场效应管，包括：位于衬底上的沟道层，位于沟道层上的控制栅极，位于控制栅极上的金属栅极，位于金属栅极上且覆盖控制栅极和金属栅极的钝化层，位于沟道层上的源极和漏极；其中，源极和漏极分别位于控制栅极的两侧，控制栅极具有顶面和与顶面连接的侧壁，侧壁具有平行于顶面的台阶面，金属栅极在衬底上的正投影落入顶面在衬底上的正投影所在区域内。具体地，沟道层作为场效应管的功能层，用于形成场效应管的二维电子气。沟道层可以包括层叠设置的GaN层和AlGaN势垒层，GaN层位于AlGaN势垒层和衬底之间。在GaN层和AlGaN势垒层的接触面可形成沟道，二维电子气位于GaN层和AlGaN势垒层的接触面。场效应管中的源极和漏极可以与GaN层形成欧姆接触，当栅结构控制沟道导通时，电子位于沟道中，源极和漏极可通过沟道中的电子导通；在栅结构控制沟道断开时，沟道中没有自由电子，源极和漏极断开。
本申请实施例提供的场效应管中，用于阻断侧壁通道的台阶面在控制栅极的侧壁形成，控制栅极的侧壁向内收缩形成的台阶面可以改善金属栅极和控制电极之间侧壁漏电问题。相较于现有技术中用于阻断侧壁通道的台阶面位于控制栅极和金属栅极之间界面的栅结构，在形成本申请提供的场效应管的过程中，控制台阶面位于控制栅极的侧壁，可以通过一次掩模构图工艺形成控制电极和金属栅极的图案，减少了工艺复杂度和工业成本，并且，在形成台阶面的过程可以采用干法刻蚀，减少了刻蚀损伤。
在本申请一个可能的实现方式中，台阶面的宽度一般大于50nm，以便台阶面可以有效阻断侧壁通道的漏电。
在本申请一个可能的实现方式中，通过搭配各膜层的厚度、光刻胶的收缩尺寸和干法刻蚀深度，可以控制台阶面的尺寸，使台阶面的高度与控制栅极的厚度的比值为0-1之间的任意值，这样台阶面可以停留在控制栅极侧壁所需的任意位置，得到不同尺寸的阶梯型栅结构。
在本申请一个可能的实现方式中，还包括位于金属栅极与钝化层之间的硬质掩膜，硬质掩膜在衬底上的正投影落入金属栅极在衬底上的正投影所在区域内。
第三方面，本申请提供了一种电子电路，该电子电路包括电路板以及设置在电路板上的本申请第二方面的各实现方式提供的场效应管。
第四方面，本申请提供了一种场效应管的制备方法，包括：首先，在衬底上依次形成沟道层、控制栅极层、金属栅极层、硬质掩膜层和光刻胶层；之后，利用掩模板对光刻胶 层进行构图，形成第一光刻胶掩模图案；然后，利用第一光刻胶掩模图案的遮挡，对硬质掩膜层进行干法刻蚀，形成第一硬质掩膜图案；接着，对第一光刻胶掩膜图案进行尺寸收缩处理，形成第二光刻胶掩模图案，第二光刻胶掩模图案暴露出第一硬质掩膜图案的部分形成台阶面；然后，利用第二光刻胶掩膜图案的遮挡，依次对第一硬质掩膜图案、金属栅极层和控制栅极层进行干法刻蚀，形成第二硬质掩膜图案、金属栅极和控制栅极，第二硬质掩膜图案和金属栅极在衬底上的正投影落入控制栅极的顶面在衬底上的正投影所在区域内，且在干法刻蚀的过程中台阶面向下传递并停留在控制栅极的侧壁。
在采用本申请实施例提供的制备方法制备出的场效应管中，用于阻断控制栅极的侧壁通道的台阶面在控制栅极的侧壁形成，控制栅极侧壁向内收缩形成的台阶面可以改善金属栅极和控制电极之间侧壁漏电问题。本申请的制备方法采用一道掩模(mask)构图工艺即可制备出阶梯型栅结构，减少工艺复杂度和工业成本。并且，相较于现有技术中用于阻断侧壁通道的台阶面位于控制栅极和金属栅极之间界面的栅结构，在形成台阶面的过程仅采用干法刻蚀，减少了刻蚀损伤。
在本申请一个可能的实现方式中，制备方法还可以包括：去除第二光刻胶掩模图案和第二硬质掩膜图案。
在本申请一个可能的实现方式中，可以利用原掩模板(也称为原光罩)对第一光刻胶掩膜图案进行二次构图(也称为二次曝光显影)，或，对第一光刻胶掩膜图案进行灰化处理(也称为干法去胶方式)，使第一光刻胶掩膜图案的尺寸收缩，形成第二光刻胶掩模图案。
在本申请一个可能的实现方式中，在对第一光刻胶掩膜图案进行尺寸收缩处理后，得到第二光刻胶掩模图案的厚度需要大于0.1um，以满足在后续刻蚀过程作为掩模图案的最低需求。
在本申请一个可能的实现方式中，在利用第一光刻胶掩模图案的遮挡，对硬质掩膜层进行干法刻蚀，形成第一硬质掩膜图案之后，还可以刻蚀控制栅极层。
在本申请一个可能的实现方式中，台阶面的宽度一般大于50nm，以便台阶面可以有效阻断侧壁通道的漏电。
在本申请一个可能的实现方式中，通过搭配各膜层的厚度、光刻胶的收缩尺寸和干法刻蚀深度，可以控制台阶面的尺寸，使台阶面的高度与控制栅极的厚度的比值为0-1之间的任意值，这样台阶面可以停留在控制栅极侧壁所需的任意位置，得到不同尺寸的阶梯型栅结构。
附图说明
图1为硬质掩膜加湿法横向腐蚀金属栅极方法的制备过程中各步骤完成后的结构示意图；
图2为采用阻挡刻蚀方法制备阶梯型栅结构的过程中各步骤完成后的结构示意图；
图3为采用三次掩模构图工艺方法制备金属栅极尺寸收缩的过程中各步骤完成后的结构示意图；
图4为本申请实施例提供的一种场效应管的制备方法的流程示意图；
图5为本申请实施例提供的制备方法中一种各步骤完成后的结构示意图；
图6为本申请实施例提供的制备方法中另一种各步骤完成后的结构示意图；
图7a为本申请实施例提供的一种场效应管的栅结构的剖面结构示意图；
图7b为本申请实施例提供的另一种场效应管的栅结构的剖面结构示意图；
图7c为本申请实施例提供的另一种场效应管的栅结构的剖面结构示意图；
图7d为本申请实施例提供的另一种场效应管的栅结构的剖面结构示意图；
图8a为本申请实施例提供的一种场效应管的剖面结构示意图；
图8b为本申请实施例提供的另一种场效应管的剖面结构示意图；
图8c为本申请实施例提供的另一种场效应管的剖面结构示意图；
图8d为本申请实施例提供的另一种场效应管的剖面结构示意图。
附图标记：
1-衬底；2-缓冲层；3-GaN层；31-沟道层；4-AlGaN层；5-控制栅极层；51-控制栅极；51a-顶面；51b-侧壁；51c-台阶面；6-金属栅极层；61-金属栅极；62-第一中间金属栅极图案；63-第二中间金属栅极图案；7-硬质掩膜层；71-第一硬质掩膜图案；72-第二硬质掩膜图案；8-光刻胶层；81-第一光刻胶掩模图案；82-第二光刻胶掩模图案；9-介质层；91-介质；10-钝化层；11-源极；12-漏极。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
基于GaN材料的AlGaN/GaN异质结HEMT结构具有高电子迁移率、高2DEG面密度，高化学稳定性、高频、大功率等优异特性，使得GaN材料器件在射频领域和电力电子领域都具有明显的优势。因此，本申请实施例提供的场效应管可以作为电子电路的元器件被广泛应用在各种场景中，例如被广泛应用于第五代移动通信技术(5th generation of wireless communications technologies，5G)无线通信基站、电力电子器件等信息收发、能量转换、高频开关等领域。
在HEMT器件中，金属栅极与控制栅极的叠层结构是最常见的栅结构。这种结构的器件在工作时，金属栅极与控制栅极之间侧壁会有一个漏电通道，使得栅极漏电等电性参数受到影响。目前业界通常利用硬质掩膜(hard mask)加湿法横向腐蚀金属栅极的方法，或使用阻挡(spacer)刻蚀方法，使金属栅极的尺寸向内收缩，形成与下方的控制栅极呈阶梯型的结构，从而切断金属栅极与控制栅极的侧壁通道，改善漏电。
参照图1，目前常用的硬质掩膜加湿法横向腐蚀金属栅极方法的工艺流程包括：参照图1中的a，在由依次层叠的衬底1、缓冲层2、GaN层3、AlGaN层4、pGaN层作为控制栅极层5构成的晶圆表面生长金属栅极层6、硬质掩膜层7和光刻胶层8后进行栅极光刻；参照图1中的b，陆续刻蚀硬质掩膜层7、金属栅极层6和控制栅极层5，得到第一硬质掩膜图案71，金属栅极61和控制栅极51的图案；参照图1中的c，去除光刻胶层8；参照图1中的d，采用湿法横向腐蚀金属栅极方法使金属栅极61实现内缩，从而阻断金属栅极61和控制栅极51之间侧壁的漏电通道；参照图1中的e，去除第一硬质掩膜图案71。由于金属栅极61的侧壁在湿法刻蚀和去除光刻胶的过程中容易形成一薄层变质层，外加湿法腐蚀存在负载效应，使金属栅极61内缩存在侧壁锯齿状异常，且金属栅极61在不同尺寸图形的横向腐蚀深度不一致，并且湿法刻蚀容易产生倒角(undercut)而影响后续薄膜沉积制程。因此，硬质掩膜加湿法横向腐蚀金属栅极方法制备出的金属栅极阶梯结构形 貌及工艺稳定性都较差。
参照图2，目前采用阻挡刻蚀方法制备阶梯型栅结构的工艺流程包括：在由依次层叠的衬底1、缓冲层2、GaN层3、AlGaN层4、pGaN层作为控制栅极层5构成的晶圆表面生长金属栅极层6、硬质掩膜层7和光刻胶层8后进行栅极光刻；参照图2中的a，陆续刻蚀硬质掩膜层7和金属栅极层6，形成第一硬质掩膜图案71和金属栅极61；参照图2中的b，去除光刻胶层8；参照图2中的c，沉积一层介质层9作为阻挡牺牲层；参照图2中的d，使用阻挡刻蚀方法大面积刻蚀介质层9，而金属栅极61两侧的介质91因刻蚀各向异性得以保留；参照图2中的e，刻蚀控制栅极层5，由于保留的介质91作为掩膜(mask)可以定义出相比于金属栅极61更大的控制栅极51的线宽，从而实现金属栅极61和控制栅极51的阶梯型栅结构；最后去除第一硬质掩膜图案71和介质91。相较于硬质掩膜加湿法横向腐蚀金属栅极方法，沉积介质层和阻挡刻蚀方法得到膜层的均一性和稳定性比较好，因此可以得到金属栅极61侧壁形貌平直、内缩深度均匀的阶梯型栅结构，但是在金属栅极刻蚀的过刻蚀步骤会损伤到控制栅极层5表面，导致最终控制栅极51伸出金属栅极61的部分有刻蚀损伤，导致漏电变大。
参照图3，目前采用三次掩模(mask)构图工艺方法制备金属栅极尺寸收缩的工艺流程包括：参照图3中的a至c，在由依次层叠的衬底1、缓冲层2、GaN层3、AlGaN层4、pGaN层5构成的晶圆上，采用第一张掩模板刻蚀出控制栅极51的图案；参照图3中的d至g，生长一层钝化层10后，用第二张掩模板刻蚀出尺寸小的开孔；参照图3中h至k，积淀金属栅极层6，采用第三张掩模板刻蚀出保留下的金属栅极61。至此，由三张掩模板设计的尺寸大小和工艺套刻精度来决定最终形成的金属栅极的尺寸收缩量。采用三次掩模构图工艺整体上相比于以上两种方法，工艺可控性大大增强，通过更改版图设计，可以加工出不同尺寸的收缩结构以及非对称性结构，但钝化层10开孔时会对控制栅极51表面带来损伤，影响离子通道，同时三道掩模方法工艺复杂度和成本大大增加。
为此，本申请实施例提供了一种改善栅极漏电以及工艺成本高问题的场效应管的栅结构、其制备方法、场效应管及电子电路，下面结合具体的附图以及实施例对其进行详细描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
图4示例性示出了本申请实施例提供的一种场效应管的制备方法的流程示意图。参照图4，在本申请一个实施例中，该制备方法主要包括以下步骤：
S101、在衬底上依次形成沟道层、控制栅极层、金属栅极层、硬质掩膜层和光刻胶层；
S102、利用掩模板对光刻胶层进行构图，形成第一光刻胶掩模图案；
S103、利用第一光刻胶掩模图案的遮挡，对硬质掩膜层进行干法刻蚀，形成第一硬质掩膜图案；
S104、对第一光刻胶掩膜图案进行尺寸收缩处理，形成第二光刻胶掩模图案，第二光刻胶掩模图案暴露出第一硬质掩膜图案的部分形成台阶面；
S105、利用第二光刻胶掩膜图案的遮挡，依次对第一硬质掩膜图案、金属栅极层和控制栅极层进行干法刻蚀，形成第二硬质掩膜图案、金属栅极和控制栅极，第二硬质掩膜图案和金属栅极在衬底上的正投影落入控制栅极的顶面在衬底上的正投影所在区域内，且在干法刻蚀的过程中台阶面向下传递并停留在控制栅极的侧壁。
在采用本申请实施例提供的制备方法制备出的场效应管中，用于阻断控制栅极的侧壁通道的台阶面在控制栅极的侧壁形成，控制栅极侧壁向内收缩形成的台阶面可以改善金属栅极和控制电极之间侧壁漏电问题。本申请的制备方法采用一道掩模(mask)构图工艺即可制备出阶梯型栅结构，减少工艺复杂度和工业成本。并且，相较于现有技术中用于阻断侧壁通道的台阶面位于控制栅极和金属栅极之间界面的栅结构，在形成台阶面的过程仅采用干法刻蚀，减少了刻蚀损伤。
可继续参照图4，在本申请该实施例中，制备方法还可以包括以下步骤：
S106、去除第二光刻胶掩模图案和第二硬质掩膜图案。
并且，后续还可以形成覆盖金属栅极和控制栅极的钝化层、以及在沟道层上形成分别位于控制栅极两侧的源极和漏极。
下面结合附图详细说明本申请实施例提供的制备方法。图5示例性示出了制备过程中各步骤完成后的结构示意图。参照图5，本申请该实施例中，制备方法包括以下步骤：
1、参照图5中的a，在衬底1上依次形成沟道层31、控制栅极层5、金属栅极层6、硬质掩膜层7和光刻胶层，利用一道掩模板(也称为光罩)对光刻胶层进行曝光显影后，去除掉多余的光刻胶形成第一光刻胶掩模图案81。
具体地，衬底1可采用Ⅲ-Ⅴ族化合物、硅、蓝宝石或碳化硅等半导体材料制备而成。沟道层31作为场效应管的功能层，用于形成场效应管的二维电子气。沟道层31可以包括层叠设置的GaN层和AlGaN势垒层，GaN层位于AlGaN势垒层和衬底1之间。在GaN层和AlGaN势垒层的接触面可形成沟道，二维电子气位于GaN层和AlGaN势垒层的接触面。场效应管中的源极和漏极可以与GaN层形成欧姆接触，当栅结构控制沟道导通时，电子位于沟道中，源极和漏极可通过沟道中的电子导通；在栅结构控制沟道断开时，沟道中没有自由电子，源极和漏极断开。
作为一个可选的方案，在衬底1上形成沟道层31之前，还可以在衬底1上形成缓冲层。缓冲层具体可通过化学气相沉积、外延生长等工艺形成在衬底1的表面。缓冲层作为一个可选的结构层。在设置时可根据需要设定缓冲层。如当衬底1可直接承载沟道层31时，可不设置缓冲层，沟道层31可直接形成在衬底1上；当沟道层31与衬底1的材质冲突时，沟道层31无法直接形成在衬底1上时，则设置缓冲层将衬底1与沟道层31隔离。缓冲层的材质需要根据衬底1的材质进行选择，在此不作限定。
具体地，控制栅极层5的材料可以包括pGaN。金属栅极层6的材料包括但不限于TiN、W、Ta、TaN、Pd、WSi等金属或金属化合物。硬质掩膜层7的材料包括但不限于SiO2、Si3N4、AlO、AlN等。
2、参照图5中的b，利用第一光刻胶掩模图案81的遮挡，对硬质掩膜层7进行干法 刻蚀，暴露出金属栅极层6，形成第一硬质掩膜图案71。
具体地，在刻蚀过程中，可以采用过刻工艺，使刻开区停留在金属栅极层6的表面。在刻蚀完成后，可以进行湿法清洗去除刻蚀残留物。
3、参照图5中的c，利用原掩模板(也称为原光罩)对第一光刻胶掩膜图案进行二次构图(也称为二次曝光显影)，或，对第一光刻胶掩膜图案进行灰化处理(也称为干法去胶方式)，使第一光刻胶掩膜图案的尺寸收缩，形成第二光刻胶掩模图案82，第二光刻胶掩模图案82暴露出第一硬质掩膜图案71的部分形成台阶面51c。
具体地，当利用原光罩进行二次曝光显影使第一光刻胶掩模图案81尺寸收缩时，可以通过调整曝光机的机台焦距/能量等方式控制其收缩尺寸。
具体地，当对第一光刻胶掩膜图案进行灰化处理时，可以利用干法去胶机(asher)去掉部分第一光刻胶掩模图案，第一光刻胶掩模图案厚度变薄的同时，其宽度尺寸也向里缩减。
具体地，在对第一光刻胶掩膜图案进行尺寸收缩处理后，得到第二光刻胶掩模图案82的厚度需要大于0.1um，以满足在后续刻蚀过程作为掩模图案的最低需求。
具体地，第一硬质掩膜图案71被第二光刻胶掩模图案82暴露出的部分形成台阶面51c，该台阶面51c的宽度a最好大于50nm，以便后续最终停留在控制电极侧壁的台阶面51c可以有效阻断侧壁通道的漏电。
4、参照图5中的d和e，在刻蚀机中利用第二光刻胶掩膜图案82的遮挡，依次对第一硬质掩膜图案71、金属栅极层6和控制栅极层5进行干法刻蚀，形成第二硬质掩膜图案72、金属栅极61和控制栅极51，第二硬质掩膜图案72和金属栅极61在衬底1上的正投影大致与控制栅极51的顶面51a在衬底1上的正投影重合，且在干法刻蚀的过程中参照图5中的d，台阶面51c会经过金属栅极层6，在金属栅极层6形成第一中间金属栅极图案62，之后台阶面51c向下传递，最终停留在控制栅极51的侧壁51b。并且，在刻蚀的过程中，第二光刻胶掩模图案82会慢慢被刻蚀掉，例如图5中的d，因此，在刻蚀金属栅极层6和控制栅极层5时实际上是利用第二硬质掩膜图案72的遮挡。
5、参照图5中的f，最后可以采用湿法去除残留的第二光刻胶掩模图案82和第二硬质掩膜图案72，得到最终的阶梯型栅结构。或者，也可以保留第二硬质掩膜图案72，在此不做限定。
在本申请提供的制备方法中，通过搭配各膜层的厚度、第一光刻胶掩膜图案81的收缩尺寸和干法刻蚀深度，可以控制台阶面的尺寸，使台阶面51c可以停留在控制栅极51侧壁51b所需的任意位置，这样就能得到不同尺寸的阶梯型栅结构。
图6示例性示出了另一种制备栅结构的过程中各步骤完成后的结构示意图。参照图6，本申请另一个实施例中，制备方法包括以下步骤：
1、参照图6中a，在衬底1上依次形成沟道层31、控制栅极层5、金属栅极层6、硬质掩膜层7和光刻胶层，利用一道掩模板(也称为光罩)对光刻胶层进行曝光显影后，去除掉多余的光刻胶形成第一光刻胶掩模图案81。具体过程和参数与图5中的a相同，在此不做赘述。
2、参照图6中的b，利用第一光刻胶掩模图案81的遮挡，对硬质掩膜层7和金属栅极层6进行干法刻蚀，暴露出控制栅极层5，形成第一硬质掩膜图案71和第二中间金属栅极图案63。
具体地，与图5所示的上一个实施例中的不同处在于在刻蚀硬质掩膜层7之后还刻蚀了控制栅极层5。并且，在刻蚀过程中，可以采用过刻工艺，使刻开区停留在控制栅极层5的表面。在刻蚀完成后，可以进行湿法清洗去除刻蚀残留物。
3、参照图6中的c，利用原掩模板(也称为原光罩)对第一光刻胶掩膜图案进行二次构图(也称为二次曝光显影)，或，对第一光刻胶掩膜图案进行灰化处理(也称为干法去胶方式)，使第一光刻胶掩膜图案的尺寸收缩，形成第二光刻胶掩模图案82，第二光刻胶掩模图案82暴露出第一硬质掩膜图案71的部分形成台阶面51c。具体过程和参数与图5中的c相同，在此不做赘述。
4、参照图6中的d和e，在刻蚀机中利用第二光刻胶掩膜图案82的遮挡，依次对第一硬质掩膜图案71、第二中间金属栅极图案63和控制栅极层5进行干法刻蚀，形成第二硬质掩膜图案72、金属栅极61和控制栅极51，第二硬质掩膜图案72和金属栅极61在衬底1上的正投影大致与控制栅极51的顶面51a在衬底1上的正投影重合，且在干法刻蚀的过程中参照图6中的d，台阶面51c会经过第二中间金属栅极图案63，在第二中间金属栅极图案63形成第一中间金属栅极图案62，之后台阶面51c向下传递，最终停留在控制栅极51的侧壁51b。并且，在刻蚀的过程中，第二光刻胶掩模图案82会慢慢被刻蚀掉，例如图6中的d，因此，在刻蚀第二中间金属栅极图案63和控制栅极层5时实际上是利用第二硬质掩膜图案72的遮挡。
5、参照图6中的f，最后可以采用湿法去除残留的第二光刻胶掩模图案82和第二硬质掩膜图案72，得到最终的阶梯型栅结构。或者，也可以保留第二硬质掩膜图案72，在此不做限定。
图7a至图7c示例性示出了本申请实施例提供的一种场效应管的栅结构的剖面结构示意图。参照图7a至图7c，在本申请一个实施例中，场效应管的栅结构可以包括：位于场效应管的沟道层31上的控制栅极51，位于控制栅极51上的金属栅极61；其中，控制栅极51具有顶面51a和与顶面51a连接的侧壁51b，侧壁51b具有平行于顶面51a的台阶面51c，金属栅极61在沟道层31的正投影落入顶面51a在沟道层31的正投影所在区域内。
本申请实施例提供的场效应管的栅结构采用上述制备方法制备，用于阻断侧壁通道的台阶面51c在控制栅极51的侧壁51b形成，控制栅极51的侧壁51b向内收缩形成的台阶面51c可以改善金属栅极61和控制电极51之间侧壁漏电问题。相较于现有技术中用于阻断侧壁通道的台阶面位于控制栅极和金属栅极之间界面的栅结构，在形成本申请提供的栅结构的过程中，控制台阶面51c位于控制栅极51的侧壁51b，可以通过一次掩模构图工艺形成控制电极51和金属栅极61的图案，减少了工艺复杂度和工业成本，并且，在形成台阶面51c的过程可以采用干法刻蚀，减少了刻蚀损伤。
可继续参照图7a，在本申请该实施例中，台阶面51c的宽度a一般大于50nm，以便台阶面51c可以有效阻断侧壁通道的漏电。
可继续参照图7a至图7c，在本申请该实施例中，通过搭配各膜层的厚度、第一光刻胶掩膜图案81的收缩尺寸和干法刻蚀深度，可以控制台阶面51c的尺寸，使台阶面51c的高度b与控制栅极51的厚度c的比值为0-1之间的任意值，这样台阶面51c可以停留在控制栅极51侧壁51b所需的任意位置，例如参照图7a台阶面51c位于侧壁51b的中部，参照图7b台阶面51c位于侧壁51b的底部，参照图7c台阶面51c位于侧壁51b的上部，得到不同尺寸的阶梯型栅结构。
图7d示例性示出了本申请实施例提供的另一种场效应管的栅结构的剖面结构示意图。参照图7d，在本申请另一个实施例中，在制备完成台阶面51c之后还包括保留第二硬质掩膜图案72，即栅结构还包括位于金属栅极61之上的硬质掩膜，硬质掩膜在沟道层31上的正投影落入金属栅极61在沟道层31上的正投影所在区域内。
图8a至图8d示例性示出了本申请实施例提供的一种场效应管的剖面结构示意图。参照图8a至图8d，在本申请实施例中，场效应管可以包括：位于衬底1上的沟道层31，位于沟道层31上的控制栅极51，位于控制栅极51上的金属栅极61，位于金属栅极61上且覆盖控制栅极51和金属栅极61的钝化层10，位于沟道层31上的源极11和漏极12；其中，源极11和漏极12分别位于控制栅极51的两侧，控制栅极51具有顶面51a和与顶面51a连接的侧壁51b，侧壁51b具有平行于顶面51a的台阶面51c，金属栅极61在衬底1上的正投影落入顶面51a在衬底1上的正投影所在区域内。
本申请实施例提供的场效应管采用上述制备方法制备，用于阻断侧壁通道的台阶面51c在控制栅极51的侧壁51b形成，控制栅极51的侧壁51b向内收缩形成的台阶面51c可以改善金属栅极61和控制电极51之间侧壁漏电问题。相较于现有技术中用于阻断侧壁通道的台阶面位于控制栅极和金属栅极之间界面的栅结构，在形成本申请提供的栅结构的过程中，控制台阶面51c位于控制栅极51的侧壁51b，可以通过一次掩模构图工艺形成控制电极51和金属栅极61的图案，减少了工艺复杂度和工业成本，并且，在形成台阶面51c的过程可以采用干法刻蚀，减少了刻蚀损伤。
并且，由于该场效应管解决问题的原理与前述一种场效应管的栅结构相似，因此该场效应管的实施可以参见前述场效应管的栅结构的实施，重复之处不再赘述。
可以理解的是，本申请对源极11和漏极12的具体实施方式不作限定，可以是能够实现场效应管功能的任何结构。源极11和漏极12分别用于连接外部电路，栅结构用于控制沟道的通断。在栅结构控制沟道导通时，场效应管处于闭合状态，源极11和漏极12连接的电路可导通；在栅结构控制沟道断开时，场效应管处于断开状态，源极11和漏极12连接的电路呈断开态。
示例性的，源极11和漏极12可以由同层设置的金属材料形成，这样源极11和漏极12可以通过对同一导电层进行刻蚀形成，从而可以减少工艺步骤，节约生产成本。在具体实施时，源极11和漏极12可以由金属形成，源极11和漏极12分别与沟道层31电连接。
参照图8a和图8b，源极11和漏极12可以在钝化层10之后形成。参照图8c和图8d，源极11和漏极12也可以在钝化层10之前形成，在此不做限定。
本申请实施例还提供了一种电子电路，该电子电路可包括电路板和本申请提供的上述实施例任一种场效应管，该场效应管设置在电路板上。由于该电子电路解决问题的原理与前述一种场效应管相似，因此该电子电路的实施可以参见前述场效应管的实施，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (12)

  1. 一种场效应管，其特征在于，包括：
    沟道层，位于衬底上；
    控制栅极，位于所述沟道层上，所述控制栅极具有顶面和与所述顶面连接的侧壁，所述侧壁具有平行于所述顶面的台阶面；
    金属栅极，位于所述控制栅极的顶面上，且所述金属栅极在所述衬底上的正投影落入所述顶面在所述衬底上的正投影所在区域内；
    钝化层，位于所述金属栅极上且覆盖所述控制栅极和所述金属栅极；
    源极和漏极，位于所述沟道层上，所述源极和所述漏极分别位于所述控制栅极的两侧。
  2. 如权利要求1所述的场效应管，其特征在于，所述台阶面的宽度大于50nm。
  3. 如权利要求1或2所述的场效应管，其特征在于，所述台阶面的高度与所述控制栅极的厚度的比值在0-1之间。
  4. 如权利要求1-3任一项所述的场效应管，其特征在于，还包括：硬质掩膜，位于所述金属栅极与所述钝化层之间，所述硬质掩膜在所述衬底上的正投影落入所述金属栅极在所述衬底上的正投影所在区域内。
  5. 一种电子电路，其特征在于，包括电路板以及设置在所述电路板上的如权利要求1-4任一项所述的场效应管。
  6. 一种场效应管的制备方法，其特征在于，包括：
    在衬底上依次形成沟道层、控制栅极层、金属栅极层、硬质掩膜层和光刻胶层；
    利用掩模板对所述光刻胶层进行构图，形成第一光刻胶掩模图案；
    利用所述第一光刻胶掩模图案的遮挡，对所述硬质掩膜层进行干法刻蚀，形成第一硬质掩膜图案；
    对所述第一光刻胶掩膜图案进行尺寸收缩处理，形成第二光刻胶掩模图案，所述第二光刻胶掩模图案暴露出所述第一硬质掩膜图案的部分形成台阶面；
    利用所述第二光刻胶掩膜图案的遮挡，依次对所述第一硬质掩膜图案、所述金属栅极层和所述控制栅极层进行干法刻蚀，形成第二硬质掩膜图案、金属栅极和控制栅极，所述第二硬质掩膜图案和所述金属栅极在所述衬底上的正投影落入所述控制栅极的顶面在所述衬底上的正投影所在区域内，且在干法刻蚀的过程中所述台阶面向下传递并停留在所述控制栅极的侧壁。
  7. 如权利要求6所述的制备方法，其特征在于，所述对所述第一光刻胶掩膜图案进行尺寸收缩处理，具体包括：
    利用所述掩模板对所述第一光刻胶掩膜图案进行二次构图，或，对所述第一光刻胶掩膜图案进行灰化处理。
  8. 如权利要求6或7所述的制备方法，其特征在于，所述第二光刻胶掩模图案的厚度大于0.1um。
  9. 如权利要求6-8任一项所述的制备方法，其特征在于，所述台阶面的宽度大于50nm。
  10. 如权利要求6-9任一项所述的制备方法，其特征在于，所述台阶面的高度与所述控制栅极的厚度的比值在0-1之间。
  11. 如权利要求6-10任一项所述的制备方法，其特征在于，还包括：去除所述第二光刻胶掩模图案和所述第二硬质掩膜图案。
  12. 如权利要求6-11任一项所述的制备方法，其特征在于，在对所述硬质掩膜层进行干法刻蚀，形成第一硬质掩膜图案时，还包括：对所述金属栅极层进行干法刻蚀。
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