WO2023036307A1 - 一种相变存储单元及相变存储器 - Google Patents

一种相变存储单元及相变存储器 Download PDF

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Publication number
WO2023036307A1
WO2023036307A1 PCT/CN2022/118183 CN2022118183W WO2023036307A1 WO 2023036307 A1 WO2023036307 A1 WO 2023036307A1 CN 2022118183 W CN2022118183 W CN 2022118183W WO 2023036307 A1 WO2023036307 A1 WO 2023036307A1
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Prior art keywords
hafnium
phase
phase change
material layer
change material
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English (en)
French (fr)
Inventor
李响
郭艳蓉
陈鑫
马平
童浩
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP22866768.9A priority Critical patent/EP4391016A4/en
Priority to KR1020247011763A priority patent/KR102872137B1/ko
Publication of WO2023036307A1 publication Critical patent/WO2023036307A1/zh
Priority to US18/602,721 priority patent/US20240268242A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of storage technology, in particular to a phase-change memory unit and a phase-change memory.
  • phase change memory phase change memory
  • PCM phase change memory
  • storage class memory storage class memory
  • Phase-change memory has the advantages of low power consumption, high density, and small size. It uses electrical pulses to make the difference in conductivity of the phase-change material when it transitions between crystalline and amorphous states to read and write data.
  • the phase change materials are mainly G x Sb y Te 1-xy system materials, because the nucleation centers of the G x Sb y Te 1-xy system materials themselves are unstable in the amorphous state, resulting in crystal The nucleation step in the chemicalization process is slow, which makes the SET operation slow.
  • the volume of the material changes repeatedly during the cycle operation. , easily lead to the generation of holes, so the cycle performance is poor.
  • the application provides a phase-change memory unit and a phase-change memory, which are used to increase the SET operation speed of the phase-change memory and improve the cycle performance of the phase-change memory.
  • the present application provides a phase-change memory cell, which includes a first electrode, a second electrode, and a phase-change material layer, wherein the phase-change material layer is located between the first electrode and the second electrode.
  • the phase-change material layer includes a matrix phase-change material doped with hafnium (Hf) metal and/or a hafnium compound, and the matrix phase-change material contains germanium (Ge), antimony (Sb), tellurium ( A material of at least one element in Te), bismuth (Bi).
  • the phase-change material layer includes a matrix phase-change material doped with hafnium metal and/or hafnium compound.
  • hafnium metal and/or hafnium compound can be used as a crystal nucleus in the crystallization process, Accelerate the crystallization process of the phase change material layer, thereby increasing the SET operation speed;
  • doping hafnium metal and/or hafnium compounds can fill the vacancies when the matrix phase change material is in the crystalline state, reducing the phase change of the phase change material layer. Volume changes before and after, thereby reducing the generation of voids and improving cycle performance.
  • the atomic percentage of the hafnium metal and/or the hafnium compound in the phase change material layer is 0.1%-40%.
  • the hafnium metal and/or hafnium compound account for an atomic percentage of 0.1%-40% in the phase change material layer, which can increase the crystallization speed of the phase change material layer and improve cycle performance.
  • Example 1 the atomic percentage of the hafnium metal and/or hafnium compound in the phase change material layer is 1.5%-6.5%.
  • Example 2 the atomic percentage of the hafnium metal and/or hafnium compound in the phase change material layer is 10%-19.5%.
  • Example 3 the atomic percentage of the hafnium metal and/or hafnium compound in the phase change material layer is 25%-35%.
  • the above three examples can increase the crystallization speed of the phase change material layer and improve the cycle performance, wherein the crystallization speed from low to high is: Example 3, Example 2, and Example 1, and the number of cycles from low to high is in order : Example 1, Example 2, Example 3.
  • the higher the crystallization rate the better the performance of the phase change material layer, and the higher the number of cycles, the better the performance of the phase change material layer, so the performance of the three examples of the phase change material layer has its own advantages and disadvantages .
  • the matrix phase change material includes any one of the following materials : GexSbyTe1 -xy , GexBiyTe1 -xy , wherein, between the x and the y The value range of sum is 0-100%.
  • the hafnium compound includes at least one of the following: hafnium metal oxide, hafnium metal boride, hafnium metal carbide, hafnium metal nitrogen compound, hafnium metal chalcogenide compound, hafnium metal Halogen compounds, binary or multi-element compounds formed by hafnium metal and other metals.
  • the phase-change memory unit may further include a gate material layer, and the gate material layer is located between the first electrode and the second electrode.
  • the specific setting position of the pass material layer is not limited.
  • the gate material layer can exhibit a high-resistance state at a small voltage to suppress leakage current, and a low-resistance state at a higher voltage to provide sufficient current for read and write operations.
  • the phase-change memory unit may further include at least one layer of the following between the first electrode and the second electrode: an insulating layer, a heating layer, an adhesion layer, The buffer layer.
  • the insulating layer When the insulating layer is specifically installed, the insulating layer can wrap the exposed surface of the phase-change material layer, and the insulating layer is not conductive, so the current is concentrated through the phase-change material layer, which can improve the current density and the heating efficiency of the current.
  • This application is specific to the insulating layer.
  • the setting position is not limited.
  • the heating layer can be arranged between any two layers between the first electrode and the second electrode, for example, the heating layer is arranged between the first electrode and the phase change material layer, and for example, the heating layer is arranged Between the phase-change material layer and the second electrode, the application does not limit the specific location of the heating layer.
  • the heating layer can increase the resistance of the entire unit, thereby improving the heating efficiency per unit current.
  • the adhesion layer When specifically disposing the adhesion layer, the adhesion layer may be disposed between any two layers between the first electrode and the second electrode, and the application does not limit the specific placement of the adhesion layer.
  • the adhesive layer can improve the adhesion effect between the two layers adjacent to the adhesive layer.
  • the buffer layer When specifically setting up the buffer layer, the buffer layer can be placed between any two layers between the first electrode and the second electrode, and the present application does not limit the specific setting position of the buffer layer.
  • the buffer layer can slow down the interdiffusion of two adjacent layers of materials in the phase-change memory unit under repeated erasing and writing (or reset/set) operations, thereby improving reliability.
  • the phase change material layer is prepared by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
  • the present application provides another phase-change memory cell, which includes a first electrode, a second electrode, and a phase-change material layer, and the phase-change material layer is located between the first electrode and the Between the second electrodes, the phase-change material layer includes at least one hafnium-containing material layer and at least one chalcogenide compound material layer stacked, and the hafnium-containing material layer includes at least one of the following materials: hafnium (Hf) metal, hafnium compound, A matrix phase change material doped with hafnium metal and/or a hafnium compound, the matrix phase change material is a material containing at least one element among germanium (Ge), antimony (Sb), tellurium (Te) and bismuth (Bi).
  • the phase change material layer includes at least one hafnium-containing material layer and at least one chalcogenide compound material layer stacked, on the one hand, the doped hafnium metal and/or hafnium contained in the hafnium-containing material layer
  • the compound can be used as a crystal nucleus in the crystallization process to accelerate the crystallization process, thereby increasing the operation speed of the SET;
  • the phase-change material layer includes at least two layers of stacked structure to change the thermal conductivity of the phase-change memory unit, and the two The interface of the layer material layer will hinder heat conduction, so it can improve heating efficiency and reduce power consumption of RESET operation, thereby reducing the probability of void generation and improving cycle performance.
  • the chalcogenide compound material layer is also beneficial to suppress the conduction between the upper and lower electrodes caused by element segregation in the hafnium-containing material layer and cause low-resistance failure, thereby improving the cycle performance of the phase-change memory unit and reducing resistance drift.
  • the chalcogenide compound material layer includes at least one of the following materials: germanium (Ge), antimony (Sb), titanium (Ti), tantalum (Ta), scandium (Sc), bismuth ( Tellurium compound of at least one element among Bi), silicon (Si), carbon (C), platinum (Pt), indium (In) and tellurium (Te) element; tellurium compound doped with hafnium metal and/or hafnium compound .
  • the matrix phase change material includes any of the following materials : GexSbyTe1 -xy , GexBiyTe1 -xy , SbxTey , where x The range of the sum with the y is 0-100%.
  • the hafnium-containing material layers and the chalcogenide compound material layers included in the phase change material layer are arranged alternately. In this way, if element segregation occurs in a hafnium-containing material layer and the hafnium-containing material layer is turned on, the elemental substance precipitated from the hafnium-containing material layer can be absorbed in the chalcogenide compound material layer adjacent to the hafnium-containing material layer Combination of materials, so as to effectively suppress the conduction of the entire phase-change material layer and cause low-resistance failure, thereby improving the cycle performance of the phase-change memory unit and helping to reduce resistance drift.
  • the phase change material layer includes at least three material layers stacked, and the at least three material layers include at least one hafnium-containing material layer and at least one chalcogenide compound material layer , and the hafnium-containing material layers included in the at least three material layers are arranged alternately with the chalcogenide compound material layers.
  • the number of interfaces in the phase-change material layer can be increased, and the thermal conductivity can be further reduced, so the heating efficiency can be improved, the power consumption of RESET operation can be reduced, the probability of void generation can be reduced, and the cycle performance can be further improved.
  • the phase change memory unit further includes a gate material layer located between the first electrode and the second electrode.
  • the present application does not limit the specific location of the gate material layer.
  • the gate material layer can exhibit a high-resistance state at a small voltage to suppress leakage current, and a low-resistance state at a higher voltage to provide sufficient current for read and write operations.
  • the phase change memory unit further includes at least one layer of the following between the first electrode and the second electrode: an insulating layer, an electrode layer, a heating layer, an adhesive layer, buffer layer.
  • the insulating layer When the insulating layer is specifically installed, the insulating layer can wrap the exposed surface of the phase-change material layer, and the insulating layer is not conductive, so the current is concentrated through the phase-change material layer, which can improve the current density and the heating efficiency of the current.
  • This application is specific to the insulating layer.
  • the setting position is not limited.
  • the electrode layer When specifically disposing the electrode layer, the electrode layer may be disposed between any two layers between the first electrode and the second electrode, and the present application does not limit the specific disposition position of the electrode layer.
  • the heating layer can be arranged between any two layers between the first electrode and the second electrode, for example, the heating layer is arranged between the first electrode and the phase change material layer, and for example, the heating layer is arranged Between the phase-change material layer and the second electrode, the application does not limit the specific location of the heating layer.
  • the heating layer can increase the resistance of the entire unit, thereby improving the heating efficiency per unit current.
  • the adhesion layer When specifically disposing the adhesion layer, the adhesion layer may be disposed between any two layers between the first electrode and the second electrode, and the application does not limit the specific placement of the adhesion layer.
  • the adhesive layer can improve the adhesion effect between the two layers adjacent to the adhesive layer.
  • the buffer layer When specifically setting the buffer layer, the buffer layer can be placed between any two layers between the first electrode and the second electrode, and the present application does not limit the specific setting position of the buffer layer.
  • the buffer layer can slow down the interdiffusion of two adjacent layers of materials in the phase-change memory unit under repeated erasing and writing (or reset/set) operations, thereby improving reliability.
  • the phase change material layer is prepared by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
  • the present application provides a phase-change memory, including a controller and a storage medium, wherein the storage medium includes the first aspect and an array composed of phase-change memory cells in various possible implementation manners of the first aspect, Alternatively, the second aspect and an array composed of phase-change memory cells in various possible implementation manners of the second aspect.
  • FIG. 1A is a schematic structural diagram of a phase-change memory cell in an embodiment of the present application.
  • FIG. 1B is another schematic structural diagram of a phase-change memory cell in an embodiment of the present application.
  • FIG. 2 is a schematic vertical cross-sectional view of a phase-change material layer 13 comprising a material layer provided in an embodiment of the present application;
  • FIG. 3 is a schematic vertical cross-sectional view of a phase-change material layer 13 comprising two material layers provided in an embodiment of the present application;
  • FIG. 4 is another schematic vertical cross-sectional view of a phase-change material layer 13 comprising two material layers provided in an embodiment of the present application;
  • FIG. 5 is another schematic vertical cross-sectional view of a phase-change material layer 13 comprising two material layers provided in an embodiment of the present application;
  • FIG. 6 is another schematic vertical cross-sectional view of a phase-change material layer 13 comprising two material layers provided in an embodiment of the present application;
  • FIG. 7 is a schematic vertical cross-sectional view of a phase-change material layer 13 comprising at least three material layers provided by an embodiment of the present application;
  • FIG. 8 is another schematic vertical cross-sectional view of a phase-change material layer 13 comprising at least three material layers provided by an embodiment of the present application;
  • FIG. 9 is another schematic vertical cross-sectional view of a phase-change material layer 13 comprising at least three material layers provided by an embodiment of the present application;
  • FIG. 10 is another schematic vertical cross-sectional view of a phase-change material layer 13 comprising at least three material layers provided by an embodiment of the present application;
  • FIG. 11 is another schematic structural diagram of a phase-change memory cell in an embodiment of the present application.
  • FIG. 12 is another schematic structural diagram of a phase-change memory cell in an embodiment of the present application.
  • FIG. 13 is another schematic structural diagram of a phase-change memory cell in an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a phase change memory in an embodiment of the present application.
  • FIG. 15 is a schematic diagram of another structure of a phase change memory in an embodiment of the present application.
  • Fig. 16 is a schematic diagram of the value ranges of x and y in GexSbyTe1-x-y in the embodiment of the present application.
  • references to "one embodiment” or “some embodiments” or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically stated otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.
  • phase-change memory is a non-volatile memory based on chalcogenide phase-change materials, which can switch between different resistance states under the action of heat.
  • the difference between 10 to 10000 times the resistance value realizes the storage of data 0 and 1 the set operation is the operation from the high-impedance state to the low-impedance state, and the reset operation is the operation from the low-impedance state to the high-impedance state.
  • the phase change materials in the current phase change memory are mainly G x Sb y Te 1-xy system materials, because the nucleation centers of the G x Sb y Te 1-xy system materials themselves are unstable in the amorphous state, resulting in crystal
  • the nucleation step in the chemicalization process is slow, which makes the SET operation slow.
  • the volume of the material changes repeatedly during the cycle operation. , easily lead to the generation of holes, so the cycle performance is poor.
  • the present application provides a phase-change memory unit and a phase-change memory.
  • the phase-change memory unit and the phase-change memory in the technical solution of the present application will be described below with reference to the accompanying drawings.
  • FIG. 1A is a schematic structural diagram of a phase-change memory cell provided by an embodiment of the present application.
  • the phase-change memory cell 1 in the embodiment of the present application includes a first electrode 11 , a second electrode 12 and a phase-change material layer 13 .
  • the phase change material layer 13 is located between the first electrode 11 and the second electrode 12 .
  • first electrode 11 and the second electrode 12 involved in the embodiment of the present application can have a vertical structure as shown in FIG. 1A, that is, in the vertical direction, the first electrode 11 is above the second electrode 12. It should be understood that , in some other embodiments, the first electrode 11 may also be below the second electrode 12 in the vertical direction, which is not limited in this embodiment of the present application. In some other embodiments, the first electrode 11 and the second electrode 12 can have a left-right structure as shown in FIG. 1B, that is, in the horizontal direction, the first electrode 11 is on the left of the second electrode 12. In some embodiments, the first electrode 11 may also be on the right of the second electrode 12 in the horizontal direction, which is not limited in this embodiment of the present application. Similarly, the first electrode 11 and the second electrode 12 in the following Fig. 11, Fig. 13 and Fig. 13 may be vertically up-down or vertically left-right, and will not be repeated hereafter.
  • first electrode 11 and the second electrode 12 are illustrated as a vertical vertical structure, which will not be described in detail below.
  • the phase-change material layer 13 has a first resistance state and a second resistance state, and the resistance value of the phase-change material layer 13 in the first resistance state is different from the resistance value of the phase-change material layer 13 in the second resistance state, thereby Read and write operations can be performed by controlling and reading the resistance value of the current phase change memory unit 1 . It should be understood that the phase-change material layer 13 may not only have two resistance states, but may have multiple resistance states, and the present application does not limit the number of resistance states of the phase-change material layer 13 .
  • the phase-change material layer 13 may have many possible implementation manners, which will be described respectively below.
  • the phase-change material layer 13 includes a material layer.
  • FIG. 2 is a schematic vertical cross-sectional view of a phase-change material layer 13 including a material layer provided in an embodiment of the present application.
  • the phase-change material layer 13 includes a layer of material layer 130, and the material layer 130 includes a matrix phase-change material 130 doped with hafnium (Hf) metal and/or a hafnium compound, and the matrix phase-change material is composed of A material of at least one element among germanium (Ge), antimony (Sb), tellurium (Te), and bismuth (Bi).
  • the local crystal structure of the hafnium metal and/or the hafnium compound is consistent with the local crystal structure of the matrix material.
  • the phase change material layer 13 includes a matrix phase change material doped with hafnium metal and/or hafnium compound. Change the crystallization process of the material layer 13, thereby improving the SET operation speed; Volume changes before and after, thereby reducing the generation of voids and improving cycle performance.
  • the atomic percentages of the hafnium-containing or hafnium-containing compound in different parts of the phase change material are inconsistent, for example, when the phase change material is located between the top electrode and the bottom electrode, the The atomic percentage of hafnium or hafnium-containing compounds in the phase change material changes from high to low, or from low to high, from the top electrode to the bottom electrode.
  • the atomic percentage of hafnium metal and/or hafnium compound in the phase change material layer 13 is 0.1%-40%.
  • the atomic percentage of hafnium metal and/or hafnium compound is set in this way, which can increase the crystallization speed of the phase change material layer and improve cycle performance.
  • Example 1 the atomic percentage of hafnium metal and/or hafnium compound in the phase change material layer 13 is 1.5% ⁇ 6.5%.
  • Example 2 the atomic percentage of hafnium metal and/or hafnium compound in the phase change material layer 13 is 10%-19.5%.
  • Example 3 the atomic percentage of hafnium metal and/or hafnium compound in the phase change material layer 13 is 25%-35%.
  • Example 4 the atomic percentage of hafnium metal and/or hafnium compound in the phase change material layer 13 is 7%-14%.
  • Example 5 the atomic percentage of hafnium metal and/or hafnium compound in the phase change material layer 13 is 17%-24%.
  • Example 6 the atomic percentage of hafnium metal and/or hafnium compound in the phase change material layer 13 is 27%-34%.
  • the above six examples can all increase the crystallization speed of the phase change material layer 13 and improve the cycle performance, wherein the crystallization speeds from low to high are: Example 3, Example 2, Example 1, and the number of cycles from low to high in order For: Example 1, Example 2, Example 3.
  • the specific material of the matrix phase change material is not limited, and the matrix phase change material may include any of the following materials : GexSbyTe1 -xy , GexBiyTe1 -xy , Sb x Te y , Bi x Te y , G x Te y , Sb, wherein, the value range of the sum of x and y is 0-100%.
  • the matrix phase change material may also include GexSbyBizTe1 -xyz , wherein the sum of x, y, and z ranges from 0% to 100 %.
  • the matrix phase change material is, for example, any material in GexSbyTe1 -xy , GexBiyTe1 -xy , wherein the value range of the sum of x and y is 0-100%.
  • the host material may also be Sb x Te y , or the host material may further include GexSbyBizTe1-xyz, wherein the sum of x, y, and z is 100%.
  • the range of G x Sb y Te 1-xy concentration can be the gray ellipse area and quadrilateral area A as shown in Figure 16, and the G x Sb y Te 1-xy material in this area has high-speed Crystallization characteristics, but also has a certain thermal stability.
  • the black ellipse area 1/7-1/10 ⁇ x:(1-xy) ⁇ 1/4+1/10 or 2/3-1/10 ⁇ y:(1-xy) ⁇ 2/ 3+1/10
  • the specific material of the above-mentioned hafnium compound is not limited, and the above-mentioned hafnium compound may include at least one of the following: hafnium metal oxide (such as HfO 2 ), hafnium metal boride (such as HfB), hafnium Metal carbides (such as HfC), hafnium metal nitrogen compounds (such as HfN), hafnium metal chalcogenide compounds (such as HfS, HfSe, HfTe, etc.), hafnium metal halide compounds (such as HfF, HfCl, HfBr, etc.), hafnium metal and Binary or multi-component compounds formed by other metals (such as HfTa, HfW, HfTi, HfSc, etc.).
  • hafnium metal oxide such as HfO 2
  • hafnium metal boride such as HfB
  • hafnium Metal carbides such as HfC
  • the phase change material layer 13 can be prepared by a deposition method, for example, the deposition method can be chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD) ), or atomic layer deposition (atomic layer deposition, ALD).
  • the deposition method can be chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD) ), or atomic layer deposition (atomic layer deposition, ALD).
  • two or more targets can be used, one target is a Hf-containing material, the other is a matrix phase change material, or an alloy target, and the alloy target can be simultaneously Including Hf-containing materials and parent materials, during the deposition process, N 2 , O 2 , etc. can also be added to form nitrides or oxides.
  • the phase change material layer 13 includes multiple material layers.
  • phase-change material layer 13 including multiple material layers provided by an embodiment of the present application.
  • the phase change material layer 13 includes at least one hafnium-containing material layer 131 and at least one chalcogenide compound material layer 132 stacked, and the hafnium-containing material layer 131 includes at least one of the following materials: hafnium (Hf ) metal, hafnium compound, doped hafnium metal and/or hafnium compound matrix phase change material, the matrix phase change material contains at least one of germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi) elements of material.
  • the phase-change material layer 13 includes at least one hafnium-containing material layer 131 and at least one chalcogenide compound material layer 132 stacked.
  • the doped hafnium metal and/or The hafnium compound can be used as a crystal nucleus in the crystallization process to accelerate the crystallization process, thereby increasing the SET operation speed;
  • the phase-change material layer 13 includes at least two layers of stacked structure so that the thermal conductivity of the phase-change memory unit changes , The interface between the two material layers will hinder heat conduction, so it can improve the heating efficiency and reduce the power consumption of RESET operation, thereby reducing the probability of void generation and improving cycle performance.
  • the chalcogenide compound material layer 132 is also beneficial to suppress low-resistance failure caused by the conduction between the upper and lower electrodes caused by element segregation in the hafnium-containing material layer 131, thereby improving the cycle performance of the phase-change memory unit and reducing the resistance. Value drift.
  • the chalcogenide compound material layer 132 may include at least one of the following materials: germanium (Ge), antimony (Sb), titanium (Ti), tantalum (Ta), scandium (Sc), bismuth Tellurium compounds of at least one of (Bi), silicon (Si), carbon (C), platinum (Pt), indium (In) and tellurium (Te) elements; tellurium doped with hafnium metal and/or hafnium compounds compound.
  • the chalcogenide material layer 132 can be GexTe1-x, SbxTe1-x, GexTe1-x, Ti x Te 1-x , Tax Te 1-x , Sc x Te 1-x , Bi x Te 1-x , G x Sb 1-x , In x Te 1-x , Six Te 1-x , C x Te 1-x , Pt x Te 1-x , G x Sb y Te 1-x , Ge x Bi y Te 1-xy , Tax Sb y Te 1-xy , Ti x Sb y Te 1-xy , Sc x Sb y Te 1-xy , can also be sulfur compounds containing Hf, such as Hf x Te 1- x , Hf x Sb y Te 1-xy , HfGex Sby Te 1-xy , or the concentration of hafnium atoms in the parent phase change material doped with hafnium (Hf) metal and/or haf
  • the specific material of the matrix phase change material is not limited, and the matrix phase change material may include any of the following materials: GexSbyTe1 -xy , GexBiyTe1 -xy , Sb x Te y , Bi x Te 1 , G x Te y , Sb, wherein, the value range of the sum of x and y is 0-100%.
  • the matrix phase change material may also include GexSbyBizTe1 -xyz , wherein the sum of x, y, and z ranges from 0% to 100 %.
  • the matrix phase change material is, for example, any one of GexSbyTe1 -xy , GexBiyTe1 -xy .
  • the specific material of the above-mentioned hafnium compound is not limited, and the above-mentioned hafnium compound may include at least one of the following: hafnium metal oxide (such as HfO 2 ), hafnium metal boride (such as HfB), hafnium Metal carbides (such as HfC), hafnium metal nitrogen compounds (such as HfN), hafnium metal chalcogenide compounds (such as HfS, HfSe, HfTe, etc.), hafnium metal halide compounds (such as HfF, HfCl, HfBr, etc.), hafnium metal and Binary or multi-component compounds formed by other metals (such as HfTa, HfW, HfTi, HfSc, etc.).
  • hafnium metal oxide such as HfO 2
  • hafnium metal boride such as HfB
  • hafnium Metal carbides such as HfC
  • the material combination of the hafnium-containing material layer 131 and the chalcogenide compound material layer 132 can be any of the following: HfGexSbyTe1 -xy / SbxTe1 -x ; HfGexSbyTe1 -xy /Ge x Sb y Te 1-xy ; HfGe x Sb y Te 1 -xy / Gex Te 1-x ; Concentration B), where Concentration A differs from Concentration B ; HfO 2 / HfGexSbyTe1 -xy ; HfxTe1 -x / HfGexSbyTe1 -xy , etc.
  • the phase change material layer 13 includes hafnium-containing material layers 131 and chalcogenide compound material layers 132 arranged alternately. In this way, if element segregation occurs in a hafnium-containing material layer 131 and the hafnium-containing material layer 131 is turned on, the elemental substance precipitated from the hafnium-containing material layer 131 can be connected to the chalcogenide compound adjacent to the hafnium-containing material layer 131 The combination of materials in the material layer 132 can effectively inhibit the conduction of the entire phase-change material layer 13 to cause low-resistance failure, thereby improving the cycle performance of the phase-change memory unit and reducing resistance drift.
  • the phase-change material layer 13 includes a layer of hafnium-containing material layer 131 and a layer of chalcogenide compound material layer 132.
  • the chalcogenide compound material layer 132 can be located Below the layer 131 , it can be understood that the chalcogenide compound material layer 132 is located on the side of the hafnium-containing material layer 131 away from the first electrode 11 in the phase change memory cell. As shown in FIG.
  • the chalcogenide compound material layer 132 can also be located above the hafnium-containing material layer 131, which can be understood as that the chalcogenide compound material layer 132 is located on a side of the hafnium-containing material layer 131 away from the second electrode 12 in the phase change memory cell. side.
  • the chalcogenide compound material layer 132 may also be located under the hafnium-containing material layer 131 , the chalcogenide compound material layer 132 wraps the sidewall and the bottom of the hafnium-containing material layer 131 . As shown in FIG.
  • the chalcogenide compound material layer 132 may also be located above the hafnium-containing material layer 131 , and the hafnium-containing material layer 131 wraps the sidewall and bottom of the chalcogenide compound material layer 132 .
  • the phase-change material layer 13 includes at least three material layers stacked, and the at least three material layers include at least one hafnium-containing material layer 131 and at least one chalcogenide compound material layer 132, and The hafnium-containing material layers 131 included in the at least three material layers are alternately arranged with the chalcogenide material layers 132 .
  • the number of interfaces in the phase-change material layer 13 can be increased to further reduce thermal conductivity, thereby improving heating efficiency and reducing power consumption of RESET operation, thereby reducing the probability of void generation and further improving cycle performance.
  • phase change material layer 13 comprises three layers and more than three layers of material layers, with the double-layer material layer of hafnium-containing material layer 131 and chalcogenide compound material layer 132 as the basic unit, repeat n times, n is an integer greater than or equal to 1.
  • the uppermost layer and the lowermost layer of the phase change material layer 13 are both chalcogenide compound material layers 132 .
  • both the uppermost layer and the lowermost layer of the phase change material layer 13 are hafnium-containing material layers 131 .
  • FIG. 7 the uppermost layer and the lowermost layer of the phase change material layer 13 are both chalcogenide compound material layers 132 .
  • both the uppermost layer and the lowermost layer of the phase change material layer 13 are hafnium-containing material layers 131 .
  • the uppermost layer of the phase change material layer 13 is a hafnium-containing material layer 131
  • the lowermost layer is a chalcogenide compound material layer 132
  • the uppermost layer of the phase change material layer 13 is a chalcogenide compound material layer 132
  • the lowermost layer is a hafnium-containing material layer 131 .
  • At least one hafnium-containing material layer 131 and at least one chalcogenide compound material layer 132 included in the phase-change material layer 13 can be prepared by a deposition method, for example, the deposition method can be a chemical vapor deposition method , physical vapor deposition, or atomic layer deposition.
  • the phase-change memory cell may further include at least one layer of the following between the first electrode 11 and the second electrode 12: an insulating layer, a heating layer, adhesion layer, buffer layer, electrode layer.
  • the insulating layer can wrap the exposed surface of the phase-change material layer 13, and the insulating layer is not conductive, so the current is concentrated through the phase-change material layer 13, which can improve the current density and the heating efficiency of the current.
  • the application for the insulating layer The specific setting position is not limited.
  • the material of the insulating layer can be, for example, at least one of silicon dioxide (SiO 2 ), silicon nitride (SiN) or titanium nitride (TiN), or other materials that can isolate current.
  • the specific material is not limited.
  • the heating layer can be arranged between any two layers between the first electrode 11 and the second electrode 12, for example, the heating layer is arranged between the first electrode 11 and the phase change material layer 13, and for example , the heating layer is disposed between the phase-change material layer 13 and the second electrode 12 , and the application does not limit the specific position of the heating layer.
  • the heating layer can increase the resistance of the entire unit, thereby improving the heating efficiency per unit current.
  • the adhesion layer When specifically disposing the adhesion layer, the adhesion layer may be disposed between any two layers between the first electrode 11 and the second electrode 12 , and the present application does not limit the specific placement of the adhesion layer.
  • the adhesive layer can improve the adhesion effect between the two layers adjacent to the adhesive layer.
  • the buffer layer When specifically setting up the buffer layer, the buffer layer can be placed between any two layers between the first electrode 11 and the second electrode 12 , and the application does not limit the specific setting position of the buffer layer.
  • the buffer layer can slow down the interdiffusion of two adjacent layers of materials in the phase-change memory unit under repeated erasing and writing (or reset/set) operations, thereby improving reliability.
  • the electrode layer When specifically disposing the electrode layer, the electrode layer can be disposed between any two layers between the first electrode 11 and the second electrode 12 , and the application does not limit the specific disposition position of the electrode layer.
  • the material of the heating layer, the adhesion layer, and the buffer layer can be, for example, oxide, boron compound, carbon compound, nitride compound, chalcogenide compound, halogen compound, etc.
  • the present application refers to the heating layer, adhesion layer,
  • the specific materials of these several material layers of the buffer layer are not limited, as long as the corresponding functions of these several material layers can be realized.
  • the phase-change memory cell may further include a gate material layer located between the first electrode 11 and the second electrode 12 , and the present application does not limit the specific location of the gate material layer.
  • the gate material layer can exhibit a high-resistance state at a small voltage to suppress leakage current, and a low-resistance state at a higher voltage to provide sufficient current for read and write operations.
  • the gate material layer may include a single material layer, or may include multiple material layers.
  • the gating material layer includes a single-layer material layer.
  • the gating material layer may include a base material doped with hafnium metal and/or a hafnium compound.
  • the base material may be, for example, G x As y Se(Te) 1-xy , where the sum of x and y equals 1.
  • hafnium compound refer to the related introduction of the hafnium compound in the aforementioned phase-change material layer 13 , which will not be repeated here.
  • the gating material layer may include multiple material layers.
  • the gating material layer may include at least one hafnium-containing material layer and at least one chalcogenide material layer, and the gating material layer may include multiple material layers.
  • the phase-change material layer including multiple material layers above, which will not be repeated here.
  • FIG. 11 is another structural schematic diagram of a phase-change memory cell in the embodiment of the present application.
  • the phase-change memory cell 1 shown in FIG. 11 is a T-type phase-change memory cell.
  • the phase-change memory cell 1 includes The first electrode 11 , the second electrode 12 , and the phase change material layer 13 located between the first electrode 11 and the second electrode 12 .
  • the phase-change memory unit 1 may further include a heating layer 16 located between the phase-change material layer 13 and the second electrode 12 , and the sidewall of the heating layer 16 is also wrapped around the insulating layer 15 .
  • the heating layer 16 needs to meet the requirement of electric conduction, and also needs to be able to increase the resistance of the entire phase-change memory unit.
  • the phase-change material layer 13 is located on a heating layer 16 with a smaller cross-sectional size and the insulating layer 15 wrapping the sidewall of the heating layer 16.
  • the phase-change material layer 13 is connected to the second electrode 12 below it through a conductive heating layer, and It is connected to the first electrode 11 above the phase-change material layer 13, and the first electrode 11 and the second electrode 12 extend in different horizontal directions to connect different phase-change memory cells in the memory array.
  • Fig. 12 is another structural diagram of a phase-change memory cell in the embodiment of the present application.
  • the phase-change memory cell 1 shown in Fig. 12 is a restricted phase-change memory cell.
  • the phase-change memory cell 1 includes The first electrode 11, the second electrode 12, and the phase-change material layer 13 between the first electrode 11 and the second electrode 12, the phase-change material layer 13 has a smaller cross-sectional size, and is directly connected to the first electrode 11 above and below.
  • the second electrode 12 is connected.
  • the phase-change memory cell 1 may further include an insulating layer 15 located between the phase-change material layer 13 and the second electrode 12 , and the insulating layer 15 wraps sidewalls of the phase-change material layer 13 .
  • FIG. 13 is a schematic diagram of another structure of a phase-change memory cell in the embodiment of the present application
  • the phase-change memory cell 1 shown in Figure 13 is a three-dimensional phase-change memory cell, as shown in Figure 13, the phase-change memory cell 1 includes a An electrode 11, a second electrode 12, and a phase change material layer 13 between the first electrode 11 and the second electrode 12, the phase change material layer 13 may also include a phase change material layer between the first electrode 11 and the second electrode 12
  • Gate material layer 14, phase-change material layer 13 and gate material layer 14 have smaller cross-sectional dimensions, and between first electrode 11 and second electrode 12, comprise first electrode layer 17, phase-change material layer 13, second Electrode layer 18, gate material layer 14, third electrode layer 19, phase change material layer 13 can be connected with first electrode 11 through first electrode layer 17, gate material layer 14 can be connected with phase change through second electrode layer 18
  • the material layer 13 is connected to the second electrode 12 through the second electrode layer 18 .
  • the phase-change memory cell 1 can also include an insulating layer 15 between the phase-change material layer 13 and the second electrode 12, and the insulating layer 15 wraps the phase-change material layer 13, the gate material layer 14, and the side walls of the electrode layers .
  • the first electrode 11 and the second electrode 12 extend in different horizontal directions, and connect different phase-change memory cells in the memory array to form an array arranged on one layer. Such an array is further stacked in the vertical direction to form a Cross-stacked three-dimensional phase-change memory.
  • FIG. 14 is a schematic structural diagram of a phase change memory in an embodiment of the present application.
  • the phase change memory 100 includes a controller 110 and a storage medium 120, wherein the storage medium 120 includes the phase change memory in any of the above-mentioned embodiments.
  • the present application also provides a phase change memory.
  • FIG. 15 is a schematic diagram of another structure of a phase change memory in an embodiment of the present application.
  • the phase change memory can also include a row decoder (row decoder), a column decoder (column decoder), a sense amplifier (sense amplifier), a driver circuit (driver circuitry), a data buffer (data buffer) and Digital controller.
  • the first electrodes 12 of a plurality of phase-change memory cells 1 are connected to form a first electrode line 2
  • the second electrodes 13 of a plurality of phase-change memory cells 1 are connected to form a second electrode line 3.
  • the extension direction of the above-mentioned first electrode lines 2 and The extending directions of the second electrode lines 3 intersect.
  • phase-change memory cell 1 there is a uniquely determined phase-change memory cell 1 at the intersection of the first electrode line 2 and the second electrode line 3 .
  • the row decoder of the phase change memory is electrically connected to all the first electrode lines 2
  • the column decoder, sense amplifier and driving circuit are electrically connected to all the second electrode lines 3 .
  • the above-mentioned row decoder, column decoder, sense amplifier and driving circuit are respectively electrically connected with the digital controller and the data buffer.
  • One of the first electrode line 2 and the second electrode line 3 is a word line (word line, WL), and the other is a bit line (bit line, BL), which can make a word line connected to a row of phase-change memory cells 1 , applying a level value different from that of other word lines on the selected word line, so as to select the phase-change memory cells 1 in a certain row to perform operations such as reading and writing.
  • a bit line is connected to a phase-change memory unit 1 of a column, and the electrical signal for writing the phase-change memory unit 1 is transmitted to the column selected by the column decoder, or along the selected column, the signal obtained by the read unit operation is transmitted to the column decoder electric signal.
  • the first electrode line 2 can be a word line
  • the second electrode line 3 can be a bit line
  • the first electrode line 2 can be a bit line
  • the second electrode line 3 can be a word line, which is not limited in this application.
  • the following takes the first electrode line 2 as a word line and the second electrode line 3 as a bit line as an example to illustrate the working process of the phase change memory in the technical solution of the present application.
  • the row decoder of the phase change memory is electrically connected to all the first electrode lines 2
  • the column decoder, sense amplifier and driving circuit are electrically connected to all the second electrode lines 3 .
  • the above-mentioned row decoder, column decoder, sense amplifier and driving circuit are respectively electrically connected with the digital controller and the data buffer. Since there is a uniquely determined phase-change memory unit 1 located at the intersection of the first electrode line 2 and the second electrode line 3, and the phase-change memory unit 1 has different resistance states, the read and write operations of the three-dimensional phase-change memory can be realized.
  • the digital controller controls the row decoder to modulate the voltage of the first electrode line 2 connected to the set phase-change memory unit 1 to a read mode (for example, the voltage is 0V), and the control column decoder will communicate with the Set the voltage modulation of the second electrode line 3 connected to the phase-change memory cell 1 to read mode (for example, the voltage is 1V). Then measure the current of the set phase-change memory cell 1 through a sense amplifier connected to the second electrode line 3, to judge the resistance state of the phase-change material layer 13 of the phase-change memory cell 1, thereby obtaining the state of stored data .
  • the digital controller controls the row decoder to modulate the voltage of the first electrode line 2 connected to the set phase-change memory unit 1 to the write mode (for example, the voltage is 2V), and the control column decoder will communicate with the Set the voltage modulation of the second electrode line 3 connected to the phase-change memory unit 1 to the write mode (for example, the voltage is 0V), and then send a write pulse current or pulse voltage through the drive circuit connected to the second electrode line 3, and transmit it to the
  • the phase-change memory cell 1 is set above, and the resistance state of the phase-change memory cell 1 is changed to realize the write operation.
  • the data read from the sense amplifier and the data to be written into the phase change memory are stored in the data buffer.
  • the above-mentioned phase-change memory may be a two-dimensional phase-change memory.
  • the phase-change memory cells 1 in the above-mentioned two-dimensional phase-change memory can be arranged in an array, for example, can be arranged in n rows and m columns, where m and n are positive integers greater than 1, respectively.

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Abstract

本申请提供一种相变存储单元及相变存储器。该相变存储单元包括第一电极、第二电极和相变材料层，其中，相变材料层位于第一电极与第二电极之间，相变材料层包括掺杂铪(Hf)金属和/或铪化合物的母体相变材料，母体相变材料为包含锗(Ge)、锑(Sb)、碲(Te)、铋(Bi)中至少一种元素的材料。铪金属和/或铪化合物可以作为晶化过程中的晶核，加速相变材料层的晶化过程，从而提升SET操作速度；而且，掺杂铪金属和/或铪化合物可以填充母体相变材料处于晶态时的空位，减少相变材料层在相变前后的体积变化，从而降低空洞的产生，提升循环性能。

Description

一种相变存储单元及相变存储器
本申请要求于2021年9月13日提交中国专利局、申请号为202111068031.7、发明名称为“一种相变存储单元及相变存储器”的中国专利申请的优先权，以及于2022年07月21日提交的申请号为202210863735.1、发明名称为“一种相变存储单元及相变存储器”的中国专利申请的优先权，前述两件专利申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储技术领域，尤其涉及一种相变存储单元及相变存储器。
背景技术
随着移动互联网、云计算、大数据、深度学习以及物联网等各项技术的广泛应用，市场对超高密度、超大容量的数据存储的需求快速增长。其中，相变存储器(phase change memory，PCM)作为应用前景最被看好的非易失存储技术之一，已经在多种存储结构方向得到应用，例如，在二维存储器结构方向，二维相变存储器已经在嵌入式应用中得到使用，又例如，在三维存储器结构方向，三维相变存储器作为存储级内存(storage class memory)已应用在数据中心等场景中。
相变存储器具有低功耗、高密度、尺寸小等优点，其通过电脉冲的方式使相变材料在晶态和非晶态之间转变时所表现出来的导电性差异实现读写数据。目前在相变存储器中，相变材料以Ge xSb yTe 1-x-y体系材料为主，由于Ge xSb yTe 1-x-y体系材料本身在非晶态时的成核中心不稳定，导致晶化过程的成核步骤慢，使得SET操作速度慢，而且，由于Ge xSb yTe 1-x-y体系材料在晶态和非晶态时的密度差异较大，导致循环操作过程中材料体积反复变化，容易导致孔洞的产生，因此循环性能差。
发明内容
本申请提供一种相变存储单元及相变存储器，用以提高相变存储器的SET操作速度，并提升相变存储器的循环性能。
第一方面，本申请提供了一种相变存储单元，该相变存储单元包括第一电极、第二电极和相变材料层，其中，相变材料层位于所述第一电极与所述第二电极之间，所述相变材料层包括掺杂铪(Hf)金属和/或铪化合物的母体相变材料，所述母体相变材料为包含锗(Ge)、锑(Sb)、碲(Te)、铋(Bi)中至少一种元素的材料。
本申请提供的相变存储单元中，相变材料层包括掺杂铪金属和/或铪化合物的母体相变材料，一方面，铪金属和/或铪化合物可以作为晶化过程中的晶核，加速相变材料层的晶化过程，从而提升SET操作速度；另一方面，掺杂铪金属和/或铪化合物可以填充母体相变材料处于晶态时的空位，减少相变材料层在相变前后的体积变化，从而降低空洞的产生，提升循环性能。
在本申请一种可能的实现方式中，所述铪金属和/或铪化合物在所述相变材料层中所占的原子百分比为0.1％～40％。该实现方式中，铪金属和/或铪化合物在相变材料层中所占的原子百分比为0.1％～40％，可以提高相变材料层的晶化速度，并提升循环性能。
以下提供几种上述铪金属和/或铪化合物在所述相变材料层中所占的原子百分比的示例：
示例一，所述铪金属和/或铪化合物在所述相变材料层中所占的原子百分比为1.5％～6.5％。
示例二，所述铪金属和/或铪化合物在所述相变材料层中所占的原子百分比为10％～19.5％。
示例三，所述铪金属和/或铪化合物在所述相变材料层中所占的原子百分比为25％～35％。
上述三种示例都可以提高相变材料层的晶化速度，并提升循环性能，其中，晶化速度从低到高依次为：示例三、示例二、示例一，循环次数从低到高依次为：示例一、示例二、示例三。一般而言，晶化速度越高，相变材料层的性能越好，循环次数越高，相变材料层的性能也越好，所以这三种示例的相变材料层的性能各有优劣。
在本申请一种可能的实现方式中，母体相变材料包括以下任一种材料：Ge xSb yTe 1-x-y、Ge xBi yTe 1-x-y，其中，所述x与所述y之和的取值范围为0-100％。
在本申请一种可能的实现方式中，所述铪化合物包括以下至少一种：铪金属氧化物，铪金属硼化物，铪金属碳化物，铪金属氮系化合物，铪金属硫系化合物，铪金属卤素化合物，铪金属与其它金属形成的二元或多元化合物。
在本申请一种可能的实现方式中，所述相变存储单元还可以包括选通材料层，所述选通材料层位于所述第一电极与所述第二电极之间，本申请对于选通材料层的具体设置位置不作限制。选通材料层可以在小电压下呈现高阻态从而抑制漏电流，在较大的电压下呈现低阻态从而提供足够的电流进行读和写操作。
在本申请一种可能的实现方式中，所述相变存储单元还可以包括位于所述第一电极与所述第二电极之间的以下至少一层：绝缘层、加热层、粘附层、缓冲层。
具体设置绝缘层时，绝缘层可以包裹相变材料层裸露的表面，绝缘层不导电，则电流集中从相变材料层经过，可以提升电流密度和电流的加热效率，本申请对于绝缘层的具体设置位置不作限制。
具体设置加热层时，加热层可以设置于第一电极与第二电极之间的任意两层之间，例如，加热层设置于第一电极与相变材料层之间，又例如，加热层设置于相变材料层与第二电极之间，本申请对于加热层的具体设置位置不作限制。加热层可以提高整个单元的电阻，从而提高单位电流下发热效率。
具体设置粘附层时，粘附层可以设置于第一电极与第二电极之间的任意两层之间，本申请对于粘附层的具体设置位置不作限制。粘附层可以提高与粘附层相邻的两层之间的粘附效果。
具体设置缓冲层时，缓冲层可以置于第一电极与第二电极之间的任意两层之间，本申请对于缓冲层的具体设置位置不作限制。缓冲层可以减缓在反复擦写(或reset/set)操作下，相变存储单元中的相邻两层材料互相扩散，从而可以提高可靠性。
在本申请一种可能的实现方式中，所述相变材料层采用化学气相沉积法、物理气相沉积、或原子层沉积制备得到。
第二方面，本申请提供了另一种相变存储单元，该相变存储单元包括第一电极、第二电极和相变材料层，所述相变材料层位于所述第一电极与所述第二电极之间，该相变材料层包括层叠的至少一个含铪材料层和至少一个硫系化合物材料层，该含铪材料层包括以下至少一种材料：铪(Hf)金属、铪化合物、掺杂铪金属和/或铪化合物的母体相变材料，该母体相变材料为包含锗(Ge)、锑(Sb)、碲(Te)、铋(Bi)中至少一种元素的材料。
本申请提供的相变存储单元中，相变材料层包括层叠的至少一个含铪材料层和至少一个 硫系化合物材料层，一方面，含铪材料层中包括的掺杂铪金属和/或铪化合物可以作为晶化过程中的晶核，加速晶化过程，从而提升SET操作速度；另一方面，相变材料层包括层叠的至少两层结构使得相变存储单元的热导率发生变化，两层材料层的界面会阻碍热传导，因此可以提升加热效率，降低RESET操作功耗，从而降低空洞产生的概率，提升循环性能。而且，硫系化合物材料层还有利于抑制含铪材料层中元素偏析导致的上下电极之间导通而发生低阻失效，从而可以提升相变存储单元的循环性能，同时有利于降低阻值漂移。
在本申请一种可能的实现方式中，硫系化合物材料层包括以下至少一种材料：锗(Ge)、锑(Sb)、钛(Ti)、钽(Ta)、钪(Sc)、铋(Bi)、硅(Si)、碳(C)、铂(Pt)、铟(In)中的至少一种元素与碲(Te)元素的碲化合物；掺杂铪金属和/或铪化合物的碲化合物。
在本申请一种可能的实现方式中，母体相变材料包括以下任一种材料：Ge xSb yTe 1-x-y、Ge xBi yTe 1-x-y、Sb xTe y，其中，所述x与所述y之和的取值范围为0-100％。
在本申请一种可能的实现方式中，所述相变材料层包括的所述含铪材料层和所述硫系化合物材料层交替排布。通过该方式，如果一个含铪材料层中发生元素偏析问题而造成该含铪材料层导通，该含铪材料层析出的单质可以与该含铪材料层相邻的硫系化合物材料层中的材料结合，从而可以与有效抑制整个相变材料层导通而发生低阻失效，从而可以提升相变存储单元的循环性能，同时有利于降低阻值漂移。
在本申请一种可能的实现方式中，所述相变材料层包括层叠设置的至少三个材料层，所述至少三个材料层中包括至少一个含铪材料层和至少一个硫系化合物材料层，且至少三个材料层中包括的所述含铪材料层与所述硫系化合物材料层交替排布。通过该方式，可以增加相变材料层中的界面数量，进一步降低热导，因此可以提升加热效率，降低RESET操作功耗，从而可以降低空洞产生的概率，进一步提升循环性能。
在本申请一种可能的实现方式中，所述相变存储单元还包括位于所述第一电极和所述第二电极之间的选通材料层。本申请对于选通材料层的具体设置位置不作限制。选通材料层可以在小电压下呈现高阻态从而可以抑制漏电流，在较大的电压下呈现低阻态从而可以提供足够的电流进行读和写操作。
在本申请一种可能的实现方式中，所述相变存储单元还包括位于所述第一电极与所述第二电极之间的以下至少一层：绝缘层、电极层、加热层、粘附层、缓冲层。
具体设置绝缘层时，绝缘层可以包裹相变材料层裸露的表面，绝缘层不导电，则电流集中从相变材料层经过，可以提升电流密度和电流的加热效率，本申请对于绝缘层的具体设置位置不作限制。
具体设置电极层时，电极层可以设置于第一电极与第二电极之间的任意两层之间，本申请对于电极层的具体设置位置不作限制。
具体设置加热层时，加热层可以设置于第一电极与第二电极之间的任意两层之间，例如，加热层设置于第一电极与相变材料层之间，又例如，加热层设置于相变材料层与第二电极之间，本申请对于加热层的具体设置位置不作限制。加热层可以提高整个单元的电阻，从而提高单位电流下发热效率。
具体设置粘附层时，粘附层可以设置于第一电极与第二电极之间的任意两层之间，本申请对于粘附层的具体设置位置不作限制。粘附层可以提高与粘附层相邻的两层之间的粘附效果。
具体设置缓冲层时，缓冲层可以置于第一电极与第二电极之间的任意两层之间，本申请 对于缓冲层的具体设置位置不作限制。缓冲层可以减缓在反复擦写(或reset/set)操作下，相变存储单元中的相邻两层材料互相扩散，从而可以提高可靠性。
在本申请一种可能的实现方式中，所述相变材料层采用化学气相沉积法、物理气相沉积法、或原子层沉积法制备得到。
第三方面，本申请提供了一种相变存储器，包括控制器和存储介质，其中，存储介质包括上述第一方面及第一方面各种可能的实现方式中的相变存储单元组成的阵列，或者，上述第二方面及第二方面各种可能的实现方式中的相变存储单元组成的阵列。
附图说明
图1A为本申请实施例中相变存储单元的一种结构示意图；
图1B为本申请实施例中相变存储单元的另一种结构示意图；
图2为本申请实施例提供的包括一层材料层的相变材料层13的垂直截面示意图；
图3为本申请实施例提供的包括两层材料层的相变材料层13的一种垂直截面示意图；
图4为本申请实施例提供的包括两层材料层的相变材料层13的另一种垂直截面示意图；
图5为本申请实施例提供的包括两层材料层的相变材料层13的另一种垂直截面示意图；
图6为本申请实施例提供的包括两层材料层的相变材料层13的另一种垂直截面示意图；
图7为本申请实施例提供的包括至少三层材料层的相变材料层13的一种垂直截面示意图；
图8为本申请实施例提供的包括至少三层材料层的相变材料层13的另一种垂直截面示意图；
图9为本申请实施例提供的包括至少三层材料层的相变材料层13的另一种垂直截面示意图；
图10为本申请实施例提供的包括至少三层材料层的相变材料层13的另一种垂直截面示意图；
图11为本申请实施例中相变存储单元的另一种结构示意图；
图12为本申请实施例中相变存储单元的另一种结构示意图；
图13为本申请实施例中相变存储单元的另一种结构示意图；
图14为本申请实施例中相变存储器的一种结构示意图；
图15为本申请实施例中相变存储器的另一种结构示意图。
图16为本申请实施例中GexSbyTe1-x-y中x和y的取值范围的示意图。
图标说明：
1-相变存储单元；
11-第一电极；
12-第二电极；
13-相变材料层；
131-含铪材料层；
132-硫系化合物材料层；
14-选通材料层；
15-绝缘层；
16-加热层；
17-第一电极层；
18-第二电极层；
19-第三电极层；
2-第一电极线；
3-第二电极线。
具体实施方式
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
为了方便理解本申请实施例提供的相变存储单元及相变存储器，下面介绍一下其应用场景。本申请提供的相变存储器可用于手机、平板电脑、笔记本电脑、可穿戴设备、车载设备等电子设备中的数据存储。相变存储器是一种基于硫系相变材料的非易失存储器，在热作用下能够在不同电阻状态下转换，利用相变存储器在高阻态(reset态)与低阻态(set态)之间10～10000倍电阻值的差异实现数据0和1的存储，set操作为从高阻态到低阻态的操，reset操作为从低阻态到高阻态的操作。
目前的相变存储器中的相变材料以Ge xSb yTe 1-x-y体系材料为主，由于Ge xSb yTe 1-x-y体系材料本身在非晶态时的成核中心不稳定，导致晶化过程的成核步骤慢，使得SET操作速度慢，而且，由于Ge xSb yTe 1-x-y体系材料在晶态和非晶态时的密度差异较大，导致循环操作过程中材料体积反复变化，容易导致孔洞的产生，因此循环性能差。为了解决上述问题，本申请提供了一种相变存储单元及相变存储器，下面结合附图来说明本申请技术方案中的相变存储单元及相变存储器。
图1A为本申请实施例提供的相变存储单元的一种结构示意图。如图1A所示，本申请实施例中的相变存储单元1包括第一电极11、第二电极12和相变材料层13。其中，相变材料层13位于第一电极11与第二电极12之间。
需要说明的是，本申请实施例涉及的第一电极11和第二电极12可以如图1A所示的上下结构，即在垂直方向上，第一电极11在第二电极12的上方，应理解，在其它一些实施例中，在垂直方向上，第一电极11也可以在第二电极12的下方，本申请实施例对此不做限制。在其它一些实施例中，第一电极11和第二电极12可以如图1B所示的左右结构，即在水平方向上，第一电极11在第二电极12的左方，应理解，在其它一些实施例中，在水平方向上，第一电极11也可以在第二电极12的右方，本申请实施例对此不做限制。同样的，以下图11、图13和图13中的第一电极11和第二电极12可以为垂直方向上的上下结构或垂直方向上的 左右结构，后文不再赘述。
为便于描述，以下实施例中以第一电极11和第二电极12为在垂直方向上的上下结构进行示意，后文不再赘述。
上述相变材料层13具有第一电阻状态和第二电阻状态，相变材料层13在第一电阻状态下的阻值，与相变材料层13在第二电阻状态下的阻值不同，从而可以通过控制和读取当前相变存储单元1的阻值来进行读写操作。应理解，相变材料层13可能不止具有两种电阻状态，可以具有多种电阻状态，本申请对相变材料层13具有的电阻状态数量不构成限制。
本申请实施例中，相变材料层13可以有多种可能的实施方式，下面分别进行说明。
可能的实施方式一，相变材料层13包括一层材料层。
图2为本申请实施例提供的包括一层材料层的相变材料层13的垂直截面示意图。如图2所示，相变材料层13包括一层材料层130，该一层材料层130包括掺杂铪(Hf)金属和/或铪化合物的母体相变材料130，母体相变材料为包含锗(Ge)、锑(Sb)、碲(Te)、铋(Bi)中至少一种元素的材料。其中，铪金属和/或铪化合物的局域晶态结构与基体材料的局域晶态结构一致。在该实施方式一中，相变材料层13包括掺杂铪金属和/或铪化合物的母体相变材料，一方面，铪金属和/或铪化合物可以作为晶化过程中的晶核，加速相变材料层13的晶化过程，从而提升SET操作速度；另一方面，掺杂铪金属和/或铪化合物可以填充母体相变材料处于晶态时的空位，减少相变材料层13在相变前后的体积变化，从而降低空洞的产生，提升循环性能。
在本申请一实施例中，所述含铪或者含铪的化合物在所述相变材料中的不同部分原子百分比不一致，例如当所述相变材料位于顶电极与底电极之间时，所述含铪或者含铪的化合物在所述相变材料中从顶电极到底电极方向原子百分比呈由高到低，或者由低到高的梯度变化。
本申请实施例中，铪金属和/或铪化合物在相变材料层13中所占的原子百分比为0.1％～40％。铪金属和/或铪化合物的原子百分比如此设置，可以提高相变材料层的晶化速度，并提升循环性能。
以下提供几种上述铪金属和/或铪化合物在所述相变材料层中所占的原子百分比的示例：
示例一，铪金属和/或铪化合物在相变材料层13中所占的原子百分比为1.5％～6.5％。
示例二，铪金属和/或铪化合物在相变材料层13中所占的原子百分比为10％～19.5％。
示例三，铪金属和/或铪化合物在相变材料层13中所占的原子百分比为25％～35％。
示例四，铪金属和/或铪化合物在相变材料层13中所占的原子百分比为7％～14％。
示例五，铪金属和/或铪化合物在相变材料层13中所占的原子百分比为17％-24％。
示例六，铪金属和/或铪化合物在相变材料层13中所占的原子百分比为27％-34％。
上述六种示例都可以提高相变材料层13的晶化速度，并提升循环性能，其中，晶化速度从低到高依次为：示例三、示例二、示例一，循环次数从低到高依次为：示例一、示例二、示例三。一般而言，晶化速度越高，相变材料层的性能越好，循环次数越高，相变材料层的性能也越好，所以这三种示例的相变材料层的性能各有优劣。
在本申请的一种实施例中，上述母体相变材料的具体材质不作限制，母体相变材料可以包括以下任一种材料：Ge xSb yTe 1-x-y、Ge xBi yTe 1-x-y、Sb xTe y、Bi xTe y、Ge xTe y，Sb，其中，x与y之和的取值范围为0-100％。母体相变材料还可以包括Ge xSb yBi zTe 1-x-y-z，其中，x、y、z之和的取值范围为0-100％。
作为示例性说明，母体相变材料例如为Ge xSb yTe 1-x-y、Ge xBi yTe 1-x-y中的任一种材料，其 中，所述x与所述y之和的取值范围为0-100％。
作为另外一种示例，所述母体材料还可以为Sb xTe y，或者所述母体材料还包括GexSbyBizTe1-x-y-z，其中，所述x,y,z之和为100％。
在所述材料GexSbyTe1-x-y中及Ge xBi yTe 1-x-y中，x:y:(1-x-y)＝4:1:5、2:2:5、3:2:6,1:2:4、或1:4:7，在所述材料Sb xTe y中，x:y＝2:3、1:1、2:1、或者1:0。
在另外一种示例中，Ge xSb yTe 1-x-y浓度取值范围可以为如图16所示的灰色椭圆区域和四边形区域A，该区域的Ge xSb yTe 1-x-y材料具有高速的结晶特性，同时也具有一定的热稳定性。在所述黑色椭圆区域中，1/7-1/10≤x:(1-x-y)≤1/4+1/10或者2/3-1/10≤y:(1-x-y)≤2/3+1/10，在所述四边形区域A中，1/7≤x:(1-x-y)≤2/5，2/3≤y:(1-x-y)≤4。在本申请的一种实施例中，上述铪化合物的具体材质不做限制，上述铪化合物可以包括以下至少一种：铪金属氧化物(例如HfO 2)，铪金属硼化物(例如HfB)，铪金属碳化物(例如HfC)，铪金属氮系化合物(例如HfN)，铪金属硫系化合物(例如HfS、HfSe、HfTe等)，铪金属卤素化合物(例如HfF、HfCl、HfBr等)，铪金属与其它金属形成的二元或多元化合物(例如HfTa、HfW、HfTi、HfSc等)。
在本申请的一种实施例中，相变材料层13可以采用沉积方法制备得到，例如，沉积方法可以为化学气相沉积法(chemical vapor deposition，CVD)、物理气相沉积法(physical vapor deposition，PVD)、或原子层沉积法(atomic layer deposition，ALD)。
作为示例性说明，以物理气相沉积方法为例，可以使用两个或多个靶材，一个靶材为含Hf材料，一个为母体相变材料，也可以为一个合金靶材，合金靶材同时包括含Hf材料以及母体材料，在沉积过程中，还可以加入N 2、O 2等形成氮化物或氧化物。
可能的实施方式二，相变材料层13包括多层材料层。
图3至图10为本申请实施例提供的包括多层材料层的相变材料层13的垂直截面示意图。
如图3至图10所示，相变材料层13包括层叠的至少一个含铪材料层131和至少一个硫系化合物材料层132，该含铪材料层131包括以下至少一种材料：铪(Hf)金属、铪化合物、掺杂铪金属和/或铪化合物的母体相变材料，该母体相变材料为包含锗(Ge)、锑(Sb)、碲(Te)、铋(Bi)中至少一种元素的材料。在该实施方式二中，相变材料层13包括层叠的至少一个含铪材料层131和至少一个硫系化合物材料层132，一方面，含铪材料层131中包括的掺杂铪金属和/或铪化合物可以作为晶化过程中的晶核，加速晶化过程，从而提升SET操作速度；另一方面，相变材料层13包括层叠的至少两层结构使得相变存储单元的热导率发生变化，两层材料层的界面会阻碍热传导，因此可以提升加热效率，降低RESET操作功耗，从而降低空洞产生的概率，提升循环性能。而且，硫系化合物材料层132还有利于抑制含铪材料层131中元素偏析导致的上下电极之间导通而发生低阻失效，从而可以提升相变存储单元的循环性能，同时有利于降低阻值漂移。
在本申请的一种实施例中，硫系化合物材料层132可以包括以下至少一种材料：锗(Ge)、锑(Sb)、钛(Ti)、钽(Ta)、钪(Sc)、铋(Bi)、硅(Si)、碳(C)、铂(Pt)、铟(In)中的至少一种元素与碲(Te)元素的碲化合物；掺杂铪金属和/或铪化合物的碲化合物。
作为示例性市说明，硫系化合物材料层132可以为GexTe1-x，SbxTe1-x，GexTe1-x，Ti xTe 1-x，Ta xTe 1-x，Sc xTe 1-x，Bi xTe 1-x，Ge xSb 1-x，In xTe 1-x，Si xTe 1-x，C xTe 1-x，Pt xTe 1-x，Ge xSb yTe 1-x-y，Ge xBi yTe 1-x-y，Ta xSb yTe 1-x-y,Ti xSb yTe 1-x-y，Sc xSb yTe 1-x-y，也可以为含Hf的硫系化合物，如Hf xTe 1-x,Hf xSb yTe 1-x-y,HfGe xSb yTe 1-x-y,或者与上述实施方式一的掺杂铪(Hf)金属和/或铪化合物的母 体相变材料中铪原子的浓度(也可以理解为铪原子在掺杂有铪(Hf)金属和/或铪化合物的母体相变材料中所占的原子百分比)不同的含Hf材料。其中，x与y之和的取值范围为0-100％。
在本申请的一种实施例中，上述母体相变材料的具体材质不作限制，母体相变材料可以包括以下任一种材料：Ge xSb yTe 1-x-y、Ge xBi yTe 1-x-y、Sb xTe y、Bi xTe 1、Ge xTe y，Sb，其中，x与y之和的取值范围为0-100％。母体相变材料还可以包括Ge xSb yBi zTe 1-x-y-z，其中，x、y、z之和的取值范围为0-100％。
作为示例性说明，母体相变材料例如为Ge xSb yTe 1-x-y、Ge xBi yTe 1-x-y中的任一种材料。
在本申请的一种实施例中，上述铪化合物的具体材质不做限制，上述铪化合物可以包括以下至少一种：铪金属氧化物(例如HfO 2)，铪金属硼化物(例如HfB)，铪金属碳化物(例如HfC)，铪金属氮系化合物(例如HfN)，铪金属硫系化合物(例如HfS、HfSe、HfTe等)，铪金属卤素化合物(例如HfF、HfCl、HfBr等)，铪金属与其它金属形成的二元或多元化合物(例如HfTa、HfW、HfTi、HfSc等)。
在一个示例中，含铪材料层131和硫系化合物材料层132的材料搭配例如可以为以下任一种：HfGe xSb yTe 1-x-y/Sb xTe 1-x；HfGe xSb yTe 1-x-y/Ge xSb yTe 1-x-y；HfGe xSb yTe 1-x-y/Ge xTe 1-x；HfGe xSb yTe 1-x-y(浓度A)/HfGe xSb yTe 1-x-y(浓度B)，其中，浓度A与浓度B不同；HfO 2/HfGe xSb yTe 1-x-y；Hf xTe 1-x/HfGe xSb yTe 1-x-y等。
在本申请的一种实施例中，相变材料层13包括的含铪材料层131和硫系化合物材料层132交替排布。通过该方式，如果一个含铪材料层131中发生元素偏析问题而造成该含铪材料层131导通，该含铪材料层131析出的单质可以与该含铪材料层131相邻的硫系化合物材料层132中的材料结合，从而可以与有效抑制整个相变材料层13导通而发生低阻失效，从而可以提升相变存储单元的循环性能，同时有利于降低阻值漂移。
继续参照图3至图6所示，相变材料层13包括一层含铪材料层131和一层硫系化合物材料层132，如图3所示，硫系化合物材料层132可以位于含铪材料层131下方，可以理解为在相变存储单元中硫系化合物材料层132位于含铪材料层131远离第一电极11的一侧。如图4所示，硫系化合物材料层132也可以位于含铪材料层131上方，可以理解为在相变存储单元中硫系化合物材料层132位于含铪材料层131远离第二电极12的一侧。如图5所示，硫系化合物材料层132也可以位于含铪材料层131下方、硫系化合物材料层132且包裹含铪材料层131的侧壁和底部。如图6所示，硫系化合物材料层132也可以位于含铪材料层131上方、且含铪材料层131包裹硫系化合物材料层132的侧壁和底部。
在本申请的一种实施例中，相变材料层13包括层叠设置的至少三个材料层，至少三个材料层中包括至少一个含铪材料层131和至少一个硫系化合物材料层132，且至少三个材料层中包括的含铪材料层131与硫系化合物材料层132交替排布。通过该方式，可以增加相变材料层13中的界面数量，进一步降低热导，因此可以提升加热效率，降低RESET操作功耗，从而可以降低空洞产生的概率，进一步提升循环性能。
继续参照图7至图10所示，相变材料层13包括三层及三层以上的材料层，以含铪材料层131和硫系化合物材料层132的双层材料层为基本单元，重复n次，n为大于或等于1的整数。如图7所示，相变材料层13的最上层和最下层均为硫系化合物材料层132。如图8所示，相变材料层13的最上层和最下层均为含铪材料层131。如图9所示，相变材料层13的最上层为含铪材料层131，最下层为硫系化合物材料层132。如图10所示，相变材料层13的最上层为硫系化合物材料层132，最下层为含铪材料层131。
在本申请的一种实施例中，相变材料层13包括的至少一个含铪材料层131和至少一个硫系化合物材料层132可以采用沉积方法制备得到，例如，沉积方法可以为化学气相沉积法、物理气相沉积法、或原子层沉积法。
基于上述实施方式一和上述实施方式二，在本申请的一种实施例中，相变存储单元还可以包括位于第一电极11与第二电极12之间的以下至少一层：绝缘层、加热层、粘附层、缓冲层、电极层。
具体设置绝缘层时，绝缘层可以包裹相变材料层13裸露的表面，绝缘层不导电，则电流集中从相变材料层13经过，可以提升电流密度和电流的加热效率，本申请对于绝缘层的具体设置位置不作限制。绝缘层的材料例如可以为二氧化硅(SiO 2)、氮化硅(SiN)或者氮化钛(TiN)中至少一种，也可以为其它可以起到隔绝电流的材料，本申请对于绝缘层的具体材料不作限制。
具体设置加热层时，加热层可以设置于第一电极11与第二电极12之间的任意两层之间，例如，加热层设置于第一电极11与相变材料层13之间，又例如，加热层设置于相变材料层13与第二电极12之间，本申请对于加热层的具体设置位置不作限制。加热层可以提高整个单元的电阻，从而提高单位电流下发热效率。
具体设置粘附层时，粘附层可以设置于第一电极11与第二电极12之间的任意两层之间，本申请对于粘附层的具体设置位置不作限制。粘附层可以提高与粘附层相邻的两层之间的粘附效果。
具体设置缓冲层时，缓冲层可以置于第一电极11与第二电极12之间的任意两层之间，本申请对于缓冲层的具体设置位置不作限制。缓冲层可以减缓在反复擦写(或reset/set)操作下，相变存储单元中的相邻两层材料互相扩散，从而可以提高可靠性。
具体设置电极层时，电极层可以设置于第一电极11与第二电极12之间的任意两层之间，本申请对于电极层的具体设置位置不作限制。
作为示例性说明，加热层、粘附层、缓冲层的材质例如可以为氧化物、硼化合物、碳化合物、氮系化物、硫系化合物、卤素化合物等，本申请对于加热层、粘附层、缓冲层这几种材料层的具体材料不作限制，只要可以实现这几种材料层相应的功能即可。
基于上述任一实施例，相变存储单元还可以包括选通材料层，选通材料层位于第一电极11与第二电极12之间，本申请对于选通材料层的具体设置位置不作限制。选通材料层可以在小电压下呈现高阻态从而抑制漏电流，在较大的电压下呈现低阻态从而提供足够的电流进行读和写操作。
其中，选通材料层可以包括单层材料层，也可以包括多层材料层。在一个示例中，选通材料层包括单层材料层，具体实施中选通材料层可以包括掺杂铪金属和/或铪化合物的基体材料，该基体材料例如可以为Ge xAs ySe(Te) 1-x-y，其中，x与y之和等于1。铪化合物可以参见前述相变材料层13中的铪化合物的相关介绍，此处不再赘述。在另一个示例中，选通材料层可以包括多层材料层，具体实施中选通材料层可以包括至少一个含铪材料层和至少一个硫系化合物材料层，选通材料层可以包括多层材料层的具体实现方式可以参见上述相变材料层包括多层材料层的相关描述，此处不再赘述。
图11为本申请实施例中相变存储单元的另一种结构示意图，图11中示出的相变存储单元1为T型相变存储单元，如图11所示，相变存储单元1包括第一电极11、第二电极12、 以及位于第一电极11与第二电极12之间的相变材料层13。相变存储单元1还可以包括位于相变材料层13与第二电极12之间的加热层16，该加热层16的侧壁还包裹了绝缘层15。加热层16需要满足导电的需求，还需要可以提高整个相变存储单元的电阻的效果。相变材料层13位于一个截面较小尺寸的加热层16和包裹该加热层16侧壁的绝缘层15之上，相变材料层13通过导电的加热层与其下方的第二电极12相连，又与相变材料层13上方的第一电极11相连，第一电极11和第二电极12在不同水平方向上延伸，将存储阵列中的不同相变存储单元连接起来。
图12为本申请实施例中相变存储单元的另一种结构示意图，图12中示出的相变存储单元1为限制型相变存储单元，如图12所示，相变存储单元1包括第一电极11、第二电极12、以及位于第一电极11与第二电极12之间的相变材料层13，相变材料层13截面尺寸较小，直接与上方的第一电极11以及下方的第二电极12相连。相变存储单元1还可以包括位于相变材料层13与第二电极12之间的绝缘层15，该绝缘层15包裹了相变材料层13的侧壁。
图13为本申请实施例中相变存储单元的另一种结构示意图，图13中示出的相变存储单元1为三维相变存储单元，如图13所示，相变存储单元1包括第一电极11、第二电极12、以及位于第一电极11与第二电极12之间的相变材料层13，相变材料层13还可以包括位于第一电极11与第二电极12之间的选通材料层14，相变材料层13和选通材料层14的截面尺寸较小，第一电极11与第二电极12之间依次包括第一电极层17、相变材料层13、第二电极层18、选通材料层14、第三电极层19，相变材料层13可以通过第一电极层17与第一电极11相连、选通材料层14可以通过第二电极层18与相变材料层13相连，通过第二电极层18与第二电极12相连。相变存储单元1还可以包括位于相变材料层13与第二电极12之间的绝缘层15，该绝缘层15包裹了相变材料层13、选通材料层14、以及电极层的侧壁。第一电极11和第二电极12在不同水平方向上延伸，将存储阵列中的不同相变存储单元连接起来，形成一个阵列排布在一层上，这样的阵列在垂直方向上进一步堆叠形成了交叉堆叠的三维相变存储器。
基于相同的发明构思，本申请还提供了一种相变存储器。图14为本申请实施例中相变存储器的一种结构示意图，如图14所示，相变存储器100包括控制器110和存储介质120，其中，存储介质120包括上述任一实施例中的相变存储单元1组成的阵列。
基于相同的发明构思，本申请还提供了一种相变存储器。
图15为本申请实施例中相变存储器的另一种结构示意图。图15所示，该相变存储器还可以包括行解码器(row decoder)、列解码器(column decoder)、灵敏放大器(sense amplifier)、驱动电路(driver circuitry)、数据缓冲器(data buffer)和数字控制器(digital controller)。多个相变存储单元1的第一电极12连接成第一电极线2，多个相变存储单元1的第二电极13连接成第二电极线3，上述第一电极线2的延伸方向和第二电极线3的延伸方向相交。具体的，上述第一电极线2和第二电极线3交叉处具有唯一确定的一个相变存储单元1。相变存储器的行解码器与所有的第一电极线2电连接，列解码器、灵敏放大器和驱动电路与所有的第二电极线3电连接。而上述行解码器、列解码器、灵敏放大器和驱动电路又分别与数字控制器和数据缓冲器电连接。第一电极线2和第二电极线3中的一个为字线(word line，WL)，另一个为位线(bit line，BL)，可以使得一条字线连接一个行的相变存储单元1，在选中的字线上施加和其他字线不同的电平值，从而选择某一行的相变存储单元1进行读和写等操作。 一条位线连接一个列的相变存储单元1，向列解码器选中的列传递写相变存储单元1操作的电信号，或者沿着选中的列，向列解码器传递读取单元操作得到的电信号。具体可以使第一电极线2为字线，第二电极线3为位线；或者，可以使第一电极线2为位线，第二电极线3为字线，本申请不做限制。
下面以第一电极线2为字线，第二电极线3为位线为例，来说明本申请技术方案中相变存储器的工作过程。相变存储器的行解码器与所有的第一电极线2电连接，列解码器、灵敏放大器和驱动电路与所有的第二电极线3电连接。而上述行解码器、列解码器、灵敏放大器和驱动电路又分别与数字控制器和数据缓冲器电连接。由于位于第一电极线2和第二电极线3交叉处具有唯一确定的一个相变存储单元1，该相变存储单元1具有不同的电阻状态，则可以实现三维相变存储器的读写操作。在进行读取操作时：数字控制器控制行解码器将与设定相变存储单元1连接的第一电极线2的电压调制到读模式(比如电压为0V)，控制列解码器将与该设定相变存储单元1连接的第二电极线3的电压调制到读模式(比如电压为1V)。然后通过与第二电极线3连接的灵敏放大器对该设定相变存储单元1的电流进行测量，以判断该相变存储单元1的相变材料层13的电阻状态，从而获取存储数据的状态。在进行写入操作时：数字控制器控制行解码器将与设定相变存储单元1连接的第一电极线2的电压调制到写模式(比如电压为2V)，控制列解码器将与该设定相变存储单元1连接的第二电极线3的电压调制到写模式(比如电压为0V)，然后通过与第二电极线3连接的驱动电路发出写的脉冲电流或者脉冲电压，传递到上述设定相变存储单元1，改变相变存储单元1的电阻状态，以实现写操作。此外，从灵敏放大器中读取出的数据以及将写入到相变存储器中的数据都存储在数据缓冲器中。
具体的实施例中，请参考图15，上述相变存储器可以为二维相变存储器。具体的实施例中，上述二维相变存储器中的相变存储单元1可以阵列排布，例如可以排布呈n行和m列，其中m和n分别为大于1的正整数。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (15)

  1. 一种相变材料，其特征在于，所述相变材料包括含铪材料，所述含铪材料由含铪或者含铪的化合物掺杂至母体材料形成，所述母体材料包括碲与锗、锑、铋中至少一个元素组成的能够发生相变的化合物。
  2. 如权利要求1所述的相变材料，其特征在于，所述相变材料还包括硫系化合物材料，所述硫系化合物材料位于所述含铪材料的上方或者下方。
  3. 如权利要求2所述的相变材料，其特征在于，所述相变材料包括多个叠加在一起的相变材料单元，每个相变材料单元包括一层所述含铪材料及一层所述硫系化合物材料。
  4. 如权利要求1至3任意一项所述的相变材料，其特征在于，所述含铪或者含铪的化合物在所述相变材料中的不同部分原子百分比不一致。
  5. 如权利要求4所述的相变材料，其特征在于，当所述相变材料位于顶电极与底电极之间时，所述含铪或者含铪的化合物在所述相变材料中从顶电极到底电极方向原子百分比呈由高到低，或者由低到高的梯度变化。
  6. 如权利要求1至5任意一项所述的相变材料，其特征在于，所述含铪材料中，所述铪和/或铪化合物所占的原子百分比为0.1％～40％。
  7. 如权利要求1至6任意一项所述的相变材料，其特征在于，所述含铪材料中，所述铪和/或铪化合物所占的原子百分比为1.5％～6.5％，或者10％～19.5％，25％～35％，7％～14％，17％-24％，或者27％-34％。
  8. 如权利要求1至7任一项所述的相变材料，其特征在于，所述母体材料包括以下任一种材料：GexSbyTe1-x-y、GexBiyTe1-x-y，其中，所述x与所述y之和的取值范围为大于0小于100％，或者所述母体材料还包括Sb xTe y，或者所述母体材料还包括GexSbyBizTe1-x-y-z，其中，所述x,y,z之和为100％。
  9. 如权利要求8所述的相变材料，其特征在于，在所述材料GexSbyTe1-x-y中及Ge xBi yTe 1-x-y中，x:y:(1-x-y)＝4:1:5、2:2:5、3:2:6、1:2:4、或1:4:7，在所述材料Sb xTe y中，x:y＝2:3、1:1、2:1、或者1:0。
  10. 如权利要求8所述的相变材料，其特征在于，在所述GexSbyTe1-x-y中，1/7-1/10≤x:(1-x-y)≤1/4+1/10、或者2/3-1/10≤y:(1-x-y)≤2/3+1/10，或者1/7≤x:(1-x-y)≤2/5，或者2/3≤y:(1-x-y)≤4。
  11. 如权利要求1至10任一项所述的相变存储单元，其特征在于，所述铪化合物包括以下至少一种：铪金属氧化物、铪金属硼化物、铪金属碳化物、铪金属氮系化合物、铪金属硫系化合物、铪金属卤素化合物、铪金属与其它金属形成的二元或多元化合物。
  12. 一种存储芯片，其特征在于，所述存储芯片包括多个存储单元，每个存储单元包括权利要求1至10任意一项所述的相变材料。
  13. 如权利要求12所述的存储芯片，其特征在于，所述每个存储单元还包括，选通材料，所述选通材料掺杂有铪或者铪化合物。
  14. 一种相变存储器，其特征在于，包括控制器和至少一个如权利要求12或13所述的存储芯片，所述控制器用于存储数据至所述至少一个存储芯片，或者从所述至少一个存储芯片读取数据。
  15. 一种电子设备，其特征在于，所述电子设备包括处理器和如权利要求10所述的相变存储器，所述处理器用于存储数据至所述相变存储器，或者从所述相变存储器读取数据。
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