WO2023036320A1 - 一种多层电路板、电路板组件及电子设备 - Google Patents

一种多层电路板、电路板组件及电子设备 Download PDF

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Publication number
WO2023036320A1
WO2023036320A1 PCT/CN2022/118256 CN2022118256W WO2023036320A1 WO 2023036320 A1 WO2023036320 A1 WO 2023036320A1 CN 2022118256 W CN2022118256 W CN 2022118256W WO 2023036320 A1 WO2023036320 A1 WO 2023036320A1
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Prior art keywords
circuit board
branch
differential signal
layer
multilayer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2022/118256
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English (en)
French (fr)
Inventor
程丁宁
刘辰钧
丁学英
赵才军
程维昶
赵振源
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP22866781.2A priority Critical patent/EP4391732A4/en
Publication of WO2023036320A1 publication Critical patent/WO2023036320A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H05K1/0225—Single or multiple openings in a shielding, ground or power plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/04—Fixed joints
    • H01P1/047—Strip line joints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/026—Coplanar striplines [CPS]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09281—Layout details of a single conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09327—Special sequence of power, ground and signal layers in multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09672—Superposed layout, i.e. in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969—Apertured conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09854—Hole or via having special cross-section, e.g. elliptical

Definitions

  • the present application relates to the field of electronic technology, specifically a multilayer circuit board, a circuit board assembly and electronic equipment.
  • Electromagnetic noise will be generated during the working process of electronic equipment, and electromagnetic noise will cause interference to other surrounding electronic equipment. Therefore, only products that have passed relevant tests such as Electro Magnetic Compatibility (EMC) certification can be marketed.
  • EMC Electro Magnetic Compatibility
  • the common-mode noise generated by high-speed chips is the main noise in the high-frequency electromagnetic radiation signal.
  • the common-mode noise mentioned above can excite the high-speed differential signal lines of the board to propagate, and then propagate to various high-speed connectors.
  • the above-mentioned connectors are usually antennas with strong radiation capabilities, which will radiate common-mode noise and cause electromagnetic interference.
  • the present application provides a multilayer circuit board, circuit board assembly and electronic equipment to increase the frequency of common mode noise suppression by the multilayer circuit board, reduce the area occupied by the common mode noise suppression structure, improve the multilayer circuit board and high-density layout, Improve the tolerance ability of preparing multi-layer circuit boards.
  • the present application provides a multilayer circuit board, which includes a differential signal line, a reference ground layer and a stub structure.
  • the above-mentioned differential signal line is located on a layer of the multilayer circuit board, which is different from the reference ground layer located on a layer of the multilayer circuit board. That is to say, the above-mentioned differential signal line and the reference ground layer are located on different layers on the multi-layer circuit board.
  • the above-mentioned differential signal lines are used to transmit differential signals, and the reference ground layer is used to form reference signals to improve the accuracy of signals transmitted by the multilayer circuit board.
  • the above-mentioned branch structure includes a main branch and an auxiliary branch, and the auxiliary branch is connected with the main branch as an integral structure.
  • the branch structure of the multilayer circuit board and the nearby conductive structure form a capacitance-inductance equivalent structure, which is equivalent to setting a capacitance-inductance resonance circuit on the multilayer circuit board.
  • the electric field and magnetic field generated by the common-mode interference signal are closely coupled with the capacitance-inductance resonant circuit formed by the branch structure, thereby suppressing the common-mode noise. Only one end of the above-mentioned main branch is connected to the reference stratum, and the rest are not connected to the reference stratum.
  • the end of the main branch not connected to the reference stratum can also form an equivalent capacitance. Therefore, with the same size and shape of the branch structure, and compared with the connection between the two ends of the main branch and the reference ground, the equivalent capacitance formed in the technical solution of the present application is larger, and the resonant frequency of common-mode noise that can be suppressed is higher. That is to say, under the same resonant frequency requirement for suppressing common mode noise, the branches in the technical solution of the present application can be made smaller and occupy a smaller board area.
  • the structure of the branch structure is relatively simple, including only main branches and auxiliary branches, and occupies less space.
  • this solution is beneficial to meet the high-frequency and high-density wiring requirements of multilayer circuit boards. Since the structure of the above-mentioned branch structure is relatively simple and the size is small, the distance between the branch structure and the adjacent wiring can be far. Even if there is a certain offset in the structure of each part when the multilayer circuit board is prepared, it is not easy to short circuit. Therefore, the tolerance capability of the multilayer circuit board preparation process is relatively strong.
  • the length (first length) of the branch structure along the direction parallel to the extension of the differential signal line may be less than or equal to 2 mm.
  • the size of the branch structure in the technical solution of the present application is small, which is beneficial to reduce the area occupied by the branch structure.
  • the length (second length) of the branch structure perpendicular to the extending direction of the differential signal line is less than or equal to 1 mm.
  • the size of the branch structure in the technical solution of the present application is small, which is beneficial to reduce the occupied area of the branch structure (the occupied area is equal to the first length*the second length).
  • the footprint of the branch structure can be made smaller than or equal to 2mm 2 .
  • the frequency of the common mode noise that can be suppressed by the branch structure in the technical solution is greater than or equal to 10 GHz. to boost the frequency of common-mode noise that can be suppressed.
  • the above-mentioned auxiliary branches are symmetrically arranged on both sides of the main branch.
  • the length direction of the above-mentioned main branch is parallel to the symmetry axis of the auxiliary branch. It can be considered that the symmetry axis of the above-mentioned main branch itself extending along the length direction is symmetrical
  • the axes overlap. This scheme can make the branch structure as a whole a symmetrical structure, which is beneficial to form a symmetrical magnetic field and an electric field, so that the symmetry of the differential signal line is not easy to be broken.
  • the specific shape of the above-mentioned branch structure is not limited.
  • the branch structure is cross-shaped, T-shaped, mountain-shaped, or towel-shaped.
  • a suitable shape of the branch structure can be selected according to the frequency band of the common-mode noise that needs to be suppressed.
  • the above-mentioned main branch is a rectangular main branch.
  • the above-mentioned rectangular main branch is arranged parallel to the differential signal line, that is, the length direction of the above-mentioned rectangular main branch is parallel to the extension direction of the differential signal line.
  • the aforementioned auxiliary branches are axially symmetrical with respect to the differential signal lines.
  • the above-mentioned branch structures are arranged symmetrically with respect to the differential signal lines, which have little impact on the differential signal lines and will not affect the transmission performance of the differential signal lines.
  • the above-mentioned reference formation has a hollow structure, and the above-mentioned hollow structure is located on the peripheral side of the branch structure. Specifically, it can also be considered that the above-mentioned reference formation has an opening, and the branch structure is located in the above-mentioned opening.
  • the above-mentioned hollow structure is arranged symmetrically with respect to the differential signal line, and the edge of the reference formation and the edge of the branch structure form the outline of the above-mentioned hollow structure. In this solution, the above-mentioned hollow structure has no influence on the symmetry of the differential signal line, thus does not affect the transmission performance of the differential signal line.
  • the shape of the outer edge of the hollow structure is not limited, for example, it may be rectangular, circular, trapezoidal or D-shaped, and of course it may also be other symmetrical structures.
  • the differential signal traces include primary traces and secondary traces, and the primary traces are on a layer of a multilayer circuit board, which is different from the secondary traces on a layer of a multilayer circuit board.
  • the above-mentioned primary traces and secondary traces are connected through signal holes, and the above-mentioned signal holes pass through the hollow structure of the reference ground layer. That is to say, the hollow structure in this technical solution is used to form branch structures on the one hand, and is also used to pass through signal holes on the other hand. It is beneficial to simplify the structure of the multilayer circuit board and simplify the preparation process of the multilayer circuit board.
  • the above-mentioned multi-layer circuit board also includes a defective ground structure (DGS), which is disposed on the reference ground layer.
  • DGS defective ground structure
  • the aforementioned defective ground structure is cascaded with the stub structure, so that the filtering bandwidth can be increased, so as to improve the tolerance capability of the circuit board assembly.
  • the widths of the auxiliary branches 1332 and the main branches 1331 can be set according to the processing capacity and the requirements for product performance. Generally speaking, the larger the width, the lower the resonant frequency of common mode noise that can be suppressed. If you need to increase the adjustment frequency, you can reduce the width, but due to the limitation of processing capacity, the width will not be infinitely reduced. Usually, the width can be set to 4 -10mil, in order to better increase the resonance frequency of common mode noise, it can be set to about 4mil.
  • the differential signal line 131 includes two signal lines, the two signal lines are arranged in parallel, the line width of each signal line can be 4-10 mil, and the distance between the two signal lines can be 5-20 mil. In one embodiment, it can be 8-10mil. In this way, the coupling capability between the two signal lines can be guaranteed to meet the transmission performance of the differential signal line, and at the same time, enough space can be reserved for the main branch, so that The vertical projection plane does not overlap with the differential signal line, so that the transmission performance of the differential signal line will not be affected.
  • the present application also provides a circuit board assembly, which includes the multilayer circuit board in any one of the above technical solutions, and further includes a chip, and the chip is connected to a differential signal line.
  • One end of the above-mentioned differential signal line is connected to the chip, and the other end may be connected to a connector, or may also be connected to other electronic devices, which is not limited in this application.
  • the circuit board assembly has a strong ability to resist common mode interference, the area of the anti-interference structure is small, and the wiring density can be made higher.
  • the type of the above-mentioned circuit board assembly is not limited.
  • the above-mentioned circuit board assembly may be a chip package, an electronic module or a single board.
  • the circuit board assembly has a multi-layer circuit board, it can be a common circuit board assembly in the technical solution of the present application.
  • the present application provides an electronic device, which includes a housing and the multilayer circuit board in any of the above technical solutions, where the multilayer circuit board is disposed on the housing.
  • the anti-interference capability of the multilayer circuit board in the electronic device specifically, the type of the electronic device is not limited, for example, it may be a server or a mobile terminal.
  • FIG. 1 is a schematic structural diagram of an electronic device in an embodiment of the present application.
  • Fig. 2 is another schematic structural diagram of the electronic device in the embodiment of the present application.
  • FIG. 3 is a schematic diagram of an exploded structure of a circuit board assembly in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of a circuit board assembly in an embodiment of the present application
  • FIG. 5 is a schematic diagram of a top view structure of a multilayer circuit board in an embodiment of the present application.
  • Fig. 6 is the simulation analysis comparison diagram of the electric field distribution of the resonance point in the embodiment of the present application.
  • Fig. 7 is the comparison diagram of the simulation analysis of the magnetic field distribution at the resonance point in the application embodiment
  • FIG. 8 is a comparison diagram of a simulation analysis of the common mode insertion loss in the embodiment of the present application.
  • FIG. 9 is a comparison diagram of a simulation analysis of differential mode insertion loss in the embodiment of the present application.
  • FIG. 10 is a comparison diagram of a simulation analysis of differential mode return loss in the embodiment of the present application.
  • FIG. 11 is a schematic diagram of a differential-mode magnetic field structure of a multilayer circuit board in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a differential-mode electric field structure of a multilayer circuit board in an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a common-mode magnetic field structure of a multilayer circuit board in an embodiment of the present application.
  • FIG. 14 is a schematic diagram of a common-mode electric field structure of a multilayer circuit board in an embodiment of the present application.
  • 15A-15I are schematic diagrams of the shapes of various branch structures in the embodiments of the present application.
  • 16A-16C are schematic diagrams of the outer edge shapes of the hollow structures of various reference formations in the embodiment of the present application.
  • FIG. 17 is a schematic diagram of another top view structure of the multilayer circuit board in the embodiment of the present application.
  • the circuit board assembly in the embodiment of the present application includes a multilayer circuit board, and the differential signal line and the reference ground layer are arranged on different layers of the multilayer circuit board.
  • a defective ground structure (Defected Ground Structure, DGS), line filter, balanced broadband adjustable common mode filter, etc. are set on the multilayer circuit board.
  • DGS Defect Ground Structure
  • line filter line filter
  • balanced broadband adjustable common mode filter etc.
  • FIG. 1 is a schematic structural diagram of an electronic device in an embodiment of the present application.
  • the above-mentioned electronic device is Server 100.
  • the server 100 may include a casing 110 , a power supply device 120 , a cooling device 130 and a circuit board assembly 1 .
  • the power supply device 120 , the heat dissipation device 130 and the circuit board assembly 1 are disposed on the casing 110 .
  • the above-mentioned power supply device 120 is connected with the circuit board assembly 1 and is used to provide power for the electronic devices on the circuit board assembly 1 .
  • the above heat dissipation device 130 can be used to dissipate heat for the electronic devices on the circuit board assembly 1 to ensure the normal operation of the circuit board assembly 1 .
  • FIG. 2 is another schematic structural diagram of an electronic device in an embodiment of the present application.
  • the above-mentioned electronic device may be a mobile terminal 200, and the mobile terminal 200 may specifically be a notebook computer.
  • the above-mentioned mobile terminal 200 may include a casing 210 and a circuit board assembly 1 , and the above-mentioned circuit board assembly 1 is disposed on the casing 210 .
  • the specific type of the circuit board assembly 1 in the embodiment of the present application is not limited, and the circuit board assembly 1 may be a chip package, an electronic module or a single board.
  • the above-mentioned chip package refers to that the circuit board assembly 1 is provided with a chip, and the circuit board assembly 1 is packaged as a whole to form a chip package. Therefore, it is convenient to install and use the circuit board assembly 1, and the volume of the circuit board assembly 1 is small.
  • the above-mentioned electronic module refers to an electronic module formed by connecting electronic devices with a multilayer circuit board. Referring to FIG. 1 and FIG. 2 , when the above-mentioned circuit board assembly 1 is a single board, the above-mentioned single board may have a chip 11 and a connector 12 , and the chip 11 and the connector 12 are connected by a differential signal line 131 .
  • FIG 3 is a schematic diagram of an exploded structure of the circuit board assembly in the embodiment of the application
  • Figure 4 is a schematic diagram of a partial cross-sectional structure of the circuit board assembly in the embodiment of the application, as shown in Figures 3 and 4, the embodiment of the application
  • the circuit board assembly 1 includes a multilayer circuit board 13 , and may also include a chip 11 and a connector 12 .
  • the above-mentioned multi-layer circuit board 13 includes a differential signal line 131 , a reference ground layer 132 and a stub structure 133 .
  • the above-mentioned differential signal line 131 is used to transmit differential signals
  • the reference ground layer 132 is used to provide a reference signal to improve the accuracy of the differential signal line 131 .
  • the layer of the differential signal line 131 on the multilayer circuit board 13 is different from the layer of the reference ground layer 132 on the multilayer circuit board 13 . That is to say, the differential signal line 131 and the reference ground layer 132 are located on different layers of the multilayer circuit board 13 .
  • the above-mentioned reference ground layer 132 may be located on a layer above or below the layer where the differential signal line 131 is located, which is not limited in the present application.
  • FIG. 5 is a schematic top view of a multilayer circuit board in an embodiment of the present application. Please refer to FIG. 4 and FIG. 5 . That is to say, the aforementioned branch structure 133 is located in the same layer as the reference formation 132 . In addition, the aforementioned branch structure 133 is electrically connected to the reference formation 132 . Specifically, the branch structure 133 includes a main branch 1331 and an auxiliary branch 1332, wherein the auxiliary branch 1332 includes a symmetrical two-part structure, and the two-part structures are respectively marked 1332-1 and 1332-2 in the figure. Parts are all connected to the main branch 1331 .
  • the auxiliary branch 1332 is arranged axially symmetrically on both sides of the main branch 1331 relative to the length direction of the main branch 1331 , that is, the two parts of the auxiliary branch are respectively arranged on both sides of the main branch 1331 .
  • the branch structure 133 only one end of the main branch 1331 is connected to the reference formation 132 , while the other end of the main branch 1331 is not connected to the reference formation 132 , and the auxiliary branch 1332 is not connected to the reference formation 132 either.
  • connection in this application refers to the physical connection unless otherwise specified, that is to say, only one end of the main branch 1331 is physically connected to the reference formation 132, the auxiliary branch 1332 is physically connected to the main branch 1331, and the auxiliary branch 1331 is physically connected to the main branch 1331.
  • the main branch 1331 , the auxiliary branch 1332 and the reference formation 132 may be integrated into one structure, which is not limited in the present application.
  • the axis of symmetry of the auxiliary branches 1332 may overlap with the axis of symmetry of the main branches 1331 extending along the length direction.
  • the above-mentioned branch structure 133 is provided on the reference ground layer 132 of the multilayer circuit board 13, and the branch structure 133 can form an equivalent capacitance inductance with the conductive structure between adjacent layers, which is equivalent to setting a capacitor on the multilayer circuit board 13.
  • Inductive resonant circuit The electric field and magnetic field generated by the common-mode interference signal are closely coupled with the stub structure 133, and the common-mode energy generated by the circuit board assembly 1 is reflected back to the source end, thereby causing the common-mode energy to be lost.
  • the source end may specifically refer to where the chip 11 is located. one end.
  • the branch structure 133 in this scheme Only one end of the branch structure 133 in this scheme is connected with the reference formation 132, and the end of the main branch 1331 that is not connected with the reference formation 132 can also form an equivalent capacitance. Therefore, with the branch structure 133 of the same size and shape, and the main branch Compared with the connection between the two ends of 1331 and the reference ground layer 132, the equivalent capacitance formed in the technical solution of the present application is larger, and the resonant frequency of common mode noise that can be suppressed is higher. That is to say, under the same resonant frequency requirement for suppressing common mode noise, the branches in the technical solution of the present application can be made smaller and occupy a smaller board area.
  • the structure of the branch structure 133 in this solution is relatively simple, only includes the main branch 1331 and the auxiliary branch 1332, and occupies less space.
  • the board area occupied by the branch structure 133 can be less than or equal to 2mm 2 , which can save more than 45% of the space compared with the prior art, and is beneficial to meet the high-frequency and high-density wiring requirements of the circuit board assembly 1 . Since the above branch structure 133 has a relatively simple structure and a small size, the distance between the branch structure and the adjacent wiring can be far. It affects the quality of the differential signal. Therefore, the multilayer circuit board 13 of this solution has a strong tolerance capability in the manufacturing process.
  • main branch includes long sides and short sides, and the length direction of the main branch refers to the extending direction of the long side of the main branch.
  • the length (first length) of the branch structure 133 along the direction parallel to the extension of the differential signal line 131 may be less than or equal to 2 mm.
  • the main branch 1331 and the auxiliary branch 1332 of the branch structure 133 are taken as a whole, and the maximum length of the whole branch structure along the direction parallel to the extension of the differential signal line 131 is less than or equal to 2 mm.
  • the size of the branch structure 133 in the technical solution of the present application is small, which is beneficial to reduce the occupied area of the branch structure.
  • the length (second length) of the branch structure perpendicular to the extending direction of the differential signal line is less than or equal to 1 mm.
  • the main branch 1331 and the auxiliary branch 1332 of the branch structure 133 are taken as a whole, and the maximum length of the whole branch structure along the direction perpendicular to the extension of the differential signal line 131 is less than or equal to 1 mm.
  • the size of the branch structure in the technical solution of the present application is small, which is beneficial to reduce the occupied area of the branch structure, wherein the occupied area is equal to the first length*the second length.
  • the footprint of the branch structure can be made smaller than or equal to 2 mm 2 .
  • the above-mentioned differential signal line 131 is on a layer of the multilayer circuit board 13 and is adjacent to the reference ground layer 132 on a layer of the multilayer circuit board 13 . Then the filtering effect of the stub structure is better, and it is beneficial to reduce the routing distance.
  • the above-mentioned auxiliary branch 1332 may be directly connected to the main branch 1331, or may be connected through other structures.
  • the above-mentioned auxiliary branch 1332 and the main branch 1331 may be integrated. This embodiment facilitates the preparation of the branch structure, and is beneficial to improving the reliability of the connection between the auxiliary branch 1332 and the main branch 1331 .
  • the branch structure and the reference stratum 132 are integrally structured, so that the reference stratum 132 and the branch structure can be formed in one process, which facilitates the preparation of the multilayer circuit board 13 and simplifies the preparation process of the multilayer circuit board 13 .
  • the widths of the auxiliary branches 1332 and the main branches 1331 can be set according to the processing capacity and the requirements for product performance. Generally speaking, the larger the width, the lower the resonant frequency of common mode noise that can be suppressed. If you need to increase the adjustment frequency, you can reduce the width, but due to the limitation of processing capacity, the width will not be infinitely reduced. Usually, the width can be set to 4 -10mil, in order to better increase the resonance frequency of common mode noise, it can be set to about 4mil.
  • the main branch 1331 of the above-mentioned branch structure 133 is a rectangular main branch, the main branch 1331 is arranged in parallel with the differential signal line 131, and the above-mentioned auxiliary branch 1332 is axially opposite to the differential signal line 131 symmetry.
  • the entire stub structure is arranged symmetrically with respect to the differential signal line 131 .
  • the differential signal line 131 includes two signal lines, the above two signal lines are arranged in parallel, the line width of each signal line can be 4-10mil, and the distance between the two signal lines can be 5-20mil . In one embodiment, it can be 8-10mil.
  • the above two differential signal lines have a symmetry axis M.
  • the shape of the above-mentioned branch structure 133 is therefore arranged symmetrically with respect to the above-mentioned axis of symmetry M.
  • the differential signal line 131 formed by two signal lines can also be simplified and understood as one line, which serves as the above-mentioned axis of symmetry.
  • the stub structure is arranged symmetrically with respect to the differential signal line 131 , and the equivalent circuit generated by the stub structure has no influence on the symmetry of the differential signal line 131 , thus not affecting the transmission performance of the differential signal line 131 .
  • the above-mentioned reference formation 132 has a hollow structure 1321, and the hollow structure 1321 is located on the peripheral side of the direct structure.
  • the edge of the reference formation 132 and the edge of the branch structure 133 form the outline of the hollow structure 1321 .
  • the above-mentioned hollow structure 1321 can be arranged symmetrically with respect to the differential signal line 131 , so that the above-mentioned hollow structure 1321 has no influence on the symmetry of the differential signal line 131 , so as not to affect the transmission performance of the differential signal line 131 .
  • a stub structure may be correspondingly provided for each group of differential signal lines.
  • the differential signal lines 131 may include primary traces 1311 and secondary traces 1312 .
  • the primary trace 1311 refers to the portion of the differential signal line 131 near the end where the chip 11 is located
  • the secondary trace 1312 refers to the portion of the differential signal line 131 near the end where the connector 12 is located.
  • the above-mentioned primary wiring 1311 is on the layer of the multilayer circuit board 13
  • the secondary wiring 1312 is on the layer of the multilayer circuit board 13 differently.
  • the reference ground layer 132 is located between the layer where the primary wiring 1311 is located and the layer where the secondary wiring 1312 is located.
  • the above-mentioned signal hole is located in the hollow structure 1321 of the reference ground layer 132 , or in other words, the above-mentioned signal hole passes through the hollow structure 1321 of the reference ground layer 132 .
  • This solution facilitates the manufacture of the above-mentioned signal hole, and the signal hole is not easy to be connected with other structures, so as to ensure the reliability of the connection of the differential signal line 131 .
  • the hollow structure 1321 used to form the stub structure can also be used to form the signal hole, which is beneficial to simplify the structure of the multilayer circuit board 13.
  • the above-mentioned primary wiring 1311 and the secondary wiring 1312 can be directly connected, or, Connections can also be made via electronics.
  • the above-mentioned electronic device may specifically be a capacitor or a resistor.
  • the entire differential signal line may be located on the same layer, which is not specifically limited in the present application.
  • the above-mentioned branch structure 133 may specifically be cross-shaped, and the branch structure 133 includes a first extension extending along a first direction and a second extension intersecting with the first extension. It is electrically connected to the reference ground plane 132 .
  • the area where the first extension part and the second extension part intersect is the intersection point, the area between the intersection point of the branch structure 133 and the connection point with the reference formation 132 is the root 1333 of the branch structure 133, and the rest is the branch structure 133 The sticks of 1334.
  • the branch structure 133 includes a root 1333 (the branch structure in the dotted elliptical frame in the figure), and three branches 1334 (the branch structure in the three dotted square boxes in the figure) .
  • the above-mentioned branch structure 133 can make the multilayer circuit board 13 form a capacitive inductance resonant circuit, and the resonance frequency of the common-mode noise that the above-mentioned branch structure 133 can suppress satisfies f:
  • L is the equivalent inductance of the branch structure 133
  • C is the equivalent capacitance of the branch structure 133 .
  • Fig. 6 is the comparison diagram of the simulation analysis of the electric field distribution at the resonance point in the embodiment of the present application. Please combine Fig. 5 and Fig. 6 to analyze respectively the distribution of the electric field at the resonance point 2 of the multilayer circuit board 13 with the cross-shaped branch structure 133, and the distribution without The electric field 2 at the resonant point of the multilayer circuit board 13 with the cross-shaped branch structure 133 is distributed. It can be seen that the electric field 2 is mainly distributed in the area where the branches 1334 of the branch structure 133 are located. Then the above-mentioned branches 1334 can form an equivalent capacitance. The length of the branch 1334 affects the value of the equivalent capacitance. The longer the branch 1334 is, the larger the equivalent capacitance is, and the lower the frequency of the suppressed common mode noise is.
  • Fig. 7 is the comparison diagram of the simulation analysis of the magnetic field distribution at the resonance point in the application embodiment. Please combine Fig. 5 and Fig. 7 to analyze the distribution of the magnetic field 3 at the resonance point of the multilayer circuit board 13 with the cross-shaped branch structure 133 and the distribution without the cross-shaped branch structure 133 respectively.
  • the resonant point magnetic field 3 of the multilayer circuit board 13 with the branch structure 133 is distributed. It can be seen that the magnetic field 3 is mainly distributed in the region of the root 1333 of the branch structure 133 .
  • the root portion 1333 can form an equivalent inductance.
  • the length of the root portion 1333 of the branch structure 133 affects the value of the equivalent inductance. The longer the root portion 1333 is, the larger the equivalent inductance is, and the lower the frequency of the suppressed common mode noise is.
  • the structure of the branch structure 133 is designed based on the above-mentioned design principles and a reasonable size is designed (for example, the effective occupied area is less than a certain value, such as less than 2mm 2 ), so that the frequency of the branch structure 133 suppressing common mode noise is greater than or equal to 10GHz. That is to say, in the technical solution of the present application, higher frequency common mode noise can be suppressed by designing a small-sized branch structure 133 . It should be noted that, in order to meet various specific performances, those skilled in the art can obtain the specific structural shape and size of the branch structure through simulation and testing based on the above-mentioned design principles.
  • the minimum size of the branch structure can also be determined in combination with machining capabilities and actual product requirements, for example, it can be approximately equal to 0.4mm ⁇ 0.5mm.
  • the multilayer circuit board 13 of the circuit board assembly 1 includes a four-layer structure, which are the first layer, the second layer, the third layer and the fourth layer in sequence.
  • the above-mentioned primary traces 1311 are set on the first layer
  • the reference ground layer 132 corresponding to the primary traces 1311 is set on the second layer
  • the secondary traces 1312 are set on the third layer
  • the fourth layer is the reference ground layer corresponding to the secondary traces.
  • the specific materials of the primary traces 1311, the reference ground layer 132, the secondary traces 1312, and the reference ground layer 134 corresponding to the secondary traces are not limited, for example, they may be copper, or may include silver and other materials with better conductivity. .
  • the reference ground layer 132 and the cross-shaped stub structure 133 are arranged symmetrically with respect to the differential signal line 131 .
  • the branch structure 133 is set on the reference ground layer 132 corresponding to the primary line; the above-mentioned branch structure can also be set on the reference ground layer 134 corresponding to the secondary line; or, the reference ground layer 132 corresponding to the primary line and the secondary line
  • the reference formations 134 corresponding to the traces are all provided with branch structures 133 .
  • FIG. 8 is a simulation analysis comparison diagram of the common mode insertion loss of the embodiment of the present application.
  • the value of the common mode insertion loss of the circuit board assembly 1 provided with the stub structure 133 is relatively low.
  • the value of the common mode insertion loss is relatively high when the aforementioned branch structure 133 is not provided.
  • FIG. 9 is a comparison diagram of a simulation analysis of differential mode insertion loss in the embodiment of the present application. As shown in FIG.
  • FIG. 10 is a comparison diagram of a simulation analysis of the differential mode return loss in the embodiment of the present application. As shown in FIG.
  • the curve of the differential mode return loss of the circuit board assembly 1 with the stub structure 133 is set, Compared with the prior art, when the above-mentioned branch structure 133 is not provided, the differential mode return loss is not much different, and it is also within an acceptable range.
  • FIG. 11 is a schematic diagram of a differential-mode magnetic field structure of a multilayer circuit board in the embodiment of the present application. As shown in FIG. The symmetrical plane in the middle of the line 131 is a virtual electric wall. Adding the stub structure 133 in the middle will not affect the differential signal.
  • FIG. 12 is a schematic diagram of a differential-mode electric field structure of the multilayer circuit board 13 in the embodiment of the present application. As shown in FIG. 12, when the differential signal line 131 transmits the differential-mode signal, the loop formed by the branch structure 133 is parallel to the magnetic field lines , will not be excited by the magnetic field.
  • the magnetic field and electric field when transmitting the differential mode signal will not couple with the stub structure 133 , and have no influence on the transmission of the differential mode signal by the circuit board assembly 1 .
  • FIG. 13 is a schematic diagram of a common-mode magnetic field structure of a multilayer circuit board in the embodiment of the present application. As shown in FIG. The electric field of the wire 131 terminates at the stub structure 133 .
  • FIG. 14 is a schematic diagram of a common-mode electric field structure of a multilayer circuit board in the embodiment of the present application. As shown in FIG. 14, when the differential signal line 131 transmits a common-mode signal, the magnetic field will pass through the middle branch structure 133 to form a loop . Both the electric field and the magnetic field resonate at the stub structure 133. At the resonant frequency, the common-mode impedance of the differential signal is mismatched, and the common-mode energy will be reflected back to the source and dissipated. It cannot continue to propagate forward and will not be excited by the magnetic field. Therefore, the aforementioned branch structure 133 is provided to suppress electromagnetic interference.
  • the specific shape of the above-mentioned branch structure 133 is not limited, for example, it can be a cross shape, a T shape, a mountain shape or a towel shape or other symmetrical structures. It can be understood that the shape of the branch structure 133 here is only similar to the shapes of various characters or letters. Rather than being exactly the same, those skilled in the art can obtain the final shape by referring to the design principles in the foregoing embodiments and various schematic diagrams in FIGS. 15A-15I .
  • the branch structure 133 in the embodiment shown in FIG. 15A is cross-shaped; the branch structure 133 in the embodiment shown in FIG. 15B is T-shaped. ;
  • the branch structure 133 in the embodiment shown in FIG. 15C is in the shape of a mountain;
  • the branch structure 133 in the embodiment shown in FIG. 15D is in the shape of a towel.
  • the above-mentioned branch structures 133 only need to be arranged symmetrically, and may not be in the above-mentioned shape.
  • the shape of the branch structure 133 in the embodiment shown in Figures 15E-15G are schematic diagrams of the shapes of various branch structures in the embodiment of the present application.
  • the branch structure 133 in the embodiment shown in FIG. 15C is in the shape of a mountain;
  • the branch structure 133 in the embodiment shown in FIG. 15D is in the
  • auxiliary branch 1332 of the above-mentioned branch structure can be parallel to the length direction of the main branch 1331, or the auxiliary branch 1332 of the above-mentioned branch structure can also intersect the length direction of the main branch 1331, that is to say, the auxiliary branch 1332 can be perpendicular to the main branch 1331 , or at an angle.
  • the auxiliary branch 1332 also includes a portion that can extend obliquely.
  • the shape of the outer edge of the hollow structure 1321 is not limited, for example, it may be a symmetrical structure such as a rectangle, a circle, a trapezoid or a D shape. It should be noted that the outer edge of the hollow structure 1321 refers to the edge of the hollow structure 1321 adjacent to the reference formation 132 , that is, the branch structure 133 is ignored.
  • 16A-16C are schematic diagrams of the shape of the hollow structure 1321 of the reference formation 132 in the embodiment of the present application.
  • the hollow structure 1321 of the reference formation 132 in the embodiment shown in FIG. 6 is rectangular; the reference formation 1321 in the embodiment shown in FIG. 16A
  • the hollow structure 1321 of 132 is circular; the hollow structure 1321 of the reference formation 132 in the embodiment shown in FIG.
  • the hollow structure 1321 of the reference formation 132 in the embodiment shown in FIG. 16C is D-shaped.
  • the above-mentioned hollow structure 1321 only needs to be arranged symmetrically, and may not be in the above-mentioned shape, which is not limited in the present application.
  • FIG. 17 is another schematic top view of the multilayer circuit board in the embodiment of the present application.
  • the defective ground structure 4 is also set in the reference formation 132 .
  • both the defective ground structure 4 and the stub structure 133 are set in the reference formation 132 , and the defective ground structure 4 and the stub structure 133 are cascaded, thereby increasing the filtering bandwidth and improving the anti-interference ability of the circuit board assembly 1 .

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Abstract

本申请提供了一种多层电路板、电路板组件及电子设备，该多层电路板包括差分信号线、参考地层和枝节结构。差分信号线和参考地层在多层电路板上位于不同的层。上述枝节结构包括主枝节和辅助枝节，主枝节的一端与参考地层连接，辅助枝节与主枝节连接。该多层电路板的枝节结构与附近的导电结构形成电容电感等效结构，相当于设置了一个电容电感谐振电路。枝节结构仅主枝节的一端与参考地层连接，其余部分均不与参考地层连接，枝节结构的滤波效果较好，可以抑制更高频率的共模干扰信号。枝节结构的结构较为简单，占用的空间较少，有利于满足多层电路板的高频、高密布线要求。此外，多层电路板制备过程的容差能力较强。

Description

一种多层电路板、电路板组件及电子设备
相关申请的交叉引用
本申请要求在2021年09月13日提交中国专利局、申请号为202111068756.6、申请名称为“一种多层电路板、电路板组件及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，具体为一种多层电路板、电路板组件及电子设备。
背景技术
电子设备工作过程中会产生电磁噪声，而电磁噪声会对周边的其他电子设备造成干扰，因此只有通过电磁兼容性(Electro Magnetic Compatibility，EMC)认证等相关测试的产品才能上市。
随着通信技术的不断发展，电子产品的芯片的工作速率不断增加，导致产品EMC认证的电磁辐射测试频段从30MHz～1GHz提升到30MHz～6GHz，美国FCC标准更是要求电磁辐射测试频段的最大值达到40GHz。通常情况下，高速芯片产生的共模噪声是高频电磁辐射信号中的主要噪声。上述共模噪声会激励电路板的高速差分信号线进行传播，然后传播到各类高速连接器。上述连接器通常都是辐射能力较强的天线，会将共模噪声辐射出去，造成电磁干扰。
现有抑制电磁干扰的实施方式为从板级进行共模噪声抑制，从业界公开的缺陷地结构滤波器(Defected Ground Structure，DGS)、走线滤波器、平衡式宽带可调共模滤波器等技术来看，其结构尺寸均较大无法满足当前产品高频、高密布局布线要求，特别是部分产品高速差分信号线通道很多，且差分信号线对的间距小于1mm。
发明内容
本申请提供一种多层电路板、电路板组件及电子设备，以提升多层电路板抑制共模噪声的频率，减小共模噪声抑制结构占用的面积，提升多层电路板和高密布局，提升制备多层电路板的容差能力。
第一方面，本申请提供了一种多层电路板，该多层电路板包括差分信号线、参考地层和枝节结构。上述差分信号线在多层电路板的层，与参考地层位于多层电路板的层不同。也就是说，上述差分信号线和参考地层在多层电路板上位于不同的层。上述差分信号线用于传输差分信号，参考地层用于形成参考信号，以提升多层电路板传输的信号的准确性。上述枝节结构包括主枝节和辅助枝节，辅助枝节与主枝节连接为一体结构。上述枝节结构只有主枝节的一端与参考地层连接，主枝节的另一端不与参考地层连接，且辅助枝节也不与参考地层连接。本申请技术方案中，多层电路板的枝节结构与附近的导电结构形成电容电感等效结构，从而相当于在多层电路板设置了一个电容电感谐振电路。共模干扰信号产生的电场和磁场与枝节结构形成的电容电感谐振电路产生紧密耦合，从而抑制共模噪声。 仅仅上述主枝节的一端与参考地层连接，其余部分均不与参考地层连接，该方案中，主枝节未与参考地层连接的一端，也可以形成等效电容，因此，与同样尺寸和形状的枝节结构，且主枝节的两端与参考地层连接相比，本申请技术方案中形成的等效电容较大，可以抑制的共模噪声的谐振频率更高。也就是说，在同样的抑制共模噪声的谐振频率需求下，本申请技术方案中的枝节可以制作的较小，占板面积也较小。此外，枝节结构的结构较为简单，只包括了主枝节和辅助枝节，占用的空间也较少。因此，该方案有利于满足多层电路板的高频、高密布线要求。由于上述枝节结构的结构较为简单，且尺寸较小，枝节结构可以制备的离相邻走线的距离较远，即使在制备多层电路板时各部分结构存在一定的偏移，也不易出现短路等问题，因此，多层电路板制备过程的容差能力较强。
具体制备上述枝节结构时，可以使得枝节结构沿平行于差分信号线延伸方向的长度(第一长度)小于或者等于2mm。本申请技术方案中的枝节结构的尺寸较小，有利于减少枝节结构的占板面积。
上述枝节结构沿垂直于差分信号线延伸方向的长度(第二长度)小于或者等于1mm。同样，本申请技术方案中的枝节结构的尺寸较小，有利于减少枝节结构的占板面积(占板面积等于第一长度*第二长度)。例如，可以使得枝节结构的占板面积小于等于2mm 2。
本技术方案中的枝节结构可以抑制的共模噪声的频率大于或等于10GHz。以提升可以抑制的共模噪声的频率。
此外，上述辅助枝节对称设置于主枝节的两侧，具体的，上述主枝节的长度方向与辅助枝节的对称轴平行，可以认为，上述主枝节自身沿长度方向延伸的对称轴与辅助枝节的对称轴重叠。该方案可以使枝节结构整体为对称结构，有利于形成对称的磁场和电场，从而不易破坏差分信号线的对称性。
上述枝节结构的具体形状不做限制，例如，枝节结构为十字形、T形、山字形或者巾字形等，具体可以根据实际需要抑制的共模噪声的频段来选择合适形状的枝节结构。
具体的技术方案中，上述主枝节为矩形主枝节。上述矩形主枝节与差分信号线平行设置，也就是说，上述矩形主枝节的长度方向与差分信号线的延伸方向平行。上述辅助枝节相对于差分信号线轴对称，该方案中，上述枝节结构关于差分信号线对称设置，对于差分信号线的影响较小，不会影响差分信号线的传输性能。
上述参考地层具有镂空结构，上述镂空结构位于枝节结构的周侧。具体的，还可以认为上述参考地层具有开口，枝节结构位于上述开口内。上述镂空结构相对于差分信号线对称设置，参考地层的边缘与枝节结构的边缘形成了上述镂空结构的轮廓。该方案中，上述镂空结构对于差分信号线的对称性无影响，从而不影响差分信号线的传输性能。
上述镂空结构的外边缘形状不做限制，例如，可以为矩形、圆形、梯形或者D字形，当然还可以为其它的对称结构。
具体的技术方案中，上述差分信号走线包括初级走线和次级走线，上述初级走线在多层电路板的层，与次级走线在多层电路板的层不同。上述初级走线与次级走线通过信号孔连接，上述信号孔穿过参考地层的镂空结构。也就是说，本技术方案中的镂空结构一方面用于形成枝节结构，另一方面，还用于穿过信号孔。有利于简化多层电路板的结构，简化多层电路板的制备工艺。
上述多层电路板还包括缺陷地结构(DGS)，该缺陷地结构设置于参考地层。上述缺陷地结构与枝节结构级联，从而可以增加滤波带宽，以提升电路板组件的容差能力。
本领域技术人员可以结合加工能力以及对产品性能的要求来设置辅助枝节1332和主枝节1331的宽度。通常来说，宽度越大，可以抑制的共模噪声的谐振频率更低，如果需要提升调整频率，可以减少宽度，但由于受到加工能力限制，宽度也不会无限缩小，通常宽度可以设置为4-10mil，为了更好地增大共模噪声的谐振频率，可以设置为4mil左右。
本申请中，差分信号线131包括两根信号线，上述两根信号线平行设置，每根信号线的线宽可以是4-10mil，两个信号线之间的间距可以是5-20mil。在一个实施例中，可以是8-10mil，这样，既可以保证两根信号线的之间的耦合能力从而满足差分信号线的传输性能，同时，又能够给主枝节留出足够的空间，使之垂直投影面不与差分信号线重叠，从而不会影响差分信号线的传输性能。
第二方面，本申请还提供了一种电路板组件，该电路板组件包括上述任一技术方案中的多层电路板，还包括芯片，芯片与差分信号线连接。上述差分信号线的一端与芯片连接，另一端可以与连接器连接，或者，也可以与其它电子器件连接，本申请不做限制。该电路板组件抗共模干扰的能力较强，抗干扰结构的面积较小，布线密度可以做的较高。
具体的技术方案中，上述电路板组件的类型不做限制。例如，上述电路板组件可以为芯片封装、电子模块或者单板。只要具有多层电路板的电路板组件，都可以为本申请技术方案中共的电路板组件。
第三方面，本申请提供了一种电子设备，该电子设备包括壳体和上述任一技术方案中的多层电路板，该多层电路板设置于壳体。该电子设备中的多层电路板的抗干扰能力，具体的，上述电子设备的类型不做限制，例如，可以为服务器或者移动终端等。
附图说明
图1为本申请实施例中电子设备的一种结构示意图；
图2为本申请实施例中电子设备的另一种结构示意图；
图3为本申请实施例中电路板组件的一种爆炸结构示意图；
图4为本申请实施例中电路板组件的一种局部剖面结构示意图；
图5为本申请实施例中多层电路板的一种俯视结构示意图；
图6为本申请实施例中谐振点电场分布仿真分析对比图；
图7为申请实施例中谐振点磁场分布仿真分析对比图；
图8为本申请实施例中共模插损的一种仿真分析对比图；
图9为本申请实施例中差模插损的一种仿真分析对比图；
图10为本申请实施例中差模回损的一种仿真分析对比图；
图11为本申请实施例中多层电路板的一种差模磁场结构示意图；
图12为本申请实施例中多层电路板的一种差模电场结构示意图；
图13为本申请实施例中多层电路板的一种共模磁场结构示意图；
图14为本申请实施例中多层电路板的一种共模电场结构示意图；
图15A-图15I为本申请实施例中各种枝节结构的形状示意图；
图16A-图16C为本申请实施例中各种参考地层的镂空结构的外边缘形状示意图；
图17为本申请实施例中多层电路板的另一种俯视结构示意图。
附图标记：
100-服务器；                       110-壳体；
120-电源装置；                      130-散热装置；
200-移动终端；                      210-壳体；
1-电路板组件；                      11-芯片；
12-连接器；                         13-多层电路板；
131-差分信号线；                    1311-初级走线；
1312-次级走线；                     132-参考地层；
1321-镂空结构；                     133-枝节结构；
1331-主枝节；                       1332-辅助枝节；
1333-根部；                         1334-枝条；
134-与次级走线对应的参考地层；      2-电场；
3-磁场；                            4-缺陷地结构；
M-对称轴。
具体实施方式
为了方便理解本申请实施例提供的多层电路板、电路板组件及电子设备，下面介绍一下其应用场景。随着电子信息技术的发展，电子设备的工作效率不断提高，高速芯片的速率越来越高，也越容易产生共模噪声。上述高速芯片通过差分信号线来传输信号，为了提升信号精准性，还包括参考地层。本申请实施例中的电路板组件包括多层电路板，差分信号线和参考地层设置于多层电路板的不同层。现有技术中，为了抑制电路板组件产生的噪声，在多层电路板设置缺陷地结构(Defected Ground Structure，DGS)、走线滤波器、平衡式宽带可调共模滤波器等，上述方案的结构尺寸较大无法满足当前产品单板的高频、高密布线要求。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“具体的实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
本申请提供了一种电子设备，本申请实施例中的电子设备的具体类型不做限制。例如，该电子设备可以为服务器、移动终端、光模块和交换机等，图1为本申请实施例中电子设备的一种结构示意图，如图1所示，一种实施例中，上述电子设备为服务器100。该服务器100可以包括壳体110、电源装置120、散热装置130和电路板组件1。上述电源装置120、散热装置130和电路板组件1设置于上述壳体110。上述电源装置120与电路板组件1连接，用于为电路板组件1上的电子器件提供电源。上述散热装置130则可以用于为电路板组件1上的电子器件散热，保证电路板组件1的正常运行。
图2为本申请实施例中电子设备的另一种结构示意图，如图2所示，另一种实施例中，上述电子设备可以为移动终端200，该移动终端200具体可以为笔记本电脑。上述移动终端200可以包括壳体210和电路板组件1，上述电路板组件1设置于壳体210。
本申请实施例中电路板组件1的具体类型不做限制，该电路板组件1可以为芯片封装、 电子模块或者单板。具体的上述芯片封装指的是电路板组件1设置有芯片，电路板组件1整体封装成整体结构，形成芯片封装。从而便于安装和使用电路板组件1，且电路板组件1的体积较小。上述电子模块指的是利用多层电路板连接电子器件，形成的电子模块。参考图1和图2，上述电路板组件1为单板时，上述单板可以具有芯片11和连接器12，芯片11与连接器12之间利用差分信号线131连接。
图3为本申请实施例中电路板组件的一种爆炸结构示意图，图4为本申请实施例中电路板组件的一种局部剖面结构示意图，如图3和图4所示，本申请实施例中的电路板组件1包括多层电路板13，还可以包括芯片11和连接器12。上述多层电路板13包括差分信号线131、参考地层132和枝节结构133。上述差分信号线131用于传输差分信号，参考地层132用于提供参考信号，以提高差分信号线131的准确性。具体设置上述多层电路板13时，上述差分信号线131在多层电路板13的层，与参考地层132在多层电路板13的层不同。也就是说，上述差分信号线131与参考地层132位于多层电路板13的不同层。具体的，上述参考地层132可以位于差分信号线131所在层的上一层，或者下一层，本申请对此不做限制。
图5为本申请实施例中多层电路板的一种俯视结构示意图，请结合图4和图5，上述枝节结构133设置于参考地层132在多层电路板13的层。也就是说，上述枝节结构133与参考地层132位于同一层。此外，上述枝节结构133与参考地层132电连接。具体的，上述枝节结构133包括主枝节1331和辅助枝节1332，其中，该辅助枝节1332包括对称的两部分结构，该两部分结构在图中的标号分别为1332-1和1332-2，上述两部分都与主枝节1331连接。具体的，辅助枝节1332相对于主枝节1331的长度方向轴向对称的设置于主枝节1331的两侧，即辅助枝节的两部分结构分别设置在主枝节1331的两侧。该枝节结构133中仅仅主枝节1331的一端与参考地层132连接，而主枝节1331的另一端不与参考地层132连接，且辅助枝节1332也不与参考地层132连接。值得说明的是，本申请中的连接如无特殊说明指的是物理连接，也就是说，仅主枝节1331的一端与参考地层132物理连接，辅助枝节1332与主枝节1331物理连接，而辅助枝节1332与参考地层132之间不存在物理连接。具体的，可以使得主枝节1331、辅助枝节1332和参考地层132为一体结构，本申请对此不做限制。具体设置上述辅助枝节时，可以使上述辅助枝节1332的对称轴与主枝节1331沿长度方向延伸的对称轴重叠。
该方案中，多层电路板13的参考地层132设置上述枝节结构133，该枝节结构133可以与相邻层间的导电结构形成等效电容电感，相当于在多层电路板13设置了一个电容电感谐振电路。共模干扰信号产生的电场和磁场与枝节结构133产生紧密耦合，电路板组件1产生的共模能量被反射回源端，从而使得共模能量被损耗，该源端具体可以指芯片11所在的一端。该方案中的枝节结构133仅一端与参考地层132连接，则主枝节1331未与参考地层132连接的一端，也可以形成等效电容，因此，与同样尺寸和形状的枝节结构133，且主枝节1331的两端与参考地层132连接相比，本申请技术方案中形成的等效电容较大，可以抑制的共模噪声的谐振频率更高。也就是说，在同样的抑制共模噪声的谐振频率需求下，本申请技术方案中的枝节可以制作的较小，占板面积也较小。此外，该方案中的枝节结构133的结构较为简单，只包括了主枝节1331和辅助枝节1332，占用的空间较少。例如，上述枝节结构133占板面积可以小于或者等于2mm 2，相比于现有技术，可以节约45％以上的空间，有利于满足电路板组件1的高频、高密布线要求。由于上述枝节结构133的 结构较为简单，且尺寸较小，枝节结构可以制备的离相邻走线的距离较远，即使在制备多层电路板13时各部分结构存在一定的偏移，也不易影响差分信号质量，因此，该方案多层电路板13制备过程的容差能力较强。
值得说明的是，上述主枝节包括长边和短边，主枝节的长度方向指的是：主枝节的长边的延伸方向。
具体制备上述枝节结构133时，可以使得枝节结构133沿平行于差分信号线131延伸方向的长度(第一长度)小于或者等于2mm。该实施例中，枝节结构133的主枝节1331和辅助枝节1332作为整体，该枝节结构的整体的尺寸沿平行于差分信号线131延伸方向的最大长度小于或者等于2mm。本申请技术方案中的枝节结构133的尺寸较小，有利于减少枝节结构的占板面积。
上述枝节结构沿垂直于差分信号线延伸方向的长度(第二长度)小于或者等于1mm。该实施例中，枝节结构133的主枝节1331和辅助枝节1332作为整体，该枝节结构的整体的尺寸沿垂直于差分信号线131延伸方向的最大长度小于或者等于1mm。同样，本申请技术方案中的枝节结构的尺寸较小，有利于减少枝节结构的占板面积，其中，占板面积等于第一长度*第二长度。例如，可以使得枝节结构的占板面积小于或者等于2mm 2。
具体的技术方案中，上述差分信号线131在多层电路板13的层，与参考地层132在多层电路板13的层相邻。则枝节结构的滤波效果更好，且有利于减少走线距离。
上述辅助枝节1332可以与主枝节1331直接连接，也可以通过其它结构实现连接。具体的实施例中，上述辅助枝节1332和主枝节1331可以为一体结构。该实施例便于制备枝节结构，且有利于提升辅助枝节1332与主枝节1331之间连接的可靠性。进一步的实施例中，上述枝节结构与参考地层132为一体结构，则可以通过一次工艺形成参考地层132和枝节结构，便于制备多层电路板13，简化多层电路板13的制备工艺。
本领域技术人员可以结合加工能力以及对产品性能的要求来设置辅助枝节1332和主枝节1331的宽度。通常来说，宽度越大，可以抑制的共模噪声的谐振频率更低，如果需要提升调整频率，可以减少宽度，但由于受到加工能力限制，宽度也不会无限缩小，通常宽度可以设置为4-10mil，为了更好地增大共模噪声的谐振频率，可以设置为4mil左右。
请继续参考图5，具体的实施例中，上述枝节结构133的主枝节1331为矩形主枝节，该主枝节1331与差分信号线131平行设置，且上述辅助枝节1332相对于差分信号线131轴向对称。该方案中，整个枝节结构相对于差分信号线131对称设置。具体的，可以理解，差分信号线131包括两根信号线，上述两根信号线平行设置，每根信号线的线宽可以是4-10mil，两个信号线之间的间距可以是5-20mil。在一个实施例中，可以是8-10mil，这样，既可以保证两根信号线的之间的耦合能力从而满足差分信号线的传输性能，同时，又能够给主枝节留出足够的空间，使之垂直投影面不与差分信号线重叠，从而不会影响差分信号线的传输性能。上述两根差分信号线具有对称轴M。上述枝节结构133的形状也就关于上述对称轴M对称设置。具体的，还可以将两根信号线构成的差分信号线131简化理解成一根线，作为上述对称轴。该方案中，枝节结构相对于差分信号线131对称设置，则枝节结构产生的等效电路对于差分信号线131的对称性无影响，从而不影响差分信号线131的传输性能。
此外，上述参考地层132具有镂空结构1321，该镂空结构1321位于直接结构的周侧。或者说，上述参考地层132的边缘与枝节结构133的边缘形成了镂空结构1321的轮廓。 本申请技术方案中，对于镂空结构1321的轮廓无特殊要求。但是，可以使得上述镂空结构1321关于差分信号线131对称设置，从而使得上述镂空结构1321对于差分信号线131的对称性无影响，从而不影响差分信号线131的传输性能。
值得说明的是，本申请技术方案中，可以使得每组差分信号线对应设置一个枝节结构。
请参考图4和图5，具体设置上述多层电路板13时，可以使差分信号线131包括初级走线1311和次级走线1312。具体的，上述初级走线1311指的是差分信号线131靠近芯片11所在的一端的部分，次级走线1312指的是差分信号线131靠近连接器12所在的一端的部分。上述初级走线1311在多层电路板13的层，与次级走线1312在多层电路板13的层不同。具体的实施例中，上述参考地层132位于初级走线1311所在的层与次级走线1312所在的层之间。上述信号孔位于参考地层132的镂空结构1321内，或者说，上述信号孔穿过参考地层132的镂空结构1321。该方案便于制作上述信号孔，信号孔不易与其它结构连接，保证差分信号线131连接的可靠性。该方案中，用于形成枝节结构的镂空结构1321，还可以用于形成信号孔，有利于简化多层电路板13的结构，上述初级走线1311和次级走线1312可以直接连接，或者，也可以通过电子器件进行连接。上述电子器件具体可以为电容或者电阻。
当然，在其它实施例中，整根差分信号线可以位于同一层，本申请对此不做具体限制。
请继续参考图5，上述枝节结构133具体可以为十字形，枝节结构133包括沿第一方向延伸的第一延伸部和与上述第一延伸部交叉设置的第二延伸部，上述第一延伸部与参考地层132电连接。上述第一延伸部与第二延伸部交叉的区域为交叉点，上述枝节结构133的交叉点和与参考地层132的连接点之间的区域为枝节结构133的根部1333，其余部分为枝节结构133的枝条1334。例如图5所示的实施例中，可以认为该枝节结构133包括一个根部1333(图中虚线椭圆框中的枝节结构)，以及三个枝条1334(图中三个虚线方框中的枝节结构)。上述枝节结构133可以使得多层电路板13形成电容电感谐振电路，上述枝节结构133能够抑制的共模噪声的谐振频率满足f：
Figure PCTCN2022118256-appb-000001
其中，L为枝节结构133的等效电感，C为枝节结构133的等效电容。
发明人对本申请技术方案做出了仿真分析。图6为本申请实施例中谐振点电场分布仿真分析对比图，请结合图5和图6，分别分析具有十字形枝节结构133的多层电路板13的谐振点电场2的分布，以及不具有十字形枝节结构133的多层电路板13的谐振点电场2分布。可见，电场2主要分布于枝节结构133的枝条1334所在的区域。则上述枝条1334可以形成等效电容。上述枝条1334的长度枝节结构133影响了等效电容的值，上述枝条1334越长，等效电容越大，抑制的共模噪声的频率越低。
图7为申请实施例中谐振点磁场分布仿真分析对比图，请结合图5和图7，分别分析具有十字形枝节结构133的多层电路板13的谐振点磁场3分布，以及不具有十字形枝节结构133的多层电路板13的谐振点磁场3分布。可见，磁场3主要分布于枝节结构133的根部1333区域。则上述根部1333可以形成等效电感。上述根部1333的长度枝节结构133影响了等效电感的值，上述根部1333越长，等效电感越大，抑制的共模噪声的频率越低。
本申请实施例中，基于上述设计原则设计枝节结构133的结构并设计合理的尺寸(例 如有效占用面积小于一定值，如小于2mm 2)，可以使枝节结构133抑制共模噪声的频率大于或等于10GHz。也就是说，本申请技术方案中，可以通过设计小尺寸的枝节结构133来抑制较高频率的共模噪声。需要说明的是，为满足各种具体性能，本领域技术人员可以基于上述设计原则对枝节结构具体的结构形状以及尺寸通过仿真、测试来得到。此外，枝节结构的最小尺寸也可以结合机械加工能力以及实际产品需求来确定，例如，可以约等于0.4mm×0.5mm。
以枝节结构133为十字形为例，下面列举一个具体的实施例。该实施例中，电路板组件1的多层电路板13包括四层结构，依次为第一层、第二层、第三层和第四层。上述初级走线1311设置于第一层，与初级走线1311对应的参考地层132设置于第二层，次级走线1312设置于第三层，第四层为与次级走线对应的参考地层134。上述初级走线1311、参考地层132、次级走线1312和与次级走线对应的参考地层134的具体材质不做限制，例如可以为铜，或者还可以包括银等导电性较好的材料。参考地层132和十字形的枝节结构133关于差分信号线131对称设置。图中枝节结构133设置于与初级走线对应的参考地层132；上述枝节结构还可以设置于与次级走线对应的参考地层134；或者，与初级走线对应的参考地层132和与次级走线对应的参考地层134均设置有枝节结构133。
图8为本申请实施例中共模插损的一种仿真分析对比图，如图8所示，本申请实施例中，设置了枝节结构133的电路板组件1的共模插损数值较低。现有技术中，未设置上述枝节结构133时共模插损数值较高。图9为本申请实施例中差模插损的一种仿真分析对比图，如图9所示，本申请实施例中，设置了枝节结构133的电路板组件1的差模插损的曲线，与现有技术中，未设置上述枝节结构133时差模插损相比，相差不大于0.1dB，在可接受的范围内。图10为本申请实施例中差模回损的一种仿真分析对比图，如图10所示，本申请实施例中，设置了枝节结构133的电路板组件1的差模回损的曲线，与现有技术中，未设置上述枝节结构133时差模回损相比，相差不大，也在可接受的范围内。
图11为本申请实施例中多层电路板的一种差模磁场结构示意图，如图11所示，当差分信号线131传输差模信号时，一组差分信号线131中的两根差分信号线131中间对称面为一虚拟电壁。中间增加枝节结构133结构，不会影响差分信号。图12为本申请实施例中多层电路板13的一种差模电场结构示意图，如图12所示，当差分信号线131传输差模信号时，枝节结构133结构形成的环路与磁力线平行，不会被磁场激励起来。因此，设置了上述枝节结构133，传输差模信号时的磁场和电场也不会与枝节结构133发生耦合，对于电路板组件1传输差模信号没有影响。
图13为本申请实施例中多层电路板的一种共模磁场结构示意图，如图13所示，当差分信号线131传输共模信号时，一组差分信号线131中的两根差分信号线131的电场终止于枝节结构133。图14为本申请实施例中多层电路板的一种共模电场结构示意图，如图14所示，当差分信号线131传输共模信号时，磁场会穿越中间的枝节结构133结构形成环路。电场和磁场均在枝节结构133处谐振，在谐振频率上，差分信号上共模阻抗失配，共模能量会反射回源端耗散，无法继续向前方传播，不会被磁场激励起来。因此，设置了上述枝节结构133，可以抑制电磁干扰。
上述枝节结构133的具体形状不做限制，例如可以为十字形、T形、山字形或者巾字形或者其它对称结构，可以理解，这里枝节结构133的形状只是与各种字或者字母的形状类似，而不是完全一样，本领域技术人员可以参考前述实施例中的设计原则以及图15A- 图15I中的各种示意图来得到最终的形状。
图15A-图15I为本申请实施例中各种枝节结构的形状示意图，如图15A所示实施例中的枝节结构133为十字形；如图15B所示实施例中的枝节结构133为T形；如图15C中的所示实施例中的枝节结构133为山字形；如图15D所示实施例中的枝节结构133为巾字形。此外，上述枝节结构133只需对称设置即可，可以不为上述的形状。例如，如图15E-图15G中所示的实施例中的枝节结构133的形状。此外，上述枝节结构的辅助枝节1332可以与主枝节1331的长度方向平行，或者，上述枝节结构的辅助枝节1332还可以与主枝节1331的长度方向相交，就是说辅助枝节1332可以与主枝节1331垂直，或者呈一定角度。如图15H和图15I所示的实施例中，辅助枝节1332中还包括可斜向延伸的部分。
上述镂空结构1321的外边缘形状也不做限制，例如可以为矩形、圆形、梯形或者D字形等对称结构。值得说明的是，上述镂空结构1321的外边缘指的是镂空结构1321与参考地层132相邻的边缘，也就是忽略掉枝节结构133。图16A-图16C为本申请实施例中参考地层132的镂空结构1321的形状示意图，如图6所示实施例中参考地层132的镂空结构1321为矩形；如图16A所示实施例中参考地层132的镂空结构1321为圆形；如图16B所示实施例中参考地层132的镂空结构1321为梯形；如图16C所示实施例中参考地层132的镂空结构1321为D字形。此外，上述镂空结构1321只需对称设置即可，可以不为上述的形状，本申请对此不做限制。
图17为本申请实施例中多层电路板的另一种俯视结构示意图，如图17所示，一种实施例中，上述电路板组件1的多层电路板13还包括缺陷地结构(DGS)4，该缺陷地结构4也设置于参考地层132。该方案中，缺陷地结构4与枝节结构133均设置于参考地层132，缺陷地结构4与枝节结构133级联，从而可以增加滤波带宽，以提升电路板组件1的抗干扰能力。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (13)

  1. 一种多层电路板，其特征在于，包括差分信号线、参考地层和与所述参考地层连接的枝节结构，其中：
    所述差分信号线在所述多层电路板的层，与所述参考地层在所述多层电路板的层不同；所述枝节结构包括主枝节和辅助枝节，所述枝节结构中只有所述主枝节的一端与所述参考地层连接，所述辅助枝节与所述主枝节连接为一体结构，所述辅助枝节相对于所述主枝节的长度方向轴对称，所述辅助枝节不与所述参考地层连接。
  2. 如权利要求1所述的多层电路板，其特征在于，所述主枝节为矩形主枝节，所述主枝节与所述差分信号线平行设置，所述辅助枝节相对于所述差分信号线轴对称。
  3. 如权利要求1或2所述的多层电路板，其特征在于，所述枝节结构为十字形、T形、山字形或者巾字形。
  4. 如权利要求1～3任一项所述的多层电路板，其特征在于，所述参考地层具有镂空结构，所述镂空结构位于所述枝节结构的周侧，所述镂空结构相对于所述差分信号线对称设置。
  5. 如权利要求4所述的多层电路板，其特征在于，所述镂空结构的外边缘为矩形、圆形、梯形或者D字形。
  6. 如权利要求4或5所述的多层电路板，其特征在于，所述差分信号走线包括初级走线和次级走线，所述初级走线在所述多层电路板的层，与所述次级走线在所述多层电路板的层不同；所述初级走线与所述次级走线通过信号孔连接，所述信号孔穿过所述参考地层的所述镂空结构。
  7. 如权利要求1～6任一项所述的多层电路板，其特征在于，所述枝节结构沿平行于所述差分信号线延伸方向的长度小于或者等于2mm。
  8. 如权利要求1～7任一项所述的多层电路板，其特征在于，所述枝节结构沿垂直于所述差分信号线延伸方向的长度小于或者等于1mm。
  9. 如权利要求1～8任一项所述的多层电路板，其特征在于，还包括缺陷地结构，所述缺陷地结构设置于所述参考地层。
  10. 如权利要求1～9任一项所述的多层电路板，其特征在于，所述枝节结构抑制共模噪声的频率大于或等于10GHz。
  11. 一种电路板组件，其特征在于，包括如权利要求1～10任一项所述的多层电路板，还包括芯片，所述芯片与所述差分信号线连接。
  12. 如权利要求11所述的电路板组件，其特征在于，所述电路板组件为芯片封装、电子模块或者单板。
  13. 一种电子设备，其特征在于，包括壳体和如权利要求1～10任一项所述的多层电路板，所述多层电路板设置于所述壳体。
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