WO2023040152A1 - 存储器件及其形成方法 - Google Patents

存储器件及其形成方法 Download PDF

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Publication number
WO2023040152A1
WO2023040152A1 PCT/CN2022/071629 CN2022071629W WO2023040152A1 WO 2023040152 A1 WO2023040152 A1 WO 2023040152A1 CN 2022071629 W CN2022071629 W CN 2022071629W WO 2023040152 A1 WO2023040152 A1 WO 2023040152A1
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Prior art keywords
trench
layer
groove
forming
opening
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English (en)
French (fr)
Inventor
郭帅
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to EP22868533.5A priority Critical patent/EP4276883B1/en
Priority to US17/844,249 priority patent/US20230084851A1/en
Publication of WO2023040152A1 publication Critical patent/WO2023040152A1/zh
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  • the present application relates to the field of memory, in particular to a memory device and a method for forming the same.
  • Dynamic Random Access Memory is a semiconductor storage device commonly used in computers, consisting of many repeated storage units. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • the transistors in the existing dynamic random access memory generally adopt a trench type transistor structure.
  • the line width of the existing trench-type transistor structure has been shrunk to the limit, and the storage capacity of the DRAM cannot be further improved. Therefore, how to further increase the storage capacity and storage density of the DRAM is an urgent problem to be solved by those skilled in the art.
  • some embodiments of the present application provide a method for forming a storage device, including:
  • a semiconductor substrate is provided, and several active regions are formed in the semiconductor substrate, and a plurality of first trenches extending along a first direction, a second trench and a plurality of trenches extending along a second direction are passed between the several active regions.
  • Several third grooves are separated, the first groove and the second groove communicate with the third groove, the first groove and the second groove are arranged at intervals in the first direction, The depth of the second groove is smaller than the depth of the first groove, and the depth of the area of the third groove outside the connection with the second groove is greater than the depth of the second groove;
  • bit line doped region in the semiconductor substrate at the bottom of the second trench and the bottom of the connection between the second trench and the third trench;
  • the surface of the first isolation layer is lower than the surface of the active region
  • a metal gate surrounding the active region is formed on the surface of the gate dielectric layer on the sidewall of the active region, and the top surface of the metal gate is lower than the top surface of the active region;
  • a source region is formed on the top surface of the active region.
  • the width of the doped bit line region is greater than or equal to the width of the bottom of the second trench.
  • the bit line doped region is formed by a first ion implantation process, and the impurity ions implanted in the first ion implantation process are N-type impurity ions or P-type impurity ions.
  • a protective layer is formed on the sidewalls and bottom surfaces of the first trench, the third trench, and the second trench; after forming the protective layer, the A mask layer is formed on the surface of the semiconductor substrate, and the mask layer has an opening of the semiconductor substrate that exposes the bottom of the second groove and the bottom of the connection between the second groove and the third groove; using the mask The layer is a mask, and the first ion implantation process is performed on the bottom of the second trench and the bottom of the semiconductor substrate where the second trench communicates with the third trench along the opening, and at the bottom of the second trench And a bit line doped region is formed in the semiconductor substrate at the bottom where the second trench communicates with the third trench.
  • the source region is formed by a second ion implantation process.
  • the type of impurity ions doped in the source region is the same as the type of impurity ions doped in the bit line doped region.
  • the forming process of the metal gate includes: forming a metal layer on the surface of the gate dielectric layer and the surface of the first isolation layer; removing the redundant metal layer by maskless etching, and forming a metal layer in the active region A metal gate surrounding the active region is formed on the surface of the gate dielectric layer on the side wall.
  • a second isolation layer covering the metal gate and filling the first trench, the third trench and the second trench is formed;
  • a conductive connection structure extending along the second direction and connecting the plurality of metal gates is formed in the second isolation layer of the trench.
  • the forming process of the metal gate includes: forming a metal layer filling the first trench, the third trench and the second trench on the surface of the gate dielectric layer and the surface of the first isolation layer; Etching back the metal layer so that the top surface of the metal layer is lower than the top surface of the active region; after etching back the metal layer, the metal layer filled in the third trench is cutting, forming a metal gate surrounding the active region on the surface of the gate dielectric layer on the sidewall of the active region.
  • the method further includes: forming a capacitor connected to the source region on the surface of the semiconductor substrate.
  • the process of forming a capacitor connected to the source region on the surface of the semiconductor substrate includes: forming a first dielectric layer on the semiconductor substrate; forming an exposed capacitor in the first dielectric layer A via hole protruding from the surface of the source region; a contact plug is formed in the via hole; a second dielectric layer is formed on the first dielectric layer; a second dielectric layer is formed in the second dielectric layer to expose the contact plug plugged capacitive holes; forming capacitors in the capacitive holes.
  • the active regions are arranged in rows and columns.
  • the forming process of the plurality of active regions includes: forming a plurality of parallel first mask patterns extending along the first direction on the semiconductor substrate, with adjacent first mask patterns having Alternately distributed first openings and second openings, the width of the first openings is greater than the width of the second openings; several parallel second masks extending along the second direction are formed on the first mask pattern There is a sixth opening between adjacent second mask patterns; using the second mask pattern as a mask, the first mask pattern is etched along the sixth opening to form in the first mask pattern a plurality of third openings extending along the second direction, and the remaining first mask patterns form a plurality of discrete etching masks; using the etching mask as a mask, the semiconductor substrate is etched, and the semiconductor substrate A first groove corresponding to the first opening, a second groove corresponding to the second opening, a third groove corresponding to the third opening are formed in the substrate, and the first groove, the second opening and the third There is an active area between the trenches, the first trench and
  • the first mask pattern and the second mask pattern are formed by a self-aligned double patterning process.
  • the forming process of the first mask pattern includes: forming a first hard mask layer on the semiconductor substrate; Several first strip structures arranged in parallel; a first sacrificial spacer layer is formed on the sidewall and top surface of the first strip structures and the surface of the first hard mask layer between the first strip structures; The first filling layer is filled between the first strip structures; the first sacrificial sidewall layer on the side wall surface of the first strip structure is removed, and a fourth strip structure is formed between the first strip structure and the first filling layer.
  • Opening etching the first hard mask layer along the fourth opening to form a first opening in the first hard mask layer; forming a second filling layer filling the first opening; on the second filling layer forming a plurality of second strip structures extending along the first direction and arranged in parallel, each of the second strip structures covers the second filling layer in a first opening and part of the first hard mask on both sides of the first opening mold layer; forming a second sacrificial spacer layer on the sidewall and top surface of the second strip structure and the first hard mask layer and the first filling layer surface between the second strip structure;
  • the third filling layer is filled between the two strip structures; the second sacrificial sidewall layer on the side wall surface of the second strip structure is removed to form a fifth opening between the second strip structure and the second filling layer, so
  • the width of the fifth opening is smaller than the width of the fourth opening; the first hard mask layer between the first openings is etched along the fifth opening, and a second opening is formed in the first hard mask layer , the
  • FIG. 1 A block diagram illustrating an exemplary computing environment in accordance with the present invention.
  • FIG. 1 A block diagram illustrating an exemplary computing environment in accordance with the present invention.
  • a semiconductor substrate in which several active regions are formed, and between the several active regions there are several first trenches extending along the first direction, second trenches and several trenches extending along the second direction.
  • the third groove is separated, the first groove and the second groove communicate with the third groove, the first groove and the second groove are arranged at intervals in the first direction, so The depth of the second groove is smaller than the depth of the first groove, and the depth of the area of the third groove outside the connection with the second groove is greater than the depth of the second groove;
  • bit line doped region in the semiconductor substrate located at the bottom of the second trench and at the bottom of the connection between the second trench and the third trench;
  • a first isolation layer located in the first trench and the third trench, the surface of the first isolation layer is lower than the surface of the active region;
  • a metal gate surrounding the active region on the surface of the gate dielectric layer on the sidewall of the active region, the top surface of the metal gate is lower than the top surface of the active region;
  • a source region located on the top surface of the active region.
  • the width of the doped bit line region is greater than or equal to the width of the bottom of the second trench.
  • the impurity ions doped in the bit line doped region are N-type impurity ions or P-type impurity ions.
  • the type of impurity ions doped in the source region is the same as the type of impurity ions doped in the bit line doped region.
  • the surface of the gate dielectric layer where the metal gate is located on the sidewall of the active region surrounds the active region, and the metal gate does not fill the first trench, the third trench and the second trench.
  • it further includes a second isolation layer covering the metal gate and filling the first trench, the third trench and the second trench; the second isolation layer located in the third trench A conductive connection structure extending along the second direction in the isolation layer and connecting several metal gates.
  • the metal gate fills the first trench, the third trench and the second trench, and the metal gate is lower than the top surface of the active region, and the metal gate The portion of the pole located in the third groove is cut along the second direction.
  • a capacitor connected to the source region on the semiconductor substrate is also included
  • the method for forming a memory device provided in some of the foregoing embodiments of the present application provides a semiconductor substrate, in which a plurality of active regions are formed, and the plurality of active regions are separated by a plurality of first extending along a first direction.
  • a groove, a second groove, and several third grooves extending along the second direction are separated, the first groove and the second groove communicate with the third groove, and the first groove
  • the groove and the second groove are arranged at intervals in the first direction, the depth of the second groove is smaller than the depth of the first groove, and the third groove communicates with the second groove
  • the depth of the region is greater than the depth of the second trench;
  • a bit line doped region is formed in the semiconductor substrate at the bottom of the second trench and at the bottom where the second trench communicates with the third trench;
  • a first isolation layer is formed in the first trench and the third trench, the surface of the first isolation layer is lower than the surface of the active region;
  • a gate dielectric layer; a metal gate surrounding the active region is formed on the surface of the gate dielectric layer on the sidewall of the active region, and the top surface of the metal gate is lower than the top surface of the active region;
  • a top surface of the active region forms a source region.
  • a plurality of vertical transistors are formed by the aforementioned method, and each vertical transistor includes a corresponding active region, a gate dielectric layer located on the sidewall surface of the active region, and a bit line doped layer located in the semiconductor substrate at the bottom of the second trench.
  • the vertical transistor since the source region and the drain region are located on the upper and lower sides of the active region, the channel region formed is located on the sidewall of the active region, so that the area of the semiconductor substrate occupied by the vertical transistor will be smaller, so that the unit area
  • the number of vertical transistors formed on it can be increased, and correspondingly, the number of capacitors connected to the source region of each transistor can also be formed on the subsequent unit area, thereby improving the storage capacity and storage density of the memory, and this specific structure.
  • the vertical transistor can reduce the body effect, reduce the leakage current generated by the subsequently formed capacitor into the substrate, and improve the electrical performance of the storage device.
  • FIG. 1 are schematic structural diagrams of the formation process of a storage device according to some embodiments of the present application.
  • a trench transistor generally includes at least one buried word line in the semiconductor substrate and a drain region and at least one source region in the semiconductor substrate on both sides of the buried word line. Such trench transistors occupy a relatively large area of the semiconductor substrate, which is not conducive to the improvement of the integration level of the DRAM, so that the storage capacity and storage density of the DRAM are limited.
  • the present application provides a novel storage device and a method for forming the same, which can further increase the storage capacity and storage density of the storage device.
  • FIG. 19 is a schematic cross-sectional structure diagram of FIG. 21 along the cutting line AB
  • FIG. 20 is a schematic cross-sectional structure diagram of FIG. 21 along the cutting line CD direction
  • the semiconductor substrate 201 on which the semiconductor substrate Several active regions 220 are formed in 201, and several first trenches 217 extending along the first direction, second trenches 218 and several third trenches 219 extending along the second direction are passed between the several active regions 220 Separated, the first groove 217 and the second groove 218 communicate with the third groove 219, the first groove 217 and the second groove 218 are arranged at intervals in the first direction, The depth of the second groove 218 is smaller than the depth of the first groove 217, and the depth of the third groove 219 outside the connection with the second groove 218 is greater than that of the second groove 218 depth.
  • the material of the semiconductor substrate 201 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); Or it can also be other materials, such as III-V group compounds such as gallium arsenide.
  • the material of the semiconductor substrate 201 in this embodiment is silicon.
  • the semiconductor substrate 201 needs to be doped with certain impurity ions according to the type of the subsequently formed vertical transistor.
  • the semiconductor substrate can be doped with a well region, and the impurity ions can be N-type impurity ions or P-type impurity ions.
  • Impurity ions are one or more of boron ions, gallium ions or indium ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions or antimony ions.
  • the active region 220 is subsequently used to form a channel region, a source region and a drain region of a vertical transistor, and several active regions 220 are separated.
  • the formed active regions 220 are arranged in rows and columns (refer to FIG. 21 ). In other embodiments, the active regions may also be arranged in other ways.
  • first direction and the second direction are perpendicular to each other, and the angle between them is 90 degrees. In other embodiments, the first direction and the second direction may not be perpendicular, for example, the angle between the first direction and the second direction may be an acute angle.
  • the plurality of second trenches 218 and the first trenches 217 extend along the first direction and are alternately distributed in the semiconductor substrate 201, and the plurality of third trenches 219 extend along the second direction,
  • the third groove 219 communicates with the first groove 217 and the second groove 218 at the intersection, the depth of the second groove 218 is smaller than the depth of the first groove 217, the third groove 219 and the second
  • the depths of the grooves 218 at the connection points are the same or have a small difference, and the depth of the third groove 219 outside the connection point with the second groove 218 is greater than the depth of the second groove 218 .
  • the width of the first trench 217 may be greater than the width of the second trench 218 .
  • the semiconductor substrate 201 may be etched first to form several first trenches 217 and second trenches 218 extending along the first direction and distributed at intervals, and the depth of the formed first trenches 217 is greater than that of the second trenches.
  • the third trenches 219 are in communication with the second trenches 218
  • the depth at the place is the same or the difference is small, and the depth of the third groove 219 outside the communication with the second groove 218 is greater than the depth of the second groove 218 (when forming the third groove
  • a mask layer is first formed on the semiconductor substrate 201, the positions where the second groove 218 and the first groove 217 have been formed can be covered by the mask layer without being etched, and the mask layer will only expose The surface of the semiconductor substrate that needs to be etched between the first trench and the second trench).
  • the semiconductor substrate 201 may be etched first to form a plurality of first trenches 217, and then the semiconductor substrate is etched to form a plurality of second trenches 218.
  • the depth of the second trenches 218 is smaller than that of the first trenches 217. depth, and finally etch the semiconductor substrate 201 to form a number of third trenches 219, thereby forming a number of discrete active regions 220, and the depths of the third trenches 219 and the second trenches 218 are the same or different from each other. small, and the depth of the third groove 219 outside the connection with the second groove 218 is greater than the depth of the second groove 218 .
  • the first trench 217 , the second trench 218 and the third trench 219 may also be formed by etching the semiconductor substrate 201 at the same time.
  • the active regions 220 are formed by a self-aligned double pattern mask process, and the formation process of the active regions 220 will be described in detail below with reference to FIGS. 1-21 .
  • a first hard mask layer 202 is formed on the semiconductor substrate 201 ; and a first material layer 203 is formed on the first hard mask layer 202 .
  • the first hard mask layer 202 is subsequently used to form a first mask pattern.
  • the first hard mask layer 202 can be a single-layer or multi-layer stack structure, and the material of the first hard mask layer 202 can be polysilicon, amorphous silicon, amorphous carbon, nitride One or more of silicon, silicon oxynitride, silicon oxide, silicon carbide nitrogen, silicon oxycarbide, silicon carbide, and silicon germanium.
  • the formation process of the first hard mask layer 202 can be normal pressure or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), physical vapor deposition (PVD) , atomic layer deposition (ALD), sputtering, sputtering, electroplating, spin coating, other suitable methods and/or combinations thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • Thermal CVD thermal chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • sputtering sputtering
  • electroplating spin coating
  • spin coating other suitable methods and/or combinations thereof.
  • the material of the first hard mask layer 202 is polysilicon.
  • a first etch stop layer (not shown in the figure) may also be formed between the first hard mask layer 202 and the semiconductor substrate 201, and the first etch stop layer is used for The underlying material layer is protected from over-etching when patterning the first hard mask layer.
  • the material of the first etch stop layer is different from the material of the first hard mask layer, and the material of the first etch stop layer is silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitride, One or several kinds of silicon carbide.
  • the material of the first etching stop layer is silicon oxide.
  • the first material layer 203 is subsequently used to form a first strip structure.
  • the first material layer 203 can be a single-layer or multi-layer stacked structure, and the material of the first material layer 203 can be polysilicon, amorphous silicon, amorphous carbon, silicon nitride, oxynitride One or more of silicon, silicon oxide, silicon carbide nitrogen, silicon oxycarbide, silicon carbide, and silicon germanium.
  • the material of the first material layer 203 is amorphous carbon.
  • a second etch stop layer may also be formed between the first material layer 203 and the first hard mask layer 202, and the second etch stop layer It is used to protect the underlying material layer from being over-etched when the first material layer 203 is patterned.
  • the material of the second etching stop layer is different from that of the first material layer 203 .
  • the material of the second etching stop layer is one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitride, and silicon oxycarbide. In this embodiment, the material of the second etching stop layer is silicon oxynitride.
  • FIG. 2 is a schematic cross-sectional structural diagram of FIG. 3 along the cutting line AB, patterning the first material layer 203 (refer to FIG. 1), forming a Several first strip structures 204 extending in the first direction and arranged in parallel.
  • the first strip structures 204 are elongated, the plurality of first strip structures 204 are separated and parallel to each other, and there are openings 205 between adjacent first strip structures 204 .
  • the patterning of the first material layer 203 adopts an anisotropic dry etching process, specifically an anisotropic plasma etching process.
  • a patterned photoresist layer (not shown in the figure) may also be formed on the first material layer 203, so that the patterned The photoresist layer is used as a mask, and the first material layer 203 is etched to form a first strip structure 204; the patterned photoresist layer is removed.
  • a first sacrificial spacer layer 206 is formed on the sidewall and top surface of the first strip structure 204 and the surface of the first hard mask layer 202 between the first strip structure 204 .
  • the material of the first sacrificial sidewall layer 206 is different from the material of the first strip structure 204, and the material of the first sacrificial sidewall layer 206 can be polysilicon, amorphous silicon, amorphous carbon, silicon nitride , One or more of silicon oxynitride, silicon oxide, silicon carbide nitrogen, silicon oxycarbide, silicon carbide, and silicon germanium.
  • Forming the first sacrificial sidewall layer 206 adopts a deposition process, and the deposition process includes an atomic layer deposition process.
  • a first filling layer 207 is filled between the first strip structures 204 .
  • the first filling layer 207 is located on the surface of the first sacrificial sidewall layer 206 between the first strip structures 204 and fills the openings between the first strip structures 204 .
  • the first sacrificial sidewall layer 206 on the sidewall surface of the first strip structure 204 is removed to form a fourth opening between the first strip structure 204 and the first filling layer 207 .
  • the material of the first filling layer 207 is different from that of the first sacrificial spacer layer 206 .
  • the material of the first filling layer 207 can be polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitrogen, silicon oxycarbide, silicon carbide, germanium One or more of silicon oxide and organic materials.
  • the formation process of the first filling layer 207 can be normal pressure or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, sputtering, electroplating, spin coating, other suitable methods and/or combinations thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • Thermal CVD thermal chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • sputtering sputtering
  • electroplating spin coating
  • the surface of the formed first filling layer 207 may be flush with the first sacrificial sidewall layer 206 on the top surface of the first strip structure 204 .
  • the first filling layer on the surface of the first sacrificial sidewall layer 206 on the top surface of 204 uses the remaining first filling material layer in the opening as the first filling layer 207 .
  • the surface of the formed first filling layer may be flush with the top surface of the first strip structure 204 .
  • the first sacrificial sidewall layer 206 and the first filling material layer on the top surface of 204 expose the top surface of the first strip structure 204, and use the remaining first filling material layer in the opening as the first filling layer, thus forming The top surface of the first filling layer is flush with the top surface of the first strip structure.
  • the filling layer and the first hard mask layer can be reduced.
  • the etching load effect caused by the different heights of the strip structures improves the accuracy of the position and size of the formed first mask pattern and maintains a better sidewall shape, so that the block formed after disconnecting the first mask pattern
  • the accuracy of the position and size of the block-shaped mask pattern is high and the shape of the side wall is maintained, which ultimately makes the position and size of the active region formed by etching the semiconductor substrate with the block mask pattern as a mask. And maintain good sidewall morphology.
  • the first sacrificial sidewall layer on the sidewall surface of the first strip structure 204 is removed to form a fourth opening 208 between the first strip structure 204 and the first filling layer 207 .
  • an anisotropic dry etching process including an anisotropic plasma etching process, is used to remove the first sacrificial sidewall layer on the sidewall surface of the first strip structure 204 .
  • the first sacrificial sidewall layer on the sidewall surface of the first strip structure 204 when the first sacrificial sidewall layer on the sidewall surface of the first strip structure 204 is removed, the first sacrificial sidewall layer on the top surface of the first strip structure 204 will also be removed.
  • FIG. 7 is a schematic cross-sectional structure diagram of FIG. 9 along the cutting line AB
  • FIG. 8 is a schematic cross-sectional structure diagram of FIG. 9 along the cutting line CD direction
  • the first hard mask is etched along the fourth opening. layer 202 , forming a plurality of first openings 210 extending along a first direction in the first hard mask layer 202 .
  • an anisotropic dry etching process including an anisotropic plasma etching process, is used to etch the first hard mask layer 202 .
  • the first opening 210 described in the present application is formed through the aforementioned self-aligned double patterning process, and subsequently when forming the active region, the width of the first trench corresponding to the first opening between the active regions can be smaller, Therefore, the area of the active region can be larger.
  • FIG. 10 is carried out on the basis of FIG. 7 to form a second filling layer that fills the first opening; on the second filling layer, several second strip structures 211 extending along the first direction and arranged in parallel are formed. , each of the second strip structures 211 covers the second filling layer in one first opening and part of the first hard mask layer 202 on both sides of the first opening, and two adjacent second strip structures 211 An opening is exposed between the filled second filler layers.
  • the second filling layer and the second strip structure 211 are formed in the same process, the specific process includes: forming a second material layer on the surface of the first hard mask layer 202, the first The second material layer fills the first opening; part of the second material layer is removed by etching to form a plurality of second strip structures 211 and a second filling layer filling the first opening.
  • the material of the second filling layer and the second strip structure 211 is different from that of the first hard mask layer 202 .
  • the material of the second filling layer and the second strip structure 211 can be polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitride, carbon One or more of silicon oxide, silicon carbide, silicon germanium, and organic materials.
  • a second sacrificial spacer layer 212 is formed on the sidewall and top surface of the second strip structure 211 and the first hard mask layer 202 and the surface of the first filling layer between the second strip structure 211 .
  • the material of the second sacrificial sidewall layer 212 is different from that of the second strip structure 211.
  • the material of the second sacrificial sidewall layer 212 can be polysilicon, amorphous silicon, or One or more of stereotyped carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitrogen, silicon oxycarbide, silicon carbide, and silicon germanium.
  • Forming the second sacrificial sidewall layer 212 adopts a deposition process, and the deposition process includes an atomic layer deposition process.
  • a third filling layer 213 is filled between the second strip structures 211 .
  • the third filling layer 213 is located on the second sacrificial sidewall layer 212 between the second strip structures 211 and fills the space between the second strip structures 211 .
  • the second sacrificial sidewall layer on the sidewall surface of the second strip structure 204 is removed to form a fifth opening between the second strip structure 211 and the third filling layer 213 .
  • the material of the third filling layer 213 is different from that of the second sacrificial sidewall layer 212 .
  • the material of the third filling layer 213 can be polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitrogen, silicon oxycarbide, silicon carbide, germanium One or more of silicon oxide and organic materials.
  • the formation process of the third filling layer 213 can be normal pressure or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, sputtering, electroplating, spin coating, other suitable methods and/or combinations thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • Thermal CVD thermal chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • sputtering sputtering
  • electroplating spin coating
  • Fig. 13 is a schematic diagram of the cross-sectional structure of Fig. 15 along the direction of cutting line AB
  • Fig. 14 is a schematic diagram of the cross-sectional structure of Fig. 15 along the direction of cutting line CD, removing the surface of the second strip structure 211
  • the second sacrificial sidewall layer 212 (refer to FIG.
  • an anisotropic dry etching process including an anisotropic plasma etching process, is used to etch the first hard mask layer 202 .
  • the plurality of first mask patterns 209 formed are discrete, specifically, the formed first mask patterns 209 extend along the first direction and are parallel to each other, and the adjacent first mask patterns 209 are alternately distributed.
  • the width of the formed second opening 214 is smaller than the width of the first opening 210, and subsequently when the semiconductor substrate 201 is etched in the same etching process, the etching rate of the semiconductor substrate at the bottom of the second opening 214 is Greater than the etching rate of the semiconductor substrate at the bottom of the first opening, so that the depth of the second groove correspondingly formed in the semiconductor substrate 201 is smaller than the depth of the first groove, so that the first groove and the second groove are formed While the size of the groove is small, the forming process of the first groove and the second groove can be simplified.
  • the aforementioned first mask pattern 209 is formed by the aforementioned self-aligned double patterning process, and subsequently when forming the active region, the width of the first trench and the second trench between the active regions can be relatively small. Small, so that the area of the active region can be larger.
  • first mask patterns 209 extending along the first direction are formed on the semiconductor substrate 201, and there are alternately distributed first openings 210 and second openings 214 between adjacent first mask patterns 209, so After the width of the first opening 210 is greater than the width of the second opening 214, it also includes: forming a plurality of parallel second mask patterns extending along the second direction on the first mask pattern 209, adjacent to the first mask pattern 209 There is a sixth opening between the two mask patterns, and the second mask pattern is also formed by a self-aligned double patterning process; using the second mask pattern as a mask, the first mask pattern is etched along the sixth opening.
  • Fig. 16-18 is a schematic cross-sectional structure along the cutting line AB
  • FIG. 17 is a schematic cross-sectional structure along the cutting line CD in FIG. 18).
  • the semiconductor substrate 201 is etched to form a first trench 217 corresponding to the first opening and a second trench 217 in the semiconductor substrate 201.
  • the second groove 218 corresponding to the opening, the third groove 219 corresponding to the third opening, the active region 220 is between the first groove 217, the second opening 218 and the third groove 219, the first A groove 217 and a second groove 218 communicate with the third groove 219, the depth of the second groove 218 is less than the depth of the first groove 217, and the third groove 219 is connected with the The depth of the area outside the connection of the second groove 218 is greater than the depth of the second groove 218 .
  • Etching the semiconductor substrate 201 uses an anisotropic dry etching process, including an anisotropic plasma etching process.
  • the etching mask can be removed synchronously during the process of etching the semiconductor substrate, or can be removed by an additional etching process after the active region is formed.
  • Fig. 22 is carried out on the basis of Fig. 19, and Fig. 23 is carried out on the basis of Fig. 20, in the sidewalls of the first groove 217, the third groove 219 and the second groove 218 and the bottom surface to form a protective layer 221 .
  • the protection layer 221 protects the sidewall surface of the active region 220 during subsequent ion implantation.
  • the material of the protection layer 221 may be silicon oxide.
  • the protective layer 221 is formed through an oxidation process, specifically furnace tube oxidation.
  • a mask layer 222 is formed on the surface of the semiconductor substrate 201, the mask layer 222 has exposed the bottom of the second trench 218 and the second trench 218 communicates with the opening of the semiconductor substrate 201 at the bottom of the third trench 219 .
  • the mask layer 222 can be a single layer or a multi-layer stack structure (such as a double-layer stack structure).
  • the mask layer 222 may include a hard mask material layer and a photoresist layer on the surface of the hard mask material layer.
  • the material of the hard mask material layer may be one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitride, and silicon oxycarbide.
  • the semiconductor substrate 201 at the bottom of the second trench 218 and the bottom of the connection between the second trench 218 and the third trench 219 along the opening is The first ion implantation process is performed to form a bit line doped region 223 in the semiconductor substrate 201 at the bottom of the second trench 218 and the bottom of the connection between the second trench 218 and the third trench 219 .
  • the bit line doped region 223 is formed by first ion implantation, and the type of impurity ions implanted in the bit line doped region 223 is different from the type of impurity ions implanted in the well region of the active region 220, for example, when the active region When P-type impurity ions are implanted in the well region 220, N-type impurity ions are implanted in the bit line doped region 217; when N-type impurity ions are implanted in the well region in the active region 220, the bit line P-type impurity ions are implanted into the line doping region 217 .
  • the impurity ions implanted in the bit line doped region 217 are N-type impurity ions or P-type impurity ions, the P-type impurity ions are one or more of boron ions, gallium ions or indium ions, and the N-type impurity ions are The impurity ions are one or more of phosphorus ions, arsenic ions or antimony ions.
  • an annealing process is required to activate the dopant ions.
  • the width of the formed bit line doped region 223 is greater than or equal to the width of the bottom of the second trench 218, and the bottom of the bit line doped region 223 is flush with the bottom of the first trench 217. Or higher than the bottom of the first trench 217 (the bottom of the bit line doped region 223 is closer to the surface of the active region 220 than the bottom of the first trench 217 ).
  • the portion of the bit line doped region 223 in contact with the active region 220 serves as the drain region of the vertical transistor, and there are two active regions 220 between the adjacent first openings 218, and the two active regions 220 are formed
  • the vertical transistors share one drain region to improve the integration of the device, and each bit line doped region 223 electrically connects the drain regions of every two adjacent rows of vertical transistors along the first direction to improve the control of the vertical transistors ability, and then improve the operation ability (read, write and delete) of the memory formed subsequently.
  • the passivation layer 221 and the mask layer 222 are removed.
  • a wet etching process is used to remove the protection layer 221 and the mask layer 222 .
  • a first isolation layer 224 is formed in the first trench 217 and the third trench 219 , the surface of the first isolation layer 224 is lower than the surface of the active region 220 .
  • the first isolation layer 224 is used for electrical isolation between adjacent active regions and adjacent bit line doped regions 223 .
  • the material of the first isolation layer 224 is silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicon glass (FSG), low dielectric constant (K is less than 2.8) material, other suitable materials and/or combinations of the above.
  • the forming process of the first isolation layer 224 includes: forming a first isolation layer on the surface of the active region 220 and in the first trench 217, the second trench 218, and the third trench 219 through a deposition process. material layer; etch back to remove part of the first isolation material layer, and form a first isolation layer 224 in the first trench 217 and the third trench 219 .
  • a gate dielectric layer 225 surrounding the active region 220 is formed on the surface of the active region 220;
  • the metal gate 226 of the active region 220 , the top surface of the metal gate 226 is lower than the top surface of the active region 220 .
  • the material of the gate dielectric layer 225 can be silicon oxide or a high-K (dielectric constant) dielectric material, and the high-K dielectric material is HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 , Al 2 O 3 , SrTiO 3 or one or more of BaSrTiO.
  • the gate dielectric layer 225 can be formed by oxidation or deposition process.
  • the gate dielectric layer 225 may be formed after the protection layer 236 is removed. In another embodiment, the protection layer 236 may not be removed, and a gate dielectric layer is directly formed on the protection layer 236 .
  • the gate dielectric layer 225 when the gate dielectric layer 225 is formed, the gate dielectric layer 225 may also be formed on the bottom surfaces of the first trench, the second trench and the third trench and the top surface of the active region. .
  • the formed metal gate 226 surrounds the sidewall of each active region, and the top surface of the metal gate 226 is lower than the top surface of the active region 220, which can improve the metal gate 220 to the side of the active region.
  • the ability to control the formation of channels in the walls improves the performance of forming vertical transistors.
  • the material of the metal gate 226 can be one of W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN, Wsi or Several kinds.
  • the forming process of the metal gate 226 includes: forming a metal layer on the surface of the gate dielectric layer and the surface of the first isolation layer; A metal gate 226 surrounding the active region is formed on the surface of the gate dielectric layer on the sidewall of the region.
  • a conductive connection structure can be formed to electrically connect multiple metal gates in each row in the second direction, and the metal gates in adjacent rows are still disconnected, so as to improve the control ability of the vertical transistor, thereby improving the control of the subsequent The operational capabilities (read, write and delete) of the formed memory.
  • the forming process of the metal gate includes: forming a metal layer filling the first trench, the third trench and the second trench on the surface of the gate dielectric layer and the surface of the first isolation layer ; etch back the metal layer so that the top surface of the metal layer is lower than the top surface of the active region; after etching the metal layer back, the metal filled in the third trench is moved along the second direction The layer is cut off, and a metal gate surrounding the active region is formed on the surface of the gate dielectric layer on the sidewall of the active region. For the metal gates formed in this way, multiple metal gates in each row in the second direction are connected together, and metal gates in adjacent rows in the second direction are disconnected.
  • an active region 227 is formed on the top surface of the active region 220 .
  • the type of impurity ions doped in the source region 227 is the same as the type of impurity ions doped in the bit line doped region 223 , and different from the type of impurity ions doped in the well region of the active region.
  • the source region 227 is formed by a second ion implantation process.
  • the implanted (doped) impurity ions in the source region 227 are N-type impurity ions or P-type impurity ions, and the P-type impurity ions are one or more of boron ions, gallium ions, or indium ions.
  • N-type impurity ions are one or more of phosphorus ions, arsenic ions or antimony ions.
  • a gate covering the metal gates 226 and filling the first trenches, the third trenches and the second trenches.
  • the metal gates in each row in the second direction when the plurality of metal gates in each row in the second direction are connected together, and the metal gates in adjacent rows in the second direction are disconnected, directly form the metal gates that fill all the gates.
  • the first trench, the third trench and the second isolation layer of the second trench do not need to form additional conductive connection structures.
  • each vertical transistor includes a corresponding active region 220, a gate dielectric layer 225 located on the sidewall surface of the active region 220, and a semiconductor substrate located at the bottom of the second trench
  • the bit line doped region 223, the source region 227 located on the top surface of the active region 220, and the surface of the gate dielectric layer located on the sidewalls of the first trench, the second trench and the third trench surround the active region 220
  • the metal gate 226, the vertical transistor of the aforementioned specific structure since the source region and the drain region are located on the upper and lower sides of the active region, the channel region formed is located on the sidewall of the active region, so that the semiconductor substrate occupied by the vertical transistor
  • the area will be smaller, so that the number of vertical transistors formed per unit area can be increased, and correspondingly, the number of capacitors connected to the source region of each transistor formed on the subsequent unit area can also be increased, thereby improving the storage capacity of the memory and The storage density, and the vertical transistor with
  • the source region 227 after forming the source region 227 , it further includes forming a capacitor connected to the source region 227 on the surface of the semiconductor substrate 201 .
  • the process of forming a capacitor connected to the source region on the surface of the semiconductor substrate includes: forming a first dielectric layer on the semiconductor substrate; forming an exposed capacitor in the first dielectric layer A via hole protruding from the surface of the source region; a contact plug is formed in the via hole; a second dielectric layer is formed on the first dielectric layer; a second dielectric layer is formed in the second dielectric layer to expose the contact plug plugged capacitive holes; forming capacitors in the capacitive holes.
  • the process of forming a capacitor connected to the source region 223 on the surface of the semiconductor substrate 201 includes: referring to FIG. 38 and FIG. 39 , forming a first dielectric layer 230 on the second isolation layer 228; A through hole 231 exposing the surface of the source region 227 is formed in the first dielectric layer 230 and the second isolation layer 228 .
  • the opening of the formed through hole 231 may be widened to both sides, so as to facilitate the subsequent formation of the contact plug, and increase the contact area between the top surface of the formed contact plug and the subsequently formed capacitor.
  • contact plugs 232 are formed in the through holes, and the material of the contact plugs 232 is metal.
  • a third dielectric layer 233 is formed on the second dielectric layer 230; a capacitor hole exposing the contact plug 232 is formed in the third dielectric layer 233; A capacitor 234 is formed in the middle.
  • the capacitor 234 includes a lower electrode layer, a dielectric layer on the lower electrode layer, and an upper electrode layer on the dielectric layer.
  • the material of the dielectric layer may be a high-K dielectric material to increase the capacitance value of the capacitor per unit area
  • the high-K dielectric material includes HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 , Al 2 O 3 , SrTiO 3 or BaSrTiO, or a stack of two or more of the above materials in the group.
  • the material of the upper electrode layer and the lower electrode layer can be one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, and P-type polysilicon, or a group of the above materials
  • the stack formed by two or more of the group can also include metal nitride and metal silicide or a compound formed by two, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), Nickel silicide (Titanium Silicide), silicon nitride (TiSixNy) and so on.
  • the capacitor can also be formed by using an existing double-sided capacitor forming process.
  • Some embodiments of the present invention also provide a storage device, referring to Figure 42 and Figure 43 and referring to Figure 19- Figure 21 in combination, including:
  • a semiconductor substrate 201, a plurality of active regions 220 are formed in the semiconductor substrate 201, and a plurality of first trenches 217, second trenches 218 extending along a first direction and Several third grooves 219 extending in the second direction are separated, the first groove 217 and the second groove 218 communicate with the third groove 219, and the first groove 217 communicates with the first groove 219.
  • Two grooves 218 are arranged at intervals in the first direction, the depth of the second groove 218 is smaller than the depth of the first groove 217, and the third groove 219 is connected with the second groove 218 the depth of the region is greater than the depth of the second trench 218;
  • bit line doped region 223 in the semiconductor substrate 201 located at the bottom of the second trench 218 and the bottom of the connection between the second trench 218 and the third trench 219;
  • a first isolation layer 224 located in the first trench 217 and the third trench 219, the surface of the first isolation layer 224 is lower than the surface of the active region 220;
  • the source region 227 is located on the top surface of the active region 220 .
  • the width of the doped bit line region 223 is greater than or equal to the width of the bottom of the second trench 218 .
  • the impurity ions doped in the bit line doped region 223 are N-type impurity ions or P-type impurity ions.
  • the source region 227 is doped with the same type of impurity ions as the bit line doped region 223 is doped with the same type of impurity ions.
  • the surface of the gate dielectric layer on the sidewall of the active region where the metal gate 226 surrounds the active region, the metal gate 226 does not fill the first trench, the third trench and second trench.
  • it also includes a second isolation layer 228 covering the metal gate 226 and filling the first trench, the third trench and the second trench; located in the third trench
  • the conductive connection structure 229 in the second isolation layer 228 extends along the second direction and connects several metal gates (refer to FIG. 43 ).
  • the metal gate fills the first trench, the third trench and the second trench, and the metal gate is lower than the top surface of the active region, and the metal gate A portion of the gate located in the third trench is cut along the second direction.
  • a capacitor 234 connected to the source region 227 on the semiconductor substrate 201 is further included.

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
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  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)

Abstract

一种存储器件及其形成方法，所述存储器件，包括：半导体衬底，半导体衬底中形成有若干有源区，所述若干有源区之间通过沿第一方向延伸的若干第一沟槽、第二沟槽以及沿第二方向延伸的若干第三沟槽分隔开；位于所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底中的位线掺杂区；位于所述第一沟槽和第三沟槽中的第一隔离层，所述第一隔离层的表面低于所述有源区的表面；位于所述有源区的表面的环绕所述有源区的栅介质层；位于所述有源区侧壁上的栅介质层表面的环绕所述有源区的金属栅极，所述金属栅极的顶部表面低于所述有源区的顶部表面；位于所述有源区的顶部表面的源区。本发明的存储器件的存储密度得到提升。

Description

存储器件及其形成方法
相关申请引用说明
本申请要求于2021年09月15日递交的中国专利申请号202111079099.5，申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及存储器领域，尤其涉及一种存储器件及其形成方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏区与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
为了提高存储结构的集成度，现有动态随机存取存储器(DRAM)中的晶体管通常采用沟槽型的晶体管结构。但是现有的沟槽型的晶体管结构线宽已经微缩到极限，不能进一步提升DRAM的存储容量，因而怎样进一步提升DRAM的存储容量和存储密度是本领域技术人员亟待解决的问题。
发明内容
鉴于此，本申请一些实施例提供了一种存储器件的形成方法，包括：
提供半导体衬底，在所述半导体衬底中形成若干有源区，所述若干有源区之间通过沿第一方向延伸的若干第一沟槽、第二沟槽以及沿第二方向延伸的若干第三沟槽分隔开，所述第一沟槽和第二沟槽与所述的第三沟槽连通，所述第一沟槽与所述第二沟槽在第一方向间隔排列，所述第二沟槽的深度小于第一沟槽的深度，且所述第三沟槽的与所述第二沟槽连通处之外区域的深度大于所述第二沟槽的深度；
在所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底中形成位线掺杂区；
在所述第一沟槽和第三沟槽中形成第一隔离层，所述第一隔离层的表面低于所述有源区的表面；
在所述有源区的表面形成环绕所述有源区的栅介质层；
在所述有源区侧壁上的栅介质层表面形成环绕所述有源区的金属栅极，所述金属栅极的顶部表面低于所述有源区的顶部表面；
在所述有源区的顶部表面形成源区。
在一些实施例中，所述位线掺杂区的宽度大于或等于第二沟槽底部的宽度。
在一些实施例中，所述位线掺杂区通过第一离子注入工艺形成，所述第一离子注入工艺注入的杂质离子为N型杂质离子或P型杂质离子。
在一些实施例中，在进行第一离子注入工艺之前，在所述第一沟槽、第三沟槽和第二沟槽的侧壁和底部表面形成保护层；形成保护层后，在所述半导体衬底表面上形成掩膜层，所述掩膜层中具有暴露出第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底的开口；以所述掩膜层为掩膜，沿开口对所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底的进行第一离子注入工艺，在所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底中形成位线掺杂区。
在一些实施例中，所述源区通过第二离子注入工艺形成。
在一些实施例中，所述源区掺杂的杂质离子类型与所述位线掺杂区掺杂的杂质离子类型相同。
在一些实施例中，所述金属栅极的形成过程包括：在所述栅介质层表面以及第一隔离层表面形成金属层；无掩膜刻蚀去除多余的金属层，在所述有源区侧壁的栅介质层表面形 成环绕所述有源区的金属栅极。
在一些实施例中，在形成金属栅极后，形成覆盖所述金属栅极并填充满所述第一沟槽、第三沟槽和第二沟槽的第二隔离层；在所述第三沟槽的第二隔离层中形成沿第二方向延伸并将若干金属栅极连接的导电连接结构。
在一些实施例中，所述金属栅极的形成过程包括：在所述栅介质层表面以及第一隔离层表面形成填充满第一沟槽、第三沟槽和第二沟槽的金属层；回刻蚀所述金属层，使得金属层的顶部表面低于所述有源区的顶部表面；回刻蚀所述金属层后，沿第二方向将所述第三沟槽中填充的金属层切断，在所述有源区侧壁的栅介质层表面形成环绕所述有源区的金属栅极。
在一些实施例中，还包括：在所述半导体衬底表面上形成与所述源区连接的电容器。
在一些实施例中，在所述半导体衬底表面上形成与所述源区连接的电容器的过程包括：在所述半导体衬底上形成第一介质层；在所述第一介质层中形成暴露出所述源区表面的通孔；在所述通孔中形成接触插塞；在所述第一介质层上形成第二介质层；在所述第二介质层中形成暴露出所述接触插塞的电容孔；在所述电容孔中形成电容器。
在一些实施例中，所述若干有源区呈行列排布。
在一些实施例中，所述若干有源区的形成过程包括：在所述半导体衬底上形成沿第一方向延伸的若干平行的第一掩膜图形，相邻第一掩膜图形之间具有交替分布的第一开口和第二开口，所述第一开口的宽度大于所述第二开口的宽度；在所述第一掩膜图形上形成沿第二方向延伸的若干平行的第二掩膜图形，相邻第二掩膜图形之间具有第六开口；以所述第二掩膜图形为掩膜，沿第六开口刻蚀所述第一掩膜图形，在第一掩膜图形中形成沿第二方向延伸的若干第三开口，剩余的第一掩膜图形形成若干分立的刻蚀掩膜；以所述刻蚀掩膜为掩膜，刻蚀所述半导体衬底，在所述半导体衬底中形成与第一开口对应的第一沟槽、与第二开口对应的第二沟槽，与第三开口对应的第三沟槽，所述第一沟槽、第二开口和第三沟槽之间为有源区，所述第一沟槽和第二沟槽与所述第三沟槽连通，所述第二沟槽的深度小于第一沟槽的深度，且所述第三沟槽的与所述第二沟槽连通处之外区域的深度大于所述第二沟槽的深度。
在一些实施例中，所述第一掩膜图形和第二掩膜图形通过自对准双重图形工艺形成。
在一些实施例中，所述第一掩膜图形的形成过程包括：在所述半导体衬底上形成第一硬掩膜层；在所述第一硬掩膜层上形成沿第一方向延伸且平行排布的若干第一条状结构；在所述第一条状结构的侧壁和顶部表面以及第一条状结构之间的第一硬掩膜层表面形成第一牺牲侧墙层；在所述第一条状结构之间填充第一填充层；去除所述第一条状结构侧壁表面的第一牺牲侧墙层，在第一条状结构和第一填充层之间形成第四开口；沿第四开口刻蚀所述第一硬掩膜层，在所述第一硬掩膜层中形成第一开口；形成填充满第一开口的第二填充层；在第二填充层上形成沿第一方向延伸且平行排布的若干第二条状结构，每一个所述第二条状结构覆盖一个第一开口中的第二填充层以及第一开口两侧的部分第一硬掩模层；在所述第二条状结构的侧壁和顶部表面以及第二条状结构之间的第一硬掩膜层和第一填充层表面形成第二牺牲侧墙层；在所述第二条状结构之间填充第三填充层；去除所述第二条状结构侧壁表面的第二牺牲侧墙层，在第二条状结构和第二填充层之间形成第五开口，所述第五开口的宽度小于所述第四开口的宽度；沿第五开口刻蚀所述第一开口之间的第一硬掩膜层，在所述第一硬掩膜层中形成第二开口，所述第二开口的宽度小于所述第一开口的宽度，所述第二开口和所述第一开口之间剩余的第一硬掩膜层即为第一掩膜图形。
本发明另一些实施例还提供了一种存储器件，包括：
半导体衬底，所述半导体衬底中形成有若干有源区，所述若干有源区之间通过沿第一方向延伸的若干第一沟槽、第二沟槽以及沿第二方向延伸的若干第三沟槽分隔开，所述第一沟槽和第二沟槽与所述的第三沟槽连通，所述第一沟槽与所述第二沟槽在第一方向间隔排列，所述第二沟槽的深度小于第一沟槽的深度，且所述第三沟槽的与所述第二沟槽连通 处之外区域的深度大于所述第二沟槽的深度；
位于所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底中的位线掺杂区；
位于所述第一沟槽和第三沟槽中的第一隔离层，所述第一隔离层的表面低于所述有源区的表面；
位于所述有源区的表面的环绕所述有源区的栅介质层；
位于所述有源区侧壁上的栅介质层表面的环绕所述有源区的金属栅极，所述金属栅极的顶部表面低于所述有源区的顶部表面；
位于所述有源区的顶部表面的源区。
在一些实施例中，所述位线掺杂区的宽度大于或等于第二沟槽底部的宽度。
在一些实施例中，所述位线掺杂区中掺杂的杂质离子为N型杂质离子或P型杂质离子。
在一些实施例中，所述源区掺杂的杂质离子类型与所述位线掺杂区掺杂的杂质离子类型相同。
在一些实施例中，所述金属栅极位于所述有源区的侧壁上的栅介质层表面环绕所述有源区，所述金属栅极未填充满第一沟槽、第三沟槽和第二沟槽。
在一些实施例中，还包括覆盖所述金属栅极并填充满所述第一沟槽、第三沟槽和第二沟槽的第二隔离层；位于所述第三沟槽中的第二隔离层中的沿第二方向延伸并将若干金属栅极连接的导电连接结构。
在一些实施例中，所述金属栅极填充满第一沟槽、第三沟槽和第二沟槽，且所述金属栅极低于所述有源区的顶部表面，且所述金属栅极位于第三沟槽中的部分沿第二方向被切断。
在一些实施例中，还包括位于所述半导体衬底上的与所述源区连接的电容器
本申请的前述一些实施例提供的存储器件的形成方法，提供半导体衬底，在所述半导体衬底中形成若干有源区，所述若干有源区之间通过沿第一方向延伸的若干第一沟槽、第二沟槽以及沿第二方向延伸的若干第三沟槽分隔开，所述第一沟槽和第二沟槽与所述的第三沟槽连通，所述第一沟槽与所述第二沟槽在第一方向间隔排列，所述第二沟槽的深度小于第一沟槽的深度，且所述第三沟槽的与所述第二沟槽连通处之外区域的深度大于所述第二沟槽的深度；在所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底中形成位线掺杂区；在所述第一沟槽和第三沟槽中形成第一隔离层，所述第一隔离层的表面低于所述有源区的表面；在所述有源区的表面形成环绕所述有源区的栅介质层；在所述有源区侧壁上的栅介质层表面形成环绕所述有源区的金属栅极，所述金属栅极的顶部表面低于所述有源区的顶部表面；在所述有源区的顶部表面形成源区。通过前述所述的方法形成若干垂直晶体管，每一个垂直晶体管包括一个相应的有源区，位于有源区侧壁表面的栅介质层，位于第二沟槽底部的半导体衬底中的位线掺杂区，位于有源区顶部表面的源区，位于第一沟槽、第二沟槽和第三沟槽侧壁的栅介质层表面上环绕所述有源区的金属栅极，前述特定结构的垂直晶体管，由于源区和漏区是位于有源区的上下两侧，形成的沟道区位于有源区的侧壁，使得垂直晶体管占据的半导体衬底的面积会较小，使得单位面积上形成的垂直晶体管的数量可以增加，相应的使得后续单位面积上形成与每个晶体管的源区连接的电容器的数量也可以增加，从而提高存储器的存储容量和存储密度，并且这种特定结构的垂直晶体管能减小体效应，减少后续形成的电容器向衬底中产生的漏电流，提高存储器件的电学性能。
附图说明
图1-图43为本申请一些实施例存储器件形成过程的结构示意图。
具体实施方式
如背景技术所言，怎样进一步提升DRAM的存储容量和存储密度是本领域技术人员亟 待解决的问题。
研究发现，沟槽型晶体管一般包括位于半导体衬底中至少一个掩埋式字线和位于掩埋式字线两侧的半导体衬底中的一个漏区和至少一个源区。这样的沟槽型晶体管占据了较大的半导体衬底面积，不利于DRAM集成度的提升，从而使得DRAM的存储容量和存储密度受到限制。
为此，本申请提供了一种新型的存储器件及其形成方法，能进一步提升存储器件的存储容量和存储密度。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在详述本申请实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
参考图19-图21，其中图19为图21沿切割线AB方向的剖面结构示意图，图20为图21沿切割线CD方向的剖面结构示意图，提供半导体衬底201，在所述半导体衬底201中形成若干有源区220，所述若干有源区220之间通过沿第一方向延伸的若干第一沟槽217、第二沟槽218以及沿第二方向延伸的若干第三沟槽219分隔开，所述第一沟槽217和第二沟槽218与所述的第三沟槽219连通，所述第一沟槽217与所述第二沟槽218在第一方向间隔排列，所述第二沟槽218的深度小于第一沟槽217的深度，且所述第三沟槽219的与所述第二沟槽218连通处之外区域的深度大于所述第二沟槽218的深度。
所述半导体衬底201的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中所述半导体衬底201材料为硅。所述半导体衬底201中根据后续形成的垂直晶体管的类型需要掺杂一定的杂质离子，比如可以对所述半导体衬底进行阱区掺杂，所述杂质离子可以为N型杂质离子或P型杂质离子，所述P型的杂质离子为硼离子、镓离子或铟离子一种或几种，所述N型的杂质离子为磷离子、砷离子或锑离子一种或几种。
所述有源区220后续用于形成垂直型的晶体管的沟道区、源区和漏区，若干有源区220是分立的。
在一些实施例中，所述形成的有源区220呈行列排布(参考图21)。在其他实施例中，所述有源区也可以为其他的排布方式。
在一些实施例中，所述第一方向和所述第二方向相互垂直，两者的夹角呈90度。在其他实施例中，所述第一方向和第二方向可以不垂直，比如第一方向和第二方向之间的夹角可以为一锐角。
在一些实施例中，若干所述第二沟槽218和第一沟槽217沿第一方向延伸，且在半导体衬底201中交替分布，若干所述第三沟槽219沿第二方向延伸，第三沟槽219与第一沟槽217和第二沟槽218在交叉处连通，所述第二沟槽218的深度小于第一沟槽217的深度，所述第三沟槽219与第二沟槽218在连通处的深度相同或相差较小，且所述第三沟槽219的与所述第二沟槽218连通处之外区域的深度大于所述第二沟槽218的深度。
在一些实施例中，所述第一沟槽217的宽度可以大于所述第二沟槽218的宽度。
在一些实施例中，可以先刻蚀半导体衬底201形成沿第一方向延伸并间隔分布的若干第一沟槽217和第二沟槽218，形成的第一沟槽217的深度大于第二沟槽的深度，然后再刻蚀半导体衬底201形成沿第二方向延伸的若干第三沟槽219，从而形成若干分立的有源区220，所述第三沟槽219与第二沟槽218在连通处的深度相同或相差较小，且所述第三沟槽219的与所述第二沟槽218连通处之外区域的深度大于所述第二沟槽218的深度(在形成第三沟槽219时，先在半导体衬底201上形成掩膜层，已形成第二沟槽218和第一沟槽217的位置可以通过掩膜层覆盖而不会被刻蚀，掩膜层仅会暴露出第一沟槽和第二沟槽之间需要被刻蚀的半导体衬底的表面)。在一些实施例中，可以先刻蚀半导体衬底201形成若干第 一沟槽217，然后再刻蚀半导体衬底形成若干第二沟槽218，第二沟槽218的深度小于第一沟槽217的深度，最后再刻蚀半导体衬底201形成若干第三沟槽219，从而形成若干分立的有源区220，所述第三沟槽219与第二沟槽218在连通处的深度相同或相差较小，且所述第三沟槽219的与所述第二沟槽218连通处之外区域的深度大于所述第二沟槽218的深度。在其他实施例中，所述第一沟槽217、第二沟槽218和第三沟槽219也可以同时刻蚀所述半导体衬底201形成。
本实施例中，所述若干有源区220通过自对准双重图形掩膜工艺形成，下面结合图1-图21对所述有源区220的形成过程进行详细的描述。
参考图1，在所述半导体衬底201上形成第一硬掩膜层202；在所述第一硬掩膜层202上形成第一材料层203。
所述第一硬掩膜层202后续用于形成第一掩膜图形。在一些实施例中，所述第一硬掩膜层202可以为单层或多层堆叠结构，所述第一硬掩膜层202的材料可以为多晶硅、无定型硅，无定型碳，氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅、碳化硅、锗化硅中的一种或几种。第一硬掩膜层202的形成工艺可以为常压或低压化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、热化学气相沉积法(Thermal CVD)、物理气相沉积法(PVD)、原子层沉积法(ALD)、溅射、溅镀、电镀、旋涂法、其它适合的方法及/或上述的组合。本实施例中，所述第一硬掩膜层202的材料为多晶硅。
在一些实施例中，所述第一硬掩膜层202与半导体衬底201之间还可以形成第一刻蚀停止层(图中未示出)，所述第一刻蚀停止层用于在图形化所述第一硬掩膜层时保护底下的材料层不会被过刻蚀。所述第一刻蚀停止层的材料与所述第一硬掩膜层的材料不相同，所述第一刻蚀停止层的材料为氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅的一种或几种。本实施例中，所述第一刻蚀停止层的材料为氧化硅。
所述第一材料层203后续用于形成第一条状结构。在一些实施例中，所述第一材料层203可以为单层或多层堆叠结构，所述第一材料层203的材料可以为多晶硅、无定型硅，无定型碳，氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅、碳化硅、锗化硅中的一种或几种。本实施例中，所述第一材料层203的材料为无定型碳。
在一些实施例中，所述第一材料层203和所述第一硬掩膜层202之间还可以形成第二刻蚀停止层(图中未示出)，所述第二刻蚀停止层用于在图形化所述第一材料层203时保护底下的材料层不会被过刻蚀。所述第二刻蚀停止层的材料与所述第一材料层203不相同。所述第二刻蚀停止层的材料为氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅的一种或几种。本实施例中，所述第二刻蚀停止层的材料为氮氧化硅。
参考图2和图3，图2为图3沿切割线AB方向的剖面结构示意图，图形化所述第一材料层203(参考图1)，在所述第一硬掩膜层202上形成沿第一方向延伸且平行排布的若干第一条状结构204。
所述第一条状结构204呈长条状，所述若干第一条状结构204是分立的，且相互平行，相邻第一条状结构204之间具有开口205。
在一些实施例中，图形化所述第一材料层203采用各向异性的干法刻蚀工艺，具体的可以为各向异性的等离子体刻蚀工艺。
在一些实施例中，在图形化所述第一材料层203之前，还可以在所述第一材料层203上形成图形化的光刻胶层(图中未示出)，以所述图形化的光刻胶层为掩膜，刻蚀所述第一材料层203，形成第一条状结构204；去除所述图形化的光刻胶层。
参考图4，在所述第一条状结构204的侧壁和顶部表面以及第一条状结构204之间的第一硬掩膜层202表面形成第一牺牲侧墙层206。
所述第一牺牲侧墙层206材料与所述第一条状结构204的材料不相同，所述第一牺牲侧墙层206的材料可以为多晶硅、无定型硅，无定型碳，氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅、碳化硅、锗化硅中的一种或几种。形成所述第一牺牲侧墙层206采用 沉积工艺，所述沉积工艺包括原子层沉积工艺。
参考图5，在所述第一条状结构204之间填充第一填充层207。
所述第一填充层207位于第一条状结构204之间的第一牺牲侧墙层206表面，填充满第一条状结构204之间的开口。
后续通过去除所述第一条状结构204侧壁表面的第一牺牲侧墙层206，在第一条状结构204和第一填充层207之间形成第四开口。
所述第一填充层207的材料与所述第一牺牲侧墙层206的材料不相同。在一些实施例中，所述第一填充层207的材料可以为多晶硅、无定型硅，无定型碳，氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅、碳化硅、锗化硅、有机材料中的一种或几种。第一填充层207的形成工艺可以为常压或低压化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、热化学气相沉积法(Thermal CVD)、物理气相沉积法(PVD)、原子层沉积法(ALD)、溅射、溅镀、电镀、旋涂法、其它适合的方法及/或上述的组合。
在一些实施例中，所述形成的第一填充层207的表面可以与所述第一条状结构204顶部表面上的第一牺牲侧墙层206齐平。具体的，形成覆盖所述第一牺牲侧墙层206以及填充满第一条状结构204之间剩余的开口的第一填充材料层后，通过化学机械掩膜工艺去除高于第一条状结构204顶部表面上的第一牺牲侧墙层206表面的第一填充层，将开口中剩余的第一填充材料层作为第一填充层207。
在一些实施例中，所述形成的第一填充层的表面可以与所述第一条状结构204顶部表面齐平。具体的，形成覆盖所述第一牺牲侧墙层206以及填充满第一条状结构204之间剩余的开口的第一填充材料层后，通过化学机械掩膜工艺去除高于第一条状结构204顶部表面的第一牺牲侧墙层206和第一填充材料层，暴露出所述第一条状结构204的顶部表面，将开口中剩余的第一填充材料层作为第一填充层，因而形成的第一填充层顶部表面与所述第一条状结构的顶部表面齐平，后续在形成第三开口后，在刻蚀所述第一硬掩膜层时，能减小填充层和第一条状结构高度不同带来的刻蚀负载效应，提高形成的第一掩膜图形的位置和尺寸的精度以及保持较好的侧壁形貌，进而使得断开第一掩膜图形后形成的块状掩膜图形位置和尺寸的精度较高以及保持较好的侧壁形貌，最终使得以块状掩膜图形为掩膜刻蚀半导体衬底形成的有源区的位置和尺寸的精度较高以及保持较好的侧壁形貌。
参考图6去除所述第一条状结构204侧壁表面的第一牺牲侧墙层，在第一条状结构204和第一填充层207之间形成第四开口208。
在一些实施例中，去除所述第一条状结构204侧壁表面的第一牺牲侧墙层采用各向异性的干法刻蚀工艺，包括各向异性的等离子体刻蚀工艺。
需要说明的是，在一些实施例中，在去除所述第一条状结构204侧壁表面的第一牺牲侧墙层时，所述第一条状结构204顶部表面的第一牺牲侧墙层也会被去除。
参考图7-图9，图7为图9沿切割线AB方向的剖面结构示意图，图8为图9沿切割线CD方向的剖面结构示意图，沿第四开口刻蚀所述第一硬掩膜层202，在所述第一硬掩膜层202中形成沿第一方向延伸的若干第一开口210。
在一些实施例中，刻蚀所述第一硬掩膜层202采用各向异性的干法刻蚀工艺，包括各向异性的等离子体刻蚀工艺。
本申请中所述第一开口210通过前述的自对准双重图形工艺形成，后续在形成有源区时，使得有源区之间的与第一开口对应的第一沟槽宽度可以较小，从而使得有源区的面积可以较大。
参考图10，图10在图7的基础上进行，形成填充满第一开口的第二填充层；在第二填充层上形成沿第一方向延伸且平行排布的若干第二条状结构211，每一个所述第二条状结构211覆盖一个第一开口中的第二填充层以及第一开口两侧的部分第一硬掩模层202，且相邻的两个第二条状结构211之间暴露出一个开口中填充的第二填充层。
在一些实施例中，所述第二填充层和第二条状结构211在同一步工艺中形成，具体过 程包括：在所述第一硬掩膜层202表面形成第二材料层，所述第二材料层填充满所述第一开口；刻蚀去除部分第二材料层，形成若干第二条状结构211和填充满第一开口的第二填充层。
所述第二填充层和和第二条状结构211的材料与所述第一硬掩膜层202的材料不相同。在一些实施例中，所述第二填充层和和第二条状结构211的材料可以为多晶硅、无定型硅，无定型碳，氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅、碳化硅、锗化硅、有机材料中的一种或几种。
参考图11，在所述第二条状结构211的侧壁和顶部表面以及第二条状结构211之间的第一硬掩膜层202和第一填充层表面形成第二牺牲侧墙层212。
所述第二牺牲侧墙层212材料与所述第二条状结构211的材料不相同，在一些实施例中，所述第二牺牲侧墙层212的材料可以为多晶硅、无定型硅，无定型碳，氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅、碳化硅、锗化硅中的一种或几种。形成所述第二牺牲侧墙层212采用沉积工艺，所述沉积工艺包括原子层沉积工艺。
参考图12，在所述第二条状结构211之间填充第三填充层213。
所述第三填充层213位于第二条状结构211之间的第二牺牲侧墙层212上，且填充满第二条状结构211之间的空间。
后续通过去除所述第二条状结构204侧壁表面的第二牺牲侧墙层，在第二条状结构211和第三填充层213之间形成第五开口。
所述第三填充层213的材料与所述第二牺牲侧墙层212的材料不相同。在一些实施例中，所述第三填充层213的材料可以为多晶硅、无定型硅，无定型碳，氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅、碳化硅、锗化硅、有机材料中的一种或几种。第三填充层213的形成工艺可以为常压或低压化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、热化学气相沉积法(Thermal CVD)、物理气相沉积法(PVD)、原子层沉积法(ALD)、溅射、溅镀、电镀、旋涂法、其它适合的方法及/或上述的组合。
参考图13-图15，图13为图15沿切割线AB方向的剖面结构示意图，图14为图15沿切割线CD方向的剖面结构示意图，去除所述第二条状结构211侧壁表面的第二牺牲侧墙层212(参考图12)，在第二条状结构211和第二填充层213之间形成第五开口，所述第五开口的宽度小于前述所述的第四开口的宽度；沿第五开口刻蚀所述第一开口210之间的第一硬掩膜层，在所述第一硬掩膜层中形成第二开口214，所述第二开口214的宽度小于所述第一开口210的宽度，若干第二开口214和第一开口210交替分布，所述第二开口214和所述第一开口210之间剩余的第一硬掩膜层即为第一掩膜图形209。
在一些实施例中，刻蚀所述第一硬掩膜层202采用各向异性的干法刻蚀工艺，包括各向异性的等离子体刻蚀工艺。
所述形成的若干第一掩膜图形209是分立的，具体的，所述形成的第一掩膜图形209沿第一方向延伸且相互平行，相邻第一掩膜图形209之间具有交替分布的第一开口210和第二开口214。
所述形成的第二开口214的宽度小于所述第一开口210的宽度，后续在同一刻蚀工艺刻蚀半导体衬底201时，使得所述第二开口214底部的半导体衬底的刻蚀速率大于所述第一开口底部的半导体衬底的刻蚀速率，从而使得半导体衬底201中对应形成的第二沟槽的深度小于第一沟槽的深度，在使得形成第一沟槽和第二沟槽的尺寸较小的同时，可以简化第一沟槽和第二沟槽的形成工艺。
本申请中前述第一掩膜图形209通过前述的自对准双重图形工艺形成，后续在形成有源区时，使得有源区之间的第一沟槽和第二沟槽的宽度都可以较小，从而使得有源区的面积可以较大。
在所述半导体衬底201上形成沿第一方向延伸的若干平行的第一掩膜图形209，相邻第一掩膜图形209之间具有交替分布的第一开口210和第二开口214，所述第一开口210的宽 度大于所述第二开口214的宽度后，还包括：在所述第一掩膜图形209上形成沿第二方向延伸的若干平行的第二掩膜图形，相邻第二掩膜图形之间具有第六开口，所述第二掩膜图形也采用自对准双重图形工艺形成；以所述第二掩膜图形为掩膜，沿第六开口刻蚀所述第一掩膜图形，在第一掩膜图形中形成沿第二方向延伸的若干第三开口215，剩余的第一掩膜图形形成若干分立的刻蚀掩膜216(参考图16-图18，图16为图18沿切割线AB方向的剖面结构示意图，图17为图18沿切割线CD方向的剖面结构示意图)。
参考图19-21，以所述刻蚀掩膜为掩膜，刻蚀所述半导体衬底201，在所述半导体衬底201中形成与第一开口对应的第一沟槽217、与第二开口对应的第二沟槽218，与第三开口对应的第三沟槽219，所述第一沟槽217、第二开口218和第三沟槽219之间为有源区220，所述第一沟槽217和第二沟槽218与所述第三沟槽219连通，所述第二沟槽218的深度小于第一沟槽217的深度，且所述第三沟槽219的与所述第二沟槽218连通处之外区域的深度大于所述第二沟槽218的深度。
刻蚀所述半导体衬底201采用各向异性的干法刻蚀工艺，包括各向异性的等离子体刻蚀工艺。
所述刻蚀掩膜可以在刻蚀半导体衬底的过程中同步去除，或者在形成有源区后采用额外的刻蚀工艺去除。
参考图22和图23，图22在图19的基础上进行，图23在图20的基础上进行，在所述第一沟槽217、第三沟槽219和第二沟槽218的侧壁和底部表面形成保护层221。
所述保护层221在后续进行离子注入时保护所述有源区220的侧壁表面。
在一些实施例中，所述保护层221的材料可以为氧化硅。所述保护层221通过氧化工艺形成，具体可以为炉管氧化。
参考图24和图25，形成保护层后221，在所述半导体衬底201表面上形成掩膜层222，所述掩膜层222中具有暴露出第二沟槽218的底部以及第二沟槽218与第三沟槽219连通处底部的半导体衬底201的开口。
所述掩膜层222可以为单层或多层堆叠结构(比如双层堆叠结构)。在一些实施例中，所述掩膜层222可以包括硬掩膜材料层和位于硬掩膜材料层表面上的光刻胶层。所述硬掩膜材料层的材料可以为氮化硅，氮氧化硅，氧化硅，氮碳化硅，碳氧化硅中的一种或几种。
参考图26和图27，以所述掩膜层222为掩膜，沿开口对所述第二沟槽218的底部以及第二沟槽218与第三沟槽219连通处底部的半导体衬底201的进行第一离子注入工艺，在所述第二沟槽218的底部以及第二沟槽218与第三沟槽219连通处底部的半导体衬底201中形成位线掺杂区223。
形成所述位线掺杂区223通过第一离子注入，所述位线掺杂区223中注入的杂质离子的类型与有源区220阱区注入的杂质离子的类型不同，比如当有源区220中阱区注入P型杂质离子时，则所述位线掺杂区217中注入N型的杂质离子，当所述当有源区220中阱区注入N型杂质离子时，则所述位线掺杂区217中注入P型的杂质离子。所述位线掺杂区217中注入的杂质离子为N型杂质离子或P型杂质离子，所述P型的杂质离子为硼离子、镓离子或铟离子一种或几种，所述N型的杂质离子为磷离子、砷离子或锑离子一种或几种。
在一些实施例中，进行第一离子注入后，还需要进行退火工艺，以激活掺杂离子。
在一些实施例中，所述形成的位线掺杂区223的宽度大于或等于第二沟槽218底部的宽度，所述位线掺杂区223的底部与第一沟槽217的底部平齐或者高于所述第一沟槽217的底部(位线掺杂区223的底部相对于第一沟槽217的底部与有源区220的表面更近)。
所述位线掺杂区223与有源区220接触的部分作为垂直晶体管的漏区，相邻第一开口218之间的具有两个有源区220，这两个有源区220中形成的垂直晶体管共用一个漏区，以提高器件的集成度，并且每一个位线掺杂区223将沿第一方向上的每相邻的两排垂直晶体管的漏区电连接，以提高垂直晶体管的操控能力，进而提高对后续形成的存储器的操作能力(读、写和删除)。
在一些实施例中，参考图28和29，形成位线掺杂区223后，去除所述保护层221和掩膜层222。
去除所述保护层221和掩膜层222采用湿法刻蚀工艺。
参考图30和图31，在所述第一沟槽217和第三沟槽219中形成第一隔离层224，所述第一隔离层224的表面低于所述有源区220的表面。
所述第一隔离层224用于相邻有源区以及相邻位线掺杂区223之间的电学隔离。在一些实施例中，所述第一隔离层224的材料为氧化硅、氮化硅、氮氧化硅、氟掺杂硅玻璃(FSG)、低介电常数(K小于2.8)材料、其它适合的材料及/或上述的组合。
在一些实施例中，所述第一隔离层224的形成过程包括：通过沉积工艺在有源区220表面以及第一沟槽217、第二沟槽218和第三沟槽219中形成第一隔离材料层；回刻蚀去除部分所述第一隔离材料层，在所述第一沟槽217和第三沟槽219中形成第一隔离层224。
参考图32和图33，在所述有源区220的表面形成环绕所述有源区220的栅介质层225；在所述有源区220侧壁上的栅介质层225表面形成环绕所述有源区220的金属栅极226，所述金属栅极226的顶部表面低于所述有源区220的顶部表面。
所述栅介质层225的材料可以为氧化硅或高K(介电常数)介质材料，所述高K介质材料为HfO 2、TiO 2、HfZrO、HfSiNO、Ta 2O 5、ZrO 2、ZrSiO 2、Al 2O 3、SrTiO 3或BaSrTiO中的一种或几种。
所述栅介质层225可以通过氧化或沉积工艺形成。
在一些实施例中，可以去除所述保护层236后，形成所述栅介质层225。在另一实施例中，所述保护层236可以不去除，直接在所述保护层236上形成栅介质层。
在一些实施例中，在形成栅介质层225时，所述栅介质层225也可以形成在所述第一沟槽、第二沟槽和第三沟槽的底部表面以及有源区的顶部表面。
所述形成的金属栅极226环绕每一个有源区的侧壁，所述金属栅极226的顶部表面低于所述有源区220的顶部表面，可以提高金属栅极220对有源区侧壁中形成沟道的控制能力，提高形成垂直晶体管的性能。
在一些实施例中，所述金属栅极226的材料可以为W、Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、WN、Wsi中的一种或几种。
在一些实施例中，所述金属栅极226的形成过程包括：在所述栅介质层表面以及第一隔离层表面形成金属层；无掩膜刻蚀去除多余的金属层，在所述有源区侧壁的栅介质层表面形成环绕所述有源区的金属栅极226。这种工艺中相邻的有源区220侧壁上的金属栅极226之间是不存在电连接的，若干金属栅极226是分立的。后续可以形成将第二方向上的每一行中的多个金属栅极电连接的导电连接结构，相邻行的金属栅极仍是断开的，以提高垂直晶体管的操控能力，进而提高对后续形成的存储器的操作能力(读、写和删除)。
在另一些实施例中，所述金属栅极的形成过程包括：在所述栅介质层表面以及第一隔离层表面形成填充满第一沟槽、第三沟槽和第二沟槽的金属层；回刻蚀所述金属层，使得金属层的顶部表面低于所述有源区的顶部表面；回刻蚀所述金属层后，沿第二方向将所述第三沟槽中填充的金属层切断，在所述有源区侧壁的栅介质层表面形成环绕所述有源区的金属栅极。这种方式形成的金属栅极，第二方向上每一行的多个金属栅极是连接在一起的，第二方向上相邻行的金属栅极是断开的。
参考图34和图35，在所述有源区220的顶部表面形成源区227。
所述源区227中掺杂的杂质离子的类型与位线掺杂区223中掺杂的杂质离子的类型相同，且与有源区中阱区掺杂的杂质离子的类型不相同。所述源区227通过第二离子注入工艺形成。所述源区227中注入的(掺杂的)杂质离子为N型杂质离子或P型杂质离子，所述P型的杂质离子为硼离子、镓离子或铟离子一种或几种，所述N型的杂质离子为磷离子、砷离子或锑离子一种或几种。
在一些实施例中，参考图36和图37，在形成若干分立的金属栅极226后，形成覆盖所 述金属栅极226并填充满所述第一沟槽、第三沟槽和第二沟槽的第二隔离层228；在所述第三沟槽的第二隔离层228中形成沿第二方向延伸并将若干金属栅极226连接的导电连接结构。
在一些实施例中，当形成的第二方向上每一行的多个金属栅极本身就是连接在一起的，第二方向上相邻行的金属栅极是断开的时，直接形成填充满所述第一沟槽、第三沟槽和第二沟槽的第二隔离层，无需额外再形成导电连接结构。
本申请中，通过前述工艺形成若干垂直晶体管，每一个垂直晶体管包括一个相应的有源区220，位于有源区220侧壁表面的栅介质层225，位于第二沟槽底部的半导体衬底中的位线掺杂区223，位于有源区220顶部表面的源区227，位于第一沟槽、第二沟槽和第三沟槽侧壁的栅介质层表面上环绕所述有源区220的金属栅极226，前述特定结构的垂直晶体管，由于源区和漏区是位于有源区的上下两侧，形成的沟道区位于有源区的侧壁，使得垂直晶体管占据的半导体衬底的面积会较小，使得单位面积上形成的垂直晶体管的数量可以增加，相应的使得后续单位面积上形成与每个晶体管的源区连接的电容器的数量也可以增加，从而提高存储器的存储容量和存储密度，并且这种特定结构的垂直晶体管能减小体效应，减少后续形成的电容器向衬底中产生的漏电流，提高存储器件的电学性能。
在一些实施例中，在形成所述源区227后，还包括，在所述半导体衬底201表面上形成与源区227连接的电容器。
在一些实施例中，在所述半导体衬底表面上形成与所述源区连接的电容器的过程包括：在所述半导体衬底上形成第一介质层；在所述第一介质层中形成暴露出所述源区表面的通孔；在所述通孔中形成接触插塞；在所述第一介质层上形成第二介质层；在所述第二介质层中形成暴露出所述接触插塞的电容孔；在所述电容孔中形成电容器。
在一些实施例中，在所述半导体衬底201表面上形成与源区223连接的电容器的过程包括：参考图38和图39，在所述第二隔离层228上形成第一介质层230；在所述第一介质层230和第二隔离层228中形成暴露出所述源区227表面的通孔231。在一些实施例中，所述形成的通孔231的开口可以向两侧扩宽，以便于后续形成接触插塞，并使得形成的接触插塞顶部表面与后续形成的电容器的接触面积增大。参考图40和图41，在所述通孔中形成接触插塞232，所述接触插塞232的材料为金属。参考图42和图43，在所述第二介质层230上形成第三介质层233；在所述第三介质层233中形成暴露出所述接触插塞232的电容孔；在所述电容孔中形成电容器234。
在一些实施例中，所述电容器234包括下电极层、位于下电极层上的介电层、和位于介电层上的上电极层。
在一些实施例中，所述介电层的材料可以为高K介质材料，以提高单位面积电容器的电容值，所述高K介质材料包括HfO 2、TiO 2、HfZrO、HfSiNO、Ta 2O 5、ZrO 2、ZrSiO 2、Al 2O 3、SrTiO 3或BaSrTiO中的一种或上述材料所组成群组中的两种以上所形成的叠层。
在一些实施例中，所述上电极层和下电极层的材料可以为钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的一种或上述材料所组成群组中的两种以上所形成的叠层，还可以包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSixNy)等。
在其他一些实施例中，所述电容器也可以采用现有的双面电容形成工艺形成。
本发明一些实施例还提供了一种存储器件，参考图42和图43并结合参考图19-图21，包括：
半导体衬底201，所述半导体衬底201中形成有若干有源区220，所述若干有源区220之间通过沿第一方向延伸的若干第一沟槽217、第二沟槽218以及沿第二方向延伸的若干第三沟槽219分隔开，所述第一沟槽217和第二沟槽218与所述的第三沟槽219连通，所述第一沟槽217与所述第二沟槽218在第一方向间隔排列，所述第二沟槽218的深度小于第一沟槽217的深度，且所述第三沟槽219的与所述第二沟槽218连通处之外区域的深度大 于所述第二沟槽218的深度；
位于所述第二沟槽218的底部以及第二沟槽218与第三沟槽219连通处底部的半导体衬底201中的位线掺杂区223；
位于所述第一沟槽217和第三沟槽219中的第一隔离层224，所述第一隔离层224的表面低于所述有源区220的表面；
位于所述有源区220的表面的环绕所述有源区220的栅介质层225；
位于所述有源区220侧壁上的栅介质层225表面的环绕所述有源区220的金属栅极226，所述金属栅极226的顶部表面低于所述有源区220的顶部表面；
位于所述有源区220的顶部表面的源区227。
在一些实施例中，所述位线掺杂区223的宽度大于或等于第二沟槽218底部的宽度。
在一些实施例中，所述位线掺杂区223中掺杂的杂质离子为N型杂质离子或P型杂质离子。
在一些实施例中，所述源区227掺杂的杂质离子类型与所述位线掺杂区223掺杂的杂质离子类型相同。
在一些实施例中，所述金属栅极226位于所述有源区的侧壁上的栅介质层表面环绕所述有源区，所述金属栅极226未填充满第一沟槽、第三沟槽和第二沟槽。
在一些实施例中，还包括，覆盖所述金属栅极226并填充满所述第一沟槽、第三沟槽和第二沟槽的第二隔离层228；位于所述第三沟槽中的第二隔离层228中的沿第二方向延伸并将若干金属栅极连接的导电连接结构229(参考图43)。
在另一些实施例中，所述金属栅极填充满第一沟槽、第三沟槽和第二沟槽，且所述金属栅极低于所述有源区的顶部表面，且所述金属栅极位于第三沟槽中的部分沿第二方向被切断。
在一些实施例中，还包括位于所述半导体衬底201上的与所述源区227连接的电容器234。
需要说明的是，本实施例(存储器件)与前述实施例(存储器件的形成过程)中相同或相似结构的限定或描述，在本实施例中不再赘述，具体请参考前述实施例中相应部分的限定或描述。
本申请虽然已以较佳实施例公开如上，但其并不是用来限定本申请，任何本领域技术人员在不脱离本申请的精神和范围内，都可以利用上述揭示的方法和技术内容对本申请技术方案做出可能的变动和修改，因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本申请技术方案的保护范围。

Claims (23)

  1. 一种存储器件的形成方法，包括：
    提供半导体衬底，在所述半导体衬底中形成若干有源区，所述若干有源区之间通过沿第一方向延伸的若干第一沟槽、第二沟槽以及沿第二方向延伸的若干第三沟槽分隔开，所述第一沟槽和第二沟槽与所述的第三沟槽连通，所述第一沟槽与所述第二沟槽在第一方向间隔排列，所述第二沟槽的深度小于第一沟槽的深度，且所述第三沟槽的与所述第二沟槽连通处之外区域的深度大于所述第二沟槽的深度；
    在所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底中形成位线掺杂区；
    在所述第一沟槽和第三沟槽中形成第一隔离层，所述第一隔离层的表面低于所述有源区的表面；
    在所述有源区的表面形成环绕所述有源区的栅介质层；
    在所述有源区侧壁上的栅介质层表面形成环绕所述有源区的金属栅极，所述金属栅极的顶部表面低于所述有源区的顶部表面；
    在所述有源区的顶部表面形成源区。
  2. 如权利要求1所述的存储器件的形成方法，其中，所述位线掺杂区的宽度大于或等于第二沟槽底部的宽度。
  3. 如权利要求2所述的存储器件的形成方法，其中，所述位线掺杂区通过第一离子注入工艺形成，所述第一离子注入工艺注入的杂质离子为N型杂质离子或P型杂质离子。
  4. 如权利要求3所述的存储器件的形成方法，其中，在进行第一离子注入工艺之前，在所述第一沟槽、第三沟槽和第二沟槽的侧壁和底部表面形成保护层；形成保护层后，在所述半导体衬底表面上形成掩膜层，所述掩膜层中具有暴露出第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底的开口；以所述掩膜层为掩膜，沿开口对所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底的进行第一离子注入工艺，在所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底中形成位线掺杂区。
  5. 如权利要求1所述的存储器件的形成方法，其中，所述源区通过第二离子注入工艺形成。
  6. 如权利要求2所述的存储器件的形成方法，其中，所述源区掺杂的杂质离子类型与所述位线掺杂区掺杂的杂质离子类型相同。
  7. 如权利要求1所述的存储器件的形成方法，其中，所述金属栅极的形成过程包括：在所述栅介质层表面以及第一隔离层表面形成金属层；无掩膜刻蚀去除多余的金属层，在所述有源区侧壁的栅介质层表面形成环绕所述有源区的金属栅极。
  8. 如权利要求3所述的存储器件的形成方法，其中，在形成金属栅极后，形成覆盖所述金属栅极并填充满所述第一沟槽、第三沟槽和第二沟槽的第二隔离层；在所述第三沟槽的第二隔离层中形成沿第二方向延伸并将若干金属栅极连接的导电连接结构。
  9. 如权利要求1所述的存储器件的形成方法，其中，所述金属栅极的形成过程包括：在所述栅介质层表面以及第一隔离层表面形成填充满第一沟槽、第三沟槽和第二沟槽的金属层；回刻蚀所述金属层，使得金属层的顶部表面低于所述有源区的顶部表面；回刻蚀所述金属层后，沿第二方向将所述第三沟槽中填充的金属层切断，在所述有源区侧壁的栅介质层表面形成环绕所述有源区的金属栅极。
  10. 如权利要求1所述的存储器件的形成方法，其中，还包括：在所述半导体衬底表面上形成与所述源区连接的电容器。
  11. 如权利要求10所述的存储器件的形成方法，其中，在所述半导体衬底表面上形成与所述源区连接的电容器的过程包括：在所述半导体衬底上形成第一介质层；在所述第一介质层中形成暴露出所述源区表面的通孔；在所述通孔中形成接触插塞；在所述第一介质层上形成第二介质层；在所述第二介质层中形成暴露出所述接触插塞的电容孔；在所述电容孔中形成电容器。
  12. 如权利要求1所述的存储器件的形成方法，其中，所述若干有源区呈行列排布。
  13. 如权利要求12所述的存储器件的形成方法，其中，所述若干有源区的形成过程包括：
    在所述半导体衬底上形成沿第一方向延伸的若干平行的第一掩膜图形，相邻第一掩膜图形之间具有交替分布的第一开口和第二开口，所述第一开口的宽度大于所述第二开口的宽度；在所述第一掩膜图形上形成沿第二方向延伸的若干平行的第二掩膜图形，相邻第二掩膜图形之间具有第六开口；以所述第二掩膜图形为掩膜，沿第六开口刻蚀所述第一掩膜图形，在第一掩膜图形中形成沿第二方向延伸的若干第三开口，剩余的第一掩膜图形形成若干分立的刻蚀掩膜；以所述刻蚀掩膜为掩膜，刻蚀所述半导体衬底，在所述半导体衬底中形成与第一开口对应的第一沟槽、与第二开口对应的第二沟槽，与第三开口对应的第三沟槽，所述第一沟槽、第二开口和第三沟槽之间为有源区，所述第一沟槽和第二沟槽与所述第三沟槽连通，所述第二沟槽的深度小于第一沟槽的深度，且所述第三沟槽的与所述第二沟槽连通处之外区域的深度大于所述第二沟槽的深度。
  14. 如权利要求13所述的存储器件的形成方法，其中，所述第一掩膜图形和第二掩膜图形通过自对准双重图形工艺形成。
  15. 如权利要求14所述的存储器件的形成方法，其中，所述第一掩膜图形的形成过程包括：
    在所述半导体衬底上形成第一硬掩膜层；在所述第一硬掩膜层上形成沿第一方向延伸且平行排布的若干第一条状结构；在所述第一条状结构的侧壁和顶部表面以及第一条状结构之间的第一硬掩膜层表面形成第一牺牲侧墙层；在所述第一条状结构之间填充第一填充层；去除所述第一条状结构侧壁表面的第一牺牲侧墙层，在第一条状结构和第一填充层之间形成第四开口；沿第四开口刻蚀所述第一硬掩膜层，在所述第一硬掩膜层中形成第一开口；形成填充满第一开口的第二填充层；在第二填充层上形成沿第一方向延伸且平行排布的若干第二条状结构，每一个所述第二条状结构覆盖一个第一开口中的第二填充层以及第一开口两侧的部分第一硬掩模层；在所述第二条状结构的侧壁和顶部表面以及第二条状结构之间的第一硬掩膜层和第一填充层表面形成第二牺牲侧墙层；在所述第二条状结构之间填充第三填充层；去除所述第二条状结构侧壁表面的第二牺牲侧墙层，在第二条状结构和第二填充层之间形成第五开口，所述第五开口的宽度小于所述第四开口的宽度；沿第五开口刻蚀所述第一开口之间的第一硬掩膜层，在所述第一硬掩膜层中形成第二开口，所述第二开口的宽度小于所述第一开口的宽度，所述第二开口和所述第一开口之间剩余的第一硬掩膜层即为第一掩膜图形。
  16. 一种存储器件，包括：
    半导体衬底，所述半导体衬底中形成有若干有源区，所述若干有源区之间通过沿第一方向延伸的若干第一沟槽、第二沟槽以及沿第二方向延伸的若干第三沟槽分隔开，所述第一沟槽和第二沟槽与所述的第三沟槽连通，所述第一沟槽与所述第二沟槽在第一方向间隔排列，所述第二沟槽的深度小于第一沟槽的深度，且所述第三沟槽的与所述第二沟槽连通处之外区域的深度大于所述第二沟槽的深度；
    位于所述第二沟槽的底部以及第二沟槽与第三沟槽连通处底部的半导体衬底中的位线掺杂区；
    位于所述第一沟槽和第三沟槽中的第一隔离层，所述第一隔离层的表面低于所述有源区的表面；
    位于所述有源区的表面的环绕所述有源区的栅介质层；
    位于所述有源区侧壁上的栅介质层表面的环绕所述有源区的金属栅极，所述金属栅极的顶部表面低于所述有源区的顶部表面；
    位于所述有源区的顶部表面的源区。
  17. 如权利要求16所述的存储器件，其中，所述位线掺杂区的宽度大于或等于第二沟槽底部的宽度。
  18. 如权利要求17所述的存储器件，其中，所述位线掺杂区中掺杂的杂质离子为N型杂质 离子或P型杂质离子。
  19. 如权利要求16所述的存储器件，其中，所述源区掺杂的杂质离子类型与所述位线掺杂区掺杂的杂质离子类型相同。
  20. 如权利要求16所述的存储器件，其中，所述金属栅极位于所述有源区的侧壁上的栅介质层表面环绕所述有源区，所述金属栅极未填充满第一沟槽、第三沟槽和第二沟槽。
  21. 如权利要求20所述的存储器件，其中，还包括覆盖所述金属栅极并填充满所述第一沟槽、第三沟槽和第二沟槽的第二隔离层；位于所述第三沟槽中的第二隔离层中的沿第二方向延伸并将若干金属栅极连接的导电连接结构。
  22. 如权利要求16所述的存储器件，其中，所述金属栅极填充满第一沟槽、第三沟槽和第二沟槽，且所述金属栅极低于所述有源区的顶部表面，且所述金属栅极位于第三沟槽中的部分沿第二方向被切断。
  23. 如权利要求16所述的存储器件，其中，还包括，位于所述半导体衬底上的与所述源区连接的电容器。
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CN117119784A (zh) * 2023-10-25 2023-11-24 合肥晶合集成电路股份有限公司 半导体结构及其制备方法
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