WO2023040278A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2023040278A1
WO2023040278A1 PCT/CN2022/089523 CN2022089523W WO2023040278A1 WO 2023040278 A1 WO2023040278 A1 WO 2023040278A1 CN 2022089523 W CN2022089523 W CN 2022089523W WO 2023040278 A1 WO2023040278 A1 WO 2023040278A1
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Prior art keywords
module
terminal
transistor
control
electrically connected
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PCT/CN2022/089523
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English (en)
French (fr)
Inventor
郭恩卿
潘康观
盖翠丽
陈发祥
邢汝博
王刚
李俊峰
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Yungu Guan Technology Co Ltd
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Yungu Guan Technology Co Ltd
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Priority to KR1020237029536A priority Critical patent/KR102784476B1/ko
Priority to JP2023568147A priority patent/JP7656084B2/ja
Priority to EP22868656.4A priority patent/EP4273844A4/en
Publication of WO2023040278A1 publication Critical patent/WO2023040278A1/zh
Priority to US18/240,684 priority patent/US12057072B2/en
Anticipated expiration legal-status Critical
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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Definitions

  • the embodiments of the present application relate to the field of display technology, for example, to a pixel circuit, a driving method thereof, and a display panel.
  • the power consumption of the display panel mainly lies in the pixel circuit and the light emitting device.
  • the power consumption can be reduced by reducing the frame rate.
  • the refresh rate of the display panel is reduced, the pixel circuit has the problem of electric leakage, which causes flickering of the display screen and affects the display quality of the display panel.
  • Embodiments of the present application provide a pixel circuit, a driving method thereof, and a display panel, so as to improve the leakage problem of the pixel circuit at a low refresh rate, thereby realizing the effect of both low power consumption and high display quality.
  • a pixel circuit comprising:
  • a drive module including a control terminal, a first terminal and a second terminal;
  • the data writing module includes a scanning control terminal, a first terminal and a second terminal, the first terminal of the data writing module is electrically connected to the first terminal of the driving module, and the second terminal of the data writing module Accessing data signals, the scanning control terminal of the data writing module accesses the first scanning signal;
  • a compensation module including a control terminal, a first terminal and a second terminal, the first terminal of the compensation module is electrically connected to the second terminal of the driving module, and the control terminal of the compensation module is connected to the first lighting control signal;
  • the leakage suppression module includes a control terminal, a first terminal and a second terminal, the first terminal of the leakage suppression module is electrically connected to the control terminal of the driving module, and the second terminal of the leakage suppression module is connected to the compensation module
  • the second end of the leakage suppression module is electrically connected to the second end, and the control terminal of the leakage suppression module is connected to the first light-emitting control signal; the leakage suppression module and the compensation module are turned on during the initialization phase and the data writing phase;
  • the first storage module includes a first terminal and a second terminal, the first terminal of the first storage module is electrically connected to the second terminal of the compensation module, and the second terminal of the first storage module is connected to a reference voltage signal; the first memory module is set to maintain the pressure difference between the first end of the first memory module and the second end of the first memory module during the data writing stage and the light emitting stage The pressure difference does not change.
  • the application of the present invention also provides a display panel, including: the pixel circuit described in any embodiment of the application of the present invention.
  • the present application also provides a driving method for a pixel circuit, which is applicable to the pixel circuit provided in any embodiment of the present application, and the driving method includes:
  • the first lighting control signal controls the compensation module and the leakage suppression module to be turned on, so that the first terminal of the driving module and the second terminal of the driving module are respectively connected to different voltages.
  • the drive module is turned on for initialization;
  • the first light-emitting control signal controls the conduction of the compensation module and the leakage suppression module
  • the first scan signal controls the conduction of the data writing module, so that the data signal write into the control terminal of the drive module; the potentials of the first terminal of the first storage module and the control terminal of the drive module are equal, and the first terminal of the first storage module and the first terminal of the first storage module A pressure difference is formed at both ends;
  • the first light-emitting control signal controls the compensation module and the leakage suppression module to be disconnected
  • the first scanning signal controls the data writing module to be disconnected
  • the first storage module maintains the The voltage difference between the first terminal of the first storage module and the second terminal of the first storage module is constant, so that the potentials of the first terminal of the leakage suppression module and the second terminal of the leakage suppression module are equal.
  • the leakage suppression module is arranged between the control terminal of the driving module and the second terminal of the compensation module, and the first storage module is arranged between the reference voltage signal and the second terminal of the compensation module.
  • the control terminal of the driving module is provided with only one leakage current channel, which connects the control terminal of the driving module and the second terminal of the driving module, and the channel is composed of a leakage suppression module and a compensation module controlled by the first lighting control signal. Only when the potential of the second terminal of the compensation module drifts greatly, the leakage suppression module will generate a large leakage current, and the potential of the control terminal of the driving module will drift.
  • the potential of the control terminal of the driving module is close to the potential of the second terminal of the compensation module, so that the leakage current of the leakage suppression module is small, and the leakage current of the only leakage channel is reduced. Therefore, the control of the driving module
  • the potential of the terminal is more stable, a high current holding rate is realized, and the flicker phenomenon of the display panel is improved.
  • the embodiment of the present application makes a breakthrough improvement on the reset path and reset method of the control terminal of the driving module.
  • the combination of the first storage module and the leakage suppression module effectively suppresses the leakage of the control terminal of the driving module, which is beneficial to realize High-quality display, which is conducive to achieving the effect of both low power consumption and high display quality.
  • the pixel circuit provided by the embodiment of the present application can be connected to different voltages at the first terminal of the driving module and the second terminal of the driving module at the initialization stage, for example, the first terminal of the driving module One end is connected to the first power supply signal, the second end is connected to the second power supply signal, the drive module is turned on, and a large current flows, which is conducive to improving the bias voltage of the drive module while initializing the control terminal of the drive module state, which is beneficial to improve the problem of afterimage.
  • FIG. 1 is a schematic circuit diagram of a pixel circuit
  • FIG. 2 is a schematic layout diagram of the pixel circuit shown in FIG. 1;
  • FIG. 3 is a schematic circuit diagram of another pixel circuit
  • FIG. 4 is a schematic layout diagram of the pixel circuit shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic layout diagram of the pixel circuit shown in FIG. 7;
  • FIG. 9 is a schematic flowchart of a method for driving a pixel circuit provided in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a driving sequence of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit is a 7T1C structure.
  • the pixel circuit includes a transistor M1', a transistor M2', a transistor M3', a transistor M4', a transistor M5', a transistor M6', a transistor M7' and a capacitor Cst'.
  • all the transistors are P-type transistors, which are manufactured by Low Temperature Poly-Silicon (LTPS) process.
  • LTPS transistors have the advantages of high mobility, strong driving capability and low process cost, and are widely used in pixel circuits.
  • the disadvantage of LTPS transistors is that the leakage current is large, which makes the driving current generated by the pixel circuit fluctuate greatly.
  • the transistor M1' is a driving transistor, and the voltage of the gate G' of the transistor M1' is saved by the capacitor Cst', but there are two leakage channels in the gate G', namely through the transistor M3' and the transistor M4'.
  • the current leaks in from the drain D' through the transistor M3', and the current leaks out from the reference voltage signal Vref through the transistor M4'. Due to the limitation of the potential difference of multiple nodes, it is difficult to completely offset the leakage current of the gate G' one in and one out, resulting in large fluctuations in the potential of the gate G', resulting in large fluctuations in the driving current of the transistor M1'.
  • the first improvement solution is to change the transistors of the two leakage channels into double-gate transistors.
  • Transistor M3' is equivalent to transistor M3-1' and transistor M3-2' connected in series
  • transistor M4' is equivalent to transistor M4-1' and transistor M4-2' connected in series.
  • the double-gate transistor has a lower leakage current, so the potential fluctuation of the gate G' can be reduced to a certain extent, but the leakage effect of this solution is not improved well.
  • the second improvement solution is to change the transistors of the two leakage channels into low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO) transistors.
  • the LTPO transistor Compared with the LTPS transistor, the LTPO transistor has the advantage of small leakage current, which can better solve the problem caused by the leakage current of the gate G'.
  • this solution adds an oxide thin film transistor process in the manufacturing process of the display panel, resulting in a substantial increase in process cost.
  • the third improvement scheme is to add transistor M8' in 7T1C circuit to obtain 8T1C circuit. Compared with the first improvement scheme, this scheme further improves the leakage problem of the gate G'.
  • this solution needs to increase the light emission control signal EMB' on the basis of the 7T1C circuit layout, so the layout of this solution is relatively complicated.
  • the above-mentioned pixel circuit cannot take into account various effects such as low power consumption, low leakage current, low cost and simple layout.
  • the pixel circuit includes: a driving module 100 , a data writing module 200 , a compensation module 300 , a leakage suppression module 400 and a first storage module 500 .
  • the driving module 100 includes a control terminal, a first terminal and a second terminal.
  • the driving module 100 includes a driving transistor MD. Taking the driving transistor MD as a P-type transistor as an example for illustration, the gate G of the driving transistor MD is the control terminal of the driving module 100, and the source S of the driving transistor MD is the second node N2, which is the first node N2 of the driving module 100.
  • the drain D of the driving transistor MD is the third node N3, that is, the second terminal of the driving module 100 . If the gate G and drain D of the drive transistor MD are turned on, the drive transistor MD forms a diode connection mode. At this time, when the source S is at a high level and the drain D is at a low level, the drive transistor MD is turned on, generating drive current.
  • the data writing module 200 includes a scan control terminal, a first terminal and a second terminal, the first terminal of the data writing module 200 is electrically connected to the first terminal of the drive module 100, and the second terminal of the data writing module 200 is connected to the data For the signal Data, the scan control terminal of the data writing module 200 is connected to the first scan signal S1.
  • the compensation module 300 includes a control terminal, a first terminal and a second terminal, the first terminal of the compensation module 300 is electrically connected to the second terminal of the drive module 100, the second terminal of the compensation module 300 is the first node N1, and the compensation module 300 The control terminal receives the first light emission control signal EMB.
  • the leakage suppression module 400 includes a control terminal, a first terminal and a second terminal, the first terminal of the leakage suppression module 400 is electrically connected to the control terminal (gate G) of the drive module 100, and the second terminal of the leakage suppression module 400 is connected to the compensation module
  • the second end (first node N1 ) of 300 is electrically connected, and the control end of leakage suppression module 400 is connected to the first light emission control signal EMB.
  • the first storage module 500 includes a first terminal and a second terminal, the first terminal of the first storage module 500 is electrically connected to the second terminal (first node N1) of the compensation module 300, and the second terminal of the first storage module 500 is connected to Input the reference voltage signal Vref.
  • the driving process of the pixel circuit shown in FIG. 5 includes an initialization phase, a data writing phase and a light emitting phase. Since both the leakage suppression module 400 and the compensation module 300 are connected to the first light emission control signal EMB, their switching states are the same.
  • the first light emission control signal EMB controls the leakage suppression module 400 and the compensation module 300 to be turned on during the initialization phase and the data writing phase.
  • the first storage module 500 is configured to keep the pressure difference constant when the first end of the first storage module 500 and the second end of the first storage module 500 form a pressure difference during the data writing phase and the light emitting phase.
  • the leakage suppression module 400 is connected to the compensation module 300 , and the second terminal of the driving module 100 is connected to the control terminal (gate G) of the driving module 100 .
  • the driving module 100 forms a diode connection mode.
  • the first terminal of the driving module 100 and the second terminal of the driving module 100 are respectively connected to different voltages, for example, the first terminal of the driving module 100 is connected to the first power supply signal to drive
  • the second end of the module 100 is connected to the second power supply signal
  • the driving module 100 is turned on, and a relatively large current flows, which helps to improve the performance of the driving module 100 while initializing the control terminal (gate G) of the driving module 100. Bias state, which is beneficial to improve the problem of afterimage.
  • the data writing module 200, the leakage suppression module 400 and the compensation module 300 are all turned on, and the data signal Data is written through the data writing module 200, the turned-on driving module 100, the compensation module 300 and the leakage suppression module 400. into the control terminal (gate G) of the driving module 100. Since the leakage suppression module 400 is in the on state, the potentials of the control terminal (gate G) of the driving module 100 and the first node N1 are equal and change synchronously.
  • a voltage difference is formed between the first terminal of the first storage module 500 and the second terminal of the first storage module 500, the second terminal of the first storage module 500 is a constant reference voltage signal Vref, and the second terminal of the first storage module 500
  • the first end stores the potential of the first node N1.
  • the potential of the control terminal (gate G) of the driving module 100 is constant, the potential of the first node N1 does not change any more, and a fixed voltage difference is formed between the first terminal and the second terminal of the first storage module 500 .
  • the data writing module 200, the leakage suppression module 400 and the compensation module 300 are all disconnected, and the first storage module 500 maintains the pressure difference between the first end of the first storage module 500 and the second end of the first storage module 500 to be the same. Change. And because the second terminal of the first storage module 500 is connected to the reference voltage signal Vref with a constant potential, the potential of the first terminal of the first storage module 500 (ie, the first node N1 ) remains at the potential during the data writing phase.
  • the control terminal (gate G) of the driving module 100 is also maintained at the potential during the data writing phase, therefore, the potentials of the first end of the leakage suppression module 400 and the second end of the leakage suppression module 400 remain equal, thereby reducing leakage
  • the leakage current of the suppression module 400 suppresses the leakage current of the control terminal (gate G) of the driving module 100 .
  • the embodiment of the present application sets the leakage suppression module 400 between the control terminal (gate G) of the driving module 100 and the second terminal (first node N1) of the compensation module 300, and sets the first storage module 500 It is located between the reference voltage signal Vref and the second terminal (the first node N1 ) of the compensation module 300 .
  • the control terminal (grid G) of the driving module 100 is provided with only one leakage current channel, which connects the control terminal of the driving module 100 and the second terminal of the driving module 100, and the leakage current controlled by the channel is controlled by the first light emission control signal.
  • the suppression module 400 is formed with the compensation module 300 .
  • the leakage suppression module 400 Only when the potential of the second terminal (first node N1 ) of the compensation module 300 drifts greatly, the leakage suppression module 400 will generate a large leakage current, and the potential of the control terminal (gate G) of the driving module 100 will drift. And in the embodiment of the present application, the potential of the control terminal (gate G) of the driving module 100 is close to the potential of the second terminal (first node N1) of the compensation module 300, so that the leakage current of the leakage suppression module 400 is small, reducing Therefore, the potential of the control terminal (gate G) of the driving module 100 is more stable, a high current retention rate is realized, and the flickering phenomenon of the display panel is improved.
  • the pixel circuit provided by the embodiment of the present application can be connected to different voltages at the first end of the driving module 100 and the second end of the driving module 100 during the initialization phase, for example, the driving module The first end of 100 is connected to the first power supply signal, the second end is connected to the second power supply signal, the driving module 100 is turned on, and a large current flows, and the control terminal (gate G) of the driving module 100 is initialized At the same time, it is beneficial to improve the bias state of the driving module 100, thereby helping to improve the problem of image sticking.
  • the following describes the case where the first terminal and the second terminal of the driving module 100 are respectively connected with different voltages and the driving module 100 generates a relatively large current.
  • the pixel circuit further includes: a first light emission control module 700 , a second light emission control module 800 and an initialization module 900 .
  • the first lighting control module 700 includes a control terminal, a first terminal and a second terminal.
  • the first terminal of the first lighting control module 700 is electrically connected to the first terminal (second node N2) of the driving module 100.
  • the first lighting control module The second terminal of 700 is connected to the first power supply signal VDD, and the control terminal of the first light emission control module 700 is connected to the second light emission control signal EM.
  • the second lighting control module 800 includes a control terminal, a first terminal and a second terminal.
  • the control terminal of the second lighting control module 800 is connected to the second lighting control signal EM.
  • the first terminal of the second lighting control module 800 is connected to the driving module 100
  • the second end (third node N3) of the second light emitting control module 800 is electrically connected to the second end of the second light emitting control module 800 and the light emitting device OLED is electrically connected.
  • the light emitting device OLED includes an anode and a cathode.
  • the second end of the second light emission control module 800 is electrically connected to the anode of the light emitting device OLED, and the cathode of the light emitting device OLED is connected to the second power signal VSS.
  • the initialization module 900 includes a control terminal, a first terminal and a second terminal.
  • the control terminal of the initialization module 900 is connected to the second scan signal S2, and the first terminal of the initialization module 900 is electrically connected to the second terminal of the second lighting control module 800.
  • the second terminal of the initialization module 900 is connected with an initialization signal.
  • the reference voltage signal Vref is multiplexed as an initialization signal.
  • the leakage suppression module 400 and the compensation module 300 are turned on, and the driving module 100 forms a diode connection mode.
  • the first lighting control module 700, the second lighting control module 800 and the initialization module 900 are turned on at the same time.
  • the first power supply signal VDD is written into the first end (second node N2) of the driving module 100 through the first light emission control module 700
  • the second power supply signal VSS is written into the second end (the second node N2) of the driving module 100 through the second light emission control module 800.
  • the driving module 100 is turned on to generate a large current.
  • the current flows out through the initialization module 900 and does not flow through the light-emitting device OLED, so that the anode of the light-emitting device OLED can be initialized, and the light-emitting device OLED is prevented from being turned on during the initialization stage.
  • the pixel circuit provided by the embodiment of the present application realizes that the driving module is controlled to generate a large current during the initialization stage, and the generated large current flows out through the initialization module 900, and is used to control the control terminal (gate G) of the driving module 100 and emit light. While the anode of the device OLED is being initialized, it is beneficial to improve the bias state of the driving module 100, thereby helping to improve the problem of image sticking.
  • the pixel circuit further includes a second storage module 600 .
  • the second storage module 600 includes a first terminal and a second terminal, the first terminal of the second storage module 600 is electrically connected to the control terminal (gate G) of the drive module 100, and the second terminal of the second storage module 600 is connected to the second terminal of the second storage module 600.
  • the second storage module 600 has the function of storing potential, and is configured to keep the potential of the control terminal of the driving module 100 unchanged during the light-emitting phase.
  • the first storage module 500 and the second storage module 600 cooperate with each other, the first storage module 500 maintains the potential of the first node N1 unchanged, and the second storage module 600 maintains the potential of the control terminal (gate G) of the driving module 100 remain unchanged, so that the potentials of the first node N1 and the gate G remain equal, which further helps to reduce the leakage of the control terminal (gate G) of the driving module 100 , achieve a high current retention rate, and improve the flicker phenomenon of the display panel.
  • the embodiment of the present application describes the arrangement of transistors in multiple modules.
  • the compensation module 300 includes a first transistor M1.
  • the first pole of the first transistor M1 is electrically connected to the second terminal (third node N3) of the driving module 100, and the second pole of the first transistor M1 is electrically connected to the second terminal (first node N1) of the leakage suppression module 400.
  • the gate of the first transistor M1 is connected to the first light emission control signal EMB.
  • the compensation module 300 only includes one transistor, and the circuit structure is simple and easy to realize.
  • the leakage suppression module 400 includes a second transistor M2 .
  • the first pole of the second transistor M2 is electrically connected to the control terminal (gate G) of the driving module 100, the second pole of the second transistor M2 is electrically connected to the second terminal (first node N1) of the compensation module 300, and the second The gate of the transistor M2 is connected to the first light emission control signal EMB.
  • the leakage suppression module 400 only includes one transistor, and the circuit structure is simple and easy to implement.
  • the data writing module 200 includes a third transistor M3 .
  • the first pole of the third transistor M3 is electrically connected to the first end (the second node N2) of the driving module 100, the second pole of the third transistor M3 is connected to the data signal Data, and the gate of the third transistor M3 is connected to the first node N2.
  • the data writing module 200 only includes one transistor, so that the number of transistors required by the pixel circuit is small.
  • the first light emission control module 700 includes a fifth transistor M5 .
  • the first pole of the fifth transistor M5 is electrically connected to the first terminal (second node N2) of the driving module 100, the second pole of the fifth transistor M5 is connected to the first power supply signal VDD, and the gate of the fifth transistor M5 is connected to The second light emission control signal EM.
  • the first lighting control module 700 only includes one transistor, and the circuit structure is simple and easy to realize.
  • the second light emission control module 800 includes a sixth transistor M6 .
  • the first pole of the sixth transistor M6 is electrically connected to the second terminal of the driving module 100, the second pole of the sixth transistor M6 is electrically connected to the light emitting device OLED, and the gate of the sixth transistor M6 is connected to the second light emission control signal EM.
  • the second lighting control module 800 only includes one transistor, and the circuit structure is simple and easy to realize.
  • the initialization module 900 includes a seventh transistor M7 .
  • the first pole of the seventh transistor M7 is electrically connected to the second terminal of the second light emission control module 800, the second pole of the seventh transistor M7 is connected to the initialization signal, and the gate of the seventh transistor M7 is connected to the second scanning signal S2.
  • the setting initialization module 900 includes only one transistor, and the circuit structure is simple and easy to implement.
  • the first storage module 500 includes a first capacitor C1.
  • the first pole of the first capacitor C1 is electrically connected to the second terminal (first node N1 ) of the compensation module 300 , and the second pole of the first capacitor C1 is connected to the reference voltage signal Vref.
  • the first storage module 500 only includes one capacitor, and the circuit structure is simple and easy to implement.
  • the second storage module 600 includes a second capacitor C2.
  • a first pole of the second capacitor C2 is electrically connected to the control terminal (gate G) of the driving module 100 , and a second pole of the second capacitor C2 is connected to the first power supply signal VDD.
  • the second storage module 600 includes only one capacitor, and the circuit structure is simple and easy to realize.
  • FIG. 6 exemplarily shows that all the transistors in the pixel circuit are P-type transistors manufactured by LTPS process, which is not a limitation of the present application. In other embodiments, part or all of the transistors in the pixel circuit can also be set as N-type transistors, which can be set according to needs in practical applications.
  • FIG. 6 exemplarily shows that both the first transistor M1 and the second transistor M2 are single-gate transistors, which is not a limitation of the present application.
  • the first transistor M1 and/or the second transistor M2 can also be set as double-gate transistors.
  • the data writing module 200 also includes a synchronous control terminal, and the synchronous control terminal is connected to the first light emission control signal EMB.
  • the data signal Data is transmitted under the common control of the control signal EMB.
  • the data writing module 200 further includes a fourth transistor M4.
  • the gate of the fourth transistor M4 is connected to the first light emission control signal EMB; the fourth transistor M4 is connected in series between the first pole of the third transistor M3 and the first terminal (the second node N2 ) of the driving module 100 .
  • the reason for such setting in the embodiment of the present application is to reduce the number of via holes in the layout without affecting other functions of the pixel circuit.
  • the layout of the pixel circuit includes a first scan line extending along the first direction X and located on the first metal layer, a first light emission control signal line, a second light emission control signal line and a second scan line.
  • the first scan line transmits a first scan signal S1
  • the first light emission control signal line transmits a first light emission control signal EMB
  • the second light emission control signal line transmits a second light emission control signal EM
  • the second scan line transmits a second scan signal S2.
  • the layout of the pixel circuit further includes a reference voltage signal line extending along the first direction X and located on the second metal layer, and the reference voltage signal line transmits a reference voltage signal Vref.
  • the layout of the pixel circuit further includes a data line and a first power signal line extending along the second direction Y and located on the third metal layer.
  • the data line transmits a data signal Data
  • the first power signal line transmits a first power signal VDD.
  • the layout of the pixel circuit also includes a semiconductor pattern on the active layer, and a transistor is formed at a position where the semiconductor pattern intersects with a plurality of signal lines on the first metal layer.
  • the S-shaped part of the semiconductor pattern intersects with the first metal layer to form the driving transistor MD.
  • a position where the semiconductor pattern crosses the first scan line forms a third transistor M3.
  • the portion where the first scan line crosses the semiconductor pattern is the gate of the third transistor M3, that is, the gate of the third transistor M3 is electrically connected to the first scan line.
  • the parts of the semiconductor pattern on both sides of the first scanning line are the first pole and the second pole of the third transistor, the second pole of the third transistor M3 is connected to the data line through the via hole 110, the first pole of the third transistor M3 is connected to the data line
  • the second electrode of the fourth transistor M4 is electrically connected.
  • a position where the semiconductor pattern crosses the first light emission control signal line forms a fourth transistor M4, a second transistor M2, and a first transistor M1.
  • the gate of the fourth transistor M4 is electrically connected to the first light-emitting control signal line
  • the first pole of the fourth transistor M4 is electrically connected to the first pole of the driving transistor MD
  • the second pole of the fourth transistor M4 is electrically connected to the third transistor M3.
  • the first pole is electrically connected.
  • the gate of the first transistor M1 is electrically connected to the first light-emitting control signal line
  • the first electrode of the first transistor M1 is electrically connected to the second electrode of the driving transistor MD
  • the second electrode of the first transistor M1 is electrically connected to the second electrode of the second transistor M2.
  • the second pole is electrically connected.
  • the gate of the second transistor M2 is electrically connected to the first light emission control signal line
  • the first pole of the second transistor M2 is connected to the gate of the driving transistor MD through the via hole 110 and the connection line 120
  • the second pole of the second transistor M2 It is electrically connected with the second electrode of the first transistor M1.
  • the connection line 120 is located on the third metal layer.
  • a fifth transistor M5 and a sixth transistor M6 are formed at positions where the semiconductor pattern crosses the second light emission control signal line.
  • the gate of the fifth transistor M5 is electrically connected to the second light emission control signal line
  • the first pole of the fifth transistor M5 is electrically connected to the first pole of the driving transistor MD
  • the second pole of the fifth transistor M5 is connected to the The first power signal line.
  • the gate of the sixth transistor M6 is electrically connected to the second light-emitting control signal line
  • the first pole of the sixth transistor M6 is electrically connected to the second pole of the drive transistor MD
  • the second pole of the sixth transistor M6 is connected to the light-emitting through the via hole 110.
  • the anode 130 of the device is electrically connected.
  • a position where the semiconductor pattern crosses the second scan line forms a seventh transistor M7.
  • the gate of the seventh transistor M7 is electrically connected to the second scanning line
  • the first pole of the seventh transistor M7 is electrically connected to the second pole of the sixth transistor M6, and the second pole of the seventh transistor M7 passes through the via hole 110 and the connecting line 120 is connected to the reference voltage signal line.
  • the gate of the drive transistor MD is used as the plate of the first pole of the second capacitor C2, and the plate of the second pole of the second capacitor C2 can be arranged on the third metal layer, and directly electrically connected to the first power signal line;
  • the plate of the second pole of the capacitor C2 can also be disposed on the second metal layer, and be electrically connected to the first power signal line by setting the via hole 110 .
  • the plate of the first pole of the first capacitor C1 is located on the second metal layer, and is connected to the second pole of the first transistor M1 through the via hole 110 and the connection line 120 .
  • the plate of the second pole of the first capacitor C1 is located on the third metal layer, and is connected to the reference voltage signal line through the via hole 110 and the connection line 120 .
  • the plate of the first pole of the first capacitor C1 is located on the third metal layer, and is connected to the second pole of the first transistor M1 through the via hole 110 and the connection line 120 .
  • the plate of the second pole of the first capacitor C1 is located on the second metal layer and is directly connected to the reference voltage signal line.
  • the embodiment of the present application provides a pixel circuit with an 8T2C structure. From the perspective of the layout, comparing Figure 2 and Figure 8, compared with the 7T1C pixel circuit of the related art, the 8T2C pixel circuit provided by the embodiment of the present application has no Add a new signal line. Comparing Fig. 4 and Fig. 8, compared with the 8T1C circuit of the related art, the 8T2C pixel circuit provided by the embodiment of the present application reduces a signal line extending along the first direction X, therefore, the embodiment of the present application is beneficial to save wiring space, It is conducive to the high number of pixels per inch (Pixels Per Inch, PPI) design.
  • PPI Pixel Per Inch
  • the embodiment of the present application at least includes the following effects:
  • the embodiment of the present application also provides a display panel.
  • the display panel includes the pixel circuit provided by any embodiment of the present application, which has corresponding effects, and will not be repeated here.
  • the embodiment of the present application also provides a driving method for a pixel circuit, which is applicable to the pixel circuit provided in any embodiment of the present application, and has corresponding effects.
  • the driving method of the pixel circuit includes:
  • the first light emission control signal EMB controls the compensation module 300 and the leakage suppression module 400 to be turned on, so that when the first terminal of the driving module 100 and the second terminal of the driving module 100 are respectively connected to different voltages, Turn on the driving module 100 for initialization.
  • the first light emission control signal EMB controls the compensation module 300 and the leakage suppression module 400 to be turned on
  • the first scan signal S1 controls the data writing module 200 to be turned on, so that the data signal Data is written into the driving module 100
  • the potentials of the first terminal of the first storage module 500 and the control terminal of the drive module 100 are equal, and a voltage difference is formed between the first terminal of the first storage module 500 and the second terminal of the first storage module 500 .
  • the first lighting control signal EMB controls the compensation module 300 and the leakage suppression module 400 to be disconnected
  • the first scan signal S1 controls the data writing module 200 to be disconnected
  • the first storage module 500 maintains the first storage module 500
  • the voltage difference between the first terminal and the second terminal of the first storage module 500 is constant, so that the potentials of the first terminal and the second terminal of the leakage suppression module 400 are equal.
  • the initialization phase includes a first initialization sub-phase and a second initialization sub-phase.
  • the first light emission control signal EMB controls the conduction of the compensation module 300 and the leakage suppression module 400
  • the second light emission control signal EM controls the conduction of the first light emission control module 700 and the second light emission control module 800
  • the second The scan signal S2 controls the initialization module 900 to turn on, so that the driving module 100 is turned on, and the generated driving current flows out through the initialization module 900 .
  • the driving module 100 is turned on, and a large current flows, which helps to improve the bias state of the driving module 100 while initializing the control terminal (gate G) of the driving module 100 , thereby helping to improve the afterimage problem.
  • the second light emission control signal EM controls the first light emission control module 700 and the second light emission control module 800 to be disconnected; the reference voltage signal Vref continues to initialize the anode of the light emitting device OLED.
  • FIG. 10 is a schematic diagram of a driving sequence of a pixel circuit provided by an embodiment of the present application. The driving process of the pixel circuit will be described below with reference to FIG. 7 and FIG. 10 .
  • the second scan signal S2, the first light emission control signal EMB and the second light emission control signal EM are at low level, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned on, the gate G of the driving transistor MD and the anode of the light-emitting device OLED are simultaneously reset, the gate G of the driving transistor MD is written into the reference voltage signal Vref, and at this time, the driving transistor MD has a large current flow
  • the second initialization sub-phase t12 different from the first initialization phase t11, the second light emission control signal EM changes from a low level to a high level, the fifth transistor M5 and the sixth transistor M6 are turned off, and the driving transistor MD does not Then generate a large current.
  • the potential of the gate G is maintained by the first capacitor C1, and the reference voltage signal Vref continues to initialize the anode of the light emitting device OLED.
  • the second scan signal S2 is at a high level, and the seventh transistor M7 is turned off.
  • the first scan signal S1 and the first light emission control signal EMB are at low level
  • the third transistor M3, the fourth transistor M4, the first transistor M1 and the second transistor M2 are turned on
  • the data signal Data passes through the third transistor M3, the fourth The transistor M4, the driving transistor MD, the first transistor M1 and the second transistor M2 write into the gate G and the first node N1, that is, write into the first capacitor C1 and the second capacitor C2. Since the reference voltage signal Vref is lower than the voltage of the data signal Data, the potential of the gate G gradually rises during the data writing phase t2.
  • the first scanning signal S1 and the first light emitting control signal EMB are at high level, and the third transistor M3, the fourth transistor M4, the first transistor M1 and the second transistor M2 are turned off.
  • the second light emitting control signal EM is at low level, the fifth transistor M5 and the sixth transistor M6 are turned on, and the light emitting device OLED is turned on.
  • the first capacitor C1 and the second capacitor C2 lock the potentials of the first node N1 and the gate G. Since the potentials of the first node N1 and the gate G are very close, the leakage current of the second transistor M2 is small, so the potential of the gate G is more stable, and the problem of flickering of the display panel is improved.
  • stage t0 is an initial state, which can be regarded as the light-emitting stage of the previous frame.
  • FIG. 10 exemplarily shows that a first transition phase is also included between the second initialization sub-phase t12 and the data writing phase t2.
  • the second scan signal S2 changes from low level to high level
  • the first light emission control signal EMB changes from low level to high level, which is not a limitation of the present application.
  • the first transition stage may not be set, the second scanning signal S2 changes from low level to high level in the data writing stage t2, and the first light emission control signal EMB Phase t2 remains low.
  • FIG. 10 exemplarily shows that a second transition phase is also included between the data writing phase t2 and the light emitting phase t3.
  • the first scan signal S1 and the first light emission control signal EMB change from low level to high level, which is not a limitation of the present application.
  • the second transition phase may not be provided, and the first scanning signal S1 and the first light-emitting control signal EMB change from low level to high level in the light-emitting phase t3.

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Abstract

本申请实施例公开了一种像素电路及其驱动方法、显示面板。像素电路包括：驱动模块、数据写入模块、补偿模块、漏电抑制模块和第一存储模块。补偿模块的第一端与驱动模块的第二端电连接，补偿模块的控制端接入第一发光控制信号；漏电抑制模块的第一端与驱动模块的控制端电连接，漏电抑制模块的第二端与补偿模块的第二端电连接，漏电抑制模块的控制端接入第一发光控制信号；第一存储模块的第一端与补偿模块的第二端电连接，第一存储模块的第二端接入参考电压信号；第一存储模块设置为当第一存储模块的第一端和第一存储模块的第二端形成压差时，维持该压差不变。

Description

像素电路及其驱动方法、显示面板
本申请要求在2021年09月18日提交中国专利局、申请号为202111100960.1的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如涉及一种像素电路及其驱动方法、显示面板。
背景技术
随着显示技术的不断发展，人们对显示面板的要求也越来越高，显示面板朝着高显示品质、多种帧频模式和低功耗的方向发展。显示面板的电量消耗主要在于像素电路和发光器件。对于像素电路来说，可以通过降低帧频来降低功耗，然而当显示面板的刷新频率降低时，像素电路存在漏电的问题，致使显示画面出现闪烁的现象，影响了显示面板的显示品质。
发明内容
本申请实施例提供一种像素电路及其驱动方法、显示面板，以改善低刷新频率下像素电路的漏电问题，从而实现兼顾低功耗和高显示品质的效果。
本申请实施例提供了如下技术方案：
一种像素电路，包括：
驱动模块，包括控制端、第一端和第二端；
数据写入模块，包括扫描控制端、第一端和第二端，所述数据写入模块的第一端与所述驱动模块的第一端电连接，所述数据写入模块的第二端接入数据信号，所述数据写入模块的扫描控制端接入第一扫描信号；
补偿模块，包括控制端、第一端和第二端，所述补偿模块的第一端与所述驱动模块的第二端电连接，所述补偿模块的控制端接入第一发光控制信号；
漏电抑制模块，包括控制端、第一端和第二端，所述漏电抑制模块的第一端与所述驱动模块的控制端电连接，所述漏电抑制模块的第二端与所述补偿模块的第二端电连接，所述漏电抑制模块的控制端接入所述第一发光控制信号；所述漏电抑制模块与所述补偿模块在初始化阶段和数据写入阶段导通；
第一存储模块，包括第一端和第二端，所述第一存储模块的第一端与所述 补偿模块的第二端电连接，所述第一存储模块的第二端接入参考电压信号；所述第一存储模块设置为在所述数据写入阶段和发光阶段，当所述第一存储模块的第一端和所述第一存储模块的第二端形成压差时，维持该压差不变。
本发明申请还提供了一种显示面板，包括：如本发明申请任意实施例所述的像素电路。
本申请还提供了一种像素电路的驱动方法，适用于本申请任意实施例所提供的像素电路，所述驱动方法包括：
在初始化阶段，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模块导通，以在所述驱动模块的第一端和所述驱动模块的第二端分别接入不同电压的情况下，使所述驱动模块导通，进行初始化；
在数据写入阶段，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模块导通，所述第一扫描信号控制所述数据写入模块导通，以使所述数据信号写入所述驱动模块的控制端；所述第一存储模块的第一端和所述驱动模块的控制端的电位相等，且所述第一存储模块的第一端和所述第一存储模块的第二端形成压差；
在发光阶段，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模块断开，所述第一扫描信号控制所述数据写入模块断开，所述第一存储模块维持所述第一存储模块的第一端和所述第一存储模块的第二端的压差不变，以使所述漏电抑制模块的第一端和所述漏电抑制模块的第二端的电位相等。
本申请实施例设置漏电抑制模块位于驱动模块的控制端和补偿模块的第二端之间，以及设置第一存储模块位于参考电压信号和补偿模块的第二端之间。这样，驱动模块的控制端只设置有一个漏电流通道，该通道连接驱动模块的控制端和驱动模块的第二端，该通道由第一发光控制信号控制的漏电抑制模块与补偿模块构成。只有当补偿模块的第二端的电位大幅漂移后漏电抑制模块才会产生较大的漏电流，驱动模块的控制端电位才会漂移。并且在本申请实施例中，驱动模块的控制端电位与补偿模块的第二端的电位接近，使得漏电抑制模块的漏电流较小，减少了这个唯一漏电通道的漏电流大小，因此驱动模块的控制端的电位更加稳定，实现了高电流保持率，显示面板的闪烁现象得到改善。
本申请实施例对驱动模块的控制端的复位路径和复位方法进行了突破性的改进，第一存储模块和漏电抑制模块组合，有效地抑制了驱动模块的控制端的漏电，有利于实现低帧频下的高质量显示，从而有利于实现兼顾低功耗和高显示品质的效果。
在实现上述效果的同时，本申请实施例所提供的像素电路能够在初始化阶 段，在驱动模块的第一端和驱动模块的第二端分别接入不同电压的情况下，例如，驱动模块的第一端接入第一电源信号，第二端接入第二电源信号，驱动模块导通，有较大电流流过，在对驱动模块的控制端进行初始化的同时有利于改善驱动模块的偏压状态，从而有利于改善残影的问题。
附图说明
图1为一种像素电路的电路示意图；
图2为图1中所示像素电路的版图示意图；
图3为另一种像素电路的电路示意图；
图4为图3中所示像素电路的版图示意图；
图5为本申请实施例提供的一种像素电路的结构示意图；
图6为本申请实施例提供的另一种像素电路的结构示意图；
图7为本申请实施例提供的又一种像素电路的结构示意图；
图8为图7中所示像素电路的版图示意图；
图9为本申请实施例提供的一种像素电路的驱动方法的流程示意图；
图10为本申请实施例提供的一种像素电路的驱动时序示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
参见图1和图2，该像素电路为7T1C结构。像素电路包括晶体管M1’、晶体管M2’、晶体管M3’、晶体管M4’、晶体管M5’、晶体管M6’、晶体管M7’和电容Cst’。示例性地，所有晶体管均为P型晶体管，采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)工艺制作而成。LTPS晶体管具有迁移率高、驱动能力强和工艺成本低的优点，被广泛应用于像素电路中，但是LTPS晶体管不足之处是漏电流较大，使得像素电路产生的驱动电流波动较大。这是因为，晶体管M1’为驱动晶体管，晶体管M1’的栅极G’的电压由电容Cst’保存，但栅极G’存在两个漏电通道，即经过晶体管M3’和晶体管M4’漏电。一般经过晶体管M3’由漏极D’漏进电流，经过晶体管M4’由参考电压信号Vref漏出电流。由于受多个节点电位的差异限制，栅极G’的漏电流一进一出难以完全抵消，导致栅极G’的电位出现较大波动，导致了晶体管M1’ 的驱动电流出现较大波动。
为解决该技术问题，继续参见图1，第一种改进方案为，将两漏电通道的晶体管改为双栅晶体管。晶体管M3’等效为串联的晶体管M3-1’和晶体管M3-2’，晶体管M4’等效为串联的晶体管M4-1’和晶体管M4-2’。相比于单栅晶体管，双栅晶体管具有更低的漏电流，因此，能够在一定程度上降低栅极G’的电位波动，但是该方案的漏电效果改善不佳。
第二种改进方案为，将两漏电通道的晶体管改为低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)晶体管。相比于LTPS晶体管，LTPO晶体管具有漏电流小的优势，能够较好地解决栅极G’的漏电流带来的问题。但是该方案在显示面板的制备工艺中增加了氧化物薄膜晶体管的工艺，导致了工艺成本大幅上升。
参见图3和图4，第三种改进方案为在7T1C电路中加入晶体管M8’得到8T1C电路。相比于第一种改进方案，该方案进一步改善了栅极G’的漏电问题。但是，通过对比图2和图4可以看出，该方案在7T1C电路版图的基础上，需要增加发光控制信号EMB’，因此，该方案的版图布局较为复杂。
综上所述，上述像素电路无法兼顾低功耗、低漏电、低成本和版图布局简单等多种效果。
本申请实施例提供了一种像素电路。参见图5，像素电路包括：驱动模块100、数据写入模块200、补偿模块300、漏电抑制模块400和第一存储模块500。驱动模块100包括控制端、第一端和第二端。可选地，驱动模块100包括驱动晶体管MD。以驱动晶体管MD为P型晶体管为例进行说明，驱动晶体管MD的栅极G即为驱动模块100的控制端，驱动晶体管MD的源极S为第二节点N2，即驱动驱动模块100的第一端，驱动晶体管MD的漏极D为第三节点N3，即驱动驱动模块100的第二端。若将驱动晶体管MD的栅极G和漏极D导通，驱动晶体管MD构成二极管连接方式，此时当源极S为高电平，漏极D为低电平，驱动晶体管MD导通，产生驱动电流。
数据写入模块200包括扫描控制端、第一端和第二端，数据写入模块200的第一端与驱动模块100的第一端电连接，数据写入模块200的第二端接入数据信号Data，数据写入模块200的扫描控制端接入第一扫描信号S1。补偿模块300包括控制端、第一端和第二端，补偿模块300的第一端与驱动模块100的第二端电连接，补偿模块300的第二端为第一节点N1，补偿模块300的控制端接入第一发光控制信号EMB。漏电抑制模块400包括控制端、第一端和第二端，漏电抑制模块400的第一端与驱动模块100的控制端(栅极G)电连接，漏电抑制模块400的第二端与补偿模块300的第二端(第一节点N1)电连接，漏电 抑制模块400的控制端接入第一发光控制信号EMB。第一存储模块500包括第一端和第二端，第一存储模块500的第一端与补偿模块300的第二端(第一节点N1)电连接，第一存储模块500的第二端接入参考电压信号Vref。
图5所示的像素电路的驱动过程包括初始化阶段、数据写入阶段和发光阶段。由于漏电抑制模块400与补偿模块300均接入第一发光控制信号EMB，因此，两者的开关状态相同。第一发光控制信号EMB控制漏电抑制模块400与补偿模块300在初始化阶段和数据写入阶段导通。第一存储模块500设置为在数据写入阶段和发光阶段，当第一存储模块500的第一端和第一存储模块500的第二端形成压差时，维持该压差不变。
在初始化阶段，漏电抑制模块400与补偿模块300导通，驱动模块100的第二端和驱动模块100的控制端(栅极G)导通。驱动模块100构成二极管连接方式，在驱动模块100的第一端和驱动模块100的第二端分别接入不同电压的情况下，例如，驱动模块100的第一端接入第一电源信号，驱动模块100的第二端接入第二电源信号，驱动模块100导通，有较大电流流过，在对驱动模块100的控制端(栅极G)进行初始化的同时有利于改善驱动模块100的偏压状态，从而有利于改善残影的问题。
在数据写入阶段，数据写入模块200、漏电抑制模块400与补偿模块300均导通，数据信号Data经由数据写入模块200、导通的驱动模块100、补偿模块300和漏电抑制模块400写入驱动模块100的控制端(栅极G)。由于漏电抑制模块400处于导通状态，因此，驱动模块100的控制端(栅极G)和第一节点N1的电位相等，同步变化。与此同时，第一存储模块500的第一端和第一存储模块500的第二端形成压差，第一存储模块500的第二端为恒定的参考电压信号Vref，第一存储模块500的第一端存储第一节点N1的电位。当驱动模块100的控制端(栅极G)的电位恒定时，第一节点N1的电位也不再变化，第一存储模块500的第一端和第二端形成固定的压差。
在发光阶段，数据写入模块200、漏电抑制模块400与补偿模块300均断开，第一存储模块500维持第一存储模块500的第一端和第一存储模块500的第二端的压差不变。且由于第一存储模块500的第二端接入电位恒定的参考电压信号Vref，因此第一存储模块500的第一端(即第一节点N1)的电位保持为数据写入阶段时的电位。驱动模块100的控制端(栅极G)也保持为数据写入阶段时的电位，因此，漏电抑制模块400的第一端和漏电抑制模块400的第二端的电位保持相等，从而减小了漏电抑制模块400的漏电流，抑制了驱动模块100的控制端(栅极G)的漏电。
由上述分析可见，本申请实施例设置漏电抑制模块400位于驱动模块100 的控制端(栅极G)和补偿模块300的第二端(第一节点N1)之间，以及设置第一存储模块500位于参考电压信号Vref和补偿模块300的第二端(第一节点N1)之间。这样，驱动模块100的控制端(栅极G)只设置有一个漏电流通道，该通道连接驱动模块100的控制端和驱动模块100的第二端，该通道由第一发光控制信号控制的漏电抑制模块400与补偿模块300构成。只有当补偿模块300的第二端(第一节点N1)的电位大幅漂移后漏电抑制模块400才会产生较大的漏电流，驱动模块100的控制端(栅极G)电位才会漂移。并且在本申请实施例中，驱动模块100的控制端(栅极G)电位与补偿模块300的第二端(第一节点N1)的电位接近，使得漏电抑制模块400的漏电流较小，减少了这个唯一漏电通道的漏电流大小，因此驱动模块100的控制端(栅极G)的电位更加稳定，实现了高电流保持率，显示面板的闪烁现象得到改善。
本申请实施例对驱动模块100的控制端(栅极G)的复位路径和复位方法进行了突破性的改进，采用第一存储模块500取代了复位驱动模块100的控制端(栅极G)的双栅晶体管，且第一存储模块500和漏电抑制模块400组合，有效地抑制了驱动模块100的控制端(栅极G)的漏电，有利于实现低帧频下的高质量显示，从而有利于实现兼顾低功耗和高显示品质的效果。
在实现上述效果的同时，本申请实施例所提供的像素电路能够在初始化阶段，在驱动模块100的第一端和驱动模块100的第二端分别接入不同电压的情况下，例如，驱动模块100的第一端接入第一电源信号，第二端接入第二电源信号，驱动模块100导通，有较大电流流过，在对驱动模块100的控制端(栅极G)进行初始化的同时有利于改善驱动模块100的偏压状态，从而有利于改善残影的问题。
下面对驱动模块100的第一端和第二端分别接入不同电压、驱动模块100产生较大电流的情况进行说明。
继续参见图5，在上述实施例的基础上，可选地，像素电路还包括：第一发光控制模块700、第二发光控制模块800和初始化模块900。第一发光控制模块700包括控制端、第一端和第二端，第一发光控制模块700的第一端与驱动模块100的第一端(第二节点N2)电连接，第一发光控制模块700的第二端接入第一电源信号VDD，第一发光控制模块700的控制端接入第二发光控制信号EM。第二发光控制模块800包括控制端、第一端和第二端，第二发光控制模块800的控制端接入第二发光控制信号EM，第二发光控制模块800的第一端与驱动模块100的第二端(第三节点N3)电连接，第二发光控制模块800的第二端与发光器件OLED电连接。发光器件OLED包括阳极和阴极。示例性地，第二发光控制模块800的第二端与发光器件OLED的阳极电连接，发光器件OLED的阴 极接入第二电源信号VSS。
初始化模块900包括控制端、第一端和第二端，初始化模块900的控制端接入第二扫描信号S2，初始化模块900的第一端与第二发光控制模块800的第二端电连接，初始化模块900的第二端接入初始化信号。可选地，参考电压信号Vref复用为初始化信号。
在初始化阶段，漏电抑制模块400和补偿模块300导通，驱动模块100构成二极管连接方式。以及，第一发光控制模块700、第二发光控制模块800和初始化模块900同时导通。第一电源信号VDD经第一发光控制模块700写入驱动模块100的第一端(第二节点N2)，第二电源信号VSS经第二发光控制模块800写入驱动模块100的第二端(第三节点N3)，驱动模块100导通，产生大电流。该电流通过初始化模块900流出，不会流经发光器件OLED，从而既能够对发光器件OLED的阳极进行初始化，又避免了发光器件OLED在初始化阶段导通。
由此可见，本申请实施例提供的像素电路实现了，在初始化阶段控制驱动模块产生大电流，产生的大电流经初始化模块900流出，在对驱动模块100的控制端(栅极G)和发光器件OLED的阳极进行初始化的同时，有利于改善驱动模块100的偏压状态，从而有利于改善残影的问题。
继续参见图5，在上述实施例的基础上，可选地，像素电路还包括第二存储模块600。第二存储模块600包括第一端和第二端，第二存储模块600的第一端与驱动模块100的控制端(栅极G)电连接，第二存储模块600的第二端接入第一电源信号VDD。第二存储模块600具有存储电位的功能，设置为在发光阶段维持驱动模块100的控制端的电位不变。这样，第一存储模块500和第二存储模块600相互配合，第一存储模块500维持第一节点N1的电位不变，第二存储模块600维持驱动模块100的控制端(栅极G)的电位不变，使得第一节点N1和栅极G的电位保持相等，从而进一步有利于降低驱动模块100的控制端(栅极G)的漏电，实现高电流保持率，改善显示面板的闪烁现象。
参见图6，在上述实施例的基础上，本申请实施例对多个模块中晶体管的设置方式进行了说明。
在本申请的一种实施方式中，可选地，补偿模块300包括第一晶体管M1。第一晶体管M1的第一极与驱动模块100的第二端(第三节点N3)电连接，第一晶体管M1的第二极与漏电抑制模块400的第二端(第一节点N1)电连接，第一晶体管M1的栅极接入第一发光控制信号EMB。本申请实施例设置补偿模块300仅包括一个晶体管，电路结构简单，易于实现。
继续参见图6，在本申请的一种实施方式中，可选地，漏电抑制模块400包括第二晶体管M2。第二晶体管M2的第一极与驱动模块100的控制端(栅极G)电连接，第二晶体管M2的第二极与补偿模块300的第二端(第一节点N1)电连接，第二晶体管M2的栅极接入第一发光控制信号EMB。本申请实施例设置漏电抑制模块400仅包括一个晶体管，电路结构简单，易于实现。
继续参见图6，在本申请的一种实施方式中，可选地，数据写入模块200包括第三晶体管M3。第三晶体管M3的第一极与驱动模块100的第一端(第二节点N2)电连接，第三晶体管M3的第二极接入数据信号Data，第三晶体管M3的栅极接入第一扫描信号S1。本申请实施例设置数据写入模块200仅包括一个晶体管，使得像素电路所需要的晶体管的数量较少。
继续参见图6，在本申请的一种实施方式中，可选地，第一发光控制模块700包括第五晶体管M5。第五晶体管M5的第一极与驱动模块100的第一端(第二节点N2)电连接，第五晶体管M5的第二极接入第一电源信号VDD，第五晶体管M5的栅极接入第二发光控制信号EM。本申请实施例设置第一发光控制模块700仅包括一个晶体管，电路结构简单，易于实现。
继续参见图6，在本申请的一种实施方式中，可选地，第二发光控制模块800包括第六晶体管M6。第六晶体管M6的第一极与驱动模块100的第二端电连接，第六晶体管M6的第二极与发光器件OLED电连接，第六晶体管M6的栅极接入第二发光控制信号EM。本申请实施例设置第二发光控制模块800仅包括一个晶体管，电路结构简单，易于实现。
继续参见图6，在本申请的一种实施方式中，可选地，初始化模块900包括第七晶体管M7。第七晶体管M7的第一极与第二发光控制模块800的第二端电连接，第七晶体管M7的第二极接入初始化信号，第七晶体管M7的栅极接入第二扫描信号S2。本申请实施例设置初始化模块900仅包括一个晶体管，电路结构简单，易于实现。
继续参见图6，在本申请的一种实施方式中，可选地，第一存储模块500包括第一电容C1。第一电容C1的第一极与补偿模块300的第二端(第一节点N1)电连接，第一电容C1的第二极接入参考电压信号Vref。本申请实施例设置第一存储模块500仅包括一个电容，电路结构简单，易于实现。
继续参见图6，在本申请的一种实施方式中，可选地，第二存储模块600包括第二电容C2。第二电容C2的第一极与驱动模块100的控制端(栅极G)电连接，第二电容C2的第二极接入第一电源信号VDD。本申请实施例设置第二存储模块600仅包括一个电容，电路结构简单，易于实现。
图6中示例性地示出了像素电路中的所有晶体管均为P型晶体管，由LTPS工艺制备而成，这并非对本申请的限定。在其他实施例中，还可以设置像素电路中的部分或全部晶体管为N型晶体管，在实际应用中可以根据需要进行设定。
图6中示例性地示出了第一晶体管M1和第二晶体管M2均为单栅晶体管，并非对本申请的限定。在其他实施例中，还可以设置第一晶体管M1和/或第二晶体管M2为双栅晶体管。
参见图7，与上述实施例不同的是，数据写入模块200还包括同步控制端，同步控制端接入第一发光控制信号EMB，数据写入模块200在第一扫描信号S1和第一发光控制信号EMB的共同控制下传输数据信号Data。可选地，数据写入模块200还包括第四晶体管M4。第四晶体管M4的栅极接入第一发光控制信号EMB；第四晶体管M4串联连接于第三晶体管M3的第一极和驱动模块100的第一端(第二节点N2)之间。本申请实施例这样设置的原因在于，在不影响像素电路的其他功能的前提下，减少版图过孔数量。
结合图7和图8，像素电路的版图包括沿第一方向X延伸且位于第一金属层的第一扫描线、第一发光控制信号线、第二发光控制信号线和第二扫描线。第一扫描线传输第一扫描信号S1，第一发光控制信号线传输第一发光控制信号EMB，第二发光控制信号线传输第二发光控制信号EM，第二扫描线传输第二扫描信号S2。
像素电路的版图还包括沿第一方向X延伸且位于第二金属层的参考电压信号线，参考电压信号线传输参考电压信号Vref。
像素电路的版图还包括沿第二方向Y延伸且位于第三金属层的数据线和第一电源信号线。数据线传输数据信号Data，第一电源信号线传输第一电源信号VDD。
像素电路的版图还包括位于有源层的半导体图案，半导体图案与位于第一金属层的多个信号线交叉的位置形成晶体管。半导体图案中S形的部分与第一金属层交叉形成驱动晶体管MD。
半导体图案与第一扫描线交叉的位置形成第三晶体管M3。第一扫描线与半导体图案交叉的部分为第三晶体管M3的栅极，即第三晶体管M3的栅极与第一扫描线电连接。半导体图案位于第一扫描线两侧的部分为第三晶体管的第一极和第二极，第三晶体管M3的第二极通过过孔110连接至数据线，第三晶体管M3的第一极与第四晶体管M4的第二极电连接。
半导体图案与第一发光控制信号线交叉的位置形成第四晶体管M4、第二晶体管M2和第一晶体管M1。第四晶体管M4的栅极与第一发光控制信号线电连 接，第四晶体管M4的第一极与驱动晶体管MD的第一极电连接，第四晶体管M4的第二极与第三晶体管M3的第一极电连接。第一晶体管M1的栅极与第一发光控制信号线电连接，第一晶体管M1的第一极与驱动晶体管MD的第二极电连接，第一晶体管M1的第二极与第二晶体管M2的第二极电连接。第二晶体管M2的栅极与第一发光控制信号线电连接，第二晶体管M2的第一极通过过孔110和连接线120连接至驱动晶体管MD的栅极，第二晶体管M2的第二极与第一晶体管M1的第二极电连接。示例性地，连接线120位于第三金属层。
半导体图案与第二发光控制信号线交叉的位置形成第五晶体管M5和第六晶体管M6。第五晶体管M5的栅极与第二发光控制信号线电连接，第五晶体管M5的第一极与驱动晶体管MD的第一极电连接，第五晶体管M5的第二极通过过孔110连接至第一电源信号线。第六晶体管M6的栅极与第二发光控制信号线电连接，第六晶体管M6的第一极与驱动晶体管MD的第二极电连接，第六晶体管M6的第二极通过过孔110与发光器件的阳极130电连接。
半导体图案与第二扫描线交叉的位置形成第七晶体管M7。第七晶体管M7的栅极与第二扫描线电连接，第七晶体管M7的第一极与第六晶体管M6的第二极电连接，第七晶体管M7的第二极通过过孔110和连接线120连接至参考电压信号线。
驱动晶体管MD的栅极作为第二电容C2的第一极的极板，第二电容C2的第二极的极板可以设置于第三金属层，直接与第一电源信号线电连接；第二电容C2的第二极的极板还可以设置于第二金属层，通过设置过孔110与第一电源信号线电连接。
第一电容C1的第一极的极板位于第二金属层，通过过孔110和连接线120连接至第一晶体管M1的第二极。第一电容C1的第二极的极板位于第三金属层，通过过孔110和连接线120连接至参考电压信号线。或者，第一电容C1的第一极的极板位于第三金属层，通过过孔110和连接线120连接至第一晶体管M1的第二极。第一电容C1的第二极的极板位于第二金属层，直接连接至参考电压信号线。
因此，由图8所示的版图可以看出，在第三晶体管M3的下部，半导体图案与第一发光控制信号线天然形成第四晶体管M4，且第四晶体管M4的存在不会影响像素电路的功能。然而，若不设置M4，需要将半导体图案打断并设置过孔和连接线，以使半导体图案跨过第一发光控制信号线；或者将第一发光控制信号线打断并设置过孔和连接线，以使第一发光控制信号线跨过半导体图案。因此，本申请实施例通过在像素电路中增加第四晶体管M4，实现了在不影响像素电路其他功能的前提下，减少了版图过孔数量。
由此可见，本申请实施例提供了一种8T2C结构的像素电路，从版图上看，对比图2和图8，相比于相关技术的7T1C像素电路，本申请实施例提供的8T2C像素电路没有增加新的信号线。对比图4和图8，相比于相关技术的8T1C电路，本申请实施例提供的8T2C像素电路减少了一条沿第一方向X延伸的信号线，因此，本申请实施例有利于节省布线空间，有利于高每英寸所拥有的像素数目(Pixels Per Inch，PPI)设计。
综上所述，本申请实施例至少包括以下效果：
第一、实现了高电流保持率，显示面板的闪烁现象得到改善，有利于实现低帧频下的高质量显示，从而有利于实现兼顾低功耗和高显示品质的效果。
第二、在对驱动晶体管MD的栅极G进行初始化的同时有利于改善驱动晶体管MD的偏压状态，从而有利于改善残影的问题。
第三、有利于节省布线空间，有利于实现高PPI设计。
本申请实施例还提供了一种显示面板。该显示面板包括如本申请任意实施例所提供的像素电路，具备相应的效果，不再赘述。
本申请实施例还提供了一种像素电路的驱动方法，该驱动方法可适用于本申请任意实施例所提供的像素电路，并具备相应的效果。结合图7和图9，像素电路的驱动方法包括：
S110、在初始化阶段，第一发光控制信号EMB控制补偿模块300和漏电抑制模块400导通，以在驱动模块100的第一端和驱动模块100的第二端分别接入不同电压的情况下，使驱动模块100导通，进行初始化。
S120、在数据写入阶段，第一发光控制信号EMB控制补偿模块300和漏电抑制模块400导通，第一扫描信号S1控制数据写入模块200导通，以使数据信号Data写入驱动模块100的控制端；第一存储模块500的第一端和驱动模块100的控制端的电位相等，且第一存储模块500的第一端和第一存储模块500的第二端形成压差。
S130、在发光阶段，第一发光控制信号EMB控制补偿模块300和漏电抑制模块400断开，第一扫描信号S1控制数据写入模块200断开，第一存储模块500维持第一存储模块500的第一端和第一存储模块500的第二端的压差不变，以使漏电抑制模块400的第一端和第二端的电位相等。
在上述实施例的基础上，可选地，初始化阶段包括第一初始化子阶段和第 二初始化子阶段。
在第一初始化子阶段，第一发光控制信号EMB控制补偿模块300和漏电抑制模块400导通，第二发光控制信号EM控制第一发光控制模块700和第二发光控制模块800导通，第二扫描信号S2控制初始化模块900导通，以使驱动模块100导通，产生的驱动电流经初始化模块900流出。驱动模块100导通，有较大电流流过，在对驱动模块100的控制端(栅极G)进行初始化的同时有利于改善驱动模块100的偏压状态，从而有利于改善残影的问题。
在第二初始化子阶段，第二发光控制信号EM控制第一发光控制模块700和第二发光控制模块800断开；参考电压信号Vref继续对发光器件OLED的阳极进行初始化。
图10为本申请实施例提供的一种像素电路的驱动时序示意图。下面结合图7和图10对像素电路的驱动过程进行说明。
在第一初始化子阶段t11，第二扫描信号S2、第一发光控制信号EMB和第二发光控制信号EM为低电平，第一晶体管M1、第二晶体管M2、第五晶体管M5、第六晶体管M6和第七晶体管M7导通，驱动晶体管MD的栅极G和发光器件OLED的阳极被同时复位，驱动晶体管MD的栅极G写入参考电压信号Vref，此时驱动晶体管MD有较大电流流过，有利于改善驱动晶体管MD的偏压状态，从而改善残影问题。
在第二初始化子阶段t12，与第一初始化阶段t11不同的是，第二发光控制信号EM由低电平变为高电平，第五晶体管M5和第六晶体管M6断开，驱动晶体管MD不再产生大电流。栅极G的电位由第一电容C1保持，参考电压信号Vref继续对发光器件OLED的阳极进行初始化。
在数据写入阶段t2，第二扫描信号S2为高电平，第七晶体管M7断开。第一扫描信号S1和第一发光控制信号EMB为低电平，第三晶体管M3、第四晶体管M4、第一晶体管M1和第二晶体管M2导通，数据信号Data经过第三晶体管M3、第四晶体管M4、驱动晶体管MD、第一晶体管M1和第二晶体管M2写入栅极G和第一节点N1，即写入第一电容C1和第二电容C2。由于参考电压信号Vref低于数据信号Data的电压，因此在数据写入阶段t2，栅极G的电位逐渐升高。
在发光阶段t3，第一扫描信号S1和第一发光控制信号EMB为高电平，第三晶体管M3、第四晶体管M4、第一晶体管M1和第二晶体管M2断开。第二发光控制信号EM为低电平，第五晶体管M5和第六晶体管M6导通，发光器件OLED被点亮。其间，第一电容C1和第二电容C2将第一节点N1和栅极G的 电位锁住。由于第一节点N1和栅极G的电位很接近，所以第二晶体管M2的漏电流很小，因此栅极G的电位更稳定，显示面板的闪烁问题得到改善。
继续参见图10，阶段t0为初始状态，可以认为是上一帧的发光阶段。
在图10中示例性地示出了在第二初始化子阶段t12和数据写入阶段t2之间还包括第一过渡阶段。在第一过渡阶段第二扫描信号S2由低电平变为高电平，第一发光控制信号EMB由低电平变为高电平，这并非对本申请的限定。在其他实施例中，还可以不设置第一过渡阶段，第二扫描信号S2在数据写入阶段t2由低电平变为高电平，以及第一发光控制信号EMB在初始化阶段和数据写入阶段t2保持低电平。
在图10中示例性地示出了在数据写入阶段t2和发光阶段t3之间还包括第二过渡阶段。在第二过渡阶段第一扫描信号S1和第一发光控制信号EMB由低电平变为高电平，这并非对本申请的限定。在其他实施例中，还可以不设置第二过渡阶段，第一扫描信号S1和第一发光控制信号EMB在发光阶段t3由低电平变为高电平。

Claims (20)

  1. 一种像素电路，包括：
    驱动模块，包括控制端、第一端和第二端；
    数据写入模块，包括扫描控制端、第一端和第二端，所述数据写入模块的第一端与所述驱动模块的第一端电连接，所述数据写入模块的第二端接入数据信号，所述数据写入模块的扫描控制端接入第一扫描信号；
    补偿模块，包括控制端、第一端和第二端，所述补偿模块的第一端与所述驱动模块的第二端电连接，所述补偿模块的控制端接入第一发光控制信号；
    漏电抑制模块，包括控制端、第一端和第二端，所述漏电抑制模块的第一端与所述驱动模块的控制端电连接，所述漏电抑制模块的第二端与所述补偿模块的第二端电连接，所述漏电抑制模块的控制端接入所述第一发光控制信号；所述漏电抑制模块与所述补偿模块在初始化阶段和数据写入阶段导通；
    第一存储模块，包括第一端和第二端，所述第一存储模块的第一端与所述补偿模块的第二端电连接，所述第一存储模块的第二端接入参考电压信号；所述第一存储模块设置为在所述数据写入阶段和发光阶段，当所述第一存储模块的第一端和所述第一存储模块的第二端形成压差时，维持该压差不变。
  2. 根据权利要求1所述的像素电路，其中，所述补偿模块包括：
    第一晶体管，所述第一晶体管的第一极与所述驱动模块的第二端电连接，所述第一晶体管的第二极与所述漏电抑制模块的第二端电连接，所述第一晶体管的栅极接入所述第一发光控制信号。
  3. 根据权利要求1所述的像素电路，其中，所述漏电抑制模块包括：
    第二晶体管，所述第二晶体管的第一极与所述驱动模块的控制端电连接，所述第二晶体管的第二极与所述补偿模块的第二端电连接，所述第二晶体管的栅极接入所述第一发光控制信号。
  4. 根据权利要求1所述的像素电路，其中，所述第一存储模块包括：
    第一电容，所述第一电容的第一极与所述补偿模块的第二端电连接，所述第一电容的第二极接入所述参考电压信号。
  5. 根据权利要求1所述的像素电路，其中，所述数据写入模块包括：
    第三晶体管，所述第三晶体管的第一极与所述驱动模块的第一端电连接，所述第三晶体管的第二极接入所述数据信号，所述第三晶体管的栅极接入所述第一扫描信号。
  6. 根据权利要求1所述的像素电路，其中，所述数据写入模块还包括：同 步控制端，所述同步控制端接入所述第一发光控制信号；所述数据写入模块在所述第一扫描信号和所述第一发光控制信号的共同控制下传输所述数据信号。
  7. 根据权利要求6所述的像素电路，其中，所述数据写入模块包括：
    第三晶体管，所述第三晶体管的第二极接入所述数据信号，所述第三晶体管的栅极接入所述第一扫描信号；
    第四晶体管，所述第四晶体管的第一极与所述驱动模块的第一端电连接，所述第四晶体管的第二极与所述第三晶体管的第一极电连接；所述第四晶体管的栅极接入所述第一发光控制信号。
  8. 根据权利要求1所述的像素电路，还包括：
    第二存储模块，所述第二存储模块包括第一端和第二端，所述第二存储模块的第一端与所述驱动模块的控制端电连接，所述第二存储模块的第二端接入第一电源信号；所述第二存储模块设置为在发光阶段维持所述驱动模块的控制端的电位不变。
  9. 根据权利要求8所述的像素电路，其中，所述第二存储模块包括第二电容，所述第二电容的第一极与所述驱动模块的控制端电连接，所述第二电容的第二极接入所述第一电源信号。
  10. 根据权利要求1所述的像素电路，还包括：
    第一发光控制模块，包括控制端、第一端和第二端，所述第一发光控制模块的第一端与所述驱动模块的第一端电连接，所述第一发光控制模块的第二端接入第一电源信号，所述第一发光控制模块的控制端接入第二发光控制信号；
    第二发光控制模块，包括控制端、第一端和第二端，所述第二发光控制模块的第一端与所述驱动模块的第二端电连接，所述第二发光控制模块的第二端与发光器件电连接，所述第二发光控制模块的控制端接入所述第二发光控制信号；
    初始化模块，包括控制端、第一端和第二端，所述初始化模块的第一端与所述第二发光控制模块的第二端电连接，所述初始化模块的第二端接入初始化信号，所述初始化模块的控制端接入第二扫描信号；所述第一发光控制模块、所述第二发光控制模块和所述初始化模块在所述初始化阶段同时导通。
  11. 根据权利要求10所述的像素电路，其中，所述第一发光控制模块包括第五晶体管，所述第五晶体管的第一极与所述驱动模块的第一端电连接，所述第五晶体管的第二极接入所述第一电源信号，所述第五晶体管的栅极接入所述第二发光控制信号。
  12. 根据权利要求10所述的像素电路，其中，所述第二发光控制模块包括第六晶体管，所述第六晶体管的第一极与所述驱动模块的第二端电连接，所述第六晶体管的第二极与所述发光器件电连接，所述第六晶体管的栅极接入所述第二发光控制信号。
  13. 根据权利要求10所述的像素电路，其中，所述初始化模块包括第七晶体管，所述第七晶体管的第一极与所述第二发光控制模块的第二端电连接，所述第七晶体管的第二极接入所述初始化信号，所述第七晶体管的栅极接入所述第二扫描信号。
  14. 根据权利要求11所述的像素电路，其中，所述参考电压信号复用为所述初始化信号。
  15. 根据权利要求10所述的像素电路，其中，所述发光器件包括阳极和阴极，所述第二发光控制模块的第二端与所述发光器件的阳极电连接，所述发光器件的阴极接入第二电源信号。
  16. 一种显示面板，包括：如权利要求1-15任一项所述的像素电路。
  17. 一种像素电路的驱动方法，所述像素电路包括驱动模块、漏电抑制模块、数据写入模块、补偿模块和第一存储模块；所述数据写入模块的第一端与所述驱动模块的第一端电连接，所述数据写入模块的第二端接入数据信号，所述数据写入模块的控制端接入第一扫描信号；所述补偿模块的第一端与所述驱动模块的第二端电连接，所述补偿模块的控制端接入第一发光控制信号；所述漏电抑制模块的第一端与所述驱动模块的控制端电连接，所述漏电抑制模块的第二端与所述补偿模块的第二端电连接，所述漏电抑制模块的控制端接入所述第一发光控制信号；所述第一存储模块的第一端与所述补偿模块的第二端电连接，所述第一存储模块的第二端接入参考电压信号；
    所述驱动方法包括：
    在初始化阶段，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模块导通，以在所述驱动模块的第一端和所述驱动模块的第二端分别接入不同电压的情况下，使所述驱动模块导通，进行初始化；
    在数据写入阶段，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模块导通，所述第一扫描信号控制所述数据写入模块导通，以使所述数据信号写入所述驱动模块的控制端；所述第一存储模块的第一端和所述驱动模块的控制端的电位相等，且所述第一存储模块的第一端和所述第一存储模块的第二端形成压差；
    在发光阶段，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模 块断开，所述第一扫描信号控制所述数据写入模块断开，所述第一存储模块维持所述第一存储模块的第一端和所述第一存储模块的第二端的压差不变，以使所述漏电抑制模块的第一端和所述漏电抑制模块的第二端的电位相等。
  18. 根据权利要求17所述的方法，其中，所述像素电路还包括第一发光控制模块、第二发光控制模块和初始化模块，所述第一发光控制模块的第一端与所述驱动模块的第一端电连接，所述第一发光控制模块的第二端接入第一电源信号，所述第一发光控制模块的控制端接入第二发光控制信号，所述第二发光控制模块的第一端与所述驱动模块的第二端电连接，所述第二发光控制模块的第二端与发光器件电连接，所述第二发光控制模块的控制端接入所述第二发光控制信号，所述初始化模块的第一端与所述第二发光控制模块的第二端电连接，所述初始化模块的第二端接入初始化信号，所述初始化模块的控制端接入第二扫描信号；
    所述初始化阶段包括第一初始化子阶段和第二初始化子阶段；在所述第一初始化子阶段，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模块导通，所述第二发光控制信号控制所述第一发光控制模块和所述第二发光控制模块导通，所述第二扫描信号控制初始化模块导通，所述参考电压信号对所述驱动晶体管的栅极和所述发光器件的阳极进行初始化；在所述第二初始化子阶段，所述第二发光控制信号控制所述第一发光控制模块和所述第二发光控制模块断开；所述参考电压信号对所述发光器件的阳极进行初始化；
    在所述数据写入阶段，所述第二扫描信号控制所述初始化模块断开，所述第一扫描信号控制所述数据写入模块导通；
    在所述发光阶段，所述第一扫描信号控制所述数据写入模块断开，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模块断开，所述第二发光控制模块控制所述第一发光控制模块和所述第二发光控制模块导通。
  19. 根据权利要求18所述的方法，其中，在所述第二初始化子阶段和所述数据写入阶段之间包括第一过渡阶段；
    在所述第一过渡阶段，所述第二扫描信号控制所述初始化模块断开，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模块断开。
  20. 根据权利要求18所述的方法，其中，在所述数据写入阶段和所述发光阶段之间包括第二过渡阶段；
    在所述第二过渡阶段，所述第一扫描信号控制所述数据写入模块断开，所述第一发光控制信号控制所述补偿模块和所述漏电抑制模块断开。
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