WO2023045057A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2023045057A1
WO2023045057A1 PCT/CN2021/131910 CN2021131910W WO2023045057A1 WO 2023045057 A1 WO2023045057 A1 WO 2023045057A1 CN 2021131910 W CN2021131910 W CN 2021131910W WO 2023045057 A1 WO2023045057 A1 WO 2023045057A1
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Prior art keywords
trench
dielectric layer
layer
conductive layer
oxide dielectric
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English (en)
French (fr)
Inventor
卢经文
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to EP21949522.3A priority Critical patent/EP4177955B1/en
Priority to US18/168,650 priority patent/US12513968B2/en
Publication of WO2023045057A1 publication Critical patent/WO2023045057A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • Embodiments of the present disclosure relate to semiconductor technology, and relate to but not limited to a semiconductor structure and a manufacturing method thereof.
  • embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method including:
  • a conductive layer is formed on the surface of the oxide medium layer, and the conductive layer is formed in the trench.
  • the method also includes:
  • Active regions arranged at intervals and isolation structures filled between the active regions are formed on the substrate, and the grooves are formed in the active regions and the isolation structures.
  • the oxide dielectric layer is formed on sidewalls of the trench in the active region.
  • the sacrificial dielectric layer includes an undoped amorphous carbon layer or a doped amorphous carbon layer.
  • the gradually etching the sacrificial dielectric layer to gradually expose the sidewall of the trench, and the exposed sidewall of the trench is oxidized to form an oxide dielectric layer, including:
  • the oxygen-containing plasma includes a water vapor plasma.
  • the method also includes:
  • the formation of a conductive layer on the surface of the oxide medium layer, the conductive layer formed in the trench includes:
  • the top surface of the photoresist material is lower than the surface of the substrate
  • a conductive layer is deposited within the trench.
  • the formation of a conductive layer on the surface of the oxide medium layer, the conductive layer formed in the trench includes:
  • the top surface of the photoresist material is lower than the surface of the substrate
  • a conductive layer is deposited within the trench.
  • the depositing a conductive layer in the trench includes:
  • the target height of the conductive layer is not less than the height of the oxide dielectric layer.
  • the method also includes:
  • An insulating layer is covered on the conductive layer and the oxide medium layer, and the insulating layer is located in the trench.
  • covering the insulating layer on the conductive layer and the oxide dielectric layer includes:
  • An insulating material is deposited in the trench by means of low-pressure chemical vapor deposition to form an insulating layer covering the conductive layer and the oxide medium layer.
  • an embodiment of the present disclosure further provides a semiconductor structure, including:
  • a substrate wherein, the substrate has a trench; the trench has a gate structure;
  • the gate structure includes: an oxide dielectric layer and a conductive layer, the oxide dielectric layer covers the sidewall of the trench, and the conductive layer is located in the trench covered with the oxide dielectric layer; The thickness of the oxide dielectric layer in the trench increases sequentially in a direction extending from the bottom of the trench to the opening of the trench.
  • the semiconductor structure also includes:
  • Active regions arranged at intervals on the substrate and isolation structures filled between the active regions, the trenches are located in the active regions and the isolation structures.
  • the oxide dielectric layer is formed in the trench located in the active region.
  • the top surfaces of the conductive layer and the oxide dielectric layer are lower than the surface of the substrate; the semiconductor structure further includes:
  • An insulating layer is located in the trench and covers the conductive layer and the oxide dielectric layer; wherein the insulating layer is used to protect the gate structure.
  • the trench runs through a plurality of active regions and isolation structures arranged at intervals; the gate structure communicates in the trench, and is located in a direction parallel to the active region.
  • a surface width of the gate structure in the isolation structure is greater than a surface width of the gate structure in the active region.
  • the trench is filled with a sacrificial dielectric layer, and the sidewall of the trench is gradually exposed and oxidized during the process of gradually etching the sacrificial dielectric.
  • the oxide dielectric layer at the bottom of the trench is relatively thin, so that the corresponding gate structure has good switching characteristics.
  • GIDL leakage occurs in the area overlapping the active area on both sides of the trench, which improves the reliability and stability of the product.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of forming a gate dielectric layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a gate structure formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 6A is a top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • Fig. 6B is a partially enlarged view of Fig. 6A;
  • FIG. 7 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 8A is a schematic cross-sectional view of various steps in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure
  • FIG. 8B is a schematic cross-sectional view of a structure formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure
  • 9A is a schematic cross-sectional view of various steps in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • 9B is a schematic cross-sectional view of a structure formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
  • 9C is a schematic cross-sectional view of a structure formed in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
  • 9D is a schematic cross-sectional view of various steps in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic cross-sectional view of a structure formed in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG. 1 , the method includes:
  • Step S101 forming a trench on the substrate
  • Step S102 filling the trench with a sacrificial dielectric layer
  • Step S103 gradually etching the sacrificial dielectric layer to gradually expose the sidewall of the trench, the exposed sidewall of the trench is at least partially oxidized to form an oxide dielectric layer, and the thickness of the oxide dielectric layer in the trench is from the bottom of the trench to the bottom of the trench.
  • the direction in which the opening of the slot extends increases sequentially;
  • Step S104 forming a conductive layer on the surface of the oxide medium layer, and the conductive layer is formed in the trench.
  • grooves may be formed on the surface of the substrate by patterned etching.
  • the trench is used to form a semiconductor structure, such as a gate structure, and the gate structure can pass through the entire semiconductor structure and can be used as a word line in the semiconductor structure. Since the gate structure is buried in the trench instead of covering the surface of the substrate, this structure is also called Buried Word Line (BWL, Buried Word Line).
  • BWL Buried Word Line
  • the plurality of grooves may be parallel to each other and have the same pitch, depth and width, or may have different pitches and widths.
  • Multiple trenches can be formed simultaneously by etching.
  • a sacrificial dielectric layer can be filled in the trench.
  • the sacrificial dielectric layer is used to assist in forming an oxide dielectric layer as a gate dielectric layer. Therefore, the sacrificial dielectric layer has been remove.
  • the sidewall of the trench is gradually exposed by gradually etching the sacrificial dielectric layer, and the sidewall of the trench is gradually oxidized to form an oxide dielectric layer.
  • the oxidation time from the opening to the bottom of the trench can be gradually reduced. That is to say, the closer to the sidewall at the opening of the trench, the longer the time to be oxidized, and thus the thicker the formed oxide dielectric layer; the closer to the sidewall to the bottom of the trench, the shorter the time to be oxidized, so the formed The oxide dielectric layer is thinner.
  • the thickness of the oxide dielectric layer increases sequentially in the extending direction from the bottom of the trench to the opening of the trench.
  • a trench 110 is formed in the substrate 100, the inner wall of the trench is covered with an oxide dielectric layer 121, and the thickness of the oxide dielectric layer 121 on the side wall of the trench is from the bottom of the trench to the direction of the opening. Gradually increase.
  • the trench can be filled with conductive material to form a conductive layer.
  • the conductive material includes metal material or compound conductive material, such as metal tungsten (W) and titanium nitride (TiN).
  • the oxide dielectric layer and the conductive layer can be etched back to a target depth, that is, the conductive layer and the oxide dielectric layer near the opening in the trench are removed.
  • the sidewall of the trench is gradually oxidized by gradually etching the sacrificial dielectric layer, and an oxide dielectric layer whose thickness gradually increases from the bottom of the trench to the extending direction of the opening can be formed. In this way, a thinner oxide dielectric layer is formed at the bottom of the trench, and a thicker gate dielectric layer is formed closer to the opening of the trench.
  • the forming method further includes:
  • Active regions arranged at intervals and isolation structures filled between the active regions are formed on the substrate, and grooves are formed in the active regions and the isolation structures.
  • active regions and isolation structures arranged at intervals may be formed on the substrate.
  • the active region can be formed by doping the silicon substrate, and an insulating material is filled between every two active regions as an isolation structure, and the insulating material can be silicon dioxide.
  • the extending direction of the active region and the extending direction of the trench have a certain included angle.
  • the extending direction of the active region and the extending direction of the trench may be perpendicular to each other.
  • an active region with a certain depth may be formed in the entire area of the substrate by doping on the substrate, and then trenches may be formed by etching the active region and the isolation structure between the active regions.
  • the above-mentioned conductive layer can be used as a gate conductive layer in the semiconductor structure for providing a gate control voltage.
  • An oxide dielectric layer with a graded thickness is located between the active area and the conductive layer.
  • the gate control voltage on the conductive layer can cause charge migration in the active regions on both sides of the trench, thereby realizing the switching function of the transistor.
  • the trench may penetrate the entire semiconductor structure, that is, the trench may penetrate multiple active regions and isolation structures.
  • the above-mentioned oxide dielectric layer and the conductive layer cover the sidewalls of the trenches, thus also penetrating through multiple active regions and isolation structures.
  • the above-mentioned oxide dielectric layer may be formed on the sidewall of the trench in the active region. Since both the isolation structure and the oxide dielectric layer can be made of silicon dioxide, when the oxide dielectric layer is formed, only the sidewall of the active region is oxidized to form the oxide dielectric layer, which is integrated with the isolation structure.
  • the sacrificial dielectric layer includes an undoped amorphous carbon layer or a doped amorphous carbon layer.
  • the oxide dielectric layer in order to form the oxide dielectric layer with a gradually changing thickness, it can be realized by means of a sacrificial dielectric layer.
  • the material of the sacrificial medium layer may be amorphous carbon material, including undoped pure amorphous carbon material and doped amorphous carbon material.
  • the doped amorphous carbon material may include boron doped amorphous carbon (BALC).
  • the sacrificial dielectric layer is gradually etched to gradually expose the sidewall of the trench, and the exposed sidewall of the trench is oxidized to form an oxide dielectric layer, including:
  • the sacrificial dielectric layer is etched by oxygen-containing plasma, and the sacrificial dielectric layer is gradually etched by controlling the flow rate of the oxygen-containing plasma; the sidewall of the trench is oxidized by the oxygen-containing plasma to form an oxide dielectric layer.
  • oxygen-containing plasma may be used to oxidize oxygen ions and carbon elements in the sacrificial medium layer through sputtering, thereby achieving the effect of removing the sacrificial medium layer.
  • the oxygen-containing plasma will be sputtered to the gradually exposed trench sidewalls synchronously, since the exposed trench sidewalls contain silicon, the oxygen-containing plasma will oxidize the silicon element on the trench sidewalls to form a silicon dioxide film .
  • the bottom of the trench is also exposed, and an oxidation reaction occurs to form a silicon dioxide film.
  • the inner walls of the trenches can be covered with silicon oxide.
  • the oxygen-containing plasma includes a water vapor plasma.
  • the above-mentioned oxygen-containing plasma may use water vapor plasma, that is, a mixed plasma of hydrogen ions and oxygen ions is formed by ionizing water vapor.
  • water vapor plasma that is, a mixed plasma of hydrogen ions and oxygen ions is formed by ionizing water vapor.
  • an inert gas may also be mixed in the water vapor plasma to achieve the effect of controlling the reaction speed and degree of reaction.
  • the forming method further includes:
  • the trench can be used to form a buried word line, that is, the gate structure is buried inside the substrate and connected as a word line by a conductive layer.
  • the formed gate dielectric layer covers the entire inner wall of the trench. Therefore, it is necessary to remove the gate dielectric layer on the sidewall at a certain depth at the opening of the trench, and only keep the gate dielectric layer near the bottom of the trench. A part of the gate dielectric layer.
  • the surface of the conductive layer and the oxide dielectric layer can be lower than the opening of the trench. Therefore, the oxide dielectric layer and the conductive layer can be etched back to the target depth to form the above-mentioned grooves located inside the trench and whose surface is lower than the trench.
  • the target structure at the opening can be lower than the opening of the trench. Therefore, the oxide dielectric layer and the conductive layer can be etched back to the target depth to form the above-mentioned grooves located inside the trench and whose surface is lower than the trench.
  • a conductive layer is formed on the surface of the oxide dielectric layer, and the conductive layer is formed in the trench, including:
  • the top surface of the photoresist material is lower than the surface of the substrate
  • a conductive layer is deposited within the trench.
  • a photoresist material may be filled in the groove formed with the oxide dielectric layer, and the thickness of the filled photoresist material is smaller than the depth of the groove. That is to say, after filling the photoresist material, part of the trench still exists, and part of the oxide dielectric layer is exposed.
  • the exposed oxide dielectric layer can be removed by means of etching or cleaning.
  • the silicon oxide film can be removed by hydrofluoric acid solution, and a part of the oxide dielectric layer near the bottom of the trench is photoresisted. Material covers without being removed.
  • the photoresist material can be removed by cleaning to expose the remaining oxide dielectric layer, so as to facilitate the subsequent continuous formation of the conductive layer.
  • the cleaning solution for removing the photoresist material may be an aqueous solution of sulfuric acid.
  • the trench is re-exposed.
  • a conductive layer can be deposited in the trench so that the conductive layer is filled in the oxide dielectric layer.
  • the surface of the conductive layer may be higher than the surface of the oxide dielectric layer, so the conductive layer can be further etched back to make its surface level with the surface of the oxide dielectric layer or lower than the surface of the oxide dielectric layer.
  • the oxide dielectric layer within a certain height at the top of the trench can be removed, so that the opening of the trench is enlarged, thereby reducing the impact of the early sealing effect during the process of forming the gate structure and depositing the conductive layer.
  • a conductive layer is formed on the surface of the oxide dielectric layer, and the conductive layer is formed in the trench, including:
  • the top surface of the photoresist material is lower than the surface of the substrate
  • a conductive layer is deposited within the trench.
  • the isolation structure and the oxide dielectric layer exposed above the photoresist material will be etched away synchronously, form a groove.
  • the photoresist material is removed, and a conductive layer can be deposited between the oxide dielectric layers in the trench.
  • depositing a conductive layer within the trench includes:
  • a conductive material is deposited in the groove, and the conductive material is controlled to a target height to form a conductive layer, and the target height of the conductive layer is smaller than the height of the groove.
  • the target height of the conductive layer is not less than the height of the oxide dielectric layer.
  • the metal material can be filled into the trench by a deposition method so as to cover the oxide dielectric layer.
  • the deposition method may include physical vapor deposition (Physical Vapor Deposition, PVD) or atomic layer deposition (Atomic Layer Deposition, ALD), etc.
  • the target height of the conductive layer is smaller than the height of the trench, that is to say, the top surface of the conductive layer can be flush with the top surface of the oxide dielectric layer that has been partially etched back, or it can be slightly lower than the top surface of the oxide dielectric layer. surface, but the top surface of the conductive layer needs to be lower than the top of the trench, and the conductive layer cannot be in contact with the silicon material on the sidewall of the trench. In this way, the conductive layer and the oxide dielectric layer form a complete gate structure.
  • the trench since the trench extends along the direction of the substrate surface, it can penetrate multiple active regions and isolation layers, so the conductive layer can also penetrate to form a word line.
  • the forming method further includes:
  • the insulating layer 123 covers the conductive layer 122 and the oxide dielectric layer 121 , and the insulating layer 123 is located in the trench 110 .
  • an insulating layer may be covered on the conductive layer and the oxide dielectric layer to achieve the function of protecting the gate structure.
  • the covered gate can be formed by depositing an insulating material in the trench The insulating layer of the structure, and then the conductive layer that runs through the trench is called a buried word line.
  • the insulating layer includes: a silicon nitride layer
  • the insulating layer may further include: oxide, or a thin film of organic material.
  • the step of covering the insulating layer on the conductive layer and the oxide dielectric layer includes:
  • An insulating material is deposited in the trench by a low-pressure chemical vapor deposition method to form an insulating layer covering the conductive layer and the oxide medium layer.
  • the formation of the insulating layer can be by means of low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) to deposit uniform silicon nitride in the remaining space in the trench, thereby forming an insulating layer covering the gate structure.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • the semiconductor structure 200 includes:
  • a substrate 210 wherein, the substrate 210 has a trench 220; the trench 220 has a gate structure 230;
  • the gate structure 230 includes: an oxide dielectric layer 231 and an electrical layer 232, the oxide dielectric layer 231 covers the sidewall of the trench 220, the conductive layer 232 is located in the trench 220 covered with the oxide dielectric layer 231; The thickness of the dielectric layer 231 in the trench 220 increases sequentially in the direction extending from the bottom of the trench 220 to the opening of the trench 220 .
  • the substrate may have a plurality of grooves, and the grooves are arranged at intervals.
  • One groove, two grooves or even more grooves may be formed on one active region, and these grooves may be formed on the substrate. distributed along a direction parallel to the substrate surface.
  • the plurality of grooves may be parallel to each other and have equal pitches, depths and widths, or may have different pitches and widths.
  • the gate structure is used as a switch control structure of the transistor, which can switch the conduction state of the conduction channel.
  • the gate structure is distributed in the trench to form a buried word line.
  • the gate structure includes an oxide dielectric layer and a conductive layer, and the oxide dielectric layer is used to isolate the conductive layer from the substrate, thus covering the inner wall of the trench.
  • the oxide dielectric layer on the sidewall of the trench has a characteristic of gradually changing thickness. The thickness of the oxide dielectric layer increases sequentially from the bottom of the trench to the opening of the trench. In this way, the oxide dielectric layer at the bottom of the trench is thinner, thereby ensuring the switching characteristics of the gate structure.
  • the closer to the trench The thicker the oxide dielectric layer at the opening of the trench, the reduction of GIDL leakage in the overlapped area between the gate and the substrate on both sides of the trench, improving the reliability and stability of the product.
  • FIG. 5 is a cross-sectional view of the semiconductor structure along the trench direction. As shown in FIG. 5, the semiconductor structure 200 further includes:
  • the active regions 240 arranged at intervals on the substrate and the isolation structures 250 filled between the active regions 240 , the trenches 220 are located in the active regions 240 and the isolation structures 250 .
  • the active region may be a doped semiconductor material with a certain conductivity.
  • the active region can be used as the source region and the drain region of the transistor, and the charge is driven to transfer in the semiconductor channel under the action of the gate control voltage.
  • the active area can be connected with external wires through the contact structure to realize the transmission of electrical signals.
  • isolation structure between the active regions arranged at intervals, and the isolation structure may be an insulating material, including silicon dioxide, silicon nitride, or other organic materials.
  • the isolation structure can provide electrical isolation between adjacent active regions, so that each active region can be used for an independent transistor structure, thereby forming an array structure of transistors.
  • the trench is formed in the active area and the isolation structure, and the gate is located in the trench, thereby forming a transistor structure with the active area.
  • the oxide dielectric layer is formed in the trench in the active region.
  • the sidewall of the active region in the trench will be oxidized to form the above-mentioned oxide dielectric layer.
  • the material of the isolation structure is silicon dioxide, it is the same as the material of the oxide dielectric layer. Therefore, the oxide dielectric layer will be integrated with the isolation region after being formed.
  • the top surfaces of the conductive layer and the oxide dielectric layer are lower than the surface of the substrate; as shown in FIG. 5, the semiconductor structure further includes:
  • the insulating layer 233 is located in the trench 220 and covers the conductive layer 232 and the oxide dielectric layer 231 ; wherein the insulating layer 233 is used to protect the gate structure.
  • the conductive layer Since the conductive layer is located in the trench, the conductive layer may be covered by an insulating layer in order to facilitate the formation of other structures on the substrate surface, including structures such as storage capacitors and bit lines. In this way, the gate structure can be buried in the substrate, reducing electrical interference with other structures.
  • the trench runs through a plurality of active regions and the isolation structure arranged at intervals; the gate structure is connected in the trench, and in the direction parallel to the active region, the gate structure located in the isolation structure
  • the surface width is greater than the surface width of the gate structure located in the active region.
  • the trench is located in the active region and the isolation structure at intervals, and the trench may penetrate multiple active regions, so as to serve as a word line in the semiconductor structure and provide gate control signals for multiple transistors.
  • the active region in the direction aa' parallel to the extension of the active region, can be divided into a plurality of regions separated by isolation structures, and the gate structure 610 is A plurality of word lines are formed through each active area and the isolation structure.
  • the isolation structure can be made of silicon dioxide.
  • the surface of the isolation structure When the surface of the active region is oxidized in the direction aa', the surface of the isolation structure will not be oxidized to form silicon oxide, and when the oxide dielectric layer on the surface of the active region is removed, The isolation structure will also be partially etched, that is, when the oxide dielectric layer is removed, the isolation structure will also be partially etched, in a direction parallel to aa', finally resulting in the surface width bb of the gate structure 610 formed in the isolation structure 'is greater than the surface width cc' of the gate structure 610 between the active regions.
  • FIG. 6B is a partially enlarged schematic view of the surface where the above-mentioned gate structure is located.
  • the gate structure 610 runs through multiple isolation structures 611 and active regions 612, but the surface width bb' of the gate structure 610 between the active regions 612 is larger than that of the gate structure.
  • the surface width cc′ of the structure 610 is located in the isolation structure 611 .
  • the semiconductor structure further includes:
  • the contact structure is located on the surface of the active area.
  • the contact structure is connected to the surface of the active region, and on the other hand, it is used to connect to other external circuits.
  • the bit line contact structure is connected to the bit line, so that the signal on the bit line can be transmitted through the bit line contact structure to the active area.
  • the storage node contact structure is connected to the external storage capacitor. When the gate control signal makes the transistor turn on, the signal transmitted by the bit line can pass through the active area connected to the bit line contact structure through the semiconductor conductive channel, and then through the active area.
  • the contact structure of the source area and the storage node reaches the storage capacitor, so as to realize reading and writing of data.
  • the word line is used to provide a gate control signal for controlling the turn-on of the transistor.
  • the transistor is turned on, the current is passed from the bit line through the transistor to the storage capacitor.
  • the contact structure here includes a bit line contact structure (BLC) and a storage node contact structure (NC).
  • BLC bit line contact structure
  • NC storage node contact structure
  • the oxide dielectric layer with a gradual thickness is formed through the following steps.
  • the oxide dielectric layer near the bottom of the trench is thinner, so that the bottom of the conductive layer has good switching characteristics and small parasitic capacitance.
  • the oxide dielectric layer near the top of the trench is thicker, so that the electric field between the conductive layer and the contact structure and the ion implantation area can be reduced, thereby reducing the occurrence of leakage defects such as GIDL.
  • FIG. 8A is a schematic cross-sectional view of various steps along the extending direction of the trench 220 and located at the center of the trench.
  • trenches 220 perpendicular to the distribution direction of the active regions can be formed.
  • a mask layer 260 may be covered on the surface of the substrate, and then the trench 220 is formed by etching.
  • the mask layer 260 can be removed after the trench is formed, and of course, the mask layer 260 can also be removed after the gate structure is formed in the trench. Since the active region 240 is made of silicon and the isolation structure 250 is made of silicon dioxide, it is necessary to simultaneously etch silicon dioxide and silicon downward during the trench etching process to form a trench 220 with a certain depth. Depth required to bury wordlines.
  • boron-doped amorphous carbon can be deposited in the trench 220 to form a sacrificial dielectric layer 221 to fill the trench 220 .
  • a schematic cross-sectional view along a direction perpendicular to the extending direction of the trench is shown in FIG. 8B .
  • FIG. 9A is a schematic cross-sectional view of each step along the extending direction of the trench 220 and at the center of the trench.
  • water vapor can be formed by adding plasma to oxygen O 2 and hydrogen H 2 .
  • the BACL is gradually cleaned from top to bottom by plasma sputtering, and at the same time, the oxygen ions in the plasma will react with the silicon element on the gradually exposed sidewall of the trench to form a silicon dioxide film.
  • a silicon dioxide film whose thickness gradually becomes thinner from top to bottom can be formed on the sidewall of the trench as the oxide dielectric layer 231 , and the remaining space in the trench will form a trapezoidal structure.
  • the speed of BACL consumption can be controlled by controlling the gas flow rate, and then the thickness of the silicon oxide film can be controlled.
  • the photoresist material (PR) 222 can be deposited in the trench first, and the deposited thickness is the required height of the gate structure 230 .
  • FIG. 9B a schematic cross-sectional view along a direction perpendicular to the extending direction of the trench is shown in FIG. 9B .
  • the silicon oxide film above the photoresist material 222 can be washed away, and then the photoresist material 222 can be removed. In this way, the remaining silicon oxide film serves as the oxide dielectric layer 231 of the gate structure. Then deposit titanium nitride material or metal tungsten material as the conductive layer 232 , and finally deposit the insulating layer 233 to cover the conductive layer 232 .
  • the schematic diagram of the cross-section corresponding to the three-dimensional viewing angle of each step in the above process is shown in FIG. 9D . In this way, the opening in the remaining trench is relatively large, which can effectively fill the metal material and etch to the required height of the word line, thereby reducing the occurrence of the early sealing effect.
  • silicon nitride material in the remaining trench 220 by LPCVD or form a silicon nitride film as the insulating layer 233 by reacting silane (SiH 4 ) and silicon dichlorohydrogen (SiH 2 Cl 2 ).
  • the gate structure 230 forms a buried word line. A schematic cross-sectional view thereof along a direction perpendicular to the extending direction of the trench is shown in FIG. 10 .
  • the etching gas for silicon, silicon oxide and silicon nitride can be sulfur hexafluoride (SF 6 ), carbon tetrafluoride (CF 4 ), chlorine (Cl 2 ), three A mixture of one or more gases in fluoromethane (CHF 3 ), oxygen (O 2 ) and argon (Ar) in a certain proportion.
  • a gate structure in which the conductive layer gradually becomes thinner from the top to the bottom can be formed, and this structure can effectively reduce the leakage of the GIDL.
  • part of the silicon oxide film on the word line is etched away, so that the opening is larger in the process of forming the gate structure, thereby reducing the early sealing effect.
  • the trench is filled with a sacrificial dielectric layer, and the sidewall of the trench is gradually exposed and oxidized during the process of gradually etching the sacrificial dielectric.
  • the oxide dielectric layer at the bottom of the trench is relatively thin, so that the corresponding gate structure has good switching characteristics.
  • GIDL leakage occurs in the area overlapping the active area on both sides of the trench, which improves the reliability and stability of the product.

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Abstract

本公开实施例公开了一种半导体结构及其制造方法。该方法包括：在衬底上形成沟槽；在所述沟槽内填充牺牲介质层；逐步蚀刻所述牺牲介质层以逐步暴露所述沟槽的侧壁，暴露的所述沟槽的侧壁至少部分氧化生成氧化物介质层，所述氧化物介质层在所述沟槽内的厚度由所述沟槽的底部向所述沟槽开口处延伸的方向上依次增大；在所述氧化物介质层表面形成导电层，所述导电层形成在所述沟槽内。

Description

半导体结构及其制造方法
相关的交叉引用
本公开基于申请号为202111138596.8、申请日为2021年09月27日、发明名称为“半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及半导体技术，涉及但不限于一种半导体结构及其制造方法。
背景技术
随着超大规模集成电路技术的迅速发展，半导体器件的尺寸在不断减小。由于半导体器件的急剧减小，晶体管栅氧化层的厚度减小至2nm甚至更薄。在半导体器件按比例缩小尺寸的同时，工作电压并未相应地等比例降低，导致短沟道器件的栅致漏极泄漏(GIDL，Gate-Induced-Drain-Leakage)电流效应非常强烈，影响了半导体器件的可靠性。因此，如何减小半导体器件中的GIDL电流效应，成为了亟需解决的问题。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其制造方法。
第一方面，本公开实施例提供一种半导体结构的制造方法，该方法包括：
在衬底上形成沟槽；
在所述沟槽内填充牺牲介质层；
逐步蚀刻所述牺牲介质层以逐步暴露所述沟槽的侧壁，暴露的所述沟槽的侧壁至少部分氧化生成氧化物介质层，所述氧化物介质层在所述沟槽内的厚度由所述沟槽的底部向所述沟槽开口处延伸的方向上依次增大；
在所述氧化物介质层表面形成导电层，所述导电层形成在所述沟槽内。
在一些实施例中，所述方法还包括：
在所述衬底上形成间隔排布的有源区和填充在所述有源区之间的隔离结构，所述沟槽形成在所述有源区和所述隔离结构中。
在一些实施例中，所述氧化物介质层形成在所述有源区的所述沟槽的侧壁。
在一些实施例中，所述牺牲介质层包括无掺杂非晶碳层或掺杂非晶碳层。
在一些实施例中，所述逐步蚀刻所述牺牲介质层以逐步暴露所述沟槽的侧壁，暴露的所述沟槽的侧壁氧化生成氧化物介质层，包括：
采用含氧等离子体蚀刻所述牺牲介质层，并通过控制所述含氧等离子体的流量逐步刻蚀所述牺牲介质层；所述含氧等离子氧化所述沟槽的侧壁生成所述氧化物介质层。
在一些实施例中，所述含氧等离子体包括水蒸气等离子体。
在一些实施例中，所述方法还包括：
回蚀刻所述氧化物介质层和所述导电层至目标深度，形成目标结构。
在一些实施例中，所述在所述氧化物介质层表面形成导电层，所述导电层形成在所述沟槽内，包括：
在形成所述氧化物介质层后，在所述沟槽内填充光阻材料，所述光阻材料的顶表面低于所述衬底的表面；
去除被所述光阻材料暴露的所述氧化物介质层；
去除所述光阻材料；
在所述沟槽内沉积导电层。
在一些实施例中，所述在所述氧化物介质层表面形成导电层，所述导电层形成在所述沟槽内，包括：
在形成所述氧化物介质层后，在所述沟槽内填充光阻材料，所述光阻材料的顶表面低于所述衬底的表面；
去除所述光阻材料上方所述氧化物介质层和部分所述隔离结构；
去除所述光阻材料；
在所述沟槽内沉积导电层。
在一些实施例中，所述在所述沟槽内沉积导电层，包括：
在所述沟槽内沉积导电材料，控制所述导电材料至目标高度，以形成所述导电层，所述导电层的所述目标高度小于所述沟槽的高度。
在一些实施例中，所述导电层的所述目标高度不小于所述氧化介质层的高度。
在一些实施例中，所述方法还包括：
在所述导电层和所述氧化物介质层上覆盖绝缘层，所述绝缘层位于所述沟槽内。
在一些实施例中，所述在所述导电层和所述氧化物介质层上覆盖绝缘层，包括：
在所述沟槽内通过低压力化学气相沉积的方法沉积绝缘材料，形成覆盖所述导电层和所述氧化物介质层的绝缘层。
第二方面，本公开实施例还提供一种半导体结构，包括：
衬底；其中，所述衬底上具有沟槽；所述沟槽内具有栅极结构；
所述栅极结构包括：氧化物介质层和导电层，所述氧化物介质层覆盖在所述沟槽的侧壁上，所述导电层位于覆盖有所述氧化物介质层的沟槽内；所述氧化物介质层在所述沟槽内的厚度由所述沟槽的底部向所述沟槽开口 处延伸的方向厚度依次增大。
在一些实施例中，所述半导体结构还包括：
在所述衬底上间隔排布的有源区和填充在所述有源区之间的隔离结构，所述沟槽位于所述有源区和所述隔离结构中。
在一些实施例中，所述氧化物介质层形成在位于所述有源区的所述沟槽中。
在一些实施例中，所述导电层和所述氧化物介质层的顶表面低于所述衬底的表面；所述半导体结构还包括：
绝缘层，位于所述沟槽内，覆盖在所述导电层和所述氧化物介质层上；其中，所述绝缘层用于保护所述栅极结构。
在一些实施例中，所述沟槽贯穿多个间隔排布的有源区和隔离结构；所述栅极结构在所述沟槽内连通，在平行于所述有源区的方向上，位于所述隔离结构中的所述栅极结构的表面宽度大于位于所述有源区中的所述栅极结构的表面宽度。
在本公开实施例中，在沟槽内填充牺牲介质层，并通过逐步刻蚀牺牲介质的过程中逐步暴露并氧化沟槽的侧壁。这样，沟槽底部的氧化物介质层较薄，从而使相应的栅极结构具有良好的开关特性，同时，越靠近沟槽开口处的氧化物介质层越厚，减少了对应形成的栅极结构与沟槽两侧有源区交叠区域发生GIDL漏电的情况，提升了产品的可靠性和稳定性。
附图说明
图1为本公开一个实施例提供的一种半导体结构的制造方法的流程图；
图2为本公开一个实施例提供的一种半导体结构的制造方法中形成栅极介质层的结构示意图；
图3为本公开一个实施例提供的一种半导体结构的制造方法中形成的栅极结构的示意图；
图4为本公开一个实施例提供的一种半导体结构的示意图；
图5为本公开一个实施例提供的一种半导体结构的示意图；
图6A为本公开一个实施例提供的一种半导体结构的俯视图；
图6B为图6A的局部放大图；
图7为本公开一个实施例提供的一种半导体结构的示意图；
图8A为本公开一个实施例提供的一种半导体结构的制造方法中各步骤的截面示意图；
图8B为本公开一个实施例提供的一种半导体结构的制造方法中形成结构的截面示意图；
图9A为本公开一个实施例提供的一种半导体结构的制造方法中各步骤的截面示意图；
图9B为本公开一个实施例提供的一种半导体结构的制造方法中形成结构的截面示意图；
图9C为本公开一个实施例提供的一种半导体结构的制造方法中形成结构的截面示意图；
图9D为本公开一个实施例提供的一种半导体结构的制造方法中各步骤的截面示意图；
图10为本公开一个实施例提供的一种半导体结构的制造方法中形成结构的截面示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的 技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本公开实施例提供一种半导体结构的制造方法，如图1所示，该方法包括：
步骤S101、在衬底上形成沟槽；
步骤S102、在沟槽内填充牺牲介质层；
步骤S103、逐步蚀刻牺牲介质层以逐步暴露沟槽的侧壁，暴露的沟槽的侧壁至少分氧化生成氧化物介质层，氧化物介质层在沟槽内的厚度由沟槽的底部向沟槽开口处延伸的方向上依次增大；
步骤S104、在氧化物介质层表面形成导电层，导电层形成在沟槽内。
在本公开实施例中，可以通过图形化刻蚀的方法在衬底表面形成沟槽。沟槽中用于形成半导体结构，例如栅极结构，栅极结构可以贯通整个半导体结构可以用于作为半导体结构中的字线。由于栅极结构被掩埋于沟槽内，而不是覆盖在衬底表面，因此这种结构又被称为掩埋字线(BWL，Buried Word Line)。
沟槽可以具有多条，并且在衬底上平行分布。示例性地，多条沟槽之间可以相互平行且具有相等的间距、深度以及宽度，也可以具有不同的间距以及宽度。多条沟槽可以通过刻蚀同步形成。
在形成沟槽后，可以在沟槽内填充牺牲介质层，牺牲介质层是用于辅助形成作为栅极介质层的氧化物介质层的，因此，在最终形成的半导体结构中牺牲介质层已经被去除。
在本公开实施例中，可以通过逐步刻蚀牺牲介质层的方式，使沟槽的侧壁逐步暴露，并且，使沟槽的侧壁逐步氧化形成氧化物介质层。通过逐 步刻蚀牺牲层并氧化沟槽侧壁的方式，可以使得沟槽的侧壁由开口至沟槽底部的氧化时长逐渐减少。也就是说，越靠近沟槽开口处的侧壁，被氧化的时间越长，因而形成的氧化物介质层越厚；越靠近沟槽底部的侧壁，被氧化的时间越短，因而形成的氧化介质层越薄。
这样，就可以使得氧化物介质层的厚度由沟槽底部到沟槽开口处延伸方向上依次增大。如图2所示，衬底100中形成有沟槽110，沟槽的内壁覆盖有氧化物介质层121，并且，沟槽侧壁的氧化物介质层121的厚度由沟槽底部到开口的方向逐渐增大。
形成氧化物介质层后，可以在沟槽内填充导电材料形成导电层，导电材料包括金属材料或者化合物导电材料等，例如金属钨(W)以及氮化钛(TiN)。
形成导电层后，可以回刻蚀氧化物介质层以及导电层至目标深度，也就是去除沟槽中靠近开口处的导电层以及氧化物介质层。通过本公开实施例的上述方法，采用逐步刻蚀牺牲介质层的方式对沟槽的侧壁进行逐步氧化，可以形成厚度由沟槽底部到开口的延伸方向上逐步增大的氧化物介质层。这样，形成了在沟槽底部较薄的氧化物介质层，而越靠近沟槽开口处的栅极介质层越厚。
在一些实施例中，形成方法还包括：
在衬底上形成间隔排布的有源区和填充在有源区之间的隔离结构，沟槽形成在有源区和隔离结构中。
在本公开实施例中，形成上述沟槽的步骤之前，可以先在衬底上形成间隔排布的有源区以及隔离结构。有源区可以通过对硅衬底进行掺杂的方式形成，每两个有源区之间填充有绝缘材料作为隔离结构，绝缘材料可以是二氧化硅。
有源区的延伸方向与沟槽的延伸方向具有一定的夹角，示例性地，有 源区的延伸方向可以与沟槽的延伸方向相互垂直。
在一实施例中，可以在衬底上通过掺杂在衬底的整个区域形成一定深度的有源区，然后通过刻蚀有源区和有源区之间的隔离结构形成沟槽。
上述导电层可以作为半导体结构中的栅极导电层，用于提供栅极控制电压。具有渐变厚度的氧化物介质层则位于有源区与导电层之间。导电层上的栅极控制电压可以使得沟槽两侧的有源区产生电荷的迁移，进而实现晶体管的开关功能。
需要说明的是，由于有源区与隔离结构间隔排布，而沟槽可以是贯穿整个半导体结构的，即沟槽会贯穿多个有源区和隔离结构。
在一实施例中，上述氧化物介质层与导电层覆盖在沟槽的侧壁上，因此也会贯穿多个有源区和隔离结构。
在另一实施例中，上述氧化物介质层可以形成在有源区的沟槽的侧壁。由于隔离结构与氧化物介质层的材料均可以为二氧化硅，因此，在形成氧化物介质层时仅有源区的侧壁被氧化形成氧化物介质层，并与隔离结构连为一体。
在一些实施例中，牺牲介质层包括无掺杂非晶碳层或掺杂非晶碳层。
本公开实施例中为了形成厚度渐变的氧化物介质层，可以借助牺牲介质层来实现，在通过刻蚀逐渐去除牺牲介质层的过程中，对氧化物介质层同步进行氧化。牺牲介质层的材料可以为非晶碳材料，包括无掺杂的纯非晶碳材料以及掺杂的非晶碳材料。掺杂的非晶碳材料可以包括硼掺杂非晶碳(BALC)。
在一些实施例中，逐步蚀刻牺牲介质层以逐步暴露沟槽的侧壁，暴露的沟槽的侧壁氧化生成氧化物介质层，包括：
采用含氧等离子体蚀刻牺牲介质层，并通过控制含氧等离子体的流量逐步刻蚀牺牲介质层；含氧等离子氧化沟槽的侧壁生成氧化物介质层。
在本公开实施例中，可以采用含氧等离子体(Plasma)通过溅射的方式使氧离子与牺牲介质层中的碳元素发生氧化反应，进而达到去除牺牲介质层的作用。
同时，由于含氧等离子体会同步溅射到逐级裸露的沟槽侧壁，由于裸露的沟槽侧壁包含硅，含氧等离子体与沟槽侧壁的硅元素发生氧化反应形成二氧化硅膜。
在逐步刻蚀牺牲介质层的过程中，氧离子会不断地溅射到沟槽侧壁，使得沟槽侧壁的二氧化硅膜变厚。由于沟槽侧壁是随着牺牲介质层逐渐消耗的过程而逐步裸露出来的，因此，沟槽侧壁越靠近沟槽开口方向裸露并发生氧化反应的时间越长，进而二氧化硅膜的厚度越厚；而越靠近沟槽底部方向的侧壁裸露并发生氧化反应的时间越短，因此形成的二氧化硅膜的厚度越薄。如此，就形成了厚度渐变的二氧化硅介质层。
当牺牲介质层完全被去除后，沟槽底部也会裸露出来，并发生氧化反应形成二氧化硅膜。这样，就可以使沟槽的内壁被氧化硅覆盖。
在一些实施例中，含氧等离子体包括水蒸气等离子体。
上述含氧等离子体可以采用水蒸气等离子体，即通过对水蒸气的电离，形成氢离子和氧离子的混合等离子体。这样，一方面成本较低，另一方面，可以提升反应的速度，并且便于控制。
此外，在一实施例中，还可以在水蒸气等离子体中混合惰性气体，以达到控制反应速度和反应程度的作用。
在一些实施例中，形成方法还包括：
回蚀刻氧化物介质层和导电层至目标深度，形成目标结构。
在本公开实施例的半导体结构中，由于沟槽可用于形成掩埋字线，即栅极结构被掩埋于衬底内部并由导电层连接为字线。而上述实施例中，形成的栅极介质层覆盖在整个沟槽的内壁上，因此，这里需要去除位于沟槽 开口处一定深度的侧壁上的栅极介质层，仅保留靠近沟槽底部的一部分栅极介质层。
导电层及氧化物介质层的表面可以低于沟槽的开口处，因此，这里可以通过回刻蚀氧化物介质层以及导电层至目标深度，进而形成上述位于沟槽内部且表面低于沟槽开口处的目标结构。
在一些实施例中，在氧化物介质层表面形成导电层，导电层形成在沟槽内，包括：
在形成氧化物介质层后，在沟槽内填充光阻材料，光阻材料的顶表面低于衬底的表面；
去除被光阻材料暴露的氧化物介质层；
去除光阻材料；
在沟槽内沉积导电层。
这里，可以在形成有氧化物介质层的沟槽内填充光阻材料，填充的光阻材料的厚度小于沟槽的深度。也就是说，填充光阻材料后，仍存在部分沟槽，并且有部分氧化物介质层裸露出来。
此时可以通过刻蚀或者清洗等手段去除裸露出来的氧化物介质层，示例性地，可以通过氢氟酸溶液去除氧化硅膜，而靠近沟槽底部的一部分氧化物介质层，则被光阻材料覆盖而不会被去除。
然后可以通过清洗去除光阻材料，使剩余的氧化物介质层裸露出来，从而便于后续继续形成导电层。示例性地，去除光阻材料的清洗液可以采用硫酸的水溶液。
当去除上述光阻材料后，沟槽被重新暴露出来，此时则可以在沟槽内沉积导电层，使导电层填充在氧化物介质层内。此时，导电层的表面可能高于氧化物介质层的表面，那么可以对导电层进一步进行回刻蚀，使其表面与氧化物介质层表面平齐或者低于氧化物介质层的表面。
通过这种方法，可以去除沟槽顶部一定高度内的氧化物介质层，使得沟槽的开口扩大，从而减少在形成栅极结构沉积导电层的过程中产生提前封口效应的影响。
在一些实施例中，在氧化物介质层表面形成导电层，导电层形成在沟槽内，包括：
在形成氧化物介质层后，在沟槽内填充光阻材料，光阻材料的顶表面低于衬底的表面；
去除光阻材料上方的氧化物介质层和部分隔离结构；
去除光阻材料；
在沟槽内沉积导电层。
在本公开实施例中，由于氧化物介质层与隔离结构的材料相同，因此，在进行刻蚀的过程中，会把光阻材料上方暴露出来的隔离结构与氧化物介质层同步刻蚀掉，形成一个凹槽。此时再去除光阻材料，则可以在沟槽内氧化物介质层之间沉积导电层。
这样，可以在沟槽开口处形成更大的开口，防止在沉积导电层时产生提前封口效应。
在一些实施例中，在沟槽内沉积导电层，包括：
在沟槽内沉积导电材料，控制导电材料至目标高度，以形成导电层，导电层的目标高度小于沟槽的高度。
在另一实施例中，导电层的目标高度不小于氧化介质层的高度。
在本公开实施例中，可以通过沉积的方法将金属材料填充至沟槽内，使其覆盖氧化物介质层。这里，沉积的方法可以包括物理气相沉积(Physical Vapor Deposition，PVD)或者原子层沉积(Atomic Layer Deposition，ALD)等。
这里，导电层的目标高度小于沟槽的高度，也就是说导电层的顶表面 可以与回刻蚀掉一部分的氧化物介质层的顶表面平齐，也可以略低于氧化物介质层的顶表面，但是导电层的顶表面需要低于沟槽顶部，并且导电层不能与沟槽侧壁的硅材料接触。这样，导电层就与氧化物介质层形成完整的栅极结构。
此外，由于沟槽沿着衬底表面的方向延伸，可以贯通多个有源区以及隔离层，因此，导电层也可以贯通形成一条字线。
在一些实施例中，如图3所示，形成方法还包括：
在导电层122和氧化物介质层121上覆盖绝缘层123，绝缘层123位于沟槽110内。
在形成上述导电层以及氧化物介质层后，可以在导电层以及氧化物介质层上覆盖绝缘层到达保护栅极结构的作用。
由于导电层以及氧化物介质层的顶表面低于衬底表面，也就是沟槽内形成栅极结构后仍存在一定的空间，因此，可以通过在沟槽内沉积绝缘材料的方式形成覆盖栅极结构的绝缘层，进而使得贯穿沟槽的导电层称为掩埋字线。
在一些实施例中，绝缘层包括：氮化硅层；
在其他实施例中，绝缘层还可以包括：氧化物，或者有机材料的薄膜。
在一些实施例中，在导电层和氧化物介质层上覆盖绝缘层的步骤包括：
在沟槽内通过低压力化学气相沉积的方法沉积绝缘材料，形成覆盖导电层和氧化物介质层的绝缘层。
在本公开实施例中，形成绝缘层可以通过低压力化学气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)的方式在沟槽内剩余的空间里沉积均匀的氮化硅，从而形成绝缘层覆盖栅极结构。
本公开实施例提供一种半导体结构，如图4所示，该半导体结构200包括：
衬底210；其中，衬底210上具有沟槽220；沟槽220内具有栅极结构230；
栅极结构230包括：氧化物介质层231和电层232，氧化物介质层231覆盖在沟槽220的侧壁上，导电层232位于覆盖有氧化物介质层231的沟槽220内；氧化物介质层231在沟槽220内的厚度由沟槽220的底部向沟槽220开口处延伸的方向厚度依次增大。
在本公开实施例中，衬底上可以具有多条沟槽，各个沟槽间隔排布，一个有源区上可以形成一个沟槽、二个沟槽甚至更多，这些沟槽可以在衬底上沿平行于衬底表面的方向平行分布。示例性地，多条沟槽之间可以相互平行且具有相等的间距、深度以及宽度，也可以具有不同的间距和宽度。
沟槽内具有栅极结构，栅极结构作为晶体管的开关控制结构，可以起到切换导电沟道的导电状态的作用。这里，栅极结构分布于沟槽内，形成掩埋字线。
栅极结构包括氧化物介质层和导电层，氧化物介质层用于隔离导电层与衬底，因此覆盖在沟槽的内壁上。在本公开实施例中，位于沟槽侧壁上的氧化物介质层具有厚度渐变的特点。氧化物介质层由沟槽底部到沟槽的开口的延伸方向上厚度依次增大，这样，沟槽底部的氧化物介质层较薄，从而保证了栅极结构的开关特性，同时，越靠近沟槽开口处的氧化物介质层越厚，减少了栅极与沟槽两侧衬底的交叠区域发生GIDL漏电的情况，提升了产品的可靠性和稳定性。
在一些实施例中，图5为半导体结构沿沟槽方向的截面图，如图5所示，半导体结构200，还包括：
在衬底上间隔排布的有源区240和填充在有源区240之间的隔离结构250，沟槽220位于有源区240和隔离结构250中。
在本公开实施例中，有源区可以为掺杂后的半导体材料，具有一定的 导电能力。有源区可以作为晶体管的源极区域以及漏极区域，在栅极控制电压的作用下驱动电荷在半导体沟道中传递。并且有源区可以通过接触结构与外接导线连接，实现电信号的传递。
间隔排布的有源区之间具有隔离结构，隔离结构可以为绝缘材料，包括二氧化硅、氮化硅或者其他有机物等材料。隔离结构可以在相邻的有源区之间起到电性隔离的作用，使得每个有源区能够用于独立的晶体管结构，从而构成晶体管的阵列结构。上述沟槽则形成于有源区与隔离结构内，并且栅极位于沟槽内，从而与有源区构成晶体管结构。
在一些实施例中，氧化物介质层形成在位于有源区的沟槽中。
在对沟槽内壁进行氧化处理的过程中，沟槽内的有源区的侧壁会被氧化形成上述氧化物介质层。若隔离结构的材料为二氧化硅，则与氧化物介质层的材料相同，因此，氧化物介质层形成后会与隔离区域连为一体。在一些实施例中，导电层和氧化物介质层的顶表面低于衬底的表面；如图5所示，半导体结构还包括：
绝缘层233，位于沟槽220内，覆盖在导电层232和氧化物介质层231上；其中，绝缘层233用于保护栅极结构。
由于导电层位于沟槽内，为了便于在衬底表面继续形成其他结构，包括存储电容、位线等结构，可以通过绝缘层将导电层覆盖。这样，栅极结构可以被掩埋于衬底内，减少与其他结构之间的电性干扰。
在一些实施例中，沟槽贯穿多个间隔排布的有源区和隔离结构；栅极结构在沟槽内连通，在平行于有源区的方向上，位于隔离结构中的栅极结构的表面宽度大于位于有源区中的栅极结构的表面宽度。在本公开实施例中，沟槽位于间隔的有源区和隔离结构中，并且沟槽可以贯穿多个有源区，从而作为半导体结构中的字线，提供多个晶体管的栅极控制信号。
在本公开的一个实施例中，如图6A所示，在平行于有源区延伸的方向 aa’上，有源区可被划分为多个由隔离结构隔开的区域，栅极结构610则贯穿于各有源区与隔离结构，形成多条字线。隔离结构可以是二氧化硅材质，在方向aa’上对有源区表面进行氧化时，隔离结构的表面不会被氧化形成氧化硅，而在去除有源区表面的氧化物介质层的时候，隔离结构也会被部分蚀刻，即在去除氧化物介质层的同时，隔离结构也会被部分蚀刻，在平行于aa’的方向上，最终导致形成在隔离结构中的栅极结构610表面宽度bb’大于位于有源区之间的栅极结构610的表面宽度cc’。
图6B是上述栅极结构所在表面的局部放大示意图，栅极结构610贯穿多个隔离结构611和有源区612，但是栅极结构610位于有源区612之间的表面宽度bb’大于栅极结构610位于隔离结构611中的表面宽度cc’。
在一些实施例中，半导体结构还包括：
接触结构，位于有源区的表面。
接触结构一方面与有源区的表面相连接，另一方面用于与外接的其他线路连接，例如，位线接触结构与位线连接，这样，位线上的信号可以通过位线接触结构传递至有源区。存储节点接触结构则与外接的存储电容相连接，当栅极控制信号使得晶体管导通时，位线传递的信号可以通过位线接触结构连接的有源区通过半导体导电沟道，然后再通过有源区和存储节点接触结构到达存储电容，从而实现数据的读写。
本公开实施例提供如下示例：
在DRAM等存储器产品中，字线用于提供控制晶体管导通的栅极控制信号，当晶体管导通时，电流从位线通过晶体管传递至存储电容。
如图7所示，从器件结构上，埋入式字线BWL的导电层的顶部希望与接触结构的底部平齐。这里的接触结构，包括位线接触结构(BLC)以及存储节点接触结构(NC)。但实际制造过程中不能做到完全对齐，接触结构以及离子注入区域N+与字线BWL之间存在交叠区域，导致漏电以及寄生 电容增加等问题。
在本公开实施例中，通过如下步骤形成具有渐变厚度的氧化物介质层，接近沟槽底部的氧化物介质层较薄，这样，导电层的底部具有良好的开关特性，并且寄生电容较小。而靠近沟槽顶部的氧化物介质层较厚，这样，可以减少导电层与接触结构以及离子注入区域之间的电场，从而降低发生GIDL等漏电不良的发生。
图8A为沿沟槽220延伸方向且位于沟槽中心的各步骤的截面示意图。
如图8A所示，可以在衬底上形成具有间隔排布的有源区240以及隔离结构250之后，形成垂直于有源区分布方向上的沟槽220。
在形成沟槽之前，可以在衬底表面覆盖掩膜层260，然后通过刻蚀形成沟槽220。形成沟槽后可以去除掩膜层260，当然，也可以在沟槽内的形成栅极结构之后再去除掩膜层260。由于有源区240为硅材料，隔离结构250为二氧化硅材料，因此，刻蚀沟槽的过程中需要同步向下刻蚀二氧化硅以及硅，形成一定深度的沟槽220，该深度即掩埋字线所需要的深度。
形成沟槽220后可以在沟槽220内沉积硼掺杂的非晶碳(BACL)形成牺牲介质层221，使其充满沟槽220。此时，沿垂直于沟槽延伸方向的截面示意图如图8B所示。
图9A为沿沟槽220延伸方向且位于沟槽中心的各步骤的截面示意图。如图9A所示，在形成牺牲介质层221后，可以通过氧气O 2和氢气H 2加等离子化的方式，形成水蒸气。通过等离子体溅射的方式使BACL从上向下逐渐被清洗掉，同时，等离子体中的氧离子会与逐渐裸露出的沟槽侧壁的硅元素发生氧化反应，形成二氧化硅薄膜。这样，就可以在沟槽侧壁上形成由上到下厚度逐渐变薄的二氧化硅薄膜作为氧化物介质层231，剩余的沟槽内的空间则会形成梯形的结构。并且这个过程中，可以通过控制气体流量的大小来控制BACL消耗的速度，进而控制氧化硅薄膜的厚度。
如图9A所示，由于栅极结构的高度小于沟槽的深度，因此，形成氧化物介质层231后需要减少氧化物介质层231覆盖的沟槽220侧壁的高度。这里，可以先在沟槽内沉积光阻材料(PR)222，沉积的厚度即为所需的栅极结构230的高度。此时，沿垂直于沟槽延伸方向的截面示意图如图9B所示。
接下来，如图9C所示，可以清洗掉光阻材料222上方的氧化硅薄膜，然后去除光阻材料222。这样，剩余的氧化硅薄膜则作为栅极结构的氧化物介质层231。再沉积氮化钛材料或者金属钨材料作为导电层232，最后再沉积绝缘层233覆盖导电层232。上述过程各步骤的截面对应立体视角的示意图如图9D所示。这样，剩余的沟槽内开口较大，能够有效填充金属材料，并刻蚀到所需的字线高度，减少提前封口效应的发生。最后再在剩余的沟槽220的空间内通过LPCVD的方式沉积氮化硅材料，或者通过硅烷(SiH 4)以及二氯氢硅(SiH 2Cl 2)反应形成氮化硅膜作为绝缘层233覆盖栅极结构230，形成掩埋的字线。其沿垂直于沟槽延伸方向的截面示意图如图10所示。
需要说明的是，本公开实施例中，硅、氧化硅以及氮化硅的刻蚀气体可以采用六氟化硫(SF 6)、四氟化碳(CF 4)、氯气(Cl 2)、三氟甲烷(CHF 3)、氧气(O 2)以及氩气(Ar)中一种或多种气体以一定比例的混合气体。
通过本公开实施例的技术方案，可以形成导电层由顶部到底部逐渐由厚变薄的栅极结构，这种结构能够有效降低GIDL的漏电情况。
此外，刻蚀掉字线上部分的氧化硅薄膜，使得形成栅极结构的过程中开口较大，从而可以减少提前封口效应。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中” 未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
以上所述，仅为本公开的实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
在本公开实施例中，在沟槽内填充牺牲介质层，并通过逐步刻蚀牺牲介质的过程中逐步暴露并氧化沟槽的侧壁。这样，沟槽底部的氧化物介质层较薄，从而使相应的栅极结构具有良好的开关特性，同时，越靠近沟槽开口处的氧化物介质层越厚，减少了对应形成的栅极结构与沟槽两侧有源区交叠区域发生GIDL漏电的情况，提升了产品的可靠性和稳定性。

Claims (18)

  1. 一种半导体结构的制造方法，包括：
    在衬底上形成沟槽；
    在所述沟槽内填充牺牲介质层；
    逐步蚀刻所述牺牲介质层以逐步暴露所述沟槽的侧壁，暴露的所述沟槽的侧壁至少部分氧化生成氧化物介质层，所述氧化物介质层在所述沟槽内的厚度由所述沟槽的底部向所述沟槽开口处延伸的方向上依次增大；
    在所述氧化物介质层表面形成导电层，所述导电层形成在所述沟槽内。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    在所述衬底上形成间隔排布的有源区和填充在所述有源区之间的隔离结构，所述沟槽形成在所述有源区和所述隔离结构中。
  3. 根据权利要求2所述的方法，其中，所述氧化物介质层形成在所述有源区的所述沟槽的侧壁。
  4. 根据权利要求1所述的方法，其中，所述牺牲介质层包括无掺杂非晶碳层或掺杂非晶碳层。
  5. 根据权利要求1所述的方法，其中，所述逐步蚀刻所述牺牲介质层以逐步暴露所述沟槽的侧壁，暴露的所述沟槽的侧壁氧化生成氧化物介质层，包括：
    采用含氧等离子体蚀刻所述牺牲介质层，并通过控制所述含氧等离子体的流量逐步刻蚀所述牺牲介质层；所述含氧等离子氧化所述沟槽的侧壁生成所述氧化物介质层。
  6. 根据权利要求5所述的方法，其中，所述含氧等离子体包括水蒸气等离子体。
  7. 根据权利要求1所述的方法，其中，所述方法还包括：
    回蚀刻所述氧化物介质层和所述导电层至目标深度，形成目标结构。
  8. 根据权利要求1所述的方法，其中，所述在所述氧化物介质层表面形成导电层，所述导电层形成在所述沟槽内，包括：
    在形成所述氧化物介质层后，在所述沟槽内填充光阻材料，所述光阻材料的顶表面低于所述衬底的表面；
    去除被所述光阻材料暴露的所述氧化物介质层；
    去除所述光阻材料；
    在所述沟槽内沉积导电层。
  9. 根据权利要求2所述的方法，其中，所述在所述氧化物介质层表面形成导电层，所述导电层形成在所述沟槽内，包括：
    在形成所述氧化物介质层后，在所述沟槽内填充光阻材料，所述光阻材料的顶表面低于所述衬底的表面；
    去除所述光阻材料上方所述氧化物介质层和部分所述隔离结构；
    去除所述光阻材料；
    在所述沟槽内沉积导电层。
  10. 根据权利要求8或9所述的方法，其中，所述在所述沟槽内沉积导电层，包括：
    在所述沟槽内沉积导电材料，控制所述导电材料至目标高度，以形成所述导电层，所述导电层的所述目标高度小于所述沟槽的高度。
  11. 根据权利要求10所述的方法，其中，所述导电层的所述目标高度不小于所述氧化介质层的高度。
  12. 根据权利要求1所述的方法，其中，所述方法还包括：
    在所述导电层和所述氧化物介质层上覆盖绝缘层，所述绝缘层位于所述沟槽内。
  13. 根据权利要求12所述的方法，其中，所述在所述导电层和所述氧化物介质层上覆盖绝缘层，包括：
    在所述沟槽内通过低压力化学气相沉积的方法沉积绝缘材料，形成覆盖所述导电层和所述氧化物介质层的绝缘层。
  14. 一种半导体结构，包括：
    衬底；其中，所述衬底上具有沟槽；所述沟槽内具有栅极结构；
    所述栅极结构包括：氧化物介质层和导电层，所述氧化物介质层覆盖在所述沟槽的侧壁上，所述导电层位于覆盖有所述氧化物介质层的沟槽内；所述氧化物介质层在所述沟槽内的厚度由所述沟槽的底部向所述沟槽开口处延伸的方向厚度依次增大。
  15. 根据权利要求14所述的半导体结构，其中，所述半导体结构还包括：
    在所述衬底上间隔排布的有源区和填充在所述有源区之间的隔离结构，所述沟槽位于所述有源区和所述隔离结构中。
  16. 根据权利要求15所述的半导体结构，其中，所述氧化物介质层形成在位于所述有源区的所述沟槽中。
  17. 根据权利要求14所述的半导体结构，其中，所述导电层和所述氧化物介质层的顶表面低于所述衬底的表面；所述半导体结构还包括：
    绝缘层，位于所述沟槽内，覆盖在所述导电层和所述氧化物介质层上；其中，所述绝缘层用于保护所述栅极结构。
  18. 根据权利要求14所述的半导体结构，其中，所述沟槽贯穿多个间隔排布的有源区和隔离结构；所述栅极结构在所述沟槽内连通，在平行于所述有源区的方向上，位于所述隔离结构中的所述栅极结构的表面宽度大于位于所述有源区中的所述栅极结构的表面宽度。
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