WO2023050902A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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Publication number
WO2023050902A1
WO2023050902A1 PCT/CN2022/099667 CN2022099667W WO2023050902A1 WO 2023050902 A1 WO2023050902 A1 WO 2023050902A1 CN 2022099667 W CN2022099667 W CN 2022099667W WO 2023050902 A1 WO2023050902 A1 WO 2023050902A1
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layer
gate
doped layer
gate structure
doped
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French (fr)
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孙辉
高彪
陈智斌
侯勇
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Huawei Digital Power Technologies Co Ltd
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Huawei Digital Power Technologies Co Ltd
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Priority to EP22874299.5A priority Critical patent/EP4383346A4/en
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Priority to US18/622,845 priority patent/US20240243179A1/en
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/012—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/0124—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group III-V semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a manufacturing method thereof.
  • the wide bandgap semiconductor gallium nitride has high breakdown electric field, high electron mobility and high electron saturation drift velocity, and has broad application prospects in the fields of power electronics and radio frequency microwave.
  • gallium nitride devices mainly include devices based on aluminum gallium nitride (AlGaN)/GaN heterostructures, such as high electron mobility transistors (HEMTs) made with AlGaN/GaN heterojunctions as the core.
  • AlGaN aluminum gallium nitride
  • HEMTs high electron mobility transistors
  • the piezoelectric polarization and spontaneous polarization produced by AlGaN/GaN will form a high-concentration two-dimensional electron gas (2-DEG) at the interface of the heterojunction, and its mobility and saturation velocity are far away. higher than silicon.
  • a doped layer can be formed on the surface of the AlGaN/GaN heterojunction in the gate region, and a gate structure is formed on the doped layer to form a stack of the doped layer and the gate structure.
  • the impurity layer can be a p-type GaN (p-GaN) layer or a p-type AlGaN (p-AlGaN).
  • p-GaN p-GaN
  • p-AlGaN p-type AlGaN
  • embodiments of the present application provide a semiconductor device and a manufacturing method thereof, so as to improve the performance of the device.
  • the semiconductor device may include sequentially stacked channel layer and barrier layer, and doped layer and gate structure, channel layer and barrier
  • the layer is made of group III nitride material
  • the barrier layer has a gate region
  • the doped layer is located on the side of the barrier layer away from the channel layer
  • the doped layer is located in the gate region
  • the material of the doped layer is containing
  • the gate structure is located on the side of the doped layer away from the channel layer
  • the side wall of the gate structure facing the doped layer is different from the side wall of the doped layer.
  • the retraction structure of the side wall of the gate structure facing the doped layer cuts off the contact between the side wall of the gate structure facing away from the doped layer and the side wall of the doped layer, which is equivalent to isolating the gate structure and the doped layer.
  • the leakage channel between the doped layers reduces the leakage current of the device and improves the performance of the device.
  • the material of the channel layer is gallium nitride
  • the material of the barrier layer is aluminum gallium nitride
  • the material of the doped layer is nitrogen containing acceptor-type doping elements. gallium nitride or aluminum gallium nitride.
  • the material of the channel layer may be gallium nitride
  • the material of the barrier layer may be aluminum gallium nitride
  • a two-dimensional electron gas may be formed at the interface between the two
  • the material of the doped layer may contain acceptor Gallium nitride or aluminum gallium nitride with doped elements can better deplete the two-dimensional electron gas in the depletion gate region, and at the same time, the doped layer has better contact with the barrier layer, which is beneficial to improve device performance.
  • a dielectric structure is provided on the periphery of the side wall of the gate structure facing the doped layer, so that the side wall of the gate structure facing away from the doped layer, The sidewall of the dielectric structure is flush with at least part of the sidewall of the doped layer.
  • the side wall of the gate structure facing the doped layer forms a recessed structure
  • a dielectric structure can be arranged on its periphery, so that the side wall of the gate structure facing away from the doped layer and the side wall of the dielectric structure And at least part of the sidewalls of the doped layer are flush, that is, the recessed structure is filled with a dielectric structure, so that the overall structure is stable, and at the same time, the dielectric structure can better block the gap between the sidewalls of the gate structure and the sidewalls of the doped layer.
  • the leakage channel between them is beneficial to improve the performance of the device.
  • a dielectric structure is provided on the periphery of the side wall of the gate structure facing the doped layer, so that the side wall of the gate structure facing away from the doped layer and The sidewalls of the dielectric structure are flush; at least part of the sidewalls of the doped layer are not parallel to the sidewalls of the dielectric structure.
  • the side wall of the gate structure facing the doped layer forms a recessed structure
  • a dielectric structure can be arranged on its periphery, so that the side wall of the gate structure facing away from the doped layer and the side wall of the dielectric structure flush, and at least part of the sidewalls of the doped layer are not parallel to the sidewalls of the dielectric structure, that is, the dielectric structure is used to fill the recessed structure.
  • the dielectric structure can fill the recessed structure or not fill the recessed structure. The filling of the recess structure stabilizes the overall structure, and at the same time, the dielectric structure can better block the leakage channel between the sidewall of the gate structure and the sidewall of the doped layer, which is beneficial to improving device performance.
  • the material of the dielectric structure includes at least one of the following materials: SiO 2 , SiON, SiNx, AlOx, AlNx, GaOx, TiOx.
  • the material of the dielectric structure can be a material with good insulation, so as to better block the leakage channel between the gate structure and the sidewall and the sidewall of the doped layer, which is beneficial to improve the performance of the device.
  • the dielectric structure surrounds the gate structure, and the widths of multiple parts of the dielectric structure located on different sides of the gate structure Not exactly the same.
  • the dielectric structure can surround the gate structure from all sides, so as to fill the depression of the side wall of the gate structure facing the doped layer from each side wall, and the width of multiple parts of the dielectric structure located on different sides Not exactly the same, so that the device can adapt to more application scenarios.
  • the size of the dielectric structure in a direction perpendicular to the surface of the channel layer is less than 5 microns.
  • the thickness of the dielectric structure is less than 5 microns, so that the thickness of the dielectric structure is small, so that when the dielectric structure is etched, whether it is dry etching or wet etching, the barrier layer will be damaged. Smaller, which is beneficial to improve device performance.
  • the material of the gate structure includes at least one of the following materials: Ti, TiN, W, Ni, NiV, Ta, TaN, Pd, Pt, WSi 2 , Au.
  • the material of the gate structure may be a material with better conductivity, so as to improve device performance.
  • the semiconductor device further includes:
  • a source and a drain are located on the side of the barrier layer away from the channel layer, and the source and the drain are respectively located on the side of the gate region sides.
  • the source and the drain on both sides of the gate region may also be included to form a complete device and achieve higher device performance.
  • the semiconductor device further includes:
  • the base is located on a side of the channel layer away from the barrier layer.
  • a substrate may be provided on the side of the channel layer away from the barrier layer to support the film layer provided on the substrate and improve the reliability of the device.
  • the semiconductor device further includes:
  • a buffer layer between the substrate and the channel layer.
  • a buffer layer may also be provided between the substrate and the channel layer, so as to improve the quality of the channel layer and improve device performance.
  • a method for manufacturing a semiconductor device including:
  • a barrier layer, a doping material layer and a dielectric material layer are sequentially formed;
  • the channel layer is composed of a group III nitride material,
  • the barrier layer is composed of a group III nitride material, and the barrier layer is composed of a group III nitride material.
  • the layer has a gate region;
  • the material of the doping material layer is a group III-V compound containing acceptor-type doping elements;
  • the material of the channel layer is gallium nitride
  • the material of the barrier layer is aluminum gallium nitride
  • the material of the doped layer is nitrogen containing acceptor-type doping elements. gallium nitride or aluminum gallium nitride. .
  • the sidewall of the dielectric structure is flush with at least part of the sidewall of the doped layer; and/or, at least part of the sidewall of the doped layer is flush with the sidewall of the dielectric structure
  • the walls are not parallel.
  • the method before etching the gate material, the dielectric material layer, and the dopant material layer, the method further includes:
  • Forming a hard mask layer on the gate material etching the gate material, dielectric material layer, and doping material layer while also etching the hard mask layer;
  • the gate material, dielectric material layer, and doping material layer After etching the gate material, dielectric material layer, and doping material layer, it also includes:
  • the gate structure is etched by wet etching, so that at least one side wall of the gate structure is flush.
  • the gate structure by wet etching after etching the gate structure by wet etching, it further includes:
  • the material of the dielectric structure includes at least one of the following materials: SiO 2 , SiON, SiNx, AlOx, AlNx, GaOx, TiOx.
  • the dielectric structure surrounds the gate structure, and the widths of multiple parts of the dielectric structure located on different sides of the gate structure Not exactly the same.
  • the dimension of the dielectric structure in a direction perpendicular to the surface of the channel layer is less than 5 um.
  • the dielectric material layer located on the doped material layer in the gate region is etched through dry etching or wet etching.
  • the material of the gate structure includes at least one of the following materials: Ti, TiN, W, Ni, NiV, Ta, TaN, Pd, Pt, WSi 2 , Au.
  • the method also includes:
  • a source and a drain are formed on the barrier layer; the source and the drain are respectively located on both sides of the gate region.
  • a substrate is provided on a side of the channel layer away from the barrier layer.
  • a buffer layer is disposed between the channel layer and the substrate.
  • a third aspect of the embodiments of the present application provides an electronic device, including a circuit board, and a semiconductor device connected to the circuit board as provided in the first aspect of the present application.
  • the embodiment of the present application provides a semiconductor device and its manufacturing method.
  • the semiconductor device may include a channel layer and a barrier layer stacked in sequence, as well as a doped layer and a gate structure.
  • the channel layer and the barrier layer are made of group III nitride Composed of materials
  • the barrier layer has a gate region
  • the doped layer is located on the side of the barrier layer away from the channel layer
  • the doped layer is located in the gate region
  • the material of the doped layer is an acceptor-type doping element III-V compound
  • the gate structure is located on the side of the doped layer away from the channel layer
  • the side wall of the gate structure facing the doped layer is retracted relative to the side wall of the doped layer
  • the gate The side wall of the structure facing the doped layer is retracted relative to the side wall of the gate structure facing away from the doped layer, so that the side walls of the gate structure and the doped layer are not in the same plane, and the gate structure
  • FIG. 1 is a schematic structural diagram of a gallium nitride device
  • FIGS. 2-9 are schematic structural diagrams of semiconductor devices provided by embodiments of the present application.
  • FIG. 10 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.
  • 11-22 are schematic diagrams of the device structure during the manufacturing process of the semiconductor device provided by the embodiment of the present application.
  • Embodiments of the present application provide a semiconductor device and a manufacturing method thereof, so as to improve the photoelectric conversion efficiency of the device.
  • a doped layer may be formed on the surface of the AlGaN/GaN heterojunction in the gate region, and a gate structure is formed on the doped layer to form a stack of the doped layer and the gate structure.
  • the doped layer can be a p-type GaN (p-GaN) layer or a p-type AlGaN (p-AlGaN).
  • the doped layer can deplete the two-dimensional electron gas channel in the gate region, and between the gate regions The outer non-gate region does not form a doped layer, so that the gate region has no channel, and the non-gate region has a channel, so that the gate is used to control the channel.
  • the gate and the sidewall of the doped layer will form a leakage channel, which will affect electrical parameters such as gate leakage (Igleak). This is because during the etching process of the gate structure and the doped layer, etching damage will inevitably be formed on the sidewalls of the gate structure and the doped layer, and the damaged position traps charges to form a leakage current.
  • Igleak gate leakage
  • the gallium nitride device may include a stacked GaN layer 100 and an AlGaN layer 110, and the AlGaN layer 110 may include an AlGaN/GaN heterojunction surface gate
  • the gate structure and the doped layer can be etched through a hard mask, so that the sidewalls of the gate structure and the doped layer are flush, and then the gate structure is etched laterally by a wet method to make the sidewalls of the gate structure opposite to each other. Because the sidewall of the doped layer is retracted, the connection between the sidewall of the gate structure and the sidewall of the doped layer is cut off, and the leakage channel is prevented from being formed between the sidewall of the gate structure and the sidewall of the doped layer.
  • the sidewall of the gate structure is easy to form a thin degenerated layer during the etching process, which will affect the gate structure.
  • the etching of the sidewall finally makes the sidewall of the gate structure uneven when forming the stepped structure, forming a jagged shape, which affects the subsequent process and the resulting stepped structure has poor morphology.
  • the semiconductor device may include sequentially stacked channel layers and barrier layers, as well as a doped layer and a gate structure, and the barrier layer has a gate region, the channel layer and the barrier layer are composed of group III nitride materials, the doped layer is located on the side of the barrier layer away from the channel layer, and the doped layer is located in the gate area, and the material of the doped layer is containing the affected
  • the III-V group compound of the bulk doping element the gate structure is located on the side of the doped layer away from the channel layer, and the side wall of the gate structure facing the doped layer is different from the side wall of the doped layer.
  • the retraction structure of the side wall of the gate structure facing the doped layer cuts off the contact between the side wall of the gate structure facing away from the doped layer and the side wall of the doped layer, which is equivalent to isolating the gate structure and the doped layer.
  • the leakage channel between the doped layers reduces the leakage current of the device and improves the performance of the device.
  • the semiconductor device may include a channel layer 220 , a barrier layer 230 , a doped layer 240 and a gate structure 250 stacked in sequence.
  • the channel layer 220 is made of group III nitride material
  • the barrier layer 230 is made of group III nitride material.
  • the material of the channel layer 220 can be gallium nitride
  • the material of the barrier layer 230 can be nitride One of aluminum gallium, aluminum nitride, etc.
  • the channel layer 220 and the barrier layer 230 form a heterostructure, such as a heterostructure of AlGaN/GaN, thereby generating a two-dimensional electron gas, and the semiconductor device formed based on this It is possible to work with the two-dimensional electron gas generated by this heterostructure.
  • the semiconductor device may be, for example, a heterostructure-based high-electron-mobility transistor (high-electron-mobility transistor, HEMT) device.
  • the thickness of the channel layer 220 can be relatively large, then the channel layer 220 can be used as a base, and the base provides support for the film layer on it, for example, the material of the channel layer 220 is gallium nitride. It can be used as a substrate and as a component of AlGaN/GaN heterostructure.
  • the channel layer 220 can be thinner, and the channel layer 220 can be formed on the substrate 200.
  • the substrate 200 is arranged on the side of the channel layer 220 away from the barrier layer 230.
  • the substrate 200 Provide support for the film layer on it, the channel layer 220 is a component of the heterostructure, wherein the material of the substrate 200 can be a III-V compound semiconductor material, which can be aluminum nitride (AlN), silicon (Si) , silicon carbide (SiC), and one or more of sapphire.
  • a buffer layer 210 may also be provided between the substrate 200 and the channel layer 220.
  • the material of the buffer layer 210 may be aluminum nitride or gallium nitride grown at a low temperature.
  • the channel layer 220 can be a high-temperature grown gallium nitride layer, so that the low-temperature gallium nitride layer acts as a buffer layer 210 between the high-temperature gallium nitride layer and the substrate 200, improving the high-temperature gallium nitride layer. epitaxial quality.
  • the barrier layer 230 may have a gate region 1001 and a non-gate region 1002 around the gate region 1001.
  • the gate region 1001 is an area on the surface of the barrier layer 230, including the surface of the barrier layer 230 and the surface vertical to the surface of the barrier layer 230. A space defined by countless straight lines.
  • the gate region 1001 is used to form the gate structure 250.
  • the gate region 1001 may be larger than the region where the gate structure 250 is located, or may be equal to the region where the gate structure 250 is located.
  • the dashed box in the middle represents the gate region 1001
  • the two sides of the gate region 1001 represent the non-gate region 1002, and the subsequent structural schematic diagrams adopt the same representation method. Since FIG. 1001 is an annular area, such as a circular area or a polygonal area.
  • a doped layer 240 may be formed on the surface of the barrier layer 230 in the gate region 1001, that is, the doped layer 240 is disposed on the side of the barrier layer 230 away from the channel layer 220, and doped The impurity layer 240 is located in the gate region 1001 .
  • the material of the doped layer 240 can be a group III-V compound containing an acceptor-type doping element, for example, the material of the doped layer 240 can be gallium nitride or aluminum nitride containing an acceptor-type (P-type) doping element Gallium, correspondingly, the doped layer can be expressed as p-type GaN (p-GaN) or p-type AlGaN (p-AlGaN).
  • the doped layer 240 can be used to deplete the two-dimensional electron gas channel of the gate region 1001, and the non-gate region 1002 outside the gate region 1001 does not form a doped layer, so that the gate region 1001 has no channel and is not a gate region. Region 1002 has a channel, and gate structure 250 is used to control the channel.
  • a gate structure 250 is formed on the doped layer 240 , and the gate structure 250 is disposed on a side of the doped layer 240 away from the channel layer 220 .
  • the material of the gate structure 250 may have good electrical conductivity, and the material may be at least one of Ti, TiN, W, Ni, NiV, Ta, TaN, Pd, Pt, WSi 2 , and Au.
  • the side wall of the gate structure 250 facing the doped layer 240 is retracted relative to the side wall of the doped layer 240 , and the side wall of the gate structure 250 facing the doped layer 240 is relatively
  • the side wall of the gate structure 250 facing away from the doped layer 240 is retracted, so that in the direction along the surface of the barrier layer 230, the size of the part of the gate structure 250 facing the doped layer 240 is smaller than that of the gate structure 250 away from The size of the part of the doped layer 240 is smaller than the size of the doped layer 240, and the part of the gate structure 250 facing the doped layer 240 constitutes a recessed structure as a whole, finally making the sidewall of the gate structure 250 and the doped layer 240
  • the sidewalls of the gate structure 250 and the sidewalls of the doped layer 240 are not in the same plane, thereby blocking the continuity of the sidewalls of the gate structure 250 and the sidewalls of the doped layer 240 , and avoiding the leak
  • the gate structure 250 has a side wall 251 facing the doped layer 240 as part of the side wall of the gate structure 250, and a side wall 252 facing away from the doped layer 240 as the other side wall of the gate structure 250.
  • a part of the sidewall and the two parts of the sidewall together constitute the sidewall of the gate structure 250 .
  • the side wall 251 facing the doped layer 240 is not only retracted relative to the side wall of the doped layer 240, but also retracted compared to the side wall facing away from the doped layer 240, forming a retracted structure, so that the gate
  • the sidewalls of the pole structure 250 and the sidewalls of the doped layer 250 are not in the same plane.
  • the retraction structure of the side wall 251 of the gate structure 250 facing the doped layer 240 cuts off the continuity between the side wall of the gate structure 250 and the side wall of the doped layer 240, which is equivalent to cutting off the gate structure.
  • the leakage channel between the doped layer 250 and the doped layer 240 reduces the leakage current of the device and improves the performance of the device.
  • the actual gate structure 250 forms a polygonal structure in the plane parallel to the barrier layer 230, and the retraction structure is formed on at least one side wall of the gate structure 250, for example, it can be formed On all sidewalls of the gate structure 250, the retraction structure forms a closed loop.
  • the side wall 251 of the gate structure 250 facing the doped layer 240 is perpendicular to the surface of the doped layer 240 facing the gate structure 250, that is, the side wall and the doped layer 240 facing the gate
  • the included angle between the structure 250 and the part of the surface not covered by the gate structure 250 is equal to 90°, as shown in FIG. 2 . That is to say, the side wall 251 of the gate structure 250 facing the doped layer 240 is not continuous with the side wall of the doped layer 240, and the side wall 252 of the gate structure 250 facing away from the doped layer 240 is not continuous. continuous.
  • the sidewall 251 of the gate structure 250 facing the doped layer 240 may not be perpendicular to the surface of the doped layer 240 facing the doped structure 250 , that is, the sidewall and the doped layer 240
  • the included angle between the partial surfaces facing the gate structure 250 and not covered by the gate structure 250 is not equal to 90°, for example, less than 90°.
  • FIG. 3 it is another semiconductor device provided by the embodiment of the present application. Schematic. That is to say, the side wall 251 of the gate structure 250 facing the doped layer 240 is discontinuous with the side wall of the doped layer 240, and the side wall 251 of the gate structure 250 facing the doped layer 240 is not continuous with the doped layer 240.
  • the intersecting angle is not equal to 90°, for example, less than 90°, while a part of the gate structure 250 facing the doped layer 240
  • the sidewall 251 intersects with the sidewall 252 of the gate structure 250 facing away from the doped layer 240 , and the intersecting angle is not equal to 90°, for example greater than 90°. Therefore, when the side wall 251 of the gate structure 250 facing the doped layer 240 is not perpendicular to the surface of the doped layer 240 facing the doped structure 250, the side of the gate structure 250 facing away from the doped layer 240 can still be blocked.
  • the contact between the wall 252 and the sidewall of the doped layer 240 can block the leakage channel between the gate structure 250 and the doped layer 240, thereby reducing the leakage current of the device and improving the performance of the device.
  • a dielectric structure 260 can be provided on the periphery of the sidewall 251 facing the doped layer 240 of the gate structure 250, as shown in FIG. 4 , which is another semiconductor device provided in the embodiment of the present application.
  • the schematic diagram of the structure that is, there is a dielectric material in the retracted structure of the side wall 251 of the gate structure 250 facing the doped layer 240, forming a dielectric structure 260, and the dielectric material fills the retracted structure, so that the formed dielectric structure 260
  • the sidewall is flush with the sidewall 252 on the side of the gate structure 250 away from the doped layer 240, so that the sidewall of the dielectric structure 260 is located at the sidewall 252 on the side of the gate structure 250 away from the doped layer 240 and the side of the doped layer 240.
  • a dielectric material is used to isolate the leakage channel between the gate structure 250 and the doped layer 240 .
  • the material of the dielectric structure 260 can be a material with better insulation, and the material can be at least one of SiO 2 , SiON, SiNx, AlOx, AlNx, GaOx, and TiOx.
  • the sidewall of the dielectric structure 260 is flush with the sidewall 252 of the side of the gate structure 250 facing away from the doped layer 240, and the sidewall of the dielectric structure 260 may be at least part of the sidewall of the doped layer 240.
  • the dielectric structure 260 may be flush with all sidewalls of the doped layer 240 , or may be flush with a part of the sidewalls of the doped layer 240 .
  • the sidewall 252 of the gate structure 250 facing away from the doped layer 240 , the sidewall of the dielectric structure 260 and the sidewall of the doped layer 240 are flush with each other, as shown in FIG. 4 .
  • the side wall 251 of the gate structure 250 facing the doped layer 240 is not in the same plane as the side wall of the doped layer 240, and the side wall of the dielectric structure 260 is located on a side of the gate structure 250 away from the doped layer 240.
  • a dielectric material is used to isolate the leakage channel between the gate structure 250 and the doped layer 240 .
  • the sidewall 252 of the gate structure 250 facing away from the doped layer 240 , the sidewall of the dielectric structure 260 and part of the sidewall of the doped layer 240 are flush.
  • the sidewall of the doped layer 240 includes a sidewall 241 facing the gate structure 250 and a side facing away from the gate structure 250
  • the sidewall 242, the sidewall 241 of the doped layer 240 facing the gate structure 250, the sidewall 252 of the gate structure 250 away from the doped layer 240 is flush with the sidewall of the dielectric structure 260, the doped layer 240
  • the sidewall 242 of the side away from the gate structure 250 is not flush with the sidewall of the dielectric structure 260.
  • the sidewall 242 of the doped layer 240 away from the gate structure 250 can be aligned with the sidewall of the dielectric structure 260 parallel to, or not parallel to, the sidewall of
  • the sidewall of the dielectric structure 260 is flush with the sidewall 252 of the side of the gate structure 250 facing away from the doped layer 240, and the sidewall of the dielectric structure 260 may be at least part of the sidewall of the doped layer 240.
  • the dielectric structure 260 may not be parallel to all sidewalls of the doped layer 240 , or may not be parallel to a part of the sidewalls of the doped layer 240 .
  • the sidewall 252 of the gate structure 250 facing away from the doped layer 240 is flush with the sidewall of the dielectric structure 260, and the sidewall of the doped layer 240 is not parallel to the sidewall of the dielectric structure 260.
  • the angle between the sidewall of the doped layer 240 and the sidewall of the dielectric structure 260 is not equal to 90°, for example, greater than 90°, Finally, a structure in which the sidewalls of the gate structure 250 and the sidewalls of the doped layer 250 are not in the same plane is formed.
  • the side wall 252 of the gate structure 250 facing away from the doped layer 240 is flush with the side wall of the dielectric structure 260 , and part of the side wall of the doped layer 240 is flush with the side wall of the dielectric structure 260 If not parallel, another part of the sidewall of the doped layer 240 may or may not be flush with the sidewall of the dielectric structure 260 .
  • the sidewall of the doped layer 240 includes a sidewall 241 facing the gate structure 250 and a sidewall facing away from the gate structure 250 .
  • the sidewall 242 of the sidewall 241 of the doped layer 240 facing the gate structure 250, the sidewall 252 of the side of the gate structure 250 away from the doped layer 240 is flush with the sidewall of the dielectric structure 260, and the doped layer
  • the sidewall 242 of 240 facing away from the gate structure 250 is not parallel to the sidewall of the dielectric structure 260 , and the angle between them is not equal to 90°, for example greater than 90°.
  • the embodiment of the present application provides various sidewalls of the gate structure 250 and the sidewalls of the doped layer 240
  • the design meets various needs in practical applications and has a great application prospect.
  • FIG. 4-FIG. 7 are cross-sectional views, in fact, in a plane parallel to the surface of the channel layer 220, the retraction structure can be located on each sidewall of the gate structure 250, and the dielectric structure 260 The gate structure 250 may be surrounded.
  • the widths of multiple parts of the dielectric structure 260 located on different sides of the gate structure 250 are not completely the same,
  • the width here refers to the distance between the sidewall of the dielectric structure 260 and the sidewall 251 of the gate structure 250 close to the doped layer 240 .
  • FIG. 8 which is a structural schematic diagram of yet another semiconductor device provided by an embodiment of the present application, the width of the first portion 261 of the dielectric structure 260 on the left side of the gate structure 250 is larger than that of the dielectric structure 260 on the right side of the gate structure 250.
  • the width of the second portion 262 of the structure 260 is a structural schematic diagram of yet another semiconductor device provided by an embodiment of the present application.
  • the design of the gate structure 250 with such an asymmetric structure can meet the individual design requirements of certain devices, and has great application prospects.
  • the size of the dielectric structure in the direction vertical to the surface of the channel layer 220 is less than 5 micrometers (um), for example, less than 500 nm, that is, the film layer formed by the dielectric material is relatively thin, and the dielectric structure is obtained after etching 260 reduces damage to the surface of the doped layer 240, avoids leakage current due to etching damage, and improves device performance.
  • the semiconductor device may also include a source 253 and a drain 254, and a source 253 and a drain 254 is located on the side of the barrier layer 230 in the non-gate region 1002 away from the channel layer 220 , and the source 253 and drain 254 are located on both sides of the gate region 1001 .
  • Both the source electrode 253 and the drain electrode 254 are made of materials with better conductivity, and the materials of the source electrode 253 and the drain electrode 254 are: Ti, TiN, W, Ni, NiV, Ta, TaN, Pd, Pt, WSi 2 , Au at least one of .
  • the semiconductor device may include a channel layer and a barrier layer stacked in sequence, as well as a doped layer and a gate structure.
  • the channel layer and the barrier layer are composed of group III nitride materials.
  • the barrier layer has a gate region, the doped layer is located on the side of the barrier layer away from the channel layer, and the doped layer is located in the gate region, and the material of the doped layer is III-V including acceptor type doping elements group compound, the gate structure is located on the side of the doped layer away from the channel layer, the side wall of the gate structure facing the doped layer is retracted relative to the side wall of the doped layer, and the direction of the gate structure is The side wall of one side of the doped layer is retracted relative to the side wall of the gate structure away from the doped layer, so that the side walls of the gate structure and the doped layer are not in the same plane, and the direction of the gate structure is doped.
  • the retracted structure of one side wall of the gate structure cuts off the contact between the side wall of the gate structure away from the doped layer and the side wall of the doped layer, which is equivalent to cutting off the leakage channel between the gate structure and the doped layer, Therefore, the leakage current of the device is reduced,
  • the embodiment of the present application also provides a method for manufacturing a semiconductor device.
  • FIG. 10 it is a flowchart of a method for manufacturing a semiconductor device provided by the embodiment of the present application.
  • FIG. 11-FIG. 22 are structural schematic diagrams of semiconductor devices during the manufacturing process, and the method may include:
  • the channel layer 220 is made of a group III nitride material
  • the barrier layer 230 is made of a group III nitride material.
  • the material of the channel layer 220 can be gallium nitride
  • the barrier layer 230 The material can be aluminum gallium nitride.
  • the stacked channel layer 220 and barrier layer 230 form an AlGaN/GaN heterostructure, thereby generating a two-dimensional electron gas.
  • the semiconductor device formed based on this can take advantage of this heterostructure Two-dimensional electron gas work generated by the structure.
  • the semiconductor device may be, for example, a heterostructure-based high-electron-mobility transistor (high-electron-mobility transistor, HEMT) device.
  • high-electron-mobility transistor high-electron-mobility transistor
  • the thickness of the channel layer 220 can be relatively large, then the channel layer 220 can be used as a base, and the base provides support for the film layer on it, for example, the material of the channel layer 220 is gallium nitride. It can be used as a substrate and as a component of AlGaN/GaN heterostructure.
  • the thickness of the channel layer 220 can be relatively thin, as shown in FIG.
  • the channel layer 220 serves as a component of the heterostructure, wherein the material of the substrate 200 can be a III-V group compound semiconductor material, and can be one of aluminum nitride (AlN), silicon (Si), silicon carbide (SiC), and sapphire. one or more species.
  • a buffer layer 210 may also be provided between the substrate 200 and the channel layer 220, and the material of the buffer layer 210 may be aluminum nitride, or gallium nitride grown at a low temperature.
  • the buffer layer 210 can be formed on the surface of the substrate 200 first, then the channel layer 220 is formed on the buffer layer 210, and then the barrier layer 230, the doping material layer 201 and the dielectric material layer are sequentially formed on the channel layer 220 202.
  • the channel layer 220, the barrier layer 230, the dopant material layer 201 and the dielectric material layer 202 may be formed by metal organic chemical vapor deposition (MOCVD).
  • the barrier layer 230 may have a gate region 1001 and a non-gate region 1002 around the gate region 1001, the gate region 1001 is an area on the surface of the barrier layer 230, including the surface of the barrier layer 230 And the space defined by countless straight lines perpendicular to the surface of the barrier layer 230 .
  • the gate region 1001 is used to form the gate structure 250.
  • the gate region 1001 may be larger than the region where the gate structure 250 is located, or may be equal to the region where the gate structure 250 is located.
  • the dashed box in the middle represents the gate region 1001
  • the two sides of the gate region 1001 represent the non-gate region 1002, and the subsequent structural schematic diagrams adopt the same representation method. Since FIG. 1001 is an annular area, such as a circular area or a polygonal area.
  • the material of the doping material layer 201 may be a III-V group compound containing an acceptor-type doping element, for example, the material of the doping material layer 201 may be nitrogen containing an acceptor-type doping element.
  • Gallium nitride or aluminum gallium nitride, that is, the doped layer can be p-type GaN (p-GaN) or p-type AlGaN (p-AlGaN).
  • the material of the dielectric material layer 202 can be an insulating material, and the material can be at least one of SiO 2 , SiON, SiNx, AlOx, AlNx, GaOx, and TiOx.
  • the dielectric material layer 202 located in the gate region 1001 may be etched to form a gate region trench penetrating the dielectric material layer 202 to the doped material layer 201 203.
  • the gate region trench 203 is located in the gate region 1001 for forming the gate structure 250 .
  • the photoresist can be spin-coated on the dielectric material layer 202, and then the photoresist is exposed and developed to expose the dielectric material layer 202 located in the gate region 1001, and then the exposed dielectric material layer 202 located in the gate region
  • the dielectric material layer 202 of 1001 is etched to obtain a gate region trench 203 that penetrates the dielectric material layer 202, and finally the photoresist is removed.
  • the photoresist can be removed by dry etching and wet etching, or by other methods .
  • the size of the dielectric material layer 202 is less than 5 micrometers (um), such as less than 500nm, that is, the film layer formed by the dielectric material is relatively thin, and the thickness of the dielectric material layer 202 is relatively thin.
  • the etching is easy to control, and the damage to the surface of the dopant material layer 201 is reduced when the dielectric material layer 202 is etched, the leakage current caused by the etching damage is avoided, and the device performance is improved.
  • the dielectric material layer 202 is relatively thin, the gate region trench 203 can be obtained by dry etching, or the gate region trench 203 can be obtained by wet etching.
  • the dielectric material layer 202 and the underlying doping material layer 201 may have a higher selectivity ratio, further reducing etching damage to the doping material layer 201 .
  • the gate material 204 may be continuously deposited, so that the gate material fills the gate trench 203 and covers the dielectric material layer 202 .
  • the gate material may have good electrical conductivity, and its material may be at least one of Ti, TiN, W, Ni, NiV, Ta, TaN, Pd, Pt, WSi 2 , and Au.
  • the deposition method of the gate material 204 may be physical vapor deposition (Physical Vapor Deposition, PVD).
  • the gate material 204 after depositing the gate material 204, the gate material 204, the dielectric material layer 202, and the dopant material layer 201 located outside the gate region 1001 are etched, and finally a gate material located in the gate region 1001 is formed.
  • the width of the doped layer 240 is greater than the width of the trench 203 in the gate region, that is, the side wall 251 of the gate structure 250 facing the doped layer 240 is finally formed.
  • a dielectric structure 260 is disposed on the periphery, so that the side wall 252 of the gate structure 250 facing away from the doped layer 240 is flush with the side wall of the dielectric structure 260 .
  • photoresist can be spin-coated on the gate material 204.
  • the width of the photoresist is greater than the width of the gate trench 203, and then the photoresist is exposure and development to expose the gate material 204, dielectric material layer 202, and dopant material layer 201 located outside the gate region 1001, and then sequentially expose the gate material 204 and dielectric material located outside the gate region 1001.
  • Layer 202 and dopant material layer 201 are dry-etched, and the gate material 204, dielectric material layer 202, and dopant material layer 201 located in the gate region 1001 are retained, and finally the photoresist is removed, and the photoresist can be dry-etched Etching and wet etch removal can also be utilized in other ways.
  • the gate shown in FIG. 2 can be formed.
  • a structure in which the angle between the side wall 251 of the pole structure 250 facing the doped layer 240 and the part of the surface 241 of the doped layer 240 facing the gate structure 250 and not covered by the gate structure 250 is equal to 90°.
  • the angle between the sidewall of the gate trench 203 and the bottom surface of the gate trench 203 is not equal to 90°, for example greater than 90°, the gate structure shown in FIG. 3 can be formed.
  • the angle between the side wall 251 facing the doped layer 240 of the doped layer 250 and the part of the surface 241 of the doped layer 240 facing the gate structure 250 and not covered by the gate structure 250 is not equal to 90°, for example, less than 90° ° structure.
  • various gate structures 250 as shown in FIGS.
  • the sidewalls of the doped layer 250 and the sidewalls of the doped layer 250 are not in the same plane, so that the sidewalls of the dielectric structure 260 are flush with at least part of the sidewalls of the doped layer 240; and/or, the doped layer 240 A structure in which at least part of the sidewalls of the dielectric structure 260 are not parallel to the sidewalls of the dielectric structure 260 .
  • the exposed gate material 204, dielectric material layer 202, and doped material layer 201 located outside the gate region 1001 may be dry-etched sequentially by using the photoresist, and then the photoresist may be trimmed. Then use the trimmed photoresist to continue dry etching the exposed gate material 204 outside the gate region 1001, the dielectric material layer 202, and part of the doped material layer 201 in order to finally obtain Figure 5 or Figure 7 A structure in which at least part of the sidewalls of the doped layer 240 are parallel to the sidewalls of the dielectric structure 260 is shown.
  • the dielectric material layer 202 on the left side of the gate trench 203 covered by the photoresist can be set The width is greater than the width of the dielectric material layer 202 on the right side of the gate trench 203, and the width of the first part 261 of the dielectric structure 260 on the left side of the gate structure 250 shown in FIG. 8 is greater than that on the right side of the gate structure 250.
  • the sidewall 251 of the gate structure 250 facing the doped layer 240 can also be further processed. Lateral etching, so that the sidewalls of the gate structure 250 are flush, that is, the sidewall 251 of the gate structure 250 facing the doped layer 240 is aligned with the sidewall 252 of the gate structure 250 facing away from the doped layer 240 At this time, a ladder structure is formed between the gate structure 250 and the doped layer 240 .
  • a hard mask layer 270 can be formed on the gate material 204.
  • the layer 270 can be formed by physical vapor deposition (Physical Vapor Deposition, PVD), as shown in FIG. 15 .
  • PVD Physical Vapor Deposition
  • the gate structure 250 can be etched laterally by using the hard mask layer 270 as a mask. , so that at least one sidewall of the gate structure 250 is flush, as shown in FIG. 17 . Since there is a dielectric structure 260 around the side wall 251 of the gate structure 250 facing the doped layer 240 when the gate structure 250 is etched laterally by wet etching, the distance of wet etching can be better controlled.
  • the wet etching is only for the part of the sidewall not covered by the dielectric structure 260, compared with the wet etching of the entire sidewall of the gate structure, it can improve the stability of the process and improve the sidewall of the gate structure 250. shape of the wall.
  • the hard mask layer 270 is removed.
  • the hard mask 270 may also be used as a protection layer for the gate structure 250 without being removed.
  • the dielectric structure 260 may or may not be removed.
  • the dielectric structure 260 can be removed while the hard mask layer 270 is removed by wet etching, or it can be divided into two steps to remove the hard mask layer 270 and the dielectric structure 260 respectively.
  • the process sequence of 260 is not specifically limited, as long as the ladder structure between the gate structure 250 and the doped layer 240 is finally formed, as shown in FIG. 18 .
  • the stepped structure between the structure 250 and the doped layer 240 is shown in FIGS. 19-22 .
  • the sidewall removal thicknesses of the gate structures 250 located in different directions are the same. In other words, after the lateral etching is completed, at least one sidewall of the gate structure 250 may not be flush, as shown in FIG. 22 .
  • the stepped structure between the gate structure 250 and the doped layer 240 prepared after the above-mentioned process has a better appearance, and the side walls of the gate structure 250 and the doped areas not covered by the gate structure 250
  • the etching damage on the surface of the layer 240 is less, which reduces the leakage current of the device and improves the performance of the device.
  • the source 253 and the drain 254 can also be formed in the non-gate region 1002 on the barrier layer 230, and the source 253 and the drain 254 are respectively located on both sides of the gate region 1001. .
  • Both the source electrode 253 and the drain electrode 254 are made of materials with better conductivity, and the materials of the source electrode 253 and the drain electrode 254 are: Ti, TiN, W, Ni, NiV, Ta, TaN, Pd, Pt, WSi 2 , Au at least one of .
  • the embodiment of the present application provides a method for manufacturing a semiconductor device.
  • a barrier layer, a dopant material layer, and a dielectric material layer are sequentially formed on the channel layer.
  • the channel layer and the barrier layer are composed of group III nitride materials.
  • the barrier layer has a gate region, and the material of the doping material layer is a group III-V compound containing acceptor-type doping elements, and the dielectric material layer on the doping material layer in the gate region is etched to form a through Gate trenches in the dielectric material layer, deposit gate material so that the gate material fills the gate trenches and cover the dielectric material layer, etch the gate material, dielectric material layer, and dopant material layer to form
  • the doped layer located in the gate region, and the gate structure on the doped layer a dielectric structure is arranged on the periphery of the side wall of the gate structure facing the doped layer, so that the side of the gate structure facing away from the doped layer
  • the sidewall of the gate structure is flush with the sidewall of the dielectric structure, so that the gate structure and the sidewall of the doped layer are not in the same plane, and the dielectric structure of the sidewall of the gate structure facing the doped layer isolates the gate structure from The contact between one side wall of the impurity

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Abstract

本申请公开了一种半导体器件及其制造方法，半导体器件可以包括依次层叠的沟道层和势垒层，以及掺杂层和栅极结构，沟道层和势垒层由Ⅲ族氮化物材料构成，势垒层具有栅极区域，掺杂层位于势垒层的背离沟道层的一侧，且掺杂层位于栅极区域，掺杂层的材料为包含受体型掺杂元素的Ⅲ-Ⅴ族化合物，栅极结构位于掺杂层的背离沟道层的一侧，栅极结构的朝向掺杂层的一侧侧壁相对于掺杂层的侧壁有回缩，且栅极结构的朝向掺杂层的一侧侧壁相对于栅极结构的背离掺杂层的一侧侧壁有回缩，使栅极结构和掺杂层的侧壁不在同一平面内，相当于隔断了栅极结构和掺杂层之间的漏电通道，因此减少了器件的漏电流，提高器件性能。

Description

一种半导体器件及其制造方法
本申请要求于2021年9月30日提交中国专利局、申请号为202111163668.4、发明名称为“一种半导体器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体器件及其制造方法。
背景技术
宽禁带半导体氮化镓(gallium nitride，GaN)具有高击穿电场、高电子迁移率及高电子饱和漂移速度，在电力电子和射频微波领域的应用前景十分广阔。
目前，氮化镓器件主要包含基于氮化铝镓(AlGaN)/GaN的异质结构的器件，例如以AlGaN/GaN异质结为核心制作的高电子迁移率晶体管(high electron mobility transistor，HEMT)有着优良的性能，非常适合制作功率半导体器件，目前被业界广泛关注。其中，AlGaN/GaN产生的压电极化及自发极化会使异质结界面处形成高浓度的二维电子气(two-dimensional electron gas，2-DEG)，其迁移率及饱和速度都远高于硅。
氮化镓器件中，在栅极区域的AlGaN/GaN异质结表面可以形成有一层掺杂层，掺杂层上形成有栅极结构，构成掺杂层和栅极结构的叠层，该掺杂层可以为p型GaN(p-GaN)层或p型AlGaN(p-AlGaN)，这种结构的氮化镓器件在工作时，栅极结构和掺杂层的侧壁会形成漏电通道，使得栅极漏电(gate leakage，Igleak)等电性参数受到影响。
发明内容
有鉴于此，本申请实施例提供了一种半导体器件及其制造方法，以提高器件的性能。
本申请实施例的第一方面，提供了一种半导体器件及其制造方法，半导体器件可以包括依次层叠的沟道层和势垒层，以及掺杂层和栅极结构，沟道层和势垒层由Ⅲ族氮化物材料构成，势垒层具有栅极区域，掺杂层位于势垒层的背离沟道层的一侧，且掺杂层位于栅极区域，掺杂层的材料为包含受体型掺杂元素的Ⅲ-Ⅴ族化合物，栅极结构位于掺杂层的背离沟道层的一侧，栅极结构的朝向掺杂层的一侧侧壁相对于掺杂层的侧壁有回缩，且栅极结构的朝向掺杂层的一侧侧壁相对于栅极结构的背离掺杂层的一侧侧壁有回缩，使栅极结构和掺杂层的侧壁不在同一平面内，栅极结构的朝向掺杂层的一侧侧壁的回缩结构隔断了栅极结构背离掺杂层的一侧侧壁和掺杂层侧壁的接触，相当于隔断了栅极结构和掺杂层之间的漏电通道，因此减少了器件的漏电流，提高器件性能。
在一些可能的实施方式中，所述沟道层的材料为氮化镓，所述势垒层的材料为氮化铝镓，所述掺杂层的材料为包含受体型掺杂元素的氮化镓或氮化铝镓。
本申请实施例中，沟道层的材料可以为氮化镓，势垒层的材料为氮化铝镓，可以在二者的界面处形成二维电子气，掺杂层的材料为包含受体型掺杂元素的氮化镓或氮化铝镓， 可以耗尽更好的耗尽栅极区域的二维电子气，同时掺杂层与势垒层有较好的接触，利于提高器件性能。
在一些可能的实施方式中，所述栅极结构的朝向所述掺杂层的一侧侧壁外围设置有介质结构，使所述栅极结构的背离所述掺杂层的一侧侧壁、所述介质结构的侧壁和所述掺杂层的至少部分侧壁齐平。
本申请实施例中，栅极结构的朝向掺杂层的一侧侧壁构成凹陷结构，其外围可以设置介质结构，使栅极结构的背离掺杂层的一侧侧壁和介质结构的侧壁以及掺杂层的至少部分侧壁齐平，即利用介质结构填充该凹陷结构，使整体结构稳定的同时，介质结构能够更好的阻断栅极结构的侧壁和掺杂层的侧壁之间的漏电通道，利于提高器件性能。
在一些可能的实施方式中，所述栅极结构的朝向所述掺杂层的一侧侧壁外围设置有介质结构，使所述栅极结构的背离所述掺杂层的一侧侧壁和所述介质结构的侧壁齐平；所述掺杂层的至少部分侧壁与所述介质结构的侧壁不平行。
本申请实施例中，栅极结构的朝向掺杂层的一侧侧壁形成凹陷结构，其外围可以设置介质结构，使栅极结构的背离掺杂层的一侧侧壁和介质结构的侧壁齐平，且掺杂层的至少部分侧壁与介质结构的侧壁不平行，即利用介质结构填充该凹陷结构，当然介质结构可以填满该凹陷结构，也可以未填满该凹陷结构，对凹陷结构的填充使整体结构稳定的同时，介质结构能够更好的阻断栅极结构的侧壁和掺杂层的侧壁之间的漏电通道，利于提高器件性能。
在一些可能的实施方式中，所述介质结构的材料包括以下材料的至少一种：SiO 2、SiON、SiNx、AlOx、AlNx、GaOx、TiOx。
本申请实施例中，介质结构的材料可以为绝缘性好的材料，以更好的阻断栅极结构和侧壁和掺杂层的侧壁之间的漏电通道，利于提高器件性能。
在一些可能的实施方式中，在平行所述沟道层的表面的平面内，所述介质结构包围所述栅极结构，且位于所述栅极结构不同侧的介质结构的多个部分的宽度不完全相同。
本申请实施例中，介质结构可以从各个侧面包围栅极结构，以从各个侧壁填充栅极结构朝向掺杂层的一侧侧壁的凹陷，位于不同侧的介质结构的多个部分的宽度不完全相同，使器件能够适应更多的应用场景。
在一些可能的实施方式中，所述介质结构在垂直所述沟道层的表面的方向上的尺寸小于5微米。
本申请实施例中，介质结构的厚度小于5微米，使介质结构的厚度较小，这样对介质结构进行刻蚀时，无论时干法刻蚀还是湿法刻蚀，均对势垒层的损伤较小，利于提高器件性能。
在一些可能的实施方式中，所述栅极结构的材料包含以下材料的至少一种：Ti、TiN、W、Ni、NiV、Ta、TaN、Pd、Pt、WSi 2、Au。
本申请实施例中，栅极结构的材料可以是导电性较好的材料，以提高器件性能。
在一些可能的实施方式中，所述半导体器件还包括：
源极和漏极；所述源极和所述漏极位于所述势垒层的背离所述沟道层的一侧，且所述 源极和所述漏极分别位于所述栅极区域的两侧。
本申请实施例中，还可以包括栅极区域两侧的源极和漏极，以构成完整的器件，实现较高的器件性能。
在一些可能的实施方式中，所述半导体器件还包括：
基底，所述基底位于所述沟道层背离所述势垒层的一侧。
本申请实施例中，可以在沟道层背离势垒层的一侧设置基底，用于支撑设置在基底其上的膜层，提高器件的可靠性。
在一些可能的实施方式中，所述半导体器件还包括：
位于所述基底和所述沟道层之间的缓冲层。
本申请实施例中，基底和沟道层之间还可以设置有缓冲层，从而提高沟道层的质量，利于提高器件性能。
本申请实施例第二方面，提供了一种半导体器件的制造方法，包括：
在沟道层上依次形成势垒层、掺杂材料层和介质材料层；所述沟道层由Ⅲ族氮化物材料构成，所述势垒层由Ⅲ族氮化物材料构成，所述势垒层具有栅极区域；所述掺杂材料层的材料为包含受体型掺杂元素的Ⅲ-Ⅴ族化合物；
对位于所述栅极区域的掺杂材料层上的介质材料层进行刻蚀，以形成贯穿所述介质材料层的栅区沟槽；
沉积栅极材料，以使所述栅极材料填充所述栅区沟槽，且覆盖所述介质材料层；
对所述栅极材料、介质材料层、掺杂材料层进行刻蚀，以形成位于所述栅极区域的掺杂层，以及所述掺杂层上的栅极结构；其中，所述栅极结构的朝向所述掺杂层的一侧侧壁外围设置有介质结构，使所述栅极结构的背离所述掺杂层的一侧侧壁和所述介质结构的侧壁齐平。
在一些可能的实施方式中，所述沟道层的材料为氮化镓，所述势垒层的材料为氮化铝镓，所述掺杂层的材料为包含受体型掺杂元素的氮化镓或氮化铝镓。。
在一些可能的实施方式中，所述介质结构的侧壁与所述掺杂层的至少部分侧壁齐平；和/或，所述掺杂层的至少部分侧壁与所述介质结构的侧壁不平行。
在一些可能的实施方式中，对所述栅极材料、介质材料层、掺杂材料层进行刻蚀之前，所述方法还包括：
在所述栅极材料上形成硬掩模层；则对所述栅极材料、介质材料层、掺杂材料层进行刻蚀的同时，还对所述硬掩模层进行刻蚀；
在对所述栅极材料、介质材料层、掺杂材料层进行刻蚀之后，还包括：
以所述硬掩模层为掩蔽，通过湿法腐蚀对所述栅极结构进行刻蚀，以使所述栅极结构的至少一侧侧壁齐平。
在一些可能的实施方式中，在通过湿法腐蚀对所述栅极结构进行刻蚀后，还包括：
去除所述硬掩模层，和/或，去除所述介质结构。
在一些可能的实施方式中，所述介质结构的材料包括以下材料的至少一种：SiO 2、SiON、SiNx、AlOx、AlNx、GaOx、TiOx。
在一些可能的实施方式中，在平行所述沟道层的表面的平面内，所述介质结构包围所述栅极结构，且位于所述栅极结构不同侧的介质结构的多个部分的宽度不完全相同。
在一些可能的实施方式中，所述介质结构在垂直所述沟道层的表面的方向上的尺寸小于5um。
在一些可能的实施方式中，对位于所述栅极区域的掺杂材料层上的介质材料层进行刻蚀，通过干法刻蚀或湿法腐蚀的方式实现。
在一些可能的实施方式中，所述栅极结构的材料包含以下材料的至少一种：Ti、TiN、W、Ni、NiV、Ta、TaN、Pd、Pt、WSi 2、Au。
在一些可能的实施方式中，所述方法还包括：
在所述势垒层上形成源极和漏极；所述源极和漏极分别位于所述栅极区域的两侧。
在一些可能的实施方式中，所述沟道层背离所述势垒层的一侧设置有基底。
在一些可能的实施方式中，所述沟道层和所述基底之间设置有缓冲层。
本申请实施例第三方面，提供了一种电子设备，包括电路板，以及与电路板连接的、如本申请第一方面提供的半导体器件。
从以上技术方案可以看出，本申请实施例具有以下优点：
本申请实施例提供一种半导体器件及其制造方法，半导体器件可以包括依次层叠的沟道层和势垒层，以及掺杂层和栅极结构，沟道层和势垒层由Ⅲ族氮化物材料构成，势垒层具有栅极区域，掺杂层位于势垒层的背离沟道层的一侧，且掺杂层位于栅极区域，掺杂层的材料为包含受体型掺杂元素的Ⅲ-Ⅴ族化合物，栅极结构位于掺杂层的背离沟道层的一侧，栅极结构的朝向掺杂层的一侧侧壁相对于掺杂层的侧壁有回缩，且栅极结构的朝向掺杂层的一侧侧壁相对于栅极结构的背离掺杂层的一侧侧壁有回缩，使栅极结构和掺杂层的侧壁不在同一平面内，栅极结构的朝向掺杂层的一侧侧壁的回缩结构隔断了栅极结构背离掺杂层的一侧侧壁和掺杂层侧壁的接触，相当于隔断了栅极结构和掺杂层之间的漏电通道，因此减少了器件的漏电流，提高器件性能。
附图说明
为了清楚地理解本申请的具体实施方式，下面将描述本申请具体实施方式时用到的附图做一简要说明。显而易见地，这些附图仅是本申请的部分实施例。
图1为一种氮化镓器件的结构示意图；
图2-图9为本申请实施例提供的半导体器件的结构示意图；
图10为本申请实施例提供的一种半导体器件的制造方法的流程图；
图11-22为本申请实施例提供的半导体器件的制造过程中的器件结构示意图。
具体实施方式
本申请实施例提供了一种半导体器件及其制造方法，以提高器件的光电转换效率。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理 解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
在氮化镓器件中，在栅极区域的AlGaN/GaN异质结表面可以形成有一层掺杂层，掺杂层上形成有栅极结构，构成掺杂层和栅极结构的叠层，该掺杂层可以为p型GaN(p-GaN)层或p型AlGaN(p-AlGaN)，具体来说，该掺杂层可以耗尽栅极区域的二维电子气沟道，栅极区域之外的非栅区域不形成掺杂层，从而使栅极区域无沟道，非栅区域有沟道，从而利用栅极对沟道进行控制。
然而，这种结构的氮化镓器件在工作时，栅极和掺杂层的侧壁会形成漏电通道，使得栅极漏电(gate leakage，Igleak)等电性参数收到影响。这是因为在对栅极结构和掺杂层的刻蚀过程中，不可避免的会在栅极结构和掺杂层的侧壁形成刻蚀损伤，损伤位置俘获电荷形成漏电流。
参考图1所示，为一种氮化镓器件的结构示意图，氮化镓器件可以包括层叠设置的GaN层100和AlGaN层110，在AlGaN层110上可以包括位于AlGaN/GaN异质结表面栅极区域的掺杂层120，以及位于掺杂层120上的栅极结构130，栅极结构130的横向尺寸小于掺杂层120的横向尺寸，使栅极结构130和掺杂层120之间形成阶梯形结构，这样可以使栅极结构的侧壁与掺杂层的侧壁不在同一平面内，二者不连续，避免栅极结构和掺杂层的侧壁形成漏电通道，提高基于AlGaN/GaN异质结构形成的HEMT器件的性能。
目前，可以通过一硬掩模刻蚀得到栅极结构和掺杂层，使栅极结构和掺杂层的侧壁齐平，而后利用湿法横向腐蚀栅极结构使栅极结构的侧壁相对于掺杂层的侧壁有回缩，隔断栅极结构侧壁和掺杂层侧壁的连接，避免栅极结构的侧壁和掺杂层的侧壁形成漏电通道。然而湿法横向腐蚀栅极结构以得到栅极结构和掺杂层之间的阶梯形结构时，栅极结构侧壁在进行刻蚀的过程中容易形成薄层变质层，会影响对栅极结构侧壁的刻蚀，最终使得栅极结构在形成阶梯形结构时侧壁不平整，形成锯齿状，影响后续工艺制程，得到的阶梯形结构形貌较差。
基于以上技术问题，本申请实施例提供了一种半导体器件及其制造方法，半导体器件可以包括依次层叠的沟道层和势垒层，以及掺杂层和栅极结构，势垒层具有栅极区域，沟道层和势垒层由Ⅲ族氮化物材料构成，掺杂层位于势垒层的背离沟道层的一侧，且掺杂层位于栅极区域，掺杂层的材料为包含受体型掺杂元素的Ⅲ-Ⅴ族化合物，栅极结构位于掺杂层的背离沟道层的一侧，栅极结构的朝向掺杂层的一侧侧壁相对于掺杂层的侧壁有回缩，且栅极结构的朝向掺杂层的一侧侧壁相对于栅极结构的背离掺杂层的一侧侧壁有回缩，使栅极结构和掺杂层的侧壁不在同一平面内，栅极结构的朝向掺杂层的一侧侧壁的回缩结构 隔断了栅极结构背离掺杂层的一侧侧壁和掺杂层侧壁的接触，相当于隔断了栅极结构和掺杂层之间的漏电通道，因此减少了器件的漏电流，提高器件性能。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。
参考图2所示，为本申请实施例提供的一种半导体器件的结构示意图，半导体器件可以包括依次层叠设置的沟道层220、势垒层230、掺杂层240和栅极结构250。其中，沟道层220由Ⅲ族氮化物材料构成，势垒层230由Ⅲ族氮化物材料构成，例如，沟道层220的材料可以为氮化镓，势垒层230的材料可以为氮化铝镓、氮化铝等中的一种，此时沟道层220和势垒层230形成异质结构，例如AlGaN/GaN的异质结构，从而产生二维电子气，基于此形成的半导体器件可以利用该异质结构产生的二维电子气工作。半导体器件例如可以为基于异质结构的高电子迁移率晶体管(high-electron-mobility transistor，HEMT)器件。
作为一种可能的实现方式，沟道层220的厚度可以较大，则沟道层220可以作为基底，该基底为其上的膜层提供支撑作用，例如材料为氮化镓的沟道层220可以作为基底，同时作为AlGaN/GaN的异质结构的组成部分。
作为另一种可能的实现方式，沟道层220的厚度可以较薄，则沟道层220可以形成于基底200上，基底200设置于沟道层220背离势垒层230的一侧，基底200为其上的膜层提供支撑作用，沟道层220作为异质结构的组成部分，其中基底200的材料可以为Ⅲ-Ⅴ族化合物半导体材料，可以为氮化铝(AlN)、硅(Si)、碳化硅(SiC)、蓝宝石中的一种或多种。可选的，在基底200和沟道层220之间，还可以设置有缓冲层210，缓冲层210的材料可以为氮化铝，也可以为低温生长的氮化镓，在缓冲层210为低温生长的氮化镓时，沟道层220可以为高温生长的氮化镓层，这样低温氮化镓层作为高温氮化镓层和基底200之间的缓冲层210，提高高温氮化镓层的外延质量。
势垒层230可以具有栅极区域1001和栅极区域1001外围的非栅区域1002，栅极区域1001为势垒层230表面上的区域，包括势垒层230表面以及垂直势垒层230表面的无数条直线界定出的空间。栅极区域1001用于形成栅极结构250，栅极区域1001可以大于栅极结构250所在区域，也可以等于栅极结构250所在区域，在图2中，中间的虚线框表示栅极区域1001，栅极区域1001两侧表示非栅区域1002，后续结构示意图采用相同的表示方式，由于图2为剖视图，因此实际上非栅区域1002可以位于栅极区域1001的两侧，可以形成包围栅极区域1001的环状区域，例如圆环区域或多边形区域。
在本申请的实施例中，在栅极区域1001的势垒层230表面可以形成有一层掺杂层240，即掺杂层240设置于势垒层230背离沟道层220的一侧，且掺杂层240位于栅极区域1001。掺杂层240的材料可以是包含受体型掺杂元素的Ⅲ-Ⅴ族化合物，例如掺杂层240的材料可以是包含受体型(P型)掺杂元素的氮化镓或氮化铝镓，对应的，该掺杂层可以表示为p型GaN(p-GaN)或p型AlGaN(p-AlGaN)。掺杂层240可以用于耗尽栅极区域1001的二维电子气沟道，栅极区域1001之外的非栅区域1002不形成掺杂层，从而使栅极区域1001无沟道，非栅区域1002有沟道，从而利用栅极结构250对沟道进行控制。
在本申请的实施例中，在掺杂层240上形成有栅极结构250，栅极结构250设置于掺杂层240背离沟道层220的一侧。栅极结构250的材料可以具有良好的导电性，其材料可以为Ti、TiN、W、Ni、NiV、Ta、TaN、Pd、Pt、WSi 2、Au中的至少一种。
本申请实施例中，栅极结构250朝向掺杂层240的一侧侧壁相对于掺杂层240的侧壁有回缩，并且栅极结构250朝向掺杂层240的一侧侧壁相对于栅极结构250背离掺杂层240的一侧侧壁有回缩，使在沿势垒层230表面的方向上，栅极结构250朝向掺杂层240的部分的尺寸，小于栅极结构250背离掺杂层240的部分的尺寸，以及小于掺杂层240的尺寸，栅极结构250朝向掺杂层240的部分在整体上构成凹陷结构，最终使得栅极结构250的侧壁与掺杂层240的侧壁不在同一平面内，从而阻断栅极结构250的侧壁和掺杂层240的侧壁的连续性，避免栅极结构250和掺杂层240的侧壁形成漏电通道。
参考图2所示，栅极结构250具有朝向掺杂层240的一侧侧壁251作为栅极结构250的部分侧壁，背离掺杂层240的一侧侧壁252作为栅极结构250的另一部分侧壁，两部分侧壁共同构成栅极结构250的侧壁。朝向掺杂层240的一侧侧壁251不仅相对于掺杂层240的侧壁有回缩，还相较于背离掺杂层240的一侧侧壁有回缩，形成回缩结构，使得栅极结构250的侧壁与掺杂层250的侧壁不在同一平面内。正是由于栅极结构250的朝向掺杂层240的一侧侧壁251的回缩结构隔断了栅极结构250的侧壁和掺杂层240侧壁的连续性，相当于隔断了栅极结构250和掺杂层240之间的漏电通道，因此减少了器件的漏电流，提高器件性能。
参考图2所示为剖视示意图，实际上的栅极结构250在平行势垒层230的平面内构成多边形结构，则回缩结构形成于栅极结构250的至少一侧侧壁，例如可以形成于栅极结构250的所有侧壁，回缩结构构成闭合环状。
在一些可能的实施方式中，栅极结构250的朝向掺杂层240的一侧侧壁251与掺杂层240朝向栅极结构250的表面垂直，即该侧壁与掺杂层240朝向栅极结构250并且未被栅极结构250覆盖的部分表面之间的夹角等于90°，参考图2所示。也就是说，栅极结构250的朝向掺杂层240的一侧侧壁251和掺杂层240的侧壁不连续，和栅极结构250的背离掺杂层240的一侧侧壁252也不连续。因此，能够阻隔栅极结构250背离掺杂层240的一侧侧壁252和掺杂层240侧壁进行接触，就能够隔断栅极结构250和掺杂层240之间的漏电通道，因此减少器件的漏电流，提高器件性能。
在另一些可能的实施方式中，栅极结构250的朝向掺杂层240的一侧侧壁251可以不垂直于掺杂层240朝向掺杂结构250的表面，即该侧壁与掺杂层240朝向栅极结构250并且未被栅极结构250覆盖的部分表面之间的夹角不等于90°，例如小于90°，参考图3所示，为本申请实施例提供的另一种半导体器件的结构示意图。也就是说，栅极结构250的朝向掺杂层240的一侧侧壁251与掺杂层240的侧壁不连续，栅极结构250的朝向掺杂层240的一侧侧壁251与掺杂层240朝向栅极结构250并且未被栅极结构250覆盖的部分表面之间相交，并且相交的夹角不等于90°，例如小于90°，同时栅极结构250的朝向掺杂层240的一侧侧壁251与栅极结构250的背离掺杂层240的一侧侧壁252相交，相交的夹角不等于90°，例如大于90°。因此，栅极结构250的朝向掺杂层240的一侧侧壁251不垂直于掺 杂层240朝向掺杂结构250的表面时，依旧能够阻隔栅极结构250背离掺杂层240的一侧侧壁252和掺杂层240侧壁进行接触，就能够隔断栅极结构250和掺杂层240之间的漏电通道，因此减少器件的漏电流，提高器件性能。
在本申请的实施例中，在栅极结构250的朝向掺杂层240的一侧侧壁251外围可以设置介质结构260，参考图4所示，为本申请实施例提供的又一种半导体器件的结构示意图，即在栅极结构250的朝向掺杂层240的一侧侧壁251的回缩结构中具有介质材料，形成介质结构260，介质材料填充回缩结构，使形成的介质结构260的侧壁和栅极结构250背离掺杂层240的一侧侧壁252齐平，这样介质结构260的侧壁位于栅极结构250背离掺杂层240的一侧侧壁252和掺杂层240侧壁之间，从而利用介质材料隔断栅极结构250和掺杂层240之间的漏电通道。介质结构260的材料可以选用绝缘性较好的材料，其材料可以为SiO 2、SiON、SiNx、AlOx、AlNx、GaOx、TiOx中的至少一种。
在本申请的实施例中，介质结构260的侧壁和栅极结构250背离掺杂层240的一侧侧壁252齐平，介质结构260的侧壁可以和掺杂层240的至少部分侧壁齐平，具体的，介质结构260可以和掺杂层240的全部侧壁齐平，也可以和掺杂层240的部分侧壁齐平。
在一些可能的实施方式中，栅极结构250的背离掺杂层240的一侧侧壁252、介质结构260的侧壁和掺杂层240的侧壁齐平，参考图4所示。此时栅极结构250的朝向掺杂层240的一侧侧壁251与掺杂层240的侧壁不在同一平面内，且介质结构260的侧壁位于栅极结构250背离掺杂层240的一侧侧壁252和掺杂层240侧壁之间，从而利用介质材料隔断栅极结构250和掺杂层240之间的漏电通道。
在另一些可能的实施方式中，栅极结构250的背离掺杂层240的一侧侧壁252、介质结构260的侧壁和掺杂层240的部分侧壁齐平。参考图5所示，为本申请实施例提供的再一种半导体器件的结构示意图，掺杂层240的侧壁包括朝向栅极结构250的一侧侧壁241和背离栅极结构250的一侧侧壁242，掺杂层240朝向栅极结构250的一侧侧壁241、栅极结构250的背离掺杂层240的一侧侧壁252和介质结构260的侧壁齐平，掺杂层240的背离栅极结构250的一侧侧壁242和介质结构260的侧壁不齐平，具体的，掺杂层240的背离栅极结构250的一侧侧壁242可以与介质结构260的侧壁平行，也可以与介质结构260的侧壁不平行。
在本申请的实施例中，介质结构260的侧壁和栅极结构250背离掺杂层240的一侧侧壁252齐平，介质结构260的侧壁可以和掺杂层240的至少部分侧壁不平行，具体的，介质结构260可以和掺杂层240的全部侧壁不平行，也可以和掺杂层240的部分侧壁不平行。
在一些可能的实施方式中，栅极结构250的背离掺杂层240的一侧侧壁252和介质结构260的侧壁齐平，掺杂层240的侧壁与介质结构260的侧壁不平行。参考图6所示，为本申请实施例提供的还一种半导体器件的结构示意图，掺杂层240的侧壁和介质结构260侧壁之间的夹角不等于90°，例如大于90°，最终形成栅极结构250的侧壁与掺杂层250的侧壁不在同一平面内的结构。
在另一些可能的实施方式中，栅极结构250的背离掺杂层240的一侧侧壁252和介质结构260的侧壁齐平，掺杂层240的部分侧壁与介质结构260的侧壁不平行，掺杂层240 的另一部分侧壁可以和介质结构260的侧壁齐平，也可以不和介质结构260的侧壁齐平。参考图7所示，为本申请实施例提供的还又一种半导体器件的结构示意图，掺杂层240的侧壁包括朝向栅极结构250的一侧侧壁241和背离栅极结构250的一侧侧壁242，掺杂层240朝向栅极结构250的一侧侧壁241、栅极结构250的背离掺杂层240的一侧侧壁252和介质结构260的侧壁齐平，掺杂层240的背离栅极结构250的一侧侧壁242和介质结构260的侧壁不平行，二者之间的夹角不等于90°，例如大于90°。
由此可见，对于栅极结构250的侧壁与掺杂层240的侧壁不在同一平面内的需求，本申请实施例提供了多种栅极结构250的侧壁与掺杂层240的侧壁的设计，满足实际应用中的多种需求，拥有较大的应用前景。
在本申请的实施例中，由于图4-图7为剖视图，因此实际上在平行于沟道层220的表面的平面内，回缩结构可以位于栅极结构250的各个侧壁，介质结构260可以包围栅极结构250。
在实际应用中，在介质结构260包围栅极结构250时，在平行于沟道层220的表面的平面内，位于栅极结构250不同侧的介质结构260的多个部分的宽度不完全相同，这里的宽度指介质结构260的侧壁与栅极结构250靠近掺杂层240的一侧侧壁251之间的距离。参考图8所示，为本申请实施例提供的再又一种半导体器件的结构示意图，位于栅极结构250左侧的介质结构260的第一部分261的宽度大于位于栅极结构250右侧的介质结构260的第二部分262的宽度。这样非对称结构的栅极结构250的设计可以满足某些器件的个性化设计需求，拥有较大的应用前景。
在本申请的实施例中，介质结构在垂直沟道层220的表面的方向上的尺寸小于5微米(um)，例如小于500nm，即介质材料形成的膜层较薄，在刻蚀得到介质结构260时减少对掺杂层240的表面的损伤，避免由于刻蚀损伤形成的漏电流，提高器件性能。
在本申请的实施例中，参考图9所示，为本申请实施例提供的还再一种半导体器件的结构示意图，半导体器件还可以包括源极253和漏极254，源极253和漏极254位于非栅区域1002的势垒层230的背离沟道层220的一侧，源极253和漏极254分别位于栅极区域1001的两侧。源极253和漏极254均采用导电性较好的材料，源极253和漏极254的材料为：Ti、TiN、W、Ni、NiV、Ta、TaN、Pd、Pt、WSi 2、Au中的至少一种。
本申请实施例提供了一种半导体器件，半导体器件可以包括依次层叠的沟道层和势垒层，以及掺杂层和栅极结构，沟道层和势垒层由Ⅲ族氮化物材料构成，势垒层具有栅极区域，掺杂层位于势垒层的背离沟道层的一侧，且掺杂层位于栅极区域，掺杂层的材料为包括受体型掺杂元素的Ⅲ-Ⅴ族化合物，栅极结构位于掺杂层的背离沟道层的一侧，栅极结构的朝向掺杂层的一侧侧壁相对于掺杂层的侧壁有回缩，且栅极结构的朝向掺杂层的一侧侧壁相对于栅极结构的背离掺杂层的一侧侧壁有回缩，使栅极结构和掺杂层的侧壁不在同一平面内，栅极结构的朝向掺杂层的一侧侧壁的回缩结构隔断了栅极结构背离掺杂层的一侧侧壁和掺杂层侧壁的接触，相当于隔断了栅极结构和掺杂层之间的漏电通道，因此减少了器件的漏电流，提高器件性能。
基于本申请实施例提供的一种半导体器件，本申请实施例还提供了一种半导体器件的制造方法，参考图10所示，为本申请实施例提供的一种半导体器件的制造方法的流程图，图11-图22为半导体器件在制造过程中的结构示意图，该方法可以包括：
S101，在沟道层220上依次形成势垒层230、掺杂材料层201和介质材料层202，参考图11所示。
在本申请的实施例中，沟道层220由Ⅲ族氮化物材料构成，势垒层230由Ⅲ族氮化物材料构成，例如，沟道层220的材料可以为氮化镓，势垒层230的材料可以为氮化铝镓，此时层叠设置的沟道层220和势垒层230形成AlGaN/GaN的异质结构，从而产生二维电子气，基于此形成的半导体器件可以利用该异质结构产生的二维电子气工作。半导体器件例如可以为基于异质结构的高电子迁移率晶体管(high-electron-mobility transistor，HEMT)器件。
作为一种可能的实现方式，沟道层220的厚度可以较大，则沟道层220可以作为基底，该基底为其上的膜层提供支撑作用，例如材料为氮化镓的沟道层220可以作为基底，同时作为AlGaN/GaN的异质结构的组成部分。
作为另一种可能的实现方式，沟道层220的厚度可以较薄，参考图11所示，则沟道层220可以形成于基底200上，基底200为其上的膜层提供支撑作用，沟道层220作为异质结构的组成部分，其中基底200的材料可以为Ⅲ-Ⅴ族化合物半导体材料，可以为氮化铝(AlN)、硅(Si)、碳化硅(SiC)、蓝宝石中的一种或多种。可选的，在基底200和沟道层220之间，还可以设置有缓冲层210，缓冲层210的材料可以为氮化铝，也可以为低温生长的氮化镓。
具体实施时，可以先在基底200表面形成缓冲层210，而后在缓冲层210上形成沟道层220，之后在沟道层220上依次形成势垒层230、掺杂材料层201和介质材料层202。沟道层220、势垒层230、掺杂材料层201和介质材料层202的形成方式可以为有机金属化学气相沉积(Metal organic chemical vapor deposition，MOCVD)。
在本申请的实施例中，势垒层230可以具有栅极区域1001和栅极区域1001外围的非栅区域1002，栅极区域1001为势垒层230表面上的区域，包括势垒层230表面以及垂直势垒层230表面的无数条直线界定出的空间。栅极区域1001用于形成栅极结构250，栅极区域1001可以大于栅极结构250所在区域，也可以等于栅极结构250所在区域，在图11中，中间的虚线框表示栅极区域1001，栅极区域1001两侧表示非栅区域1002，后续结构示意图采用相同的表示方式，由于图11为剖视图，因此实际上非栅区域1002可以位于栅极区域1001的两侧，可以形成包围栅极区域1001的环状区域，例如圆环区域或多边形区域。
在本申请的实施例中，掺杂材料层201的材料可以是包含受体型掺杂元素的Ⅲ-Ⅴ族化合物，例如掺杂材料层201的材料可以是包含受体型掺杂元素的氮化镓或氮化铝镓，即该掺杂层可以为p型GaN(p-GaN)或p型AlGaN(p-AlGaN)。介质材料层202的材料可以选用绝缘材料，其材料可以为SiO 2、SiON、SiNx、AlOx、AlNx、GaOx、TiOx中的至少一种。
S102，对位于栅极区域1001的掺杂材料层201上的介质材料层202进行刻蚀，以形成贯穿介质材料层202的栅区沟槽203，参考图12所示。
在本申请的实施例中，在形成介质材料层202之后，可以对位于栅极区域1001的介质材料层202进行刻蚀，以形成贯穿介质材料层202至掺杂材料层201的栅区沟槽203。栅区沟槽203位于栅极区域1001，用于形成栅极结构250。
具体实施时，可以在介质材料层202上旋涂光刻胶，而后对光刻胶进行曝光以及显影等处理，以暴露位于栅极区域1001的介质材料层202，之后对暴露的位于栅极区域1001的介质材料层202进行刻蚀，得到贯穿介质材料层202的栅区沟槽203，最后去除光刻胶，光刻胶可以利用干法刻蚀和湿法刻蚀去除，也可以利用其他方式。
在实际应用中，在垂直沟道层220的表面的方向上，介质材料层202的尺寸小于5微米(um)，例如小于500nm，即介质材料形成的膜层较薄，对介质材料层202的刻蚀易于控制，在刻蚀介质材料层202时减少对掺杂材料层201的表面的损伤，避免由于刻蚀损伤形成的漏电流，提高器件性能。由于介质材料层202较薄，因此既可以采用干法刻蚀得到栅区沟槽203，也可以采用湿法腐蚀得到栅区沟槽203，采用湿法腐蚀介质材料层202时，介质材料层202和其下的掺杂材料层201可以具有较高的选择比，进一步减少对掺杂材料层201的刻蚀损伤。
S103，沉积栅极材料204，以使栅极材料204填充栅区沟槽203，且覆盖介质材料层202，参考图13所示。
在本申请的实施例中，在去除光刻胶之后，可以继续沉积栅极材料204，使得栅极材料填充栅区沟槽203并且覆盖介质材料层202。栅极材料可以具有良好的导电性，其材料可以为Ti、TiN、W、Ni、NiV、Ta、TaN、Pd、Pt、WSi 2、Au中的至少一种。栅极材料204的沉积方式可以为物理气相沉积(Physical Vapor Deposition，PVD)。
S104，对栅极材料204、介质材料层202、掺杂材料层201进行刻蚀，以形成位于栅极区域1001的掺杂层240，以及掺杂层240上的栅极结构250，参考图14-图22所示。
在本申请的实施例中，在沉积栅极材料204之后，对位于栅极区域1001以外的栅极材料204、介质材料层202、掺杂材料层201进行刻蚀，最终形成位于栅极区域1001的掺杂层240，以及掺杂层240上的栅极结构250。
其中，在平行于沟道层220的表面的平面内，掺杂层240的宽度大于栅区沟槽203的宽度，即最终形成的栅极结构250的朝向掺杂层240的一侧侧壁251外围设置有介质结构260，使栅极结构250的背离掺杂层240的一侧侧壁252和介质结构260的侧壁齐平。
具体实施时，可以在栅极材料204上旋涂光刻胶，在平行于沟道层220的表面的平面内，光刻胶的宽度大于栅区沟槽203的宽度，而后对光刻胶进行曝光以及显影等处理，以暴露位于栅极区域1001以外的栅极材料204、介质材料层202、掺杂材料层201，之后依次对暴露的位于栅极区域1001以外的栅极材料204、介质材料层202、掺杂材料层201进行干法刻蚀，保留位于栅极区域1001的栅极材料204、介质材料层202、掺杂材料层201，最后去除光刻胶，光刻胶可以利用干法刻蚀和湿法刻蚀去除，也可以利用其他方式。
在本申请的实施例中，通过控制在刻蚀介质材料层202时，栅区沟槽203的侧壁与栅 区沟槽203的底面的夹角等于90°，可以形成图2所示的栅极结构250的朝向掺杂层240的一侧侧壁251与掺杂层240朝向栅极结构250并且未被栅极结构250覆盖的部分表面241之间的夹角等于90°的结构。通过控制在刻蚀介质材料层202时，栅区沟槽203的侧壁与栅区沟槽203的底面的夹角不等于90°，例如大于90°，可以形成图3所示的栅极结构250的朝向掺杂层240的一侧侧壁251与掺杂层240朝向栅极结构250并且未被栅极结构250覆盖的部分表面241之间的夹角不等于90°的结构，例如小于90°的结构。
在本申请的实施例中，可以通过控制对栅极材料204、介质材料层202、掺杂材料层201进行刻蚀的工艺参数，以得到图4-图7所示的多种栅极结构250的侧壁与掺杂层250的侧壁不在同一平面内的叠层结构，以最终形成介质结构260的侧壁与掺杂层240的至少部分侧壁齐平；和/或，掺杂层240的至少部分侧壁与介质结构260的侧壁不平行的结构。
具体实施时，可以在利用光刻胶依次对暴露的位于栅极区域1001以外的栅极材料204、介质材料层202、掺杂材料层201进行干法刻蚀后，对光刻胶进行修剪，而后利用修剪后的光刻胶继续依次对暴露的位于栅极区域1001以外的栅极材料204、介质材料层202、部分掺杂材料层201进行干法刻蚀，以最终得到图5或图7所示的掺杂层240的至少部分侧壁与介质结构260的侧壁平行的结构。
在实际应用中，可以在利用光刻胶刻蚀栅极材料204、介质材料层202、掺杂材料层201时，设置光刻胶覆盖的位于栅区沟槽203左侧的介质材料层202的宽度大于位于栅区沟槽203右侧的介质材料层202的宽度，可以获得图8所示的位于栅极结构250左侧的介质结构260的第一部分261的宽度大于位于栅极结构250右侧的介质结构260的第二部分262的宽度的介质结构。
在实际应用中，在形成栅极结构250的朝向掺杂层240的一侧侧壁251的回缩结构之后，还可以继续对栅极结构250的朝向掺杂层240的一侧侧壁251进行横向刻蚀，使得栅极结构250的侧壁齐平，即栅极结构250的朝向掺杂层240的一侧侧壁251和栅极结构250的背离掺杂层240的一侧侧壁252齐平，此时栅极结构250和掺杂层240之间形成阶梯形结构。
具体实施时，可以在沉积栅极材料204之后，对栅极材料204、介质材料层202、掺杂材料层201进行刻蚀之前，在栅极材料204上形成硬掩模层270，硬掩模层270的形成方式可以为物理气相沉积(Physical Vapor Deposition，PVD)，参考图15所示。之后在对栅极材料204、介质材料层202、掺杂材料层201进行刻蚀时，同时也对硬掩模层270进行刻蚀，参考图16所示。在经过刻蚀得到栅极结构250的朝向掺杂层240的一侧侧壁251的回缩结构之后，可以以硬掩模层270为掩蔽，通过湿法腐蚀对栅极结构250进行横向刻蚀，使得栅极结构250的至少一侧侧壁齐平，参考图17所示。由于在利用湿法腐蚀对栅极结构250进行横向刻蚀时，栅极结构250的朝向掺杂层240的一侧侧壁251周围存在介质结构260，因此能够较好的控制湿法腐蚀的距离，且湿法腐蚀仅针对未被介质结构260覆盖的部分侧壁，相较于采用湿法横向腐蚀栅极结构的整个侧壁而言，能够提高工艺制程的稳定性和提高栅极结构250侧壁的形貌。
在本申请的实施例中，在对栅极结构250横向刻蚀完毕后，去除硬掩模层270，当然 硬掩模270也可以不去除而作为栅极结构250的保护层。介质结构260可以去除，也可以不去除。可以在利用湿法腐蚀去除硬掩模层270的同时去除介质结构260，也可以分为两步工艺分别去除硬掩模层270和介质结构260，本申请对去除硬掩模层270和介质结构260的工艺顺序不做具体限定，只要最终形成栅极结构250和掺杂层240之间的阶梯形结构即可，参考图18所示。
在本申请的实施例中，图4-图8所示的栅极结构250和掺杂层240形成的叠层结构，都可以执行对栅极结构250进行横向刻蚀的步骤，以获得栅极结构250和掺杂层240之间的阶梯形结构，如图19-图22所示。
具体实施时，在利用湿法腐蚀对栅极结构250进行横向刻蚀时，位于不同方向的栅极结构250的侧壁去除厚度相同，对于图8所示的非对称结构的栅极结构250而言，在横向刻蚀完毕后，可以存在栅极结构250的至少一侧侧壁不齐平的情况，如图22所示。
由此可见，经过上述工艺后制备得到的栅极结构250和掺杂层240之间的阶梯形结构，形貌较好，栅极结构250的侧壁和未被栅极结构250覆盖的掺杂层240表面刻蚀损伤较少，减少了器件的漏电流，提高器件性能。
本申请实施例中，参考图9所示，还可以在势垒层230上的非栅区域1002形成源极253和漏极254，源极253和漏极254分别位于栅极区域1001的两侧。源极253和漏极254均采用导电性较好的材料，源极253和漏极254的材料为：Ti、TiN、W、Ni、NiV、Ta、TaN、Pd、Pt、WSi 2、Au中的至少一种。
本申请实施例提供了一种半导体器件的制造方法，在沟道层上依次形成势垒层、掺杂材料层和介质材料层，沟道层和势垒层由Ⅲ族氮化物材料构成，势垒层具有栅极区域，掺杂材料层的材料为包含受体型掺杂元素的Ⅲ-Ⅴ族化合物，对位于栅极区域的掺杂材料层上的介质材料层进行刻蚀，以形成贯穿介质材料层的栅区沟槽，沉积栅极材料，以使栅极材料填充栅区沟槽，且覆盖介质材料层，对栅极材料、介质材料层、掺杂材料层进行刻蚀，以形成位于栅极区域的掺杂层，以及掺杂层上的栅极结构，栅极结构的朝向掺杂层的一侧侧壁外围设置有介质结构，使栅极结构的背离掺杂层的一侧侧壁和介质结构的侧壁齐平，使栅极结构和掺杂层的侧壁不在同一平面内，栅极结构的朝向掺杂层的一侧侧壁的介质结构隔断了栅极结构背离掺杂层的一侧侧壁和掺杂层侧壁的接触，相当于隔断了栅极结构和掺杂层之间的漏电通道，因此减少了器件的漏电流，提高器件性能。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。
以上为本申请的具体实现方式。应当理解，以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (25)

  1. 一种半导体器件，其特征在于，包括：
    依次层叠的沟道层和势垒层；所述沟道层由Ⅲ族氮化物材料构成，所述势垒层由Ⅲ族氮化物材料构成，所述势垒层具有栅极区域；
    掺杂层，所述掺杂层位于所述势垒层的背离所述沟道层的一侧，且所述掺杂层位于所述栅极区域；所述掺杂层的材料为包含受体型掺杂元素的Ⅲ-Ⅴ族化合物；
    栅极结构，所述栅极结构位于所述掺杂层的背离所述沟道层的一侧；所述栅极结构的朝向所述掺杂层的一侧侧壁相对于所述掺杂层的侧壁有回缩，且所述栅极结构的朝向所述掺杂层的一侧侧壁相对于所述栅极结构的背离所述掺杂层的一侧侧壁有回缩，使所述栅极结构和所述掺杂层的侧壁不在同一平面内。
  2. 根据权利要求1所述的器件，其特征在于，所述沟道层的材料为氮化镓，所述势垒层的材料为氮化铝镓，所述掺杂层的材料为包含受体型掺杂元素的氮化镓或氮化铝镓。
  3. 根据权利要求1或2所述的器件，其特征在于，所述栅极结构的朝向所述掺杂层的一侧侧壁外围设置有介质结构，使所述栅极结构的背离所述掺杂层的一侧侧壁、所述介质结构的侧壁和所述掺杂层的至少部分侧壁齐平。
  4. 根据权利要求1或2所述的器件，其特征在于，所述栅极结构的朝向所述掺杂层的一侧侧壁外围设置有介质结构，使所述栅极结构的背离所述掺杂层的一侧侧壁和所述介质结构的侧壁齐平；所述掺杂层的至少部分侧壁与所述介质结构的侧壁不平行。
  5. 根据权利要求3或4所述的器件，其特征在于，所述介质结构的材料包括以下材料的至少一种：SiO 2、SiON、SiNx、AlOx、AlNx、GaOx、TiOx。
  6. 根据权利要求3-5任一项所述的器件，其特征在于，在平行所述沟道层的表面的平面内，所述介质结构包围所述栅极结构，且位于所述栅极结构不同侧的介质结构的多个部分的宽度不完全相同。
  7. 根据权利要求3-6任一项所述的器件，其特征在于，所述介质结构在垂直所述沟道层的表面的方向上的尺寸小于5微米。
  8. 根据权利要求1-7任一项所述的器件，其特征在于，所述栅极结构的材料包含以下材料的至少一种：Ti、TiN、W、Ni、NiV、Ta、TaN、Pd、Pt、WSi 2、Au。
  9. 根据权利要求1-8任一项所述的器件，其特征在于，还包括：
    源极和漏极；所述源极和所述漏极位于所述势垒层的背离所述沟道层的一侧，且所述源极和所述漏极分别位于所述栅极区域的两侧。
  10. 根据权利要求1-9任一项所述的器件，其特征在于，还包括：
    基底，所述基底位于所述沟道层背离所述势垒层的一侧。
  11. 根据权利要求10所述的器件，其特征在于，还包括：
    位于所述基底和所述沟道层之间的缓冲层。
  12. 一种半导体器件的制造方法，其特征在于，包括：
    在沟道层上依次形成势垒层、掺杂材料层和介质材料层；所述沟道层由Ⅲ族氮化物材料构成，所述势垒层由Ⅲ族氮化物材料构成，所述势垒层具有栅极区域；所述掺杂材料层 的材料为包含受体型掺杂元素的Ⅲ-Ⅴ族化合物；
    对位于所述栅极区域的掺杂材料层上的介质材料层进行刻蚀，以形成贯穿所述介质材料层的栅区沟槽；
    沉积栅极材料，以使所述栅极材料填充所述栅区沟槽，且覆盖所述介质材料层；
    对所述栅极材料、介质材料层、掺杂材料层进行刻蚀，以形成位于所述栅极区域的掺杂层，以及所述掺杂层上的栅极结构；其中，所述栅极结构的朝向所述掺杂层的一侧侧壁外围设置有介质结构，使所述栅极结构的背离所述掺杂层的一侧侧壁和所述介质结构的侧壁齐平。
  13. 根据权利要求12所述的方法，其特征在于，所述沟道层的材料为氮化镓，所述势垒层的材料为氮化铝镓，所述掺杂层的材料为包含受体型掺杂元素的氮化镓或氮化铝镓。
  14. 根据权利要求12或13所述的方法，其特征在于，所述介质结构的侧壁与所述掺杂层的至少部分侧壁齐平；和/或，所述掺杂层的至少部分侧壁与所述介质结构的侧壁不平行。
  15. 根据权利要求12-14任一项所述的方法，其特征在于，对所述栅极材料、介质材料层、掺杂材料层进行刻蚀之前，所述方法还包括：
    在所述栅极材料上形成硬掩模层；则对所述栅极材料、介质材料层、掺杂材料层进行刻蚀的同时，还对所述硬掩模层进行刻蚀；
    在对所述栅极材料、介质材料层、掺杂材料层进行刻蚀之后，还包括：
    以所述硬掩模层为掩蔽，通过湿法腐蚀对所述栅极结构进行刻蚀，以使所述栅极结构的至少一侧侧壁齐平。
  16. 根据权利要求15所述的方法，其特征在于，在通过湿法腐蚀对所述栅极结构进行刻蚀后，还包括：
    去除所述硬掩模层，和/或，去除所述介质结构。
  17. 根据权利要求12-16任一项所述的方法，其特征在于，所述介质结构的材料包括以下材料的至少一种：SiO 2、SiON、SiNx、AlOx、AlNx、GaOx、TiOx。
  18. 根据权利要求12-17任一项所述的方法，其特征在于，在平行所述沟道层的表面的平面内，所述介质结构包围所述栅极结构，且位于所述栅极结构不同侧的介质结构的多个部分的宽度不完全相同。
  19. 根据权利要求12-18任一项所述的方法，其特征在于，所述介质结构在垂直所述沟道层的表面的方向上的尺寸小于5微米。
  20. 根据权利要求12-19任一项所述的方法，其特征在于，对位于所述栅极区域的掺杂材料层上的介质材料层进行刻蚀，通过干法刻蚀或湿法腐蚀的方式实现。
  21. 根据权利要求12-20任一项所述的方法，其特征在于，所述栅极结构的材料包含以下材料的至少一种：Ti、TiN、W、Ni、NiV、Ta、TaN、Pd、Pt、WSi 2、Au。
  22. 根据权利要求12-21任一项所述的方法，其特征在于，还包括：
    在所述势垒层上形成源极和漏极；所述源极和所述漏极分别位于所述栅极区域的两侧。
  23. 根据权利要求12-22任一项所述的方法，其特征在于，所述沟道层背离所述势垒层的一侧设置有基底。
  24. 根据权利要求23所述的方法，其特征在于，所述沟道层和所述基底之间设置有缓冲层。
  25. 一种电子设备，其特征在于，包括电路板，以及与所述电路板连接的、如权利要求1-11任意一项所述的半导体器件。
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