WO2023060834A1 - 单通道通信编码方法、解码方法、编码电路及解码电路 - Google Patents

单通道通信编码方法、解码方法、编码电路及解码电路 Download PDF

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Publication number
WO2023060834A1
WO2023060834A1 PCT/CN2022/080838 CN2022080838W WO2023060834A1 WO 2023060834 A1 WO2023060834 A1 WO 2023060834A1 CN 2022080838 W CN2022080838 W CN 2022080838W WO 2023060834 A1 WO2023060834 A1 WO 2023060834A1
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WIPO (PCT)
Prior art keywords
signal
long
short code
pulse
clock
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Ceased
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PCT/CN2022/080838
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English (en)
French (fr)
Inventor
黄家赓
盛云
林建烽
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Suzhou Novosense Microelectronics Co Ltd China
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Suzhou Novosense Microelectronics Co Ltd China
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Priority to EP22879785.8A priority Critical patent/EP4333336A4/en
Priority to JP2024517070A priority patent/JP7675301B2/ja
Priority to US18/700,519 priority patent/US20250016033A1/en
Priority to KR1020247009352A priority patent/KR20240052784A/ko
Publication of WO2023060834A1 publication Critical patent/WO2023060834A1/zh
Anticipated expiration legal-status Critical
Priority to JP2025034119A priority patent/JP7819380B2/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0091—Transmitter details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4902—Pulse width modulation; Pulse position modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/06—Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell
    • H03M5/08—Code representation by pulse width
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • the invention belongs to the field of analog-digital hybrid circuits, and in particular relates to a single-channel communication encoding method, a decoding method, an encoding circuit and a decoding circuit.
  • the digital isolator is used for communication, which includes a source side and a secondary side, and the secondary side receives the signal sent by the source side.
  • Figure 1 is a common method of isolated data and clock transmission.
  • the data and clock on the source side use an isolation channel to transmit the signal to the isolated secondary side.
  • This method requires two isolation channels and consumes a lot of power during operation. , the cost of the wafer is high, and more wire bonding is required when the chip is packaged, and the packaging cost is high.
  • Figure 2 is a single-channel isolated communication based on clock data recovery technology.
  • the data signal synchronized with the clock on the source side is sent to the isolated secondary side in serial mode through the transmitter, and the secondary side uses the clock data recovery circuit to convert the clock from the received data signal. It is extracted, and then the data is re-sampled with the extracted clock, and finally the recovered clock and data signals are obtained.
  • Figure 3 is a common clock data recovery circuit and timing based on a phase-locked loop circuit.
  • the circuits shown in Fig. 2 and Fig. 3 have the following technical disadvantages: (1) It is impossible to communicate a long series of "0" or "1" signals; (2) The data code rate and phase of the transmitted signal are restored with the clock data of the receiving end The frequency and phase of the voltage-controlled oscillator in the circuit are deviated, and it takes a long time to complete the locking of frequency and phase. Therefore, it takes a long time to establish communication; (3) the clock data recovery circuit needs to lock the frequency first and then lock the phase. There are many loops, the design complexity is high, and the implementation cost is high.
  • the purpose of the present invention is to design a method for high-efficiency communication, which can simultaneously encode clock signals and data signals, reduce circuit complexity, and reduce chip packaging and wiring.
  • an embodiment of the present invention provides a single-channel communication encoding method, including: synthesizing a clock signal and a data signal into a long-short code signal; the long-short code signal includes a long-code signal and a short-code signal, The pulse width of the long code signal is consistent with the clock signal, and the pulse width of the short code signal is consistent with the clock signal; the duty cycle of the long code signal and the short code signal is different.
  • synthesizing the clock signal and the data signal into a long-short code signal includes: generating a first delayed clock signal according to the clock signal; generating a pulse signal according to the first delayed clock signal; generating a pulse signal according to the pulse signal Generate the high level of the long code signal and the high level of the short code signal; produce the second delayed clock signal according to the first delayed clock signal; generate the low level of the short code signal according to the second delayed clock signal; The signal generates the low level of the long code signal; generates the data delay signal according to the first delayed clock signal and the data signal; selects the long code signal or the short code signal according to the data signal and generates the long and short code signal.
  • the delay time of the first delayed clock signal relative to the clock signal is TS; the delay time of the second delayed clock signal relative to the first delayed clock signal is TS; the data delay signal The delay time relative to the data signal is TS.
  • synthesizing the clock signal and the data signal into a long-short code signal further includes: generating a first pulse signal according to the clock signal; generating a first delayed clock signal according to the clock signal; generating a first delayed clock signal according to the first delayed clock The signal generates a second delayed clock signal; generates a second pulse signal according to the second delayed clock signal; generates a third pulse signal according to the first delayed clock signal; generates a high voltage of a long code signal according to the third pulse signal.
  • the high level of the flat or short code signal generate a data delay signal according to the data signal and the first delayed clock signal; select the first pulse signal or the second pulse signal according to the data delay signal;
  • the low level of the short code signal is generated by the second pulse signal; the low level of the long code signal is generated according to the selected first pulse signal.
  • an embodiment of the present invention provides a single-channel communication encoding circuit, including: a first delay circuit for generating a first delayed clock signal according to a clock signal; a pulse generator for generating a first delayed clock signal according to the clock signal; The first delayed clock signal generates a pulse signal; the long code trigger receives the pulse signal at its reset end, and outputs the high level of the long code signal, and its clock terminal receives the clock signal, and the clock signal triggers the low level of the long code signal output level; the short code trigger, its reset end receives the pulse signal, and outputs the high level of the short code signal; the second delay circuit is used to generate a second delayed clock signal according to the first delayed clock signal; the The clock end of the short code flip-flop receives the second delayed clock signal, and outputs the low level of the short code signal; the flip-flop is selected, its clock end receives the first delayed clock signal, the data end is connected to the data signal, and the output end outputs Data delay signal; data select
  • an embodiment of the present invention provides a single-channel communication encoding circuit, including: a first delay circuit for generating a first delayed clock signal according to a clock signal; a second delay circuit for generating a first delayed clock signal according to the first delay circuit A delayed signal generates a second delayed clock signal; a first pulse generator is used to generate a first pulse signal according to the first delayed clock signal; a second pulse generator is used to generate a second pulse according to the second delayed clock signal signal; a third pulse generator, which is used for the first delayed clock signal to generate a third pulse signal; a trigger is selected, its clock end receives the first delayed clock signal, the data end is connected to the data signal, and the output end outputs the data delay signal; A data selector, the first input end of which is connected to the first pulse generator, and the second input end is connected to the second pulse generator; the selection end of the data selector is connected to a data delay signal, and is delayed according to the data The signal selects the first pulse signal or the
  • an embodiment of the present invention provides a single-channel communication decoding method, including: generating a low level of a clock signal according to the high level of the long-short code signal; generating a delayed pulse signal according to the long-short code signal, so The delay time of the delayed pulse signal is half a clock cycle; the high level of the clock signal is generated according to the delayed pulse signal; and the digital signal is generated according to the clock signal and the long-short code signal.
  • the generating the delayed pulse signal according to the long-short code signal further includes: generating the long-short code delayed signal according to the long-short code signal, and controlling the phase difference between the long-short code delayed signal and the long-short code signal The delay time of the long and short code signals.
  • controlling the delay time of the long-short code signal according to the phase difference between the long-short code delay signal and the long-short code signal further includes: converting the phase difference signal into a voltage signal, and according to the voltage The signal controls the delay time of the long and short code delay signal.
  • an embodiment of the present invention provides a single-channel communication decoding circuit, including: a delay pulse circuit, which is used to delay the long and short code signals by half a clock cycle and generate long and short code delayed signals; a pulse generator, It is used to generate a delayed pulse signal according to the long and short code delay signal; a clock trigger, whose clock terminal is connected to the long and short code signal and generates a low level of the clock signal according to the long and short code signal, and resets the terminal and the output of the pulse generator
  • the clock trigger is connected to the high level of the clock signal according to the delayed pulse signal;
  • the digital signal trigger is connected to the output terminal of the clock trigger, and the data terminal is connected to the long and short code signal , the digital signal trigger generates a digital high level or a digital low level according to a clock signal.
  • the delay pulse circuit includes a delay circuit and a pulse circuit
  • the delay circuit includes: an intermediate stage of the delay circuit, which is used to convert the long-short code signal into a long-short code delayed signal;
  • a phase detector is used to detect the phase difference between the long-short code delay signal and the long-short code signal;
  • a charge pump is used to convert the phase difference into a current signal;
  • a low-pass filter is used to convert the current signal into A voltage signal; wherein, the intermediate stage of the delay circuit is connected to the low-pass filter, and the intermediate stage of the delay circuit is used to receive the voltage signal and control the delay time of the long and short code delayed signal.
  • the decoding circuit further includes an inversion detector, an oscillator, and a data selector; when there is no communication, the inversion detector outputs a low level, and the data selector outputs the The output of the oscillator is connected to the delay locked loop, and a voltage signal is established; when communicating, the flip detector outputs a high level, and the data selector connects the long and short code signals to the delay pulse circuit.
  • the present invention has at least the following beneficial technical effects: (1) use the long-short code coding scheme to integrate the data signal and the clock signal for communication, which has higher efficiency and lower power consumption; (2) supports single-channel communication Chip packaging and wire bonding can be reduced, and chip manufacturing costs can be reduced; (3) the encoding circuit and the decoding circuit are simple in structure, reducing the complexity of circuit design; (4) the communication establishment time is short.
  • FIG. 1 is a schematic diagram of a communication circuit in the prior art.
  • FIG. 2 is a schematic diagram of another communication circuit in the prior art.
  • Fig. 3 is a schematic diagram of another communication circuit in the prior art.
  • Fig. 4 is a schematic structural diagram of the communication circuit of the present invention.
  • Fig. 5 is a schematic diagram of the encoding sequence of the present invention.
  • Fig. 6 is a schematic flow chart of the encoding method of the present invention.
  • Fig. 7 is a schematic structural diagram of the encoding circuit of the present invention.
  • Fig. 8 is a schematic diagram of the sequence of the encoding circuit of the present invention.
  • FIG. 9 is a schematic flowchart of another encoding method of the present invention.
  • Fig. 10 is a schematic diagram of another circuit structure of the present invention.
  • FIG. 11 is a schematic diagram of another circuit sequence of the present invention.
  • Fig. 12 is a schematic flow chart of the decoding method of the present invention.
  • Fig. 13 is a schematic structural diagram of the decoding circuit of the present invention.
  • Fig. 14 is a schematic diagram of the timing sequence of the decoding circuit of the present invention.
  • FIG. 15 is a schematic structural diagram of a decoding circuit including a delay circuit according to the present invention.
  • FIG. 16 is a schematic structural diagram of a decoding circuit of the present invention including a circuit for pre-establishing a control voltage.
  • FIG. 4 it is a schematic structural diagram of a communication circuit such as a digital isolation chip or an isolation amplifier chip.
  • the communication circuit includes a source side 401 and a secondary side 403, the source side 401 sends communication data, and the secondary side 403 receives communication data.
  • the source side 401 includes an encoder 402 and a transmitter 404
  • the secondary side 403 includes a receiver 406 and a decoder 408 .
  • the transmitter 404 and the receiver 406 are connected through an isolation capacitor 410 .
  • the input terminal of the encoder 402 is used to receive the data signal TD and the clock signal TCLK, and the output terminal of the decoder 408 outputs the digital signal RD and the clock signal RCLK.
  • FIG. 5 is a schematic diagram of the encoding sequence of the data signal TD, the clock signal TCLK, and the long-short code signal WNP according to the present invention.
  • the clock signal TCLK and the data signal TD are synthesized into one long-short code signal WNP by an encoding method.
  • the long and short code signal WNP includes the long code signal WP and the short code signal NP, the pulse width of the long code signal WP is consistent with the clock signal TCLK, the pulse width of the short code signal NP is consistent with the clock signal TCLK; the long code signal WP and the short code signal NP The duty cycle is different.
  • the duty cycle of the high and low levels of the long code signal WP is greater than the duty cycle of the high and low levels of the short code signal NP.
  • the long code signal WP is used to indicate that the data signal TD is "1"
  • the short code signal NP is used to indicate that the data signal TD is "0".
  • Tclk is the clock period
  • TS is the short code signal
  • the high level time of NP, TL is the high level time of the long code signal WP, and TS is not equal to TL.
  • the pulse width of the low level of the long code signal WP is equal to the high level of the short code signal NP.
  • the data signal TD and the clock signal TCLK are integrated and communicated through the long-short code coding scheme, which has higher efficiency and lower power consumption.
  • supporting single-channel communication can reduce chip packaging and wiring, and reduce chip manufacturing costs.
  • the encoding circuit and the decoding circuit have simple structures, which reduces the complexity of circuit design.
  • the present invention is essentially different from the traditional OOK method.
  • an oscillating signal (ON) is used to represent 1
  • no oscillating signal (OFF) is used to represent 0.
  • the long and short code signals WNP of different duty ratios are transmitted by the OOK method, that is, the high level in the long and short code signal WNP is transmitted with ON, and the low level in the long and short code signal WNP is transmitted with OFF, that is, High and low levels are represented by ON or OFF, but the content of the data signal TD is represented by different duty cycles of the long and short code signal WNP.
  • FIG. 6 it is a schematic flow chart of the long and short code encoding method, which includes steps after obtaining the "clock signal":
  • 606 Generate the high level of the long code signal and the high level of the short code signal according to the pulse signal;
  • steps 602 to 616 will be further explained in detail in conjunction with the circuit structure shown in FIG. 7 and the timing sequence shown in FIG. 8 .
  • Circuits such as delay circuits, pulse generators, flip-flops, and data selectors included in Fig. 7 and other accompanying drawings are all standard devices, and the present invention no longer discusses these standard devices, and those skilled in the art can knowledge realized.
  • the clock signal TCLK is connected to the first delay circuit (Delay) 702, and the output terminal of the first delay circuit 702 is connected to the pulse generator (One-shot) 706, and the pulse generator 706 operates according to the sequence shown in the bottom right of Figure 7, and its
  • the output terminal is connected to the reset terminal S of the long code trigger 708 and the short code trigger 710; the data terminal D of the long code trigger 708 and the short code trigger 710 is grounded, and the output of the long code trigger 708 and the short code trigger 710 End Q is respectively connected to the first input terminal (No. 1 terminal of MUX, wherein MUX is called as Multiplexer, and the Chinese translation is called data selector) and the second input terminal (No.
  • the second delay circuit The input end of (Delay) 704 is connected with the output end of the first delay circuit 702, and the output end of the second delay circuit 704 is connected with the clock end of short code flip-flop 710;
  • the clock terminal is connected, the data signal TD is connected to the data terminal D of the selection flip-flop 716 , and the output terminal Q of the selection flip-flop 716 is connected to the selection terminal Sel of the data selector 712 .
  • the data selector 712 also includes an output terminal for outputting the long and short code information WNP.
  • a first delayed clock signal TD1 is generated according to the clock signal TCLK.
  • the first delay circuit 702 generates a first delayed clock signal TD1 according to the clock signal TCLK, and the delay time of the first delayed clock signal TD1 relative to the clock signal TCLK is TS.
  • step 604 a pulse signal is generated according to the first delayed clock signal TD1.
  • the rising edge of the first delayed clock signal TD1 triggers the pulse generator 706, and the pulse generator 706 generates a pulse signal according to the first delayed clock signal TD1, and the pulse signal is sent to the reset terminal of the long code flip-flop 708 and the short code flip-flop 710 S.
  • step 606 the long code trigger 708 and the short code trigger 710 generate the high level 8022 of the long code signal WP and the high level 8024 of the short code signal NP according to the pulse signal; and after the pulse signal disappears, the long code signal WP and the short code signal NP can maintain a high level state.
  • a second delayed clock signal TD2 is generated according to the first delayed clock signal TD1.
  • the second delay circuit 704 generates a second delayed clock signal TD2 according to the first delayed clock signal TD1, and the delay time of the second delayed clock signal TD2 relative to the first delayed clock signal TD1 is TS.
  • the clock terminal of the short code flip-flop 710 When the rising edge of the second delayed clock signal TD2 occurs, the clock terminal of the short code flip-flop 710 is at a high level, and the short code flip-flop 710 outputs a low level at which the data terminal D is grounded, thereby generating a low level of the short code signal NP Flat 804.
  • step 612 a low level 808 of the long code signal WP is generated according to the clock signal.
  • the clock terminal of the long code trigger 708 receives the clock signal to trigger the level of the output data terminal D, and the data terminal D is grounded. At this time, the output signal forms the low voltage of the long code signal WP Flat 808.
  • a data delay signal TDD1 is generated according to the first delayed clock signal TD1 and the data signal TD.
  • the first delayed clock signal TD1 is delayed by TS than the clock signal TCLK or the data signal TD, and the data signal TD and the clock signal TCLK are synchronized. Therefore, the first delayed clock signal TD1 is used as the clock source, and the data signal TD is connected to the data terminal of the selection flip-flop 716 , the data delay signal TDD1 will be generated synchronously. That is, the delay time of the data delay signal TDD1 relative to the data signal TD is TS.
  • step 616 the long code signal WP or the short code signal NP is selected according to the data signal TD and the long code signal WNP is generated.
  • the data delay signal TDD1 is connected to the selection terminal Sel of the data selector 712.
  • the long code signal WP is selected for output, corresponding to the input signal at the first input terminal in the figure;
  • the data delay signal TDD1 is at a low level, Select the short code signal NP output, corresponding to the input signal of the second input terminal in the figure, the data delay signal TDD1 is synchronized with the long and short code signal WNP, and the long code signal WP or the short code signal NP is selected to be output according to the data delay signal TDD1, thereby forming a long and short code signal WNP encoding.
  • the present invention provides another single-channel communication encoding method. It includes the following steps after obtaining the "clock signal":
  • Steps 902 to 920 will be further explained in detail below in conjunction with the circuit structure shown in FIG. 10 and the timing diagram shown in FIG. 11 .
  • the encoding circuit includes a first delay circuit (Delay) 1002, a second delay circuit (Delay) 1004, a first pulse generator (One-shot1) 1006, a second pulse generator (One-shot2) 1008, a second pulse generator (One-shot2) 1008, Three-shot generator (One-shot3) 1014, data selector (MUX) 1010, selection flip-flop 1012, output flip-flop 1016.
  • the clock signal TCLK is connected to the first delay circuit 1002 and the first pulse generator 1006 .
  • the output end of the first delay circuit 1002 is connected to the input end of the second delay circuit 1004, the output end of the second delay circuit 1004 is connected to the input end of the second pulse generator 1008, and the output end of the second pulse generator 1008 is connected to the data selector The second input end of 1010 (end 0 of MUX).
  • the output terminal of the first pulse generator 1006 is connected to the first input terminal of the data selector 1010 (No. 1 terminal of MUX), the data signal TD is connected to the data input terminal D of the selection flip-flop 1012, and the output terminal Q of the selection flip-flop 1012 is connected to The selection terminal Sel of the data selector 1010 (that is, the selection terminal Sel of the data selector 1010 is connected to the data delay signal TDD1), the output terminal of the third pulse generator 1014 is connected to the reset terminal S of the output flip-flop 1016, and the output flip-flop 1016
  • the clock terminal of the data selector 1010 is connected to the output terminal to form a node A (Node A).
  • the output flip-flop 1016 also includes a grounded data terminal D and an output terminal Q for outputting the long and short code signal WNP.
  • step 902 according to clock signal TCLK node A (Node A) place produces the first pulse signal P1, the rising edge 1102 of clock signal triggers the first pulse generator 1006, the first pulse generator 1006 generates a first pulse signal P1 according to the first delayed clock signal (ie rising edge 1102 ), and the first pulse signal P1 is input to the first input terminal of the data selector 1010 .
  • step 904 a first delayed clock signal TD1 is generated according to the clock signal TCLK.
  • the first delay circuit 1002 generates the first delayed clock signal TD1 according to the clock signal TCLK.
  • the first delayed clock signal TD1 serves as the basis of the second delayed clock signal TD2.
  • the delay time of the first delayed clock signal TD1 relative to the clock signal is TS.
  • step 906 a second delayed clock signal TD2 is generated according to the first delayed clock signal TD1.
  • the second delay circuit 1004 generates a second delayed clock signal TD2 according to the first delayed signal TD1, and the delay time of the second delayed clock signal TD2 relative to the first delayed clock signal TD1 is TS.
  • a second pulse signal P2 is generated according to the second delayed clock signal TD2.
  • the second pulse generator 1008 generates a second pulse signal P2 according to the second delayed clock signal TD2, and the second pulse signal P2 is used to make the output flip-flop 1016 output a low level.
  • a third pulse signal (not shown in the timing diagram) is generated according to the first delayed clock signal TD1.
  • the third pulse generator 1014 generates a third pulse signal according to the first delayed clock signal TD1.
  • step 912 the third pulse signal resets the output flip-flop 1016 to generate a high level 1104 of the long code signal WP or a high level 1106 of the short code signal NP (the long code signal WP and the short code signal NP are described in the length code signal WNP).
  • a data delay signal TDD1 is generated according to the data signal TD and the first delayed clock signal TD1.
  • the clock terminal of the selection flip-flop 1012 receives the first delayed clock signal TD1, the data terminal D is connected to the data signal TD, the output terminal Q outputs the data delayed signal TDD1, and the data delayed signal TDD1 is synchronized with the first delayed clock signal TD1.
  • step 916 the first pulse signal P1 or the second pulse signal P2 is selected according to the data delay signal TDD1.
  • the data selector 1012 selects the first pulse signal P1 or the second pulse signal P2 according to the data delay signal TDD1 .
  • the data selector 1012 When the data delay signal TDD1 is at a high level, the data selector 1012 outputs a first pulse signal P1; when the data delay signal TDD1 is at a low level, the data selector 1012 outputs a second pulse signal P2.
  • step 920 a low level 1108 of the long code signal WP is generated according to the selected first pulse signal P1.
  • the rising edge of the first pulse signal P1 is aligned with the rising edge of the clock signal TCLK, therefore, the first pulse signal P1 causes the output flip-flop 1016 to generate the low level 1108 of the long code signal WP, and then the third pulse generator 1014 generates a pulse signal, pull up the output level of the output flip-flop 1016 again to form the high level 1104 of the long code signal WP, thereby completing a long code encoding.
  • step 918 a low level 1110 of the short code signal NP is generated according to the selected second pulse signal P2.
  • the delay time of the rising edge of the second pulse signal P2 relative to the first delayed clock signal TD1 is TS, and after the output flip-flop 1016 is high for the delay time TS, the output level of the output flip-flop 1016 is pulled by the second pulse signal P2
  • the low level 1110 of the short code signal NP is formed low, and after the rising edge of the subsequent first delayed clock signal TD1 appears, the third pulse generator 1014 generates a pulse signal, and the output level of the output flip-flop 1016 is pulled up again to form
  • the high level 1106 of the short code signal NP completes one short code encoding.
  • the decoding method of single-channel communication comprises the following steps after obtaining the "long and short code signal":
  • steps 1202 to 1208 will be further explained in detail in conjunction with the circuit structure shown in FIG. 13 and the timing diagram shown in FIG. 14 .
  • the circuit structure includes a delay pulse circuit (Delay 0.5Tclk) 1302, a pulse generator (One-shot) 1304, a clock flip-flop 1306, and a digital signal flip-flop 1308.
  • the delay pulse circuit 1302 is connected with the long and short code signal WNP, the output terminal of the delay pulse circuit 1302 is connected with the pulse generator 1304, the data terminal D of the digital signal trigger 1308 is connected with the long and short code signal WNP, and the clock terminal of the clock trigger 1306 is connected with the long and short code signal WNP.
  • the code signal WNP is connected, the reset end S of the clock flip-flop 1306 is connected with the output end of the pulse generator 1304, to receive the delay pulse signal SET, the output Q of the clock flip-flop 1306 is connected with the clock end of the digital signal flip-flop 1308, To output the clock signal RCLK.
  • the clock flip-flop 1306 also includes a grounded data terminal D, and the digital signal flip-flop 1308 also includes an output terminal Q for outputting a digital signal RD.
  • a low level 1402 of the clock signal RCLK is generated according to the high level of the long and short code signal WNP.
  • the output terminal Q of the clock flip-flop 1306 outputs the low level 1402 (included in the clock signal RCLK) of the data terminal D, that is, the clock flip-flop 1306 according to the long-short code signal WNP Generate the low level of the clock signal RCLK.
  • a delayed pulse signal SET is generated according to the long-short code signal WNP, and the delay time of the delayed pulse signal SET is half a clock period (0.5Tclk).
  • the delay pulse circuit 1302 delays the long and short code signal WNP by half a clock cycle and generates a long and short code delay signal.
  • the pulse generator 1304 generates a delay pulse signal SET according to the long and short code delay signal.
  • the rising edge 1404 of signal WNP is half a clock period long.
  • step 1206 the delay pulse signal SET resets the output terminal Q of the clock flip-flop 1306 to output a high level, which constitutes the high level of the clock signal RCLK.
  • Multiple clock signals RCLK can be generated by repeating steps 1202 to 1206 .
  • a digital signal RD is generated according to the clock signal RCLK and the long-short code signal WNP.
  • the digital signal flip-flop 1308 generates a digital high level or a digital low level 1406 included in the digital signal RD according to the clock signal RCLK.
  • the output signal of the digital signal flip-flop 1308 is the high level of the long code signal WP or the low level of the short code signal NP, so that The output decoded high and low level signals correspond exactly to the WNP encoding of the long and short code signals.
  • generating the delayed pulse signal SET according to the long and short code signal WNP further includes: generating the long and short code delay signal according to the long and short code signal WNP, and controlling the long and short code signal WNP according to the phase difference between the long and short code delay signal and the long and short code signal WNP delay.
  • controlling the delay time of the long and short code signal WNP according to the phase difference between the long and short code delay signal and the long and short code signal WNP further includes: converting the phase difference signal corresponding to the phase difference into a voltage signal, and controlling the long and short code according to the voltage signal The delay time of the delayed signal.
  • the single-channel communication decoding circuit shown in FIG. 15 it includes the internal structure of the delay circuit of the delay pulse circuit 1302 in FIG. 13 , and the delay pulse circuit 1302 may also include a pulse circuit.
  • a delay circuit intermediate stage 1502 for converting the long and short code signal WNP into a long and short code delayed signal WNPD; a frequency and phase detector 1504 for detecting the phase difference between the long and short code delayed signal WNPD and the long and short code signal WNP ;
  • the charge pump 1506 is used to convert the phase difference into a current signal;
  • the low-pass filter 1508 is used to convert the current signal into a voltage signal Vctrl;
  • the delay circuit intermediate stage 1502 is connected to the output end of the low-pass filter 1508, and the delay circuit
  • the intermediate stage 1502 is used for receiving the voltage signal Vctrl and controlling the delay time of the long and short code delay signal WNPD.
  • the above-mentioned feedback loop from the phase signal to the voltage signal formed by the frequency detector 1504 and the low-pass filter 1508 can precisely control the time of the delay circuit, making its delay time control more precise, combined with other parts of the decoding circuit, So as to restore the precise clock signal RCLK.
  • the other parts include a pulse generator One-shot, a clock flip-flop and a digital signal flip-flop.
  • the input terminal of the pulse generator One-shot is connected to the long-short code delay signal WNPD, and the output terminal is connected to the reset terminal S of the clock flip-flop to output the delayed pulse signal Set.
  • the data terminal D of the clock trigger is grounded, the clock terminal is connected to the long and short code signal WNP, and the clock signal RCLK is output through the output terminal Q.
  • the clock terminal of the digital signal trigger is connected to the output terminal Q of the clock trigger, the data terminal D is connected to the long and short code signal WNP, and the output terminal Q outputs a digital signal RD.
  • a circuit for pre-establishing the control voltage is further added, including a flip detector 602 , an oscillator 604 (period is Tosc) and a data selector (MUX) 608 .
  • Oscillator 604 is connected to the second input end (No. 0 end of MUX) of data selector 608, and the long-short code signal WNP accesses the first input end (No. 1 end of MUX) of data selector 608 and the input of inversion detector 602
  • the output terminal of the flip detector 602 is connected to the selection terminal Sel of the data selector 608, and the output terminal of the data selector 608 replaces the WNP input of the circuit in FIG. 15 .
  • the flip detector 602 When there is no communication, the flip detector 602 outputs a low level, and the data selector 608 connects the output of the oscillator 604 to the delay-locked loop (including the rear-side delay circuit intermediate stage 1502, frequency and phase detector, charge pump, low-pass The circuit formed by the filter), and establishes the voltage signal Vctrl.
  • the delay-locked loop including the rear-side delay circuit intermediate stage 1502, frequency and phase detector, charge pump, low-pass The circuit formed by the filter
  • the inversion detector 602 When communicating, the inversion detector 602 outputs a high level, and the data selector 608 connects the long and short code signal WNP to the delay pulse circuit.
  • pulse generator One-shot is connected to the long-short code delay signal WNPD
  • the output terminal is connected to the reset terminal S of the clock trigger and outputs the delayed pulse signal Set
  • the data terminal D of the clock trigger is grounded, and the clock terminal is connected to the long-short code signal WNP, and output the clock signal RCLK through the output terminal Q
  • the clock terminal of the digital signal trigger is connected to the output terminal Q of the clock trigger, the data terminal D is connected to the long and short code signal WNP, and the output terminal Q outputs a digital signal RD.
  • the frequency and phase detector is connected to the charge pump through two output terminals to output control signals UP and DOWN.
  • the delay locked loop Since the delay locked loop has established the voltage signal Vctrl of the voltage-controlled delay line (including the intermediate stage 1502 of the delay circuit) when not communicating, and the voltage signal Vctrl is close to the final voltage signal during communication, therefore, the long and short code signal WNP Accurate communication is achieved immediately upon arrival, eliminating the need for the settling time required by general clock data recovery circuits, enabling rapid communication establishment.

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Abstract

本发明涉及一种单通道通信编码方法、解码方法、编码电路及解码电路，单通道通信编码方法包括：将时钟信号和数据信号合成一路长短码信号；长短码信号包括长码信号和短码信号，长码信号的脉宽与时钟信号一致，短码信号的脉宽与时钟信号一致；长码信号与短码信号的占空比不同，本编码方法同时编码时钟信号和数据信号，能降低电路复杂度，以及减少芯片封装打线。

Description

单通道通信编码方法、解码方法、编码电路及解码电路
本申请要求了申请日为2021年10月15日，申请号为202111200511.4，发明名称为“单通道通信编码方法、解码方法、编码电路及解码电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于模数混合电路领域，具体涉及一种单通道通信编码方法、解码方法、编码电路及解码电路。
背景技术
数字隔离器用于通信，其包括源边和副边，副边接收源边发送的信号。
图1是一种常见的数据与时钟隔离传输的方式，源边的数据与时钟分别使用一个隔离通道将信号传输到隔离的副边，该方式需要占用两个隔离通道，工作时功耗较大，晶圆成本较高，且芯片封装时需要更多打线，封装成本较高。
图2为基于时钟数据恢复技术的单通道隔离通信，源边同步于时钟的数据信号通过发送器以串行方式发送到隔离的副边，副边通过时钟数据恢复电路将时钟从接收的数据信号里提取出来，然后用提取的时钟对数据进行重新采样，最终得到了恢复的时钟和数据信号。
图3是一种常见的基于锁相环电路的时钟数据恢复电路和时序。
图2和图3所示的电路都有以下技术缺点：(1)无法通信一长串的“0”或“1”信号；(2)传输信号的数据码率、相位与接收端时钟数据恢复电路中压控振荡器的频率、相位有偏差，需要较长的时间完成频率和相位的锁定，因此，需要较长时间建立通信；(3)时钟数据恢复电路需要先锁定频率再锁定相位，控制环路较多，设计复杂度较高，实现成本较高。
发明内容
本发明目的是设计一种高效通信的方法，能同时编码时钟信号和数据信号，降低电路复杂度，减少芯片封装打线。
为实现上述发明目的之一，本发明一实施方式提供一种单通道通信编码方法，包括：将时钟信号和数据信号合成一路长短码信号；所述长短码信号包括长码信号和短码信号，所述长码信号的脉宽与时钟信号一致，所述短码信号的脉宽与时钟信号一致；所述长码信号与所述短码信号的占空比不同。
作为本发明一实施方式的进一步改进，所述长短码信号的占空比满足关系式：Tclk＝TS+TL，其中，Tclk为时钟周期，TS为短码信号的高电平时间，TL为长码信号的高电平时间，且TS不等于TL。
作为本发明一实施方式的进一步改进，将时钟信号和数据信号合成一路长短码信号包括：根据时钟信号产生第一延迟时钟信号；根据所述第一延迟时钟信号产生脉冲信号；根据所述脉冲信号生成长码信号的高电平和短码信号的高电平；根据所述第一延迟时钟信号产生第二延迟时钟信号；根据所述第二延迟时钟信号生成短码信号的低电平；根据时钟信号生成长码信号的低电平；根据所述第一延迟时钟信号和数据信号产生数据延迟信号；根据数据信号选择所述长码信号或所述短码信号 并生成长短码信号。
作为本发明一实施方式的进一步改进，所述第一延迟时钟信号相对于时钟信号延迟时间为TS；所述第二延迟时钟信号相对于第一延迟时钟信号延迟时间为TS；所述数据延迟信号相对于数据信号延迟时间为TS。
作为本发明一实施方式的进一步改进，将时钟信号和数据信号合成一路长短码信号进一步包括：根据时钟信号产生第一脉冲信号；根据时钟信号产生第一延迟时钟信号；根据所述第一延迟时钟信号产生第二延迟时钟信号；根据所述第二延迟时钟信号产生第二脉冲信号；根据所述第一延迟时钟信号产生第三脉冲信号；根据所述第三脉冲信号生成长码信号的高电平或短码信号的高电平；根据所述数据信号和所述第一延迟时钟信号产生数据延迟信号；根据所述数据延迟信号选择第一脉冲信号或第二脉冲信号；根据被选择的第二脉冲信号生成短码信号的低电平；根据被选择的第一脉冲信号生成长码信号的低电平。
为实现上述发明目的之一，本发明一实施方式提供一种单通道通信编码电路，包括：第一延迟电路，用于根据时钟信号产生第一延迟时钟信号；脉冲发生器，用于根据所述第一延迟时钟信号产生脉冲信号；长码触发器，其重置端接收所述脉冲信号，并输出长码信号的高电平，其时钟端接收时钟信号，时钟信号触发输出长码信号的低电平；短码触发器，其重置端接收所述脉冲信号，输出短码信号的高电平；第二延迟电路，用于根据所述第一延迟时钟信号产生第二延迟时钟信号；所述短码触发器的时钟端接收所述第二延迟时钟信号，并输出短码信号的低电平；选择触发器，其时钟端接收第一延迟时钟信号，数据端连接数据信号，输出端输出数据延迟信号；数据选择器，其第一输入端连接所述长码触发器的输出端，第二输入端连接短码触发器的输出端；选择端连接所述选择触发器的输出端，所述数据选择器根据所述数据延迟信号选择输出所述长码信号或短码信号并形成长短码信号。
为实现上述发明目的之一，本发明一实施方式提供一种单通道通信编码电路，包括：第一延迟电路，用于根据时钟信号产生第一延迟时钟信号；第二延迟电路，用于根据第一延迟信号产生第二延迟时钟信号；第一脉冲发生器，用于根据第一延迟时钟信号产生第一脉冲信号；第二脉冲发生器，用于根据所述第二延迟时钟信号产生第二脉冲信号；第三脉冲发生器，用于所述第一延迟时钟信号产生第三脉冲信号；选择触发器，其时钟端接收第一延迟时钟信号，数据端连接数据信号，输出端输出数据延迟信号；数据选择器，其第一输入端连接所述第一脉冲发生器，第二输入端连接所述第二脉冲发生器；所述数据选择器的选择端连接数据延迟信号，并根据所述数据延迟信号选择第一脉冲信号或第二脉冲信号；输出触发器，其重置端与所述第三脉冲发生器连接，时钟端与所述数据选择器的输出端连接；所述输出触发器根据所述第三脉冲信号产生长码信号的高电平或短码信号的高电平，所述时钟端收到所述第一脉冲信号并产生长码信号的低电平；所述时钟端收到所述第二脉冲信号并产生短码信号的低电平。
为实现上述发明目的之一，本发明一实施方式提供一种单通道通信解码方法，包括：根据长短码信号的高电平产生时钟信号的低电平；根据长短码信号产生延迟脉冲信号，所述延迟脉冲信号的延迟时间为半个时钟周期；根据所述延迟脉冲信号产生时钟信号的高电平；根据所述时钟信号和长短码信号产生数字信号。
作为本发明一实施方式的进一步改进，所述根据长短码信号产生延迟脉冲信号进一步包括：根据所述长短码信号产生长短码延迟信号，根据所述长短码延迟信号和长短码信号的相位差控制所述长短码信号的延迟时间。
作为本发明一实施方式的进一步改进，根据长短码延迟信号和长短码信号的相位差控制所述长短码信号的延迟时间进一步包括：将所述相位差的信号转换为电压信号，根据所述电压信号控制长短码延迟信号的延迟时间。
为实现上述发明目的之一，本发明一实施方式提供一种单通道通信解码电路，包括：延迟脉冲电路，用于将长短码信号延迟半个时钟周期并产生长短码延迟信号；脉冲发生器，用于根据所述长短码延迟信号产生延迟脉冲信号；时钟触发器，其时钟端与长短码信号连接并根据长短码信号产生时钟信号的低电平，重置端与所述脉冲发生器的输出端连接，所述时钟触发器根据所述延迟脉冲信号产生时钟信号的高电平；数字信号触发器，其时钟端与所述时钟触发器的输出端连接，数据端与所述长短码信号连接，所述数字信号触发器根据时钟信号生成数字高电平或数字低电平。
作为本发明一实施方式的进一步改进，所述延迟脉冲电路包括延迟电路和脉冲电路，所述延迟电路包括：延迟电路中间级，用于将所述长短码信号转换为长短码延迟信号；鉴频鉴相器，用于检测长短码延迟信号和长短码信号之间的相位差；电荷泵，用于将所述相位差转换为电流信号；低通滤波器，用于将所述电流信号转换为电压信号；其中，所述延迟电路中间级与所述低通滤波器连接，且所述延迟电路中间级用于接收所述电压信号并控制长短码延迟信号的延迟时间。
作为本发明一实施方式的进一步改进，所述解码电路进一步包括翻转检测器、振荡器和数据选择器；当不通信时，所述翻转检测器输出低电平，所述数据选择器将所述振荡器的输出接入延迟锁定环，并建立电压信号；当通信时，所述翻转检测器输出高电平，所述数据选择器将所述长短码信号接入所述延迟脉冲电路。
本发明相对现有技术至少有以下几方面的有益技术效果：(1)使用长短码编码方案将数据信号和时钟信号融合通信，效率更高，且功耗更低；(2)支持单通道通信可减少芯片封装和打线，降低芯片制造成本；(3)编码电路和解码电路结构简单，降低了电路设计复杂度；(4)通信建立时间短。
附图说明
图1是现有技术的通信电路示意图。
图2是另一现有技术的通信电路示意图。
图3是又一现有技术的通信电路示意图。
图4是本发明通信电路结构示意图。
图5是本发明编码时序示意图。
图6是本发明编码方法流程示意图。
图7是本发明编码电路结构示意图。
图8是本发明编码电路时序示意图。
图9是本发明另一种编码方法流程示意图。
图10是本发明另一种电路结构示意图。
图11是本发明另一种电路时序示意图。
图12是本发明解码方法流程示意图。
图13是本发明解码电路结构示意图。
图14是本发明解码电路时序示意图。
图15是本发明解码电路其中包含延迟电路的结构示意图。
图16是本发明解码电路其中包含用于预建立控制电压的电路的结构示意图。
具体实施方式
以下参照附图对本发明技术方案作进一步详尽的说明，以帮助本领域技术人员理解本发明的技术方案。以下按照编码解码的顺序叙述本发明技术方案。
编码方法
参图4，为数字隔离芯片或隔离放大芯片等通信电路结构示意图。
通信电路包括源边401和副边403，源边401发送通信数据，副边403接收通信数据。
源边401包括编码器402和发送器404，副边403包括接收器406和解码器408。
发送器404和接收器406之间通过隔离电容410连接。
编码器402的输入端用于接收数据信号TD和时钟信号TCLK，解码器408的输出端输出数字信号RD和时钟信号RCLK。
图5为本发明数据信号TD、时钟信号TCLK和长短码信号WNP的编码时序示意图，通过编码方法将时钟信号TCLK和数据信号TD合成一路长短码信号WNP。
长短码信号WNP包括长码信号WP和短码信号NP，长码信号WP的脉宽与时钟信号TCLK一致，短码信号NP的脉宽与时钟信号TCLK一致；长码信号WP与短码信号NP的占空比不同。
长码信号WP的高低电平的占空比大于短码信号NP的高低电平的占空比。长码信号WP用于表示数据信号TD为“1”，短码信号NP用于表示数据信号TD为“0”。
长码信号WP或短码信号NP的脉宽为一个时钟周期Tclk，并且，长短码信号WNP的占空比满足关系式：Tclk＝TS+TL，其中，Tclk为时钟周期，TS为短码信号NP的高电平时间，TL为长码信号WP的高电平时间，并且TS不等于TL。如图中所示，长码信号WP的低电平与短码信号NP的高电平的脉宽相等。
通过上述长短码编码方案将数据信号TD和时钟信号TCLK融合通信，效率更高功耗更低。同时，支持单通道通信可减少芯片封装和打线，降低芯片制造成本。并且，编码电路和解码电路结构简单，降低了电路设计复杂度。
需要指出的是，本发明和传统的OOK法有本质区别，OOK法是用振荡信号(ON)表示1，没有振荡信号(OFF)表示0。而本发明中不同占空比的长短码信号WNP是用OOK法传输的，即用ON传输长短码信号WNP中的高电平，用OFF传输长短码信号WNP中的低电平，亦即，用ON或OFF表示高低电平，但数据信号TD的内容则使用长短码信号WNP的不同占空比表示。
编码方法一
参照图6，是长短码编码方法流程示意图，其在获得“时钟信号”后包括步骤：
602：根据时钟信号产生第一延迟时钟信号；
604：根据第一延迟时钟信号产生脉冲信号；
606：根据脉冲信号生成长码信号的高电平和短码信号的高电平；
608：根据第一延迟时钟信号产生第二延迟时钟信号；
610：根据第二延迟时钟信号生成短码信号的低电平；
612：根据时钟信号生成长码信号的低电平；
614：根据第一延迟时钟信号和数据信号产生数据延迟信号；
616：根据数据信号选择长码信号或短码信号并生成长短码信号。
以下，结合图7所示的电路结构和图8所示的时序对步骤602至616做进一步详尽的解释。
图7及其他附图中所包含的延迟电路、脉冲发生器、触发器、数据选择器等电路均为标准器件，本发明不再对这些标准器件展开讨论，本领域技术人员能够根据其掌握的知识实现。
时钟信号TCLK连接第一延迟电路(Delay)702，第一延迟电路702的输出端连接脉冲发生器(One-shot)706，脉冲发生器706按照图7右下方示出的时序进行动作，且其输出端连接长码触发器708和短码触发器710的重置端S；长码触发器708和短码触发器710的数据端D接地，长码触发器708和短码触发器710的输出端Q分别连接数据选择器712的第一输入端(MUX的1号端，其中MUX全称为Multiplexer，中文译名为数据选择器)和第二输入端(MUX的0号端)；第二延迟电路(Delay)704的输入端与第一延迟电路702的输出端连接，第二延迟电路704的输出端连接短码触发器710的时钟端；第一延迟电路702的输出端与选择触发器716的时钟端连接，数据信号TD与选择触发器716的数据端D连接，选择触发器716的输出端Q与数据选择器712的选择端Sel连接。数据选择器712还包括用于输出长短码信息WNP的输出端。
参照图6至图8，在步骤602中，根据时钟信号TCLK产生第一延迟时钟信号TD1。
第一延迟电路702根据时钟信号TCLK产生第一延迟时钟信号TD1，第一延迟时钟信号TD1相对时钟信号TCLK的延迟时间为TS。
在步骤604中，根据第一延迟时钟信号TD1产生脉冲信号。
第一延迟时钟信号TD1的上升沿触发脉冲发生器706，脉冲发生器706根据第一延迟时钟信号TD1产生脉冲信号，该脉冲信号送入长码触发器708和短码触发器710的重置端S。
在步骤606中，长码触发器708和短码触发器710根据脉冲信号生成长码信号WP的高电平8022和短码信号NP的高电平8024；并且在脉冲信号消失后，长码信号WP和短码信号NP能够保持高电平状态。
在步骤608和步骤610中，根据第一延迟时钟信号TD1产生第二延迟时钟信号TD2。
第二延迟电路704根据第一延迟时钟信号TD1产生第二延迟时钟信号TD2，第二延迟时钟信号TD2相对于第一延迟时钟信号TD1的延迟时间为TS。
第二延迟时钟信号TD2上升沿出现时，短码触发器710的时钟端为高电平，短码触发器710输出数据端D接地的低电平，由此，生成短码信号NP的低电平804。
在步骤612中，根据时钟信号生成长码信号WP的低电平808。
在下一个时钟周期上升沿806到来时，长码触发器708的时钟端接收时钟信号，以触发输出数据端D的电平，数据端D接地，此时，输出信号形成长码信号WP的低电平808。
在步骤614中，根据第一延迟时钟信号TD1和数据信号TD产生数据延迟信号TDD1。
第一延迟时钟信号TD1比时钟信号TCLK或数据信号TD延迟TS，数据信号TD和时钟信号TCLK同步，因此，以第一延迟时钟信号TD1作为时钟源，数据信号TD连接选择触发器716数据端后，会同步产生数据延迟信号TDD1。也即数据延迟信号TDD1相对于数据信号TD延迟时间为TS。
在步骤616中，根据数据信号TD选择长码信号WP或短码信号NP并生成长短码信号WNP。
数据延迟信号TDD1与数据选择器712的选择端Sel连接，数据延迟信号TDD1为高电平时，选择长码信号WP输出，对应图中第一输入端的输入信号；数据延迟信号TDD1为低电平时，选择短码信号NP输出，对应图中第二输入端的输入信号，数据延迟信号TDD1与长短码信号WNP同步，根据数据延迟信号TDD1选择输出长码信号WP或短码信号NP，从而形成长短码信号WNP编码。
编码方法二
参照图9，本发明提供另一种单通道通信编码方法。其包括下述在得到“时钟信号”后的步骤：
902：根据时钟信号产生第一脉冲信号；
904：根据时钟信号产生第一延迟时钟信号；
906：根据第一延迟时钟信号产生第二延迟时钟信号；
908：根据第二延迟时钟信号产生第二脉冲信号；
910：根据第一延迟时钟信号产生第三脉冲信号；
912：根据第三脉冲信号生成长码信号的高电平或短码信号的高电平；
914：根据数据信号和第一延迟时钟信号产生数据延迟信号；
916：根据数据延迟信号选择第一脉冲信号或第二脉冲信号；
918：根据被选择的第二脉冲信号生成短码信号的低电平；
920：根据被选择的第一脉冲信号生成长码信号的低电平。
以下结合图10所示的电路结构和图11所示的时序图对步骤902至920做进一步详尽的解释。
参照图10，编码电路包括第一延迟电路(Delay)1002、第二延迟电路(Delay)1004、第一脉冲发生器(One-shot1)1006、第二脉冲发生器(One-shot2)1008、第三脉冲发生器(One-shot3)1014、数据选择器(MUX)1010、选择触发器1012、输出触发器1016。
时钟信号TCLK连接第一延迟电路1002、第一脉冲发生器1006。
第一延迟电路1002的输出端连接第二延迟电路1004的输入端，第二延迟电路1004的输出端连接第二脉冲发生器1008的输入端，第二脉冲发生器1008的输出端连接数据选择器1010的第二输入端(MUX的0号端)。
第一脉冲发生器1006的输出端连接数据选择器1010的第一输入端(MUX的1号端)，数据信号TD连接选择触发器1012的数据输入端D，选择触发器1012的输出端Q连接数据选择器1010的选择端Sel(也即数据选择器1010的选择端Sel连接数据延迟信号TDD1)，第三脉冲发生器1014的输出端连接输出触发器1016的重置端S，输出触发器1016的时钟端连接数据选择器1010的输出端形成结点A(Node A)。输出触发器1016还包括接地的数据端D和用于输出长短码信号WNP的输 出端Q。
参照图9至图11，在步骤902中，根据时钟信号TCLK结点A(Node A)处产生第一脉冲信号P1，时钟信号的上升沿1102触发第一脉冲发生器1006，第一脉冲发生器1006根据第一延迟时钟信号(即上升沿1102)产生第一脉冲信号P1，该第一脉冲信号P1输入数据选择器1010的第一输入端。
在步骤904中，根据时钟信号TCLK产生第一延迟时钟信号TD1。
第一延迟电路1002根据时钟信号TCLK产生第一延迟时钟信号TD1，第一延迟时钟信号TD1作为第二延迟时钟信号TD2的基础，第一延迟时钟信号TD1相对时钟信号的延迟时间为TS。
在步骤906中，根据第一延迟时钟信号TD1产生第二延迟时钟信号TD2。
第二延迟电路1004根据第一延迟信号TD1产生第二延迟时钟信号TD2，第二延迟时钟信号TD2相对第一延迟时钟信号TD1的延迟时间为TS。
在步骤908中，根据第二延迟时钟信号TD2产生第二脉冲信号P2。第二脉冲发生器1008根据第二延迟时钟信号TD2产生第二脉冲信号P2，该第二脉冲信号P2用于使得输出触发器1016输出低电平。
在步骤910中，根据第一延迟时钟信号TD1产生第三脉冲信号(时序图中未示出)。
第三脉冲发生器1014根据第一延迟时钟信号TD1产生第三脉冲信号。
在步骤912中，该第三脉冲信号重置输出触发器1016而产生长码信号WP的高电平1104或短码信号NP的高电平1106(长码信号WP和短码信号NP记载于长短码信号WNP中)。
在步骤914中，根据数据信号TD和第一延迟时钟信号TD1产生数据延迟信号TDD1。
选择触发器1012的时钟端接收第一延迟时钟信号TD1，数据端D连接数据信号TD，输出端Q输出数据延迟信号TDD1，该数据延迟信号TDD1与第一延迟时钟信号TD1同步。
在步骤916中，根据数据延迟信号TDD1选择第一脉冲信号P1或第二脉冲信号P2。
数据选择器1012根据数据延迟信号TDD1选择第一脉冲信号P1或第二脉冲信号P2。数据延迟信号TDD1为高电平时，数据选择器1012输出第一脉冲信号P1；数据延迟信号TDD1为低电平时，数据选择器1012输出第二脉冲信号P2。
在步骤920中，根据被选择的第一脉冲信号P1生成长码信号WP的低电平1108。
第一脉冲信号P1的上升沿与时钟信号TCLK的上升沿对齐，因此，第一脉冲信号P1使得输出触发器1016产生长码信号WP的低电平1108，随后，第三脉冲发生器1014产生脉冲信号，重新将输出触发器1016的输出电平拉高形成长码信号WP的高电平1104，从而完成一次长码编码。
在步骤918中，根据被选择的第二脉冲信号P2生成短码信号NP的低电平1110。
第二脉冲信号P2的上升沿相对第一延迟时钟信号TD1的延迟时间为TS，在输出触发器1016高电平持续延迟时间TS后，输出触发器1016的输出电平被第二脉冲信号P2拉低形成短码信号NP的低电平1110，在随后的第一延迟时钟信号TD1的上升沿出现后，第三脉冲发生器1014产生脉冲信号，重新将输出触发器1016的输出电平拉高形成短码信号NP的高电平1106，从而完成一次短码编码。
解码方法
参照图12，单通道通信的解码方法包括下述在得到“长短码信号”后的步骤：
1202：根据长短码信号的高电平产生时钟信号的低电平；
1204：根据长短码信号产生延迟脉冲信号，延迟脉冲信号的延迟时间为半个时钟周期；
1206：根据延迟脉冲信号产生时钟信号的高电平；
1208：根据时钟信号和长短码信号产生数字信号。
以下，结合图13所示的电路结构和图14所示的时序图对步骤1202至1208做进一步详尽的解释。
参照图13，电路结构包括延迟脉冲电路(Delay 0.5Tclk)1302、脉冲发生器(One-shot)1304、时钟触发器1306、数字信号触发器1308。
延迟脉冲电路1302与长短码信号WNP连接，延迟脉冲电路1302的输出端与脉冲发生器1304连接，数字信号触发器1308的数据端D与长短码信号WNP连接，时钟触发器1306的时钟端与长短码信号WNP连接，时钟触发器1306的重置端S与脉冲发生器1304的输出端连接，以接收延迟脉冲信号SET，时钟触发器1306的输出端Q与数字信号触发器1308的时钟端连接，以输出时钟信号RCLK。时钟触发器1306还包括接地的数据端D，数字信号触发器1308还包括用于输出数字信号RD的输出端Q。
参照图12至图14，在步骤1202中，根据长短码信号WNP的高电平产生时钟信号RCLK的低电平1402。
长短码信号WNP上升沿1404输入时钟触发器1306后，时钟触发器1306输出端Q输出数据端D的低电平1402(包含于时钟信号RCLK中)，也即时钟触发器1306根据长短码信号WNP产生时钟信号RCLK的低电平。
在步骤1204中，根据长短码信号WNP产生延迟脉冲信号SET，延迟脉冲信号SET延迟时间为半个时钟周期(0.5Tclk)。
延迟脉冲电路1302将长短码信号WNP延迟半个时钟周期并产生长短码延迟信号，脉冲发生器1304根据该长短码延迟信号产生延迟脉冲信号SET，换言之，延迟脉冲信号SET的上升沿1408距离长短码信号WNP的上升沿1404的长度为半个时钟周期。
在步骤1206中，该延迟脉冲信号SET重置时钟触发器1306输出端Q而使之输出高电平，构成了时钟信号RCLK的高电平。
重复步骤1202至1206即可产生多个时钟信号RCLK。
在步骤1208中，根据时钟信号RCLK和长短码信号WNP产生数字信号RD。
数字信号触发器1308根据时钟信号RCLK生成包含于数字信号RD内的数字高电平或数字低电平1406。
由于时钟信号RCLK的上升沿1410恰好在数据信号的中间位置(半个周期处)，数字信号触发器1308的输出信号为长码信号WP的高电平或短码信号NP的低电平，使得输出的解码高低电平信号恰好与长短码信号WNP编码对应。
进一步地对上述方法改进，根据长短码信号WNP产生延迟脉冲信号SET进一步包括：根据长短码信号WNP产生长短码延迟信号，根据长短码延迟信号和长短码信号WNP的相位差控制长短码 信号WNP的延迟时间。
进一步地对上述方法改进，根据长短码延迟信号和长短码信号WNP的相位差控制长短码信号WNP的延迟时间进一步包括：将相位差对应的相位差信号转换为电压信号，根据电压信号控制长短码延迟信号的延迟时间。
参照图15所示的单通道通信的解码电路，其包括图13中延迟脉冲电路1302的延迟电路的内部结构，延迟脉冲电路1302还可以包括脉冲电路。
具体的，包括延迟电路中间级1502，用于将长短码信号WNP转换为长短码延迟信号WNPD；鉴频鉴相器1504，用于检测长短码延迟信号WNPD和长短码信号WNP之间的相位差；电荷泵1506，用于将相位差转换为电流信号；低通滤波器1508，用于将电流信号转换为电压信号Vctrl；延迟电路中间级1502与低通滤波器1508输出端连接，且延迟电路中间级1502用于接收电压信号Vctrl并控制长短码延迟信号WNPD的延迟时间。
上述由鉴频鉴相器1504至低通滤波器1508形成的、由相位信号到电压信号的反馈回路，能够精确控制延迟电路的时间，使得其延迟时间控制更加精准，结合解码电路的其他部分，从而还原出精确的时钟信号RCLK。
所述其他部分，与图13中电路相似地，包括脉冲发生器One-shot、时钟触发器和数字信号触发器。其中，脉冲发生器One-shot的输入端连接长短码延迟信号WNPD，输出端连接时钟触发器的重置端S并输出延迟脉冲信号Set。时钟触发器的数据端D接地，时钟端连接长短码信号WNP，且通过输出端Q输出时钟信号RCLK。数字信号触发器的时钟端与时钟触发器的输出端Q连接，数据端D与长短码信号WNP连接，输出端Q输出数字信号RD。
参照图16，其在图15的基础上进一步增加了用于预建立控制电压的电路，包括翻转检测器602、振荡器604(周期为Tosc)和数据选择器(MUX)608。振荡器604连接数据选择器608的第二输入端(MUX的0号端)，长短码信号WNP接入数据选择器608的第一输入端(MUX的1号端)和翻转检测器602的输入端，翻转检测器602的输出端连接数据选择器608的选择端Sel，并以数据选择器608的输出端替换图15中电路的WNP输入。
当不通信时，翻转检测器602输出低电平，数据选择器608将振荡器604的输出接入延迟锁定环(包括后侧延迟电路中间级1502、鉴频鉴相器、电荷泵、低通滤波器所形成的电路)，并建立电压信号Vctrl。
当通信时，翻转检测器602输出高电平，数据选择器608将长短码信号WNP接入延迟脉冲电路。
电路其他部分与图15中电路相似地，包括脉冲发生器One-shot、时钟触发器和数字信号触发器。其中，脉冲发生器One-shot的输入端连接长短码延迟信号WNPD，输出端连接时钟触发器的重置端S并输出延迟脉冲信号Set；时钟触发器的数据端D接地，时钟端连接长短码信号WNP，且通过输出端Q输出时钟信号RCLK；数字信号触发器的时钟端与时钟触发器的输出端Q连接，数据端D与长短码信号WNP连接，输出端Q输出数字信号RD。
同时，鉴频鉴相器通过两个输出端与电荷泵连接，以输出控制信号UP和DOWN。
由于在不通信时，延迟锁定环已建立了压控延迟线(包括延迟电路中间级1502)的电压信号Vctrl， 且该电压信号Vctrl与通信时最终的电压信号相近，因此，在长短码信号WNP到来时即可立即实现准确的通信，无需一般时钟数据恢复电路所需的建立时间，实现了快速建立通信。
本发明的技术内容及技术特征已揭示如上，然后熟悉本领域的技术人员仍可基于本发明的教导及揭示而作种种不背离本发明精神的替换及修饰，因此，本发明保护范围不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为本专利申请的权利要求所涵盖。

Claims (13)

  1. 一种单通道通信编码方法，其特征在于，包括：
    将时钟信号和数据信号合成一路长短码信号；
    所述长短码信号包括长码信号和短码信号，所述长码信号的脉宽与时钟信号一致，所述短码信号的脉宽与时钟信号一致；
    所述长码信号与所述短码信号的占空比不同。
  2. 根据权利要求1所述的单通道通信编码方法，其特征在于，所述长短码信号的占空比满足关系式：Tclk＝TS+TL，其中，Tclk为时钟周期，TS为短码信号的高电平时间，TL为长码信号的高电平时间，且TS不等于TL。
  3. 根据权利要求2所述单通道通信编码方法，其特征在于，将时钟信号和数据信号合成一路长短码信号包括：
    根据时钟信号产生第一延迟时钟信号；
    根据所述第一延迟时钟信号产生脉冲信号；
    根据所述脉冲信号生成长码信号的高电平和短码信号的高电平；
    根据所述第一延迟时钟信号产生第二延迟时钟信号；
    根据所述第二延迟时钟信号生成短码信号的低电平；
    根据时钟信号生成长码信号的低电平；
    根据所述第一延迟时钟信号和数据信号产生数据延迟信号；
    根据数据信号选择所述长码信号或所述短码信号并生成长短码信号。
  4. 根据权利要求3所述单通道通信编码方法，其特征在于，所述第一延迟时钟信号相对于时钟信号延迟时间为TS；所述第二延迟时钟信号相对于第一延迟时钟信号延迟时间为TS；所述数据延迟信号相对于数据信号延迟时间为TS。
  5. 根据权利要求2所述单通道通信编码方法，其特征在于，将时钟信号和数据信号合成一路长短码信号进一步包括：
    根据时钟信号产生第一脉冲信号；
    根据时钟信号产生第一延迟时钟信号；
    根据所述第一延迟时钟信号产生第二延迟时钟信号；
    根据所述第二延迟时钟信号产生第二脉冲信号；
    根据所述第一延迟时钟信号产生第三脉冲信号；
    根据所述第三脉冲信号生成长码信号的高电平或短码信号的高电平；
    根据所述数据信号和所述第一延迟时钟信号产生数据延迟信号；
    根据所述数据延迟信号选择第一脉冲信号或第二脉冲信号；
    根据被选择的第二脉冲信号生成短码信号的低电平；
    根据被选择的第一脉冲信号生成长码信号的低电平。
  6. 一种单通道通信编码电路，其特征在于，包括：
    第一延迟电路，用于根据时钟信号产生第一延迟时钟信号；
    脉冲发生器，用于根据所述第一延迟时钟信号产生脉冲信号；
    长码触发器，其重置端接收所述脉冲信号，并输出长码信号的高电平，其时钟端接收时钟信号，时钟信号触发输出长码信号的低电平；
    短码触发器，其重置端接收所述脉冲信号，输出短码信号的高电平；
    第二延迟电路，用于根据所述第一延迟时钟信号产生第二延迟时钟信号；
    所述短码触发器的时钟端接收所述第二延迟时钟信号，并输出短码信号的低电平；
    选择触发器，其时钟端接收第一延迟时钟信号，数据端连接数据信号，输出端输出数据延迟信号；
    数据选择器，其第一输入端连接所述长码触发器的输出端，第二输入端连接短码触发器的输出端；选择端连接所述选择触发器的输出端，所述数据选择器根据所述数据延迟信号选择输出所述长码信号或短码信号并形成长短码信号。
  7. 一种单通道通信编码电路，其特征在于，包括：
    第一延迟电路，用于根据时钟信号产生第一延迟时钟信号；
    第二延迟电路，用于根据第一延迟信号产生第二延迟时钟信号；
    第一脉冲发生器，用于根据第一延迟时钟信号产生第一脉冲信号；
    第二脉冲发生器，用于根据所述第二延迟时钟信号产生第二脉冲信号；
    第三脉冲发生器，用于所述第一延迟时钟信号产生第三脉冲信号；
    选择触发器，其时钟端接收第一延迟时钟信号，数据端连接数据信号，输出端输出数据延迟信号；
    数据选择器，其第一输入端连接所述第一脉冲发生器，第二输入端连接所述第二脉冲发生器；所述数据选择器的选择端连接数据延迟信号，并根据所述数据延迟信号选择第一脉冲信号或第二脉冲信号；
    输出触发器，其重置端与所述第三脉冲发生器连接，时钟端与所述数据选择器的输出端连接；所述输出触发器根据所述第三脉冲信号产生长码信号的高电平或短码信号的高电平，所述时钟端收到所述第一脉冲信号并产生长码信号的低电平；所述时钟端收到所述第二脉冲信号并产生短码信号的低电平。
  8. 一种单通道通信解码方法，其特征在于，包括：
    根据长短码信号的高电平产生时钟信号的低电平；
    根据长短码信号产生延迟脉冲信号，所述延迟脉冲信号的延迟时间为半个时钟周期；
    根据所述延迟脉冲信号产生时钟信号的高电平；
    根据所述时钟信号和长短码信号产生数字信号。
  9. 根据权利要求8所述的单通道通信解码方法，其特征在于：
    所述根据长短码信号产生延迟脉冲信号进一步包括：根据所述长短码信号产生长短码延迟信号，根据所述长短码延迟信号和长短码信号的相位差控制所述长短码信号的延迟时间。
  10. 根据权利要求9所述的单通道通信解码方法，其特征在于：
    根据长短码延迟信号和长短码信号的相位差控制所述长短码信号的延迟时间进一步包括：将所述相位差的信号转换为电压信号，根据所述电压信号控制长短码延迟信号的延迟时间。
  11. 一种单通道通信解码电路，其特征在于，包括：
    延迟脉冲电路，用于将长短码信号延迟半个时钟周期并产生长短码延迟信号；
    脉冲发生器，用于根据所述长短码延迟信号产生延迟脉冲信号；
    时钟触发器，其时钟端与长短码信号连接并根据长短码信号产生时钟信号的低电平，重置端与所述脉冲发生器的输出端连接，所述时钟触发器根据所述延迟脉冲信号产生时钟信号的高电平；
    数字信号触发器，其时钟端与所述时钟触发器的输出端连接，数据端与所述长短码信号连接，所述数字信号触发器根据时钟信号生成数字高电平或数字低电平。
  12. 根据权利要求11所述的单通道通信解码电路，其特征在于：
    所述延迟脉冲电路包括延迟电路和脉冲电路，所述延迟电路包括：
    延迟电路中间级，用于将所述长短码信号转换为长短码延迟信号；
    鉴频鉴相器，用于检测长短码延迟信号和长短码信号之间的相位差；
    电荷泵，用于将所述相位差转换为电流信号；
    低通滤波器，用于将所述电流信号转换为电压信号；
    其中，所述延迟电路中间级与所述低通滤波器连接，且所述延迟电路中间级用于接收所述电压信号并控制长短码延迟信号的延迟时间。
  13. 根据权利要求11或12所述的单通道通信解码电路，其特征在于，所述解码电路进一步包括翻转检测器、振荡器和数据选择器；
    当不通信时，所述翻转检测器输出低电平，所述数据选择器将所述振荡器的输出接入延迟锁定环，并建立电压信号；
    当通信时，所述翻转检测器输出高电平，所述数据选择器将所述长短码信号接入所述延迟脉冲电路。
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