WO2023065542A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023065542A1
WO2023065542A1 PCT/CN2022/070590 CN2022070590W WO2023065542A1 WO 2023065542 A1 WO2023065542 A1 WO 2023065542A1 CN 2022070590 W CN2022070590 W CN 2022070590W WO 2023065542 A1 WO2023065542 A1 WO 2023065542A1
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Prior art keywords
layer
word line
substrate
conductive layer
channel
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PCT/CN2022/070590
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English (en)
French (fr)
Inventor
郭帅
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to KR1020237018619A priority Critical patent/KR102730091B1/ko
Priority to JP2023534229A priority patent/JP7595171B2/ja
Priority to EP22865907.4A priority patent/EP4199085B1/en
Priority to US17/807,747 priority patent/US11508731B1/en
Publication of WO2023065542A1 publication Critical patent/WO2023065542A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials

Definitions

  • a semiconductor structure may include a memory cell, which typically includes a transistor, and a capacitor electrically coupled to the transistor.
  • the capacitor stores data information, and the transistor controls reading and writing of the data information in the capacitor.
  • the gate of the transistor is electrically connected with the word line (Word Line, referred to as WL), and the opening and closing of the transistor is controlled by the voltage on the word line; one of the source and the drain of the transistor is connected with the bit line (Bit Line, referred to as WL).
  • BL bit line
  • the other of the source and the drain is electrically connected to the capacitor, and the data information is stored or output through the bit line.
  • a full-surround gate transistor includes a first conductive layer, a channel region, and a second conductive layer stacked in sequence, one of the first conductive layer and the second conductive layer is a source, and the other is a drain , the side surface of the channel region is surrounded by a dielectric layer, and the gate is arranged on the dielectric layer.
  • the contact resistance between the above-mentioned transistor and other structures is relatively large, the current required by the transistor is relatively large, and the performance of the semiconductor structure is poor.
  • embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are used to improve the performance of the semiconductor structure.
  • the first aspect of the embodiments of the present application provides a method for fabricating a semiconductor structure, which includes: providing a substrate; A first conductive layer, an insulating layer and a second conductive layer, at least one of the first conductive layer and the second conductive layer is a semi-metal layer; forming a channel layer covering the stacked structure, and covering the The dielectric layer of the channel layer; forming a word line extending along a first direction, the word line includes a plurality of contact portions and connecting portions connecting adjacent contact portions, the contact portions surround and contact the dielectric A side surface of the layer, the contact portion is opposite to at least part of the insulating layer.
  • the first conductive layer, the insulating layer, the second conductive layer, the channel layer, the dielectric layer and the contact part form a vertical transistor
  • the length of the channel layer can be increased by adjusting the height of the stacked structure, so as to improve the short channel of the transistor. effect to improve the performance of semiconductor structures.
  • the second aspect of the embodiments of the present application provides a semiconductor structure, which includes: a stacked structure, a channel layer covering the side surface of the stacked structure, a dielectric layer covering the side surface of the channel layer, and a ring A gate provided on the dielectric layer;
  • the stacked structure includes a first conductive layer, an insulating layer and a second conductive layer stacked in sequence, one of the first conductive layer and the second conductive layer is a source, the other of the first conductive layer and the second conductive layer is a drain, and at least one of the source and the drain is a half-metal layer.
  • the first conductive layer, the insulating layer and the second conductive layer are stacked in sequence to form a laminated structure, one of the first conductive layer and the second conductive layer is a source, and the other is a drain , at least one of the first conductive layer and the second conductive layer is a semi-metal layer, which can reduce the contact resistance between the stacked structure and other structures on the one hand, and can also reduce the contact resistance of the first conductive layer and/or the second conductive layer on the other hand. contact resistance with the channel layer, thereby improving the performance of the semiconductor structure.
  • the side surface of the stacked structure is covered with a channel layer
  • the side surface of the channel layer is covered with a dielectric layer
  • the dielectric layer is surrounded by a gate
  • the stacked structure, channel layer, dielectric layer and gate form a vertical transistor , the length of the channel layer can be increased by adjusting the height of the stacked structure, so as to improve the short channel effect of the transistor and improve the performance of the semiconductor structure.
  • Fig. 1 is the flowchart of the manufacturing method of the semiconductor structure in the embodiment of the present application.
  • FIG. 2 is a schematic diagram of a first cross-section after forming a second conductive layer in an embodiment of the present application
  • FIG. 3 is a schematic diagram of a second cross-section after forming a second conductive layer in an embodiment of the present application
  • FIG. 4 is a schematic diagram of a first cross-section after forming a stacked structure in an embodiment of the present application
  • FIG. 5 is a schematic diagram of a second cross-section after forming a stacked structure in an embodiment of the present application
  • FIG. 7 is a schematic diagram of a second cross-section after forming a channel layer in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a first cross-section after forming a dielectric layer in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a second cross-section after forming a dielectric layer in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a first cross-section after word lines are formed in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a second cross-section after word lines are formed in the embodiment of the present application
  • Fig. 12 is a schematic diagram of the first section after forming the first initial support layer in the embodiment of the present application.
  • Fig. 13 is a schematic diagram of the second section after forming the first initial support layer in the embodiment of the present application.
  • Fig. 14 is a schematic diagram of the first cross-section after forming the first support layer in the embodiment of the present application.
  • FIG. 15 is a schematic diagram of a second cross-section after forming a first support layer in an embodiment of the present application.
  • 16 is a schematic diagram of a first cross-section after forming an initial word line layer in an embodiment of the present application
  • 17 is a schematic diagram of a second cross-section after forming an initial word line layer in an embodiment of the present application.
  • FIG. 18 is a schematic diagram of the first cross-section after forming the first photoresist layer in the embodiment of the present application.
  • FIG. 19 is a schematic diagram of a second cross-section after forming a first photoresist layer in an embodiment of the present application.
  • FIG. 20 is a schematic diagram of the first cross-section after etching the mask layer in the embodiment of the present application.
  • FIG. 21 is a schematic diagram of the second cross section after etching the mask layer in the embodiment of the present application.
  • FIG. 22 is a schematic diagram of a first cross-section after forming an intermediate word line layer in an embodiment of the present application
  • FIG. 23 is a schematic diagram of a second cross-section after forming an intermediate word line layer in an embodiment of the present application.
  • 24 is a schematic diagram of the first cross-section after forming the second photoresist layer in the embodiment of the present application.
  • 25 is a schematic diagram of a second cross-section after forming a second photoresist layer in an embodiment of the present application.
  • FIG. 26 is a schematic diagram of a first cross-section after forming a contact hole in an embodiment of the present application.
  • FIG. 27 is a schematic diagram of a second cross-section after forming a contact hole in an embodiment of the present application.
  • 29 is a schematic diagram of a second cross-section after removing the second photoresist layer in the embodiment of the present application.
  • FIG. 30 is another schematic diagram of the first cross-section after the contact hole is formed in the embodiment of the present application.
  • FIG. 31 is another schematic diagram of the second cross-section after the formation of the contact hole in the embodiment of the present application.
  • FIG. 32 is a schematic diagram of the first cross-section after forming the third conductive layer in the embodiment of the present application.
  • FIG. 33 is a schematic diagram of the second cross-section after forming the third conductive layer in the embodiment of the present application.
  • a vertical transistor is formed, and at least one of the source and the drain in the vertical transistor is a half-metal layer, so as to reduce the contact between the vertical transistor and other The contact resistance of the structure, as well as the contact resistance inside the vertical transistor, thereby improving the performance of the semiconductor structure.
  • an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method includes the following steps:
  • Step S101 providing a substrate.
  • the substrate 10 can be a semiconductor body substrate.
  • the substrate 10 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon on insulator (Silicon on Insulator, referred to as SOI) substrate or germanium on insulator (Germanium on Insulator, referred to as GOI) substrate.
  • SOI silicon on Insulator
  • GOI germanium on Insulator
  • the substrate 10 may be doped or non-doped, for example, the substrate 10 may be an N-type substrate or a P-type substrate.
  • the first section shown in FIG. 2 is a plane perpendicular to the second direction
  • the second section shown in FIG. 3 is a plane parallel to the second direction.
  • a plurality of bit lines 11 may also be disposed in the substrate 10 , and the plurality of bit lines 11 are spaced apart from each other and extend along the second direction. As shown in FIG. 3, a plurality of bit lines 11 extend in the horizontal direction (X direction shown in FIG. 3).
  • the bit lines 11 may be exposed on the surface of the substrate 10 , as shown in FIGS. 2 and 3 , the bit lines 11 are exposed on the upper surface of the substrate 10 so as to be electrically connected to other structures on the substrate 10 .
  • a shallow trench isolation structure 12 (Shallow Trench Isolation, STI for short) is also disposed in the substrate 10 .
  • the shallow trench isolation structure 12 is disposed between adjacent bit lines 11 to isolate the bit lines 11 .
  • the filling material in the shallow trench isolation structure 12 may be an insulating material such as silicon nitride or silicon oxide.
  • Step S102 forming a plurality of stacked structures arranged at intervals on the substrate, the stacked structure includes a first conductive layer, an insulating layer and a second conductive layer stacked in sequence, and at least one of the first conductive layer and the second conductive layer One is a semi-metal layer.
  • the laminated structure 20 includes a first conductive layer 21 , an insulating layer 22 and a second conductive layer 23 .
  • One of the first conductive layer 21 and the second conductive layer 23 is electrically connected to the capacitor, and the other of the first conductive layer 21 and the second conductive layer 23 is electrically connected to the bit line 11 (Bit Line, BL for short).
  • the first conductive layer 21, the insulating layer 22 and the second conductive layer 23 are sequentially stacked along the vertical direction (Z direction shown in FIG. 5), the first conductive layer 21 is electrically connected to the bit line 11, and the second conductive layer 23 is electrically connected with the capacitor.
  • the insulating layer 22 may be an oxide layer, for example, the material of the insulating layer 22 may be silicon oxide.
  • At least one of the first conductive layer 21 and the second conductive layer 23 is a half-metal layer.
  • the first conductive layer 21 is a half-metal layer
  • the second conductive layer 23 is also a half-metal layer.
  • the material of the semi-metal layer may be bismuth.
  • the laminated structure 20 may be columnar, such as a cylinder, an elliptical column, a square column or a rectangular column, and the laminated structure 20 may be arranged in an array.
  • a plurality of stacked structures 20 arranged at intervals are formed on the substrate 10, and the stacked structure 20 includes a first conductive layer 21, an insulating layer 22, and a second stacked layer arranged in sequence.
  • Two conductive layers 23, at least one of the first conductive layer 21 and the second conductive layer 23 is a semi-metal layer and may include:
  • a first conductive layer 21 , an insulating layer 22 and a second conductive layer 23 which are stacked are deposited on the substrate 10 .
  • a first conductive layer 21 is deposited on the substrate 10
  • an insulating layer 22 is deposited on the first conductive layer 21
  • a second conductive layer 23 is deposited on the insulating layer 22 .
  • the deposition can be chemical vapor deposition (Chemical Vapor Deposition, CVD for short), physical vapor deposition (Physical Vapor Deposition, PVD for short) or atomic layer deposition (Atomic Layer Deposition, ALD for short).
  • the first conductive layer 21 , the insulating layer 22 and the second conductive layer 23 are then etched to form a plurality of stacked structures 20 arranged at intervals. As shown in FIG. 4 and FIG. 5, dry etching or wet etching removes part of the first conductive layer 21, insulating layer 22 and second conductive layer 23, so that the remaining first conductive layer 21, insulating layer 22 and The second conductive layer 23 is separated to form a plurality of stacked structures 20 spaced apart from each other.
  • Step S103 forming a channel layer covering the stacked structure and a dielectric layer covering the channel layer.
  • the channel layer 30 covers the stacked structure 20
  • the dielectric layer 40 covers the channel layer 30 .
  • the channel layer 30 covers the side surfaces and the top surface of the stacked structure 20
  • the dielectric layer 40 covers the side surfaces and the top surface of the channel layer 30 .
  • the top surface refers to the surface away from the substrate 10 . 6 and 7, the channel layer 30 covers the outer peripheral surface of the first conductive layer 21, the outer peripheral surface of the insulating layer 22, and the outer peripheral surface of the second conductive layer 23, and the channel layer 30 also covers the second The top surface 24 of the conductive layer.
  • the channel region is layered, and the material of the channel layer 30 may include molybdenum sulfide, such as molybdenum disulfide, and the material of the channel layer 30 may also be transition metal dichalcogenides (TMDs).
  • TMDs transition metal dichalcogenides
  • the layered molybdenum sulfide has a high specific surface area, which is beneficial to overcome the short channel effect.
  • the on-off ratio refers to the ratio of the on-state current to the off-state current of the device. Specifically, in a transistor, when the source and drain voltages are constant, the ratio between the source and drain currents measured when the gate voltage is applied and when the gate voltage is not applied is The ratio is the switch ratio.
  • the material of the channel layer 30 is molybdenum sulfide, and the material of the semi-metal layer is bismuth.
  • the material of the channel layer 30 is molybdenum sulfide, and the materials of the first conductive layer 21 and the second conductive layer 23 are both bismuth. In this way, the energy barrier at the interface between the molybdenum sulfide and bismuth is reduced, and the channel layer 30 can be reduced. and the gap state (MIGS) between the first conductive layer 21, the channel layer 30 and the second conductive layer 23, thereby reducing the gap between the channel layer 30 and the first conductive layer 21, the channel layer 30 and the second conductive layer 23 contact resistance between them.
  • MIGS gap state
  • forming the channel layer 30 covering the laminated structure 20, and the dielectric layer 40 covering the channel layer 30 may include:
  • a channel layer 30 is deposited on the stacked structure 20 and the substrate 10 , and the channel layer 30 covers the top surface and side surfaces of the stacked structure 20 and the top surface of the substrate 10 .
  • the channel layer 30 is formed through a deposition process, and the channel layer 30 covers the top surface, the side surfaces of the stacked structure 20 , and the top surface of the substrate 10 .
  • a dielectric layer 40 is then deposited on the channel layer 30 .
  • a dielectric layer 40 is formed through a deposition process, and the dielectric layer 40 covers the entire surface of the channel layer 30 .
  • Step S104 forming a word line extending along the first direction, the word line includes a plurality of contact portions and connecting portions connecting adjacent contact portions, the contact portions surround and contact the side surface of the dielectric layer, and the contact portions are in contact with at least part of the insulating layer correspond.
  • word lines 63 are formed between the stacked structure 20 after the channel layer 30 and the dielectric layer 40 are formed. direction (Y direction shown in FIG. 10 ). As shown in FIGS. 10 and 11 , the word line 63 includes a plurality of contact portions 64 and connecting portions 65 connecting adjacent contact portions 64 , wherein the contact portions 64 surround and contact the side surface of the dielectric layer 40 .
  • the contact portion 64 corresponds to at least part of the insulating layer 22 , and the contact portion 64 is used as the gate of the transistor, that is, a part of the word line 63 is the gate.
  • the orthographic projection of the insulating layer 22 in this direction and the orthographic projection of the contact portion 64 in this direction at least partially coincide, for example, the top of the contact portion 64
  • the surface is lower than the top surface of the insulating layer 22 , and the bottom surface of the contact portion 64 is higher than the bottom surface of the insulating layer 22 .
  • the first conductive layer 21, the insulating layer 22 and the second conductive layer 23 are sequentially stacked to form a laminated structure 20, and at least one of the first conductive layer 21 and the second conductive layer 23 is half
  • the metal layer on the one hand, can reduce the contact resistance between the laminated structure 20 and other structures, and on the other hand, can also reduce the contact resistance between the first conductive layer 21 and/or the second conductive layer 23 and the channel layer 30, thereby improving Properties of semiconductor structures.
  • the first conductive layer 21, the insulating layer 22, the second conductive layer 23, the channel layer 30, the dielectric layer 40 and the contact portion 64 form a vertical transistor, and the length of the channel layer 30 can be increased by adjusting the height of the stacked structure 20 , it is convenient to improve the short channel effect of the transistor and improve the performance of the semiconductor structure.
  • a word line 63 extending along a first direction is formed, and the word line 63 includes a plurality of contact portions 64 and connecting portions 65 connecting adjacent contact portions 64 , the contact portion 64 surrounds and contacts the side surface of the dielectric layer 40, and before the step of the contact portion 64 facing at least part of the insulating layer 22, it also includes: filling between the stacked structure 20 covered with the channel layer 30 and the dielectric layer 40
  • the first supporting layer 50 , the surface of the first supporting layer 50 facing away from the substrate 10 is higher than the surface of the first conductive layer 21 facing away from the substrate 10 , and lower than the surface of the insulating layer 22 facing away from the substrate 10 .
  • the first support layer 50 can be used as a pad layer to increase the distance between the subsequently formed word line 63 and the substrate 10 , so that the bottom surface of the word line 63 is higher than the top of the first conductive layer 21
  • the surface, that is, the surface of the word line 63 facing the substrate 10 is higher than the surface of the first conductive layer 21 facing away from the substrate 10 .
  • the surface of the first support layer 50 facing away from the substrate 10 is lower than the surface of the insulating layer 22 facing away from the substrate 10, so that the bottom surface of the word line 63 is lower than the top surface of the first conductive layer 21, thereby ensuring that the word line 63 is in contact with the insulating layer. 22 relative.
  • the material of the first support layer 50 can be silicon nitride or silicon oxynitride, and the first support layer 50 has a larger selectivity ratio to the dielectric layer 40, for example, the selectivity ratio of the first support layer 50 to the dielectric layer 40 is greater than 5, to avoid damage to the dielectric layer 40 when etching the first supporting layer 50, thereby reducing damage to the gate oxide layer of the transistor.
  • a first support layer 50 is filled between the stacked structure 20 covered with the channel layer 30 and the dielectric layer 40 , and the first support layer 50 is away from the substrate.
  • the surface of the bottom 10 is higher than the surface of the first conductive layer 21 facing away from the substrate 10, and lower than the surface of the insulating layer 22 facing away from the substrate 10 may include the following processes:
  • a first initial support layer 51 is formed on the dielectric layer 40, the first initial support layer 51 is filled between the laminated structure 20 covered with the channel layer 30 and the dielectric layer 40, and the first initial support layer 51 covers the dielectric layer 40 of the top surface.
  • a first initial support layer 51 is formed by deposition, and the first initial support layer 51 is filled between the laminated structures 20 covered with the channel layer 30 and the dielectric layer 40.
  • the first initial support layer 51 The top surface of the dielectric layer 40 is also covered. Specifically, the upper surface of the first initial support layer 51 is higher than the upper surface of the dielectric layer 40 .
  • first initial support layer 51 After the first initial support layer 51 is formed, part of the first initial support layer 51 is removed, and the remaining first initial support layer 51 forms the first support layer 50 . As shown in FIG. 14 and FIG. 15 , along the direction perpendicular to the substrate 10, dry etching or wet etching removes part of the first initial support layer 51, leaving the stack covered with the channel layer 30 and the dielectric layer 40. Part of the first initial support layer 51 between the layer structures 20 and the remaining first initial support layer 51 form the first support layer 50 .
  • the contact portion 64 and the connecting portion 65 connecting adjacent contact portions 64, the contact portion 64 surrounds and contacts the side surface of the dielectric layer 40, and the contact portion 64 is opposite to at least part of the insulating layer 22 may include the following steps:
  • Step S1041 forming an initial word line layer covering the first supporting layer and the dielectric layer.
  • an initial word line layer 61 is formed through a deposition process, and the initial word line layer 61 covers the first supporting layer 50 and the dielectric layer 40 .
  • the initial word line layer 61 covers the top surface of the first supporting layer 50 and covers the side surface and the top surface of the dielectric layer 40 .
  • Step S1042 removing part of the initial word line layer on the first supporting layer along the first direction, so that the initial word line layer forms a plurality of intermediate word line layers arranged at intervals.
  • part of the initial word line layer 61 located on the first support layer 50 is removed, so that the initial word line layer 61 forms a plurality of intermediate word line layers 62 arranged at intervals, and each intermediate word line layer 62 is along the Extending in the first direction, that is, part of the initial word line layer 61 on the first supporting layer 50 is removed along the first direction, and the remaining initial word line layer 61 forms an intermediate word line layer 62 .
  • part of the initial word line layer 61 located on the first support layer 50 is removed along the first direction, so that the initial word line layer 61 forms a plurality of intermediate word line layers 62 arranged at intervals.
  • a mask layer 71 covering the initial word line layer 61 is formed, the mask layer 71 is filled between the stacked structure 20 covered with the channel layer 30, the dielectric layer 40 and the initial word line layer 61, and the mask layer 71 covers the initial The top surface of the word line layer 61 .
  • a mask layer 71 is deposited on the initial word line layer 61, and the mask layer 71 is filled between the stacked structure 20 of the channel layer 30, the dielectric layer 40 and the initial word line layer 61, The mask layer 71 also covers the top surface of the initial word line layer 61 .
  • the top surface of the mask layer 71 is higher than the top surface of the initial word line layer 61 .
  • a first photoresist layer 72 is formed on the mask layer 71, the first photoresist layer 72 has a groove 73 extending along the first direction, and the front surface of the groove 73 on the substrate 10 is The projection does not overlap with the orthographic projection of the initial word line layer 61 on the side surface of the stacked structure 20 on the substrate 10 .
  • the mask layer 71 is etched using the first photoresist layer 72 as a mask.
  • the pattern on the first photoresist layer 72 is transferred to the mask layer 71, as shown in Figure 20 and Figure 21, the mask layer 71 is formed
  • the initial word line layer 61 is exposed in the pattern.
  • the initial word line layer 61 is etched using the etched mask layer 71 as a mask to form the middle word line layer 62 .
  • Anisotropic etching is used to remove part of the initial word line layer 61 on the first support layer 50 , as shown in FIG. 22 and FIG. 23 , the remaining initial word line layer 61 forms an intermediate word line layer 62 . Gaps between the plurality of middle word line layers 62 expose the first supporting layer 50 .
  • Step S1043 removing the middle word line layer on the top surface of the dielectric layer, and part of the middle word line layer on the side surface of the dielectric layer away from the substrate, and the remaining middle word line layer forms a word line.
  • the middle word line layer 62 on the top surface of the dielectric layer 40 and the upper part of the middle word line layer 62 on the side surface of the dielectric layer 40 are removed by etching, and the remaining middle word line layer 62 forms the word line 63 .
  • the top surface of the word line 63 is lower than the top surface of the insulating layer 22 , and the word line 63 is opposite to the insulating layer 22 .
  • a word line 63 extending along the first direction is formed, and the word line 63 includes a plurality of contact portions 64 and a connection portion 65 connecting adjacent contact portions 64, the contact portion 64 and the stack
  • the manufacturing method of the semiconductor structure further includes:
  • a second support layer 81 covering the word lines 63 , the first support layer 50 , and the dielectric layer 40 is formed. As shown in Figure 24 and Figure 25, deposit the second supporting layer 81, the second supporting layer 81 covers the word line 63, the first supporting layer 50 and the dielectric layer 40, the top surface of the second supporting layer 81 is higher than the dielectric layer 40 top surface. The surface of the second support layer 81 facing away from the substrate 10 can be flush. Exemplarily, the second support layer 81 is planarized, such as chemical mechanical polishing (CMP for short), so that the surface of the second support layer 81 The top surface is flush.
  • CMP chemical mechanical polishing
  • the material of the second support layer 81 can be the same as the material of the first support layer 50, both are insulating materials, so that the second support layer 81 and the first support layer 50 are integrated, and the second support layer 81 and the first support layer 50 Each word line 63 is covered and isolated to insulate each word line 63 .
  • a second photoresist layer 82 is formed on the second support layer 81 , the second photoresist layer 82 has a plurality of openings 83 , and the openings 83 are opposite to the stacked structure 20 .
  • a second photoresist layer 82 is formed on the second supporting layer 81, the second photoresist layer 82 has a plurality of openings 83, and the plurality of openings 83 and the plurality of stacked structures 20 are respectively Correspondingly, and the opening 83 is opposite to the corresponding stacked structure 20 .
  • each opening 83 on the substrate 10 is located within the orthographic projection of its corresponding stacked structure 20 on the substrate 10, or, the orthographic projection of each opening 83 on the substrate 10 and its corresponding stacked structure 20 The orthographic projections on the substrate 10 are superimposed.
  • the second photoresist layer 82 After forming the second photoresist layer 82, use the second photoresist layer 82 as a mask to etch the second supporting layer 81, the dielectric layer 40 and the channel layer 30 to form a contact hole 84, which exposes the second Conductive layer 23. As shown in FIG. 26 and FIG. 27 , the contact hole 84 penetrates through the second support layer 81 , the dielectric layer 40 and the channel layer 30 to expose the second conductive layer 23 . While forming the contact hole 84, the second photoresist layer 82 is also removed, or, after the contact hole 84 is formed, the second photoresist layer 82 is removed. As shown in FIGS. 28 and 29 , after removing the second photoresist layer 82 , the top surface of the second supporting layer 81 is exposed.
  • the area of the opening 83 of the contact hole 84 is larger than the area of the bottom of the contact hole 84 , that is, the upper part of the contact hole 84 has a larger width and the lower part has a smaller width.
  • the width of the upper part of the third conductive layer 90 is larger, and the width of the operation window is increased to facilitate alignment with the capacitor.
  • the width of the lower portion of the third conductive layer 90 is smaller, which can reduce the critical dimension of the transistor.
  • the cross-sectional shape of the contact hole 84 may be an inverted trapezoid with a large top and a small bottom.
  • the cross-sectional shape of the contact hole 84 can also be a connected rectangle and trapezoid, the rectangle is set on the side of the trapezoid close to the substrate 10, and the bottom of the rectangle coincides with the upper bottom of the trapezoid.
  • a third conductive layer 90 is formed in the contact hole 84, and the third conductive layer 90 is electrically connected to the second conductive layer.
  • a third conductive layer 90 is deposited in the contact hole 84 , and the third conductive layer 90 is in contact with the second conductive layer 23 to realize electrical connection between the third conductive layer 90 and the second conductive layer 23 .
  • the third conductive layer 90 may be a capacitor contact pad, and a capacitor is formed on the third conductive layer 90 .
  • the embodiment of the present application further provides a semiconductor structure, which includes: a stacked structure 20 , a channel layer 30 , a dielectric layer 40 and a gate.
  • the stacked structure 20 is disposed on a substrate 10, and the substrate 10 is used to support the stacked structure 20, and the substrate 10 may be a semiconductor substrate, such as a silicon substrate.
  • a plurality of bit lines 11 may also be arranged in the substrate 10 , the plurality of bit lines 11 are spaced apart from each other, and the plurality of bit lines 11 extend along the second direction (direction X shown in FIG. 11 ).
  • the bit lines 11 may be exposed on the surface of the substrate 10 so as to be electrically connected to other structures on the substrate 10 .
  • a shallow trench isolation structure 12 may also be provided between adjacent bit lines 11 , and the bit lines 11 are isolated by the shallow trench isolation structure 12 .
  • a plurality of stacked structures 20 are disposed on the substrate 10 , and each stacked structure 20 is arranged at intervals.
  • the stacked structure 20 includes a first conductive layer 21 , an insulating layer 22 and a second conductive layer 23 which are stacked. As shown in FIG. 10 and FIG. 11 , along the direction away from the substrate 10 , the first conductive layer 21 , the insulating layer 22 and the second conductive layer 23 are arranged in sequence.
  • One of the first conductive layer 21 and the second conductive layer 23 is a source
  • the other of the first conductive layer 21 and the second conductive layer 23 is a drain
  • at least one of the source and the drain is a half-metal layer
  • the material of the semi-metal layer may be bismuth
  • the material of the insulating layer 22 may be silicon oxide.
  • the laminated structure 20 may be columnar, such as cylinder, elliptical column, square column or rectangular column, and the laminated structure 20 may be arranged in an array.
  • the side surface of the stacked structure 20 is covered with a channel layer 30, and a channel region is formed around the channel layer 30 on the side surface of the stacked structure 20 to provide a conductive channel between the source and the drain, so that the current carrying Electrons can move from source to drain or from drain to source.
  • the channel region is layered, and the material of the channel layer 30 may include molybdenum sulfide, such as molybdenum disulfide. There is a band gap in the layered molybdenum sulfide, and the field effect transistor formed by it has a high switching ratio.
  • the channel layer 30 is made of molybdenum sulfide, and the source and drain are made of bismuth, so as to reduce the gap state and energy barrier between the channel layer 30 and the source, and between the channel layer 30 and the drain, Thereby reducing the contact resistance between the channel layer 30 and the source, and between the channel layer 30 and the drain.
  • the side surface of the channel layer 30 is covered with a dielectric layer 40, which may be an oxide layer, and the dielectric layer 40 located on the side surface of the channel layer 30 forms a gate oxide layer.
  • a dielectric layer 40 which may be an oxide layer
  • the dielectric layer 40 located on the side surface of the channel layer 30 forms a gate oxide layer.
  • the material of the dielectric layer 40 is silicon oxide.
  • the dielectric layer 40 is surrounded by a gate, and the gate surrounds the side surface of the dielectric layer 40 and is in contact with the side surface of the dielectric layer 40 .
  • the gate is opposite to at least part of the insulating layer 22, and along a direction perpendicular to the substrate 10 (direction Z shown in FIG. 10 ), the orthographic projection of the dielectric layer 40 in this direction and the orthographic projection of the gate in this direction at least partially overlap.
  • the top surface of the gate is lower than the top surface of the dielectric layer 40
  • the bottom surface of the gate is higher than the bottom surface of the dielectric layer 40 .
  • the semiconductor structure in the embodiment of the present application further includes a word line 63, and the word line 63 extends along the first direction.
  • the word line 63 includes a contact portion 64 and a connection portion 65 connecting two adjacent contact portions 64, wherein the contact portion 64 is The gate ring disposed on the dielectric layer 40, that is, a part of the word line 63 is the gate. It can be understood that, along the first direction, the connecting portion 65 is spaced apart from the gates, and the connecting portion 65 connects a plurality of gates in the first direction to form a word line 63 .
  • the word line 63 is disposed on the first support layer 50, the first support layer 50 is located below the word line 63, and is filled with the dielectric layer 40 and the channel layer. 30 between the stacked structures 20 to pad the word lines 63 .
  • the word line 63 may also be covered with a second supporting layer 81 , and the second supporting layer 81 and the first supporting layer 50 electrically isolate the word line 63 .
  • the material of the second supporting layer 81 may be the same as that of the first supporting layer 50 , so that the second supporting layer 81 and the first supporting layer 50 are integrated.
  • the second support layer 81 also covers the dielectric layer 40, the second support layer 81 has a contact hole, the contact hole penetrates the dielectric layer 40 and the channel layer 30, to expose the second conductive layer of the laminated structure 20.
  • the third conductive layer 90 is filled in the contact hole, and one end of the third conductive layer 90 is in contact with the second conductive layer 23, so as to realize the electrical connection between the third conductive layer 90 and the second conductive layer 23, and the other end of the third conductive layer 90 Capacitors can be connected.
  • the first conductive layer 21, the insulating layer 22 and the second conductive layer 23 are stacked in sequence to form a laminated structure 20, and one of the first conductive layer 21 and the second conductive layer 23 is a source , the other is the drain, and at least one of the first conductive layer 21 and the second conductive layer 23 is a semi-metal layer, which can reduce the contact resistance between the laminated structure 20 and other structures on the one hand, and can also reduce the first The contact resistance between the conductive layer 21 and/or the second conductive layer 23 and the channel layer 30 is improved, thereby improving the performance of the semiconductor structure.
  • the side surface of the stacked structure 20 is covered with a channel layer 30, and the side surface of the channel layer 30 is covered with a dielectric layer 40, and a gate is arranged on the dielectric layer 40.
  • the stacked structure 20, the channel layer 30, the dielectric layer The layer 40 and the gate form a vertical transistor, and the length of the channel layer 30 can be increased by adjusting the height of the stacked structure 20, so as to improve the short channel effect of the transistor and improve the performance of the semiconductor structure.

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Abstract

一种半导体结构及其制作方法，涉及半导体技术领域，用于解决半导体结构的性能较差的技术问题，该半导体结构的制作方法包括：提供衬底（10）；在衬底（10）上形成多个间隔设置的叠层结构（20），叠层结构（20）包括依次层叠设置的第一导电层（21）、绝缘层（22）和第二导电层（23），第一导电层（21）和第二导电层（23）中的至少一个为半金属层；形成覆盖叠层结构（20）的沟道层（30），以及覆盖沟道层（30）的介质层（40）；形成沿第一方向延伸的字线（63），字线（63）包括多个接触部（64）和连接相邻的接触部（64）的连接部（65），接触部（64）环绕且接触介质层（40）的侧表面，接触部（64）与至少部分绝缘层（22）相对。

Description

半导体结构及其制作方法
本申请要求于2021年10月22日提交中国专利局、申请号为202111231509.3、申请名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
半导体结构可以包括存储单元，存储单元通常包括晶体管，以及和晶体管电连接的电容器。电容器存储数据信息，晶体管控制电容器中的数据信息的读写。其中，晶体管的栅极与字线(Word Line，简称WL)电连接，通过字线上的电压控制晶体管的开启和关闭；晶体管的源极和漏极中的一个与位线(Bit Line，简称BL)电连接，源极和漏极中的另一个与电容器电连接，通过位线对数据信息进行存储或者输出。
随着半导体结构尺寸的微缩，晶体管通常采用全环绕式栅极(Gate all Around，简称GAA)晶体管。相关技术中，全环绕式栅极晶体管包括依次层叠设置的第一导电层、沟道区和第二导电层，第一导电层和第二导电层中的一个为源极，另一个为漏极，沟道区的侧表面环绕有介质层，介质层上设置有栅极。然而，上述晶体管与其他结构(例如位线或者电容器)的接触电阻较大，晶体管所需电流较大，半导体结构性能较差。
发明内容
鉴于上述问题，本申请实施例提供一种半导体结构及其制作方法，用于提高半导体结构的性能。
本申请实施例的第一方面提供一种半导体结构的制作方法，其包括：提供衬底；在所述衬底上形成多个间隔设置的叠层结构，所述叠层结构包括依次层叠设置的第一导电层、绝缘层和第二导电层，所述第一导电层和 所述第二导电层中的至少一个为半金属层；形成覆盖所述叠层结构的沟道层，以及覆盖所述沟道层的介质层；形成沿第一方向延伸的字线，所述字线包括多个接触部和连接相邻的所述接触部的连接部，所述接触部环绕且接触所述介质层的侧表面，所述接触部与至少部分所述绝缘层相对。
本申请实施例提供的半导体结构的制作方法至少具有如下优点：
本申请实施例提供的半导体结构的制作方法，第一导电层、绝缘层和第二导电层依次层叠设置形成叠层结构，第一导电层和第二导电层中的至少一个为半金属层，一方面可以降低叠层结构与其他结构的接触电阻，另一方面还可以降低第一导电层和/或第二导电层与沟道层之间的接触电阻，从而提高半导体结构的性能。此外，第一导电层、绝缘层、第二导电层、沟道层、介质层和接触部形成垂直晶体管，可以通过调整叠层结构的高度增加沟道层的长度，便于改善晶体管的短沟道效应，提高半导体结构的性能。
本申请实施例的第二方面提供一种半导体结构，其包括：叠层结构、覆盖所述叠层结构的侧表面的沟道层、覆盖所述沟道层的侧表面的介质层，以及环设在所述介质层上的栅极；所述叠层结构包括依次层叠设置的第一导电层、绝缘层和第二导电层，所述第一导电层和所述第二导电层中的一个为源极，所述第一导电层和所述第二导电层中的另一个为漏极，所述源极和所述漏极中的至少一个为半金属层。
本申请实施例提供的半导体结构至少具有如下优点：
本申请实施例的半导体结构中，第一导电层、绝缘层和第二导电层依次层叠设置形成叠层结构，第一导电层和第二导电层中的一个为源极，另一个为漏极，第一导电层和第二导电层中的至少一个为半金属层，一方面可以降低叠层结构与其他结构的接触电阻，另一方面还可以降低第一导电层和/或第二导电层与沟道层之间的接触电阻，从而提高半导体结构的性能。此外，叠层结构的侧表面覆盖有沟道层，沟道层的侧表面覆盖有介质层，介质层上环设有栅极，叠层结构、沟道层、介质层和栅极形成垂直晶体管，可以通过调整叠层结构的高度增加沟道层的长度，便于改善晶体管的短沟道效应，提高半导体结构的性能。
附图说明
图1为本申请实施例中的半导体结构的制作方法的流程图；
图2为本申请实施例中的形成第二导电层后的第一截面的示意图；
图3为本申请实施例中的形成第二导电层后的第二截面的示意图；
图4为本申请实施例中的形成叠层结构后的第一截面的示意图；
图5为本申请实施例中的形成叠层结构后的第二截面的示意图；
图6为本申请实施例中的形成沟道层后的第一截面的示意图；
图7为本申请实施例中的形成沟道层后的第二截面的示意图；
图8为本申请实施例中的形成介质层后的第一截面的示意图；
图9为本申请实施例中的形成介质层后的第二截面的示意图；
图10为本申请实施例中的形成字线后的第一截面的示意图；
图11为本申请实施例中的形成字线后的第二截面的示意图
图12为本申请实施例中的形成第一初始支撑层后的第一截面的示意图；
图13为本申请实施例中的形成第一初始支撑层后的第二截面的示意图；
图14为本申请实施例中的形成第一支撑层后的第一截面的示意图；
图15为本申请实施例中的形成第一支撑层后的第二截面的示意图；
图16为本申请实施例中的形成初始字线层后的第一截面的示意图；
图17为本申请实施例中的形成初始字线层后的第二截面的示意图；
图18为本申请实施例中的形成第一光刻胶层后的第一截面的示意图；
图19为本申请实施例中的形成第一光刻胶层后的第二截面的示意图；
图20为本申请实施例中的刻蚀掩膜层后的第一截面的示意图；
图21为本申请实施例中的刻蚀掩膜层后的第二截面的示意图；
图22为本申请实施例中的形成中间字线层后的第一截面的示意图；
图23为本申请实施例中的形成中间字线层后的第二截面的示意图；
图24为本申请实施例中的形成第二光刻胶层后的第一截面的示意图；
图25为本申请实施例中的形成第二光刻胶层后的第二截面的示意图；
图26为本申请实施例中的形成接触孔后的第一截面的一种示意图；
图27为本申请实施例中的形成接触孔后的第二截面的一种示意图；
图28为本申请实施例中的去除第二光刻胶层后的第一截面的示意图；
图29为本申请实施例中的去除第二光刻胶层后的第二截面的示意图；
图30为本申请实施例中的形成接触孔后的第一截面的另一种示意图；
图31为本申请实施例中的形成接触孔后的第二截面的另一种示意图；
图32为本申请实施例中的形成第三导电层后的第一截面的示意图；
图33为本申请实施例中的形成第三导电层后的第二截面的示意图。
具体实施方式
为了提高半导体结构的性能，本申请实施例提供的半导体结构的制作方法中，通过形成垂直晶体管，且垂直晶体管中的源极和漏极中的至少一个为半金属层，以降低垂直晶体管与其他结构的接触电阻，以及垂直晶体管内部的接触电阻，从而提高半导体结构的性能。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参考图1，本申请实施例提供一种半导体结构的制作方法，该制作方法包括以下步骤：
步骤S101：提供衬底。
衬底10可以为半导体体衬底，示例性的，衬底10可以为硅衬底、锗衬底、硅锗衬底、氮化镓衬底、砷化镓衬底、绝缘体上硅(Silicon on Insulator，简称SOI)衬底或者绝缘体上锗(Germanium on Insulator，简称GOI)衬底等。其中，衬底10可以为掺杂或者非掺杂，例如，衬底10可以为N型衬底或者P型衬底。
在一些可能的示例中，参考图2和图3，图2所示的第一截面为垂直于第二方向的平面，图3所示的第二截面为平行于第二方向的平面。衬底10内还可以设置有多条位线11，多条位线11之间彼此间隔，且沿第二方向延伸。如图3所示，多条位线11沿水平方向(图3所示的X方向)延伸。位线11可以暴露于衬底10的表面，如图2和图3所示，位线11暴露于衬底10的上表面，以便于与位于衬底10上的其他结构电连接。
继续参考图2和图3，衬底10内还设置有浅槽隔离结构12(Shallow  Trench Isolation，简称STI)。浅槽隔离结构12设置在相邻的位线11之间，以将各位线11隔离。浅槽隔离结构12中的填充材料可以为氮化硅或者氧化硅等绝缘材料。
步骤S102：在衬底上形成多个间隔设置的叠层结构，叠层结构包括依次层叠设置的第一导电层、绝缘层和第二导电层，第一导电层和第二导电层中的至少一个为半金属层。
参考图4和图5，衬底10上形成多个叠层结构20，各叠层结构20间隔设置。叠层结构20包括第一导电层21、绝缘层22和第二导电层23。第一导电层21中和第二导电层23中的一个与电容电连接，第一导电层21和第二导电层23中的另一个与位线11(Bit Line，简称BL)电连接。例如，第一导电层21、绝缘层22和第二导电层23沿竖直方向(图5所示的Z方向)依次层叠设置，第一导电层21与位线11电连接，第二导电层23与电容器电连接。
其中，绝缘层22可以为氧化物层，示例性的，绝缘层22的材质可以为氧化硅。第一导电层21和第二导电层23中的至少一个为半金属层，示例性的，第一导电层21为半金属层，第二导电层23也为半金属层。其中，半金属层的材质可以为铋。通过将第一导电层21和/或第二导电层23设置为半金属层，可以减少叠层结构20与位线11和/或电容之间的接触电阻，从而提高半导体结构的性能。
继续参考图4和图5，沿第二方向(图5所示的X方向)，每条位线11上至少设置有一个叠层结构20，第一导电层21与位线11相接触，从而实现第一导电层21与位线11的电连接。叠层结构20可以为柱状，例如圆柱、椭圆柱、方柱或者长方柱，叠层结构20可以呈阵列排布。
参考图2至图5，在一些可能的示例中，在衬底10上形成多个间隔设置的叠层结构20，叠层结构20包括依次层叠设置的第一导电层21、绝缘层22和第二导电层23，第一导电层21和第二导电层23中的至少一个为半金属层可以包括：
在衬底10上沉积形成层叠设置的第一导电层21、绝缘层22和第二导电层23。如图2和图3所示，在衬底10上沉积第一导电层21，在第一导电层21上沉积绝缘层22，并在绝缘层22上沉积第二导电层23。其中，沉积可以为化学气相沉积(Chemical Vapor Deposition，简称CVD)、物理 气相沉积(Physical Vapor Deposition，简称PVD)或者原子层沉积(Atomic Layer Deposition，简称ALD)。
再刻蚀第一导电层21、绝缘层22和第二导电层23，形成多个间隔设置的叠层结构20。如图4和图5所示，干法刻蚀或者湿法刻蚀去除部分第一导电层21、绝缘层22和第二导电层23，以使剩余的第一导电层21、绝缘层22和第二导电层23分隔形成多个彼此间隔的叠层结构20。
步骤S103：形成覆盖叠层结构的沟道层，以及覆盖沟道层的介质层。
参考图6至图9，沟道层30覆盖叠层结构20，介质层40覆盖沟道层30。具体的，沟道层30覆盖叠层结构20的侧表面和顶表面，介质层40覆盖沟道层30的侧表面和顶表面。其中，顶表面是指背离衬底10的表面。如图6和图7所示，沟道层30覆盖在第一导电层21的外周面、绝缘层22的外周面，以及第二导电层23的外周面，沟道层30还覆盖在第二导电层的顶表面24。
其中，第一导电层21和第二导电层23中的一个形成源极，另一个形成漏极，环绕在叠层结构20的侧表面上的沟道层30形成沟道区，以在源极和漏极之间提供导电通道，使得载流子可以由源极移动至漏极或者由漏极移动至源极。介质层40可以为氧化物层，位于沟道层30的侧表面的介质层40形成栅氧层。
如图6和图7所示，沟道区为层状，沟道层30的材质可以包括硫化钼，例如二硫化钼，沟道层30的材质还可以为过渡金属硫化合物(TMDs)等。层状的硫化钼中存在带隙，其形成的场效应晶体管开关比高。此外，层状的硫化钼具有较高的比表面积，有利于克服短沟道效应。其中，开关比是指器件开状态电流与关状态电流的比值，具体的，在晶体管中，源、漏电压不变的情况下，施加门压和不施加门压时测得的源漏电流之比为开关比。
在一些可能的实施例中，沟道层30的材质为硫化钼，半金属层的材质为铋。优选地，沟道层30的材质为硫化钼，第一导电层21和第二导电层23的材质均为铋，如此设置，硫化钼与铋界面处的能垒降低，可以降低沟道层30和第一导电层21、沟道层30和第二导电层23之间的间隙态(MIGS)，从而降低沟道层30和第一导电层21、沟道层30和第二导电层23之间的接触电阻。
在本申请实施例中，形成覆盖叠层结构20的沟道层30，以及覆盖沟 道层30的介质层40可以包括：
在叠层结构20和衬底10上沉积沟道层30，沟道层30覆盖叠层结构20的顶表面、侧表面，以及衬底10的顶表面。参考图6和图7，沟道层30通过沉积工艺形成，沟道层30覆盖叠层结构20的顶表面、侧表面，以及衬底10的顶表面。再在沟道层30上沉积介质层40。参考图8和图9，介质层40通过沉积工艺形成，介质层40覆盖沟道层30的整个表面。
步骤S104：形成沿第一方向延伸的字线，字线包括多个接触部和连接相邻的接触部的连接部，接触部环绕且接触介质层的侧表面，接触部与至少部分绝缘层相对应。
参考图10和图11，在形成沟道层30和介质层40之后的叠层结构20之间形成字线63，字线63的数量为多条，多条字线63间隔设置且沿第一方向(图10所示的Y方向)延伸。如图10和图11所示，字线63包括多个接触部64和连接相邻接触部64的连接部65，其中，接触部64环绕且接触介质层40的侧表面。
如图10和图11所示，接触部64与至少部分绝缘层22相对应，接触部64用作晶体管的栅极，即字线63的一部分为栅极。沿垂直于衬底10的方向(图10所示的Z方向)，绝缘层22在该方向的正投影与接触部64在该方向的正投影至少部分重合，示例性的，接触部64的顶表面低于绝缘层22的顶表面，接触部64的底面高于绝缘层22的底面。
沿第一方向，连接部65连接相邻的两个接触部64，连接部65的高度可以与接触部64的高度相同，也可以不同，连接部65的具体结构可以根据实际工况确定。
综上，本申请实施例中，第一导电层21、绝缘层22和第二导电层23依次层叠设置形成叠层结构20，第一导电层21和第二导电层23中的至少一个为半金属层，一方面可以降低叠层结构20与其他结构的接触电阻，另一方面还可以降低第一导电层21和/或第二导电层23与沟道层30之间的接触电阻，从而提高半导体结构的性能。此外，第一导电层21、绝缘层22、第二导电层23、沟道层30、介质层40和接触部64形成垂直晶体管，可以通过调整叠层结构20的高度增加沟道层30的长度，便于改善晶体管的短沟道效应，提高半导体结构的性能。
在本申请一种可能的实施例中，参考图12至图15，形成沿第一方向 延伸的字线63，字线63包括多个接触部64和连接相邻的接触部64的连接部65，接触部64环绕且接触介质层40的侧表面，接触部64与至少部分绝缘层22相对的步骤之前，还包括：在覆盖有沟道层30和介质层40的叠层结构20之间填充第一支撑层50，第一支撑层50背离衬底10的表面高于第一导电层21背离衬底10的表面，且低于绝缘层22背离衬底10的表面。
如图12至图15所示，第一支撑层50可以作为垫层，增加后续形成的字线63与衬底10之间的间距，使得字线63的底面高于第一导电层21的顶表面，即字线63朝向衬底10的表面高于第一导电层21背离衬底10的表面。同时，第一支撑层50背离衬底10的表面低于绝缘层22背离衬底10的表面，使得字线63的底面低于第一导电层21的顶表面，从而保证字线63与绝缘层22相对。其中，第一支撑层50的材质可以为氮化硅或者氮氧化硅，第一支撑层50与介质层40具有较大的选择比，例如，第一支撑层50与介质层40的选择比大于5，以避免刻蚀第一支撑层50时损伤介质层40，从而减少晶体管的栅氧层的损伤。
在本申请一种可能的实现方式中，参考图12至图15，在覆盖有沟道层30和介质层40的叠层结构20之间填充第一支撑层50，第一支撑层50背离衬底10的表面高于第一导电层21背离衬底10的表面，且低于绝缘层22背离衬底10的表面可以包括以下过程：
在介质层40上形成第一初始支撑层51，第一初始支撑层51填充在覆盖有沟道层30和介质层40的叠层结构20之间，且第一初始支撑层51覆盖介质层40的顶表面。如图12和图13所示，沉积形成第一初始支撑层51，第一初始支撑层51填充在覆盖有沟道层30和介质层40的叠层结构20之间，第一初始支撑层51还覆盖介质层40的顶表面。具体的，第一初始支撑层51的上表面高于介质层40的上表面。
形成第一初始支撑层51后，去除部分第一初始支撑层51，保留的第一初始支撑层51形成第一支撑层50。如图14和图15所示，沿垂直于衬底10的方向，干法刻蚀或湿法刻蚀去除部分第一初始支撑层51，保留位于覆盖有沟道层30和介质层40的叠层结构20之间的部分第一初始支撑层51，保留的第一初始支撑层51形成第一支撑层50。
在上述实施例的基础上，即形成第一支撑层50后，在一种可能的示例 中，参考图16至图23，形成沿第一方向延伸的字线63，字线63包括多个接触部64和连接相邻的接触部64的连接部65，接触部64环绕且接触介质层40的侧表面，接触部64与至少部分绝缘层22相对可以包括以下步骤：
步骤S1041：形成覆盖第一支撑层和介质层的初始字线层。
参考图16和图17，通过沉积工艺形成初始字线层61，初始字线层61覆盖第一支撑层50和介质层40。如图16和图17所示，初始字线层61覆盖第一支撑层50的顶表面，且覆盖介质层40的侧表面和顶表面。覆盖在各介质层40的侧表面上的初始字线层61之间还具有间隙，也就是说，初始字线层61没有填充满覆盖有沟道层30和介质层40的叠层结构20之间的空间。
步骤S1042：沿第一方向去除位于第一支撑层上的部分初始字线层，以使初始字线层形成多条间隔设置的中间字线层。
参考图18至图23，去除位于第一支撑层50上的部分初始字线层61，以使初始字线层61形成多条间隔设置的中间字线层62，各中间字线层62均沿第一方向延伸，即沿第一方向去除第一支撑层50上的部分初始字线层61，保留的初始字线层61形成中间字线层62。
具体的，如图18至图23所示，沿第一方向去除位于第一支撑层50上的部分初始字线层61，以使初始字线层61形成多条间隔设置的中间字线层62还可以包括以下过程：
形成覆盖初始字线层61的掩膜层71，掩膜层71填充在覆盖有沟道层30、介质层40和初始字线层61的叠层结构20之间，且掩膜层71覆盖初始字线层61的顶表面。如图18和图19所示，在初始字线层61上沉积掩膜层71，掩膜层71填充在沟道层30、介质层40和初始字线层61的叠层结构20之间，掩膜层71还覆盖初始字线层61的顶表面。掩膜层71的顶表面高于初始字线层61的顶表面。
形成掩膜层71后，在掩膜层71上形成第一光刻胶层72，第一光刻胶层72具有沿第一方向延伸的沟槽73，沟槽73在衬底10上的正投影与位于叠层结构20侧表面的初始字线层61在衬底10上的正投影不相重叠。如图18和图19所示，在掩膜层71上旋涂第一光刻胶层72，第一光刻胶层72具有贯穿第一光刻胶层72的沟槽73，该沟槽73与位于介质层40的侧表面和顶表面上的初始字线层61错开，与第一支撑层50上的部分初始字 线层61相对。
形成第一光刻胶层72后，以第一光刻胶层72为掩膜，刻蚀掩膜层71。通过以第一光刻胶层72为掩膜刻蚀掩膜层71，第一光刻胶层72上的图形转移到掩膜层71，如图20和图21所示，掩膜层71形成的图案中暴露初始字线层61。
刻蚀掩膜层71后，以刻蚀后的掩膜层71为掩膜，刻蚀初始字线层61，以形成中间字线层62。利用各向异性刻蚀，去除第一支撑层50上的部分初始字线层61，如图22和图23所示，保留的初始字线层61形成中间字线层62。多个中间字线层62之间的间隙暴露第一支撑层50。
步骤S1043：去除介质层的顶表面上的中间字线层，以及介质层的侧表面上远离衬底的部分中间字线层，保留的中间字线层形成字线。
刻蚀去除介质层40的顶表面上的中间字线层62，以及介质层40的侧表面上的上部分中间字线层62，保留的中间字线层62形成字线63。如图10和图11所示，字线63的顶表面低于绝缘层22的顶表面，字线63与绝缘层22相对。
在本申请另一种可能的实施例中，形成沿第一方向延伸的字线63，字线63包括多个接触部64和连接相邻的接触部64的连接部65，接触部64与叠层结构20连接，且接触部64环绕在介质层40的侧表面上的步骤之后，参考图24至图33，半导体结构的制作方法还包括：
形成覆盖字线63、第一支撑层50，以及介质层40的第二支撑层81。如图24和图25所示，沉积第二支撑层81，第二支撑层81覆盖字线63、第一支撑层50和介质层40，第二支撑层81的顶表面高于介质层40的顶表面。第二支撑层81背离衬底10的表面可以齐平，示例性的，对第二支撑层81平坦化处理，例如化学机械研磨(Chemical Mechanical Polishing，简称CMP)，以使第二支撑层81的顶表面齐平。第二支撑层81的材质可以与第一支撑层50的材质相同，均为绝缘材料，以使第二支撑层81和第一支撑层50形成一体，第二支撑层81和第一支撑层50将各字线63包覆并隔离，以使各字线63之间绝缘。
形成第二支撑层81后，在第二支撑层81上形成第二光刻胶层82，第二光刻胶层82具有多个开口83，开口83与叠层结构20正对。如图24和 图25所示，在第二支撑层81上形成第二光刻胶层82，第二光刻胶层82具有多个开口83，多个开口83与多个叠层结构20分别对应，且开口83与相对应的叠层结构20正对。各开口83在衬底10上的正投影位于其对应的叠层结构20在衬底10上的正投影之内，或者，各开口83在衬底10上的正投影与其对应的叠层结构20在衬底10上的正投影相重合。
形成第二光刻胶层82后，以第二光刻胶层82为掩膜，刻蚀第二支撑层81、介质层40和沟道层30，形成接触孔84，接触孔84暴露第二导电层23。如图26和图27所示，接触孔84贯穿第二支撑层81、介质层40和沟道层30，以暴露第二导电层23。形成接触孔84的同时，第二光刻胶层82也被去除，或者，形成接触孔84后，再去除第二光刻胶层82。如图28和图29所示，去除第二光刻胶层82后，第二支撑层81的顶表面暴露出来。
需要说明的是，接触孔84的开口83的面积大于接触孔84的底部的面积，即接触孔84的上部分宽度较大，下部分宽度较小。如此设置，在接触孔84内形成第三导电层90后，第三导电层90的上部分宽度较大，通过增加操作窗口的宽度，便于与电容对准。此外，第三导电层90的下部分宽度较小，可以降低晶体管的临界尺寸。
示例性的，以垂直与衬底10的平面为截面，接触孔84的截面形状可以为上大下小的倒梯形。如图30和图31所示，接触孔84的截面形状还可以为相连接的矩形和梯形，矩形设置在梯形靠近衬底10的一侧，矩形的底边与梯形的上底相重合。
形成接触孔84后，在接触孔84内形成第三导电层90，第三导电层90与第二导电电连接。如图32和图33所示，接触孔84内沉积第三导电层90，第三导电层90与第二导电层23相接触，以实现第三导电层90与第二导电层23电连接。第三导电层90可以为电容接触垫，第三导电层90上形成电容。
参考图10和图11，本申请实施例还提供一种半导体结构，其包括：叠层结构20、沟道层30、介质层40和栅极。其中，叠层结构20设置在衬底10上，衬底10用于支撑叠层结构20，衬底10可以为半导体衬底，例如硅衬底。
衬底10内还可以设置有多条位线11，多条位线11之间彼此间隔，多条位线11沿第二方向(图11所示的X方向)延伸。位线11可以暴露于衬底10的表面，以便于与位于衬底10上的其他结构电连接。相邻的位线11之间还可以设置浅槽隔离结构12，通过浅槽隔离结构12将各位线11隔离。
衬底10上设置有多个叠层结构20，各叠层结构20间隔设置。叠层结构20包括层叠设置的第一导电层21、绝缘层22和第二导电层23。如图10和图11所示，沿远离衬底10的方向，第一导电层21、绝缘层22和第二导电层23依次设置。第一导电层21和第二导电层23中的一个为源极，第一导电层21和第二导电层23中的另一个为漏极，源极和漏极中的至少一个为半金属层，半金属层的材质可以为铋，绝缘层22的材质可以为氧化硅。通过将源极或者漏极中的至少一个设置为半金属层，可以减少叠层结构20与其他结构(例如位线11和/或电容)之间的接触电阻，从而提高半导体结构的性能。
继续参考图10和图11，沿第二方向，每条位线11上至少设置有一个叠层结构20，叠层结构20中的源极和漏极中的一个与位线11相接触，从而实现该源极或者漏极与位线11的电连接。叠层结构20可以为柱状，例如圆柱、椭圆柱、方柱或者长方柱，叠层结构20可以为阵列排布。
叠层结构20的侧表面覆盖有沟道层30，环绕在叠层结构20的侧表面上的沟道层30形成沟道区，以在源极和漏极之间提供导电通道，使得载流子可以由源极移动至漏极或者由漏极移动至源极。沟道区为层状，沟道层30的材质可以包括硫化钼，例如二硫化钼。层状的硫化钼中存在带隙，其形成的场效应晶体管开关比高。优选地，沟道层30的材质为硫化钼，源极和漏极的材质均为铋，以降低沟道层30和源极、沟道层30和漏极之间的间隙态及能垒，从而降低沟道层30和源极、沟道层30和漏极之间的接触电阻。
沟道层30的侧表面覆盖有介质层40，介质层40可以为氧化物层，位于沟道层30的侧表面的介质层40形成栅氧层。示例性的，介质层40的材质为氧化硅。
继续参考图10和图11，介质层40上环设有栅极，栅极环绕在介质层40的侧表面上，且与介质层40的侧表面相接触。栅极与至少部分绝缘层 22相对，沿垂直与衬底10的方向(图10所示的Z方向)，介质层40在该方向的正投影与栅极在该方向的正投影至少部分重合。示例性的，栅极的顶表面低于介质层40的顶表面，栅极的底面高于介质层40的底面。
本申请实施例中的半导体结构还包括字线63，字线63沿第一方向延伸，字线63包括接触部64和连接相邻两个接触部64的连接部65，其中，接触部64为环设在介质层40上的栅极，即字线63的一部分为栅极。可以理解的是，沿第一方向，连接部65和栅极间隔设置，连接部65将第一方向上的多个栅极连成一体，形成字线63。
在一些可能的示例中，参考图32和图33，字线63设置在第一支撑层50上，第一支撑层50位于字线63的下方，并填充在覆盖有介质层40和沟道层30的叠层结构20之间，以垫高字线63。字线63上还可以覆盖有第二支撑层81，第二支撑层81和第一支撑层50对字线63进行电气隔离。第二支撑层81的材质可以与第一支撑层50的材质相同，以使第二支撑层81和第一支撑层50形成一体。
继续参考图32和图33，第二支撑层81还覆盖介质层40，第二支撑层81具有接触孔，接触孔贯穿介质层40和沟道层30，以暴露叠层结构20的第二导电层23。接触孔内填充第三导电层90，第三导电层90的一端与第二导电层23相接触，以实现第三导电层90与第二导电层23电连接，第三导电层90的另一端可以连接电容。
本申请实施例的半导体结构中，第一导电层21、绝缘层22和第二导电层23依次层叠设置形成叠层结构20，第一导电层21和第二导电层23中的一个为源极，另一个为漏极，第一导电层21和第二导电层23中的至少一个为半金属层，一方面可以降低叠层结构20与其他结构的接触电阻，另一方面还可以降低第一导电层21和/或第二导电层23与沟道层30之间的接触电阻，从而提高半导体结构的性能。此外，叠层结构20的侧表面覆盖有沟道层30，沟道层30的侧表面覆盖有介质层40，介质层40上环设有栅极，叠层结构20、沟道层30、介质层40和栅极形成垂直晶体管，可以通过调整叠层结构20的高度增加沟道层30的长度，便于改善晶体管的短沟道效应，提高半导体结构的性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参 见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制作方法，包括：
    提供衬底；
    在所述衬底上形成多个间隔设置的叠层结构，所述叠层结构包括依次层叠设置的第一导电层、绝缘层和第二导电层，所述第一导电层和所述第二导电层中的至少一个为半金属层；
    形成覆盖所述叠层结构的沟道层，以及覆盖所述沟道层的介质层；
    形成沿第一方向延伸的字线，所述字线包括多个接触部和连接相邻的所述接触部的连接部，所述接触部环绕且接触所述介质层的侧表面，所述接触部与至少部分所述绝缘层相对。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述沟道层的材质包括硫化钼，和/或所述半金属层的材质包括铋。
  3. 根据权利要求1所述的半导体结构的制作方法，其中，形成覆盖所述叠层结构的沟道层，以及覆盖所述沟道层的介质层的步骤包括：
    在所述叠层结构和所述衬底上沉积所述沟道层，所述沟道层覆盖所述叠层结构的顶表面、侧表面，以及所述衬底的顶表面；
    在所述沟道层上沉积所述介质层。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，形成沿第一方向延伸的字线，所述字线包括多个接触部和连接相邻的所述接触部的连接部，所述接触部环绕且接触所述介质层的侧表面，所述接触部与至少部分所述绝缘层相对的步骤之前，还包括：
    在覆盖有所述沟道层和所述介质层的所述叠层结构之间填充第一支撑层，所述第一支撑层背离所述衬底的表面高于所述第一导电层背离所述衬底的表面，且低于所述绝缘层背离所述衬底的表面。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，在覆盖有所述沟道层和所述介质层的所述叠层结构之间填充第一支撑层，所述第一支撑层背离所述衬底的表面高于所述第一导电层背离所述衬底的表面，且低于所述绝缘层背离所述衬底的表面的步骤包括：
    在所述介质层上形成第一初始支撑层，所述第一初始支撑层填充在覆盖有所述沟道层和所述介质层的所述叠层结构之间，且所述第一初始支撑 层覆盖所述介质层的顶表面；
    去除部分所述第一初始支撑层，保留的所述第一初始支撑层形成所述第一支撑层。
  6. 根据权利要求4所述的半导体结构的制作方法，其中，形成沿第一方向延伸的字线，所述字线包括多个接触部和连接相邻的所述接触部的连接部，所述接触部环绕且接触所述介质层的侧表面，所述接触部与至少部分所述绝缘层相对的步骤包括：
    形成覆盖所述第一支撑层和所述介质层的初始字线层；
    沿第一方向去除位于所述第一支撑层上的部分所述初始字线层，以使所述初始字线层形成多条间隔设置的中间字线层；
    去除所述介质层的顶表面上的所述中间字线层，以及所述介质层的侧表面上远离所述衬底的部分所述中间字线层，保留的所述中间字线层形成字线。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，沿第一方向去除位于所述第一支撑层上的部分所述初始字线层，以使所述初始字线层间断，形成多条间隔设置的中间字线层的步骤包括：
    形成覆盖所述初始字线层的掩膜层，所述掩膜层填充在覆盖有所述沟道层、所述介质层和所述初始字线层的所述叠层结构之间，且所述掩膜层覆盖所述初始字线层的顶表面；
    在所述掩膜层上形成第一光刻胶层，所述第一光刻胶层具有沿第一方向延伸的沟槽，所述沟槽在所述衬底上的正投影与位于所述叠层结构侧表面的初始字线层在所述衬底上的正投影不相重叠；
    以所述第一光刻胶层为掩膜，刻蚀所述掩膜层；
    以刻蚀后的所述掩膜层为掩膜，刻蚀所述初始字线层，以形成所述中间字线层。
  8. 根据权利要求4所述的半导体结构的制作方法，其中，形成沿第一方向延伸的字线，所述字线包括多个接触部和连接相邻的所述接触部的连接部，所述接触部环绕且接触所述介质层的侧表面，所述接触部与至少部分所述绝缘层相对的步骤之后，还包括：
    形成覆盖所述字线、所述第一支撑层，以及所述介质层的第二支撑层，所述第二支撑层背离所述衬底的表面齐平；
    在所述第二支撑层上形成第二光刻胶层，所述第二光刻胶层具有多个开口，所述开口与所述叠层结构正对；
    以所述第二光刻胶层为掩膜，刻蚀所述第二支撑层、所述介质层和所述沟道层，形成接触孔，所述接触孔暴露所述第二导电层；
    在所述接触孔内形成第三导电层，所述第三导电层与所述第二导电电连接。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，所述接触孔的开口的面积大于所述接触孔的底部的面积。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，以垂直于所述衬底的平面为截面，所述接触孔的截面形状包括相连接的矩形和梯形，所述矩形设置在所述梯形靠近所述衬底的一侧，所述矩形的底边与所述梯形的上底相重合。
  11. 根据权利要求1所述的半导体结构的制作方法，其中，所述衬底内设置有多条间隔设置的位线，所述位线沿第二方向延伸；
    沿所述第二方向，每条所述位线上至少设置有一个所述叠层结构，所述第一导电层与所述位线电连接。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，所述衬底内还设置有浅槽隔离结构，所述浅槽隔离结构设置在相邻的所述位线之间。
  13. 一种半导体结构，包括：叠层结构、覆盖所述叠层结构的侧表面的沟道层、覆盖所述沟道层的侧表面的介质层，以及环设在所述介质层上的栅极；
    所述叠层结构包括依次层叠设置的第一导电层、绝缘层和第二导电层，所述第一导电层和所述第二导电层中的一个为源极，所述第一导电层和所述第二导电层中的另一个为漏极，所述源极和所述漏极中的至少一个为半金属层。
  14. 根据权利要求13所述的半导体结构，其中，所述沟道层的材质包括硫化钼，和/或所述半金属层的材质包括铋。
  15. 根据权利要求13所述的半导体结构，其中，所述半导体结构还包括字线和位线；
    所述位线设置在衬底中，所述叠层结构设置在所述衬底上，所述源极和所述漏极中的一个与所述位线电连接，所述字线包括栅极以及连接相邻 的两个所述栅极之间的连接部。
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