WO2023071237A1 - 一种绝缘栅双极晶体管及其制造方法、电子设备 - Google Patents

一种绝缘栅双极晶体管及其制造方法、电子设备 Download PDF

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Publication number
WO2023071237A1
WO2023071237A1 PCT/CN2022/100066 CN2022100066W WO2023071237A1 WO 2023071237 A1 WO2023071237 A1 WO 2023071237A1 CN 2022100066 W CN2022100066 W CN 2022100066W WO 2023071237 A1 WO2023071237 A1 WO 2023071237A1
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region
type
igbt
collector
area
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English (en)
French (fr)
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杨文韬
胡淼
宋超凡
赵倩
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Huawei Digital Power Technologies Co Ltd
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Huawei Digital Power Technologies Co Ltd
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Priority to EP22885143.2A priority Critical patent/EP4340036A4/en
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Priority to US18/651,513 priority patent/US20240282811A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments

Definitions

  • the present application relates to the field of integrated circuit manufacturing, in particular to an insulated gate bipolar transistor, a manufacturing method thereof, and electronic equipment.
  • Insulated gate bipolar transistor is composed of bipolar junction transistor (BJT) and metal-oxide-semiconductor field-effect Transistor (MOSFET) Composite fully controlled voltage-driven functional semiconductor device.
  • BJT bipolar junction transistor
  • MOSFET metal-oxide-semiconductor field-effect Transistor
  • IGBT integrates the advantages of MOSFET and BJT, that is, it has high input impedance, fast switching speed, good thermal stability, simple driving circuit, small driving current, low saturation voltage, high withstand voltage and large current. Therefore, IGBT is very suitable for application in the conversion system with a DC voltage of 600V and above, such as AC motors, frequency converters, switching power supplies, lighting circuits, traction drives and other fields.
  • the existing IGBT has the problem of poor withstand voltage characteristics.
  • the withstand voltage characteristics include the maximum reverse withstand voltage level of the IGBT, which can be reflected by BVCES (collector–emitter blocking voltage).
  • BVCES is the gap between the gate and the emitter. When short-circuited, under the specified collector and emitter current, the maximum reverse withstand voltage between the collector and emitter can be tolerated. The larger the maximum reverse withstand voltage, the better the withstand voltage characteristics of the device.
  • the embodiments of the present application provide an insulated gate bipolar transistor, a manufacturing method thereof, and an electronic device, so as to improve the withstand voltage characteristic of the device.
  • an insulated gate bipolar transistor IGBT which includes a first surface and a second surface opposite to each other, and has sequentially connected front-side devices in the direction from the first surface to the second surface.
  • the IGBT drift region has a first type of doping element
  • the IGBT buffer has a first type of doping element
  • the concentration of the first type of doping element in the IGBT buffer is greater than that in the IGBT drift region
  • the concentration of the first type of doping element, the IGBT collector region includes the cell collector region, the field plate collector region and the field limit ring collector region, the projection of the cell collector region and the cell region on the first surface
  • the IGBT collector region has the second type of doping element, when the concentration of the second type of doping
  • the cell collector region is a heavily doped region
  • the field plate collector region is a lightly doped region
  • the cell collector region may be a heavily doped region
  • the field plate collector region may be a lightly doped region
  • the concentration of the second type of doping element in the field plate collector region is effectively reduced, so The amplification factor of the triode in the field plate area can be effectively reduced, and the withstand voltage characteristic of the device can be improved.
  • the concentration of the second type of doping element in the cell collector region is greater than the concentration of the second type of doping element in the field limiting ring collector region.
  • the concentration of the second type of dopant element in the cell collector region may be greater than the concentration of the second type of dopant element in the field plate collector region, and may also be greater than that of the field limiting ring collector.
  • concentration of the second type of doping element in the region can effectively reduce the amplification factor of the triode in the terminal region and improve the withstand voltage characteristics of the device.
  • the cell collector region is a heavily doped region
  • the field limiting ring collector region is a lightly doped region
  • the collector region of the field limiting ring can be a lightly doped region, so that the concentration of the second type of doping element in the collector region of the field limiting ring can be effectively reduced, so the concentration of the field limiting ring region can be effectively reduced.
  • the amplification factor of the triode improves the withstand voltage characteristics of the device.
  • the IGBT is a planar gate IGBT
  • the cell region includes a base region, a gate region, and a gate oxide region
  • the base region includes a base region, a first emitter region, and a second emitter region, and the first emitter region and the second emitter region are located at The side of the base region away from the second surface;
  • the first emitter region has a first type of doping element
  • the second emitter region has a second type of dopant element
  • the base has a second type of doping element;
  • the first emission region is used to connect the emitter;
  • the concentration of the second type of doping element in the second emission region is greater than that of the second type in the base region
  • the gate region is used to connect the gate electrode, and the gate region and the gate oxide region are located on the side away from the second surface outside the base region;
  • the IGBT set The electrode area is used to connect the collector.
  • the IGBT may be a planar gate IGBT, and the gate region and the gate oxide region are arranged outside the base region, which is beneficial to realize device diversity.
  • the IGBT is a trench gate IGBT
  • the cell region includes a base region, the base region includes a base region, a gate region, a gate oxide region, a first emitter region, and a second emitter region, the gate region, the gate oxide region, the The first emitter region and the second emitter region are located on the side of the base region away from the second surface; the first emitter region has a doping element of the first type, and the second emitter region There is a doping element of the second type in the base region, the doping element of the second type is present in the base region; the first emitting region is used to connect the emitter; the doping element of the second type in the second emitting region The concentration is greater than the concentration of the second type of doping element in the base region; the gate region is used to connect the gate electrode, and the gate oxide region surrounds the gate region in the base region; The IGBT collector region is used to connect the collector.
  • the IGBT may be a trench gate IGBT, and the gate region and the gate oxide region are arranged inside the base region, which is beneficial to realize device diversity.
  • the field plate region includes a first field ring region, a gate bus line, and a field plate dielectric layer located between the first field ring region and the gate bus line; the first There is a second type of doping element in the field ring region, which is used to connect the emitter; the gate bus is used to connect the gate electrode;
  • the field-limiting ring area includes a second field ring area, a control structure, and a field-limiting ring dielectric layer between the second field ring area and the control structure; the second field ring area has a second type doping elements.
  • the field plate area may include a first field ring area, a gate bus line, and a field plate dielectric layer
  • the field-limited ring area may include a second field ring area, a control structure, and a field-limited ring dielectric layer, thereby effectively
  • the IGBT realizes the function of planar electric field voltage division.
  • the first type is N type
  • the second type is P type
  • the first type may be N type
  • the second type may be P type
  • a method for manufacturing an insulated gate bipolar transistor IGBT including:
  • a front device region is formed on the first surface of the substrate;
  • the substrate has a first type of doping element;
  • the front device region includes a cell region and a terminal region surrounding the cell region;
  • the terminal region includes a surrounding a field plate region of the cellular region, and a field limiting ring region surrounding the field plate region;
  • the part of the substrate facing the second surface is doped with the first type of doping element to obtain an IGBT buffer zone; the concentration of the first type of doping element in the IGBT buffer zone is greater than that in the substrate
  • the concentration of the doping element of the first type, the substrate between the front device region and the IGBT buffer zone serves as the IGBT drift region; the first surface and the second surface are opposite surfaces;
  • the first doping of the second type of doping element is carried out in the part of the IGBT drift region facing the second surface to obtain the IGBT collector region;
  • the IGBT collector region includes a cell collector region, a field plate collector area and field limiting ring collector area, the cell collector area coincides with the projection of the cell area on the first surface, the field plate collector area and the field plate area are in the The projection of the first surface coincides, and the field-limiting ring collector region coincides with the projection of the field-limiting ring region on the first surface;
  • the first type is P-type or N-type
  • the second type is P-type or N-type, the first type and the second type are different;
  • the concentration is greater than the concentration of the dopant element of the second type in the field plate collector region.
  • the field plate collector region is shielded, and the IGBT collector region is doped with a second type of doping element for the second time, so that the The concentration of the second type of dopant element is greater than the concentration of the second type of dopant element in the field plate collector region, comprising:
  • the concentration of the second type of dopant element is greater than the concentration of the second type of dopant element in the field plate collector region, and greater than the concentration of the second type of dopant element in the field limiting ring collector region concentration.
  • the first doping is light doping
  • the second doping is heavy doping
  • the IGBT is a planar gate IGBT
  • the cell region includes a base region, a gate region, and a gate oxide region
  • the base region includes a base region, a first emitter region, and a second emitter region.
  • Two emission regions, the first emission region and the second emission region are located on the side of the base region away from the second surface; the first emission region is used to connect the emitter, and the gate region
  • the IGBT collector region is used for connecting the collector; the gate region and the gate oxide region are located on a side away from the second surface outside the substrate;
  • forming a base region on the first surface of the substrate includes: performing doping with a second type of doping element on a part of the substrate that is away from the second surface to obtain a base region; The first part of the two surfaces is doped with a doping element of the first type to obtain a first emitter region, and the second part of the base region facing away from the second surface is doped with a doping element of a second type to obtain a second emission region. launch area.
  • the IGBT is a trench gate IGBT
  • the cell region includes a base region; the base region includes a base region, a gate region, a gate oxide region, a first emitter region, and a second emitter region.
  • Two emitter regions, the gate region, the gate oxide region, the first emitter region and the second emitter region are located on the side of the base region away from the second surface; the first The emitter region is used to connect the emitter, the gate region is used to connect the gate electrode, and the IGBT collector region is used to connect the collector; the gate region and the gate oxide region are located in the substrate away from the one side of the second surface;
  • forming a base region on the first surface of the substrate includes: performing doping with a second type of doping element on a part of the substrate that is away from the second surface to obtain a base region; The first part of the two surfaces is doped with a doping element of the first type to obtain a first emitter region, and the second part of the base region facing away from the second surface is doped with a doping element of a second type to obtain a second emission region. launch area.
  • the field plate region includes a first field ring region, a gate bus line, and a field plate dielectric layer located between the first field ring region and the gate bus line; the first There is a second type of doping element in the field ring region, which is used to connect the emitter; the gate bus is used to connect the gate electrode;
  • the field limit ring area includes a second field ring area, a control area, and a field limit ring dielectric layer between the second field ring area and the control area; the second field ring area has a second type doping elements.
  • the first type is N type
  • the second type is P type
  • a third aspect of the embodiments of the present application provides an electronic device, including a circuit board and the IGBT according to the first aspect connected to the circuit board.
  • the electronic device is a power converter.
  • FIG. 1 is a schematic diagram of a smart grid architecture provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of an IGBT provided in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another IGBT provided in the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a static characteristic of an IGBT provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an IGBT working safety area provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a negative resistance phenomenon provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another IGBT provided in the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another IGBT provided in the embodiment of the present application.
  • FIG. 9 is a flowchart of a method for manufacturing an IGBT provided in an embodiment of the present application.
  • FIGS 10-14 are structural schematic diagrams of the IGBT provided in the embodiment of the present application during the manufacturing process.
  • Embodiments of the present application provide an insulated gate bipolar transistor, a manufacturing method thereof, and an electronic device, which improve the withstand voltage characteristics of the device.
  • the IGBT has the problem of poor withstand voltage characteristics.
  • the withstand voltage characteristics include the maximum reverse withstand voltage level of the IGBT, which can be reflected by BV CES .
  • BV CES is when the gate and the emitter are short-circuited. Under the action of the current of the electrode and the emitter, the maximum reverse withstand voltage between the collector and the emitter, the greater the maximum reverse withstand voltage, the better the withstand voltage characteristics of the device.
  • the maximum reverse withstand voltage As the current between the collector and emitter increases, the maximum reverse withstand voltage also increases. However, when the maximum reverse withstand voltage exceeds the avalanche withstand capacity of the device, BV CES will snap back. At this time, as the current increases, the maximum reverse withstand voltage decreases instead, that is, the BV negative resistance effect appears, and the device will generate a large leakage phenomenon in the device terminal area. As the current further increases, the device magnification Increase, under this negative feedback, the device is damaged and eventually burned.
  • an embodiment of the present application provides an insulated gate bipolar transistor IGBT and its manufacturing method, and electronic equipment.
  • the IGBT includes opposite first surfaces and second surfaces.
  • On the top there are sequentially connected front device area, IGBT drift area, IGBT buffer zone and IGBT collector area, wherein the front device area can include the cell area and the terminal area surrounding the cell area, and the terminal area includes the field surrounding the cell area
  • the IGBT drift area has a first type of doping element
  • the IGBT buffer area has a first type of doping element
  • the IGBT buffer area has a first type of doping element
  • the concentration of the element is greater than the concentration of the first type of doping element in the IGBT drift region.
  • the IGBT collector region includes the cell collector region, the field plate collector region and the field limit ring collector region.
  • the cell collector region and the element The projection of the cell area on the first surface coincides, the projection of the field plate collector area and the field plate area on the first surface coincides, the projection of the field limiting ring collector area and the field limiting ring area on the first surface coincides, and the IGBT collector area
  • There is a second type of doping element in the cell collector region when the concentration of the second type of doping element in the cell collector region is equal to the concentration of the second type of doping element in the field plate collector region, the field plate region is often larger than the element
  • the cell region is easier to break down, so the concentration of the second type of doping element in the cell collector region can be designed to be greater than the concentration of the second type of doping element in the field plate collector region, that is, the same as that of the cell region
  • the opposite part of the collector region has a larger concentration of the second type of doping element, while the part of the
  • IGBT is used to realize power conversion and can be applied to power converters, suitable for conversion systems with a DC voltage of 600V and above, such as frequency converters, AC motors, switching power supplies, lighting circuits, traction drives and other fields, and is also suitable for new energy Automotive, smart grid, rail transit and other fields.
  • IGBT modules play a vital role in electric vehicles and are the core technical components of equipment such as electric vehicle charging piles. IGBT modules account for nearly 10% of the cost of electric vehicles and about 20% of the cost of charging piles. IGBT can be applied to the electronic control system of electric vehicles, through high-power DC/AC (DC/AC) inverter to drive the motor; /AC) inverter, where IGBTs with smaller currents can be used; it can also be applied to charging piles, where the IGBT modules are used as switching elements.
  • DC/AC DC/AC
  • IGBTs are widely used in power generation, transmission, transformation and consumption of smart grids: From the perspective of power generation, rectifiers and inverters in wind power generation and photovoltaic power generation require IGBT modules. From the perspective of power transmission, flexible AC transmission systems (FACTS) in UHV DC transmission require a large number of power devices such as IGBTs. From the point of view of the substation, the IGBT is the key device of the power electronic transformer (PET). From the perspective of power consumption, household white goods, microwave ovens, light-emitting diode (light-emitting diode, LED) lighting drivers, etc. all have a large demand for IGBTs.
  • FACTS flexible AC transmission systems
  • PEG power electronic transformer
  • Fig. 1 it is a structure of a smart grid in the embodiment of the present application, including sequentially connected solar panels (PV panels), DC-DC (DC-DC) maximum power point tracking (maximum power point tracking, MPPT) ) system, DC link (DC link), DC-AC inverter (DC-AC inverter), AC filter (AC Filter), and output terminal, wherein the DC-AC inverter may be provided with IGBT devices.
  • PV panels DC-DC
  • MPPT maximum power point tracking
  • DC link DC link
  • DC-AC inverter DC-AC inverter
  • AC Filter AC filter
  • the DC-AC inverter may be provided with IGBT devices.
  • IGBT devices have become mainstream power electronic devices for rail vehicle traction converters and various auxiliary converters.
  • AC drive technology is one of the core technologies of modern rail transit.
  • the traction converter is a key component in the AC drive system, and the IGBT is one of the core components of the traction converter.
  • the insulated gate bipolar transistor may include the opposite first surface A1 and the second surface A2, and in the direction from the first surface A1 to the second surface A2, there are sequentially a front device region 1001 and an IGBT drift region 1002 , IGBT buffer zone 1003 and IGBT collector region 1004 .
  • the first surface A1 can be used as the front side of the chip
  • the second surface A2 can be used as the back side of the chip.
  • FIG. 2 it is a top view of an IGBT provided by the embodiment of the present application, that is, a schematic structural diagram of the front side of the chip.
  • FIG. 3 it is a schematic structural diagram of another IGBT provided by the embodiment of the present application, FIG. 3 It may be a cross-sectional view of the IGBT in FIG. 2 along the AA direction.
  • the first surface A1 is used as the upper surface
  • the second surface A2 is used as the lower surface, that is, “upper” and “lower” are defined.
  • the positional relationship, in fact, the "upper” and “lower” here are defined for the convenience of description, and are related to the placement position of the IGBT, so this description should not be used as a limitation of the device structure.
  • doping elements can be doped in semiconductors, and the types of doping elements can be divided into P-type (hole type, positive) and N-type (electronic type, negative).
  • P-type doping elements are used to obtain P-type semiconductors, such that P-type semiconductors are mainly hole-conducting, or N-type semiconductors are obtained by doping N-type doping elements in semiconductors, such that N-type semiconductors are mainly electronically conducting.
  • the concentration of the doping element in the semiconductor after doping is used as the doping concentration, which can be expressed by the ratio of the doping element to the semiconductor element, or by the number of atoms of the doping element per unit volume.
  • the P-type doping elements may be group III elements, such as boron, indium, etc.
  • the N-type elements may be group V elements, such as nitrogen, phosphorus, and the like.
  • the doping of the semiconductor can be divided into lightly doped and heavily doped, and the corresponding doped semiconductor is lightly doped semiconductor and heavily doped semiconductor.
  • lightly doped means that the amount of doping elements doped is small, and the concentration of doping elements in the semiconductor after doping is relatively low, for example, the atomic number ratio of doping elements and semiconductor elements is about one billionth.
  • lightly doping P-type doping elements in semiconductors can be expressed as hole-less (P-type) doping to obtain P-type semiconductors
  • lightly doping N-type doping elements in semiconductors can be expressed as electron-less type (N-type) doping to obtain an N-type semiconductor.
  • Heavy doping refers to the amount of doping elements added, and the concentration of doping elements in the semiconductor after doping is relatively high, for example, the atomic number ratio of doping elements and semiconductor elements is about 1/1000.
  • heavy doping of P-type doping elements in semiconductors can be expressed as multi-hole type (P+ type) doping to obtain P+ type semiconductors
  • heavy doping of N-type doping elements in semiconductors can be expressed as multi-electron type (N+ type) doping to obtain N+ type semiconductor.
  • the front device region 1001 is located on the side of the device facing the first surface A1, including the cell region 10 and the terminal region 20 surrounding the cell region 10.
  • the terminal region 20 can realize the function of chip plane electric field voltage division .
  • the termination region 20 may include a field plate region 21 and a field limit ring region 22 , wherein the field plate region 21 surrounds the cell region 10 , and the field limit ring region 22 surrounds the field plate region 21 .
  • the cellular region 10, the field plate region 21, and the field limiting ring region 22 can be separated by two dashed lines, and the positions of the two dashed lines are used to represent the cellular region 10, the field plate region 21, and the field limiting ring region.
  • Fig. 3 is a cross-sectional view, in fact the boundary between the cell region 10 and the field plate region 21 is a closed ring, and the boundary between the field plate region 21 and the field limiting ring 22 is a closed ring.
  • the cell region 10 may include a base region, a gate region 106 and a gate oxide region 107, the base region includes a base region 103, a first emitter region 104 and a second emitter region 105, the first The emitter region 104 and the second emitter region 105 are located on the side of the base region away from the second surface A2, wherein the first emitter region 104 has a doping element of the first type, and the second emitter region 105 has a dopant element of the second type.
  • the base region 103 has a second type of doping element
  • the first emitter region 104 is used to connect the emitter 108
  • the concentration of the second type of doping element in the second emitter region is greater than that of the second type of doping element in the base region 103
  • the concentration of the type of dopant element is not limited to that of the second type of dopant element.
  • the gate region 106 and the gate oxide region 107 may be located on the side away from the second surface A2 outside the base region, and the gate oxide region 107 is connected to the first emitter region 104 and the base region 103 at the same time, for example, the gate oxide region 107 is located on The first emitter region 104 and the base region 103 are away from the side of the second surface A2, that is, above the base region, and the gate region 106 is located on the side of the gate oxide region 107 away from the second surface A2, that is, the gate oxide region 107 Above, the gate region 106 is used to connect the gate electrode, serving as the control region of the device.
  • the cell region 10 may include a base region, and the base region includes a base region 103, a gate region 106, a gate oxide region 107, a first emitter region 104, and a second emitter region 105.
  • the electrode region 106, the gate oxide region 107, the first emitter region 104 and the second emitter region 105 are located on the side of the base region away from the second surface A2, wherein the first emitter region 104 has a doping element of the first type, The second emitter region 105 has a doping element of the second type, the base region 103 has a dopant element of the second type, the first emitter region 104 is used to connect the emitter 108, and the dopant element of the second type in the second emitter region
  • the concentration of the hetero element is greater than the concentration of the second type of doping element in the base region 103 .
  • the gate region 106 and the gate oxide region 107 may be located in the base region, the gate oxide region 107 surrounds the gate region 106 in the base region, and the gate oxide region 107 is simultaneously connected to the first emitter region 104 and the base region 103
  • the sidewall of the gate oxide region 107 is connected to the first emitter region 104 on the side away from the second surface A2, and the other part of the sidewall is connected to the base region 103, and the gate region 106 is used to connect the gate electrode, as the device control area.
  • the first emission region 104 and the second emission region 105 may be covered with a cellular dielectric layer, and the cellular dielectric layer may include a first dielectric layer 101 and a second dielectric layer 102 thereon, the first dielectric layer 101 covers the first emitter region 104 and the second emitter region 105, the first dielectric layer 101 may be a local oxidation of silicon (LOCOS) layer, and the material of the second dielectric layer 102 may be silicon oxide.
  • LOC local oxidation of silicon
  • the first dielectric layer 101 and the second dielectric layer 102 can be etched to form an etching hole, and a conductor material is formed in the etching hole, and the conductor material can be used as the emitter 108 .
  • the field plate region 21 may include a first field ring region 211, the first field ring region 211 may be connected to the emitter 108, the first field ring region 211 has a second type of doping element, and the first field ring region 211 is provided with There is a field ring dielectric layer.
  • the field ring dielectric layer includes a third dielectric layer 212 and a fourth dielectric layer 213 thereon.
  • the third dielectric layer 212 can be an oxide isolation layer, and the material of the fourth dielectric layer 213 can be silicon oxide.
  • a gate bus (gate bus) 214 can be arranged on the fourth dielectric layer 213, and the gate bus 214 can be connected to the gate electrode of the cell area 10; the field-limiting ring area 22 can include a plurality of second field ring areas 221, the first A field-limiting ring dielectric layer is arranged on the second field ring region 221.
  • the field-limiting ring dielectric layer may include a fifth dielectric layer 222 and a sixth dielectric layer 223 thereon.
  • the fifth dielectric layer 222 may be an oxide isolation layer.
  • the material of the dielectric layer 223 can be silicon oxide, and the fifth dielectric layer 222 is also provided with a control structure 225 and a lead-out structure 224 on the control structure.
  • the lead-out structure 224 can penetrate the sixth dielectric layer 223, and the material of the control structure 225 can be polysilicon , the material of the lead-out structure 224 may be aluminum.
  • an IGBT drift region 1002 may be provided, that is, the IGBT drift region 1002 is located below the front device region 1001, and the IGBT drift region 1002 is connected to the front device region 1001, for example, to the cell region 10
  • the base region 103 is connected, connected with the first field ring region 211 of the field plate region 21, and connected with the second field ring region 221 of the field limit ring region 22.
  • the IGBT drift region 1002 can also be connected with The gate oxide region of the cell region 10 is connected.
  • the IGBT drift region 1002 may have a doping element of the first type.
  • the part of the IGBT drift region 1002 located on the side of the cell region 10 facing the second surface A2 may be referred to as the first drift region 111, and the part located on the side of the field plate region 21 facing the second surface A2.
  • Part of the IGBT drift region 1002 on one side of the two surfaces A2 can be marked as the second drift region 217
  • the part of the IGBT drift region 1002 on the side of the field limiting ring region 22 facing the second surface A2 can be marked as the third drift region 227 .
  • the first drift region 111 is located below the cellular region 10, and the projections of the first drift region 111 and the cellular region 10 on the first surface A1 coincide, the second drift region 217 is located below the field plate region 21, and the second drift The projections of the region 217 and the field plate region 21 on the first surface A1 coincide, the third drift region 227 is located below the field limit ring region 22 , and the projections of the third drift region 227 and the field limit ring region 22 on the first surface A1 coincide.
  • the cellular region 10 and the first drift region are located on the same side of the dotted line
  • the field plate region 21 and the second drift region 217 are located on the same side of the dotted line
  • the field-limiting ring region 22 and the third drift region 227 are located on the same side of the dotted line
  • the dotted line is introduced for the convenience of description, in fact, there may be no obvious boundaries among the first drift region 111 , the second drift region 217 and the third drift region 227 .
  • an IGBT buffer 1003 may be provided, that is, the IGBT buffer 1003 is located below the IGBT drift region 1002, and the IGBT buffer 1003 is connected to the IGBT drift region 1002.
  • the IGBT buffer 1003 has the first type of doping element, that is, the doping element is of the same type as that of the IGBT drift region 1002, and the concentration of the first type of doping element in the IGBT buffer zone 1003 is greater than that of the IGBT drift region 1002.
  • the concentration of doping elements which can act as a field stop layer, improves the performance of the IGBT.
  • Part of the IGBT buffer zone 1003 located on the side of the first drift region 111 facing the second surface A2 is denoted as the first buffer zone 121
  • part of the IGBT buffer zone 1003 located on the side of the second drift region 217 facing the second surface A2 is denoted as In the second buffer zone 218
  • the part of the IGBT buffer zone 1003 located on the side of the third drift region 227 facing the second surface A2 is denoted as the third buffer zone 228 .
  • the first buffer zone 121 is located below the first drift region 111, and the projections of the first buffer zone 121 and the cell region 10 on the first surface A1 coincide, the second buffer zone 218 is located below the second drift region 217, and the second buffer zone 121 is located below the second drift region 217, and The projections of the second buffer zone 218 and the field plate region 21 on the first surface A1 coincide, the third buffer zone 228 is located below the third drift region 227, and the projection of the third buffer zone 228 and the field limit ring region 22 on the first surface A1 Coincidentally, as shown in FIG.
  • the first buffer zone 121, the cell region 10 and the first drift region are located on the same side of the dotted line
  • the second buffer zone 218, the field plate region 21 and the second drift region 217 are located on the same side of the dotted line
  • the first The three buffer zones 228 , the field limit ring zone 22 and the third drift zone 227 are located on the same side of the dotted line.
  • An IGBT collector region 1004 may be provided on the side of the IGBT buffer 1003 facing the second surface A2, that is, the IGBT collector region 1004 is located below the IGBT buffer 1003, and the IGBT collector region 1004 is connected to the IGBT buffer 1003, and is used for connected to the collector, the IGBT collector region 1004 may have a second type of doping element, that is, the doping element is opposite to the type of the doping element of the IGBT buffer area 1003, and is located on the side of the first buffer area 121 facing the second surface A2 Part of the IGBT collector region 1004 of the IGBT can be marked as the cell collector region 131, and the part of the IGBT collector region 1004 located on the side of the terminal region 20 facing the second surface A2 can be marked as the terminal collector region.
  • the part of the IGBT collector region 1004 located on the side of the second buffer zone 218 facing the second surface A2 can be referred to as the field plate collector region 219, and the part of the IGBT collector located on the side of the third buffer region 228 facing the second surface A2 Region 1004 may be referred to as field limiting ring collector region 229 . That is, the cell collector region 131 is located below the first buffer zone 121, and the projections of the cell collector region 131 and the cell region 10 on the first surface A1 coincide, and the terminal collector region is located between the second buffer zone 218 and the third buffer zone 218.
  • the mid-plate collector region 219 of the terminal collector region is located below the second buffer zone 218, and the field plate collector region 219 and The projections of the field plate region 21 on the first surface A1 coincide, the field limiting ring collector region 229 is located below the third buffer zone 228, and the projections of the field limiting ring collector region 229 and the field limiting ring region 22 on the first surface A1 coincide , as shown in FIG.
  • the cell collector region 131, the first buffer region 121, the cell region 10 and the first drift region are located on the same side of the dotted line
  • the field plate collector region 219, the second buffer region 218, the field plate region 21 and the second drift region 217 are located on the same side of the dotted line
  • the field-limiting ring collector region 229, the third buffer zone 228, the field-limiting ring region 22 and the third drift region 227 are located on the same side of the dotted line, and in fact the cell collector region 131 , the field plate collector region 219 , and the field limiting ring collector region 229 may have no clear boundaries.
  • the IGBT buffer zone 1003 is arranged between the IGBT drift region 1002 and the IGBT collector region 1004, which can be used as a field stop layer, making the IGBT a field stop IGBT (field stop IGBT, FS-IGBT).
  • the function of the field stop layer has three points: 1) Cut off the forward electric field, compared with the structure without the field stop layer, the same thickness can withstand a larger voltage drop; 2) Reduce the thickness of the drift region to achieve thinning , reduce the conduction loss; 3) reduce the storage space for injecting minority carrier holes, and reduce the turn-off time and loss.
  • the doping element of the first type and the doping element of the second type are different types of doping elements, both of which are P-type and N-type respectively, and the semiconductor doped with the doping element of the first type has the first conductivity Type, a semiconductor doped with a second type of doping element has a second conductivity type, the first conductivity type and the second conductivity type are different conductivity types, the conductivity type of a semiconductor doped with a P-type doping element is P type, The conductivity type of the semiconductor doped with N-type doping elements is N-type.
  • the first conductivity type can be N-type
  • the second conductivity type can be P-type.
  • the conductivity type of the base region 103 is P
  • the first conductivity type can be P-type.
  • the conductivity type of the emitter region 104 is N
  • the conductivity type of the second emitter region 105 is P
  • the conductivity type of the first field ring region 211 and the second field ring region 221 is P type
  • the conductivity type of the IGBT drift region 1002 is N
  • the IGBT buffer The conductivity type of the region 1003 is N
  • the conductivity type of the IGBT collector region 1004 is P.
  • the above base region 103, first emitter region 104, second emitter region 105, first field ring region 211, second field ring region 221, IGBT drift region 1002, IGBT buffer region 1003, and IGBT collector region 1004 can be the base different positions, obtained by doping at different positions, the doping of the base region 103 can be lightly doped, denoted as P-, the doping of the first emitter region 104 and the second emitter region 105 can be heavily doped, respectively Expressed as N+ and P+, the doping of the IGBT drift region 1002 can be lightly doped, expressed as N-, and the doping of the IGBT buffer zone 1003 can be heavily doped, expressed as N+, and the doping level can be 1E12 ⁇ 1E13 .
  • the collector, the gate electrode, and the emitter 108 constitute three electrode ports of the IGBT.
  • a conduction channel will be formed on the surface of the base region 103 of the cell region, and the conduction channel is formed close to the boundary of the gate oxide region 107.
  • One side of the conduction channel is the first emitter region 104.
  • the other side of the track is the first drift region 111, electrons flow from the emitter 108 to the collector through the first drift region 111, due to the requirements of the forward bias of the collector and electrical neutrality, a large number of holes will be continuously injected from the collector In the first drift region 111 , some holes and electrons in the first drift region 111 form conductance modulation, and the remaining holes diffuse to the junction formed by the base region 103 and the first drift region 111 , and are finally collected by the emitter 108 .
  • the external performance of the IGBT is: there is a load current, and the IGBT is in the on state. It is precisely because of the conductance modulation effect during the forward conduction of the IGBT that the IGBT has the advantages of reduced forward conduction voltage, large on-state current, and low loss.
  • the static characteristic of the IGBT mainly includes a transfer characteristic and an output characteristic.
  • the transfer characteristic of the IGBT is used to describe the relationship between the IGBT collector current Ic and the gate-emitter voltage V GE (U GE ), referring to FIG. 4A , which is a transfer characteristic curve of an IGBT in the embodiment of the present application,
  • the abscissa is U GE
  • the ordinate is I C .
  • the turn-on voltage U GE(th) is the lowest gate-emitter voltage at which the IGBT can realize conductance modulation and turn on.
  • U GE is greater than the turn-on voltage, the IGBT turns on and has a positive IC in the direction, and IC increases gradually with U GE .
  • the output characteristic of the IGBT is also called the volt-ampere characteristic, which describes the relationship between the collector current I C and the collector-emitter voltage V CE (U CE ) when the gate-emitter voltage is used as a parameter.
  • V CE collector-emitter voltage
  • FIG 4B it is The output characteristic curve of an IGBT in the embodiment of the present application, the abscissa is U CE , and the ordinate is I C , and the distribution of different curves (1, 2, 3, 4, 5) corresponds to the sequentially increasing U GE , the output of the IGBT
  • the characteristics are divided into three regions: forward blocking region III, active region II and saturation region I. When the IGBT is in the forward blocking region, the IGBT is cut off.
  • IGBT When the IGBT is in the active region, I C increases with the increase of U CE and U GE , and the increase of I C with U CE is small. When the IGBT is in the saturation zone I, I C increases with the increase of U CE and U GE , and the increase of I C is relatively large.
  • V CE (U CE ) ⁇ 0 the IGBT is in the reverse blocking state. In the power electronic circuit, the IGBT works in the switching state, switching between the forward blocking region III and the saturation region I.
  • FIG. 5 it is a schematic diagram of a safe operating area of an IGBT provided by an embodiment of the present application, wherein the abscissa is the collector-emitter voltage V CE (U CE ), the ordinate is I C , and the safe operation area (safe operation area, SOA) reflects the ability of a power device to withstand a certain voltage and current at the same time.
  • the voltage and the maximum allowable voltage rise rate dV CE /dt are determined. It can be seen from the figure that under the action of repeated pulses, RBSOA is within the range of I C ⁇ 200V and V CE ⁇ 1200V, which means that the gate bias is zero. or turn-off transient when negative but present because the hole current does not disappear.
  • the IGBT also has certain performance parameters. During its use, it needs to be within the range of its minimum or maximum limit capacity or limit conditions. The IGBT cannot exceed the maximum and minimum ratings during its operation.
  • the main parameters are as follows:
  • BVCES Collector–Emitter blocking voltage
  • VGES Gate–Emitter voltage
  • Continuous collector current The maximum DC current allowed by the collector. Generally refers to the DC current value required when the junction temperature rises from the case temperature of 25°C to the maximum junction temperature of 150°C.
  • Peak collector repetitive current generally refers to the fact that under transient conditions, the IGBT can withstand a peak current higher than its maximum continuous current.
  • PD Maximum power dissipation
  • junction temperature (Tj) The allowable range of IGBT junction temperature during operation.
  • Collector–Emitter leakage current (ICES): When the gate and the emitter are short-circuited, the leakage current when a specified voltage and a specified temperature are applied between the collector and the emitter.
  • Gate–Emitter threshold voltage(VGE(th)) This parameter defines the gate-emitter voltage range within which the IGBT is turned on.
  • the threshold voltage has a negative temperature coefficient.
  • the threshold voltage increases linearly with the thickness of the gate oxide layer and is proportional to the square root of the doping concentration of the P-type base region. The fixed surface charge at the oxide-silicon interface and the mobile ions in the gate oxide lead to a shift in the threshold voltage.
  • VCE (SAT) Collector–Emitter saturation voltage
  • Input capacitance(Cies) The measured gate-emitter capacitance when the collector is shorted to the emitter.
  • the input capacitance is the sum of the gate-emitter and Miller capacitances.
  • the gate-emitter capacitance is much larger than the Miller capacitance.
  • Output capacitance (Coes): The capacitance between the collector and the emitter when the gate is short-circuited to the emitter has a typical PN junction voltage dependence.
  • Reverse transfer capacitance The Miller capacitance between the gate and the collector has a complex voltage dependence.
  • the IGBT with a field stop layer has the problem of poor withstand voltage characteristics.
  • the withstand voltage characteristics include the maximum reverse withstand voltage level of the IGBT, which can be reflected by BV CES .
  • BV CES is when the gate and emitter are short-circuited. Under the action of the specified collector and emitter current, the maximum reverse withstand voltage between the collector and emitter, the greater the maximum reverse withstand voltage, the better the withstand voltage characteristics of the device.
  • the maximum reverse withstand voltage As the current between the collector and emitter increases, the maximum reverse withstand voltage also increases. However, when the maximum reverse withstand voltage exceeds the avalanche withstand capacity of the device, BV CES will snap back. At this time, as the current increases, the maximum reverse withstand voltage decreases instead, that is, the BV negative resistance effect appears, and the device will generate a large leakage phenomenon in the device terminal area 20. As the current further increases, the device will enlarge The multiplier increases, and under this negative feedback, the device is damaged and eventually burns out.
  • FIG. 6 it is a schematic diagram of a negative resistance effect in the embodiment of the present application.
  • the abscissa is VCES, and the ordinate is ICES.
  • magnification of the PNP transistor is inversely related to the diffusion coefficient DE/base width WB/base implant dose NB of the emitter region, and is inversely related to the diffusion coefficient DB of the base region/the width WE of the emitter region/emission
  • the injection dose NE in the area is positively correlated, as shown in the following formula:
  • the emitter region of the PNP transistor can be used as the IGBT collector region, so the base region width can be reduced by reducing the implant dose of the emitter region of the PNP transistor, or increasing the implant dose and/or width of the base region of the PNP transistor, thereby reducing the PNP transistor
  • the magnification factor of the IGBT can be reduced by reducing the implantation dose of the IGBT collector region 1004, or increasing the doping concentration/width of the IGBT buffer region 1003, etc. to reduce the IGBT base region width, thereby reducing the IGBT magnification factor and suppressing the negative blocking purpose.
  • the adjustment of this scheme is an overall change to the device.
  • each cell region 10 can be divided into two and implanted with different hole concentrations, thereby reducing the leakage between the emitter 108 and the collector. , while reducing the turn-off loss and improving the product's RBSOA characteristics (reverse bias safe operating area).
  • the disadvantage of this technology is that although each cell has been partitioned in half, after the differential injection of holes, the saturation voltage drop of the device will be pulled up due to the thin P-type implantation in the other half of the cell area 10, which increases the static loss.
  • the IGBT collector region 1004 and the IGBT buffer region 1003 are doped with different types of doping elements, and a PN junction is formed at the interface between the two, and the IGBT collector region 1004 faces away from the surface of the IGBT buffer region 1003 and the PN junction The distance is taken as the junction depth of the PN junction.
  • the junction of the PN junction is deeply affected by the doping depth of the IGBT collector region 1004 and the thickness of the PN junction. When the doping depth of the IGBT collector region 1004 is constant, the thinner the PN junction , the deeper the junction depth of the PN junction, the easier it is for the PN junction to be broken down.
  • the structural characteristics of the IGBT make the junction depth of the terminal region 20 deeper than that of the cell region 10, and the electric field breakdown Points will be concentrated at the PN junction of the terminal region 20, and as shown in FIG. There are both horizontal and vertical breakdown paths in the area, which are easier to break down. Due to the intrinsic characteristics of the IGBT device, there are parasitic PNP transistors in the vertical direction, but the concentration of hole injection on the back directly affects the saturation voltage drop (VCESAT). Too concentrated hole injection on the back will make the PN junction thinner, and the transistor The increase in the magnification of the device will lead to aggravated snapback of the device, causing the negative resistance effect of BV breakdown, and ultimately affecting the performance of the device.
  • VCESAT saturation voltage drop
  • the area under the field plate region 21 is the area where the electric field intensity is the most concentrated, and the leakage current control for this area can effectively control the overall leakage current of the device. Therefore, according to the breakdown characteristics of the parasitic transistor, the implantation dose of the region under the field plate region 21 of the PNP can be adjusted to reduce the hole injection concentration of the field plate collector region 219, so that the second type of the cell collector region 131 The concentration of the dopant element is greater than the concentration of the second type of dopant element in the field plate collector region 219.
  • the injection dose of the P collector can reduce the magnification of the triode in the field plate region 21 in a targeted manner. That is to say, in the embodiment of the present application, by injecting holes with different concentrations into the cell collector region 131 and the field plate collector region 219, local leakage current control is performed, and the magnification factor is reduced in a targeted manner, so that the Under the premise of affecting the saturation voltage drop level of the device, the withstand voltage capability of the device is improved, the BV negative resistance phenomenon is eliminated, and the reliability of the device is improved.
  • the terminal collector region may have a uniform concentration of the second type of dopant element, that is, the concentration of the second type of dopant element in the field plate collector region 219 is equal to that of the second type of dopant element in the field limiting ring collector region 229.
  • the concentration of the dopant element, the concentration of the second type of dopant element in the cell collector region 131 is greater than the concentration of the second type of dopant element in the field plate collector region 219, and at the same time greater than the concentration of the field limit ring collector region
  • the concentration of the second type of dopant element at 229 is a schematic structural diagram of another IGBT provided by the embodiment of the present application.
  • the electric field distribution in the device can be used
  • the solid line of the arrow indicates that when the concentration of the second type dopant element in the field plate collector region 219 and the field limiting ring collector region 229 is low, the PN between the field plate collector region 219 and the second buffer zone 218 The lateral breakdown path of the region where the junction is located, the field limiting ring collector region 229 and the third buffer zone 228 is suppressed, and it is less prone to breakdown.
  • the field plate collector region 219 and the field plate When the concentration of the second type of dopant element in the confining ring collector region 229 is low, it is beneficial to increase the thickness of the PN junction between the field plate collector region 219 and the first buffer region 121, and the field confining ring collector region The thickness of the PN junction between 229 and the second buffer zone 218 reduces the junction depth of the PN junction between the terminal collector region and the IGBT buffer zone 1003, making the PN junction there less prone to breakdown.
  • the doping of the cell collector region 131 is heavily doped, and the doping level is 1E13 ⁇ 1E14cm -3 (that is, 10 12 ⁇ 10 14 cm -3 ), the field plate collector region 219 and the field limit ring collector region
  • the doping of 229 is light doping, and the doping level is 1E12-1E13 (ie, 10 12 -10 13 cm -3 ).
  • the terminal collector region may have a non-uniform concentration of the second type of doping element, for example, the concentration of the second type of doping element in the field plate collector region 219 is smaller than the second concentration of the field limiting ring collector region 229.
  • the concentration of the dopant element of the type, and the concentration of the dopant element of the second type in the cell collector region 131 is greater than the concentration of the dopant element of the second type in the field plate collector region 219, in addition, the cell collector region
  • the concentration of the second type of doping element in 131 may be equal to the concentration of the second type of doping element in the field confining ring collector region 229, or may be greater than the concentration of the second type of doping element in the field confining ring collector region 229. concentration.
  • the electric field distribution in the device can be represented by a solid line with arrows, and the field plate collector region 219
  • the concentration of the second type of doping element is low, the lateral breakdown path of the region where the PN junction between the field plate collector region 219 and the second buffer zone 218 is located is suppressed, and it is less likely to break down, correspondingly
  • the concentration of the second type dopant element in the field plate collector region 219 is low, it is beneficial to increase the width of the PN junction between the field plate collector region 219 and the first buffer region 121, and reduce the junction of the PN junction.
  • the doping of the cell collector region 131 and the field-limiting ring collector region 229 is heavily doped, and the concentration of the second type of doping element is on the order of 1E13-1E14 cm -3 (that is, 10 12 -10 14 cm -3 ), the doping of the field plate collector region 219 is lightly doped, and the magnitude of the second type of doping element is 1E12 ⁇ 1E13 cm ⁇ 3 (ie, 10 12 ⁇ 10 13 cm ⁇ 3 ).
  • An embodiment of the present application provides an insulated gate bipolar transistor IGBT, which includes an opposite first surface and a second surface, and has a front device region and an IGBT drift region connected in sequence in the direction from the first surface to the second surface , IGBT buffer area and IGBT collector area, wherein the front device area may include a cell area and a terminal area surrounding the cell area, and the terminal area includes a field plate area surrounding the cell area and a field limit ring area surrounding the field plate area, There is a first type of doping element in the IGBT drift region, there is a first type of doping element in the IGBT buffer, and the concentration of the first type of doping element in the IGBT buffer is greater than that of the first type in the IGBT drift region The concentration of doping elements, the IGBT collector region includes the cell collector region, the field plate collector region and the field limit ring collector region, the cell collector region coincides with the projection of the cell region on the first surface, and the field plate set The projection of the electrode area and the field
  • the embodiment of the present application also provides a method for manufacturing an IGBT.
  • FIG. 9 it is a flowchart of a method for manufacturing an IGBT in the embodiment of the present application.
  • the method may include :
  • the IGBT may include opposite first surface A1 and second surface A2, wherein the first surface A1 may serve as the front side of the chip, and the second surface A2 may serve as the back side of the chip.
  • the substrate can be a semiconductor substrate, and doping in the substrate can result in a P-type semiconductor or an N-type semiconductor.
  • the substrate can have a relatively large thickness, and different positions are used for being doped to form different doping structures in the IGBT.
  • the substrate may have the first type of doping element, and the substrate corresponds to the regions corresponding to the subsequent IGBT buffer region 1003 and the IGBT collector region 1004 , but no corresponding doping has been performed.
  • a front device region 1001 can be formed on the first surface of the substrate.
  • the front device region 1001 can include a cell region 10 and a termination region 20 surrounding the cell region 10.
  • the termination region 20 can realize the function of chip plane electric field voltage division.
  • the termination region 20 may include a field plate region 21 and a field limit ring region 22 , wherein the field plate region 21 surrounds the cell region 10 , and the field limit ring region 22 surrounds the field plate region 21 .
  • the cell region 10 may include a base region, a gate region 106 and a gate oxide region 107, the base region includes a base region 103, a first emitter region 104 and a second emitter region 105, the first The emitter region 104 and the second emitter region 105 are located on the side of the base region away from the second surface A2, wherein the first emitter region 104 has a doping element of the first type, and the second emitter region 105 has a dopant element of the second type.
  • the base region 103 has a second type of doping element
  • the first emitter region 104 is used to connect the emitter 108
  • the concentration of the first type of doping element in the second emitter region is greater than that of the first type of doping element in the base region 103
  • the concentration of the type of dopant element is not limited to that of the first type of dopant element.
  • the gate region 106 and the gate oxide region 107 may be located on the side away from the second surface A2 outside the base region, and the gate oxide region 107 is connected to the first emitter region 104 and the base region 103 at the same time, for example, the gate oxide region 107 is located on The first emitter region 104 and the base region 103 are away from the side of the second surface A2, that is, above the base region, and the gate region 106 is located on the side of the gate oxide region 107 away from the second surface A2, that is, the gate oxide region 107 Above, the gate region 106 is used to connect the gate electrode, serving as the control region of the device.
  • the base region is formed on the first surface of the substrate, which may be specifically, the base region 103 is obtained by doping the part of the substrate away from the second surface A2 with a doping element of the second type; in the base region 103 away from the second The first part of the surface A2 is doped with the doping element of the first type to obtain the first emitter region 104, and the second part of the base region 103 away from the second surface A2 is doped with the doping element of the second type to obtain the first emission region 104.
  • Two emission regions 105 so that the concentration of the doping element of the first type in the second emission region 105 is greater than the doping element of the first type in the remaining part of the base region 103 except the first emission region 104 and the second emission region 105 concentration.
  • Forming a gate region 106 and a gate oxide region 107 on the first surface of the substrate may be specifically, forming a gate oxide and a gate structure on the side of the substrate away from the second surface, where the gate oxide is located in The gate oxide region 107 , the region where the gate structure is located is the gate region 106 .
  • the gate oxide and the gate structure may be formed by a deposition process.
  • the gate oxide region is formed before the gate region 106
  • the base region can be formed before the gate oxide region 107 or after the gate region 106 .
  • the cell region 10 may include a base region, and the base region includes a base region 103, a gate region 106, a gate oxide region 107, a first emitter region 104, and a second emitter region 105.
  • the electrode region, the gate oxide region, the first emitter region and the second emitter region are located on the side of the base region away from the second surface A2, wherein the first emitter region 104 has a doping element of the first type, and the second emitter region 105 has a doping element of the second type, the base region 103 has a doping element of the second type, the first emitter region 104 is used to connect the emitter 108, and the concentration of the doping element of the first type in the second emitter region greater than the concentration of the first type of dopant element in the base region 103 .
  • the gate region 106 and the gate oxide region 107 may be located in the base region, the gate oxide region 107 surrounds the gate region 106 in the base region, and the gate oxide region 107 is simultaneously connected to the first emitter region 104 and the base region 103
  • the sidewall of the gate oxide region 107 is connected to the first emitter region 104 on the side away from the second surface A2, and the other part of the sidewall is connected to the base region 103, and the gate region 106 is used to connect the gate electrode, as the device control area.
  • the formation of the base region on the first surface of the substrate may be specifically, doping the part of the substrate away from the second surface A2 with the second type of doping element to obtain the base region 103, and in the base region 103 away from the second surface A2
  • the first part of the surface A2 is doped with the doping element of the first type to obtain the first emitter region 104
  • the second part of the base region 103 away from the second surface A2 is doped with the doping element of the second type to obtain the first emission region 104.
  • Two emission regions 105, the concentration of the doping element of the first type in the second emission region 105 is greater than that of the doping element of the first type in the remaining part of the base region 103 except the first emission region 104 and the second emission region 105 concentration.
  • Forming a gate region 106 and a gate oxide region 107 on the first surface of the substrate may be specifically, etching a third part of the substrate away from the second surface to obtain a gate hole, and forming a gate oxide and a gate oxide in the gate hole.
  • the region where the gate oxide is located is the gate oxide region 107
  • the region where the gate structure is located is the gate region 106 .
  • the gate oxide region is formed before the gate region 106
  • the base region can be formed before the gate oxide region 107 or after the gate region 106 .
  • the first emission region 104 and the second emission region 105 may be covered with a cellular dielectric layer, and the cellular dielectric layer may include a first dielectric layer 101 and a second dielectric layer 102 thereon, the first dielectric layer 101 covers the first emitter region 104 and the second emitter region 105, the first dielectric layer 101 may be an oxide isolation (Local Oxidation of Silicon, LOCOS) layer, and the material of the second dielectric layer 102 may be silicon oxide.
  • LOCOS Low Oxidation of Silicon
  • the first dielectric layer 101 and the second dielectric layer 102 can be etched to form an etching hole, and a conductor material is formed in the etching hole, and the conductor material can be used as the emitter 108 .
  • the field plate region 21 may include a first field ring region 211, the first field ring region 211 may be connected to the emitter 108, the first field ring region 211 has a second type of doping element, and the first field ring region 211 is provided with There is a field ring dielectric layer.
  • the field ring dielectric layer includes a third dielectric layer 212 and a fourth dielectric layer 213 thereon.
  • the third dielectric layer 212 can be an oxide isolation layer, and the material of the fourth dielectric layer 213 can be silicon oxide.
  • a gate bus line 214 may be provided on the fourth dielectric layer 213, and the gate bus line 214 may be connected to the gate electrode of the cell area 10;
  • the field limiting ring area 22 may include a plurality of second field ring areas 221, and the second field ring area 221 is provided with a field-limiting ring dielectric layer, the field-limiting ring dielectric layer may include a fifth dielectric layer 222 and a sixth dielectric layer 223 thereon, the fifth dielectric layer 222 may be an oxide isolation layer, and the sixth dielectric layer 223
  • the material can be silicon oxide, and the fifth dielectric layer 222 is also provided with a control structure 225 and a lead-out structure 224 on the control structure.
  • the lead-out structure 224 can penetrate the sixth dielectric layer 223, and the material of the control structure 225 can be polysilicon.
  • the lead-out structure 224 The material can be aluminum.
  • the doping element of the first type and the doping element of the second type are different types of doping elements, both of which are P-type and N-type respectively, and the semiconductor doped with the doping element of the first type has the first conductivity Type, a semiconductor doped with a second type of doping element has a second conductivity type, the first conductivity type and the second conductivity type are different conductivity types, the conductivity type of a semiconductor doped with a P-type doping element is P type, The conductivity type of the semiconductor doped with N-type doping elements is N-type.
  • the first conductivity type can be N-type
  • the second conductivity type can be P-type.
  • the conductivity type of the base region 103 is P
  • the first conductivity type can be P-type.
  • the conductivity type of the emitter region 104 is N
  • the conductivity type of the second emitter region 105 is P
  • the conductivity type of the first field ring region 211 and the second field ring region 221 is P type.
  • the base region 103, the first emitter region 104, the second emitter region 105, the first field ring region 211, and the second field ring region 221 above can be different positions of the substrate, obtained by doping different positions, and the base region 103
  • the doping can be lightly doped, represented as P-, and the doping of the first emitter region 104 and the second emitter region 105 can be heavily doped, represented as N+ and P+ respectively.
  • the substrate After forming the front device region 1001, the substrate can be thinned from the second surface, and the thickness of the substrate after thinning is reduced, usually 80-120 micrometers (um).
  • the thickness of the substrate after thinning and doping The thickness of the structure is related, so it is related to the BV withstand voltage of the device, and those skilled in the art can set the thickness according to the actual situation.
  • the substrate After forming the front device region 1001, the substrate can be doped with the first type of doping element from the second surface of the substrate to obtain the IGBT buffer zone 1003, and the substrate between the front device region 1001 and the IGBT buffer zone 1003 is used as an IGBT Drift Zone 1002.
  • the IGBT drift region 1002 is located on the side of the front device region 1001 facing the second surface, that is, the IGBT drift region 1002 is located below the front device region 1001, and the IGBT drift region 1002 is connected to the front device region 1001, for example, to the base region of the cell region 10 103 connection, connected with the first field ring region 211 of the field plate region 21, connected with the second field ring region 221 of the field limit ring region 22, in the trench gate IGBT, the IGBT drift region 1002 can also be connected with the cell region 10 gate oxide connections.
  • the IGBT drift region 1002 may have a doping element of the first type, and the part of the IGBT drift region 1002 located on the side of the cell region 10 facing the second surface A2 may be referred to as the first drift region 111, and the part located on the side of the field plate region 21 facing the second surface A2 Part of the IGBT drift region 1002 on one side of the surface A2 can be marked as the second drift region 217 , and the part of the IGBT drift region 1002 on the side of the field limiting ring region 22 facing the second surface A2 can be marked as the third drift region 227 .
  • the first drift region 111 is located below the cellular region 10, and the projections of the first drift region 111 and the cellular region 10 on the first surface A1 coincide, the second drift region 217 is located below the field plate region 21, and the second drift The projections of the region 217 and the field plate region 21 on the first surface A1 coincide, the third drift region 227 is located below the field limit ring region 22 , and the projections of the third drift region 227 and the field limit ring region 22 on the first surface A1 coincide.
  • the first drift region 111, the second drift region 217 and the third drift region 227 have the same doping concentration, and the IGBT buffer region 1003 is formed by the same doping process, and may have the same doping depth at different positions, Therefore, the first drift region 111 , the second drift region 217 and the third drift region 227 have the same material and size.
  • the IGBT buffer 1003 is located on the side of the IGBT drift region 1002 facing the second surface A2, that is, the IGBT buffer 1003 is located below the IGBT drift region 1002, the IGBT buffer 1003 is connected to the IGBT drift region 1002, and the IGBT buffer 1003 has a first type of doping element, that is, the doping element is of the same type as the doping element of the IGBT drift region 1002, and the concentration of the first type of doping element in the IGBT buffer zone 1003 is greater than that of the first type of doping element in the IGBT drift region 1002
  • concentration of elements which can act as a field stop layer, improves the performance of the IGBT.
  • Part of the IGBT buffer zone 1003 located on the side of the first drift region 111 facing the second surface A2 is denoted as the first buffer zone 121
  • part of the IGBT buffer zone 1003 located on the side of the second drift region 217 facing the second surface A2 is denoted as In the second buffer zone 218
  • the part of the IGBT buffer zone 1003 located on the side of the third drift region 227 facing the second surface A2 is denoted as the third buffer zone 228 .
  • the first buffer zone 121 is located below the first drift region 111, and the projections of the first buffer zone 121 and the cell region 10 on the first surface A1 coincide, the second buffer zone 218 is located below the second drift region 217, and the second buffer zone 121 is located below the second drift region 217, and The projections of the second buffer zone 218 and the field plate region 21 on the first surface A1 coincide, the third buffer zone 228 is located below the third drift region 227, and the projection of the third buffer zone 228 and the field limit ring region 22 on the first surface A1 coincide.
  • the first buffer zone 121 , the second buffer zone 218 and the third buffer zone 228 have the same doping concentration, are formed by the same doping process, may have the same doping depth, and therefore have the same material and size.
  • the first doping of the second type of doping element is performed to obtain the IGBT collector region 1004, and the first surface A1 and the second surface A2 are opposite surfaces, for example When the first surface A1 is the upper surface, the second surface A2 may be the lower surface.
  • the IGBT collector region 1004 is located on the side of the IGBT buffer 1003 facing the second surface A2, that is, the IGBT collector region 1004 is located below the IGBT buffer 1003, and the IGBT collector region 1004 is connected to the IGBT buffer 1003 and is used to connect the collector , the IGBT collector region 1004 may have a second type of doping element, that is, the type of the doping element is opposite to that of the IGBT buffer area 1003, and the part of the IGBT located on the side of the first buffer area 121 facing the second surface A2
  • the collector region 1004 can be marked as the cell collector region 131, and the part of the IGBT collector region 1004 located on the side of the terminal region 20 facing the second surface A2 can be marked as the terminal collector region.
  • the part of the IGBT collector region 1004 on the side of the buffer zone 218 facing the second surface A2 can be denoted as the field plate collector region 219, and the part of the IGBT collector region 1004 located on the side of the third buffer region 228 facing the second surface A2 can be Denoted as field limiting ring collector region 229 .
  • the cell collector region 131 is located below the first buffer zone 121, and the projections of the cell collector region 131 and the cell region 10 on the first surface A1 coincide, and the terminal collector region is located between the second buffer zone 218 and the third buffer zone 218.
  • the mid-plate collector region 219 of the terminal collector region is located below the second buffer zone 218, and the field plate collector region 219 and The projections of the field plate region 21 on the first surface A1 coincide, the field limiting ring collector region 229 is located below the third buffer zone 228, and the projections of the field limiting ring collector region 229 and the field limiting ring region 22 on the first surface A1 coincide .
  • the cell collector region 131, the field plate collector region 219 and the field limiting ring collector region 229 have the same doping concentration, and are formed by the same doping process, and may have the same doping depth and therefore have the same material and dimensions.
  • the first conductivity type can be N type
  • the second conductivity type can be P type
  • the conductivity type of the base region 103 is P
  • the conductivity type of the first emitter region 104 is N
  • the conductivity type of the second emitter region 105 is P
  • the conductivity type of the first field ring region 211 and the second field ring region 221 is P type
  • the conductivity type of the IGBT drift region 1002 is N
  • the conductivity type of the IGBT buffer zone 1003 is N
  • the above base region 103, first emitter region 104, second emitter region 105, first field ring region 211, second field ring region 221, IGBT drift region 1002, IGBT buffer region 1003, and IGBT collector region 1004 can be the base different positions, obtained by doping at different positions, the doping of the base region 103 can be lightly doped, denoted as P-, the doping of the first emitter region 104 and the second emitter region 105 can be heavily doped, respectively Expressed as N+ and P+, the doping of the IGBT drift region 1002 can be lightly doped, expressed as N-, and the doping of the IGBT buffer zone 1003 can be heavily doped, expressed as N+, and the doping level can be 1E12 ⁇ 1E13 .
  • the field plate collector region 219 can be shielded, and the IGBT collector region 1004 is doped with the second type.
  • the second doping of heteroelements so that the concentration of the second type of doping element in the cell collector region 131 is greater than the concentration of the second type of doping element in the field plate collector region 219, through the amplification of the above-mentioned PNP transistor.
  • the functional relationship between the multiple and the emitter region and the base region shows that reducing the implant dose to the P collector directly under the field plate region 21 can reduce the magnification of the transistor in the field plate region 21 in a targeted manner.
  • the terminal collector region may have a uniform concentration of the second type of dopant element, that is, the concentration of the second type of dopant element in the field plate collector region 219 is equal to that of the second type of dopant element in the field limiting ring collector region 229.
  • the concentration of the dopant element, the concentration of the second type of dopant element in the cell collector region 131 is greater than the concentration of the second type of dopant element in the field plate collector region 219, and at the same time greater than the concentration of the field limit ring collector region
  • the concentration of the second type of doping element at 229 as shown in FIG.
  • the collector region is doped for the second time with the doping element of the second type, so that the concentration of the doping element of the second type in the cell collector region 131 is greater than that of the doping element of the second type in the field plate collector region 219
  • the concentration of the dopant element can be specifically, shielding the field plate collector region 219 and the field limit ring collector region 229, and performing the second doping of the second type of dopant element on the IGBT collector region 1004, so that the element
  • the concentration of the second type of doping element in the cell collector region 131 is greater than the concentration of the second type of doping element in the field plate collector region 219 and greater than the concentration of the second type of doping element in the field limit ring collector region 229
  • the concentration of the second type of doping element in the field plate collector region 219 is equal to the concentration of the second type of doping
  • the terminal collector region may have a non-uniform concentration of the second type of doping element, for example, the concentration of the second type of doping element in the field plate collector region 219 is smaller than the second concentration of the field limiting ring collector region 229.
  • the concentration of the dopant element of the same type, and the concentration of the dopant element of the second type in the cell collector region 131 is greater than the concentration of the dopant element of the second type in the field plate collector region 219, and can be equal to the field limit ring set
  • the concentration of the second type of doping element in the electrode region 229 as shown in FIG.
  • the concentration of the second type of doping element is greater than the concentration of the second type of doping element in the field plate region, and the concentration of the second type of doping element in the field limiting ring collector region 229 is greater than that of the second type of doping element in the field plate collector region 219.
  • the concentration of the type of dopant element This is because the area under the field plate region 21 is the area where the electric field intensity is the most concentrated, and the leakage current control for this area can effectively control the overall leakage current of the device.
  • the doping concentration of the second doping is greater than that of the first doping.
  • the first doping can be light doping
  • the second doping can be heavy doping.
  • the field plate collector region 219 can be shielded by a photomask, and the same photomask can also be used to shield the field-limiting ring collector region 229 while shielding the field plate collector region 219 .
  • a collector 240 can be formed on the second surface, and the material of the collector 240 can be a case with better conductivity, such as a metal material, and the collector 240 and the IGBT collector
  • the electrode area 1004 is connected, as shown in FIG. 13 and FIG. 14 .
  • An embodiment of the present application provides a method for manufacturing an insulated gate bipolar transistor IGBT.
  • a front device region is formed on the first surface of the substrate.
  • the front device region may include a cell region and a terminal region surrounding the cell region.
  • the terminal region includes a surrounding The field plate region of the cell region and the field-limiting ring region surrounding the field plate region, the substrate has a first type of doping element, and the part of the substrate facing the second surface is doped with the first type of doping element to obtain
  • the IGBT buffer, the substrate between the front device region and the IGBT buffer serves as the IGBT drift region, and the concentration of the first type of doping element in the IGBT buffer is greater than the concentration of the first type of doping element in the IGBT drift region, in the IGBT
  • the part of the drift region facing the second surface is doped with the second type of doping element for the first time to obtain the IGBT collector region.
  • the IGBT collector region includes the cell collector region, the field plate collector region and the field limiting ring Collector region, shielding the field plate collector region, doping the IGBT collector region with the second type of doping element for the second time, the concentration of the second type of doping element in the cell collector region is equal to the field plate
  • concentration of the second type of doping element in the collector area is higher than that of the cell area, the field plate area is often easier to break down, so the concentration of the second type of doping element in the cell collector area can be designed to be greater than that of the field plate set
  • the concentration of the second type of doping element in the electrode region that is to say, the part of the collector region opposite to the cell region has a larger concentration of the second type of doping element, while the part of the collector region opposite to the field plate region
  • the electrode area has a smaller concentration of the second type of doping elements, which effectively reduces the magnification of the parasitic transistor in the field plate area, reduces the leakage value of the device when it is subjected to
  • the embodiment of the present application also provides an electronic device, including a circuit board and the IGBT connected to the circuit board.
  • the electronic device may be a power converter, and the power converter includes an inverter, a rectifier, and the like.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本申请公开了一种IGBT及其制造方法，在从第一表面向第二表面的方向上，IGBT具有依次连接的正面器件区、IGBT漂移区、IGBT缓冲区和IGBT集电极区，正面器件区可以包括元胞区、场板区和场限环区，IGBT漂移区中具有第一类型的掺杂元素，IGBT缓冲区中具有第一类型的掺杂元素，IGBT缓冲区中的第一类型的掺杂元素的浓度大于IGBT漂移区中的第一类型的掺杂元素的浓度，IGBT集电极区包括元胞集电极区、场板集电极区和场限环集电极区，IGBT集电极区中具有第二类型的掺杂元素，元胞集电极区的第二类型的掺杂元素的浓度大于场板集电极区的第二类型的掺杂元素的浓度，有效减少场板区寄生三极管的放大倍数，改善器件的耐压特性以及安全工作区特性，提高器件整体的工作性能。

Description

一种绝缘栅双极晶体管及其制造方法、电子设备
本申请要求于2021年10月30日提交中国专利局、申请号为202111278434.4、发明名称为“一种绝缘栅双极晶体管及其制造方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路制造领域，尤其涉及一种绝缘栅双极晶体管及其制造方法、电子设备。
背景技术
绝缘栅双极型晶体管(insulated gate bipolar transistor，IGBT)，是由双极型晶体管(bipolar junction transistor，BJT)和绝缘栅型场效应管(metal-oxide-semiconductor field-effect Transistor，MOSFET)组成的复合全控型电压驱动式功能半导体器件。
其中，BJT饱和压降低，载流密度大，但驱动电流较大；MOSFET驱动功率很小，开关速度快，但导通压降大，载流密度小。IGBT集MOSFET和BJT的优点于一体，即具有输入阻抗高、开关速度快、热稳定性好，且驱动电路简单，驱动电流小，又具有饱和压降低，耐压高及承受电流大的优点。因此，IGBT非常适合应用于直流电压为600V及以上的变流系统如交流电机、变频器、开关电源、照明电路、牵引传动等领域。
然而现有的IGBT存在耐压特性较差的问题，耐压特性包括IGBT的最大承受反向耐压的水平，可以利用BVCES(collector–emitter blocking voltage)来体现，BVCES是栅极与发射极间短路时，在指定的集电极和发射极的电流作用下，集电极与发射极间能承受的最大反向耐压，最大反向耐压越大，器件的耐压特性越好。
发明内容
有鉴于此，本申请实施例提供了一种绝缘栅双极晶体管及其制造方法、电子设备，提高器件的耐压特性。
本申请实施例的第一方面，提供了一种绝缘栅双极晶体管IGBT，包括相对的第一表面和第二表面，在从第一表面向第二表面的方向上，具有依次连接的正面器件区、IGBT漂移区、IGBT缓冲区和IGBT集电极区，其中正面器件区可以包括元胞区和环绕元胞区的终端区，终端区包括环绕元胞区的场板区和环绕场板区的场限环区，IGBT漂移区中具有第一类型的掺杂元素，IGBT缓冲区中具有第一类型的掺杂元素，IGBT缓冲区中的第一类型的掺杂元素的浓度大于IGBT漂移区中的第一类型的掺杂元素的浓度，IGBT集电极区包括元胞集电极区、场板集电极区和场限环集电极区，元胞集电极区与元胞区在第一表面的投影重合，场板集电极区与场板区在第一表面的投影重合，场限环集电极区与场限环区在第一表面的投影重合，IGBT集电极区中具有第二类型的掺杂元素，在元胞集电极区的第二类型的掺杂元素的浓度等于场板集电极区的第二类型的掺杂元素的浓度时，场板区往往比元胞区更容易击穿，因此可以设计元胞集电极区的第二类型的掺杂元素的浓度大于场板集电极区 的第二类型的掺杂元素的浓度，也就是说，与元胞区相对的部分集电极区具有较大的第二类型的掺杂元素的浓度，而与场板区相对的部分集电极区具有较小的第二类型的掺杂元素的浓度，有效减少场板区寄生三极管的放大倍数，减少器件在承受反向耐压时的漏电值，改善器件的耐压特性以及安全工作区特性，加强器件的鲁棒性，提高器件整体的工作性能。
在一些可能的实施方式中，所述元胞集电极区为重掺杂区，所述场板集电极区为轻掺杂区。
本申请实施例中，元胞集电极区可以为重掺杂区，场板集电极区可以为轻掺杂区，场板集电极区的第二类型的掺杂元素的浓度得到有效降低，因此能够有效降低场板区的三极管的放大系数，提高器件的耐压特性。
在一些可能的实施方式中，所述元胞集电极区中的第二类型的掺杂元素的浓度大于所述场限环集电极区中的第二类型的掺杂元素的浓度。
本申请实施例中，元胞集电极区的第二类型的掺杂元素的浓度在大于场板集电极区的第二类型的掺杂元素的浓度的基础上，还可以大于场限环集电极区的第二类型的掺杂元素的浓度，这样有效降低终端区的三极管的放大系数，提高器件的耐压特性。
在一些可能的实施方式中，所述元胞集电极区为重掺杂区，所述场限环集电极区为轻掺杂区。
本申请实施例中，可以令场限环集电极区为轻掺杂区，使场限环集电极区的第二类型的掺杂元素的浓度得到有效降低，因此能够有效降低场限环区的三极管的放大系数，提高器件的耐压特性。
在一些可能的实施方式中，所述IGBT为平面栅IGBT；
所述元胞区包括基体区、栅极区和栅极氧化区，所述基体区包括基区、第一发射区和第二发射区，所述第一发射区和所述第二发射区位于所述基体区中背离所述第二表面的一侧；所述第一发射区中具有第一类型的掺杂元素，所述第二发射区中具有第二类型的掺杂元素，所述基区具有第二类型的掺杂元素；所述第一发射区用于连接发射极；所述第二发射区中的第二类型的掺杂元素的浓度大于所述基区中的第二类型的掺杂元素的浓度；所述栅极区用于连接栅电极，所述栅极区和所述栅极氧化区位于所述基体区之外背离所述第二表面的一侧；所述IGBT集电极区用于连接集电极。
本申请实施例中，IGBT可以为平面栅IGBT，栅极区和栅极氧化区设置在基体区外部，利于实现器件多样性。
在一些可能的实施方式中，所述IGBT为沟槽栅IGBT；
所述元胞区包括基体区，所述基体区包括基区、栅极区、栅极氧化区、第一发射区和第二发射区，所述栅极区、所述栅极氧化区、所述第一发射区和所述第二发射区位于所述基体区中背离所述第二表面的一侧；所述第一发射区中具有第一类型的掺杂元素，所述第二发射区中具有第二类型的掺杂元素，所述基区具有第二类型的掺杂元素；所述第一发射区用于连接发射极；所述第二发射区中的第二类型的掺杂元素的浓度大于所述基区中的第二类型的掺杂元素的浓度；所述栅极区用于连接栅电极，所述栅极氧化区在所述基体区中包围所述栅极区；所述IGBT集电极区用于连接集电极。
本申请实施例中，IGBT可以为沟槽栅IGBT，栅极区和栅极氧化区设置在基体区内部，利于实现器件多样性。
在一些可能的实施方式中，所述场板区包括第一场环区、栅极总线和位于所述第一场环区与所述栅极总线之间的场板介质层；所述第一场环区中具有第二类型的掺杂元素，用于连接发射极；所述栅极总线用于连接栅电极；
所述场限环区包括第二场环区、控制结构和位于所述第二场环区与所述控制结构之间的场限环介质层；所述第二场环区中具有第二类型的掺杂元素。
本申请实施例中，场板区可以包括第一场环区、栅极总线和场板介质层，场限环区可以包括第二场环区、控制结构和场限环介质层，从而有效为IGBT实现平面电场分压的功能。
在一些可能的实施方式中，所述第一类型为N型，所述第二类型为P型。
本申请实施例中，第一类型可以为N型，第二类型可以为P型，使器件有更低的驱动能耗。
本申请实施例第二方面，提供了一种绝缘栅双极晶体管IGBT的制造方法，包括：
在基底的第一表面形成正面器件区；所述基底中具有第一类型的掺杂元素；所述正面器件区包括元胞区和环绕所述元胞区的终端区；所述终端区包括环绕所述元胞区的场板区，以及环绕所述场板区的场限环区；
在所述基底中朝向第二表面的部分进行第一类型的掺杂元素的掺杂，得到IGBT缓冲区；所述IGBT缓冲区中的第一类型的掺杂元素的浓度大于所述基底中的第一类型的掺杂元素的浓度，所述正面器件区和所述IGBT缓冲区之间的基底作为IGBT漂移区；所述第一表面和所述第二表面为相对的表面；
在所述IGBT漂移区中朝向所述第二表面的部分进行第二类型的掺杂元素的第一次掺杂，得到IGBT集电极区；所述IGBT集电极区包括元胞集电极区、场板集电极区和场限环集电极区，所述元胞集电极区与所述元胞区在所述第一表面的投影重合，所述场板集电极区与所述场板区在所述第一表面的投影重合，所述场限环集电极区与所述场限环区在所述第一表面的投影重合；所述第一类型为P型或N型，所述第二类型为P型或N型，所述第一类型和所述第二类型不同；
遮挡所述场板集电极区，对所述IGBT集电极区进行第二类型的掺杂元素的第二次掺杂，以使所述元胞集电极区中的第二类型的掺杂元素的浓度大于所述场板集电极区中的第二类型的掺杂元素的浓度。
在一些可能的实施方式中，遮挡所述场板集电极区，对所述IGBT集电极区进行第二类型的掺杂元素的第二次掺杂，以使所述元胞集电极区中的第二类型的掺杂元素的浓度大于所述场板集电极区中的第二类型的掺杂元素的浓度，包括：
遮挡所述场板集电极区和所述场限环集电极区，对所述IGBT集电极区进行第二类型的掺杂元素的第二次掺杂，以使所述元胞集电极区中的第二类型的掺杂元素的浓度大于所述场板集电极区中的第二类型的掺杂元素的浓度，且大于所述场限环集电极区中的第二类 型的掺杂元素的浓度。
在一些可能的实施方式中，所述第一次掺杂为轻掺杂，所述第二次掺杂为重掺杂。
在一些可能的实施方式中，所述IGBT为平面栅IGBT，则所述元胞区包括基体区、栅极区和栅极氧化区；所述基体区中包括基区、第一发射区和第二发射区，所述第一发射区和所述第二发射区位于所述基体区中背离所述第二表面的一侧；所述第一发射区用于连接发射极，所述栅极区用于连接栅电极，所述IGBT集电极区用于连接集电极；所述栅极区和所述栅极氧化区位于所述基底之外背离所述第二表面的一侧；
其中，在基底的第一表面形成基体区，包括：在所述基底中背离所述第二表面的部分进行第二类型的掺杂元素的掺杂得到基区；在所述基区中背离第二表面的第一部分进行第一类型的掺杂元素的掺杂得到第一发射区，在所述基区中背离第二表面的第二部分进行第二类型的掺杂元素的掺杂得到第二发射区。
在一些可能的实施方式中，所述IGBT为沟槽栅IGBT，所述元胞区包括基体区；所述基体区中包括基区、栅极区、栅极氧化区、第一发射区和第二发射区，所述栅极区、所述栅极氧化区、所述第一发射区和所述第二发射区位于所述基体区中背离所述第二表面的一侧；所述第一发射区用于连接发射极，所述栅极区用于连接栅电极，所述IGBT集电极区用于连接集电极；所述栅极区和所述栅极氧化区位于所述基底中背离所述第二表面的一侧；
其中，在基底的第一表面形成基体区，包括：在所述基底中背离所述第二表面的部分进行第二类型的掺杂元素的掺杂得到基区；在所述基区中背离第二表面的第一部分进行第一类型的掺杂元素的掺杂得到第一发射区，在所述基区中背离第二表面的第二部分进行第二类型的掺杂元素的掺杂得到第二发射区。
在一些可能的实施方式中，所述场板区包括第一场环区、栅极总线和位于所述第一场环区与所述栅极总线之间的场板介质层；所述第一场环区中具有第二类型的掺杂元素，用于连接发射极；所述栅极总线用于连接栅电极；
所述场限环区包括第二场环区、控制区和位于所述第二场环区与所述控制区之间的场限环介质层；所述第二场环区中具有第二类型的掺杂元素。
在一些可能的实施方式中，所述第一类型为N型，所述第二类型为P型。
本申请实施例的第三方面提供了一种电子设备，包括电路板以及电路板上连接的如第一方面所述的IGBT。
在一些可能的实施方式中，所述电子设备为功率变换器。
附图说明
为了清楚地理解本申请的具体实施方式，下面将描述本申请具体实施方式时用到的附图做一简要说明。显而易见地，这些附图仅是本申请的部分实施例。
图1为本申请实施例提供的一种智能电网的架构示意图；
图2为本申请实施例提供的一种IGBT的结构示意图；
图3为本申请实施例提供的另一种IGBT的结构示意图；
图4为本申请实施例提供的一种IGBT的静态特性的示意图；
图5为本申请实施例提供的一种IGBT的工作安全区的示意图；
图6为本申请实施例提供的一种负阻现象的示意图；
图7为本申请实施例提供的又一种IGBT的结构示意图；
图8为本申请实施例提供的还一种IGBT的结构示意图；
图9为本申请实施例提供的一种IGBT的制造方法的流程图；
图10-14为本申请实施例提供的IGBT在制造过程中的结构示意图。
具体实施方式
本申请实施例提供了一种绝缘栅双极晶体管及其制造方法、电子设备，提高器件的耐压特性。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
目前，IGBT存在耐压特性较差的问题，耐压特性包括IGBT的最大承受反向耐压的水平，可以利用BV CES来体现，BV CES是栅极与发射极间短路时，在指定的集电极和发射极的电流作用下，集电极与发射极间能承受的最大反向耐压，最大反向耐压越大，器件的耐压特性越好。
随着集电极和发射极之间的电流的增大，最大反向耐压也随之增加，然而当最大反向耐压超过器件的雪崩耐量后，BV CES会发生回退(snap back)的现象，此时随着电流的增大，最大反向耐压反而减小，即显现BV负阻效应，则器件会在器件终端区产生漏电大的现象，随着电流进一步增大，器件放大倍数增加，在该负反馈下，器件发生损坏，最终烧毁。
基于以上技术问题，本申请实施例提供了一种绝缘栅双极晶体管IGBT及其制造方法、电子设备，IGBT包括相对的第一表面和第二表面，在从第一表面向第二表面的方向上，具有依次连接的正面器件区、IGBT漂移区、IGBT缓冲区和IGBT集电极区，其中正面器件区可以包括元胞区和环绕元胞区的终端区，终端区包括环绕元胞区的场板区和环绕场板区的场限环区，IGBT漂移区中具有第一类型的掺杂元素，IGBT缓冲区中具有第一类型的掺杂元素，IGBT缓冲区中的第一类型的掺杂元素的浓度大于IGBT漂移区中的第一类型的掺杂元素的浓度，IGBT集电极区包括元胞集电极区、场板集电极区和场限环集电极区，元胞 集电极区与元胞区在第一表面的投影重合，场板集电极区与场板区在第一表面的投影重合，场限环集电极区与场限环区在第一表面的投影重合，IGBT集电极区中具有第二类型的掺杂元素，在元胞集电极区的第二类型的掺杂元素的浓度等于场板集电极区的第二类型的掺杂元素的浓度时，场板区往往比元胞区更容易击穿，因此可以设计元胞集电极区的第二类型的掺杂元素的浓度大于场板集电极区的第二类型的掺杂元素的浓度，也就是说，与元胞区相对的部分集电极区具有较大的第二类型的掺杂元素的浓度，而与场板区相对的部分集电极区具有较小的第二类型的掺杂元素的浓度，有效减少场板区寄生三极管的放大倍数，减少器件在承受反向耐压时的漏电值，改善器件的耐压特性以及安全工作区特性，加强器件的鲁棒性，提高器件整体的工作性能。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。
IGBT用于实现功率变换，可以应用于功率变换器，适用于直流电压为600V及以上的变流系统，如变频器、交流电机、开关电源、照明电路、牵引传动等领域，还适用于新能源汽车、智能电网、轨道交通等领域。
IGBT模块在电动汽车中发挥着至关重要的作用，是电动汽车充电桩等设备的核心技术部件，IGBT模块占电动汽车成本将近10％，占充电桩成本约20％。IGBT可以应用于电动汽车的电控控制系统，通过大功率直流/交流(DC/AC)逆变后驱动汽车电机；也可以应用于电动汽车的车载空调控制系统，通过小功率直流/交流(DC/AC)逆变，这里可以使用电流较小的IGBT；还可以应用于充电桩，其中IGBT模块被作用开关元件使用。
IGBT广泛应用于智能电网的发电端、输电端、变电端及用电端：从发电端来看，风力发电、光伏发电中的整流器和逆变器都需要使用IGBT模块。从输电端来看，特高压直流输电中柔性交流输电系统(flexible AC transmission systems，FACTS)需要大量使用IGBT等功率器件。从变电端来看，IGBT是电力电子变压器(power electronic transformer，PET)的关键器件。从用电端来看，家用白电、微波炉、发光二极管(light-emitting diode，LED)照明驱动等都对IGBT有大量的需求。
参考图1所示，为本申请实施例中一种智能电网的架构，包括依次连接的太阳能电池板(PV panels)、直流-直流(DC-DC)最大功率点跟踪(maximum power point tracking，MPPT)系统、直流连接(DC link)、直流-交流逆变器(DC-AC inverter)、交流滤波器(AC Filter)、输出端，其中DC-AC逆变器中可以设置有IGBT器件。
IGBT器件已成为轨道交通车辆牵引变流器和各种辅助变流器的主流电力电子器件。交流传动技术是现代轨道交通的核心技术之一，在交流传动系统中牵引变流器是关键部件，而IGBT又是牵引变流器最核心的器件之一。
本申请实施例中，绝缘栅双极晶体管可以包括相对的第一表面A1和第二表面A2，在从第一表面A1到第二表面A2的方向上，依次具有正面器件区1001、IGBT漂移区1002、IGBT缓冲区1003和IGBT集电极区1004。其中，第一表面A1可以作为芯片的正面，第 二表面A2可以作为芯片的背面。
参考图2所示，为本申请实施例提供的一种IGBT的俯视图，即芯片的正面的结构示意图，参考图3所示，为本申请实施例提供的另一种IGBT的结构示意图，图3可以为图2中的IGBT沿AA向的剖视图，为了便于描述，以下说明中，将第一表面A1作为上表面，将第二表面A2作为下表面，即定义了“上”和“下”的位置关系，实际上，这里的“上”和“下”是为了便于描述而定义的，与绝缘栅双极晶体管的放置位置有关，因此这种描述不应该作为对该器件结构的限定。
在半导体器件领域中，可以在半导体中掺入掺杂元素，掺杂元素的类型可以分为P型(空穴型，positive)和N型(电子型，negative)，例如可以在半导体中掺杂P型掺杂元素得到P型半导体，这样P型半导体以空穴导电为主，或在半导体中掺杂N型掺杂元素得到N型半导体，这样N型半导体以电子导电为主。掺杂后半导体中掺杂元素的浓度作为掺杂浓度，可以利用掺杂元素和半导体元素的比例表示，也可以利用单位体积内掺杂元素的原子数表示。P型掺杂元素可以为Ⅲ族元素，例如硼、铟等，N型元素可以为Ⅴ族元素，例如氮、磷等。
根据掺杂后半导体中掺杂元素的浓度，可以将对半导体的掺杂分为轻掺杂和重掺杂，对应掺杂后的半导体为轻掺杂半导体和重掺杂半导体。
其中，轻掺杂指掺入的掺杂元素的数量较少，掺杂后半导体中掺杂元素的浓度较低，例如掺杂元素和半导体元素的原子数量比例约为十亿分之一。例如在半导体中轻掺杂P型掺杂元素可以表示为少空穴型(P-型)掺杂，得到P-型半导体；在半导体中轻掺杂N型掺杂元素可以表示为少电子型(N-型)掺杂，得到N-型半导体。
重掺杂指掺入的掺杂元素的数量较多，掺杂后半导体中掺杂元素的浓度较高，例如掺杂元素和半导体元素的原子数量比例约为千分之一。例如在半导体中重掺杂P型掺杂元素可以表示为多空穴型(P+型)掺杂，得到P+型半导体；在半导体中重掺杂N型掺杂元素可以表示为多电子型(N+型)掺杂，得到N+型半导体。
本申请实施例中，正面器件区1001位于器件中朝向第一表面A1的一侧，包括元胞区10和环绕元胞区10的终端区20，终端区20可实现芯片平面电场分压的功能。终端区20可以包括场板区21和场限环区22，其中场板区21包围元胞区10，场限环区22包围场板区21。参考图3所示，元胞区10、场板区21、场限环区22可以利用两个虚线分隔开，两个虚线位置用于表征元胞区10、场板区21、场限环区22之间的界限位置，由于图3为剖视图，因此实际上元胞区10和场板区21之间的界限为闭合的环，场板区21和场限环22之间的界限为闭合的环。
在IGBT为平面栅型IGBT时，元胞区10可以包括基体区、栅极区106和栅极氧化区107，基体区包括基区103、第一发射区104和第二发射区105，第一发射区104和第二发射区105位于基体区中背离第二表面A2的一侧，其中第一发射区104中具有第一类型的掺杂元素，第二发射区105中具有第二类型的掺杂元素，基区103具有第二类型的掺杂元素，第一发射区104用于连接发射极108，第二发射区中的第二类型的掺杂元素的浓度大于基区103中的第二类型的掺杂元素的浓度。栅极区106和栅极氧化区107可以位于基体 区之外背离第二表面A2的一侧，栅极氧化区107同时与第一发射区104和基区103连接，例如栅极氧化区107位于第一发射区104和基区103背离第二表面A2的一侧，即基体区的上方，栅极区106位于栅极氧化区107的背离第二表面A2的一侧，即栅极氧化区107的上方，栅极区106用于连接栅电极，作为器件的控制区。
在IGBT为沟槽栅型IGBT时，元胞区10可以包括基体区，基体区包括基区103、栅极区106、栅极氧化区107、第一发射区104和第二发射区105，栅极区106、栅极氧化区107、第一发射区104和第二发射区105位于基体区中背离第二表面A2的一侧，其中第一发射区104中具有第一类型的掺杂元素，第二发射区105中具有第二类型的掺杂元素，基区103具有第二类型的掺杂元素，第一发射区104用于连接发射极108，第二发射区中的第二类型的掺杂元素的浓度大于基区103中的第二类型的掺杂元素的浓度。此外，栅极区106和栅极氧化区107可以位于基体区中，栅极氧化区107在基体区中包围栅极区106，栅极氧化区107同时与第一发射区104和基区103连接，例如栅极氧化区107的侧壁在背离第二表面A2的一侧与第一发射区104连接，其他部分侧壁与基区103连接，栅极区106用于连接栅电极，作为器件的控制区。
本申请实施例中，可以利用元胞介质层覆盖第一发射区104和第二发射区105，元胞介质层可以包括第一介质层101和其上的第二介质层102，第一介质层101覆盖第一发射区104和第二发射区105，第一介质层101可以为氧化物隔离(local oxidation of silicon，LOCOS)层，第二介质层102的材料可以为氧化硅。在需要引出第一发射区104时，可以对第一介质层101和第二介质层102进行刻蚀得到刻蚀孔，在刻蚀孔中形成导体材料，该导体材料可以作为发射极108。
场板区21可以包括第一场环区211，第一场环区211可以和发射极108连接，第一场环区211中具有第二类型的掺杂元素，第一场环区211上设置有场环介质层，场环介质层包括第三介质层212及其上的第四介质层213，第三介质层212可以为氧化物隔离层，第四介质层213的材料可以为氧化硅，第四介质层213上可以设置有栅极总线(gate bus)214，栅极总线214可以和元胞区10的栅电极连接；场限环区22可以包括多个第二场环区221，第二场环区221上设置有场限环介质层，场限环介质层可以包括第五介质层222及其上的第六介质层223，第五介质层222可以为氧化物隔离层，第六介质层223的材料可以为氧化硅，第五介质层222上还设置有控制结构225和控制结构上的引出结构224，引出结构224可以贯穿第六介质层223，控制结构225的材料可以为多晶硅，引出结构224的材料可以为铝。
在正面器件区1001朝向第二表面A2的一侧可以设置有IGBT漂移区1002，即IGBT漂移区1002位于正面器件区1001下方，IGBT漂移区1002与正面器件区1001连接，例如与元胞区10的基区103连接，与场板区21的第一场环区211连接，与场限环区22的第二场环区221连接，在沟槽栅型IGBT中，IGBT漂移区1002还可以与元胞区10的栅氧化区连接。IGBT漂移区1002可以中具有第一类型的掺杂元素，位于元胞区10朝向第二表面A2的一侧的部分IGBT漂移区1002可以记为第一漂移区111，位于场板区21朝向第二表面A2的一侧的部分IGBT漂移区1002可以记为第二漂移区217，位于场限环区22朝向第 二表面A2的一侧的部分IGBT漂移区1002可以记为第三漂移区227。即，第一漂移区111位于元胞区10下方，且第一漂移区111和元胞区10在第一表面A1的投影重合，第二漂移区217位于场板区21下方，且第二漂移区217和场板区21在第一表面A1的投影重合，第三漂移区227位于场限环区22下方，且第三漂移区227和场限环区22在第一表面A1的投影重合。参考图3所示，元胞区10和第一漂移区位于虚线同一侧，场板区21和第二漂移区217位于虚线同一侧，场限环区22和第三漂移区227位于虚线同一侧，虚线是为了便于说明引入的，实际上第一漂移区111、第二漂移区217和第三漂移区227之间可以并无明显界限。
在IGBT漂移区1002朝向第二表面A2的一侧可以设置有IGBT缓冲区1003，即IGBT缓冲区1003位于IGBT漂移区1002的下方，IGBT缓冲区1003与IGBT漂移区1002连接，IGBT缓冲区1003中具有第一类型的掺杂元素，即掺杂元素与IGBT漂移区1002的掺杂元素的类型相同，且IGBT缓冲区1003的第一类型的掺杂元素的浓度大于IGBT漂移区1002的第一类型的掺杂元素的浓度，其可以作为场截止层，提高IGBT的性能。位于第一漂移区111朝向第二表面A2的一侧的部分IGBT缓冲区1003记为第一缓冲区121，位于第二漂移区217朝向第二表面A2的一侧的部分IGBT缓冲区1003记为第二缓冲区218，位于第三漂移区227朝向第二表面A2的一侧的部分IGBT缓冲区1003记为第三缓冲区228。即，第一缓冲区121位于第一漂移区111下方，且第一缓冲区121和元胞区10在第一表面A1的投影重合，第二缓冲区218位于第二漂移区217下方，且第二缓冲区218和场板区21在第一表面A1的投影重合，第三缓冲区228位于第三漂移区227下方，且第三缓冲区228和场限环区22在第一表面A1的投影重合，参考图3所示，第一缓冲区121、元胞区10和第一漂移区位于虚线同一侧，第二缓冲区218、场板区21和第二漂移区217位于虚线同一侧，第三缓冲区228、场限环区22和第三漂移区227位于虚线同一侧，实际上第一缓冲区121、第二缓冲区218、第三缓冲区228之间可以并无明显界限。
在IGBT缓冲区1003朝向第二表面A2的一侧可以设置有IGBT集电极区1004，即IGBT集电极区1004位于IGBT缓冲区1003下方，IGBT集电极区1004与IGBT缓冲区1003连接，且用于连接集电极，IGBT集电极区1004可以具有第二类型的掺杂元素，即掺杂元素与IGBT缓冲区1003的掺杂元素的类型相反，位于第一缓冲区121朝向第二表面A2的一侧的部分IGBT集电极区1004可以记为元胞集电极区131，位于终端区20朝向第二表面A2的一侧的部分IGBT集电极区1004可以记为终端集电极区，终端集电极区中，位于第二缓冲区218朝向第二表面A2的一侧的部分IGBT集电极区1004可以记为场板集电极区219，位于第三缓冲区228朝向第二表面A2的一侧的部分IGBT集电极区1004可以记为场限环集电极区229。即，元胞集电极区131位于第一缓冲区121下方，且元胞集电极区131和元胞区10在第一表面A1的投影重合，终端集电极区位于第二缓冲区218和第三缓冲区228下方，且终端集电极区和终端区20在第一表面A1的投影重合，终端集电极区中场板集电极区219位于第二缓冲区218下方，且场板集电极区219和场板区21在第一表面A1的投影重合，场限环集电极区229位于第三缓冲区228下方，且场限环集电极区229和场限环区22在第一表面A1的投影重合，参考图3所示，元胞集电极区131、第一缓冲区121、 元胞区10和第一漂移区位于虚线同一侧，场板集电极区219、第二缓冲区218、场板区21和第二漂移区217位于虚线同一侧，场限环集电极区229、第三缓冲区228、场限环区22和第三漂移区227位于虚线同一侧，实际上元胞集电极区131、场板集电极区219、场限环集电极区229之间可以并无明显界限。
IGBT缓冲区1003设置在IGBT漂移区1002和IGBT集电极区1004之间，其可以作为场截止层，使IGBT为场截止型IGBT(field stop IGBT，FS-IGBT)。场截止层的作用有三点：1)截止正向电场，相比于没有场截止层的结构而言，同样的厚度能够承受更大的压降；2)减小漂移区的厚度，实现薄片化，降低导通损耗；3)减少注入少子空穴的存储空间，降低关断时间和损耗。
其中，第一类型的掺杂元素和第二类型的掺杂元素为不同类型的掺杂元素，二者分别为P型和N型，掺杂第一类型的掺杂元素的半导体具有第一导电类型，掺杂第二类型的掺杂元素的半导体具有第二导电类型，第一导电类型和第二导电类型为不同的导电类型，掺杂P型掺杂元素的半导体的导电类型为P型，掺杂N型掺杂元素的半导体的导电类型为N型，作为一种示例，第一导电类型可以为N型，第二导电类型可以为P型，则基区103导电类型为P，第一发射区104导电类型为N，第二发射区105导电类型为P，第一场环区211和第二场环区221的导电类型为P型，IGBT漂移区1002的导电类型为N，IGBT缓冲区1003的导电类型为N，IGBT集电极区1004的导电类型为P。
以上的基区103、第一发射区104、第二发射区105、第一场环区211、第二场环区221、IGBT漂移区1002、IGBT缓冲区1003、IGBT集电极区1004可以为基底的不同位置，通过不同位置的掺杂得到，基区103的掺杂可以为轻掺杂，表示为P-，第一发射区104和第二发射区105的掺杂可以为重掺杂，分别表示为N+和P+，IGBT漂移区1002的掺杂可以为轻掺杂，表示为N-，IGBT缓冲区1003的掺杂可以为重掺杂，表示为N+，掺杂量级可以为1E12～1E13。集电极、栅电极和发射极108构成IGBT的3个电极端口。当IGBT正常工作时，元胞区的基区103表面会形成导通沟道，导电沟道在紧靠栅极氧化区107边界形成，导电沟道一侧为第一发射区104，在导电沟道另一侧为第一漂移区111，电子从发射极108经第一漂移区111流向集电极，由于集电极正向偏置以及电中性的要求，大量空穴将不断地从集电极注入到第一漂移区111，部分空穴和第一漂移区111的电子形成电导调制，其余空穴则扩散至基区103与第一漂移区111形成的结位置，最终由发射极108收集。此时IGBT的外部表现为：存在负载电流，IGBT处于导通状态。正是由于IGBT正向导通时的电导调制效应使得IGBT具有正向导通压降低、通态电流大，损耗小的优点。
参考图4所示，为本申请实施例提供的一种IGBT的静态特性的示意图，IGBT的静态特性主要包括转移特性和输出特性。
其中，IGBT的转移特性用于描述IGBT集电极电流Ic与栅-射电压V GE(U GE)之间的关系，参考图4A所示，为本申请实施例中一种IGBT的转移特性曲线，横坐标为U GE，纵坐标为I C，开启电压U GE(th)是IGBT能实现电导调制而导通的最低栅--射电压，在U GE大于开启电压时，IGBT导通从而具有正向的I C，且I C随着U GE逐渐增大。
IGBT的输出特性也称为伏安特性，描述以栅-射电压为参变量时，集电极电流I C与集- 射电压V CE(U CE)之间的关系，参考图4B所示，为本申请实施例中一种IGBT的输出特性曲线，横坐标为U CE，纵坐标为I C，不同的曲线(1、2、3、4、5)分布对应依次增长的U GE，IGBT的输出特性分为三个区域：正向阻断区Ⅲ、有源区Ⅱ和饱和区Ⅰ，在IGBT处于正向阻断区时，IGBT截止。在IGBT处于有源区时，I C随着U CE和U GE的增长而增长，且I C随着U CE增长幅度较小。在IGBT处于饱和区Ⅰ时，I C随着U CE和U GE的增长而增长，且I C增长幅度较大。当V CE(U CE)<0时，IGBT为反向阻断状态。在电力电子电路中，IGBT在开关状态工作，在正向阻断区Ⅲ和饱和区Ⅰ之间转换。
参考图5所示，为本申请实施例提供的一种IGBT的安全工作区的示意图，其中横坐标为集-射电压V CE(U CE)，纵坐标为I C，安全工作区(safe operation area，SOA)反映了一个功率器件同时承受一定电压和电流的能力，反向偏置安全工作区(Reverse Bias Safe Operation Area，RBSOA)，由反向最大集电极电流、最大集电极-发射极间电压和最大允许电压上升率dV CE/dt确定，从图中可以看出，在重复脉冲作用下，RBSOA在I C≤200V且V CE≤1200V的区域范围内，这个区域表示栅偏压为零或负值但因空穴电流没有消失而存在时的关断瞬态。
IGBT还具有一定的性能参数，在其使用过程中需要在其最小或最大极限能力或极限条件的范围内，IGBT工作过程中不能超过最高会最低额定值，其主要的参数如下：
Collector–Emitter blocking voltage(BVCES):栅极与发射极间短路时，集电极与发射极间的最大电压；
Gate–Emitter voltage(VGES):集电极与发射极短路时，栅极与发射极间最大电压；
Continuous collector current(IC):集电极所允许的最大直流电流。一般指结温从25℃的壳体温度升到150℃的最大结温时所需的直流电流值。
Peak collector repetitive current(ICM):一般指在瞬态条件下，IGBT能够承受比其最大连续电流更高的峰值电流。
Maximum power dissipation(PD):此参数表示在25℃的壳体温度下，将结温提高到最大值150℃所需的功率耗散。
Junction temperature(Tj):IGBT结温在工作时的允许范围。
Collector–Emitter leakage current(ICES):栅极与发射极短路时，在集电极、发射极间加上指定的电压和指定的温度时的漏电流。
Gate–Emitter threshold voltage(VGE(th)):该参数定义了栅极-发射极的电压范围，在此范围内，IGBT导通。阈值电压具有负温度系数。阈值电压随栅极氧化层厚度线性增加，与P型基区掺杂浓度的平方根成正比。氧化物-硅界面间的固定表面电荷和栅氧中的可移动离子会导致阈值电压的偏移。
Collector–Emitter saturation voltage(VCE(SAT)):在指定的集电极电流和栅极电压的情况下，集电极与发射极间的电压。
Input capacitance(Cies):当集电极对发射极短路时，测得的栅极-发射极电容。输入电容为栅极发射极与米勒电容之和。栅极-发射极电容比米勒电容大得多。
Output capacitance(Coes):栅极对发射极短路时集电极与发射极之间的电容，具有典型 的PN结电压相关性。
Reverse transfer capacitance(Cres):栅极与集电极之间的米勒电容，具有复杂的电压依赖性。
具有场截止层的IGBT存在耐压特性较差的问题，耐压特性包括IGBT的最大承受反向耐压的水平，可以利用BV CES来体现，BV CES是栅极与发射极间短路时，在指定的集电极和发射极的电流作用下，集电极与发射极间能承受的最大反向耐压，最大反向耐压越大，器件的耐压特性越好。
随着集电极和发射极之间的电流的增大，最大反向耐压也随之增加，然而当最大反向耐压超过器件的雪崩耐量后，BV CES会发生回退(snap back)的现象，此时随着电流的增大，最大反向耐压反而减小，即显现BV负阻效应，则器件会在器件终端区20产生漏电大的现象，随着电流进一步增大，器件放大倍数增加，在该负反馈下，器件发生损坏，最终烧毁。
参考图6所示，为本申请实施例中一种负阻效应的示意图，横坐标为VCES，纵坐标为ICES，在ICES为20nA时，VCES为1100V(三角形所在位置)，在最大反向耐压超过器件的雪崩耐量后，随着电流的增大，最大反向耐压反而减小，参考左侧虚线，在ICES增加到1mA时，VCES为1100V回退到1100V，在出现BV负阻效应后，SOA特性相应减小。在没有BV CES回退现象，即不显现BV负阻效应时，随着电流的增大，最大反向耐压也逐渐增大，参考右侧虚线。
在反向耐压时，PNP晶体管的放大倍数与发射区的扩散系数DE/基区宽度WB/基区注入剂量NB呈反相关，而与基区的扩散系数DB/发射区的宽度WE/发射区的注入剂量NE呈正相关，如下公式所示：
Figure PCTCN2022100066-appb-000001
PNP晶体管的发射区可以作为IGBT集电极区，因此可以通过降低PNP晶体管的发射区的注入剂量，或增加PNP晶体管的基区的注入剂量和/或宽度来减小基区宽度，从而降低PNP晶体管的放大倍数，即可以通过降低IGBT集电极区1004的注入剂量，或增加IGBT缓冲区1003的掺杂浓度/宽度等方式来减小IGBT的基区宽度，从而降低IGBT的放大倍数，达到抑制负阻的目的。然而该方案调整是对器件整体性的改变，降低放大倍数的同时也会影响到BV耐压的整体水平，抑或提高器件的饱和电压，导致通态损耗的增加。具体的，IGBT背面在进行空穴注入时，是通过对整个背面区域进行空穴的注入，各区域注入的离子浓度都完全一致。
目前，还可以对元胞区10的背面进行空穴注入时，将每个元胞区10进行一分为二的不同空穴浓度的注入，从而减小发射极108与集电极之间的漏电，同时降低关断损耗，提升产品的RBSOA特性(反向偏置安全工作区)。该技术的缺点在于：虽然对每个元胞都进行了半边的分区，空穴的差异注入后，器件的饱和压降会由于元胞区10另外半边的薄P型注入被拉高，增加了静态损耗。
在IGBT中，IGBT集电极区1004和IGBT缓冲区1003掺杂有不同类型的掺杂元素， 则二者界面处形成PN结，IGBT集电极区1004背离IGBT缓冲区1003的表面与PN结之间的距离作为该PN结的结深，PN结的结深受IGBT集电极区1004的掺杂深度以及PN结厚度影响，在IGBT集电极区1004的掺杂深度一定的情况下，PN结越薄，PN结的结深越深，PN结越容易被击穿。针对IGBT集电极区1004和IGBT缓冲区1003之间的PN结，IGBT的结构特性使终端区20的结深相较于元胞区10的结深更深，在反向耐压时，电场击穿点会集中在终端区20的PN结处，而参考图3所示，当纵向承受反向耐压时，器件中的电场分布可以利用带箭头的实线表示，在终端区20的PN结所在区域同时存在横向和纵向的击穿路径，较容易击穿。由于IGBT的器件本征特性，在纵向上存在寄生的PNP三极管，但背面的空穴注入的浓度直接影响到饱和压降(VCESAT)，过浓的背面空穴注入会使得PN结更薄，三极管的放大倍数增加，导致器件的snapback加剧，引起BV击穿的负阻效应，最终影响器件的使用性能。
此外，场板区21下的区域是电场强度最集中的区域，针对该区域的漏电流控制可以有效控制器件整体漏电流。因此，根据寄生晶体管的击穿特性，可以调整PNP的场板区21下的区域的注入剂量，降低场板集电极区219的空穴注入浓度，令元胞集电极区131的第二类型的掺杂元素的浓度大于场板集电极区219的第二类型的掺杂元素的浓度，通过上述PNP晶体管的放大倍数与发射区和基区的函数关系，可知降低正对场板区21下的P集电极的注入剂量，可以针对性地减小场板区21三极管的放大倍数。也就是说，本申请实施例中，通过对元胞集电极区131和场板集电极区219注入不同浓度的空穴，进行局部的漏电流控制，针对性的降低放大倍数，从而能够在不影响器件的饱和压降的水平的前提下，改善器件的耐压能力，消除BV负阻现象，提高器件的可靠性。
具体的，终端集电极区可以具有均匀的第二类型的掺杂元素的浓度，即场板集电极区219的第二类型的掺杂元素的浓度等于场限环集电极区229的第二类型的掺杂元素的浓度，则元胞集电极区131的第二类型的掺杂元素的浓度大于场板集电极区219的第二类型的掺杂元素的浓度，同时大于场限环集电极区229的第二类型的掺杂元素的浓度，参考图7所示，为本申请实施例提供的又一种IGBT的结构示意图，当纵向承受反向耐压时，器件中的电场分布可以利用带箭头的实线表示，场板集电极区219和场限环集电极区229的第二类型的掺杂元素的浓度较低时，场板集电极区219和第二缓冲区218之间的PN结所在区域、场限环集电极区229和第三缓冲区228之间的PN结所在区域的横向击穿路径得到了抑制，较不容易击穿，相应的，场板集电极区219和场限环集电极区229的第二类型的掺杂元素的浓度较低时，利于增大场板集电极区219和第一缓冲区121之间的PN结的厚度，以及场限环集电极区229和第二缓冲区218之间的PN结的厚度，降低终端集电极区和IGBT缓冲区1003之间的PN结的结深，使该处的PN结更不易击穿。例如元胞集电极区131的掺杂为重掺杂，掺杂量级为1E13～1E14cm -3(即10 12～10 14cm -3)，场板集电极区219和场限环集电极区229的掺杂为轻掺杂，掺杂量级为1E12～1E13(即10 12～10 13cm -3)。
具体的，终端集电极区可以具有不均匀的第二类型的掺杂元素的浓度，例如场板集电极区219的第二类型的掺杂元素的浓度小于场限环集电极区229的第二类型的掺杂元素的浓度，而元胞集电极区131的第二类型的掺杂元素的浓度大于场板集电极区219的第二类 型的掺杂元素的浓度，此外，元胞集电极区131的第二类型的掺杂元素的浓度可以等于场限环集电极区229的第二类型的掺杂元素的浓度，也可以大于场限环集电极区229的第二类型的掺杂元素的浓度。参考图8所示，为本申请实施例提供的还一种IGBT的结构示意图，当纵向承受反向耐压时，器件中的电场分布可以利用带箭头的实线表示，场板集电极区219的第二类型的掺杂元素的浓度较低时，场板集电极区219和第二缓冲区218之间的PN结所在区域的横向击穿路径得到了抑制，较不容易击穿，相应的，场板集电极区219的第二类型的掺杂元素的浓度较低时，利于增大场板集电极区219和第一缓冲区121之间的PN结的宽度，降低该PN结的结深，使该处的PN结更不易击穿。例如元胞集电极区131和场限环集电极区229的掺杂为重掺杂，第二类型的掺杂元素的浓度量级为1E13～1E14cm -3(即10 12～10 14cm -3)，场板集电极区219的掺杂为轻掺杂，第二类型的掺杂元素的量级为1E12～1E13cm -3(即10 12～10 13cm -3)。
本申请实施例提供了一种绝缘栅双极晶体管IGBT，包括相对的第一表面和第二表面，在从第一表面向第二表面的方向上，具有依次连接的正面器件区、IGBT漂移区、IGBT缓冲区和IGBT集电极区，其中正面器件区可以包括元胞区和环绕元胞区的终端区，终端区包括环绕元胞区的场板区和环绕场板区的场限环区，IGBT漂移区中具有第一类型的掺杂元素，IGBT缓冲区中具有第一类型的掺杂元素，IGBT缓冲区中的第一类型的掺杂元素的浓度大于IGBT漂移区中的第一类型的掺杂元素的浓度，IGBT集电极区包括元胞集电极区、场板集电极区和场限环集电极区，元胞集电极区与元胞区在第一表面的投影重合，场板集电极区与场板区在第一表面的投影重合，场限环集电极区与场限环区在第一表面的投影重合，IGBT集电极区中具有第二类型的掺杂元素，在元胞集电极区的第二类型的掺杂元素的浓度等于场板集电极区的第二类型的掺杂元素的浓度时，场板区往往比元胞区更容易击穿，因此可以设计元胞集电极区的第二类型的掺杂元素的浓度大于场板集电极区的第二类型的掺杂元素的浓度，也就是说，与元胞区相对的部分集电极区具有较大的第二类型的掺杂元素的浓度，而与场板区相对的部分集电极区具有较小的第二类型的掺杂元素的浓度，有效减少场板区寄生三极管的放大倍数，减少器件在承受反向耐压时的漏电值，改善器件的耐压特性以及安全工作区特性，加强器件的鲁棒性，提高器件整体的工作性能。
基于本申请实施例提供的一种IGBT，本申请实施例还提供了一种IGBT的制造方法，参考图9所示，为本申请实施例中一种IGBT的制造方法流程图，该方法可以包括：
S101，在基底的第一表面形成正面器件区1001，第一基底中具有第一类型的掺杂元素，参考图10所示。
本申请实施例中，绝缘栅双极晶体管可以包括相对的第一表面A1和第二表面A2，其中，第一表面A1可以作为芯片的正面，第二表面A2可以作为芯片的背面。基底可以为半导体基底，在基底中掺杂可以得到P型半导体或N型半导体，基底可以具有较大的厚度，不同的位置用于被掺杂而形成IGBT中的不同掺杂结构。具体的，基底可以具有第一类型的掺杂元素，基底中对应有后续IGBT缓冲区1003、IGBT集电极区1004对应的区域，但是还未进行相应的掺杂。
在基底的第一表面可以形成正面器件区1001，正面器件区1001可以包括元胞区10和环绕元胞区10的终端区20，终端区20可实现芯片平面电场分压的功能。终端区20可以包括场板区21和场限环区22，其中场板区21包围元胞区10，场限环区22包围场板区21。
在IGBT为平面栅型IGBT时，元胞区10可以包括基体区、栅极区106和栅极氧化区107，基体区包括基区103、第一发射区104和第二发射区105，第一发射区104和第二发射区105位于基体区中背离第二表面A2的一侧，其中第一发射区104中具有第一类型的掺杂元素，第二发射区105中具有第二类型的掺杂元素，基区103具有第二类型的掺杂元素，第一发射区104用于连接发射极108，第二发射区中的第一类型的掺杂元素的浓度大于基区103中的第一类型的掺杂元素的浓度。栅极区106和栅极氧化区107可以位于基体区之外背离第二表面A2的一侧，栅极氧化区107同时与第一发射区104和基区103连接，例如栅极氧化区107位于第一发射区104和基区103背离第二表面A2的一侧，即基体区的上方，栅极区106位于栅极氧化区107的背离第二表面A2的一侧，即栅极氧化区107的上方，栅极区106用于连接栅电极，作为器件的控制区。
其中，在基底的第一表面形成基体区，可以具体为，在基底中背离第二表面A2的部分进行第二类型的掺杂元素的掺杂得到基区103；在基区103中背离第二表面A2的第一部分进行第一类型的掺杂元素的掺杂得到第一发射区104，在基区103中背离第二表面A2的第二部分进行第二类型的掺杂元素的掺杂得到第二发射区105，从而使第二发射区105的第一类型的掺杂元素的浓度大于基区103中除第一发射区104和第二发射区105的剩余部分的第一类型的掺杂元素的浓度。
在基底的第一表面形成栅极区106和栅极氧化区107，可以具体为，在基底之外背离第二表面的一侧形成栅极氧化物和栅极结构，栅极氧化物所在区域为栅极氧化区107，栅极结构所在区域为栅极区106。栅极氧化物和栅极结构的形成方式可以为沉积工艺。
具体实施时，栅极氧化区在栅极区106之前形成，基体区可以在栅极氧化区107之前形成，也可以在栅极区106之后形成。
在IGBT为沟槽栅型IGBT时，元胞区10可以包括基体区，基体区包括基区103、栅极区106、栅极氧化区107、第一发射区104和第二发射区105，栅极区、栅极氧化区、第一发射区和第二发射区位于基体区中背离第二表面A2的一侧，其中第一发射区104中具有第一类型的掺杂元素，第二发射区105中具有第二类型的掺杂元素，基区103具有第二类型的掺杂元素，第一发射区104用于连接发射极108，第二发射区中的第一类型的掺杂元素的浓度大于基区103中的第一类型的掺杂元素的浓度。此外，栅极区106和栅极氧化区107可以位于基体区中，栅极氧化区107在基体区中包围栅极区106，栅极氧化区107同时与第一发射区104和基区103连接，例如栅极氧化区107的侧壁在背离第二表面A2的一侧与第一发射区104连接，其他部分侧壁与基区103连接，栅极区106用于连接栅电极，作为器件的控制区。
其中，在基底的第一表面形成基体区，可以具体为，在基底中背离第二表面A2的部分进行第二类型的掺杂元素的掺杂得到基区103，在基区103中背离第二表面A2的第一部分进行第一类型的掺杂元素的掺杂得到第一发射区104，在基区103中背离第二表面A2的 第二部分进行第二类型的掺杂元素的掺杂得到第二发射区105，使第二发射区105的第一类型的掺杂元素的浓度大于基区103中除第一发射区104和第二发射区105的剩余部分的第一类型的掺杂元素的浓度。
在基底的第一表面形成栅极区106和栅极氧化区107，可以具体为，在基底中背离第二表面的第三部分刻蚀得到栅孔，在栅孔中形成栅极氧化物和栅极结构，栅极氧化物所在区域为栅极氧化区107，栅极结构所在区域为栅极区106。
具体实施时，栅极氧化区在栅极区106之前形成，基体区可以在栅极氧化区107之前形成，也可以在栅极区106之后形成。
本申请实施例中，可以利用元胞介质层覆盖第一发射区104和第二发射区105，元胞介质层可以包括第一介质层101和其上的第二介质层102，第一介质层101覆盖第一发射区104和第二发射区105，第一介质层101可以为氧化物隔离(Local Oxidation of Silicon，LOCOS)层，第二介质层102的材料可以为氧化硅。在需要引出第一发射区104时，可以对第一介质层101和第二介质层102进行刻蚀得到刻蚀孔，在刻蚀孔中形成导体材料，该导体材料可以作为发射极108。
场板区21可以包括第一场环区211，第一场环区211可以和发射极108连接，第一场环区211中具有第二类型的掺杂元素，第一场环区211上设置有场环介质层，场环介质层包括第三介质层212及其上的第四介质层213，第三介质层212可以为氧化物隔离层，第四介质层213的材料可以为氧化硅，第四介质层213上可以设置有栅极总线214，栅极总线214可以和元胞区10的栅电极连接；场限环区22可以包括多个第二场环区221，第二场环区221上设置有场限环介质层，场限环介质层可以包括第五介质层222及其上的第六介质层223，第五介质层222可以为氧化物隔离层，第六介质层223的材料可以为氧化硅，第五介质层222上还设置有控制结构225和控制结构上的引出结构224，引出结构224可以贯穿第六介质层223，控制结构225的材料可以为多晶硅，引出结构224的材料可以为铝。
其中，第一类型的掺杂元素和第二类型的掺杂元素为不同类型的掺杂元素，二者分别为P型和N型，掺杂第一类型的掺杂元素的半导体具有第一导电类型，掺杂第二类型的掺杂元素的半导体具有第二导电类型，第一导电类型和第二导电类型为不同的导电类型，掺杂P型掺杂元素的半导体的导电类型为P型，掺杂N型掺杂元素的半导体的导电类型为N型，作为一种示例，第一导电类型可以为N型，第二导电类型可以为P型，则基区103导电类型为P，第一发射区104导电类型为N，第二发射区105导电类型为P，第一场环区211和第二场环区221的导电类型为P型。以上的基区103、第一发射区104、第二发射区105、第一场环区211、第二场环区221可以为基底的不同位置，通过不同位置的掺杂得到，基区103的掺杂可以为轻掺杂，表示为P-，第一发射区104和第二发射区105的掺杂可以为重掺杂，分别表示为N+和P+。
在形成正面器件区1001之后，可以对基底从第二表面进行减薄，减薄后基底的厚度降低，通常为80～120微米(um)，当然，基底减薄后的厚度与掺杂后的结构的厚度相关，因此与器件的BV耐压有相关性，本领域技术人员可以根据实际情况设置其厚度。
S102，在基底中朝向第二表面的部分进行第一类型的掺杂元素的掺杂，得到IGBT缓冲区1003，正面器件区1001和IGBT缓冲区1003之间的基底作为IGBT漂移区1002，参考图11所示。
在形成正面器件区1001后，可以从基底的第二表面对基底进行第一类型的掺杂元素的掺杂，得到IGBT缓冲区1003，正面器件区1001和IGBT缓冲区1003之间的基底作为IGBT漂移区1002。
IGBT漂移区1002位于正面器件区1001的朝向第二表面的一侧，即IGBT漂移区1002位于正面器件区1001下方，IGBT漂移区1002与正面器件区1001连接，例如与元胞区10的基区103连接，与场板区21的第一场环区211连接，与场限环区22的第二场环区221连接，在沟槽栅型IGBT中，IGBT漂移区1002还可以与元胞区10的栅氧化区连接。IGBT漂移区1002可以具有第一类型的掺杂元素，位于元胞区10朝向第二表面A2的一侧的部分IGBT漂移区1002可以记为第一漂移区111，位于场板区21朝向第二表面A2的一侧的部分IGBT漂移区1002可以记为第二漂移区217，位于场限环区22朝向第二表面A2的一侧的部分IGBT漂移区1002可以记为第三漂移区227。
即，第一漂移区111位于元胞区10下方，且第一漂移区111和元胞区10在第一表面A1的投影重合，第二漂移区217位于场板区21下方，且第二漂移区217和场板区21在第一表面A1的投影重合，第三漂移区227位于场限环区22下方，且第三漂移区227和场限环区22在第一表面A1的投影重合。其中，第一漂移区111、第二漂移区217和第三漂移区227具有相同的掺杂浓度，且IGBT缓冲区1003利用同一掺杂工艺形成，在不同位置处可以具有相同的掺杂深度，因此第一漂移区111、第二漂移区217和第三漂移区227具有相同的材料以及尺寸。
IGBT缓冲区1003位于IGBT漂移区1002朝向第二表面A2的一侧，即IGBT缓冲区1003位于IGBT漂移区1002的下方，IGBT缓冲区1003与IGBT漂移区1002连接，IGBT缓冲区1003中具有第一类型的掺杂元素，即掺杂元素与IGBT漂移区1002的掺杂元素的类型相同，且IGBT缓冲区1003的第一类型的掺杂元素的浓度大于IGBT漂移区1002的第一类型的掺杂元素的浓度，其可以作为场截止层，提高IGBT的性能。位于第一漂移区111朝向第二表面A2的一侧的部分IGBT缓冲区1003记为第一缓冲区121，位于第二漂移区217朝向第二表面A2的一侧的部分IGBT缓冲区1003记为第二缓冲区218，位于第三漂移区227朝向第二表面A2的一侧的部分IGBT缓冲区1003记为第三缓冲区228。
即，第一缓冲区121位于第一漂移区111下方，且第一缓冲区121和元胞区10在第一表面A1的投影重合，第二缓冲区218位于第二漂移区217下方，且第二缓冲区218和场板区21在第一表面A1的投影重合，第三缓冲区228位于第三漂移区227下方，且第三缓冲区228和场限环区22在第一表面A1的投影重合。其中，第一缓冲区121、第二缓冲区218和第三缓冲区228具有相同的掺杂浓度，且利用同一掺杂工艺形成，可以具有相同的掺杂深度，因此具有相同的材料以及尺寸。
S103，在IGBT漂移区1002中朝向第二表面的部分进行第二类型的掺杂元素的第一次掺杂，得到IGBT集电极区1004，参考图12所示。
在IGBT漂移区1002中朝向第二表面的部分进行第二类型的掺杂元素的第一次掺杂，可以得到IGBT集电极区1004，第一表面A1和第二表面A2为相对的表面，例如第一表面A1为上表面时，第二表面A2可以为下表面。IGBT集电极区1004位于IGBT缓冲区1003朝向第二表面A2的一侧，即IGBT集电极区1004位于IGBT缓冲区1003下方，IGBT集电极区1004与IGBT缓冲区1003连接，且用于连接集电极，IGBT集电极区1004可以具有第二类型的掺杂元素，即掺杂元素与IGBT缓冲区1003的掺杂元素的类型相反，位于第一缓冲区121朝向第二表面A2的一侧的部分IGBT集电极区1004可以记为元胞集电极区131，位于终端区20朝向第二表面A2的一侧的部分IGBT集电极区1004可以记为终端集电极区，终端集电极区中，位于第二缓冲区218朝向第二表面A2的一侧的部分IGBT集电极区1004可以记为场板集电极区219，位于第三缓冲区228朝向第二表面A2的一侧的部分IGBT集电极区1004可以记为场限环集电极区229。
即，元胞集电极区131位于第一缓冲区121下方，且元胞集电极区131和元胞区10在第一表面A1的投影重合，终端集电极区位于第二缓冲区218和第三缓冲区228下方，且终端集电极区和终端区20在第一表面A1的投影重合，终端集电极区中场板集电极区219位于第二缓冲区218下方，且场板集电极区219和场板区21在第一表面A1的投影重合，场限环集电极区229位于第三缓冲区228下方，且场限环集电极区229和场限环区22在第一表面A1的投影重合。其中，在第一次掺杂后，元胞集电极区131、场板集电极区219和场限环集电极区229具有相同的掺杂浓度，且利用同一掺杂工艺形成，可以具有相同的掺杂深度，因此具有相同的材料以及尺寸。
作为一种示例，第一导电类型可以为N型，第二导电类型可以为P型，则基区103导电类型为P，第一发射区104导电类型为N，第二发射区105导电类型为P，第一场环区211和第二场环区221的导电类型为P型，IGBT漂移区1002的导电类型为N，IGBT缓冲区1003的导电类型为N，IGBT集电极区1004的导电类型为P。以上的基区103、第一发射区104、第二发射区105、第一场环区211、第二场环区221、IGBT漂移区1002、IGBT缓冲区1003、IGBT集电极区1004可以为基底的不同位置，通过不同位置的掺杂得到，基区103的掺杂可以为轻掺杂，表示为P-，第一发射区104和第二发射区105的掺杂可以为重掺杂，分别表示为N+和P+，IGBT漂移区1002的掺杂可以为轻掺杂，表示为N-，IGBT缓冲区1003的掺杂可以为重掺杂，表示为N+，掺杂量级可以为1E12～1E13。
S104，遮挡场板集电极区219，对IGBT集电极区1004进行第二类型的掺杂元素的第二次掺杂，参考图7、图8、图13和图14。
本申请实施例中，在对IGBT集电极区1004进行第二类型的掺杂元素的第一次掺杂后，可以遮挡场板集电极区219，对IGBT集电极区1004进行第二类型的掺杂元素的第二次掺杂，这样元胞集电极区131的第二类型的掺杂元素的浓度大于场板集电极区219的第二类型的掺杂元素的浓度，通过上述PNP晶体管的放大倍数与发射区和基区的函数关系，可知降低正对场板区21下的P集电极的注入剂量，可以针对性地减小场板区21三极管的放大倍数。也就是说，本申请实施例中，通过对元胞集电极区131和场板集电极区219注入不同浓度的空穴，进行局部的漏电流控制，针对性的降低放大倍数，从而能够在不影响器件 的饱和压降的水平的前提下，改善器件的耐压能力，消除BV负阻现象，提高器件的可靠性。
具体的，终端集电极区可以具有均匀的第二类型的掺杂元素的浓度，即场板集电极区219的第二类型的掺杂元素的浓度等于场限环集电极区229的第二类型的掺杂元素的浓度，则元胞集电极区131的第二类型的掺杂元素的浓度大于场板集电极区219的第二类型的掺杂元素的浓度，同时大于场限环集电极区229的第二类型的掺杂元素的浓度，参考图7所示，则遮挡场板集电极区219的同时，还可以遮挡场限环集电极区229，即遮挡场板集电极区，对IGBT集电极区进行第二类型的掺杂元素的第二次掺杂，以使元胞集电极区131中的第二类型的掺杂元素的浓度大于场板集电极区219中的第二类型的掺杂元素的浓度，可以具体为，遮挡场板集电极区219和场限环集电极区229，对IGBT集电极区1004进行第二类型的掺杂元素的第二次掺杂，以使元胞集电极区131的第二类型的掺杂元素的浓度大于场板集电极区219的第二类型的掺杂元素的浓度，且大于场限环集电极区229的第二类型的掺杂元素的浓度，当然，场板集电极区219的第二类型的掺杂元素的浓度等于场限环集电极区229的第二类型的掺杂元素的浓度。
具体的，终端集电极区可以具有不均匀的第二类型的掺杂元素的浓度，例如场板集电极区219的第二类型的掺杂元素的浓度小于场限环集电极区229的第二类型的掺杂元素的浓度，而元胞集电极区131的第二类型的掺杂元素的浓度大于场板集电极区219的第二类型的掺杂元素的浓度，同时可以等于场限环集电极区229的第二类型的掺杂元素的浓度，参考图8所示，则遮挡场板集电极区219，对IGBT集电极区1004进行第二次掺杂后，元胞集电极区的第二类型的掺杂元素的浓度大于场板区的第二类型的掺杂元素的浓度，场限环集电极区229的第二类型的掺杂元素的浓度大于场板集电极区219的第二类型的掺杂元素的浓度。这是因为场板区21下的区域是电场强度最集中的区域，针对该区域的漏电流控制可以有效控制器件整体漏电流。
具体实施时，第二次掺杂的掺杂浓度大于第一次掺杂的掺杂浓度，具体的，第一次掺杂可以为轻掺杂，第二次掺杂可以为重掺杂。场板集电极区219可以利用光罩遮挡，在遮挡场板集电极区219的同时对场限环集电极区229的遮挡也可以利用同一光罩。
在对IGBT集电极区1004进行第二次掺杂后，可以在第二表面形成集电极240，集电极240的材料可以为导电性较好的此案例，例如金属材料，集电极240与IGBT集电极区1004连接，参考图13和图14所示。
本申请实施例提供了一种绝缘栅双极晶体管IGBT的制造方法，在基底的第一表面形成正面器件区，正面器件区可以包括元胞区和环绕元胞区的终端区，终端区包括环绕元胞区的场板区和环绕场板区的场限环区，基底中具有第一类型的掺杂元素，在基底中朝向第二表面的部分进行第一类型的掺杂元素掺杂，得到IGBT缓冲区，正面器件区和IGBT缓冲区之间的基底作为IGBT漂移区，IGBT缓冲区的第一类型的掺杂元素的浓度大于IGBT漂移区的第一类型的掺杂元素的浓度，在IGBT漂移区中朝向第二表面的部分进行第二类型的掺杂元素的第一次掺杂，得到IGBT集电极区，IGBT集电极区包括元胞集电极区、场板集电极区和场限环集电极区，遮挡场板集电极区，对IGBT集电极区进行第二类型的掺杂 元素的第二次掺杂，在元胞集电极区的第二类型的掺杂元素的浓度等于场板集电极区的第二类型的掺杂元素的浓度时，场板区往往比元胞区更容易击穿，因此可以设计元胞集电极区的第二类型的掺杂元素的浓度大于场板集电极区的第二类型的掺杂元素的浓度，也就是说，与元胞区相对的部分集电极区具有较大的第二类型的掺杂元素的浓度，而与场板区相对的部分集电极区具有较小的第二类型的掺杂元素的浓度，有效减少场板区寄生三极管的放大倍数，减少器件在承受反向耐压时的漏电值，改善器件的耐压特性以及安全工作区特性，加强器件的鲁棒性，提高器件整体的工作性能。
本申请实施例还提供了一种电子设备，包括电路板以及与电路板连接的所述的IGBT。所述电子设备可以为功率变换器，功率变换器包括逆变器、整流器等。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。
以上为本申请的具体实现方式。应当理解，以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (17)

  1. 一种绝缘栅双极晶体管IGBT，其特征在于，包括相对的第一表面和第二表面；在从所述第一表面向所述第二表面的方向上，具有依次连接的正面器件区、IGBT漂移区、IGBT缓冲区和IGBT集电极区；
    其中，所述正面器件区包括元胞区和环绕所述元胞区的终端区；所述终端区包括环绕所述元胞区的场板区，以及环绕所述场板区的场限环区；
    所述IGBT漂移区中具有第一类型的掺杂元素；
    所述IGBT缓冲区中具有第一类型的掺杂元素，所述IGBT缓冲区中的第一类型的掺杂元素的浓度大于所述IGBT漂移区中的第一类型的掺杂元素的浓度；
    所述IGBT集电极区包括元胞集电极区、场板集电极区和场限环集电极区，所述IGBT集电极区中具有第二类型的掺杂元素；所述元胞集电极区与所述元胞区在所述第一表面的投影重合，所述场板集电极区与所述场板区在所述第一表面的投影重合，所述场限环集电极区与所述场限环区在所述第一表面的投影重合；所述元胞集电极区中的第二类型的掺杂元素的浓度大于所述场板集电极区中的第二类型的掺杂元素的浓度；
    所述第一类型为P型或N型，所述第二类型为P型或N型，所述第一类型和所述第二类型不同。
  2. 根据权利要求1所述的IGBT，其特征在于，所述元胞集电极区为重掺杂区，所述场板集电极区为轻掺杂区。
  3. 根据权利要求1或2所述的IGBT，其特征在于，所述元胞集电极区中的第二类型的掺杂元素浓度大于所述场限环集电极区中的第二类型的掺杂元素的浓度。
  4. 根据权利要求1-3任一项所述的IGBT，其特征在于，所述元胞集电极区为重掺杂区，所述场限环集电极区为轻掺杂区。
  5. 根据权利要求1-4任一项所述的IGBT，其特征在于，所述IGBT为平面栅IGBT；
    所述元胞区包括基体区、栅极区和栅极氧化区，所述基体区包括基区、第一发射区和第二发射区，所述第一发射区和所述第二发射区位于所述基体区中背离所述第二表面的一侧；所述第一发射区中具有第一类型的掺杂元素，所述第二发射区中具有第二类型的掺杂元素，所述基区具有第二类型的掺杂元素；所述第一发射区用于连接发射极；所述第二发射区中的第二类型的掺杂元素的浓度大于所述基区中的第二类型的掺杂元素的浓度；所述栅极区用于连接栅电极，所述栅极区和所述栅极氧化区位于所述基体区之外背离所述第二表面的一侧；所述IGBT集电极区用于连接集电极。
  6. 根据权利要求1-4任一项所述的IGBT，其特征在于，所述IGBT为沟槽栅IGBT；
    所述元胞区包括基体区，所述基体区包括基区、栅极区、栅极氧化区、第一发射区和第二发射区，所述栅极区、所述栅极氧化区、所述第一发射区和所述第二发射区位于所述基体区中背离所述第二表面的一侧；所述第一发射区中具有第一类型的掺杂元素，所述第二发射区中具有第二类型的掺杂元素，所述基区具有第二类型的掺杂元素；所述第一发射区用于连接发射极；所述第二发射区中的第二类型的掺杂元素的浓度大于所述基区中的第二类型的掺杂元素的浓度；所述栅极区用于连接栅电极，所述栅极氧化区在所述基体区中 包围所述栅极区；所述IGBT集电极区用于连接集电极。
  7. 根据权利要求1-6任一项所述的IGBT，其特征在于，
    所述场板区包括第一场环区、栅极总线和位于所述第一场环区与所述栅极总线之间的场板介质层；所述第一场环区中具有第二类型的掺杂元素，用于连接发射极；所述栅极总线用于连接栅电极；
    所述场限环区包括第二场环区、控制结构和位于所述第二场环区与所述控制结构之间的场限环介质层；所述第二场环区中具有第二类型的掺杂元素。
  8. 根据权利要求1-7任一项所述的IGBT，其特征在于，所述第一类型为N型，所述第二类型为P型。
  9. 一种绝缘栅双极晶体管IGBT的制造方法，其特征在于，包括：
    在基底的第一表面形成正面器件区；所述基底中具有第一类型的掺杂元素；所述正面器件区包括元胞区和环绕所述元胞区的终端区；所述终端区包括环绕所述元胞区的场板区，以及环绕所述场板区的场限环区；
    在所述基底中朝向第二表面的部分进行第一类型的掺杂元素的掺杂，得到IGBT缓冲区；所述IGBT缓冲区中的第一类型的掺杂元素的浓度大于所述基底中的第一类型的掺杂元素的浓度，所述正面器件区和所述IGBT缓冲区之间的基底作为IGBT漂移区；所述第一表面和所述第二表面为相对的表面；
    在所述IGBT漂移区中朝向所述第二表面的部分进行第二类型的掺杂元素的第一次掺杂，得到IGBT集电极区；所述IGBT集电极区包括元胞集电极区、场板集电极区和场限环集电极区，所述元胞集电极区与所述元胞区在所述第一表面的投影重合，所述场板集电极区与所述场板区在所述第一表面的投影重合，所述场限环集电极区与所述场限环区在所述第一表面的投影重合；所述第一类型为P型或N型，所述第二类型为P型或N型，所述第一类型和所述第二类型不同；
    遮挡所述场板集电极区，对所述IGBT集电极区进行第二类型的掺杂元素的第二次掺杂，以使所述元胞集电极区中的第二类型的掺杂元素的浓度大于所述场板集电极区中的第二类型的掺杂元素的浓度。
  10. 根据权利要求9所述的方法，其特征在于，遮挡所述场板集电极区，对所述IGBT集电极区进行第二类型的掺杂元素的第二次掺杂，以使所述元胞集电极区中的第二类型的掺杂元素的浓度大于所述场板集电极区中的第二类型的掺杂元素的浓度，包括：
    遮挡所述场板集电极区和所述场限环集电极区，对所述IGBT集电极区进行第二类型的掺杂元素的第二次掺杂，以使所述元胞集电极区中的第二类型的掺杂元素的浓度大于所述场板集电极区中的第二类型的掺杂元素的浓度，且大于所述场限环集电极区中的第二类型的掺杂元素的浓度。
  11. 根据权利要求9或10所述的方法，其特征在于，所述第一次掺杂为轻掺杂，所述第二次掺杂为重掺杂。
  12. 根据权利要求9-11任一项所述的方法，其特征在于，所述IGBT为平面栅IGBT，则所述元胞区包括基体区、栅极区和栅极氧化区；所述基体区中包括基区、第一发射区和 第二发射区，所述第一发射区和所述第二发射区位于所述基体区中背离所述第二表面的一侧；所述第一发射区用于连接发射极，所述栅极区用于连接栅电极，所述IGBT集电极区用于连接集电极；所述栅极区和所述栅极氧化区位于所述基底之外背离所述第二表面的一侧；
    其中，在所述基底的第一表面形成所述基体区，包括：在所述基底中背离所述第二表面的部分进行第二类型的掺杂元素的掺杂得到基区；在所述基区中背离第二表面的第一部分进行第一类型的掺杂元素的掺杂得到第一发射区，在所述基区中背离第二表面的第二部分进行第二类型的掺杂元素的掺杂得到第二发射区。
  13. 根据权利要求9-11任一项所述的方法，其特征在于，所述IGBT为沟槽栅IGBT，所述元胞区包括基体区；所述基体区中包括基区、栅极区、栅极氧化区、第一发射区和第二发射区，所述栅极区、所述栅极氧化区、所述第一发射区和所述第二发射区位于所述基体区中背离所述第二表面的一侧；所述第一发射区用于连接发射极，所述栅极区用于连接栅电极，所述IGBT集电极区用于连接集电极；所述栅极区和所述栅极氧化区位于所述基底中背离所述第二表面的一侧；
    其中，在所述基底的第一表面形成所述基体区，包括：在所述基底中背离所述第二表面的部分进行第二类型的掺杂元素的掺杂得到基区；在所述基区中背离第二表面的第一部分进行第一类型的掺杂元素的掺杂得到第一发射区，在所述基区中背离第二表面的第二部分进行第二类型的掺杂元素的掺杂得到第二发射区。
  14. 根据权利要求9-13任一项所述的方法，其特征在于，
    所述场板区包括第一场环区、栅极总线和位于所述第一场环区与所述栅极总线之间的场板介质层；所述第一场环区中具有第二类型的掺杂元素，用于连接发射极；所述栅极总线用于连接栅电极；
    所述场限环区包括第二场环区、控制区和位于所述第二场环区与所述控制区之间的场限环介质层；所述第二场环区中具有第二类型的掺杂元素。
  15. 根据权利要求9-14任一项所述的方法，其特征在于，所述第一类型为N型，所述第二类型为P型。
  16. 一种电子设备，其特征在于，包括电路板以及与电路板连接的如权利要求1-8任一项所述的IGBT。
  17. 根据权利要求16所述的电子设备，其特征在于，所述电子设备为功率变换器。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116544231A (zh) * 2023-07-06 2023-08-04 上海埃积半导体有限公司 一种压接式igbt器件结构
WO2025026093A1 (zh) * 2023-07-28 2025-02-06 珠海格力电器股份有限公司 Igbt器件及其元胞结构、元胞结构的制作方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114188396B (zh) * 2021-10-30 2024-01-30 华为数字能源技术有限公司 一种绝缘栅双极晶体管及其制造方法、电子设备
CN115083895B (zh) * 2022-07-21 2022-11-18 深圳芯能半导体技术有限公司 一种背面变掺杂结构的场截止igbt芯片制作方法
CN115065350B (zh) * 2022-08-16 2022-11-18 深圳芯能半导体技术有限公司 一种集成门极米勒钳位功能的igbt芯片及其制备方法
CN115207108A (zh) * 2022-09-14 2022-10-18 淄博美林电子有限公司 一种低米勒电容igbt及其制作方法
CN119584610A (zh) * 2024-11-25 2025-03-07 海信家电集团股份有限公司 一种igbt结构及其制造方法、半导体器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007220724A (ja) * 2006-02-14 2007-08-30 Toyota Motor Corp 薄板型ｉｇｂｔの製造方法及び薄板型ｉｇｂｔ
CN202282353U (zh) * 2011-09-26 2012-06-20 上海华虹Nec电子有限公司 绝缘栅双极晶体管的器件结构
CN104143568A (zh) * 2014-08-15 2014-11-12 无锡新洁能股份有限公司 具有终端结构的场截止型igbt器件及其制造方法
CN113097287A (zh) * 2019-12-23 2021-07-09 全球能源互联网研究院有限公司 一种igbt芯片终端结构及igbt芯片终端结构制作方法
CN114188396A (zh) * 2021-10-30 2022-03-15 华为数字能源技术有限公司 一种绝缘栅双极晶体管及其制造方法、电子设备

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5205856B2 (ja) * 2007-01-11 2013-06-05 富士電機株式会社 電力用半導体素子
CN103094332B (zh) * 2013-01-30 2016-03-30 华为技术有限公司 一种绝缘栅双极晶体管
CN109256422B (zh) * 2017-07-12 2022-04-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN109671771B (zh) * 2018-11-19 2022-04-01 全球能源互联网研究院有限公司 Igbt芯片的背面结构、igbt芯片结构及制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007220724A (ja) * 2006-02-14 2007-08-30 Toyota Motor Corp 薄板型ｉｇｂｔの製造方法及び薄板型ｉｇｂｔ
CN202282353U (zh) * 2011-09-26 2012-06-20 上海华虹Nec电子有限公司 绝缘栅双极晶体管的器件结构
CN104143568A (zh) * 2014-08-15 2014-11-12 无锡新洁能股份有限公司 具有终端结构的场截止型igbt器件及其制造方法
CN113097287A (zh) * 2019-12-23 2021-07-09 全球能源互联网研究院有限公司 一种igbt芯片终端结构及igbt芯片终端结构制作方法
CN114188396A (zh) * 2021-10-30 2022-03-15 华为数字能源技术有限公司 一种绝缘栅双极晶体管及其制造方法、电子设备

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHINA NATIONAL INTELLECTUAL PROPERTY ADMINISTRATION, 30 October 2021 (2021-10-30)
See also references of EP4340036A4

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116544231A (zh) * 2023-07-06 2023-08-04 上海埃积半导体有限公司 一种压接式igbt器件结构
CN116544231B (zh) * 2023-07-06 2023-09-29 上海埃积半导体有限公司 一种压接式igbt器件结构
WO2025026093A1 (zh) * 2023-07-28 2025-02-06 珠海格力电器股份有限公司 Igbt器件及其元胞结构、元胞结构的制作方法

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