WO2023071284A1 - 沟槽栅半导体器件及其制造方法 - Google Patents

沟槽栅半导体器件及其制造方法 Download PDF

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WO2023071284A1
WO2023071284A1 PCT/CN2022/104255 CN2022104255W WO2023071284A1 WO 2023071284 A1 WO2023071284 A1 WO 2023071284A1 CN 2022104255 W CN2022104255 W CN 2022104255W WO 2023071284 A1 WO2023071284 A1 WO 2023071284A1
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trench
layer
epitaxial layer
conductivity type
gate
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French (fr)
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高博
黄伯宁
唐龙谷
张毅
周锋
胡飞
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Huawei Digital Power Technologies Co Ltd
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Huawei Digital Power Technologies Co Ltd
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Priority to EP22885189.5A priority Critical patent/EP4343850A4/en
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Priority to US18/581,921 priority patent/US20240243181A1/en
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species

Definitions

  • the embodiments of the present application relate to the field of semiconductor technologies, and in particular to a trench gate semiconductor device and a method for manufacturing the trench gate semiconductor device.
  • Trench gate metal-oxide-semiconductor field-effect transistor (MOSFET) device structure has higher electron mobility and smaller JFET resistance effect due to the vertical channel, so that the same size trench gate
  • the specific on-resistance of the device is much smaller than that of the planar gate device.
  • the oxide layer at the bottom of the trench gate is subjected to a higher electric field, which intensifies the risk of breakdown of the oxide layer of the trench gate.
  • Embodiments of the present application provide a trench gate semiconductor device and a method for manufacturing the trench gate semiconductor device, so as to improve the reliability of the trench gate semiconductor device.
  • a first aspect of an embodiment of the present application provides a trench gate semiconductor device.
  • the trench gate semiconductor device includes a substrate, an epitaxial layer, a well region, a source region, a first trench, a gate, a gate insulating film and an amorphous semiconductor layer.
  • the substrate is of the first conductivity type.
  • the epitaxial layer is of the first conductivity type and is grown on the substrate.
  • the well region is of the second conductivity type and is formed on the surface layer of the epitaxial layer.
  • the source region is of the first conductivity type and is formed on the surface layer of the well region.
  • the first groove extends from the surface of the source region through the well region to the epitaxial layer, and the gate is formed in the first groove through the gate insulating film.
  • the first conductivity type is P-type
  • the second conductivity type is N-type.
  • the P-type conductivity type is formed by doping acceptor impurities such as aluminum ions, boron ions or gallium ions
  • the N-type conductivity type is formed by doping N-type loser impurities such as nitrogen ions or phosphorus ions.
  • the amorphous semiconductor layer is formed in the first trench and wraps the outer bottom wall of the gate and the corners on both sides of the outer bottom wall through the gate insulation film.
  • the amorphous semiconductor layer is made of low dielectric constant material. In addition to wrapping the oxide layer on the outer wall of the gate, an amorphous semiconductor layer with a low dielectric constant is further wrapped on the bottom of the gate, thereby increasing the breakdown field strength at the bottom of the trench gate and improving the reliability of the gate oxide layer.
  • the thickness of the amorphous semiconductor layer is more than 0.1 um.
  • the trench gate semiconductor device further includes a shielding layer of the second conductivity type formed on the epitaxial layer at the bottom of the first trench, the shielding layer wraps the amorphous semiconductor layer, and is chamfered by a circular arc The extension ends on the gate insulating film at the corner or sidewall of the gate.
  • the shielding layer can form a PN junction with the substrate, thereby reducing the voltage borne by the gate insulating film at the corner of the gate, and improving the reliability of the trench gate semiconductor device.
  • the junction depth of the shielding layer is greater than or equal to 0.4um.
  • the corners of the gate are arc-shaped on the longitudinal section of the trench gate semiconductor device. In this way, the squeeze on the electric field lines between the gate and the drain can be reduced, thereby reducing the voltage that the gate insulating film at the corner of the gate can withstand.
  • the epitaxial layer includes a first sub-epitaxial layer and a second sub-epitaxial layer, the first sub-epitaxial layer is located between the substrate and the second sub-epitaxial layer, and the well region, the source region and the amorphous semiconductor layer Formed on the second sub-epitaxial layer, the doping concentration of the first sub-epitaxial layer is lower than that of the substrate and greater than that of the second sub-epitaxial layer. In this way, the on-resistance of the epitaxial layer can be reduced.
  • the trench gate semiconductor device further includes: a contact region with a second conductivity type connected to the well region, the doping concentration of the contact region is greater than that of the well region; the source electrode is connected to the source region It is connected to the contact area; the drain is connected to the side of the substrate away from the epitaxial layer.
  • the surface doping concentration of the contact region is greater than the surface doping concentration of the well region, and the contact region is used to connect with the source, so that the resistivity of the well region can be reduced.
  • the semiconductor material constituting the substrate and the epitaxial layer is silicon carbide, and/or the amorphous semiconductor is amorphous silicon carbide.
  • Silicon carbide has superior physical properties such as wide band gap, high critical breakdown field strength, and large thermal conductivity, which make silicon carbide semiconductor devices have the advantages of high voltage resistance, high temperature resistance, fast switching speed, and low switching loss.
  • the second aspect of the embodiment of the present application provides a method for manufacturing a trench gate semiconductor device.
  • the method includes: depositing an epitaxial layer with the first conductivity type on a substrate with the first conductivity type; Implanting ions of the second conductivity type to form a well region; implanting ions of the first conductivity type on the surface of the well region to form a source region; photolithographically forming a first trench extending through the well region to the epitaxial layer on the surface of the source region; The bottom wall and corner of a trench are implanted with ions of the second conductivity type to form an amorphous semiconductor layer; a gate insulating film is grown in the first trench and deposited and doped to form a gate of a polysilicon gate structure. Ion implantation is performed on the bottom of the trench after the formation of the trench, that is, the requirements for the junction depth of the amorphous semiconductor layer are not high, the process is simple, the performance parameters of the process equipment are low, and the production cost is low.
  • the steps before implanting ions into the bottom wall of the first trench and part of the sidewall to form the amorphous semiconductor layer, the steps include: depositing a masking film on the sidewall of the first trench; The walls and corners are implanted with ions of the second conductivity type to form a shielding layer, the implantation depth of the shielding layer is greater than the implantation depth of the amorphous semiconductor layer, and the doping concentration of the shielding layer is lower than the doping concentration of the amorphous semiconductor layer. impurity concentration.
  • the implanted junction depth of the shielding layer is greater than or equal to 0.4um.
  • the thickness of the amorphous semiconductor layer is greater than or equal to 0.1 um.
  • the corners of the gate are arc-shaped on the longitudinal section of the trench gate semiconductor device.
  • FIG. 1 is a schematic structural view of an embodiment of a trench gate semiconductor device provided by the present application.
  • FIG. 2 is a schematic flow diagram of an embodiment of a method for manufacturing a trench gate semiconductor device provided by the present application
  • FIG. 3 is a schematic flowchart of another embodiment of the method for manufacturing a trench gate semiconductor device provided by the present application.
  • FIG. 4 is a schematic flowchart of another embodiment of the method for manufacturing a trench gate semiconductor device provided in the present application.
  • Embodiments of the present application provide a trench gate semiconductor device and a method for manufacturing the trench gate semiconductor device, so as to improve the reliability of the trench gate semiconductor device.
  • FIG. 1 is a schematic structural diagram of an embodiment of a trench gate semiconductor device provided in the present application. It can be understood that the thickness and width of each region in FIG. 1 are only examples, and are not intended to limit the structure of the trench gate semiconductor of the present application.
  • a plurality of semiconductor devices having the same structure as the trench gate semiconductor device shown in FIG. 1 are arranged in strips, squares, hexagons or atomic lattices to form a multi-cell semiconductor device.
  • the trench-gate semiconductor 100 of this embodiment includes a substrate 11, an epitaxial layer 12, a well region 13, a source region 14, a first trench 15, a gate 16, a gate insulating film 17, an amorphous semiconductor layer 18, and a contact region. 19. Source 20 and drain 21 .
  • the substrate 11 is of the first conductivity type.
  • the epitaxial layer 12 is grown on the substrate 11 and is also of the first conductivity type.
  • the well region 13 is formed on the surface layer of the epitaxial layer 12 and is of the second conductivity type.
  • the source region 14 is formed on the surface layer of the well region 13 and is of the first conductivity type.
  • the first trench 15 extends from the surface of the source region 14 through the well region 13 to the epitaxial layer 12 .
  • the gate 16 is formed in the first trench 15 via a gate insulating film 17 .
  • the amorphous semiconductor layer 18 is formed in the first trench 15 and wraps the outer bottom wall of the gate 16 and the corners on both sides of the outer bottom wall via the gate insulating film 17 .
  • the source region 14 and the well region 13 are located on both sides of the gate 16 , and the contact region 19 is located on a side of the source region 14 and/or the well region 13 away from the gate 16 .
  • the contact region 19 is connected to the well region 13
  • the source 20 is connected to the source region 14 and the contact region 19
  • the drain 21 is connected to the side of the substrate 11 away from the epitaxial layer 12 .
  • the first conductivity type may be N type
  • the second conductivity type may be P type
  • the trench gate semiconductor device 100 is an inverted trench gate metal oxide semiconductor field effect transistor (metal oxide semiconductor field effect transistor) formed with an N channel. -oxide-semiconductor field-effect transistor, MOSFET) device.
  • MOSFET metal oxide semiconductor field effect transistor
  • the first conductivity type can also be P-type
  • the second conductivity type can be N-type
  • the trench gate semiconductor device 100 is a MOSFET device formed with a P-channel.
  • the first conductivity type may be N-type
  • the second conductivity type may be P-type as an example for illustration.
  • the substrate 11 is doped with N-type impurities such as nitrogen ions or phosphorus ions, so that the resistivity of the substrate 11 reaches 0.01-0.025 ⁇ cm.
  • the thickness of the substrate 11 is about 150 microns (um), for example, 145 um, 150 um or 155 um.
  • the doping concentration of N-type ions in the epitaxial layer 12 is lower than that of the substrate 11 .
  • the thickness of the epitaxial layer 12 is about 11um, for example, 10.5um, 11um, 11.5um or 12um.
  • the epitaxial layer 12 may include a first sub-epitaxial layer 121 and a second sub-epitaxial layer 122 .
  • the first sub-epitaxial layer 121 is located between the substrate 11 and the second sub-epitaxial layer 122 .
  • the well region 13 , the source region 14 and the amorphous semiconductor layer 18 are formed on the second sub-epitaxial layer 122 .
  • the doping concentration of the first sub-epitaxial layer 121 is lower than that of the substrate 11 and greater than that of the second sub-epitaxial layer 122 .
  • the thickness of the first sub-epitaxial layer 121 is about 0.5um, for example, 0.4um, 0.5um or 0.6um.
  • the thickness of the second sub-epitaxial layer 122 is about 11 um, for example, 10 um, 10.6 um, 11 um or 11.4 um.
  • the doping concentration distribution of the first sub-epitaxial layer 121 can be a single concentration, a step concentration or a gradually changing concentration. When the doping concentration of the first sub-epitaxial layer 121 is a step concentration or a slowly changing concentration, the doping concentration on the side close to the substrate 11 is greater than the doping concentration on the side far from the substrate 11 . In this way, the on-resistance of the epitaxial layer 12 can be reduced.
  • the well region 13 is specifically formed by performing ion implantation on the surface layer of the epitaxial layer 12, and the implanted ions may be P-type impurities such as aluminum ions, boron ions, or gallium ions.
  • the implantation concentration distribution of the P-type impurities in the well region 13 is uniform, the implantation junction depth is greater than or equal to 0.5 um, and the implantation junction depth is less than the thickness of the second sub-epitaxial layer 122 .
  • the source region 14 is specifically formed by ion implantation in the surface layer of the well region 13, and the implanted ions may be N-type impurities such as nitrogen ions or boron ions.
  • the surface implantation concentration of N-type impurities in the source region 14 is greater than 1.0 ⁇ 10 19 /cm 3 , and the implantation junction depth is about 0.2 um.
  • the thickness of the source region 14 can be, for example, 0.18um, 0.19um, 2um or 2.1um.
  • the conductivity type of the contact region 19 and the well region 13 are both P-type, and the two have a connection relationship.
  • the contact region 19 is used to connect with the source 20 , and the doping concentration of the surface of the contact region 19 is greater than 1.0 ⁇ 10 19 /cm 3 , which is greater than the doping concentration of the well region 13 . In this way, the resistivity of the well region 13 can be reduced, and the avalanche energy and the reliability of the semiconductor device can be improved.
  • the contact region 19 can be formed by selectively implanting P-type impurities such as aluminum ions, boron ions, or gallium ions into the surface layer of the epitaxial layer 12, and the implantation junction depth is greater than the implantation junction depth of the source region 14, so as to The contact region 19 is connected to the well region 13 .
  • the surface layer of the contact region 19 is equal to the surface layer of the source region 14, and the manufacturing process is relatively simple.
  • the contact region 19 may also be formed by implanting P-type impurities near the well region 13 after etching the epitaxial layer 12 to form a second trench (not shown).
  • the source electrode 20 protrudes into the second trench and connects with the contact region 19 to realize a trench-type contact, which can reduce the distance between the source electrode and the drain electrode, thereby reducing the on-resistance of the trench-gate semiconductor device 100 .
  • the source region 14 , the well region 13 and the contact region 19 are symmetrically distributed on both sides of the first trench 15 .
  • the first trench 15 is selectively formed by photolithography and etching on the surface of the source region 14.
  • the surface extends down through source region 14 and well region 13 to epitaxial layer 12 .
  • the depth of the first trench 15 is greater than 0.7um and less than the sum of the thicknesses of the second epitaxial layer 122 , the well region 13 and the source region 14 .
  • Sidewalls of the first trench 15 are perpendicular or approximately perpendicular to the surface of the source region 14
  • bottom walls of the first trench 15 are parallel or approximately parallel to the surface of the source region 14 .
  • the corners of the first trench 15 are arc-shaped, that is, the junction of the side wall and the bottom wall of the first trench 15 is arc-shaped, so as to reduce the gap between the corners of the first trench 15 and the gate 16 and the drain 21.
  • the extrusion of the electric field reduces the electric field at the corner of the first trench 15 and improves the reliability of the trench gate.
  • the amorphous semiconductor layer 18 is formed by low-temperature implantation of boron ions into the epitaxial layer 12 exposed at the bottom wall and at least part of the corners of the first trench 15, so that the amorphous semiconductor layer 18 covers the bottom wall and at least part of the corners of the first trench 15. department.
  • the boron ion implantation concentration of the amorphous semiconductor layer 18 is 1.0 ⁇ 10 14 /cm 3 , and the thickness of the amorphous semiconductor is greater than or equal to 0.1 um.
  • the amorphous semiconductor layer 18 has a low dielectric constant and is insulating or semi-insulating.
  • the amorphous semiconductor layer 18 can be made of a material with a dielectric constant of about 8.9, specifically amorphous silicon carbide, or other amorphous semiconductor materials that meet the requirements of the dielectric constant, which is not limited in this application.
  • Amorphous silicon carbide has the characteristics of high electron mobility, fast saturation electron drift and high breakdown field strength, thereby improving the reliability of the trench gate semiconductor device 100 .
  • Both the substrate 11 and the epitaxial layer 12 may also be made of silicon carbide.
  • Silicon carbide has superior physical properties such as wide band gap, high critical breakdown field strength, and large thermal conductivity, which make silicon carbide semiconductor devices have the advantages of high voltage resistance, high temperature resistance, fast switching speed, and low switching loss.
  • the substrate and the epitaxial layer may also be made of other wide bandgap materials such as gallium nitride, which is not limited in this application.
  • a gate insulating film 17 is grown to cover the sidewalls, bottom walls and corners of the first trench 15 for isolating the contact between the gate 16 and the epitaxial layer 12 , the well region 13 and the source region 14 .
  • the thickness of the gate insulating film 17 is greater than 50 nanometers (nm), and less than half of the width of the first trench 15 , that is, the gate insulating film 17 cannot completely fill the first trench 15 .
  • the thickness of the gate insulating film 17 is, for example, 50 nm, 55 nm, or 60 nm.
  • the gate insulating film 17 may be a silicon dioxide film, a silicon nitride film, or a low dielectric constant film, or the like.
  • the gate 16 is formed by depositing polysilicon on the surface of the gate insulating film 17 in the first trench 15 , and the gate 16 completely fills the first trench 15 . Since the corners of the first trench 15 are arc-shaped, the grid 16 and the gate insulating film 17 are also arc-shaped, thereby reducing the field strength borne by the gate insulating film 17 at the corners of the grid 16, which can The reliability of the gate insulating film 17 is improved. Furthermore, the amorphous semiconductor layer 18 wraps the gate insulating film 17 at the corners and the bottom wall of the gate 16 , which can increase the breakdown field strength of the gate insulating film 17 .
  • the source 20 is specifically formed by depositing metal on the source region 14 and the contact region 19
  • the drain 21 is formed by depositing metal on a side away from the epitaxial layer 12 .
  • the trench gate semiconductor device further includes a shielding layer 22 .
  • the shielding layer 22 is formed by implanting P-type impurities on the epitaxial layer 12 corresponding to the bottom wall and corner of the first trench 15, and the implantation junction depth is greater than the ion implantation junction depth of the amorphous semiconductor, and is smaller than the bottom wall of the first trench 15. The distance to the first sub-epitaxial layer 121.
  • the implanted junction depth of the shielding layer 22 is, for example, 0.4um, 0.5um, 0.6um or 0.7um.
  • the doping concentration of the shielding layer is 4.0 ⁇ 1013/cm3, which is higher than the doping concentration of the second sub-epitaxial layer 122. Therefore, the conductivity type of the shielding layer 22 is P-type when it also contains N-type ions. Since the conductivity type of the shielding layer 22 is P-type, and the conductivity type of the epitaxial layer 12 is N-type, the shielding layer 22 and the epitaxial layer 12 can form a PN junction, thereby avoiding the electric field from being concentrated on the gate insulating film at the corner of the gate 16 17 , reducing the field strength borne by the gate insulating film 17 .
  • the implantation range of the shielding layer 22 is greater than the implantation range of the amorphous semiconductor layer 18, so that the shielding layer 22 can wrap the amorphous semiconductor layer 18 and extend to the corner of the gate 16 or the gate at the side wall with a circular chamfer. on the insulating film 17. In this way, the gate insulating film 17 at the corner of the gate 16 is wrapped in multiple layers, which can increase the breakdown field strength of the gate insulating film 17 , thereby improving the reliability of the trench gate semiconductor device 100 .
  • FIG. 2 is a schematic flowchart of an embodiment of a method for manufacturing a trench gate semiconductor device provided in the present application.
  • the manufacturing method of this embodiment is used to manufacture the above-mentioned trench gate semiconductor device.
  • this embodiment includes the following steps:
  • 201 Deposit an epitaxial layer with a first conductivity type on a substrate with a first conductivity type.
  • the first conductivity type may be N type
  • the second conductivity type may be P type
  • the first conductivity type may also be P type
  • the second conductivity type may be N type
  • the first conductivity type may be N-type
  • the second conductivity type may be P-type as an example for illustration.
  • both the substrate and the epitaxial layer may be made of silicon carbide.
  • Silicon carbide has high critical avalanche breakdown electric field strength and carrier saturation drift velocity, high thermal conductivity and carrier mobility, which can make trench gate semiconductor devices have the ability to withstand high voltage, low pass State resistance, good thermal conductivity and thermal stability, and strong ability to withstand high temperature and ray radiation.
  • the substrate and the epitaxial layer may also be made of other wide bandgap materials such as gallium nitride, which is not limited in this application.
  • the first sub-epitaxial layer with a thickness of about 0.5um on the N+ (heavily doped with N-type impurities) substrate with a resistivity of 0.01-0.025 ⁇ .cm, and implant the first sub-epitaxial layer with a low concentration N-type impurities (such as nitrogen ions or phosphorus ions, etc.) in the substrate, so that the conductivity type of the first sub-epitaxial layer is N-type.
  • N-type impurities such as nitrogen ions or phosphorus ions, etc.
  • a silicon dioxide dielectric layer with a thickness of about 1.5um for masking is deposited on the second sub-epitaxial layer, and then the surface of the second sub-epitaxial layer is selectively removed by photolithography, etching, etc.
  • the silicon dioxide dielectric layer is used to form the implantation window in the well region, and the unetched silicon dioxide dielectric layer is used as a masking layer for ion implantation.
  • the etching can be performed by dry etching, and the etching is carried out in a direction perpendicular to the surface of the second sub-epitaxial layer.
  • the ion implantation method is used to implant P-type ions into the second sub-epitaxial layer through the well region implantation window to form a well region with a uniform concentration distribution and a junction depth greater than 0.5um.
  • Ion implantation is to make the ionized elements collide with the epitaxial layer under high accelerating voltage, so that the ions physically invade into the crystal lattice of the epitaxial layer.
  • silicon dioxide dielectric layer on the surface layer of the wafer that is, the trench gate semiconductor device in the processing state
  • photolithography and etching processes The silicon dioxide dielectric layer on the surface of the second sub-epitaxial layer is selectively removed to form a source region implantation window on the surface layer of the well region.
  • the ion implantation method is used to implant N-type impurities such as nitrogen ions through the source region implantation window to form an N-type source region with a surface implantation concentration greater than 1.0 ⁇ 1019/cm3 and a junction depth of 0.2um.
  • the method of ion implantation is used to implant P-type impurities such as boron ions or aluminum ions into the second sub-epitaxial layer through the implantation window of the contact area to form a contact area with a surface implantation concentration greater than 1.0 ⁇ 1019/cm3 and a junction depth greater than that of the source area.
  • P-type ion implantation concentration in the contact region is greater than the ion implantation concentration in the well region.
  • the silicon dioxide dielectric layer on the surface of the wafer is removed, a layer of 20nm carbon film dielectric is deposited, and the wafer is subjected to high-temperature annealing treatment. Thereby recovering the crystal lattice and activating the ions implanted into the epitaxial layer, the well region, the source region and the contact region.
  • annealing treatment is rapid thermal anneal (rapid thermal anneal, RTA), which can reduce the heating and cooling time of the wafer, improve the activation efficiency, and the short time can also suppress the distribution change of impurities and prevent the impurities from diffusing to other regions.
  • RTA rapid thermal anneal
  • the annealing temperature is greater than or equal to 1600 degrees and lower than the melting point of the substrate and the epitaxial layer. Specifically, the annealing temperature may be, for example, 1600 degrees, 1700 degrees, 1750 degrees or the like.
  • the carbon film is used to prevent the surface of the wafer from becoming rough during high-temperature annealing, and the carbon film is removed by plasma etching after annealing.
  • a silicon dioxide dielectric layer of about 1.5um is deposited on the wafer surface, and a part of the silicon dioxide dielectric layer on the wafer surface is selectively removed by photolithography, etching and other processes to form a trench gate etching window.
  • ICP Inductively coupled plasma
  • ICP can provide high-rate, high-selectivity and low-damage etching, and the plasma can be kept stable under low pressure, so the etching morphology can be better controlled to form sidewall and bottom wall with good straightness and no micro Groove morphology.
  • a silicon dioxide dielectric layer of about 1.2um is deposited on the surface of the wafer, a trench gate process window is etched by photolithography and etching, and a layer of about 100nm silicon dioxide is deposited on the wafer.
  • the silicon dielectric layer is implanted with boron ions into the bottom wall and corner of the first trench by ion implantation, the concentration of boron ion implantation is 1.0 ⁇ 1014/cm3, the implantation junction depth is greater than or equal to 0.1um, and the implantation temperature is less than 50 degrees, thereby forming Amorphous semiconductor layer.
  • a sacrificial oxide layer larger than 20nm is formed on the surface of the wafer (including the first trench) by high temperature oxidation. Then a wet process is used to remove the sacrificial oxide layer, thereby reducing the roughness of the wafer surface and making the wafer surface smooth.
  • a silicon dioxide dielectric layer of about 300nm is deposited on the surface of the wafer, and the active region of the gate (that is, the region corresponding to the first trench on the surface of the wafer) is etched out by photolithography, etching and other processes.
  • a 50nm gate insulating film is oxidized and grown on the surface of the wafer at high temperature, and a layer of 500nm polysilicon is deposited in the first trench by a low-pressure chemical vapor phase method, and the polysilicon is doped in situ, and the square resistance of the film is less than 30 ⁇ / ⁇ , and a polycrystalline gate structure is formed by photolithography and etching processes.
  • a silicon dioxide dielectric layer of about 100nm and a boro-phospho-silicate glass (BPSG) layer of 800nm are sequentially deposited on the surface of the wafer, and reflowed at a high temperature of 980°C.
  • the BPSG layer is It has fluidity at high temperature and can flatten the wafer surface. Then deposit a silicon dioxide dielectric layer of about 100nm, and use photolithography and etching to form an ohmic contact hole process window.
  • Ni nickel
  • RTP rapid thermal process
  • SiSi silicon-nickel
  • a silicon dioxide or silicon nitride dielectric layer and a polyimide film layer are deposited on the surface of the wafer, and the front source and gate electrodes are formed by photolithography and etching processes.
  • etching or grinding and polishing to thin the back of the wafer (that is, the side of the substrate away from the epitaxial layer) to about 150um, evaporate a layer of Ni metal on the back of the wafer, and use laser for high-speed annealing to form NiSi alloy.
  • FIG. 3 is a schematic flowchart of another embodiment of a method for manufacturing a trench gate semiconductor device provided in the present application. If manufacturing a trench gate semiconductor device that also includes a shielding layer, the manufacturing process is as follows:
  • Steps 301-303 are the same as steps 201-203, so they will not be repeated here.
  • step 204 high temperature annealing treatment is not performed on the wafer after the contact region is formed in this step.
  • a masking film is deposited on the sidewall of the first trench, and a silicon dioxide dielectric layer with a thickness of 100 nm is deposited on the surface of the wafer by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the implantation method implants P-type ions of 4.0 ⁇ 1013/cm3 and junction depth greater than 0.4um into the bottom and corner of the first trench.
  • the shielding layer After forming the shielding layer, remove all the dielectric on the surface, deposit a layer of 20nm carbon film dielectric, and perform high-temperature annealing on the wafer to activate the ions implanted into the epitaxial layer, well region, source region, contact region and shielding layer.
  • the annealing treatment is RTA or RTP, which can reduce the heating and cooling time of the wafer, improve the activation efficiency, and the short time can also suppress the distribution change of impurities and prevent the impurities from diffusing to other regions.
  • the annealing temperature is greater than or equal to 1600 degrees and lower than the melting point of the substrate and the epitaxial layer.
  • the annealing temperature may be, for example, 1600 degrees, 1700 degrees, 1750 degrees or the like.
  • the carbon film is used to prevent the surface of the wafer from becoming rough during high-temperature annealing, and the carbon film is removed by plasma etching after annealing.
  • Steps 307-309 are similar to steps 206-208, so they will not be repeated here.
  • FIG. 4 is a schematic flowchart of another embodiment of a method for manufacturing a trench gate semiconductor device provided by the present application.
  • the manufacturing process of this embodiment is as follows:
  • Steps 401-403 are the same as steps 301-303, so they will not be repeated here.
  • a first groove and a second groove are formed on the surface of the source region by photolithography.
  • the first trench is used to form a gate therein
  • the second trench is used to form a contact region at its bottom
  • a part of the source is formed in the second trench.
  • the first trench and the second trench can be etched simultaneously or separately.
  • the depth of the first trench is greater than the sum of thicknesses of the source region and the well region.
  • the depth of the second trench is greater than the depth of the source region and less than the sum of the thicknesses of the source region and the well region, so that a contact region is subsequently formed on the bottom wall of the second trench to connect with the well region.
  • the ion implantation method is used to implant P-type impurities such as boron ions or aluminum ions into the bottom wall of the second trench through the implantation window of the contact area to form a contact area with a surface implantation concentration greater than 1.0 ⁇ 1019/cm3.
  • P-type impurity implantation concentration in the contact region is greater than the ion implantation concentration in the well region.
  • Steps 406-409 are similar to steps 306-309, so they will not be repeated here.
  • the trench gate semiconductor device proposed in this application adopts a vertical trench gate structure, and by changing the direction of the channel, the mobility of the channel is improved and the specific on-resistance can be reduced.
  • the trench gate structure is adopted, which can reduce the cell size, increase the current density, and reduce the specific on-resistance.
  • a P+ shielding layer and an amorphous semiconductor layer are used to bear the reverse voltage, reduce the electric field of the gate oxide film, and improve the long-term reliability of the gate oxide film.
  • the device manufacturing method proposed in this application has a simple manufacturing process, and ion implantation can be performed on the bottom of the trench after the trench is formed, that is, the requirements for the junction depth of the P+ shielding layer and the amorphous semiconductor layer are not high, and the performance parameters of the process equipment are low. The production cost is low.
  • an oxide film formed by thermal oxidation was cited as an example of the gate insulating film, but it may be a film including an oxide film or a nitride film formed not by thermal oxidation.
  • the etching of the first trench may also be performed before the formation of the well region, the source region, or the contact region.

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Abstract

一种沟槽栅半导体器件及其制造方法，用于提高沟槽栅半导体的可靠性。沟槽栅半导体器件包括具有第一导电类型的衬底（11）；具有第一导电类型的外延层（12），生长于衬底（11）上；具有第二导电类型的阱区（13），形成于外延层（12）的表层上；具有第一导电类型的源区（14），形成于阱区（13）的表层上；第一沟槽（15），从源区（14）的表面贯穿阱区（13）延伸到外延层（12）；栅极（16），隔着栅极绝缘膜（17）形成于第一沟槽（15）内；非晶半导体层（18），形成于第一沟槽（15）内且隔着栅极绝缘膜（17）包裹栅极（16）的外底壁和外底壁两侧的角部，非晶半导体层（18）由低介电常数材料构成。

Description

沟槽栅半导体器件及其制造方法
本申请要求于2021年10月29日提交中国专利局、申请号为202111275645.2、发明名称为“沟槽栅半导体器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种沟槽栅半导体器件及沟槽栅半导体器件的制造方法。
背景技术
沟槽栅金氧半场效晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)器件结构由于垂直沟道具有较高的电子迁移率和较小的JFET电阻效应，使得相同尺寸下沟槽栅器件比导通电阻比平面栅器件的比导通电阻小很多。
但由于反向阻断后器件承载较高的电压，使得沟槽栅底部的氧化层承受较高的电场，加剧了沟槽栅的氧化层的击穿风险。
发明内容
本申请实施例提供了一种沟槽栅半导体器件及沟槽栅半导体器件的制造方法，以提高沟槽栅半导体器件的可靠性。
本申请实施例第一方面提供一种沟槽栅半导体器件。沟槽栅半导体器件包括衬底、外延层、阱区、源区、第一沟槽、栅极，栅极绝缘膜和非晶半导体层。衬底为第一导电类型。外延层为第一导电类型，生长于衬底上。阱区为第二导电类型，形成于外延层的表层上。源区为第一导电类型，形成于阱区的表层上。第一沟槽，从源区的表面贯穿阱区延伸到外延层，栅极隔着栅极绝缘膜形成于第一沟槽内。其中，第一导电类型P型，第二导电类型为N型。或者第一导电类型为N型，第二导电类型为P型。P型导电类型为掺杂铝离子、硼离子或镓离子等受主杂质形成的，N型导电类型为掺杂氮离子或磷离子等N型失主杂质形成的。非晶半导体层形成于第一沟槽内且隔着栅极绝缘膜包裹栅极的外底壁和外底壁两侧的角部，非晶半导体层由低介电常数材料构成。栅极外壁除了包裹氧化层，进一步在栅极的底部包裹低介电常数的非晶半导体层，从而提高沟槽栅底部的击穿场强，提高栅极氧化层的可靠性。
在一些可能实现的方式中，非晶半导体层的厚度为0.1um以上。
在一些可能实现的方式中，沟槽栅半导体器件还包括具有第二导电类型的屏蔽层，形成于第一沟槽底部的外延层上，屏蔽层包裹非晶半导体层，并以圆弧倒角延伸截止于栅极的角部或侧壁的栅极绝缘膜上。屏蔽层能够与衬底形成PN结，从而降低栅极角部位置的栅极绝缘膜承受的电压，提高沟槽栅半导体器件的可靠性。
在一些可能实现的方式中，屏蔽层的结深大于或等于0.4um。
在一些可能实现的方式中，栅极的角部在沟槽栅半导体器件的纵切面呈圆弧状。如此能够降低对栅极和漏极之间的电场线的挤压，从而降低栅极角部位置的栅极绝缘膜承受的电压。
在一些可能实现的方式中，外延层包括第一子外延层和第二子外延层，第一子外延层位于衬底和第二子外延层之间，阱区、源区和非晶半导体层形成于第二子外延层上，第一子外延层的掺杂浓度小于衬底的掺杂浓度，且大于第二子外延层的掺杂浓度。如此能够降低外延层的导通电阻。
在一些可能实现的方式中，沟槽栅半导体器件还包括：具有第二导电类型的接触区，与阱区连接，接触区的掺杂浓度大于阱区的掺杂浓度；源极，与源区和接触区连接；漏极，与衬底远离外延层的一面连接。接触区的表面掺杂浓度大于阱区的表面掺杂浓度，接触区用于与源极连接，如此能够降低阱区电阻率。
在一些可能实现的方式中，构成衬底和外延层的半导体材料为碳化硅，和/或非晶半导体为非晶碳化硅。碳化硅具有禁带宽度宽、临界击穿场强高、热导率大等优越的物理特性，使得碳化硅半导体器件具有耐高压、耐高温、开关速度快、开关损耗小等优点。
本申请实施例第二方面提供一种沟槽栅半导体器件的制造方法，该制造方法包括：在具有第一导电类型的衬底上沉积具有第一导电类型的外延层；在外延层的表层上注入第二导电类型的离子形成阱区；在阱区的表层上注入第一导电类型的离子形成源区；在源区表面光刻形成贯穿阱区延伸到外延层的第一沟槽；在第一沟槽的底壁及角部注入第二导电类型的离子形成非晶半导体层；在第一沟槽内生长栅极绝缘膜并淀积、掺杂形成多晶硅栅结构的栅极。在沟槽形成后对沟槽底部进行离子注入，即非晶半导体层的结深要求不高，工艺简单，对工艺设备性能参数低，制作成本低。
在一些可能实现的方式中，在第一沟槽底壁及部分侧壁注入离子形成非晶半导体层之前，包括：在第一沟槽的侧壁淀积掩蔽膜；在第一沟槽的底壁及角部注入第二导电类型的离子形成屏蔽层，所述屏蔽层的注入深度大于所述非晶半导体层的注入深度，所述屏蔽层的掺杂浓度小于所述非晶半导体层的掺杂浓度。
在一些可能实现的方式中，屏蔽层的注入结深大于或等于0.4um。
在一些可能实现的方式中，非晶半导体层的厚度大于或等于0.1um。
在一些可能实现的方式中，栅极的角部在沟槽栅半导体器件的纵切面呈圆弧状。
附图说明
图1是本申请提供的沟槽栅半导体器件一实施例的结构示意图；
图2是本申请提供的沟槽栅半导体器件的制造方法一实施例的流程示意图；
图3为本申请提供的沟槽栅半导体器件的制造方法另一实施例的流程示意图；
图4是本申请提供的沟槽栅半导体器件的制造方法又一实施例的流程示意图。
具体实施方式
本申请实施例提供了一种沟槽栅半导体器件及沟槽栅半导体器件的制造方法，以提高沟槽栅半导体器件的可靠性。
请参阅图1，图1是本申请提供的沟槽栅半导体器件一实施例的结构示意图。可以理解，图1中各区域的厚度、宽度等仅作为示例，不作为对本申请的沟槽栅半导体的结构的限制。 与图1所示的沟槽栅半导体器件具有相同构造的多个半导体器件以条形排列、方形排列、六角形排列或原子晶格排列等方式排列，构成多元胞的半导体器件。本实施例的沟槽栅半导体100包括衬底11、外延层12、阱区13、源区14、第一沟槽15、栅极16、栅极绝缘膜17、非晶半导体层18、接触区19、源极20和漏极21。
其中，衬底11为第一导电类型。外延层12生长于衬底11上，同样为第一导电类型。阱区13形成于外延层12的表层上，为第二导电类型。源区14形成于阱区13的表层上，为第一导电类型。第一沟槽15从源区14的表面贯穿阱区13延伸到外延层12。栅极16隔着栅极绝缘膜17形成于第一沟槽15内。非晶半导体层18形成于第一沟槽15内且隔着栅极绝缘膜17包裹栅极16的外底壁和外底壁两侧的角部。源区14和阱区13位于栅极16的两侧，接触区19位于源区14和/或阱区13远离栅极16的一侧。接触区19与阱区13连接，源极20与源区14、接触区19连接，漏极21与衬底11远离外延层12的一面连接。
本申请实施例中，第一导电类型可以为N型，第二导电类型为P型，沟槽栅半导体器件100则为形成有N沟道的反型沟槽栅金氧半场效晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)器件。当然，第一导电类型还可以为P型，第二导电类型为N型，沟槽栅半导体器100件则为形成有P沟道的MOSFET器件。本申请以第一导电类型可以为N型，第二导电类型为P型为例进行说明。
衬底11中掺杂有氮离子或磷离子等N型杂质，以使衬底11的电阻率达到0.01-0.025Ω·cm。衬底11的厚度为150微米(um)左右，具体例如为145um、150um或155um等。
外延层12的N型离子的掺杂浓度低于衬底11的N型离子掺杂浓度。外延层12的厚度为11um左右，具体例如为10.5um、11um、11.5um或12um等。
可选的，外延层12可以包括第一子外延层121和第二子外延层122。第一子外延层121位于衬底11和第二子外延层122之间。阱区13、源区14和非晶半导体层18形成于第二子外延层122上。第一子外延层121的掺杂浓度小于衬底11的掺杂浓度，且大于第二子外延层122的掺杂浓度。第一子外延层121的厚度为0.5um左右，具体例如为0.4um、0.5um或0.6um等。第二子外延层122的厚度为11um左右，具体例如为10um、10.6um、11um或11.4um等。第一子外延层121的掺杂浓度分布可以为单一浓度、台阶浓度或缓变浓度。第一子外延层121的掺杂浓度为台阶浓度或缓变浓度时，靠近衬底11一侧的掺杂浓度大于远离衬底11一侧的掺杂浓度。如此能够降低外延层12的导通电阻。
阱区13具体为在外延层12的表层进行离子注入形成的，注入的离子可以为铝离子、硼离子或镓离子等P型杂质。阱区13的P型杂质的注入浓度分布为均匀分布，注入结深大于或等于0.5um，且注入结深小于第二子外延层122的厚度。
源区14具体为在阱区13的表层进行离子注入形成的，注入的离子可以为氮离子或硼离子等N型杂质。源区14的N型杂质的表面注入浓度大于1.0×1019/cm3，注入结深为0.2um左右。源区14的厚度具体例如可以为0.18um、0.19um、2um或2.1um等。
接触区19与阱区13的导电类型同为P型，且二者具有连接关系。接触区19用于与源极20连接，接触区19的表面掺杂浓度大于1.0×1019/cm3，大于阱区13的掺杂浓度。如此能够降低阱区13电阻率，提高雪崩能量和半导体器件的可靠性。
在一些实施方式中，接触区19可以是选择性地在外延层12的表层注入铝离子、硼离子 或镓离子等P型杂质形成的，并且注入结深大于源区14的注入结深，以使接触区19与阱区13连接。该情况下，接触区19的表层与源区14的表层持平，制作工艺相对简单。
在另一些实施方式中，接触区19还可以是刻蚀外延层12形成第二沟槽(图未示)后，通过在阱区13附近注入P型杂质形成的。源极20伸入第二沟槽与接触区19连接，实现沟槽型的接触，如此能够降低源极和漏极之间的距离，从而降低沟槽栅半导体器件100的导通电阻。
可选地，源区14、阱区13和接触区19对称分布在第一沟槽15的两侧。
第一沟槽15具体是选择性地在源区14表面进行光刻、刻蚀形成的，刻蚀深度大于源区14和阱区13深度之和，以使第一沟槽15从源区14表面向下贯穿源区14和阱区13抵达外延层12。第一沟槽15深度大于0.7um，且小于第二外延层122、阱区13和源区14厚度之和。第一沟槽15的侧壁垂直于或大致垂直于源区14表面，第一沟槽15的底壁平行于或大致平行于源区14表面。第一沟槽15的角部呈圆弧状，即第一沟槽15侧壁与底壁连接处圆弧过渡，以减小第一沟槽15角部对栅极16和漏极21之间的电场的挤压，降低第一沟槽15角部的电场，提高沟槽栅的可靠性。
非晶半导体层18为在第一沟槽15的底壁和至少部分角部暴露的外延层12低温注入硼离子形成，从而非晶半导体层18覆盖第一沟槽15的底壁和至少部分角部。非晶半导体层18的硼离子注入浓度为1.0×1014/cm3，非晶半导体的厚度大于或等于0.1um。非晶半导体层18具有介电常数低，呈绝缘或半绝缘特性。非晶半导体层18可以为介电常数为8.9左右的材料构成，具体可以为非晶碳化硅，当然也可以是其他符合介电常数要求的非晶半导体材料构成，对此本申请不做限制。非晶碳化硅具有电子迁移率高，饱和电子漂移速度快和击穿场强高的特点，从而能够提高沟槽栅半导体器件100的可靠性。
衬底11和外延层12也可以均为碳化硅材料构成。碳化硅具有禁带宽度宽、临界击穿场强高、热导率大等优越的物理特性，使得碳化硅半导体器件具有耐高压、耐高温、开关速度快、开关损耗小等优点。当然，衬底和外延层还可以由氮化镓等其他宽禁带材料构成，本申请对此不做限制。
栅极绝缘膜17生长覆盖于第一沟槽15的侧壁、底壁和角部上，用于隔离栅极16与外延层12、阱区13和源区14的接触。栅极绝缘膜17的厚度大于50纳米(nm)，且小于第一沟槽15宽度的二分之一，即栅极绝缘膜17不能完全填充第一沟槽15。栅极绝缘膜17的厚度具体例如为50nm、55nm或60nm等。栅极绝缘膜17具体可以为二氧化硅膜、氮化硅膜或低介电常数膜等。
栅极16为在第一沟槽15内的栅极绝缘膜17表面淀积多晶硅生成的，栅极16将第一沟槽15全部填埋。由于第一沟槽15的角部为圆弧状，栅极16及栅极绝缘膜17同样为圆弧状，从而降低栅极16角部处的栅极绝缘膜17所承受的场强，能够提高栅极绝缘膜17的可靠性。并且，非晶半导体层18包裹栅极16的角部和底壁处的栅极绝缘膜17，能够提高栅极绝缘膜17的击穿场强。
源极20具体为在源区14和接触区19淀积金属而成，漏极21为在远离外延层12的一侧淀积金属而成。通过在源极20、漏极21和栅极16施加电压实现第一沟槽15栅半导体器件的导通或关断。
在一些其他的实施方式中，为了进一步提高沟槽栅半导体器件100的可靠性，沟槽栅半导体器件还包括屏蔽层22。屏蔽层22为在第一沟槽15底壁和角部对应的外延层12上注入P型杂质形成的，注入结深大于非晶半导体的离子注入结深，且小于第一沟槽15底壁到第一子外延层121的距离。屏蔽层22的注入结深例如为0.4um、0.5um、0.6um或0.7um等。屏蔽层的掺杂浓度为4.0×1013/cm3，大于第二子外延层122的掺杂浓度，因而屏蔽层22在还包含N型离子的情况下，实现导电类型呈P型。由于屏蔽层22的导电类型为P型，外延层12的导电类型为N型，屏蔽层22与外延层12能够形成PN结，从而避免电场集中于栅极16的角部处的栅极绝缘膜17，降低栅极绝缘膜17承受的场强。
屏蔽层22的注入范围大于非晶半导体层18的注入范围，从而能够屏蔽层22包裹非晶半导体层18，并以圆弧倒角延伸截止于栅极16的角部或侧壁处的栅极绝缘膜17上。如此使得栅极16的角部的栅极绝缘膜17被多层次地包裹起来，能够提高栅极绝缘膜17的击穿场强，从而提高沟槽栅半导体器件100的可靠性。
请参阅图2，图2是本申请提供的沟槽栅半导体器件的制造方法一实施例的流程示意图。本是实施例的制造方法用于制造上述的沟槽栅半导体器件。当制造的是单沟槽的沟槽栅半导体器件时，本实施例包括如下步骤：
201：在具有第一导电类型的衬底上沉积具有第一导电类型的外延层。
本申请中，第一导电类型可以为N型，第二导电类型为P型。当然，第一导电类型还可以为P型，第二导电类型为N型。本实施例以第一导电类型可以为N型，第二导电类型为P型为例进行说明。
本实施例中，衬底和外延层可以都是由碳化硅材料构成。碳化硅具有高的临界雪崩击穿电场强度和载流子饱和漂移速度、较高的热导率和载流子迁移率，能使沟槽栅半导体器件具有耐受高电压的能力、低的通态电阻、良好的导热性能和热稳定性以及强的耐受高温和射线辐射的能力。当然，衬底和外延层还可以由氮化镓等其他宽禁带材料构成，本申请对此不做限制。
在提供的电阻率为0.01-0.025Ω.cm的N+(重掺杂有N型杂质)的衬底上生长厚度为0.5um左右的第一子外延层，并对第一子外延层注入浓度低于衬底的N型杂质(如氮离子或磷离子等)，以使第一子外延层的导电类型为N型。然后继续在子外延层上生长厚度11um左右的第二子外延层，并对第一子外延层注入浓度低于第一子外延层的N型杂质，以使第二子外延层的导电类型也为N型。
202：在外延层的表层上注入第二导电类型的离子形成阱区。
具体地，在第二子外延层上淀积一层厚度为1.5um左右的用于掩蔽的二氧化硅介质层，之后采用光刻、刻蚀等工艺选择性地去除第二子外延层的表面的二氧化硅介质层，以形成阱区注入窗口，未被刻蚀的二氧化硅介质层用于做离子注入的掩蔽层。刻蚀可以采用干法刻蚀，使刻蚀沿垂直于第二子外延层的表面垂直的方向进行。
采用离子注入的方法通过阱区注入窗口向第二子外延层注入P型离子，形成浓度均匀分布、结深大于0.5um的阱区。离子注入是使离子化的各元素在高加速电压下碰撞外延层，使离子物理式地侵入外延层的晶格中。
203：在阱区的表层上注入第一导电类型的离子形成源区。
具体地，去除晶圆(即处于加工状态的沟槽栅半导体器件)表层剩余的二氧化硅介质层，重新淀积一层1.5um左右的二氧化硅介质层，并采用光刻、刻蚀工艺选择性地去除第二子外延层的表面的二氧化硅介质层，以在阱区的表层形成源区注入窗口。
采用离子注入的方法通过源区注入窗口注入氮离子等N型杂质，形成表面注入浓度大于1.0×1019/cm3、结深为0.2um的N型源区。
204：在外延层表层形成接触区。
去除晶圆表层剩余的二氧化硅介质层，重新淀积一层1.5um左右的二氧化硅介质层，采用光刻、刻蚀工艺选择性地去除第二子外延层的表面的二氧化硅介质层，以形成接触区注入窗口，接触区的注入窗口与源区表面不重合。
采用离子注入的方法通过接触区注入窗口向第二子外延层注入硼离子或铝离子等P型杂质，形成表面注入浓度大于1.0×1019/cm3、结深大于源区的接触区。接触区的P型离子注入浓度大于阱区的离子注入浓度。
由于离子注入过程中，高能离子会破坏晶圆的晶格，所以在形成接触区后，去除晶圆表面二氧化硅介质层，淀积一层20nm碳膜介质，对晶圆进行高温退火处理，从而回复晶格，并激活注入到外延层、阱区、源区和接触区的离子。退火处理具体例如是快速退火(rapid thermal anneal,RTA)，可以减少晶圆的升温和降温时间，提高激活效率，并且时间短还能够抑制杂质的分布变化，避免杂质扩散到其他区域。退火温度大于或等于1600度，且小于衬底及外延层的熔点。退火温度具体例如可以是1600度、1700度、1750度等。
碳膜用于抑制晶圆表面在高温退火的过程中变粗糙，退火后采用等离子体刻蚀方法将碳膜去除。
205：在源区表面光刻形成贯穿阱区延伸到外延层的第一沟槽。
在晶圆表面淀积一层1.5um左右的二氧化硅介质层，采用光刻、刻蚀等工艺选择性地去除晶圆表面的部分二氧化硅介质层，以形成沟槽栅刻蚀窗口。
采用电感应耦合等离子体(inductively coupled plasma，ICP)技术刻蚀沟槽栅刻蚀窗口暴露出的源区，形成贯穿源区、阱区并延伸到第二子外延层的第一沟槽。
ICP可提供高速率、高选择比以及低损伤的刻蚀，等离子体能够在低气压下保持稳定，因此能够更好地控制刻蚀形貌，以形成侧壁和底壁直线度好、无微沟槽形貌。
206：在第一沟槽的底壁及底角注入第二导电类型的离子形成非晶半导体层。
具体地，在晶圆表面淀积一层1.2um左右的二氧化硅介质层，采用光刻、刻蚀工艺刻蚀出沟槽栅工艺窗口，再在晶圆上淀积一层100nm左右二氧化硅介质层，通过离子注入向第一沟槽的底壁和角部注入硼离子，硼离子注入浓度为1.0×1014/cm3，注入结深大于或等于0.1um，注入温度小于50度，从而形成非晶半导体层。
207：在第一沟槽内生长栅极绝缘膜并淀积、掺杂形成多晶硅栅结构的栅极。
在生长栅极绝缘膜之前，通过高温氧化在晶圆表面(包括第一沟槽)形成大于20nm的牺牲氧化层。然后采用湿法工艺去除牺牲氧化层，从而降低晶圆表面的粗糙程度，使晶圆表面光滑。
在晶圆表面淀积一层300nm左右的二氧化硅介质层，通过光刻、刻蚀等工艺刻蚀出栅极的有源区(即第一沟槽在晶圆表面上对应的区域)。在晶圆表面高温氧化生长一层50nm栅极 绝缘膜，采用低压化学气相的方法在第一沟槽中淀积一层500nm的多晶硅，且多晶硅为原位掺杂，薄膜方阻小于30Ω/□，并采用光刻、刻蚀工艺形成多晶栅结构。
208：对晶圆进行欧姆接触埋置和布线处理。
具体地，在晶圆表面依次淀积一层100nm左右的二氧化硅介质层和800nm硼磷硅玻璃(boro-phospho-silicate glass，BPSG)层，并在980℃下进行高温回流，BPSG层在高温下具有流动性，能够使晶圆表面平坦化。之后再淀积一层100nm左右的二氧化硅介质层，并采用光刻、刻蚀工艺形成欧姆接触孔工艺窗口。在晶圆表面淀积一层镍(Ni)层，采用快速热处理(rapid thermal process，RTP)对Ni层进行退火，在欧姆接触孔工艺窗口暴露的晶圆表面形成硅镍(NiSi)合金，然后采用酸洗方式自对准去除未合金的Ni层。继续溅射一层5um左右的铝铜(AlCu)合金，并采用光刻、刻蚀工艺形成金属电极。在晶圆表面淀积一层二氧化硅或氮化硅介质层和聚酰亚胺薄膜层，采用光刻、刻蚀工艺形成正面源极和栅极电极。使用刻蚀或研磨抛光等工艺将晶圆背面(即衬底远离外延层的一侧)减薄至150um左右，晶圆背面蒸发一层Ni金属，采用激光进行高速退火，形成NiSi合金，晶圆背面蒸发钛/镍/银(Ti/Ni/Ag)多层金属，形成背面电极(即漏极)。
在另一些实施方式中，如图3所示，图3是本申请提供的沟槽栅半导体器件的制造方法另一实施例的流程示意图。若制造还包括屏蔽层的沟槽栅半导体器件，制造工艺如下：
301：在具有第一导电类型的衬底上沉积具有第一导电类型的外延层。
302：在外延层的表层上注入第二导电类型的离子形成阱区。
303：在阱区的表层上注入第一导电类型的离子形成源区。
步骤301-303与步骤201-203相同，故在此不再赘述。
304：在外延层表层形成接触区。
与204不同的是，本步骤形成接触区后不对晶圆进行高温退火处理。
305：在源区表面光刻形成贯穿阱区延伸到外延层的第一沟槽。
306：在第一沟槽的底壁及角部注入第二导电类型的离子形成屏蔽层。
在第一沟槽的侧壁淀积掩蔽膜，采用等离子体增强化学的气相沉积法(plasma enhanced chemical vapor deposition，PECVD)在晶圆表面淀积一层100nm厚度的二氧化硅介质层，采用离子注入的方法向第一沟槽底部和角部注入4.0×1013/cm3、结深大于0.4um的P型离子。
在形成屏蔽层后，去除表面全部介质，淀积一层20nm碳膜介质，对晶圆进行高温退火处理，从而激活注入到外延层、阱区、源区、接触区和屏蔽层的离子。退火处理具体例如是RTA或RTP，可以减少晶圆的升温和降温时间，提高激活效率，并且时间短还能够抑制杂质的分布变化，避免杂质扩散到其他区域。退火温度大于或等于1600度，且小于衬底及外延层的熔点。退火温度具体例如可以是1600度、1700度、1750度等。碳膜用于抑制晶圆表面在高温退火的过程中变粗糙，退火后采用等离子体刻蚀方法将碳膜去除。
307：在第一沟槽的底壁及底角注入第二导电类型的离子形成非晶半导体层。
308：在第一沟槽内生长栅极绝缘膜并淀积、掺杂形成多晶硅栅结构的栅极。
309：对晶圆进行欧姆接触埋置和布线处理。
步骤307-309与步骤206-208类似，故在此不再赘述。
对于双沟槽的沟槽栅半导体器件，如图4所示，图4是本申请提供的沟槽栅半导体器件的制造方法又一实施例的流程示意图，本实施例的制造工艺如下：
401：在具有第一导电类型的衬底上沉积具有第一导电类型的外延层。
402：在外延层的表层上注入第二导电类型的离子形成阱区。
403：在阱区的表层上注入第一导电类型的离子形成源区。
步骤401-403与步骤301-303相同，故在此不再赘述。
404：在源区表面光刻形成双沟槽。
在源区表面光刻形成第一沟槽和第二沟槽。其中，第一沟槽用于在其中形成栅极，第二沟槽用于在其底部形成接触区，以及在第二沟槽中生成部分源极。
第一沟槽和第二沟槽可以是同时刻蚀的，也可以是分开刻蚀的。第一沟槽的深度大于源区和阱区的厚度之和。第二沟槽的深度大于源区的深度，且小于源区和阱区的厚度之和，以使后续在第二沟槽底壁形成接触区与阱区连接。
405：在第二沟槽底部形成接触区。
在晶圆表面淀积一层1.5um左右的二氧化硅介质层，采用光刻、刻蚀工艺选择性地去除晶圆表面上的部分二氧化硅介质层，以形成接触区注入窗口，即第二沟槽的底壁。
采用离子注入的方法通过接触区注入窗口向第二沟槽的底壁注入硼离子或铝离子等P型杂质，形成表面注入浓度大于1.0×1019/cm3的接触区。接触区的P型杂质注入浓度大于阱区的离子注入浓度。
406：在沟槽的底壁及角部注入第二导电类型的离子形成屏蔽层。
407：在沟槽的底壁及底角注入第二导电类型的离子形成非晶半导体层。
408：在沟槽内生长栅极绝缘膜并淀积、掺杂形成多晶硅栅结构的栅极。
409：对晶圆进行欧姆接触埋置和布线处理。
步骤406-409与步骤306-309类似，故在此不再赘述。
本申请提出的沟槽栅半导体器件，采用垂直沟槽栅结构，通过改变沟道方向，提高沟道迁移率，能够降低比导通电阻。同时，采用沟槽栅结构，可减小元胞尺寸，提高电流密度，降低比导通电阻。在沟槽栅底部采用P+屏蔽层和非晶半导体层双层承担反向电压，降低栅极氧化膜的电场，提高栅极氧化膜长期使用可靠性。且本申请提出的器件制作方法，制作工艺简单，可以在沟槽形成后对沟槽底部进行离子注入，即P+屏蔽层和非晶半导体层的结深要求不高，对工艺设备性能参数低，制作成本低。
上述各实施方式中，对适用本申请的情况下的一例进行了说明，但能够适当进行设计变更等。例如，上述各实施方式中，作为栅极绝缘膜的例子而举出了因热氧化形成的氧化膜，但也可以是包含不通过热氧化形成的氧化膜或氮化膜等的膜。并且，第一沟槽的刻蚀也可以是在阱区或源区或接触区形成前等。
本申请依据实施例进行了描述，但应理解为本申请不限定于该实施例和构造。本申请还包含各种变形例及等价范围内的变形。进而，多种组合及形态、并且对它们增加或删除要素的其他组合及形态也包含在本申请的范畴及思想范围中。

Claims (14)

  1. 一种沟槽栅半导体器件，其特征在于，所述沟槽栅半导体器件包括：
    具有第一导电类型的衬底；
    具有所述第一导电类型的外延层，生长于所述衬底上；
    具有第二导电类型的阱区，形成于所述外延层的表层上；
    具有所述第一导电类型的源区，形成于所述阱区的表层上；
    第一沟槽，从所述源区的表面贯穿所述阱区延伸到所述外延层；
    栅极，隔着栅极绝缘膜形成于所述第一沟槽内；
    非晶半导体层，形成于所述第一沟槽内且隔着所述栅极绝缘膜包裹所述栅极的外底壁和所述外底壁两侧的角部，所述非晶半导体层由低介电常数材料构成。
  2. 根据权利要求1所述的沟槽栅半导体器件，其特征在于，所述非晶半导体层的厚度大于或等于0.1um。
  3. 根据权利要求1或2所述的沟槽栅半导体器件，其特征在于，所述沟槽栅半导体器件还包括：
    具有所述第二导电类型的屏蔽层，形成于所述第一沟槽底部的所述外延层上，所述屏蔽层包裹所述非晶半导体层，并以圆弧倒角延伸截止于所述栅极的角部或侧壁的所述栅极绝缘膜上。
  4. 根据权利要求1至3中任一项所述的沟槽栅半导体器件，其特征在于，所述屏蔽层的结深为大于或等于0.4um。
  5. 根据权利要求1至4中任一项所述的沟槽栅半导体器件，其特征在于，所述栅极的角部在所述第一沟槽栅半导体器件的纵切面呈圆弧状。
  6. 根据权利要求1至5中任一项所述的沟槽栅半导体器件，其特征在于，所述外延层包括第一子外延层和第二子外延层，所述第一子外延层位于所述衬底和所述第二子外延层之间，所述阱区、所述源区和所述非晶半导体层形成于所述第二子外延层上，所述第一子外延层的掺杂浓度小于所述衬底的掺杂浓度，且大于所述第二子外延层的掺杂浓度。
  7. 根据权利要求1至6中任一项所述的沟槽栅半导体器件，其特征在于，所述沟槽栅半导体器件还包括：
    具有所述第二导电类型的接触区，与所述阱区连接，所述接触区的掺杂浓度大于所述阱区的掺杂浓度；
    源极，与所述源区和所述接触区连接；
    漏极，与所述衬底远离所述外延层的一面连接。
  8. 根据权利要求1至7中任一项所述的沟槽栅半导体器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型；或
    所述第一导电类型为P型，所述第二导电类型为N型。
  9. 根据权利要求1至8中任一项所述的沟槽栅半导体器件，其特征在于，构成所述衬底和所述外延层的半导体材料为碳化硅，和/或所述非晶半导体为非晶碳化硅。
  10. 一种沟槽栅半导体器件的制造方法，其特征在于，所述制造方法包括：
    在具有第一导电类型的衬底上沉积具有所述第一导电类型的外延层；
    在所述外延层的表层上注入第二导电类型的离子形成阱区；
    在所述阱区的表层上注入所述第一导电类型的离子形成源区；
    在所述源区表面光刻形成贯穿所述阱区延伸到所述外延层的第一沟槽；
    在所述第一沟槽的底壁及底角注入所述第二导电类型的离子形成非晶半导体层；
    在所述第一沟槽内生长栅极绝缘膜并淀积、掺杂形成多晶硅栅结构的栅极。
  11. 根据权利要求10所述的制造方法，其特征在于，所述非晶半导体层的厚度大于或等于0.1um。
  12. 根据权利要求10或11所述的制造方法，其特征在于，所述在所述第一沟槽底壁及部分侧壁注入离子形成非晶半导体层之前，包括：
    在所述第一沟槽的侧壁淀积掩蔽膜；
    在所述第一沟槽的底壁及角部注入所述第二导电类型的离子形成屏蔽层，所述屏蔽层的注入深度大于所述非晶半导体层的注入深度，所述屏蔽层的掺杂浓度小于所述非晶半导体层的掺杂浓度。
  13. 根据权利要求12所述的制造方法，其特征在于，所述屏蔽层的注入结深大于或等于0.4um。
  14. 根据权利要求10至13中任一项所述的制造方法，其特征在于，所述栅极的角部在所述沟槽栅半导体器件的纵切面呈圆弧状。
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