WO2023072164A1 - 一种太阳能电池 - Google Patents

一种太阳能电池 Download PDF

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Publication number
WO2023072164A1
WO2023072164A1 PCT/CN2022/127773 CN2022127773W WO2023072164A1 WO 2023072164 A1 WO2023072164 A1 WO 2023072164A1 CN 2022127773 W CN2022127773 W CN 2022127773W WO 2023072164 A1 WO2023072164 A1 WO 2023072164A1
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Prior art keywords
layer
semiconductor substrate
doped polysilicon
solar cell
tunneling
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PCT/CN2022/127773
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English (en)
French (fr)
Inventor
胡匀匀
徐冠超
张倬涵
张学玲
陈达明
陈奕峰
冯志强
阿特玛特·皮亚同·皮特
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Trina Solar Co Ltd
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Trina Solar Co Ltd
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Priority to EP22886039.1A priority Critical patent/EP4425570A4/en
Priority to US18/704,439 priority patent/US20250006853A1/en
Publication of WO2023072164A1 publication Critical patent/WO2023072164A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/122—Active materials comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/129—Passivating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the application belongs to the technical field of crystalline silicon solar cell design, and relates to a passivated contact solar cell.
  • the currently used cell technology is Tunneling Oxide Passivation Contact (Topcon) technology, but due to the high light absorption coefficient of the polysilicon layer in the solar cell, it will cause serious parasitic absorption and current loss, so the conventional Topcon technology is only for cells.
  • the back (non-main light-receiving surface) has a passivation contact structure, and the front (main light-receiving surface) is still a traditional heavily doped or selectively doped emitter.
  • the purpose of this application is to provide a solar cell.
  • the metal-semiconductor substrate contact regions on the front and back sides of the semiconductor substrate can be passivated simultaneously, reducing the load on the contact regions on both sides.
  • Carrier recombination and putting the emitter on the back can reduce the carrier recombination in the front non-contact area, so as to obtain higher open circuit voltage and conversion efficiency than conventional Topcon.
  • the present application provides a solar cell, the solar cell includes a semiconductor substrate, and the front side of the semiconductor substrate has a metal contact area and a non-metal contact area;
  • the metal contact region is sequentially stacked with a first tunneling layer, a first doped polysilicon layer and a first metal electrode; wherein, the first metal electrode and the The first doped polysilicon layer is electrically connected;
  • a second tunneling layer, a second doped polysilicon layer, and a second metal electrode are sequentially stacked on the back of the semiconductor substrate in a direction away from the back of the semiconductor substrate;
  • the front side of the semiconductor substrate is the main light-receiving surface, and the back side of the semiconductor substrate is the non-main light-receiving surface; the conductivity type of the semiconductor substrate and the first doped polysilicon layer is the same, and the semiconductor substrate and the The conductivity types of the second doped polysilicon are different.
  • the metal-semiconductor substrate contact area on the front and back sides of the semiconductor substrate can be passivated at the same time, the carrier recombination in the contact area on both sides can be reduced, and the emitter can be placed on the back side, which can reduce the contact area of the non-contact area on the front side. Carrier recombination, resulting in higher open circuit voltage and conversion efficiency than conventional Topcon.
  • the non-metal contact area is covered with a first dielectric layer.
  • the non-metal contact region is provided with a third tunneling layer, a third doped polysilicon layer, and the first dielectric layer in sequence. layer.
  • the first tunneling layer and the third tunneling layer are arranged in the same layer; the first doped polysilicon layer and the third doped polysilicon layer are the same layers, and the thickness of the first doped polysilicon layer is greater than the thickness of the third doped polysilicon layer.
  • the thickness of the third tunneling layer is ⁇ 3 nm; the thickness of the third doped polysilicon layer is 1-100 nm, and the square resistance is 1-1000 ohm/sq.
  • the non-metal contact region of the semiconductor substrate is doped with a first lightly doped layer; the first lightly doped layer is covered with the first dielectric layer.
  • the square resistance of the first lightly doped layer is 50-1000 ohm/sq.
  • the first dielectric layer is made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, gallium oxide, zinc oxide, titanium oxide or magnesium fluoride Any one or any combination of multiples.
  • the front side of the semiconductor substrate is textured.
  • the thickness of the second tunneling layer is ⁇ 3 nm; the thickness of the second doped polysilicon layer is 10-1000 nm.
  • the back surface of the semiconductor substrate is a textured or polished surface.
  • the back surface of the semiconductor substrate is at least partially textured or at least partially polished.
  • the back surface of the semiconductor substrate is partly suede and partly polished.
  • the first tunneling layer and the second tunneling layer are dielectric films having a carrier tunneling effect and an interface passivation effect.
  • the first tunneling layer and the second tunneling layer are silicon oxide dielectric films or aluminum oxide dielectric films.
  • the thickness of the first tunneling layer is ⁇ 3 nm; the thickness of the first doped polysilicon layer is 10-1000 nm.
  • Fig. 1 is a structural schematic diagram 1 of a solar cell structure provided by a specific embodiment of the present application;
  • Fig. 2 is a structural schematic diagram II of a solar cell structure provided in a specific embodiment of the present application.
  • Fig. 3 is a structural schematic diagram III of a solar cell structure provided in a specific embodiment of the present application.
  • Fig. 4 is a structural schematic diagram 4 of a solar cell structure provided in a specific embodiment of the present application.
  • Fig. 5 is a schematic diagram of the back of the solar cell structure provided by a specific embodiment of the present application.
  • 1-semiconductor substrate 2-second tunneling layer; 3-second doped polysilicon layer; 4-second dielectric layer; 5-second metal electrode; 6-first tunneling layer; 1-doped polysilicon layer; 8-first lightly doped layer; 9-third doped polysilicon layer; 10-third tunneling layer; 11-first dielectric layer; 12-first metal electrode.
  • Heavily doped layer refers to a doped layer with a surface concentration not lower than 1e19cm -3 ;
  • Lightly doped layer refers to a doped layer with a surface concentration not higher than 1e20cm -3 .
  • the solar cell disclosed in this application adopts Topcon technology, and the passivation contact structure is formed by superimposing an ultra-thin tunnel oxide layer and a doped polysilicon layer on crystalline silicon.
  • the oxide layer is used to passivate the surface
  • the doped polysilicon layer is used as a carrier selective contact material, which can significantly reduce the carrier recombination in the metal-semiconductor contact area, and has good contact performance, thereby greatly improving the solar cell. efficiency.
  • the present application provides a solar cell, as shown in FIGS. 1-4 , the solar cell includes a semiconductor substrate 1 .
  • the semiconductor substrate 1 may be made of crystalline silicon. It should be noted that the semiconductor substrate 1 includes but not limited to crystalline silicon.
  • the semiconductor substrate 1 may be a semiconductor substrate of the first conductivity type.
  • the conductivity type is divided into a first conductivity type and a second conductivity type, and the first conductivity type and the second conductivity type may be N type or P type.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the first conductivity type is P type
  • the second conductivity type is N type.
  • the front and back of the semiconductor substrate 1 are defined, wherein the front of the semiconductor substrate 1 is the main light-receiving surface, and the back of the semiconductor substrate 1 is the non-main light-receiving surface.
  • the above-mentioned main light-receiving surface can be understood as the surface of the semiconductor substrate 1 facing sunlight when the solar cell is in use; the non-main light-receiving surface is another surface opposite to the main light-receiving surface.
  • the front side of the semiconductor substrate 1 has a metal contact region b and a non-metal contact region a.
  • the metal contact area a refers to the area in contact with the metal electrode.
  • the non-metal contact region b is other regions on the front surface of the semiconductor substrate 1 except the metal contact region a.
  • FIG. 1 mainly shows the structure of the metal contact region b of the semiconductor substrate in the solar cell.
  • the surface of the metal contact region b is sequentially provided with a first tunneling layer 6, a first doped polysilicon layer 7 and a first metal electrode 12, the first doped polysilicon layer 7 and the semiconductor
  • the first metal electrode 12 of the substrate 1 is electrically connected.
  • the first tunneling layer 6 is a tunneling layer of the metal contact region;
  • the first doped polysilicon layer 7 is a doped polysilicon layer of the first conductivity type in the metal contact region.
  • the conductivity type of the first doped polysilicon layer 7 is the same as that of the semiconductor substrate 1 . Same as P type, or same as N type.
  • the semiconductor substrate 1 is an N-type semiconductor
  • the first doped polysilicon layer 7 is N-type doped, and the doping element is phosphorus
  • the semiconductor substrate 1 is a P-type semiconductor
  • the first doped polysilicon layer 7 is The polysilicon layer 7 is P-type doped, and the doping element is boron.
  • the first tunneling layer 6 is prepared in the metal contact region b, the first doped polysilicon layer 7 is deposited on the first tunneling layer 6 and covers the first tunneling layer 6, the first metal electrode 12 and the first The doped polysilicon layer 7 contacts and realizes the conductive connection.
  • the first metal electrode 12 is a front metal electrode of the semiconductor substrate.
  • the first metal electrode 12 can be produced in a manner including but not limited to screen printing, electroplating, inkjet printing, laser transfer printing, vapor deposition or other metallization schemes.
  • the first tunneling layer 6 is used to passivate the substrate surface.
  • the thickness of the first tunneling layer 6 is between 0.5-3 nm.
  • the thickness of the first tunneling layer 6 may be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm. It should be understood that the thickness of the first tunneling layer 6 is not limited to the listed values, and other unlisted values within this range of values are also applicable.
  • the first doped polysilicon layer 7 is used as a heavily doped layer for forming good electrical contact with the first metal electrode 12 .
  • the surface concentration of the first doped polysilicon layer 7 is between 1e18-1e22 cm ⁇ 3 .
  • the first doped polysilicon layer 7 is used to form an ohmic contact with the first metal electrode 12 , and the heavily doped layer of the first doped polysilicon layer 7 can reduce the contact resistance when connected to the first metal electrode 12 .
  • the thickness of the first doped polysilicon layer 7 is 10-1000nm, for example, it can be 10nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, but it is not limited to the numerical values listed. Other unrecited values within the range also apply.
  • the thickness of the first doped polysilicon layer 7 can prevent the first metal electrode 12 from being etched downward by the metal paste during the preparation of the first tunneling layer 6 and the semiconductor substrate 1 . On the other hand, it is avoided that the thickness of the first doped polysilicon layer 7 is too thick to affect the light absorption effect.
  • a second tunneling layer 2 and a second doped polysilicon layer 3 are sequentially stacked on the back of the semiconductor substrate 1, and the second metal electrode 5 is in contact with the second doped polysilicon layer 3; wherein, the second doped polysilicon layer 3 A doped polysilicon layer of the second conductivity type.
  • a second dielectric layer 4 may also be provided on the side of the second doped polysilicon layer 3 facing away from the second tunneling layer 2 , and the second dielectric layer 4 is a back dielectric layer of the semiconductor substrate.
  • the back of the semiconductor substrate 1 is sequentially stacked with the second tunneling layer 2, the second doped polysilicon layer 3 and the second metal electrode 5.
  • the second metal electrode 5 is a metal electrode on the back side of the semiconductor substrate.
  • the solar cell in this application is a solar cell with passivation contact, which can simultaneously passivate the metal-semiconductor substrate contact regions on the front and back sides of the semiconductor substrate 1 during preparation, reducing the carrier recombination in the contact regions on both sides, Putting the emitter on the back can reduce the carrier recombination in the front non-contact area, so as to obtain higher open circuit voltage and conversion efficiency than conventional Topcon.
  • the non-metal contact region b can be set in different ways. The following descriptions will be made respectively in conjunction with the accompanying drawings.
  • FIG. 2 shows a specific arrangement of non-metallic contact regions.
  • the non-metallic contact region b is only covered with a dielectric layer (the dielectric layer on the front side of the semiconductor substrate).
  • this dielectric layer is defined as the first dielectric layer 11 .
  • the first dielectric layer 11 When the first dielectric layer 11 is provided, the first dielectric layer 11 is used to passivate the surface of the non-metallic contact region b, and the first dielectric layer 11 is used as an anti-reflection film, which can reduce the reflection loss of the incident light and increase the reflection loss of the incident light. utilization rate. Since the surface of the non-metal contact region b is not doped, the surface recombination current is very small after being passivated by the first dielectric layer 11 .
  • the first dielectric layer 11 includes, but is not limited to, one, two, and A laminated film composed of two or more types. In the embodiment of the present application, no specific limitation is made.
  • FIG. 3 shows another solar cell structure provided by an embodiment of the present application.
  • FIG. 3 shows that the non-metal contact region a of the semiconductor substrate 1 is doped with the first lightly doped layer 8 ; the first lightly doped layer 8 is covered with the first dielectric layer 11 .
  • the non-metal contact region a of the semiconductor substrate 1 is doped along the direction away from the front surface of the semiconductor substrate 1 to form the first lightly doped layer 8 .
  • the first lightly doped layer 8 is a lightly doped layer of the first conductivity type in the non-contact region.
  • the doping methods include but are not limited to thermal diffusion, ion implantation, printing of source-containing paste, and the like.
  • the first lightly doped layer 8 is used to form a front surface field, increase the carrier transmission length, and increase the open circuit voltage. Moreover, since the first lightly doped layer 8 is a lightly doped layer, the passivation quality requirement for the first dielectric layer 11 is not as high as that of the non-doped layer (semiconductor substrate 1 ). Therefore, the process complexity of preparing the first dielectric layer 11 can be reduced without affecting the passivation quality and cell efficiency.
  • the thickness of the first lightly doped layer 8 is very thin.
  • the dopant ions of the first conductivity type enter the substrate surface at a shallow depth, and the surface recombination current is relatively low.
  • the thickness of the first doped polysilicon layer 7 is greater than the thickness of the first lightly doped layer 8.
  • the square resistance of the first lightly doped layer 8 is 50 ⁇ 1000 ohm/sq.
  • it can be 50ohm/sq, 100ohm/sq, 200ohm/sq, 300ohm/sq, 400ohm/sq, 500ohm/sq, 600ohm/sq, 700ohm/sq, 800ohm/sq, 900ohm/sq, 1000ohm/sq, etc. resistance.
  • the square resistance of the first lightly doped layer 8 exemplified in the present application is not limited to the listed values, and other unlisted values within this range are also applicable.
  • the first lightly doped layer 8 is N-type doped, and the doping element is phosphorus; when the semiconductor substrate 1 is a P-type semiconductor, the first lightly doped layer 8 is P-type doping, the doping element is boron.
  • FIG. 4 shows the structure of another solar cell provided by an embodiment of the present application.
  • a third tunneling layer 10 is the tunneling layer of the non-metal contact region a
  • the third doped polysilicon layer 9 is the doped polysilicon layer of the first conductivity type in the non-metal contact region a
  • the first dielectric layer 11 is the semiconductor substrate Bottom front medium layer.
  • the non-metal contact region a is provided with a third tunneling layer 10 , a third doped polysilicon layer 9 and a first dielectric layer 11 in sequence.
  • the third tunneling layer 10 is prepared in the non-metal contact region a
  • the third doped polysilicon layer 9 covers the third tunneling layer 10
  • the first dielectric layer 11 covers the third doped polysilicon layer 9 .
  • the conductivity type of the third doped polysilicon layer 9 is the same as that of the semiconductor substrate 1 , both of which are the first conductivity type.
  • the third tunneling layer 10 and the third doped polysilicon layer 9 are stacked on the non-metal contact region a.
  • the third tunneling layer 10 is used to passivate the front surface of the semiconductor substrate 1
  • the third doped polysilicon layer 9 serves as a front surface field, which can increase the carrier transmission length and increase the open circuit voltage.
  • the first tunneling layer 6 and the third tunneling layer 10 are provided in the same layer, and the thickness of the first tunneling layer 6 may be greater than or equal to the thickness of the third tunneling layer 10 .
  • the above-mentioned setting in the same layer can be: the first tunneling layer 6 and the third tunneling layer 10 are located in the same layer structure during preparation, and their lower surfaces are located on the same surface (the front side of the semiconductor substrate 1), and the first tunneling layer 6 There may be a difference in height from the surface of the third tunneling layer 10 away from the semiconductor substrate 1 , and the difference may be a process difference during fabrication, or a difference formed by etching and thinning the third tunneling layer 10 .
  • the tunneling layer can be prepared simultaneously on the metal contact region b and the non-metal contact region a of the semiconductor substrate 1 to form the first tunneling layer 6 and the third tunneling layer 10 .
  • the first tunneling layer 6 and the third tunneling layer 10 are prepared by the above-mentioned preparation method, the first tunneling layer 6 and the third tunneling layer 10 are integrally formed.
  • the thickness of the third tunneling layer 10 is between 0.5-3 nm.
  • the thickness of the third tunneling layer 10 may be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm. It should be understood that the thickness of the third tunneling layer 10 is not limited to the listed values, and other unlisted values within this range of values are also applicable.
  • the thickness of the third doped polysilicon layer 9 is very thin.
  • the thickness of the first doped polysilicon layer 7 is greater than the thickness of the third doped polysilicon layer 9 to reduce light loss.
  • the third doped polysilicon layer 9 can be arranged in the same layer as the first doped polysilicon layer 7 , that is, the first doped polysilicon layer 7 and the third doped polysilicon layer 9 can be prepared on the same layer.
  • the first doped polysilicon layer 7 and the third doped polysilicon layer 9 are located in the same layer structure; wherein, the first doped polysilicon layer 7 is located on the side of the first tunneling layer 6 away from the semiconductor substrate 1, and the third doped polysilicon layer 9 is located on the side of the first tunneling layer 6 away from the semiconductor substrate 1.
  • the doped polysilicon layer 9 is located on the side of the third tunneling layer 10 away from the semiconductor substrate 1 .
  • the thickness of the first doped polysilicon layer 7 is greater than the thickness of the third doped polysilicon layer 9 .
  • a doped polysilicon layer can be prepared simultaneously in the metal contact region b and the non-metal contact region a of the semiconductor substrate 1, and then the doped polysilicon layer located in the non-metal contact region a can be removed by etching or other means thinned to form a third doped polysilicon layer 9 .
  • the first doped polysilicon layer 7 and the third doped polysilicon layer 9 are prepared by the above-mentioned preparation method, the first doped polysilicon layer 7 and the third doped polysilicon layer 9 form an integral structure.
  • the thickness of the third doped polysilicon layer 9 is 1-100 nm.
  • the thickness of the third doped polysilicon layer 9 is 10 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900nm, 1000nm, but not limited to the listed values, other unlisted values within this range are also applicable.
  • the square resistance of the third doped polysilicon layer 9 is 1 ⁇ 1000 ohm/sq. Exemplary, 1ohm/sq, 100ohm/sq, 200ohm/sq, 300ohm/sq, 400ohm/sq, 500ohm/sq, 600ohm/sq, 700ohm/sq, 800ohm/sq, 900ohm/sq, 1000ohm/sq, but not Not limited to the listed values, other unlisted values within the range of values are also applicable.
  • the third doped polysilicon layer 9 is N-type doped, and the doping element is phosphorus; when the semiconductor substrate 1 is a P-type semiconductor, the third doped polysilicon layer 9 is P-type doping, the doping element is boron.
  • a second tunneling layer 2, a second doped polysilicon layer 3 and a second dielectric layer 4 are sequentially stacked on the back of the semiconductor substrate 1, and the second metal electrode 5 is in contact with the second doped polysilicon layer 3.
  • the second doped polysilicon layer 3 is a doped polysilicon layer of the second conductivity type; the second dielectric layer 4 is a back dielectric layer of the semiconductor substrate.
  • the second tunneling layer 2 , the second doped polysilicon layer 3 and the second metal electrode 5 are sequentially stacked on the back of the semiconductor substrate 1 along the direction away from the back of the semiconductor substrate 1 .
  • the second metal electrode 5 is a metal electrode on the back side of the semiconductor substrate.
  • the solar cell in this application is a solar cell with passivation contact, which can simultaneously passivate the metal-semiconductor substrate contact regions on the front and back sides of the semiconductor substrate 1 during preparation, reducing the carrier recombination in the contact regions on both sides, Putting the emitter on the back can reduce the carrier recombination in the front non-contact area, so as to obtain higher open circuit voltage and conversion efficiency than conventional Topcon.
  • the thickness of the second tunneling layer 2 on the back of the semiconductor substrate 1 is ⁇ 3 nm.
  • it can be 1nm, 1.5nm, 2nm, 2.5nm, 3nm, but it is not limited to the enumerated numerical values, other unenumerated numerical values within this numerical range are also applicable.
  • the thickness of the second doped polysilicon layer 3 on the back side of the semiconductor substrate 1 is 10-1000nm, such as 10nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, but not limited to the listed The numerical value of , other unlisted numerical values in this numerical range are also applicable.
  • the conductivity type of the second doped polysilicon layer 3 is opposite to that of the semiconductor substrate 1; for example, when the semiconductor substrate 1 is an N-type semiconductor, the second doped polysilicon layer 3 is P-type doped, and the doped The element is boron; when the semiconductor substrate 1 is a P-type semiconductor, the second doped polysilicon layer 3 is N-type doped, and the doping element is phosphorus.
  • the front surface of the semiconductor substrate 1 is textured.
  • the front side of the semiconductor substrate 1 in this application can be conventional suede or a combination of other types of complete and incomplete suede, and the specific selection depends on the actual situation.
  • the back surface of the semiconductor substrate 1 can be a textured surface or a polished surface, that is, the entire surface of the back surface of the semiconductor substrate 1 is a textured surface, or the entire surface is a polished surface.
  • the back surface of the semiconductor substrate 1 may be at least partially textured or at least partially polished. At least part of the back of the semiconductor substrate 1 is a suede surface: part of the surface of the back of the semiconductor substrate 1 is a suede surface, or the entire surface of the back of the semiconductor substrate 1 is a suede surface; the back of the semiconductor substrate 1 is at least partially a polished surface: Part of the surface of the back surface of the semiconductor substrate 1 is a polished surface, or the entire surface of the back surface of the semiconductor substrate 1 is a polished surface.
  • the back side of the semiconductor substrate 1 is at least partly suede or at least partly polished, including but not limited to: the entire surface of the back side of the semiconductor substrate 1 is a polished surface; or the entire surface is a suede; or a part of the entire surface The surface is polished and some surfaces are suede.
  • the back side of the semiconductor substrate 1 in the present application can be a complete or incomplete suede surface (or a combination of the two), a polished surface (acid polishing, alkali polishing or a combination of the two) and a local suede surface, a local Polishing surface, etc., the specific choice depends on the actual situation.
  • the second tunneling layer 2 is a dielectric film with carrier tunneling and interface passivation.
  • the second tunneling layer 2 may be a silicon oxide dielectric film or an aluminum oxide dielectric film.
  • a dielectric layer is provided on the outer surface of the semiconductor substrate 1, including a first dielectric layer 11 on the front side of the semiconductor substrate and a second dielectric layer 4 on the back side of the semiconductor substrate.
  • the materials of the dielectric layer include silicon nitride, oxide Any one or combination of two or more of silicon, silicon oxynitride, silicon carbide, aluminum oxide, gallium oxide, zinc oxide, titanium oxide or magnesium fluoride.
  • An ultra-thin second tunneling layer 2 and a second doped polysilicon layer 3 are stacked between the back side of the semiconductor substrate 1 (not the main light-receiving surface) and the second metal electrode 5, which can significantly reduce the metal-semiconductor contact area. Carrier recombination, which greatly improves the efficiency of solar cells.
  • the second tunneling layer 2 is used on the back side of the semiconductor substrate 1 with a thickness of 0.5-3nm; the second doped polysilicon layer 3 is used to form the back emitter and forms a good electrical connection with the second metal electrode 5. In contact, its surface concentration is between 1e18-1e22cm -3 .
  • the outermost second dielectric layer 4 on the back surface is used to further passivate the back of the semiconductor substrate 1, and the second dielectric layer 4 acts as an anti-reflection film, which can reduce the reflection loss of incident light and increase the utilization rate of incident light.
  • preparation method of the second tunneling layer 2 in the present application includes but not limited to thermal oxygen method, wet chemical method, PECVD method, ALD method or excimer source dry oxygen method and the like. In the embodiment of the present application, the above preparation method may also be used for other tunneling layers.
  • the doped polysilicon layer (the first doped polysilicon layer 7, the second doped polysilicon layer 3 and the third doped polysilicon layer 9) in the present application can be prepared by chemical vapor deposition (CVD), including but not limited to LPCVD , PECVD, etc., and then heat-treated to form polysilicon.
  • the doping method can be in-situ doping or ex-situ doping. Ex-situ doping includes but is not limited to thermal diffusion, ion implantation, and source-containing paste printing.
  • the metal electrodes (the first metal electrode 12 and the second metal electrode) in the present application can be screen-printed metal paste, electroplated metal or ink-jet printing, laser transfer, or vapor-deposited metal, and the specific selection depends on the actual situation. It is fixed, and the dielectric layer may or may not have holes in the metal contact region b by means of laser or etching.

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Abstract

本申请提供了一种太阳能电池，太阳能电池包括半导体衬底(1)，半导体衬底(1)的正面具有金属接触区和非金属接触区；金属接触区依次层叠设置有第一隧穿层(6)、第一掺杂多晶硅层(7)以及第一金属电极(12)；第一金属电极(12)与第一掺杂多晶硅层(7)导电连接；半导体衬底(1)的背面依次层叠设置有第二隧穿层(2)、第二掺杂多晶硅层以及第二金属电极(5)。在本申请中，可以同时钝化半导体衬底的正面和背面的金属-半导体衬底接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。

Description

一种太阳能电池
本申请要求于2021年10月27日提交中国专利局、申请号为202111254049.6、申请名称为“一种钝化接触的太阳能电池”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于晶体硅太阳能电池设计技术领域，涉及一种钝化接触太阳能电池。
背景技术
在晶体硅太阳能电池中，表面复合及金属-半导体接触区的复合，是制约太阳能电池效率提升的关键因素。
目前采用的电池技术为隧穿氧化层钝化接触(Topcon)技术，但是由于太阳能电池中的多晶硅层的吸光系数较大，会导致严重的寄生吸收和电流损失，因此常规的Topcon技术针对电池只有背面(非主受光面)有钝化接触结构，正面(主受光面)仍是传统的重掺或选择性掺杂的发射极。
发明内容
针对现有技术存在的不足，本申请的目的在于提供一种太阳能电池，在本申请中，可以同时钝化半导体衬底的正面和背面的金属-半导体衬底接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。
为达此目的，本申请采用以下技术方案：
本申请提供了一种太阳能电池，所述太阳能电池包括半导体衬底，所述半导体衬底的正面具有金属接触区和非金属接触区；
沿远离所述半导体衬底的正面的方向，所述金属接触区依次层叠设置有第一隧穿层、第一掺杂多晶硅层以及第一金属电极；其中，所述第一金属电极与所述第一掺杂多晶硅层导电连接；
沿远离所述半导体衬底背面的方向，所述半导体衬底的背面依次层叠设置有第二隧穿层、第二掺杂多晶硅层以及第二金属电极；
所述半导体衬底的正面为主受光面，所述半导体衬底的背面为非主受光 面；所述半导体衬底和所述第一掺杂多晶硅层的导电类型相同，所述半导体衬底和所述第二掺杂多晶硅的导电类型不同。
在本申请中，可以同时钝化半导体衬底的正面和背面的金属-半导体衬底接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。
作为本申请的一种可选的技术方案，所述非金属接触区覆盖有第一介质层。
作为本申请的一种可选的技术方案，沿远离所述半导体衬底的正面方向，所述非金属接触区依次设置有第三隧穿层、第三掺杂多晶硅层以及所述第一介质层。
作为本申请的一种可选的技术方案，所述第一隧穿层与所述第三隧穿层同层设置；所述第一掺杂多晶硅层与所述第三掺杂多晶硅层为同层设置，且所述第一掺杂多晶硅层的厚度大于第三掺杂多晶硅层的厚度。
作为本申请的一种可选的技术方案，所述第三隧穿层的厚度为≤3nm；所述第三掺杂多晶硅层的厚度为1～100nm，方阻为1～1000ohm/sq。
作为本申请的一种可选的技术方案，所述半导体衬底的非金属接触区掺杂有第一轻掺杂层；所述第一轻掺杂层上覆盖有所述第一介质层。
作为本申请的一种可选的技术方案，所述的第一轻掺杂层的方阻为50～1000ohm/sq。
作为本申请的一种可选的技术方案，所述第一介质层为包括氮化硅、氧化硅、氮氧化硅、碳化硅、氧化铝、氧化镓、氧化锌、氧化钛或氟化镁中任意一种或任意多种的组合。
作为本申请的一种可选的技术方案，所述半导体衬底正面为绒面。
作为本申请的一种可选的技术方案，所述第二隧穿层厚度为≤3nm；所述第二掺杂多晶硅层的厚度为10～1000nm。
作为本申请的一种可选的技术方案，所述半导体衬底的背面为绒面或抛光面。
作为本申请的一种可选的技术方案，所述半导体衬底的背面至少部分为绒面或至少部分为抛光面。
所述半导体衬底的背面为部分绒面、部分抛光面的表面。
作为本申请的一种可选的技术方案，所述第一隧穿层和所述第二隧穿层为具有载流子隧穿作用和界面钝化作用的介质膜。
作为本申请的一种可选的技术方案，所述第一隧穿层和所述第二隧穿层为氧化硅介质膜或氧化铝介质膜。
作为本申请的一种可选的技术方案，所述第一隧穿层厚度为≤3nm；所述第一掺杂多晶硅层厚度为10～1000nm。
附图说明
图1为本申请一个具体实施方式提供的太阳能电池结构的结构示意图一；
图2为本申请一个具体实施方式提供的太阳能电池结构的结构示意图二；
图3为本申请一个具体实施方式提供的太阳能电池结构的结构示意图三；
图4为本申请一个具体实施方式提供的太阳能电池结构的结构示意图四；
图5为本申请一个具体实施方式提供的太阳能电池结构的背面示意图；
其中，1-半导体衬底；2-第二隧穿层；3-第二掺杂多晶硅层；4-第二介质层；5-第二金属电极；6-第一隧穿层；7-第一掺杂多晶硅层；8-第一轻掺杂层；9-第三掺杂多晶硅层；10-第三隧穿层；11-第一介质层；12-第一金属电极。
具体实施方式
需要理解的是，在本申请的描述中，术语“中心”、“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
需要说明的是，在本申请的描述中，除非另有明确的规定和限定，术语“设置”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的 普通技术人员而言，可以通过具体情况理解上述术语在本申请中的具体含义。
为方便理解本申请实施例提供的方案，首先介绍相关的名词：
重掺杂层：指代为表面浓度不低于1e19cm -3的掺杂层；
轻掺杂层：指代为表面浓度不高于1e20cm -3的掺杂层。
下面结合附图并通过具体实施方式来进一步说明本申请的技术方案。
本申请公开的太阳能电池采用Topcon技术，这种钝化接触结构是由在晶体硅上叠加一层超薄的隧穿氧化层和掺杂多晶硅层形成。其中氧化层用来钝化表面，掺杂多晶硅层作为载流子选择性接触材料，可以显著降低金属-半导体接触区的载流子复合，同时具有良好的接触性能，从而极大地提升太阳能电池的效率。
在一个具体实施方式中，本申请提供了一种太阳能电池，如图1-4所示，所述太阳能电池包括一半导体衬底1。在本申请实施例中，半导体衬底1可采用晶体硅材质。需要说明的是，半导体衬底1包括但不限于晶体硅。示例性的，半导体衬底1可为第一导电类型的半导体衬底。在本申请实施例中，将导电类型划分为第一导电类型和第二导电类型，第一导电类型和第二导电类型可为N型或P型。如第一导电类型为N型，第二导电类型为P型；或，第一导电类型为P型，第二导电类型为N型。
为方面描述，定义了半导体衬底1的正面和背面，其中，半导体衬底1的正面为主受光面，半导体衬底1的背面为非主受光面。上述主受光面可理解为太阳能电池在使用时半导体衬底1朝向阳光的表面；非主受光面为与主受光面相对的另一表面。
半导体衬底1的正面具有金属接触区b和非金属接触区a。其中，金属接触区a指代为与金属电极接触的区域。非金属接触区b为半导体衬底1的正面上除去金属接触区a外的其他区域。
参考图1，图1中主要示出太阳能电池中半导体衬底的金属接触区b部分的结构。沿远离半导体衬底1的正面的方向，金属接触区b表面依次层叠设置有第一隧穿层6、第一掺杂多晶硅层7以及第一金属电极12，第一掺杂多晶硅层7和半导体衬底1的第一金属电极12导电连接。其中，第一隧穿层6为金属接触区的隧穿层；第一掺杂多晶硅层7为金属接触区第一导电类型的掺杂多晶硅层。也即在本申请实施例中，第一掺杂多晶硅层7与半导体衬底1的导电类型相同。如同为P型，或同为N型。示例性的，在半导体衬底1为 N型半导体时，第一掺杂多晶硅层7为N型掺杂，掺杂元素为磷元素；在半导体衬底1为P型半导体时，第一掺杂多晶硅层7为P型掺杂，掺杂元素为硼元素。
在具体设置时，第一隧穿层6制备在金属接触区b，第一掺杂多晶硅层7沉积在第一隧穿层6并覆盖第一隧穿层6，第一金属电极12与第一掺杂多晶硅层7接触，并实现导电连接。其中，第一金属电极12为半导体衬底正面金属电极。在制备时，第一金属电极12的制作方式包括但不限于丝网印刷、电镀、喷墨打印、激光转印、蒸镀或其他金属化方案。
第一隧穿层6用于钝化衬底表面。在本申请实施例中，第一隧穿层6的厚度过厚会影响载流子的隧穿和收集，且第一隧穿层6的厚度过薄对半导体衬底1的钝化效果不好。因此，在本申请实施例中，第一隧穿层6厚度为介于0.5～3nm。示例性的，第一隧穿层6的厚度可以是0.5nm、1nm、1.5nm、2nm、2.5nm、3nm。应理解，第一隧穿层6的厚度并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
第一掺杂多晶硅层7作为重掺杂层，用于和第一金属电极12之间形成良好的电学接触。在本申请实施例中，第一掺杂多晶硅层7的表面浓度在1e18-1e22cm -3之间。第一掺杂多晶硅层7用于和第一金属电极12形成欧姆接触，第一掺杂多晶硅层7采用重掺杂层可降低与第一金属电极12连接时的接触电阻。
第一掺杂多晶硅层7的厚度为10～1000nm，例如可以是10nm、100nm、200nm、300nm、400nm、500nm、600nm、700nm、800nm、900nm、1000nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。在采用上述厚度时，一方面可通过第一掺杂多晶硅层7的厚度阻挡第一金属电极12在制备时，金属浆料向下蚀刻第一隧穿层6和半导体衬底1。另一方面避免第一掺杂多晶硅层7的厚度过厚影响对光的吸收效果。
在半导体衬底1的背面依次层叠设置有第二隧穿层2和第二掺杂多晶硅层3，第二金属电极5和第二掺杂多晶硅层3接触；其中，第二掺杂多晶硅层3为第二导电类型的掺杂多晶硅层。另外，也可在第二掺杂多晶硅层3背离第二隧穿层2的一面设置第二介质层4，该第二介质层4为半导体衬底背面介质层。
在设置时，沿远离半导体衬底1的背面的方向，半导体衬底1的背面依 次层叠设置有第二隧穿层2、第二掺杂多晶硅层3以及第二金属电极5。第二金属电极5为半导体衬底背面金属电极。
在本申请中的太阳能电池为一钝化接触的太阳能电池，在制备时可以同时钝化半导体衬底1的正面和背面的金属-半导体衬底接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。
在本申请实施例中，非金属接触区b可采用不同的方式设置。下面结合附图分别进行说明。
参考图2，图2示出了一种具体的非金属接触区的设置方式。在图2中非金属接触区b仅覆盖有介质层(半导体衬底正面介质层)。为方面描述，将该介质层定义为第一介质层11。
在设置该第一介质层11时，第一介质层11用于钝化非金属接触区b的表面，并且第一介质层11作为减反射膜，能够减少入射光的反射损失，增加入射光的利用率。由于非金属接触区b表面无掺杂，因此，在通过第一介质层11钝化后表面复合电流很小。
该第一介质层11包括但不限于氮化硅、氧化硅、氮氧化硅、碳化硅、氧化铝、氧化镓、氧化锌、氧化钛、氟化镁等介质层中的一种、两种及两种以上组成的叠层膜。在本申请实施例中，不做具体限定。
参考图3，图3示出了本申请实施例提供的另一太阳能电池结构。在图3中示出了半导体衬底1的非金属接触区a掺杂有第一轻掺杂层8；在第一轻掺杂层8上覆盖有第一介质层11。
示例性的，在设置时，沿远离半导体衬底1的正面方向，在半导体衬底1的非金属接触区a掺杂以形成第一轻掺杂层8。第一轻掺杂层8为非接触区的第一导电类型的轻掺杂层。在具体掺杂时，掺杂方式包括但不限于热扩散、离子注入、含源浆料印刷等。
该第一轻掺杂层8用于形成前表面场，增加载流子的传输长度，提高开路电压。并且，由于第一轻掺杂层8为轻掺杂层，对第一介质层11的钝化质量要求没有无掺杂层(半导体衬底1)高。因此，可以在不影响钝化质量及电池效率的前提下，降低制备第一介质层11的工艺复杂程度。
在设置第一轻掺杂层8时，第一轻掺杂层8的厚度很薄。第一导电类型的掺杂离子进入衬底表面的深度很浅，表面复合电流较低。示例性的，第一 掺杂多晶硅层7的厚度大于第一轻掺杂层8的厚度。
在形成第一轻掺杂层8时，第一轻掺杂层8的方阻为50～1000ohm/sq。例如可以是50ohm/sq、100ohm/sq、200ohm/sq、300ohm/sq、400ohm/sq、500ohm/sq、600ohm/sq、700ohm/sq、800ohm/sq、900ohm/sq、1000ohm/sq等不同的方阻。但应理解本申请示例的第一轻掺杂层8的方阻但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
在半导体衬底1为N型半导体时，第一轻掺杂层8为N型掺杂，掺杂元素为磷元素；在半导体衬底1为P型半导体时，第一轻掺杂层8为P型掺杂，掺杂元素为硼元素。
图3中所示的半导体衬底1的背面的结构可参考图2中的相关描述，在此不再赘述。
参考图4，图4示出了本申请实施例提供的另一太阳能电池的结构。在图4所示的太阳能电池中，在非金属接触区a设置有第三隧穿层10、第三掺杂多晶硅层9以及第一介质层11。其中，第三隧穿层10为非金属接触区a的隧穿层，第三掺杂多晶硅层9为非金属接触区a第一导电类型的掺杂多晶硅层；第一介质层11为半导体衬底正面介质层。
示例性的，沿远离半导体衬底1的正面方向，非金属接触区a依次设置有第三隧穿层10、第三掺杂多晶硅层9以及第一介质层11。其中，第三隧穿层10制备在非金属接触区a，第三掺杂多晶硅层9覆盖第三隧穿层10，第一介质层11覆盖第三掺杂多晶硅层9。其中，第三掺杂多晶硅层9与半导体衬底1的导电类型相同，均为第一导电类型。
在采用上述结构时，在非金属接触区a叠加第三隧穿层10和第三掺杂多晶硅层9。其中，第三隧穿层10用于钝化半导体衬底1的正面，第三掺杂多晶硅层9作为前表面场，可以增加载流子的传输长度，提高开路电压。
在设置第三隧穿层10时，第一隧穿层6与第三隧穿层10同层设置，且第一隧穿层6的厚度可以大于或者等于第三隧穿层10的厚度。上述同层设置可以为：第一隧穿层6和第三隧穿层10在制备时，位于同一层结构，其下表面位于同一表面(半导体衬底1的正面)，第一隧穿层6和第三隧穿层10背离半导体衬底1的表面的高度可存在差异，该差异可为工艺制备时的工艺差异，或者对第三隧穿层10进行刻蚀减薄形成的差异。示例性的，在制备时，可在半导体衬底1的金属接触区b和非金属接触区a同时制备隧穿层，以形 成第一隧穿层6和第三隧穿层10。在采用上述制备方式制备第一隧穿层6和第三隧穿层10时，第一隧穿层6和第三隧穿层10为一体成型的结构。
第三隧穿层10厚度过厚会影响载流子的隧穿和收集，且第三隧穿层10的厚度过薄对半导体衬底1的钝化效果不好。因此，在本申请实施例中，第三隧穿层10厚度介于0.5～3nm。示例性的，第三隧穿层10的厚度可以是0.5nm、1nm、1.5nm、2nm、2.5nm、3nm。应理解，第三隧穿层10的厚度并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
在设置第三掺杂多晶硅层9时，由于第三掺杂多晶硅层9的吸光系数较大，第三掺杂多晶硅层9的厚度越厚，造成的光损失越多。因此，在本申请实施例中第三掺杂多晶硅层9的厚度很薄。示例性的，第一掺杂多晶硅层7的厚度大于所述第三掺杂多晶硅层9的厚度，以降低光损。
另外，第三掺杂多晶硅层9可与第一掺杂多晶硅层7为同层设置，也即可将第一掺杂多晶硅层7和第三掺杂多晶硅层9在同一层制备而成。在制备时，第一掺杂多晶硅层7和第三掺杂多晶硅层9位于同一层结构；其中，第一掺杂多晶硅层7位于第一隧穿层6背离半导体衬底1的一面，第三掺杂多晶硅层9位于第三隧穿层10背离半导体衬底1的一面。另外，在设置时，第一掺杂多晶硅层7的厚度大于第三掺杂多晶硅层9的厚度。示例性的，可在半导体衬底1的金属接触区b和非金属接触区a同时制备掺杂多晶硅层，之后在通过刻蚀或者其他的手段，将位于非金属接触区a的掺杂多晶硅层减薄，形成第三掺杂多晶硅层9。在采用上述制备方式制备第一掺杂多晶硅层7和第三掺杂多晶硅层9时，第一掺杂多晶硅层7和第三掺杂多晶硅层9为一体成型的结构。
作为一个示例，第三掺杂多晶硅层9的厚度为1～100nm，示例性的，第三掺杂多晶硅层9的厚度为10nm、100nm、200nm、300nm、400nm、500nm、600nm、700nm、800nm、900nm、1000nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
第三掺杂多晶硅层9的方阻为1～1000ohm/sq。示例性的，1ohm/sq、100ohm/sq、200ohm/sq、300ohm/sq、400ohm/sq、500ohm/sq、600ohm/sq、700ohm/sq、800ohm/sq、900ohm/sq、1000ohm/sq，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
在半导体衬底1为N型半导体时，第三掺杂多晶硅层9为N型掺杂，掺 杂元素为磷元素；在半导体衬底1为P型半导体时，第三掺杂多晶硅层9为P型掺杂，掺杂元素为硼元素。
图4中所示的半导体衬底1的背面的结构可参考图2中的相关描述，在此不再赘述。
参考图5，在半导体衬底1的背面依次层叠设置有第二隧穿层2、第二掺杂多晶硅层3和第二介质层4，第二金属电极5和第二掺杂多晶硅层3接触。第二掺杂多晶硅层3为第二导电类型的掺杂多晶硅层；第二介质层4为半导体衬底背面介质层。
在设置时，沿远离半导体衬底1的背面的方向，半导体衬底1的背面依次层叠设置有第二隧穿层2、第二掺杂多晶硅层3以及第二金属电极5。第二金属电极5为半导体衬底背面金属电极。
在本申请中的太阳能电池为一钝化接触的太阳能电池，在制备时可以同时钝化半导体衬底1的正面和背面的金属-半导体衬底接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。
半导体衬底1背面的第二隧穿层2厚度为≤3nm。例如可以是1nm、1.5nm、2nm、2.5nm、3nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
半导体衬底1背面的第二掺杂多晶硅层3厚度为10～1000nm，例如可以是10nm、100nm、200nm、300nm、400nm、500nm、600nm、700nm、800nm、900nm、1000nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
第二掺杂多晶硅层3的导电类型与半导体衬底1的导电类型相反；示例性的，在半导体衬底1为N型半导体时，第二掺杂多晶硅层3为P型掺杂，掺杂元素为硼元素；在半导体衬底1为P型半导体时，第二掺杂多晶硅层3为N型掺杂，掺杂元素为磷元素。
作为一个示例，在具体制备半导体衬底1时，半导体衬底1正面为绒面。需要说明的是，本申请中的半导体衬底1正面可以是常规的绒面或其他类型完整和不完整绒面相结合，具体选择依照实际情况而定。
半导体衬底1背面可为绒面或者抛光面，也即半导体衬底1背面整个表面为绒面，或者整个表现为抛光面。
另外，半导体衬底1的背面还可采用至少部分为绒面或至少部分为抛光面。半导体衬底1背面至少部分为绒面为：半导体衬底1背面中的部分表面为绒面，或半导体衬底1背面的整个表面为绒面；半导体衬底1背面至少部分为抛光面为：半导体衬底1背面中的部分表面为抛光面，或半导体衬底1背面的整个表面为抛光面。
在半导体衬底1的背面至少部分为绒面或至少部分为抛光面时，包括但不限定：半导体衬底1背面的整个表面为抛光面；或者整个表面为绒面；或者整个表面中的部分表面为抛光面、部分表面为绒面。
通过上述描述可看出，本申请中半导体衬底1背面可以是完整或不完整的绒面(或二者结合)、抛光面(酸抛、碱抛或二者结合)以及局部绒面、局部抛光面等，具体选择依照实际情况而定。
第二隧穿层2为具有载流子隧穿作用和界面钝化作用的介质膜，示例性的，第二隧穿层2可为氧化硅介质膜或氧化铝介质膜。
在本申请实施例中，半导体衬底1外表面均设置有介质层，包括半导体衬底正面第一介质层11和半导体衬底背面第二介质层4，介质层的材质包括氮化硅、氧化硅、氮氧化硅、碳化硅、氧化铝、氧化镓、氧化锌、氧化钛或氟化镁的任意一种和两种及以上的组合。
在半导体衬底1背面(非主受光面)和第二金属电极5之间叠加一层超薄的第二隧穿层2和第二掺杂多晶硅层3，可以显著降低金属-半导体接触区的载流子复合，从而极大地提升太阳能电池的效率。其中，第二隧穿层2用于半导体衬底1的背面，厚度为0.5-3nm；第二掺杂多晶硅层3用于形成背面发射极，并且与第二金属电极5之间形成良好的电学接触，其表面浓度在1e18-1e22cm -3之间。背表面最外层的第二介质层4用于进一步钝化半导体衬底1的背面，并且第二介质层4作为减反射膜，能够减少入射光的反射损失，增加入射光的利用率。
需要说明的是，本申请中的第二隧穿层2制备方法包括但不限于热氧法、湿化学法、PECVD法、ALD法或准分子源干氧法等。在本申请实施例中，对于其他的隧穿层也可采用上述制备方法。
本申请中的掺杂多晶硅层(第一掺杂多晶硅层7、第二掺杂多晶硅层3及第三掺杂多晶硅层9)可以是由化学气相沉积(CVD)法制备，包括但不限于LPCVD、PECVD等，再经过热处理形成多晶硅，其掺杂方式可以是原位掺杂 或非原位掺杂，非原位掺杂包括但不限于热扩散、离子注入、含源浆料印刷等方式。
本申请中的金属电极(第一金属电极12及第二金属电极)可以为丝网印刷的金属浆料、电镀金属或喷墨打印、激光转印、蒸镀的金属，具体选择依照实际情况而定，且介质层在金属接触区b可以通过激光、刻蚀等手段开孔也可以不开孔。
申请人声明，以上所述仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，所属技术领域的技术人员应该明了，任何属于本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，均落在本申请的保护范围和公开范围之内。

Claims (15)

  1. 一种太阳能电池，所述太阳能电池包括半导体衬底(1)，所述半导体衬底(1)的正面具有金属接触区和非金属接触区；
    沿远离所述半导体衬底(1)的正面的方向，所述金属接触区依次层叠设置有第一隧穿层(6)、第一掺杂多晶硅层(7)以及第一金属电极(12)；其中，所述第一金属电极(12)与所述第一掺杂多晶硅层(7)导电连接；
    沿远离所述半导体衬底(1)背面的方向，所述半导体衬底(1)的背面依次层叠设置有第二隧穿层(2)、第二掺杂多晶硅层(3)以及第二金属电极(5)；
    所述半导体衬底(1)的正面为主受光面，所述半导体衬底(1)的背面为非主受光面；所述半导体衬底(1)和所述第一掺杂多晶硅层(7)的导电类型相同，所述半导体衬底(1)和所述第二掺杂多晶硅的导电类型不同。
  2. 根据权利要求1所述的太阳能电池，所述非金属接触区覆盖有第一介质层(11)。
  3. 根据权利要求2所述的太阳能电池，沿远离所述半导体衬底(1)的正面方向，所述非金属接触区依次设置有第三隧穿层(10)、第三掺杂多晶硅层(9)以及所述第一介质层(11)。
  4. 根据权利要求3所述的太阳能电池，所述第一隧穿层(6)与所述第三隧穿层(10)同层设置；所述第一掺杂多晶硅层(7)与所述第三掺杂多晶硅层(9)为同层设置，且所述第一掺杂多晶硅层(7)的厚度大于第三掺杂多晶硅层(9)的厚度。
  5. 根据权利要求3或4所述的太阳能电池，所述第三隧穿层(10)的厚度为≤3nm；所述第三掺杂多晶硅层(9)的厚度为1～100nm，方阻为1～1000ohm/sq。
  6. 根据权利要求2所述的太阳能电池，所述半导体衬底(1)的非金属接触区掺杂有第一轻掺杂层(8)；所述第一轻掺杂层(8)上覆盖有所述第一介质层(11)。
  7. 根据权利要求6所述的太阳能电池，所述的第一轻掺杂层(8)的方阻为50～1000ohm/sq。
  8. 根据权利要求2～7任一项所述的太阳能电池，所述第一介质层(11)为包括氮化硅、氧化硅、氮氧化硅、碳化硅、氧化铝、氧化镓、氧化锌、氧化 钛或氟化镁中任意一种或任意多种的组合。
  9. 根据权利要求1～8任一项所述的太阳能电池，所述半导体衬底(1)正面为绒面。
  10. 根据权利要求1～9任一项所述的太阳能电池，所述第二隧穿层(2)厚度为≤3nm；所述第二掺杂多晶硅层(3)的厚度为10～1000nm。
  11. 根据权利要求1～10任一项所述的太阳能电池，所述半导体衬底(1)的背面为绒面或抛光面。
  12. 根据权利要求1～10任一项所述的太阳能电池，所述半导体衬底(1)的背面至少部分为绒面或至少部分为抛光面。
  13. 根据权利要求1～12任一项所述的太阳能电池，所述第一隧穿层(6)和所述第二隧穿层(2)均为具有载流子隧穿作用和界面钝化作用的介质膜。
  14. 根据权利要求13所述的太阳能电池，所述第一隧穿层(6)和所述第二隧穿层(2)为氧化硅介质膜或氧化铝介质膜。
  15. 根据权利要求1～14任一项所述的太阳能电池，所述第一隧穿层(6)厚度为≤3nm；所述第一掺杂多晶硅层(7)厚度为10～1000nm。
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