WO2023087323A1 - 光电收发器组件及其制造方法 - Google Patents

光电收发器组件及其制造方法 Download PDF

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Publication number
WO2023087323A1
WO2023087323A1 PCT/CN2021/132160 CN2021132160W WO2023087323A1 WO 2023087323 A1 WO2023087323 A1 WO 2023087323A1 CN 2021132160 W CN2021132160 W CN 2021132160W WO 2023087323 A1 WO2023087323 A1 WO 2023087323A1
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WIPO (PCT)
Prior art keywords
integrated circuit
heat conduction
layer
molding compound
bumps
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/132160
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English (en)
French (fr)
Inventor
张文奇
王猛
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP21964472.1A priority Critical patent/EP4421852A4/en
Priority to PCT/CN2021/132160 priority patent/WO2023087323A1/zh
Priority to CN202180102263.1A priority patent/CN117941043A/zh
Publication of WO2023087323A1 publication Critical patent/WO2023087323A1/zh
Priority to US18/669,690 priority patent/US20240302611A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4248—Feed-through connections for the hermetical passage of fibres through a package wall
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4255—Moulded or casted packages
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4256—Details of housings
    • G02B6/426—Details of housings mounting, engaging or coupling of the package to a board, a frame or a panel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4266—Thermal aspects, temperature control or temperature monitoring
    • G02B6/4268—Cooling
    • G02B6/4269—Cooling with heat sinks or radiation fins
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects
    • G02B6/428—Electrical aspects containing printed circuit boards [PCB]

Definitions

  • Embodiments of the present disclosure generally relate to the field of electronic devices, and more particularly, to an optoelectronic transceiver assembly and a method of manufacturing the same.
  • optical transceiver module needs to integrate the optical chip (also known as photonic integrated circuit, abbreviated as PIC) and electrical chip (also called electronic integrated circuit, abbreviated as EIC) at the same time, and also needs to realize the optical fiber array unit (FAU) and the optical chip.
  • PIC photonic integrated circuit
  • EIC electronic integrated circuit
  • FAU optical fiber array unit
  • FIG. 1 shows a schematic structural diagram of a conventional optical transceiver module 100 .
  • the optical transceiver module 100 includes a substrate 10 , an electronic integrated circuit 20 , a photonic integrated circuit 30 and an optical fiber 71 .
  • the electronic integrated circuit 20 and the photonic integrated circuit 30 are arranged on the substrate 10 and are spaced apart from each other by a certain distance.
  • the electronic integrated circuit 20 and the photonic integrated circuit 30 are electrically coupled to each other through the bonding wire 50 .
  • Electronic integrated circuit 20 and photonic integrated circuit 30 are also electrically coupled to substrate 10 via bonding wires 50 , respectively.
  • the optical fiber 71 is optically coupled to an optical port on the sidewall of the photonic integrated circuit 30 . Since each bonding wire 50 has a certain arc height and a relatively long length, it will generate relatively large parasitic effects such as parasitic inductance and parasitic capacitance, thereby resulting in relatively large power consumption.
  • TSV Thine-Silicon- Via
  • Embodiments of the present disclosure provide an optoelectronic transceiver assembly and a manufacturing method thereof, aiming to solve the above-mentioned problems and other potential problems existing in conventional integration schemes of optical chips and electrical chips.
  • an optoelectronic transceiver assembly comprising: an electronic integrated circuit comprising a first surface, a second surface opposite to the first surface, and a A first side wall between the second surfaces; a molding compound, which plastic-seals the electronic integrated circuit around the first side wall, and the molding compound includes a third surface close to the first surface and a third surface close to the second The fourth surface of the surface, and the molding compound is provided with one or more overmolding compound through holes extending from the third surface to the fourth surface; the first rewiring layer is arranged on the first surface and the third surface, and includes a plurality of first bumps electrically coupled to the first surface and the one or more overmolding compound via holes; the second rewiring layer is disposed on the first surface On the second surface and the fourth surface, and including a plurality of second bumps electrically coupled to the second surface and the one or more overmolded via holes; and a photonic integrated circuit, via a plurality of first
  • the electronic integrated circuit is pre-molded with a molding compound and through-molding vias are provided in the molding compound for electrical coupling between the photonic integrated circuit and the substrate.
  • photonic integrated circuits can be reliably integrated with electronic integrated circuits.
  • the first redistribution layer, the second redistribution layer, and the via hole through the plastic encapsulant are used to realize the electrical coupling between the photonic integrated circuit and the electronic integrated circuit and between the photonic integrated circuit and the electronic integrated circuit and the substrate,
  • the use of traditional bonding wires with a certain arc height and relatively long length is avoided, so parasitic effects caused by the use of bonding wires can be avoided, thereby reducing power consumption of optical transceiver components.
  • the second redistribution layer and through-molding through holes to realize the electrical coupling between the photonic integrated circuit and the electronic integrated circuit and the connection between the photonic integrated circuit and the electronic integrated circuit and the substrate
  • the electrical coupling avoids the complicated manufacturing process of forming TSVs in the photonic integrated circuit or the electronic integrated circuit, and does not need to set a stress safe area in the photonic integrated circuit or the electronic integrated circuit, so that the cost of the optical transceiver component can be significantly reduced.
  • the optoelectronic transceiver assembly further includes an optical fiber array unit optically coupled to the photonic integrated circuit, wherein the molding compound further includes a The notch is used to avoid the optical fiber array unit.
  • the molding compound further includes a The notch is used to avoid the optical fiber array unit.
  • the first surface and the third surface are in the same plane.
  • the first surface and the third surface being in the same plane can simplify the manufacturing process when pre-molding the electronic integrated circuit with the molding compound, and facilitate the formation of the first rewiring on these two surfaces. layer.
  • the second surface is in the same plane as the fourth surface.
  • the second surface and the fourth surface being in the same plane can simplify the manufacturing process when pre-molding the electronic integrated circuit with the molding compound, and facilitate the formation of the second rewiring on these two surfaces. layer.
  • the photonic integrated circuit includes a fifth surface, a sixth surface opposite to the fifth surface, and a second sidewall between the fifth surface and the sixth surface, so The fifth surface is electrically coupled to the plurality of second bumps in the second redistribution layer via the plurality of first solder balls.
  • the second redistribution layer further includes a first heat conduction layer in contact with the second surface of the electronic integrated circuit
  • the optoelectronic transceiver assembly further includes a first heat conduction block and a heat sink , the first heat conduction block is connected between the first heat conduction layer and the heat sink, and the heat sink is in contact with the sixth surface of the photonic integrated circuit.
  • the heat generated by the electronic integrated circuit can be effectively dissipated by using the first heat conducting layer, the first heat conducting block and the heat sink, and the heat generated by the photonic integrated circuit can also be effectively dissipated by using the heat sink . In this way, the device performance of electronic integrated circuits and photonic integrated circuits can be improved, and the service life of devices can be extended.
  • the one or more overmolding compound via holes include one or more heat conduction via holes, one end of the one or more heat conduction via holes is in contact with the first heat conduction layer; the first The rewiring layer also includes a second heat conduction layer in contact with the other end of the one or more heat conduction vias; Balls are electrically coupled to the plurality of first bumps in the first redistribution layer, and the second thermally conductive block is connected between the substrate and the second thermally conductive layer.
  • the heat generated by the electronic integrated circuit can be further conducted into the substrate to be dissipated by utilizing the heat conducting vias, the second heat conducting layer and the second heat conducting block. In this way, the device performance of the electronic integrated circuit can be further improved, and the service life of the device can be extended.
  • the first redistribution layer further includes a third thermally conductive layer in contact with the first surface of the electronic integrated circuit
  • the optoelectronic transceiver assembly further includes a substrate and a third thermally conductive block
  • the substrate is electrically coupled to the plurality of first bumps in the first redistribution layer via a plurality of second solder balls
  • the third heat conduction block is connected between the substrate and the third heat conduction layer between.
  • the heat generated by the electronic integrated circuit can be further conducted into the substrate through the third heat conducting layer and the third heat conducting block to be dissipated. In this way, the device performance of the electronic integrated circuit can be further improved, and the service life of the device can be extended.
  • an optical module comprising the optoelectronic transceiver assembly according to the first aspect of the present disclosure.
  • an optical switch comprising the optoelectronic transceiver assembly according to the first aspect of the present disclosure.
  • a method of manufacturing an optoelectronic transceiver assembly includes: arranging an electronic integrated circuit and one or more through-holes of overmolding compound at intervals on a carrier board, wherein the electronic integrated circuit includes a first surface, a second surface opposite to the first surface, and a first side wall located between the first surface and the second surface, and the second surface faces the carrier; forming a molding compound around the first side wall to encapsulate the electronic integrated circuit And the one or more overmolding compound through holes, wherein the molding compound includes a third surface close to the first surface and a fourth surface close to the second surface, and the one or more overmolding A via hole extends from the third surface to the fourth surface; a first rewiring layer is formed on the first surface and the third surface, and the first rewiring layer includes an electrical coupling to the A plurality of first bumps on the first surface and the one or more overmolded through holes; removing the carrier from the second
  • the electronic integrated circuit is pre-molded with a molding compound and through-molding vias are provided in the molding compound for electrical coupling between the photonic integrated circuit and the substrate.
  • photonic integrated circuits can be reliably integrated with electronic integrated circuits.
  • the second redistribution layer and through-molding through holes to realize the electrical coupling between the photonic integrated circuit and the electronic integrated circuit and the connection between the photonic integrated circuit and the electronic integrated circuit and the substrate Electrical coupling avoids the use of traditional bonding wires with a certain arc height and relatively long length, thereby avoiding parasitic effects caused by the use of bonding wires, thereby reducing power consumption of optical transceiver components.
  • the second redistribution layer and through-molding through holes to realize the electrical coupling between the photonic integrated circuit and the electronic integrated circuit and the connection between the photonic integrated circuit and the electronic integrated circuit and the substrate
  • the electrical coupling avoids the complicated manufacturing process of forming TSVs in the photonic integrated circuit or the electronic integrated circuit, and does not need to set a stress safe area in the photonic integrated circuit or the electronic integrated circuit, so that the cost of the optical transceiver component can be significantly reduced.
  • the electronic integrated circuit is only pre-molded without any molding process on the photonic integrated circuit before the optical fiber is connected to the photonic integrated circuit, pollution to the optical port on the photonic integrated circuit can be avoided, thereby reducing The transmission loss between the optical fiber and the photonic integrated circuit after connecting the two.
  • the manufacturing method further includes optically coupling an optical fiber array unit to the photonic integrated circuit, wherein forming the molding compound further includes: forming a A notch, the notch is used to avoid the optical fiber array unit.
  • forming the molding compound further includes: forming a A notch, the notch is used to avoid the optical fiber array unit.
  • the first surface and the third surface are in the same plane.
  • the first surface and the third surface being in the same plane can simplify the manufacturing process when pre-molding the electronic integrated circuit with the molding compound, and facilitate the formation of the first rewiring on these two surfaces. layer.
  • the second surface is in the same plane as the fourth surface.
  • the second surface and the fourth surface being in the same plane can simplify the manufacturing process when pre-molding the electronic integrated circuit with the molding compound, and facilitate the formation of the second rewiring on these two surfaces. layer.
  • the photonic integrated circuit includes a fifth surface, a sixth surface opposite the fifth surface, and a second sidewall between the fifth surface and the sixth surface, and Wherein electrically coupling the photonic integrated circuit to the plurality of second bumps in the second redistribution layer includes: electrically coupling the fifth surface to the second redistribution layer via the plurality of first solder balls. The plurality of second bumps in the wiring layer.
  • forming the second redistribution layer further includes: forming a first thermally conductive layer in contact with the second surface of the electronic integrated circuit, and wherein the manufacturing method further includes forming a first thermally conductive block and a heat sink, the first heat conduction block is connected between the first heat conduction layer and the heat sink, and the heat sink is in contact with the sixth surface of the photonic integrated circuit.
  • the heat generated by the electronic integrated circuit can be effectively dissipated by using the first heat conducting layer, the first heat conducting block and the heat sink, and the heat generated by the photonic integrated circuit can also be effectively dissipated by using the heat sink . In this way, the device performance of electronic integrated circuits and photonic integrated circuits can be improved, and the service life of devices can be extended.
  • the one or more overmolding compound vias include one or more thermally conductive vias, one end of the one or more thermally conductive vias is in contact with the first thermally conductive layer, and the method It also includes: forming a second heat conduction layer in the first redistribution layer in contact with the other end of the one or more heat conduction vias; electrically coupling the substrate to the first redistribution layer via a plurality of second solder balls. the plurality of first bumps in the wiring layer; and connecting the second heat conduction block between the substrate and the second heat conduction layer.
  • the heat generated by the electronic integrated circuit can be further conducted into the substrate to be dissipated by utilizing the heat conducting vias, the second heat conducting layer and the second heat conducting block. In this way, the device performance of the electronic integrated circuit can be further improved, and the service life of the device can be extended.
  • the manufacturing method further includes: forming a third heat conduction layer in the first redistribution layer in contact with the first surface of the electronic integrated circuit; A substrate is electrically coupled to the plurality of first bumps in the first redistribution layer; and a third heat conduction block is connected between the substrate and the third heat conduction layer.
  • the heat generated by the electronic integrated circuit can be further conducted into the substrate through the third heat conducting layer and the third heat conducting block to be dissipated. In this way, the device performance of the electronic integrated circuit can be further improved, and the service life of the device can be extended.
  • Fig. 1 shows a schematic structural diagram of a conventional optical transceiver module.
  • Figure 2 shows a top view of an optical transceiver assembly according to one embodiment of the present disclosure.
  • FIG. 3 shows a schematic cross-sectional view taken along the section line A-A shown in FIG. 2 .
  • Fig. 4 shows a schematic cross-sectional view of an optical transceiver assembly according to another embodiment of the present disclosure.
  • Fig. 5 shows a schematic cross-sectional view of an optical transceiver assembly according to yet another embodiment of the present disclosure.
  • 6A to 6G illustrate a schematic manufacturing process of an optical transceiver assembly according to one embodiment of the present disclosure.
  • the term “comprise” and its variants mean open inclusion, ie “including but not limited to”.
  • the term “or” means “and/or” unless otherwise stated.
  • the term “based on” means “based at least in part on”.
  • the terms “one example embodiment” and “one embodiment” mean “at least one example embodiment.”
  • the term “another embodiment” means “at least one further embodiment”.
  • Embodiments of the present disclosure provide an optoelectronic transceiver assembly and a manufacturing method thereof, so as to solve the above-mentioned problems and other potential problems existing in conventional integration schemes of optical chips and electrical chips.
  • the principle of the present disclosure will be described in detail with reference to the accompanying drawings and exemplary embodiments.
  • the terms “photonic integrated circuit” and “optical chip” may be used interchangeably, and the terms “electronic integrated circuit” and “electrical chip” may be used interchangeably.
  • a driver also referred to as a driver circuit or a driver chip
  • a modulator also referred to as a modulation circuit
  • the embodiments of the present disclosure aim to improve the layout and connection methods of the electronic integrated circuit and the photonic integrated circuit, but not to improve the circuit structure of the electronic integrated circuit and the photonic integrated circuit itself. Therefore, in this article, the circuit structure of the electronic integrated circuit and the photonic integrated circuit itself will not be described in detail.
  • Electronic integrated circuits and photonic integrated circuits may have various known structures or other structures available in the future, and the scope of the present disclosure is not strictly limited in this regard.
  • FIG. 2 shows a top view of an optical transceiver assembly according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic cross-sectional view taken along the section line A-A shown in FIG. 2
  • the display of some components is omitted in FIG. 2 .
  • the heat sink 70 and the first heat conducting block 61 are shown in FIG. 3 but not shown in FIG. 2 .
  • the optoelectronic transceiver assembly 200 described here includes a substrate 10 , an electronic integrated circuit 20 , a molding compound 40 , a photonic integrated circuit 30 and an optical fiber array unit 7 .
  • substrate 10 may comprise a printed circuit board (PCB). In other embodiments, the substrate 10 may include a ceramic substrate. In other embodiments, the substrate 10 may also be of other types, which are not strictly limited in the embodiments of the present disclosure.
  • PCB printed circuit board
  • the substrate 10 may include a ceramic substrate. In other embodiments, the substrate 10 may also be of other types, which are not strictly limited in the embodiments of the present disclosure.
  • the electronic integrated circuit 20 includes a first surface 201 , a second surface 202 opposite to the first surface 201 , and a first sidewall 203 between the first surface 201 and the second surface 202 .
  • the first surface 201 of the electronic integrated circuit 20 faces the substrate 10
  • the second surface 202 of the electronic integrated circuit 20 faces away from the substrate 10 .
  • the molding compound 40 encapsulates the electronic integrated circuit 20 around the first sidewall 203 of the electronic integrated circuit 20 .
  • the molding compound 40 includes a third surface 403 close to the first surface 201 and a fourth surface 404 close to the second surface 202 .
  • the molding compound 40 may be made of epoxy resin or other molding materials, and embodiments of the present disclosure are not strictly limited in this respect.
  • the molding compound 40 is provided with a through-molding compound hole 401 extending from the third surface 403 to the fourth surface 404 .
  • the over-molding vias 401 may be made of copper, other metals, or other types of conductive materials for forming a conductive path extending from the third surface 403 to the fourth surface 404 in the molding compound 40 .
  • Two overmolded vias 401 are shown in FIG. 3 to illustrate the principles of the embodiments of the present disclosure. However, it should be understood that the number of overmolding compound through holes 401 may be one or more, and embodiments of the present disclosure do not make strict limitations in this respect.
  • a first redistribution layer 51 is disposed on the first surface 201 of the electronic integrated circuit 20 and the third surface 403 of the molding compound 40 .
  • the first redistribution layer 51 includes a plurality of first bumps 511 electrically coupled to the first surface 201 of the electronic integrated circuit 20 and the overmolded vias 401 in the molding compound 40 .
  • the number of the first bumps 511 may be two, three, four or more, and the embodiments of the present disclosure are not strictly limited in this aspect.
  • the substrate 10 may be electrically coupled to the plurality of first bumps 511 in the first redistribution layer 51 via the plurality of second solder balls 531 .
  • the second redistribution layer 52 is disposed on the second surface 202 of the electronic integrated circuit 20 and the fourth surface 404 of the molding compound 40 .
  • the second redistribution layer 52 includes a plurality of second bumps 521 electrically coupled to the second surface 202 of the electronic integrated circuit 20 and the overmolded vias 401 in the molding compound 40 .
  • the number of the second bumps 521 may be two, three, four, five or more, and embodiments of the present disclosure are not strictly limited in this respect.
  • the photonic integrated circuit 30 is electrically coupled to the plurality of second bumps 521 in the second redistribution layer 52 via the plurality of first solder balls 532 .
  • the light array unit 7 is optically coupled to the photonic integrated circuit 30 for transmitting optical signals to the photonic integrated circuit 30, or receiving optical signals from the photonic integrated circuit 30 for transmitting to other external circuits send.
  • the optical fiber array unit 7 includes optical fibers 71 and a cover plate 72 .
  • Optical fiber 71 is optically coupled to an optical port (not shown) on photonic integrated circuit 30 .
  • the cover plate 72 is used for fixing and installing the optical fiber 71 .
  • the optical fiber array unit 7 may have other structures, which are not strictly limited in the embodiments of the present disclosure.
  • the electronic integrated circuit 20 is pre-molded by using the molding compound 40 and the through-molding compound through hole 401 is provided in the molding compound 40 for realizing the connection between the photonic integrated circuit 30 and the substrate 10. electrical coupling between them. In this way, the photonic integrated circuit 30 can be reliably integrated with the electronic integrated circuit 20 .
  • the electrical coupling between the substrates 10 avoids the use of traditional bonding wires with a certain arc height and a relatively long length, thereby avoiding parasitic effects caused by the use of bonding wires, thereby reducing the cost of the optical transceiver assembly 200. power consumption.
  • the first redistribution layer 51, the second redistribution layer 52 and the via hole 401 through the molding compound to realize the connection between the photonic integrated circuit 30 and the electronic integrated circuit 20 and between the photonic integrated circuit 30 and the electronic integrated circuit 20.
  • the electrical coupling between the substrates 10 avoids the complex manufacturing process of forming TSVs in the photonic integrated circuit 30 or the electronic integrated circuit 20, and does not need to set a stress safe area in the photonic integrated circuit 30 or the electronic integrated circuit 20, thereby significantly reducing The cost of the optical transceiver assembly 200.
  • the molding compound 40 further includes a notch 402 disposed at an end of the molding compound 40 close to the optical fiber array unit 7 .
  • the notch 402 may completely penetrate the molding compound 40 along a direction perpendicular to the substrate 10 .
  • the notch 402 may partially pass through the molding compound 40 along a direction perpendicular to the substrate 10 .
  • the projection of the notch 402 in a top view may be a rectangle. In other embodiments, the projection of the notch 402 in the top view may be in other shapes, which are not strictly limited in the embodiments of the present disclosure.
  • the first surface 201 of the electronic integrated circuit 20 and the third surface 403 of the molding compound 40 are substantially in the same plane (ie, coplanar). Utilizing such an arrangement can simplify the manufacturing process when the electronic integrated circuit 20 is premolded with the molding compound 40 , and facilitate the formation of the first rewiring layer 51 on the first surface 201 and the third surface 403 .
  • the first surface 201 of the electronic integrated circuit 20 may not be coplanar with the third surface 403 of the molding compound 40 . Although this increases the difficulty of the process to a certain extent, it does not affect the realization of the circuit function.
  • the second surface 202 of the electronic integrated circuit 20 and the fourth surface 404 of the molding compound 40 are substantially in the same plane (ie, coplanar). Utilizing such an arrangement can simplify the manufacturing process when the electronic integrated circuit 20 is pre-molded with the molding compound 40 , and facilitate the formation of the second redistribution layer 52 on the second surface 202 and the fourth surface 404 .
  • the second surface 202 of the electronic integrated circuit 20 may not be coplanar with the fourth surface 404 of the molding compound 40 . Although this will increase the difficulty of the process to a certain extent, it will not affect the realization of the circuit function.
  • the photonic integrated circuit 30 includes a fifth surface 305 , a sixth surface 306 opposite to the fifth surface 305 , and a second sidewall 302 located between the fifth surface 305 and the sixth surface 306 .
  • the fifth surface 305 faces the molding compound 40 and the electronic integrated circuit 20
  • the sixth surface faces away from the molding compound 40 and the electronic integrated circuit 20 .
  • the fifth surface 305 is electrically coupled to the second bump 521 in the second redistribution layer 52 via the first solder ball 532 .
  • the second redistribution layer 52 further includes a first thermally conductive layer 522 in contact with the second surface 202 of the electronic integrated circuit 20, and the optoelectronic transceiver assembly 200 further includes a second A heat conduction block 61 and a heat sink 70 .
  • the first heat conduction block 61 is connected between the first heat conduction layer 522 and the heat sink 70, thereby forming a passageway from the second surface 202 of the electronic integrated circuit 20, through the first heat conduction layer 522 and the first heat conduction block 61, to the heat sink 70.
  • the heat dissipation path can dissipate the heat generated by the electronic integrated circuit 20 from the second surface 202 in time.
  • the heat sink 70 is also in contact with the sixth surface 306 of the photonic integrated circuit 30 to dissipate the heat generated by the photonic integrated circuit 30 from the sixth surface 306 in time.
  • the first heat conduction layer 522 and the first heat conduction block 61 may be made of copper, other metals or other types of heat dissipation materials, and embodiments of the present disclosure are not strictly limited in this respect.
  • the first heat conduction layer 522 and the first heat conduction block 61 may include the same or different materials, and embodiments of the present disclosure are not strictly limited in this respect.
  • Fig. 4 shows a schematic cross-sectional view of an optical transceiver assembly according to another embodiment of the present disclosure.
  • the structure of the optical transceiver assembly 200 of the embodiment shown in Figure 4 is similar to the structure of the optical transceiver assembly 200 of the embodiment shown in Figure 3, the difference is that the optical transceiver assembly 200 of the embodiment shown in Figure 4 also includes additional thermal path.
  • this article only the differences between the two will be described in detail, and the same parts of the two will not be repeated here.
  • the through-molding compound via hole 401 includes a heat conduction via hole 405, the heat conduction via hole 405 extends from the third surface 403 to the fourth surface 404, and one end (top) of the heat conduction via hole 405 is connected to the first heat conduction layer 522 touch.
  • the first redistribution layer 51 further includes a second heat conduction layer 512 in contact with the other end (bottom end) of the heat conduction via 405 .
  • the optoelectronic transceiver assembly 200 further includes a second heat conduction block 62 connected between the substrate 10 and the second heat conduction layer 512 .
  • an additional heat dissipation path is formed from the second surface 202 of the electronic integrated circuit 20 to the substrate 10 via the first heat conduction layer 522 , the heat conduction via 405 , the second heat conduction layer 512 and the second heat conduction block 62 .
  • the heat generated by the electronic integrated circuit 20 during operation can be conducted to the substrate 10 and dissipated through the additional heat dissipation path, thereby further improving the heat dissipation performance of the electronic integrated circuit 20 .
  • thermal via 405 Only one thermal via 405 is shown in FIG. 4 to illustrate the principles of embodiments of the present disclosure. However, it should be understood that the number of the heat conduction vias 405 may be one or more, and embodiments of the present disclosure are not strictly limited in this regard.
  • Fig. 5 shows a schematic cross-sectional view of an optical transceiver assembly according to yet another embodiment of the present disclosure.
  • the structure of the optical transceiver assembly 200 of the embodiment shown in Figure 5 is similar to the structure of the optical transceiver assembly 200 of the embodiment shown in Figure 3, the difference is that the optical transceiver assembly 200 of the embodiment shown in Figure 5 also includes Another additional thermal path.
  • this article only the differences between the two will be described in detail, and the same parts of the two will not be repeated here.
  • the first redistribution layer 51 further includes a third heat conducting layer 513 in contact with the first surface 201 of the electronic integrated circuit 20 .
  • the optoelectronic transceiver assembly 200 further includes a third heat conduction block 63 , and the third heat conduction block 63 is connected between the substrate 10 and the third heat conduction layer 513 .
  • the above-mentioned optical transceiver assembly 200 can be applied in an optical module for optical communication. In some other embodiments, the above-mentioned optical transceiver assembly 200 can be applied in an optical switch for optical communication. It should be understood that the optical transceiver assembly 200 may be applied to various electronic devices, and embodiments of the present disclosure are not strictly limited in this regard.
  • 6A to 6G illustrate a schematic manufacturing process of an optical transceiver assembly according to one embodiment of the present disclosure.
  • the electronic integrated circuits 20 and the via holes 401 of the overmolding compound are arranged on the carrier board 80 at intervals.
  • the electronic integrated circuit 20 includes a first surface 201, a second surface 202 opposite to the first surface 201, and a first sidewall 203 between the first surface 201 and the second surface 202, and the second surface 202 faces carrier board 80 .
  • Two overmolded vias 401 are shown in FIG. 6A to illustrate the principles of embodiments of the present disclosure. However, it should be understood that the number of overmolding compound through holes 401 may be one or more, and embodiments of the present disclosure do not make strict limitations in this aspect.
  • a molding compound 40 is formed around the first sidewall 203 of the electronic integrated circuit 20 to encapsulate the electronic integrated circuit 20 and the via hole 401 through the molding compound.
  • the first surface 201 of the electronic integrated circuit 20 may be exposed through a grinding process, or the first surface 201 of the electronic integrated circuit 20 may not be covered by the molding compound 40 by controlling the process parameters of the molding process.
  • the molding compound 40 includes a third surface 403 close to the first surface 201 and a fourth surface 404 close to the second surface 202 , and one or more through-molding compound holes 401 extend from the third surface 403 to the fourth surface 404 .
  • a first redistribution layer 51 is formed on the first surface 201 of the electronic integrated circuit 20 and the third surface 403 of the molding compound 40 .
  • the first redistribution layer 51 includes a plurality of first bumps 511 electrically coupled to the first surface 201 and the one or more overmolded vias 401 .
  • the number of the first bumps 511 may be two, three, four or more, and the embodiments of the present disclosure are not strictly limited in this aspect.
  • a plurality of second solder balls 531 are also formed on each first bump 511 for electrically coupling the substrate 10 in subsequent steps. It should be understood that the second solder balls 531 may also be re-formed during the coupling of the substrate 10 in a subsequent step, and the embodiments of the present disclosure are not strictly limited in this regard.
  • the carrier 80 is removed from the second surface 202 and the fourth surface 404 to expose the second surface 202 of the electronic integrated circuit 20 and the fourth surface 404 of the molding compound 40 .
  • a second redistribution layer 52 is formed on the second surface 202 of the electronic integrated circuit 20 and the fourth surface 404 of the molding compound 40 .
  • the second redistribution layer 52 includes a plurality of second bumps 521 electrically coupled to the second surface 202 and through the molding compound vias 401 .
  • the number of the second bumps 521 may be two, three, four, five or more, and embodiments of the present disclosure are not strictly limited in this respect.
  • a plurality of first solder balls 532 are also formed on each second bump 521 for electrically coupling the photonic integrated circuit 30 in subsequent steps.
  • the second redistribution layer 52 further includes a first thermally conductive layer 522 in contact with the second surface 202 of the electronic integrated circuit 20 .
  • the photonic integrated circuit 30 is electrically coupled to the plurality of second bumps 521 in the second redistribution layer 52 via the first solder balls 532 .
  • the light array unit 7 can also be optically coupled to the photonic integrated circuit 30 for transmitting optical signals to the photonic integrated circuit 30, or receiving optical signals from the photonic integrated circuit 30 for transmitting to other external circuits. send.
  • the substrate 10 can also be electrically coupled to the plurality of first bumps 511 in the first redistribution layer 51 via the plurality of second solder balls 531 .
  • a first heat conducting block 61 and a heat sink 70 are also formed.
  • the first heat conduction block 61 is connected between the first heat conduction layer 522 and the heat sink 70, thereby forming a passageway from the second surface 202 of the electronic integrated circuit 20, through the first heat conduction layer 522 and the first heat conduction block 61, to the heat sink 70.
  • the heat dissipation path can dissipate the heat generated by the electronic integrated circuit 20 from the second surface 202 in time.
  • the radiator 70 is also in contact with the photonic integrated circuit 30 to dissipate the heat generated by the photonic integrated circuit 30 in time.
  • forming the molding compound 40 further includes: forming a gap 402 at an end of the molding compound 40 close to the fiber array unit 7 , and the gap 402 is used to avoid the fiber array unit 7 .
  • the first surface 201 of the electronic integrated circuit 20 and the third surface 403 of the molding compound 40 are substantially in the same plane (ie, coplanar). Utilizing such an arrangement can simplify the manufacturing process when the electronic integrated circuit 20 is premolded with the molding compound 40 , and facilitate the formation of the first rewiring layer 51 on the first surface 201 and the third surface 403 .
  • the first surface 201 of the electronic integrated circuit 20 may not be coplanar with the third surface 403 of the molding compound 40 . Although this increases the difficulty of the process to a certain extent, it does not affect the realization of the circuit function.
  • the second surface 202 of the electronic integrated circuit 20 and the fourth surface 404 of the molding compound 40 are substantially in the same plane (ie, coplanar). Utilizing such an arrangement can simplify the manufacturing process when the electronic integrated circuit 20 is pre-molded with the molding compound 40 , and facilitate the formation of the second redistribution layer 52 on the second surface 202 and the fourth surface 404 .
  • the second surface 202 of the electronic integrated circuit 20 may not be coplanar with the fourth surface 404 of the molding compound 40 . Although this will increase the difficulty of the process to a certain extent, it will not affect the realization of the circuit function.
  • the photonic integrated circuit 30 includes a fifth surface 305 , a sixth surface 306 opposite to the fifth surface 305 , and a second surface between the fifth surface 305 and the sixth surface 306 . side wall 302 .
  • the fifth surface 305 faces the molding compound 40 and the electronic integrated circuit 20
  • the sixth surface faces away from the molding compound 40 and the electronic integrated circuit 20 .
  • the fifth surface 305 is electrically coupled to the second bump 521 in the second redistribution layer 52 via the first solder ball 532 .
  • the through-molding compound via hole 401 includes a heat conduction via hole 405, the heat conduction via hole 405 extends from the third surface 403 to the fourth surface 404, and one end (top) of the heat conduction via hole 405 It is in contact with the first thermal conduction layer 522 .
  • the first redistribution layer 51 further includes a second heat conduction layer 512 in contact with the other end (bottom end) of the heat conduction via 405 .
  • the optoelectronic transceiver assembly 200 further includes a second heat conduction block 62 connected between the substrate 10 and the second heat conduction layer 512 .
  • an additional heat dissipation path is formed from the second surface 202 of the electronic integrated circuit 20 to the substrate 10 via the first heat conduction layer 522 , the heat conduction via 405 , the second heat conduction layer 512 and the second heat conduction block 62 .
  • the heat generated by the electronic integrated circuit 20 during operation can be conducted to the substrate 10 and dissipated through the additional heat dissipation path, thereby further improving the heat dissipation performance of the electronic integrated circuit 20 .
  • the first redistribution layer 51 further includes a third heat conducting layer 513 in contact with the first surface 201 of the electronic integrated circuit 20 .
  • the optoelectronic transceiver assembly 200 further includes a third heat conduction block 63 , and the third heat conduction block 63 is connected between the substrate 10 and the third heat conduction layer 513 .

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Abstract

本公开的实施例涉及光电收发器组件及其制造方法。该光电收发器组件包括：电子集成电路，包括第一表面、与第一表面相对的第二表面、以及位于第一表面与第二表面之间的第一侧壁；塑封料，围绕第一侧壁塑封电子集成电路，塑封料包括靠近第一表面的第三表面以及靠近第二表面的第四表面，并且塑封料中设置有从第三表面延伸到第四表面的一个或多个过塑封料通孔；第一再布线层，设置在第一表面以及第三表面上，并且包括电耦合至第一表面以及一个或多个过塑封料通孔的多个第一凸点；第二再布线层，设置在第二表面以及第四表面上，并且包括电耦合至第二表面以及一个或多个过塑封料通孔的多个第二凸点；以及光子集成电路，经由多个第一焊球电耦合至多个第二凸点。

Description

光电收发器组件及其制造方法 技术领域
本公开的实施例总体上涉及电子器件领域，并且更具体地，涉及一种光电收发器组件及其制造方法。
背景技术
全球数据通信业务的持续增长推动了硅基光电子学的不断发展，特别是基于硅基光电子学的高速高带宽光收发器模块(也被称作光引擎)得到广泛应用和发展。光收发器模块需要同时集成光芯片(也称作光子集成电路，简写为PIC)和电芯片(也称作电子集成电路，简写为EIC)，还需要实现光纤阵列单元(FAU)与光芯片上的波导阵列之间的耦合。目前，这种集成方式在高密度和高频领域存在两个主要技术挑战：
1)传统打线互连方案很难满足输入/输出(I/O)密度和互连长度的要求，为降低寄生电感等造成的损耗，要求电芯片上的驱动器与光芯片上的调制器之间的互连长度尽量短；以及
2)为降低由光纤阵列单元与波导阵列之间的耦合造成的损耗，需要在封装过程中保护光芯片表面上的特定区域以及用于边耦合波导阵列单元的侧壁，以避免侧壁上的光口在连接光纤之前被污染。
图1示出了一种常规的光收发器模块100的结构示意图。如图1所示，该光收发器模块100包括基板10、电子集成电路20、光子集成电路30以及光纤71。电子集成电路20和光子集成电路30布置在基板10上，并且彼此间隔开一定距离。电子集成电路20和光子集成电路30彼此之间通过键合线50进行电耦合。电子集成电路20和光子集成电路30还分别通过键合线50电耦合到基板10。光纤71被光耦合到光子集成电路30的侧壁上的光口。由于各个键合线50具有一定的弧高且具有较大的长度，因而会产生较大的寄生电感和寄生电容等寄生效应，从而导致较大的功耗。
目前业界趋向采用倒装焊(flip-chip)的技术将电芯片上的驱动器与光芯片上的调制器直接垂直互连，然后通过光芯片或电芯片上的过硅通孔(Through-Silicon-Via，TSV)与基板进行互连。这种光电集成方式的互连路径短，I/O密度高，但要求在有源芯片(光芯片或者电芯片)上制备TSV。在有源芯片中制备TSV的工艺非常复杂且对于工艺精度的要求非常高，这导致器件制造成本相当高。此外，由于TSV造成的应力会影响光芯片或电芯片的器件性能，因此需要设置应力安全区域，将TSV设计在该安全区域之内，这样无形中减少了芯片的有效利用面积，进一步增加了成本。
因此，存在对于改进的光芯片和电芯片集成方案的需要。
发明内容
本公开的实施例提供了一种光电收发器组件及其制造方法，旨在解决常规的光芯片和电芯片集成方案存在的上述问题以及其他潜在的问题。
根据本公开的第一方面，提供了一种光电收发器组件，其包括：电子集成电路，包括第一表面、与所述第一表面相对的第二表面、以及位于所述第一表面与所述第二表面之间的第一侧壁；塑封料，围绕所述第一侧壁塑封所述电子集成电路，所述塑封料包括 靠近所述第一表面的第三表面以及靠近所述第二表面的第四表面，并且所述塑封料中设置有从所述第三表面延伸到所述第四表面的一个或多个过塑封料通孔；第一再布线层，设置在所述第一表面以及所述第三表面上，并且包括电耦合至所述第一表面以及所述一个或多个过塑封料通孔的多个第一凸点；第二再布线层，设置在所述第二表面以及所述第四表面上，并且包括电耦合至所述第二表面以及所述一个或多个过塑封料通孔的多个第二凸点；以及光子集成电路，经由多个第一焊球电耦合至所述多个第二凸点。
在这样的实施例中，利用了塑封料来对电子集成电路进行预模制并且在塑封料中设置了过塑封料通孔以用于实现光子集成电路与基板之间的电耦合。以此方式，能够可靠地将光子集成电路与电子集成电路集成在一起。
此外，由于采用第一再布线层、第二再布线层以及过塑封料通孔来实现光子集成电路与电子集成电路之间以及光子集成电路和电子集成电路二者与基板之间的电耦合，避免了使用传统的具有一定弧高以及较大长度的键合线，因而能够避免由于键合线的使用而导致的寄生效应，从而降低了光收发器组件的功耗。
此外，由于采用第一再布线层、第二再布线层以及过塑封料通孔来实现光子集成电路与电子集成电路之间的电耦合以及光子集成电路和电子集成电路二者与基板之间的电耦合，避免了在光子集成电路或电子集成电路中形成TSV的复杂制造工艺，且无需在光子集成电路或电子集成电路中设置应力安全区域，因而能够显著降低光收发器组件的成本。
此外，由于在将光纤连接至光子集成电路之前仅需对电子集成电路进行预模制而无需对光子集成电路进行任何模制工艺，因此能够避免对光子集成电路上的光口的污染，从而降低了在将光纤连接至光子集成电路之后二者之间的传输损耗。
在一些实施例中，所述光电收发器组件还包括光耦合至所述光子集成电路的光纤阵列单元，其中所述塑封料还包括设置在所述塑封料的靠近所述光纤阵列单元的一端处的缺口，所述缺口用于避开所述光纤阵列单元。在这样的实施例中，通过在塑封料中设置用于避开光纤阵列单元的缺口，能够避免光纤阵列单元与塑封料发生干涉，便于将光纤阵列单元连接到光子集成电路上。
在一些实施例中，所述第一表面与所述第三表面处于相同平面中。在这样的实施例中，第一表面与第三表面处于相同平面中能够简化在利用塑封料对电子集成电路进行预模制时的制造工艺，并且便于在这两个表面上形成第一再布线层。
在一些实施例中，所述第二表面与所述第四表面处于相同平面中。在这样的实施例中，第二表面与第四表面处于相同平面中能够简化在利用塑封料对电子集成电路进行预模制时的制造工艺，并且便于在这两个表面上形成第二再布线层。
在一些实施例中，所述光子集成电路包括第五表面、与所述第五表面相对的第六表面、以及位于所述第五表面与所述第六表面之间的第二侧壁，所述第五表面经由所述多个第一焊球电耦合至所述第二再布线层中的所述多个第二凸点。
在一些实施例中，所述第二再布线层还包括与所述电子集成电路的所述第二表面接触的第一导热层，并且所述光电收发器组件还包括第一导热块以及散热器，所述第一导热块连接在所述第一导热层与所述散热器之间，并且所述散热器与所述光子集成电路的所述第六表面接触。在这样的实施例中，利用第一导热层、第一导热块以及散热器能够将电子集成电路产生的热量有效地消散掉，并且利用散热器还能够将光子集成电路产生 的热量有效地消散掉。以此方式，能够提升电子集成电路和光子集成电路的器件性能，并且延长器件使用寿命。
在一些实施例中，所述一个或多个过塑封料通孔包括一个或多个导热通孔，所述一个或多个导热通孔的一端与所述第一导热层接触；所述第一再布线层还包括与所述一个或多个导热通孔的另一端接触的第二导热层；并且所述光电收发器组件还包括基板以及第二导热块，所述基板经由多个第二焊球电耦合至所述第一再布线层中的所述多个第一凸点，并且所述第二导热块连接在所述基板与所述第二导热层之间。在这样的实施例中，利用导热通孔、第二导热层以及第二导热块能够进一步将电子集成电路产生的热量传导到基板中而消散掉。以此方式，能够进一步提升电子集成电路的器件性能，并且延长器件使用寿命。
在一些实施例中，所述第一再布线层还包括与所述电子集成电路的所述第一表面接触的第三导热层，并且所述光电收发器组件还包括基板以及第三导热块，所述基板经由多个第二焊球电耦合至所述第一再布线层中的所述多个第一凸点，并且所述第三导热块连接在所述基板与所述第三导热层之间。在这样的实施例中，通过第三导热层和第三导热块能够进一步将电子集成电路产生的热量传导到基板中而消散掉。以此方式，能够进一步提升电子集成电路的器件性能，延长器件使用寿命。
根据本公开的第二方面，提供了一种光模块，其包括根据本公开的第一方面的光电收发器组件。
根据本公开的第三方面，提供了一种光交换机，其包括根据本公开的第一方面的光电收发器组件。
根据本公开的第四方面，提供了一种光电收发器组件的制造方法。该制造方法包括：将电子集成电路以及一个或多个过塑封料通孔间隔布置在载板上，其中所述电子集成电路包括第一表面、与所述第一表面相对的第二表面、以及位于所述第一表面与所述第二表面之间的第一侧壁，并且所述第二表面面朝所述载板；围绕所述第一侧壁形成塑封料以塑封所述电子集成电路以及所述一个或多个过塑封料通孔，其中所述塑封料包括靠近所述第一表面的第三表面以及靠近所述第二表面的第四表面，并且所述一个或多个过塑封料通孔从所述第三表面延伸到所述第四表面；在所述第一表面以及所述第三表面上形成第一再布线层，所述第一再布线层包括电耦合至所述第一表面以及所述一个或多个过塑封料通孔的多个第一凸点；从所述第二表面以及所述第四表面去除所述载板；在所述第二表面以及所述第四表面上形成第二再布线层，所述第二再布线层包括电耦合至所述第二表面以及所述一个或多个过塑封料通孔的多个第二凸点；经由多个第一焊球将光子集成电路电耦合至所述第二再布线层中的所述多个第二凸点。
在这样的实施例中，利用了塑封料来对电子集成电路进行预模制并且在塑封料中设置了过塑封料通孔以用于实现光子集成电路与基板之间的电耦合。以此方式，能够可靠地将光子集成电路与电子集成电路集成在一起。
此外，由于采用第一再布线层、第二再布线层以及过塑封料通孔来实现光子集成电路与电子集成电路之间的电耦合以及光子集成电路和电子集成电路二者与基板之间的电耦合，避免了使用传统的具有一定弧高以及较大长度的键合线，因而能够避免由于键合线的使用而导致的寄生效应，从而降低了光收发器组件的功耗。
此外，由于采用第一再布线层、第二再布线层以及过塑封料通孔来实现光子集成电 路与电子集成电路之间的电耦合以及光子集成电路和电子集成电路二者与基板之间的电耦合，避免了在光子集成电路或电子集成电路中形成TSV的复杂制造工艺，且无需在光子集成电路或电子集成电路中设置应力安全区域，因而能够显著降低光收发器组件的成本。
此外，由于在将光纤连接至光子集成电路之前仅对电子集成电路进行预模制而未对光子集成电路进行任何模制工艺，因此能够避免对光子集成电路上的光口的污染，从而能够降低在将光纤连接至光子集成电路之后二者之间的传输损耗。
在一些实施例中，所述制造方法还包括将光纤阵列单元光耦合至所述光子集成电路，其中形成所述塑封料还包括：在所述塑封料的靠近所述光纤阵列单元的一端处形成缺口，所述缺口用于避开所述光纤阵列单元。在这样的实施例中，通过在塑封料中形成用于避开光纤阵列单元的缺口，能够避免光纤阵列单元与塑封料发生干涉，便于将光纤阵列单元连接到光子集成电路上。
在一些实施例中，所述第一表面与所述第三表面处于相同平面中。在这样的实施例中，第一表面与第三表面处于相同平面中能够简化在利用塑封料对电子集成电路进行预模制时的制造工艺，并且便于在这两个表面上形成第一再布线层。
在一些实施例中，所述第二表面与所述第四表面处于相同平面中。在这样的实施例中，第二表面与第四表面处于相同平面中能够简化在利用塑封料对电子集成电路进行预模制时的制造工艺，并且便于在这两个表面上形成第二再布线层。
在一些实施例中，所述光子集成电路包括第五表面、与所述第五表面相对的第六表面、以及位于所述第五表面与所述第六表面之间的第二侧壁，并且其中将光子集成电路电耦合至所述第二再布线层中的所述多个第二凸点包括：将所述第五表面经由所述多个第一焊球电耦合至所述第二再布线层中的所述多个第二凸点。
在一些实施例中，形成所述第二再布线层还包括：形成与所述电子集成电路的所述第二表面接触的第一导热层，并且其中所述制造方法还包括形成第一导热块以及散热器，所述第一导热块连接在所述第一导热层与所述散热器之间，并且所述散热器与所述光子集成电路的所述第六表面接触。在这样的实施例中，利用第一导热层、第一导热块以及散热器能够将电子集成电路产生的热量有效地消散掉，并且利用散热器还能够将光子集成电路产生的热量有效地消散掉。以此方式，能够提升电子集成电路和光子集成电路的器件性能，并且延长器件使用寿命。
在一些实施例中，所述一个或多个过塑封料通孔包括一个或多个导热通孔，所述一个或多个导热通孔的一端与所述第一导热层接触，并且所述方法还包括：在所述第一再布线层中形成与所述一个或多个导热通孔的另一端接触的第二导热层；经由多个第二焊球将基板电耦合至所述第一再布线层中的所述多个第一凸点；以及将述第二导热块连接在所述基板与所述第二导热层之间。在这样的实施例中，利用导热通孔、第二导热层以及第二导热块能够进一步将电子集成电路产生的热量传导到基板中而消散掉。以此方式，能够进一步提升电子集成电路的器件性能，并且延长器件使用寿命。
在一些实施例中，所述制造方法还包括：在所述第一再布线层中形成与所述电子集成电路的所述第一表面接触的第三导热层；经由多个第二焊球将基板电耦合至所述第一再布线层中的所述多个第一凸点；以及将第三导热块连接在所述基板与所述第三导热层之间。在这样的实施例中，通过第三导热层和第三导热块能够进一步将电子集成电路产 生的热量传导到基板中而消散掉。以此方式，能够进一步提升电子集成电路的器件性能，延长器件使用寿命。
提供发明内容部分是为了简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开内容的关键特征或主要特征，也无意限制本公开内容的范围。
附图说明
通过参考附图阅读下文的详细描述，本公开的实施例的上述以及其他目的、特征和优点将变得易于理解。在附图中，以示例而非限制性的方式示出了本公开的若干实施例。
图1示出了一种常规的光收发器模块的结构示意图。
图2示出了根据本公开的一个实施例的光收发器组件的俯视图。
图3示出了沿图2中所示的剖面线A-A截取的示意性截面图。
图4示出了根据本公开的另一实施例的光收发器组件的示意性截面图。
图5示出了根据本公开的又一实施例的光收发器组件的示意性截面图。
图6A至图6G示出了根据本公开的一个实施例的光收发器组件的示意性制造过程。
在各个附图中，相同或对应的标号表示相同或对应的部分。
具体实施方式
下面将参照附图更详细地描述本公开的优选实施例。虽然附图中显示了本公开的优选实施例，然而应该理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了使本公开更加透彻和完整，并且能够将本公开的范围完整地传达给本领域的技术人员。
在本文中使用的术语“包括”及其变形表示开放性包括，即“包括但不限于”。除非特别申明，术语“或”表示“和/或”。术语“基于”表示“至少部分地基于”。术语“一个示例实施例”和“一个实施例”表示“至少一个示例实施例”。术语“另一实施例”表示“至少一个另外的实施例”。术语“上”、“下”、“前”、“后”等指示放置或者位置关系的词汇均基于附图所示的方位或者位置关系，仅为了便于描述本公开的原理，而不是指示或者暗示所指的元件必须具有特定的方位、以特定的方位构造或操作，因此不能理解为对本公开的限制。
如在上文中所描述的，在采用传统打线互连方案实现光芯片和电芯片的集成时，由于各个键合线具有一定的弧高且具有较大的长度，因而会产生较大的寄生电感和寄生电容等寄生效应，从而导致较大的功耗；而在采用倒装焊和TSV工艺实现光芯片和电芯片的集成时，TSV的制造工艺非常复杂且对于工艺精度的要求非常高，这导致器件制造成本相当高，而且由于需要在光芯片或电芯片中设置应力安全区域，导致减小了芯片的有效利用面积，进一步增加了成本。本公开的实施例提供了一种光电收发器组件及其制造方法，以解决常规的光芯片和电芯片集成方案存在的上述问题以及其他潜在的问题。在下文中将参考附图结合示例性实施例来详细描述本公开的原理。
在本文中，术语“光子集成电路”与“光芯片”可以可互换地使用，并且术语“电子集成电路”与“电芯片”可以可互换地使用。电子集成电路中例如可以设置有驱动器(也可称作驱动电路或驱动芯片)以及其他功能单元。光子集成电路中例如可以设置有 调制器(也可称作调制电路)以及其他功能。本公开的实施例旨在改善电子集成电路与光子集成电路的布局和连接方式，而不旨在改善电子集成电路和光子集成电路本身的电路结构。因此，在本文中，对于电子集成电路和光子集成电路本身的电路结构，将不再进行详细赘述。电子集成电路和光子集成电路可以具有各种已知结构或者未来可用的其他结构，本公开的范围在此方面不做严格限制。
下面将结合图2和图3来描述根据本公开的一个实施例的光收发器组件的结构。图2示出了根据本公开的一个实施例的光收发器组件的俯视图，图3示出了沿图2中所示的剖面线A-A截取的示意性截面图。为了在俯视图中更清楚地示出光收发器组件的各部分在水平方向上的相对布局，在图2中省略了对于一些部件的显示。例如，散热器70和第一导热块61在图3中被示出，而在图2中未被未示出。
如图2和图3所示，总体上，在此描述的光电收发器组件200包括基板10、电子集成电路20、塑封料40、光子集成电路30以及光纤阵列单元7。
在一些实施例中，基板10可以包括印刷电路板(PCB)。在另一些实施例中，基板10可以包括陶瓷基板。在其他实施例中，基板10还可以为其他类型，本公开的实施例在此方面不做严格限制。
如图3所示，电子集成电路20包括第一表面201、与第一表面201相对的第二表面202、以及位于第一表面201与第二表面202之间的第一侧壁203。电子集成电路20的第一表面201朝向基板10，电子集成电路20的第二表面202背对基板10。
如图2和图3所示，塑封料40围绕电子集成电路20的第一侧壁203塑封电子集成电路20。塑封料40包括靠近第一表面201的第三表面403以及靠近第二表面202的第四表面404。塑封料40可以由环氧树脂或者其他模塑材料制成，本公开的实施例在此方面不做严格限制。塑封料40中设置有从第三表面403延伸到第四表面404的过塑封料通孔401。过塑封料通孔401可以由铜、其他金属或其他类型的导电材料制成，以用于在塑封料40中形成从第三表面403延伸到第四表面404的导电路径。图3中示出了两个过塑封料通孔401以用于说明本公开的实施例的原理。然而，应当理解的是，过塑封料通孔401的数目可以为一个或多个，本公开的实施例在此方面不做严格限制。
如图3所示，电子集成电路20的第一表面201和塑封料40的第三表面403上设置有第一再布线层51。第一再布线层51包括电耦合至电子集成电路20的第一表面201以及塑封料40中的过塑封料通孔401的多个第一凸点511。第一凸点511的数目可以为两个、三个、四个或更多个，本公开的实施例在此方面不做严格限制。基板10可以经由多个第二焊球531电耦合至第一再布线层51中的多个第一凸点511。
如图3所示，电子集成电路20的第二表面202和塑封料40的第四表面404上设置有第二再布线层52。第二再布线层52包括电耦合至电子集成电路20的第二表面202以及塑封料40中的过塑封料通孔401的多个第二凸点521。第二凸点521的数目可以为两个、三个、四个、五个或更多个，本公开的实施例在此方面不做严格限制。光子集成电路30经由多个第一焊球532电耦合至第二再布线层52中的多个第二凸点521。
如图2和图3所示，光线阵列单元7光耦合至光子集成电路30，以用于向光子集成电路30传送光信号，或者从光子集成电路30接收光信号以用于向其他外部电路进行传送。在一些实施例中，光纤阵列单元7包括光纤71以及盖板72。光纤71光耦合至光子集成电路30上的光口(未示出)。盖板72用于实现对光纤71的固定和安装。在其他实 施例中，光纤阵列单元7可以具有其他结构，本公开的实施例在此方面不做严格限制。
在根据本公开的实施例中，利用了塑封料40来对电子集成电路20进行预模制并且在塑封料40中设置了过塑封料通孔401以用于实现光子集成电路30与基板10之间的电耦合。以此方式，能够可靠地将光子集成电路30与电子集成电路20集成在一起。
此外，由于采用第一再布线层51、第二再布线层52以及过塑封料通孔401来实现光子集成电路30与电子集成电路20之间以及光子集成电路30和电子集成电路20二者与基板10之间的电耦合，避免了使用传统的具有一定弧高以及较大长度的键合线，因而能够避免由于键合线的使用而导致的寄生效应，从而降低了光收发器组件200的功耗。
此外，由于采用第一再布线层51、第二再布线层52以及过塑封料通孔401来实现光子集成电路30与电子集成电路20之间以及光子集成电路30和电子集成电路20二者与基板10之间的电耦合，避免了在光子集成电路30或电子集成电路20中形成TSV的复杂制造工艺，且无需在光子集成电路30或电子集成电路20中设置应力安全区域，因而能够显著降低光收发器组件200的成本。
此外，由于在将光纤71连接至光子集成电路30之前仅需对电子集成电路20进行预模制而无需对光子集成电路30进行任何模制工艺，因此能够避免对光子集成电路30上的光口的污染，从而降低了在将光纤71连接至光子集成电路30之后二者之间的传输损耗。
在一些实施例中，如图2和图3所示，塑封料40还包括设置在塑封料40的靠近光纤阵列单元7的一端处的缺口402。如图2所示，缺口402可以沿着垂直于基板10的方向完全贯穿塑封料40。通过在塑封料40中设置用于避开光纤阵列单元7的缺口402，能够避免光纤阵列单元7与塑封料4发生干涉，便于将光纤阵列单元7连接到光子集成电路30上。在其他实施例中，缺口402可以沿着垂直于基板10的方向部分地穿过塑封料40。另外，如图2所示，缺口402在俯视图中的投影可以为矩形。在其他实施例中，缺口402在俯视图中的投影可以为其他形状，本公开的实施例在此方面不做严格限制。
在一些实施例中，如图3所示，电子集成电路20的第一表面201与塑封料40的第三表面403基本上处于相同平面中(即共面)。利用这样的布置能够简化在利用塑封料40对电子集成电路20进行预模制时的制造工艺，并且便于在第一表面201和第三表面403上形成第一再布线层51。在其他实施例中，电子集成电路20的第一表面201与塑封料40的第三表面403可以不共面，这虽然在一定程度上增加了工艺难度，但是并不会影响电路功能的实现。
在一些实施例中，如图3所示，电子集成电路20的第二表面202与塑封料40的第四表面404基本上处于相同平面中(即共面)。利用这样的布置能够简化在利用塑封料40对电子集成电路20进行预模制时的制造工艺，并且便于在第二表面202和第四表面404上形成第二再布线层52。在其他实施例中，电子集成电路20的第二表面202与塑封料40的第四表面404可以不共面，这虽然在一定程度上会增加工艺难度，但是并不会影响电路功能的实现。
如图3所示，光子集成电路30包括第五表面305、与第五表面305相对的第六表面306、以及位于第五表面305与第六表面306之间的第二侧壁302。第五表面305朝向塑封料40和电子集成电路20，第六表面背对塑封料40和电子集成电路20。第五表面305经由第一焊球532电耦合至第二再布线层52中的第二凸点521。
由于光子集成电路30和电子集成电路20在工作时会产生热量，如果不将所产生的热量及时消散，则会对光子集成电路30和电子集成电路20的性能和使用寿命产生影响。为此，在一些实施例中，如图3所示，第二再布线层52还包括与电子集成电路20的第二表面202接触的第一导热层522，并且光电收发器组件200还包括第一导热块61以及散热器70。第一导热块61连接在第一导热层522与散热器70之间，从而形成从电子集成电路20的第二表面202，经由第一导热层522和第一导热块61，到达散热器70的散热路径，能够将电子集成电路20产生的热量从第二表面202及时地消散掉。此外，散热器70还与光子集成电路30的第六表面306接触，以将光子集成电路30产生的热量从第六表面306及时地消散掉。第一导热层522和第一导热块61可以由铜、其他金属或其他类型的散热材料制成，本公开的实施例在此方面不做严格限制。第一导热层522和第一导热块61可以包括相同或者不同的材料，本公开的实施例在此方面不做严格限制。
图4示出了根据本公开的另一实施例的光收发器组件的示意性截面图。图4所示的实施例的光收发器组件200的结构与图3所示的实施例的光收发器组件200的结构类似，区别在于图4所示的实施例的光收发器组件200还包括附加的散热路径。在本文中将仅详细描述二者之间的区别，而对于二者相同的部分，在此将不再赘述。
如图4所示，过塑封料通孔401包括导热通孔405，导热通孔405从第三表面403延伸到第四表面404，并且导热通孔405的一端(顶端)与第一导热层522接触。此外，第一再布线层51还包括与导热通孔405的另一端(底端)接触的第二导热层512。光电收发器组件200还包括第二导热块62，第二导热块62连接在基板10与第二导热层512之间。利用这样的布置，形成了从电子集成电路20的第二表面202，经由第一导热层522、导热通孔405、第二导热层512和第二导热块62，到达基板10的附加散热路径。以此方式，电子集成电路20在工作时产生的热量能够经由该附加散热路径传导到基板10中消散掉，从而能够进一步提升电子集成电路20的散热性能。
图4中仅示出了一个导热通孔405以用于说明本公开的实施例的原理。然而，应当理解的是，导热通孔405的数目可以为一个或多个，本公开的实施例在此方面不做严格限制。
图5示出了根据本公开的又一实施例的光收发器组件的示意性截面图。图5所示的实施例的光收发器组件200的结构与图3所示的实施例的光收发器组件200的结构类似，区别在于图5所示的实施例的光收发器组件200还包括另一个附加散热路径。在本文中将仅详细描述二者之间的区别，而对于二者相同的部分，在此将不再赘述。
如图5所示，第一再布线层51还包括与电子集成电路20的第一表面201接触的第三导热层513。此外，光电收发器组件200还包括第三导热块63，第三导热块63连接在基板10与第三导热层513之间。利用这样的布置，形成了从电子集成电路20的第一表面201，经由第三导热层513和第三导热块63，到达基板10的附加散热径。以此方式，电子集成电路20在工作时产生的热量能够经由该附加散热路径传导到基板10中消散掉，从而能够进一步提升电子集成电路20的散热性能。
在一些实施例中，如上所述的光收发器组件200可以应用于光模块中，以用于进行光通信。在另一些实施例中，如上所述的光收发器组件200可以应用于光交换机中，以用于进行光通信。应当理解，光收发器组件200可以应用于各种电子设备中，本公开的实施例在此方面不做严格限制。
下面将描述根据本公开的实施例的光收发器组件的示例性制造方法。图6A至图6G示出了根据本公开的一个实施例的光收发器组件的示意性制造过程。
如图6A所示，将电子集成电路20以及过塑封料通孔401间隔布置在载板80上。其中电子集成电路20包括第一表面201、与第一表面201相对的第二表面202、以及位于第一表面201与第二表面202之间的第一侧壁203，并且第二表面202面朝载板80。图6A中示出了两个过塑封料通孔401以用于说明本公开的实施例的原理。然而，应当理解的是，过塑封料通孔401的数目可以为一个或多个，本公开的实施例在此方面不做严格限制。
如图6B所示，围绕电子集成电路20的第一侧壁203形成塑封料40以塑封电子集成电路20以及过塑封料通孔401。可以通过打磨工艺使电子集成电路20的第一表面201露出，也可以通过控制模制工艺的工艺参数来使电子集成电路20的第一表面201不被塑封料40覆盖。其中塑封料40包括靠近第一表面201的第三表面403以及靠近第二表面202的第四表面404，并且一个或多个过塑封料通孔401从第三表面403延伸到第四表面404。
如图6C所示，在电子集成电路20的第一表面201和塑封料40的第三表面403上形成第一再布线层51。第一再布线层51包括电耦合至第一表面201以及一个或多个过塑封料通孔401的多个第一凸点511。第一凸点511的数目可以为两个、三个、四个或更多个，本公开的实施例在此方面不做严格限制。如图6C所示，在每个第一凸点511上还形成了多个第二焊球531以用于在后续步骤中电耦合基板10。应当理解，第二焊球531也可以在后续步骤中进行基板10的耦合时再形成，本公开的实施例在此方面不做严格限制。
如图6D所示，从第二表面202以及第四表面404去除载板80，以露出电子集成电路20的第二表面202和塑封料40的第四表面404。
如图6E所示，在电子集成电路20的第二表面202和塑封料40的第四表面404上形成第二再布线层52。第二再布线层52包括电耦合至第二表面202以及过塑封料通孔401的多个第二凸点521。第二凸点521的数目可以为两个、三个、四个、五个或更多个，本公开的实施例在此方面不做严格限制。如图6E所示，在每个第二凸点521上还形成了多个第一焊球532以用于在后续步骤中电耦合光子集成电路30。在一些实施例中，如图6E所示，第二再布线层52还包括与电子集成电路20的第二表面202接触的第一导热层522。
如图6F所示，经由第一焊球532将光子集成电路30电耦合至第二再布线层52中的多个第二凸点521。在一些实施例中，还可以将光线阵列单元7光耦合至光子集成电路30，以用于向光子集成电路30传送光信号，或者从光子集成电路30接收光信号以用于向其他外部电路进行传送。在一些实施例中，还可以经由多个第二焊球531将基板10电耦合至第一再布线层51中的多个第一凸点511。
在一些实施例中，如图6G所示，还形成第一导热块61以及散热器70。第一导热块61连接在第一导热层522与散热器70之间，从而形成从电子集成电路20的第二表面202，经由第一导热层522和第一导热块61，到达散热器70的散热路径，能够将电子集成电路20产生的热量从第二表面202及时地消散掉。此外，散热器70还与光子集成电路30接触，以将光子集成电路30产生的热量及时地消散掉。
在一些实施例中，结合图2和图6B所示，形成塑封料40还包括：在塑封料40的靠近光纤阵列单元7的一端处形成缺口402，缺口402用于避开光纤阵列单元7。
在一些实施例中，如图6B所示，电子集成电路20的第一表面201与塑封料40的第三表面403基本上处于相同平面中(即共面)。利用这样的布置能够简化在利用塑封料40对电子集成电路20进行预模制时的制造工艺，并且便于在第一表面201和第三表面403上形成第一再布线层51。在其他实施例中，电子集成电路20的第一表面201与塑封料40的第三表面403可以不共面，这虽然在一定程度上增加了工艺难度，但是并不会影响电路功能的实现。
在一些实施例中，如图6D所示，电子集成电路20的第二表面202与塑封料40的第四表面404基本上处于相同平面中(即共面)。利用这样的布置能够简化在利用塑封料40对电子集成电路20进行预模制时的制造工艺，并且便于在第二表面202和第四表面404上形成第二再布线层52。在其他实施例中，电子集成电路20的第二表面202与塑封料40的第四表面404可以不共面，这虽然在一定程度上会增加工艺难度，但是并不会影响电路功能的实现。
在一些实施例中，如图6F所示，光子集成电路30包括第五表面305、与第五表面305相对的第六表面306、以及位于第五表面305与第六表面306之间的第二侧壁302。第五表面305朝向塑封料40和电子集成电路20，第六表面背对塑封料40和电子集成电路20。第五表面305经由第一焊球532电耦合至第二再布线层52中的第二凸点521。
在一些实施例中，结合图4所示，过塑封料通孔401包括导热通孔405，导热通孔405从第三表面403延伸到第四表面404，并且导热通孔405的一端(顶端)与第一导热层522接触。此外，第一再布线层51还包括与导热通孔405的另一端(底端)接触的第二导热层512。光电收发器组件200还包括第二导热块62，第二导热块62连接在基板10与第二导热层512之间。利用这样的布置，形成了从电子集成电路20的第二表面202，经由第一导热层522、导热通孔405、第二导热层512和第二导热块62，到达基板10的附加散热路径。以此方式，电子集成电路20在工作时产生的热量能够经由该附加散热路径传导到基板10中消散掉，从而能够进一步提升电子集成电路20的散热性能。
在一些实施例中，结合图5所示，第一再布线层51还包括与电子集成电路20的第一表面201接触的第三导热层513。此外，光电收发器组件200还包括第三导热块63，第三导热块63连接在基板10与第三导热层513之间。利用这样的布置，形成了从电子集成电路20的第一表面201，经由第三导热层513和第三导热块63，到达基板10的附加散热径。以此方式，电子集成电路20在工作时产生的热量能够经由该附加散热路径传导到基板10中消散掉，从而能够进一步提升电子集成电路20的散热性能。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (18)

  1. 一种光电收发器组件(200)，包括：
    电子集成电路(20)，包括第一表面(201)、与所述第一表面(201)相对的第二表面(202)、以及位于所述第一表面(201)与所述第二表面(202)之间的第一侧壁(203)；
    塑封料(40)，围绕所述第一侧壁(203)塑封所述电子集成电路(20)，所述塑封料(40)包括靠近所述第一表面(201)的第三表面(403)以及靠近所述第二表面(202)的第四表面(404)，并且所述塑封料(40)中设置有从所述第三表面(403)延伸到所述第四表面(404)的一个或多个过塑封料通孔(401)；
    第一再布线层(51)，设置在所述第一表面(201)以及所述第三表面(403)上，并且包括电耦合至所述第一表面(201)以及所述一个或多个过塑封料通孔(401)的多个第一凸点(511)；
    第二再布线层(52)，设置在所述第二表面(202)以及所述第四表面(404)上，并且包括电耦合至所述第二表面(202)以及所述一个或多个过塑封料通孔(401)的多个第二凸点(521)；以及
    光子集成电路(30)，经由多个第一焊球(532)电耦合至所述多个第二凸点(521)。
  2. 根据权利要求1所述的光电收发器组件(200)，还包括光耦合至所述光子集成电路(30)的光纤阵列单元(7)，其中所述塑封料(40)还包括设置在所述塑封料(40)的靠近所述光纤阵列单元(7)的一端处的缺口(402)，所述缺口(402)用于避开所述光纤阵列单元(7)。
  3. 根据权利要求1所述的光电收发器组件(200)，其中所述第一表面(201)与所述第三表面(403)处于相同平面中。
  4. 根据权利要求1所述的光电收发器组件(200)，其中所述第二表面(202)与所述第四表面(404)处于相同平面中。
  5. 根据权利要求1所述的光电收发器组件(200)，其中所述光子集成电路(30)包括第五表面(305)、与所述第五表面(305)相对的第六表面(306)、以及位于所述第五表面(305)与所述第六表面(306)之间的第二侧壁(302)，所述第五表面(305)经由所述多个第一焊球(532)电耦合至所述第二再布线层(52)中的所述多个第二凸点(521)。
  6. 根据权利要求5所述的光电收发器组件(200)，其中所述第二再布线层(52)还包括与所述电子集成电路(20)的所述第二表面(202)接触的第一导热层(522)，并且
    其中所述光电收发器组件(200)还包括第一导热块(61)以及散热器(70)，所述第一导热块(61)连接在所述第一导热层(522)与所述散热器(70)之间，并且所述散热器(70)与所述光子集成电路(30)的所述第六表面(306)接触。
  7. 根据权利要求6所述的光电收发器组件(200)，其中所述一个或多个过塑封料通孔(401)包括一个或多个导热通孔(405)，所述一个或多个导热通孔(405)的一端与所述第 一导热层(522)接触；
    其中所述第一再布线层(51)还包括与所述一个或多个导热通孔(405)的另一端接触的第二导热层(512)；并且
    其中所述光电收发器组件(200)还包括基板(10)以及第二导热块(62)，所述基板(10)经由多个第二焊球(531)电耦合至所述第一再布线层(51)中的所述多个第一凸点(511)，并且所述第二导热块(62)连接在所述基板(10)与所述第二导热层(512)之间。
  8. 根据权利要求1所述的光电收发器组件(200)，其中所述第一再布线层(51)还包括与所述电子集成电路(20)的所述第一表面(201)接触的第三导热层(513)，并且
    所述光电收发器组件(200)还包括基板(10)以及第三导热块(63)，所述基板(10)经由多个第二焊球(531)电耦合至所述第一再布线层(51)中的所述多个第一凸点(511)，并且所述第三导热块(63)连接在所述基板(10)与所述第三导热层(513)之间。
  9. 一种光模块，包括根据权利要求1至8中任一项所述的光电收发器组件(200)。
  10. 一种光交换机，包括根据权利要求1至8中任一项所述的光电收发器组件(200)。
  11. 一种光电收发器组件(200)的制造方法，包括：
    将电子集成电路(20)以及一个或多个过塑封料通孔(401)间隔布置在载板(80)上，其中所述电子集成电路(20)包括第一表面(201)、与所述第一表面(201)相对的第二表面(202)、以及位于所述第一表面(201)与所述第二表面(202)之间的第一侧壁(203)，并且所述第二表面(202)面朝所述载板(80)；
    围绕所述第一侧壁(203)形成塑封料(40)以塑封所述电子集成电路(20)以及所述一个或多个过塑封料通孔(401)，其中所述塑封料(40)包括靠近所述第一表面(201)的第三表面(403)以及靠近所述第二表面(202)的第四表面(404)，并且所述一个或多个过塑封料通孔(401)从所述第三表面(403)延伸到所述第四表面(404)；
    在所述第一表面(201)以及所述第三表面(403)上形成第一再布线层(51)，所述第一再布线层(51)包括电耦合至所述第一表面(201)以及所述一个或多个过塑封料通孔(401)的多个第一凸点(511)；
    从所述第二表面(202)以及所述第四表面(404)去除所述载板(80)；
    在所述第二表面(202)以及所述第四表面(404)上形成第二再布线层(52)，所述第二再布线层(52)包括电耦合至所述第二表面(202)以及所述一个或多个过塑封料通孔(401)的多个第二凸点(521)；
    经由多个第一焊球(532)将光子集成电路(30)电耦合至所述第二再布线层(52)中的所述多个第二凸点(521)。
  12. 根据权利要求11所述的制造方法，还包括将光纤阵列单元(7)光耦合至所述光子集成电路(30)，
    其中形成所述塑封料(40)还包括：在所述塑封料(40)的靠近所述光纤阵列单元(7)的一端处形成缺口(402)，所述缺口(402)用于避开所述光纤阵列单元(7)。
  13. 根据权利要求11所述的制造方法，其中所述第一表面(201)与所述第三表面(403)处于相同平面中。
  14. 根据权利要求11所述的制造方法，其中所述第二表面(202)与所述第四表面(404)处于相同平面中。
  15. 根据权利要求11所述的制造方法，其中所述光子集成电路(30)包括第五表面(305)、与所述第五表面(305)相对的第六表面(306)、以及位于所述第五表面(305)与所述第六表面(306)之间的第二侧壁(302)，并且
    其中将光子集成电路(30)电耦合至所述第二再布线层(52)中的所述多个第二凸点(521)包括：将所述第五表面(305)经由所述多个第一焊球(532)电耦合至所述第二再布线层(52)中的所述多个第二凸点(521)。
  16. 根据权利要求15所述的制造方法，其中形成所述第二再布线层(52)还包括：形成与所述电子集成电路(20)的所述第二表面(202)接触的第一导热层(522)，并且
    其中所述制造方法还包括形成第一导热块(61)以及散热器(70)，所述第一导热块(61)连接在所述第一导热层(522)与所述散热器(70)之间，并且所述散热器(70)与所述光子集成电路(30)的所述第六表面(306)接触。
  17. 根据权利要求16所述的制造方法，其中所述一个或多个过塑封料通孔(401)包括一个或多个导热通孔(405)，所述一个或多个导热通孔(405)的一端与所述第一导热层(522)接触，并且所述方法还包括：
    在所述第一再布线层(51)中形成与所述一个或多个导热通孔(405)的另一端接触的第二导热层(512)；
    经由多个第二焊球(531)将基板(10)电耦合至所述第一再布线层(51)中的所述多个第一凸点(511)；以及
    将述第二导热块(62)连接在所述基板(10)与所述第二导热层(512)之间。
  18. 根据权利要求11所述的制造方法，还包括：
    在所述第一再布线层(51)中形成与所述电子集成电路(20)的所述第一表面(201)接触的第三导热层(513)；
    经由多个第二焊球(531)将基板(10)电耦合至所述第一再布线层(51)中的所述多个第一凸点(511)；以及
    将第三导热块(63)连接在所述基板(10)与所述第三导热层(513)之间。
PCT/CN2021/132160 2021-11-22 2021-11-22 光电收发器组件及其制造方法 Ceased WO2023087323A1 (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240413038A1 (en) * 2023-06-08 2024-12-12 Samsung Electronics Co., Ltd. Stacked semiconductor package and lower semiconductor package used for the same
WO2025206793A1 (ko) * 2024-03-28 2025-10-02 주식회사 라이팩 광 시스템-인-패키지, 광 시스템-인-패키지의 제조방법 및 이를 이용한 광모듈

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118471839B (zh) * 2024-07-09 2024-09-27 华进半导体封装先导技术研发中心有限公司 一种具有光口保护的光电合封结构及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107958882A (zh) * 2017-12-20 2018-04-24 苏州晶方半导体科技股份有限公司 芯片的封装结构及其制作方法
CN108962773A (zh) * 2018-07-26 2018-12-07 华进半导体封装先导技术研发中心有限公司 扇出型封装结构及其制造方法
CN109473405A (zh) * 2018-12-07 2019-03-15 华进半导体封装先导技术研发中心有限公司 一种硅刻蚀通孔的扇出型晶圆级封装结构及其方法
WO2020000179A1 (zh) * 2018-06-26 2020-01-02 华为技术有限公司 芯片封装结构及芯片封装方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10001611B2 (en) * 2016-03-04 2018-06-19 Inphi Corporation Optical transceiver by FOWLP and DoP multichip integration
EP3436857B1 (en) * 2016-03-28 2024-12-25 Intel Corporation Optical fiber connection on package edge
US20180348434A1 (en) * 2017-05-31 2018-12-06 Intel Corporation Photonic die package with edge lens
US11841541B2 (en) * 2019-09-26 2023-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Package assembly and manufacturing method thereof
US11614592B2 (en) * 2020-01-22 2023-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107958882A (zh) * 2017-12-20 2018-04-24 苏州晶方半导体科技股份有限公司 芯片的封装结构及其制作方法
WO2020000179A1 (zh) * 2018-06-26 2020-01-02 华为技术有限公司 芯片封装结构及芯片封装方法
CN108962773A (zh) * 2018-07-26 2018-12-07 华进半导体封装先导技术研发中心有限公司 扇出型封装结构及其制造方法
CN109473405A (zh) * 2018-12-07 2019-03-15 华进半导体封装先导技术研发中心有限公司 一种硅刻蚀通孔的扇出型晶圆级封装结构及其方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4421852A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240413038A1 (en) * 2023-06-08 2024-12-12 Samsung Electronics Co., Ltd. Stacked semiconductor package and lower semiconductor package used for the same
WO2025206793A1 (ko) * 2024-03-28 2025-10-02 주식회사 라이팩 광 시스템-인-패키지, 광 시스템-인-패키지의 제조방법 및 이를 이용한 광모듈

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