WO2023087533A1 - 一种锤击刷新方法、锤击刷新电路及半导体存储器 - Google Patents

一种锤击刷新方法、锤击刷新电路及半导体存储器 Download PDF

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Publication number
WO2023087533A1
WO2023087533A1 PCT/CN2022/072108 CN2022072108W WO2023087533A1 WO 2023087533 A1 WO2023087533 A1 WO 2023087533A1 CN 2022072108 W CN2022072108 W CN 2022072108W WO 2023087533 A1 WO2023087533 A1 WO 2023087533A1
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Prior art keywords
refresh
signal
word line
hammer
state
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English (en)
French (fr)
Inventor
陈继兴
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to JP2023514723A priority Critical patent/JP7433518B2/ja
Priority to EP22738523.4A priority patent/EP4210059B1/en
Priority to KR1020237008481A priority patent/KR102834395B1/ko
Priority to US17/807,478 priority patent/US11894042B2/en
Publication of WO2023087533A1 publication Critical patent/WO2023087533A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of integrated circuits, in particular to a hammer refresh method, a hammer refresh circuit and a semiconductor memory.
  • Dynamic Random Access Memory is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells, and different memory cells need to be selected through word lines and bit lines. That is to say, there are a large number of word lines in the DRAM, and these word lines are arranged adjacent to each other. When a certain word line is subjected to a hammer attack (Row Hammer), the word lines adjacent to the word line may generate errors. In the related art, after the hammer attack is detected, the affected word lines are refreshed. However, the refresh process needs to be completed by means of two refresh commands, which occupies bandwidth resources and easily leads to refresh errors.
  • the present disclosure provides a hammer refresh method, a hammer refresh circuit and a semiconductor memory, which can reduce bandwidth resources occupied by the hammer refresh process and improve refresh accuracy.
  • an embodiment of the present disclosure provides a hammer refresh method, which includes:
  • the preset hammer refresh signal is set to an active state; wherein, the active state of the preset hammer refresh signal indicates that the hammer refresh instruction is executed in the first refresh cycle;
  • the preset hammer refresh signal is valid until a refresh period next to the first refresh period.
  • the method further includes: setting the preset hammer refresh signal to an invalid state when it is detected that the hammer refresh instruction is completed.
  • the hammer refresh command instructs to refresh the first adjacent word line of the target word line and the second adjacent word line of the target word line;
  • the method further includes: in the first refresh period, judging whether the first adjacent word line and the second adjacent word line are all refreshed; if the first adjacent word line is refreshed and the second adjacent word line If not refreshed, it is determined that the hammer refresh instruction has not been completed in the first refresh cycle; or if the first adjacent word line and the second adjacent word line are all refreshed, then it is determined that the hammer refresh is completed in the first refresh cycle instruction.
  • the method further includes: determining a first target state signal and a second target state signal; wherein, the first target state signal is used to record the refresh state of the first adjacent word line, and the second target state signal is used for When recording the refresh state of the second adjacent word line; when the first adjacent word line is refreshed, the first target state signal is set to an active state, and the second target state signal is set to an invalid state; When two adjacent word lines are refreshed, the first target state signal is set to an invalid state, and the second target state signal is set to an active state.
  • the method when it is detected that the hammer refresh command has not been completed within the first refresh cycle, the method further includes: judging whether a word line activation command is received; if the judging result is yes, setting the first target state to signal and the second target state signal are set to an inactive state.
  • the method further includes: judging whether the preset hammer refresh signal is in a valid state; if the preset hammer refresh signal is in a valid state, determining a first target state signal and a second target state signal; Perform word line refresh processing on adjacent word lines of the target word line according to the first target state signal and the second target state signal.
  • performing word line refresh processing on word lines adjacent to the target word line according to the first target state signal and the second target state signal includes: When both are in an invalid state, perform word line refresh processing on the first adjacent word line and the second adjacent word line; when the first target state signal is in an active state and the second target state signal is in an invalid state , perform two word line refreshing processes on the second adjacent word line.
  • an embodiment of the present disclosure provides a hammer refresh circuit, including:
  • a detection circuit for determining a hammer refresh trigger signal and a refresh execution signal
  • the hammer refresh trigger signal indicates that a hammer refresh instruction for the target word line is received and the refresh execution signal indicates that the hammer refresh instruction has not been completed, outputting a preset hammer refresh signal in an active state;
  • the valid state of the preset hammer refresh signal indicates that the hammer refresh command is executed in the first refresh cycle, and the valid state of the preset hammer refresh signal will be executed if the hammer refresh command is not completed in the first refresh cycle Continue to the next refresh period of the first refresh period.
  • the refresh execution signal includes an initial refresh execution signal and a refresh pulse signal
  • the detection circuit includes a first clock circuit, a first refresh state determination circuit and a control signal output circuit; wherein, the first refresh state determination circuit is used to refresh the trigger signal according to the hammering, the first clock signal and the first inversion The clock signal is used to determine the first refresh state signal and the second refresh state signal; the first clock circuit is used to determine the first clock signal and the first inverted clock according to the first refresh state signal, the initial refresh execution signal and the refresh pulse signal signal; the control signal output circuit is used to determine the preset hammer refresh signal according to the hammer refresh trigger signal and the second refresh state signal; wherein, the hammer refresh instruction indicates the first adjacent word line and the target word line to the target word line The second adjacent word line of the word line performs the word line refresh process, the initial refresh execution signal is used to indicate the word line refresh process that occurs for the first time in each refresh cycle, and the refresh pulse signal is used to indicate each time in each refresh cycle The word line refresh process occurs.
  • the first clock circuit includes a first two-input NAND gate, a second two-input NAND gate, and a first two-input NAND gate; wherein, the input terminals of the first two-input NAND gate are respectively connected to the first refresh state The signal is connected to the initial refresh execution signal; the input terminals of the second two-input NAND gate are respectively connected to the output terminals of the first two-input NAND gate and the refresh pulse signal, and the output terminals of the second two-input NAND gate are used to output the first An inverted clock signal; the input end of the first NOT gate is connected to the first inverted clock signal, and the output end of the first NOT gate is used to output the first clock signal.
  • the first refresh state determination circuit includes a first two-input NOR gate, a third two-input NAND gate, a second NOT gate, a first flip-flop, and a second flip-flop; wherein, the first two-input The input ends of the NOR gate are respectively connected with the first refresh state signal and the second refresh state signal, and the input ends of the third two-input NAND gate are respectively connected with the output ends of the first two-input NOR gate and the hammer refresh trigger signal , the input end of the second NOT gate is connected with the output end of the third two-input NAND gate respectively; the input end of the first flip-flop is connected with the output end of the second NOT gate, and the clock end of the first flip-flop is respectively connected with the first The clock signal is connected to the first inverted clock signal, the output terminal of the first flip-flop is used to output the first refresh status signal; the input terminal of the second flip-flop is connected to the first refresh status signal, and the clock terminals of the second flip-flop are respectively
  • control signal output circuit includes a third NOT gate, a fourth two-input NAND gate, and a fourth NOT gate; wherein, the input terminal of the third NOT gate is connected to the second refresh status signal, and the fourth two-input The input end of the NAND gate is respectively connected with the output end of the third NOT gate and the hammer refresh trigger signal; the input end of the fourth NOT gate is connected with the output end of the fourth second input NAND gate, and the output of the fourth NOT gate The terminal is used to output the preset hammer refresh signal.
  • the hammer refresh circuit further includes a state counting circuit; the state count circuit is used to receive the preset hammer refresh signal and the word line state signal, and determine according to the preset hammer refresh signal and the word line state signal A first target state signal and a second target state signal; wherein, the first target state signal is used to record the refresh state of the first adjacent word line, and the second target state signal is used to record the refresh state of the second adjacent word line.
  • the word line state signal includes a refresh state valid signal and a word line start pulse signal;
  • the state counting circuit includes a second clock circuit, a second refresh state determination circuit and a reset circuit; wherein, the second clock circuit is used for Determine the second clock signal and the second inverted clock signal according to the preset hammer refresh signal, the refresh state valid signal and the word line open pulse signal;
  • the reset circuit is used to determine the refresh state valid signal, the word line open pulse signal and the The first target state signal is used to determine the reset signal;
  • the second refresh state determination circuit is used to determine the first target state signal and the second target state signal according to the second clock signal, the second inverted clock signal and the reset signal; wherein,
  • the refresh status valid signal indicates whether it is in a refresh cycle, and the word line on pulse signal indicates the start of any word line.
  • the second clock circuit includes a first three-input NAND gate and a fifth NAND gate; wherein, the input terminals of the first three-input NAND gate are respectively connected to the preset hammer refresh signal, the refresh state valid signal and word line open pulse signal connection, the output end of the first three-input NAND gate is used to output the second inverted clock signal; the input end of the fifth NAND gate is connected with the output end of the first three-input NAND gate, and the fifth NAND gate The output terminal of the gate is used to output the second clock signal.
  • the second refresh state determination circuit includes a third flip-flop, a fourth flip-flop and a sixth NOT gate; the input end of the third flip-flop is connected to the output end of the third flip-flop through the sixth NOT gate, And the output end of the third flip-flop is used to output the first target state signal; the clock end of the third flip-flop is respectively connected with the second clock signal and the second inverted clock signal; the input end of the fourth flip-flop is connected with the first target The state signal is connected, the clock end of the fourth flip-flop is respectively connected with the second clock signal and the second inverted clock signal, and the output end of the fourth flip-flop is used to output the second target state signal; the third flip-flop and the fourth flip-flop The respective reset terminals of the flip-flops are connected to the reset signal.
  • the reset circuit includes a seventh NOT gate and a second three-input NAND gate; the input terminal of the seventh NOT gate is connected to the refresh state valid signal, and the input terminal of the second three-input NAND gate is respectively connected to the seventh
  • the output terminal of the NOT gate is connected with the word line start pulse signal and the first target state signal, and the output terminal of the second three-input NAND gate is used to output a reset signal.
  • an embodiment of the present disclosure provides a semiconductor memory, including the hammer refresh circuit as described in the second aspect.
  • An embodiment of the present disclosure provides a hammer refresh method, a hammer refresh circuit, and a semiconductor memory, which determine a hammer refresh instruction for a target word line; and set a preset hammer refresh signal to be valid according to the hammer refresh instruction. state; wherein, the valid state of the preset hammer refresh signal indicates that the hammer refresh instruction is executed in the first refresh cycle; if it is detected that the hammer refresh instruction is not completed within the first refresh cycle, Then, the valid state of the preset hammer refresh signal is extended to the next refresh period of the first refresh period.
  • the valid state of the preset hammer refresh signal lasts for one refresh cycle, so that the hammer refresh instruction is completed within one refresh cycle; in the case of occasional errors, the valid state of the preset hammer refresh signal It will continue until the next refresh cycle, so that the hammer refresh instruction can be completed in two refresh cycles, which can not only save bandwidth resources, but also improve the accuracy of the hammer refresh.
  • FIG. 1A is a schematic diagram of a hammer refresh process provided by the related art
  • FIG. 1B is a schematic diagram of another hammer refresh process provided by the related art
  • FIG. 2 is a schematic diagram of another hammer refresh process provided by the related art
  • FIG. 3 is a schematic flowchart of a hammer refresh method provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a hammer refresh circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a detection circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a specific circuit structure of a first clock circuit provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a specific circuit structure of a first refresh state determination circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a specific circuit structure of a control signal output circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of signal timing of a detection circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another hammer refresh circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a state counting circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a specific circuit structure of a second clock circuit provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a specific circuit structure of a second refresh state determination circuit provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a specific circuit structure of a reset circuit provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific ordering of objects. Understandably, “first ⁇ second ⁇ third 3" where permitted, the specific order or sequence may be interchanged such that the embodiments of the disclosure described herein can be practiced in sequences other than those illustrated or described herein.
  • Row Hammer hammer attack, or row hammer
  • DRAM dynamic random access memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • Word Line, WL word line
  • Bit Line, BL bit line
  • RHR preset hammer refresh signal
  • RHRact1 first target status signal
  • RHRact2 second target status signal
  • Refreshpulse1 initial refresh execution signal
  • RefPulseCounter refresh pulse signal
  • RHRCk first clock signal
  • RHRCkN first inverted clock signal
  • RHRState1 first refresh state signal
  • RHRState2 second refresh state signal
  • RHRCounterN second inverted clock signal
  • ResetN reset signal
  • DRAM is a semiconductor storage device commonly used in computers. It consists of many repeated memory cells to form a Memory Array, and different memory cells need to be selected through word lines and bit lines.
  • FIG. 1A it shows a schematic diagram of a hammer refresh process provided by the related art.
  • FIG. 1B it shows a schematic diagram of another hammer refresh process provided by the related art.
  • ActCmd refers to the word line activation command
  • PreCmd refers to the word line precharge command (Pre)
  • REFCmdA refers to the first refresh command
  • REFCmdB refers to the second refresh command.
  • the time required to complete a refresh command is also called a refresh cycle.
  • the refresh of adjacent word lines needs to involve two refresh commands, which not only occupies bandwidth resources, but also easily leads to some errors.
  • FIG. 1B refresh of adjacent word lines is completed in one refresh command, but this method may also cause RHR errors in some occasional cases.
  • FIG. 2 it shows a schematic diagram of the process of another hammer refresh method provided by the related art.
  • the RHR signal is in a valid state to instruct the Memory Array to perform hammer refresh in the refresh command (REFCmd1, etc.).
  • the refresh command corresponds to two pulses, that is, 1st Pulse and 2nd Pulse, so that RHRa and RHRb are respectively executed via these two pulses, so as to complete the hammer refresh in one refresh command.
  • an embodiment of the present disclosure provides a hammer refresh method, which determines a hammer refresh command for a target word line; according to the hammer refresh command, sets a preset hammer refresh signal to an active state; wherein, the The valid state of the preset hammer refresh signal indicates that the hammer refresh command is executed in the first refresh cycle; if it is detected that the hammer refresh command is not completed in the first refresh cycle, the preset It is assumed that the valid state of the hammer refresh signal continues to a refresh period next to the first refresh period.
  • the valid state of the preset hammer refresh signal lasts for one refresh cycle, so that the hammer refresh instruction is completed within one refresh cycle; in the case of occasional errors, the valid state of the preset hammer refresh signal It will continue until the next refresh cycle, so that the hammer refresh instruction can be completed in two refresh cycles, which can not only save bandwidth resources, but also improve the accuracy of the hammer refresh.
  • FIG. 3 shows a schematic flow chart of a hammer refresh method provided by an embodiment of the present disclosure.
  • the method may include:
  • the hammer refresh method provided by the embodiments of the present disclosure is applied to semiconductor memory devices, such as DRAM, SDRAM, etc., and can better refresh word lines subjected to Row Hammer attacks.
  • the target word line refers to the target row in the Row Hammer attack
  • the first adjacent word line and the second adjacent word line refer to the victim row in the Row Hammer attack.
  • S102 According to the hammer refresh instruction, set the preset hammer refresh signal to an active state; wherein, the active state of the preset hammer refresh signal indicates that the hammer refresh instruction is executed in the first refresh cycle.
  • a preset hammer refresh signal specially used to instruct a memory array (Memory Array) to perform a hammer refresh operation is set.
  • the Memory Array needs to perform hammer refresh on the specified word line; if the preset hammer refresh signal is invalid, the Memory Array does not need to perform hammer refresh.
  • a preset hammer refresh signal is made active, so as to execute the refresh command in the first refresh cycle.
  • the refresh period can be understood as a time period for performing a refresh operation, specifically refers to the time after a refresh command is received and before the next operation command is received, that is, one refresh period corresponds to one refresh command.
  • the first refresh period may refer to the latest refresh period after the preset hammer refresh signal is in an active state.
  • the first refresh cycle can refresh the first adjacent word line and the second adjacent word line, and once the hammer refresh instruction is completed. However, if there is an occasional error, the first refresh cycle may not be able to complete the hammer refresh command, and it is necessary to continue the valid state of the preset hammer refresh signal to the next refresh cycle of the first refresh cycle, so as to complete the hammer refresh within two refresh cycles. Click Refresh command.
  • the preset hammer refresh signal is set to an invalid state if it is detected that the hammer refresh command is completed.
  • the preset hammer refresh signal will be set to an invalid state after the end of the first refresh cycle, and the hammer refresh process will be completed by a refresh command at this time ;
  • the valid state of the preset hammer refresh signal will continue until the next refresh cycle of the first refresh cycle, so that the next refresh cycle continues to perform hammer refresh process, at this time the hammer refresh process is completed through two refresh commands.
  • the valid state of the preset hammer refresh signal will be fixed for two refresh cycles, so that one hammer refresh command can be completed in two refresh commands, but the occupied bandwidth is relatively large. Waste of resources; in another related technology, the valid state of the preset hammer refresh signal will be fixed for one refresh cycle, so that one hammer refresh instruction can be completed in one refresh command, but the refresh may fail due to occasional errors.
  • a hammer refresh method capable of automatic error correction.
  • the valid state of the preset hammer refresh signal lasts for one refresh cycle, so that the hammer refresh can be completed within one refresh cycle.
  • the valid state of the preset hammer refresh signal will continue to the next refresh cycle, so that the hammer refresh instruction can be completed through two refresh cycles, which can not only save bandwidth resources, but also improve the hammer Refreshed correctness.
  • the hammer refresh command instructs to refresh the first adjacent word line of the target word line and the second adjacent word line of the target word line.
  • the method may also include:
  • the hammer refresh instruction includes refreshing the first adjacent word line and the second adjacent word line on both sides of the target word line respectively. Therefore, it is judged whether the hammer refresh command is completed in the first refresh cycle according to the refresh states of the first adjacent word line and the second adjacent word line.
  • a first target state signal and a second target state signal are set to be used to record the states of the first adjacent word line and the second adjacent word line, respectively.
  • the method can also include:
  • Determining a first target state signal and a second target state signal wherein, the first target state signal is used to record the refresh state of the first adjacent word line, and the second target state signal is used to record the refresh state of the second adjacent word line ;
  • the first target state signal is set to an inactive state
  • the second target state signal is set to an active state
  • the initial states of the first target state signal and the second target state signal are both invalid.
  • the first adjacent word line is refreshed, and at this time, the first target state signal jumps to be valid, and the second target state signal is still invalid; finally, the second adjacent word line is refreshed. Refresh, the first target status signal jumps to invalid again, the second target status signal jumps to valid, and the hammer refresh command is completed.
  • the first target state signal and the second target state signal will be reset to an invalid state again, and the specific reset process can be realized by circuits with various principles, which will not be described further in the embodiments of the present disclosure.
  • a word line activation operation may be inserted between the refresh operations of the first adjacent word line and the second adjacent word line. That is to say, only the refresh of the first adjacent word line is completed in the first refresh cycle, and a word line activation command is received after the first refresh cycle ends, thereby entering the activation operation cycle, and then entering the next refresh cycle again, And the operation on the second adjacent word line is completed in the next refresh period.
  • This situation can easily lead to processing errors, and the embodiments of the present disclosure record this situation separately for subsequent processing.
  • the first target state signal and the second target state signal are jointly deasserted.
  • the method may further include:
  • both the first target state signal and the second target state signal are set to an invalid state.
  • word line activation command may be an activation command for any word line in the Memory Array, and is not limited to the target word line, the first adjacent word line and the second adjacent word line.
  • the method may also include:
  • the preset hammer refresh signal is in a valid state, determining a first target state signal and a second target state signal;
  • performing word line refresh processing on word lines adjacent to the target word line according to the first target state signal and the second target state signal may include:
  • the reasons for not choosing to refresh the two word lines separately include: only one word line needs to be turned on to perform two refreshes on a word line, the process is simple, and the power consumption is low; the circuit design is complex For this part, please refer to the subsequent instructions on the hammer refresh circuit.
  • case 2 may also adopt a way of refreshing the first adjacent word line and the second adjacent word line separately.
  • the definitions of the valid state and the invalid state may be selected according to actual application scenarios.
  • the valid state of a certain signal can mean that the signal is in a high level state
  • the valid state of a certain signal can mean that the signal is in a low level state
  • the valid state of a certain signal can mean that the signal is in a low level state
  • Level state the valid state of a certain signal may mean that the signal is in a high level state.
  • the embodiments of the present disclosure provide a hammer refresh method with an automatic error correction function.
  • the hammer refresh method is accomplished by means of a preset hammer refresh signal, a first target state signal and a second target state signal.
  • the valid state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh instruction can be completed within one refresh cycle; in the case of occasional errors, the preset hammer refresh signal
  • the valid state of the system will continue until the next refresh cycle, so that the hammer refresh instruction can be completed in two refresh cycles, which can not only save bandwidth resources, but also ensure the smooth completion of the hammer refresh; on the other hand, the first target state signal and the second target state signal
  • the two target state signals are used to record the refresh states of the first adjacent word line and the second adjacent word line, and whether a word line activation command is received after the refresh of the first adjacent word line and before the refresh of the second adjacent word line , so as to perform subsequent targeted processing,
  • An embodiment of the present disclosure provides a hammer refresh method, which determines the hammer refresh command for the target word line; according to the hammer refresh command, sets the preset hammer refresh signal to an active state; wherein, the preset hammer refresh signal The valid state of the signal indicates that the hammer refresh command is executed in the first refresh cycle; if it is detected that the hammer refresh command is not completed in the first refresh cycle, the valid state of the preset hammer refresh signal is extended to the first refresh cycle next refresh cycle.
  • the valid state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh instruction can be completed within one refresh cycle; in the case of occasional errors, the valid state of the preset hammer refresh signal It will continue until the next refresh cycle, so that the hammer refresh instruction can be completed in two refresh cycles, which can not only save bandwidth resources, but also improve the accuracy of the hammer refresh.
  • FIG. 4 shows a schematic structural diagram of a hammer refresh circuit 20 provided by an embodiment of the present disclosure.
  • the hammer refresh circuit 20 includes a detection circuit 21 for determining a hammer refresh trigger signal RHRStart and a refresh execution signal; and
  • the preset hammer refresh signal RHR in an active state is output.
  • the hammering refresh circuit 20 provided by the embodiment of the present disclosure is applied to semiconductor memory devices, such as DRAM, SDRAM, etc., and can better refresh word lines that suffer from Row Hammer attacks.
  • the hammer refresh circuit 20 includes a detection circuit 21 , the input terminal of the detection circuit 21 is a hammer refresh trigger signal RHRStart and a refresh execution signal, and the output terminal of the detection circuit 21 is a preset hammer refresh signal RHR.
  • different states of the hammer refresh trigger signal RHR can indicate whether the hammer refresh command for the target word line is received; different states of the refresh execution signal can indicate whether the hammer refresh command is completed.
  • the valid state of the preset hammer refresh signal RHR indicates that the hammer refresh command is executed in the first refresh cycle, and the valid state of the preset hammer refresh signal RHR does not complete the hammer refresh command in the first refresh cycle. The case will continue to the next refresh period of the first refresh period.
  • the detection circuit 21 when the hammer refresh instruction for the target word line is received and the execution of the hammer refresh instruction is not completed, the detection circuit 21 will continue to output the preset hammer refresh signal RHR in an active state to indicate the storage
  • the array performs related hammer refresh processing; in addition, when no hammer refresh command for the target word line is received, or when the hammer refresh command has been completed, the detection circuit 21 will continue to output the preset in an invalid state Hammer refresh signal RHR.
  • the valid state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh instruction can be completed within one refresh cycle; in the case of occasional errors, the valid state of the preset hammer refresh signal It will continue until the next refresh cycle, so that the hammer refresh instruction can be completed in two refresh cycles, which can not only save bandwidth resources, but also improve the accuracy of the hammer refresh.
  • the hammer refresh instruction indicates to perform word line refresh processing on the first adjacent word line of the target word line and the second adjacent word line of the target word line, that is, one hammer refresh instruction includes two word line refresh processing.
  • the refresh execution signal includes an initial refresh execution signal Refreshpulse1 and a refresh pulse signal RefPulseCounter.
  • the initial refresh execution signal Refreshpulse1 is used to indicate the word line refresh process that occurs for the first time in each refresh cycle
  • the refresh pulse signal RefPulseCounter is used to indicate the word line refresh process that occurs every time in each refresh cycle.
  • FIG. 5 shows a schematic structural diagram of a detection circuit 21 provided by an embodiment of the present disclosure.
  • the detection circuit 21 includes a first clock circuit 211, a first refresh state determination circuit 212 and a control signal output circuit 213; wherein,
  • the first refresh state determination circuit 212 is configured to determine the first refresh state signal RHRState1 and the second refresh state signal RHRState2 according to the hammer refresh trigger signal RHRStart, the first clock signal RHRCk and the first inverted clock signal RHRCkN;
  • the first clock circuit 211 is configured to determine the first clock signal RHRCk and the first inverted clock signal RHRCkN according to the first refresh state signal RHRState1, the initial refresh execution signal Refreshpulse1 and the refresh pulse signal RefPulseCounter;
  • the control signal output circuit 213 is configured to determine a preset hammer refresh signal RHR according to the hammer refresh trigger signal RHRStart and the second refresh state signal RHRState2 .
  • the detection circuit 21 includes at least the following three parts: a first clock circuit 211 , a first refresh state determination circuit 212 and a control signal output circuit 213 . in,
  • the first clock circuit 211 is mainly used to output the first clock signal RHRCk and the first inverted clock signal RHRCkN, so as to provide necessary signal support for the subsequent first refresh state determination circuit 212 .
  • FIG. 6 shows a schematic diagram of a specific circuit structure of a first clock circuit 211 provided by an embodiment of the present disclosure.
  • the first clock circuit includes a first two-input NAND gate 2111, a second two-input NAND gate 2112 and a first NAND gate 2113; wherein,
  • the 2111 input terminals of the first two-input NAND gate are respectively connected to the first refresh state signal RHRState1 and the initial refresh execution signal Refreshpulse1; the input terminals of the second two-input NAND gate 2112 are respectively connected to the output of the first two-input NAND gate 2111 terminal is connected to the refresh pulse signal RefPulseCounter, the output terminal of the second two-input NAND gate 2112 is used to output the first inverted clock signal RHRCkN; the input terminal of the first NOT gate 2113 is connected to the first inverted clock signal RHRCkN, and the first The output end of the NOT gate 2113 is used to output the first clock signal RHRCk.
  • the first refresh state determination circuit 212 is mainly used to output the first refresh state signal RHRState1 and the second refresh state signal RHRState2 to record the refresh state of the first adjacent word line and the second adjacent word line, for subsequent
  • the control signal output circuit 213 provides necessary signal support.
  • FIG. 7 shows a schematic diagram of a specific circuit structure of a first refresh state determining circuit 212 provided by an embodiment of the present disclosure.
  • the first refresh state determination circuit 212 includes a first two-input NOR gate 2121, a third two-input NAND gate 2122, a second NOT gate 2123, a first flip-flop 2124 and a second flip-flop 2125; in,
  • the input ends of the first two-input NOR gate 2121 are respectively connected to the first refresh state signal RHRState1 and the second refresh state signal RHRState2, and the input ends of the third two-input NOR gate 2122 are connected to the first two-input NOR gate 2121 respectively.
  • the output end is connected to the hammer refresh trigger signal RHRStart, the input end of the second NOT gate 2123 is respectively connected to the output end of the third two-input NAND gate 2122; the input end of the first flip-flop 2124 is connected to the output of the second NOT gate 2123
  • the clock terminals of the first flip-flop 2124 are respectively connected to the first clock signal RHRCk and the first inverted clock signal RHRCkN, and the output end of the first flip-flop 2124 is used to output the first refresh state signal RHRState1; the second flip-flop
  • the input end of the 2125 is connected to the first refresh state signal RHRState1, the clock end of the second flip-flop 2125 is respectively connected to the first clock signal RHRCk and the first inverted clock signal RHRCkN, and the output end of the second flip-flop 2125 is used to output the first Two refresh state signal RHRState2.
  • respective reset terminals of the first flip-flop 2124 and the second flip-flop 2125 are connected to a signal RST for resetting the first refresh status signal and the second refresh status signal.
  • the control signal output circuit 213 is mainly used to preset the hammer refresh signal RHR.
  • FIG. 8 shows a schematic diagram of a specific circuit structure of a control signal output circuit 213 provided by an embodiment of the present disclosure.
  • the control signal output circuit 213 includes a third NOT gate 2131, a fourth two-input NAND gate 2132 and a fourth NOT gate 2133; wherein,
  • the input terminal of the third NOT gate 2131 is connected to the second refresh state signal RHRState2, the input terminal of the fourth NAND gate 2132 is respectively connected to the output terminal of the third NOT gate 2131 and the hammer refresh trigger signal RHRStart; the fourth NOT gate
  • the input terminal of the gate 2133 is connected to the output terminal of the fourth two-input NAND gate 2132 , and the output terminal of the fourth NOT gate 2133 is used to output the preset hammer refresh signal RHR.
  • the first refresh state determination circuit 212 the first clock circuit 211 and the control signal output circuit 213, the first The refresh state signal RHRState1 and the second refresh state signal RHRState2 finally output a preset hammer refresh signal RHR.
  • the initial refresh execution signal Refreshpulse1 is in an active state during the first pulse (the pulse is used to turn on the word line) in the refresh cycle, and is in an invalid state at other times; the refresh pulse
  • the signal RefPulseCounter generates a square wave for each pulse in the refresh cycle
  • RHRStart generates a rising edge after receiving the hammer refresh instruction, and generates a falling edge after the hammer refresh instruction ends, and the change mode of other signals can be deduced through specific circuit components.
  • the first pulse (1 st pulse) in the first refresh cycle (that is, the refresh cycle corresponding to REFCmd1) is normally executed, but the second pulse (2 nd pulse) is missing due to accidental errors, resulting in Only RHRa is executed in the first refresh cycle, and RHRa and RHRb need to be executed again in the next refresh cycle.
  • FIG. 9 shows a schematic diagram of a signal timing sequence of a detection circuit 21 provided by an embodiment of the present disclosure. As shown in Figure 9,
  • RHRStart changes to a high level (that is, an active state), and RHR changes to a high level accordingly to indicate that the first adjacent word line and the second adjacent word line are refreshed deal with;
  • the word line refresh process ie, RHRa
  • the word line refresh process ie, RHRa
  • Refreshpulse1 is high level
  • RefPulseCounter generates a square wave after the address of each Pulse is latched, thus causing RHRCkN (not shown in the figure) and RHRCk output by the first clock circuit to generate
  • RHRCkN not shown in the figure
  • RHRCk output by the first clock circuit to generate
  • RHRState1 changes from a low level to a high level during the process of RHRa, so as to record and complete the refresh of the first adjacent word line;
  • RHRa and RHRb once in the 1st Pulse and 2nd Pulse of the next refresh cycle respectively.
  • Refreshpulse1 is only in the high level state during the 1st Pulse period, and RefPulseCounter generates a square wave for each Pulse, so that RHRCkN and RHRCk change accordingly.
  • RHRState1 will be on the falling edge of the second square wave of RefPulseCounter Change from high level to low level, otherwise, RHRState2 will change from low level to high level at the falling edge of the second square wave of RefPulseCounter to indicate that the refresh of the second adjacent word line is completed.
  • RHRStart remains high, RHRState2 changes from low to high, so the RHR signal changes from high to low, and RHRStart will change from high to the falling edge of 2nd Pulse changes to a low level.
  • the valid state of the preset hammer refresh signal RHR will continue until the next refresh cycle, so that the hammer refresh command can be completed in two refresh cycles, which can save bandwidth resources and improve hammer speed. Click to refresh the correctness.
  • word line activation commands need to be avoided between refresh operations on the first adjacent word line and the second adjacent word line. That is to say, if a word line activation instruction is received after the first adjacent word line is refreshed and before the second adjacent word line is refreshed, it needs to be recorded for subsequent processing.
  • FIG. 10 shows a schematic structural diagram of another hammer refresh circuit 20 provided by an embodiment of the present disclosure.
  • the hammer refresh circuit 20 also includes a state counting circuit 22;
  • the state counting circuit 22 is configured to receive the preset hammer refresh signal RHR and the word line state signal, and determine the first target state signal RHRAct1 and the second target state signal RHRAct2 according to the preset hammer refresh signal RHR and the word line state signal ;
  • the state counting circuit 22 is configured to output the first target state signal RHRAct1 and the second target state signal RHRAct2 , so as to record the current hammer refresh process.
  • the first target state signal RHRAct1 is used to record the refresh state of the first adjacent word line
  • the second target state signal RHRAct2 is used to record the refresh state of the second adjacent word line.
  • the word line status signal includes a refresh status valid signal Rfsh and a word line enable pulse signal RasEnpulse
  • the refresh status valid signal Rfsh indicates whether it is in a refresh cycle
  • the word line enable pulse signal RasEnpulse indicates that any word line is enabled.
  • the refresh state valid signal Rfsh is in the valid state; is in an invalid state.
  • the word line enable pulse signal RasEnpulse generates a square wave during the turn-on period of any word line.
  • FIG. 11 shows a schematic structural diagram of a state counting circuit 22 provided by an embodiment of the present disclosure.
  • the state counting circuit 22 includes a second clock circuit 221, a second refresh state determination circuit 222 and a reset circuit 223; wherein,
  • the second clock circuit 221 is used to determine the second clock signal RHRCounter and the second inverted clock signal RHRCounterN according to the preset hammer refresh signal RHR, the refresh state valid signal Rfsh and the word line enable pulse signal RasEnpulse;
  • the reset circuit 223 is used to determine the reset signal ResetN according to the refresh state effective signal Rfsh, the word line enable pulse signal RasEnpulse and the first target state signal RHRAct1;
  • the second refresh state determination circuit 222 is configured to determine the first target state signal RHRAct1 and the second target state signal RHRAct2 according to the second clock signal RHRCounter, the second inverted clock signal RHRCounterN and the reset signal ResetN;
  • the state counting circuit 22 includes at least the following three parts: a second clock circuit 221 , a second refresh state determination circuit 222 and a reset circuit 223 . in,
  • the second clock circuit 221 is mainly used to output the second clock signal RHRCounter and the second inverted clock signal RHRCounterN, so as to provide necessary signal support for the subsequent second refresh state determination circuit 222 .
  • FIG. 12 shows a schematic diagram of a specific circuit structure of a second clock circuit 221 provided by an embodiment of the present disclosure.
  • the second clock circuit 221 includes a first three-input NAND gate 2211 and a fifth NOT gate 2212; wherein,
  • the input terminals of the first three-input NAND gate 2211 are respectively connected to the preset hammer refresh signal RHR, the refresh state valid signal Rfsh and the word line enable pulse signal RasEnpulse, and the output terminals of the first three-input NAND gate 2211 are used to output the first three-input NAND gate 2211.
  • the second refresh state determination circuit 222 is mainly used to output the first target state signal RHRAct1 and the second refresh state signal RHRAct2 to record the refresh state of the first adjacent word line and the second adjacent word line.
  • FIG. 13 shows a schematic diagram of a specific circuit structure of a second refresh state determination circuit 222 provided by an embodiment of the present disclosure.
  • the second refresh state determination circuit 222 includes a third flip-flop 2221, a fourth flip-flop 2222 and a sixth NOT gate 2223;
  • the input end of the third flip-flop 2221 is connected to the output end of the third flip-flop 2221 through the sixth NOT gate 2223, and the output end of the third flip-flop 2221 is used to output the first target state signal RHRAct1; the third flip-flop 2221
  • the clock end is respectively connected with the second clock signal RHRCounter and the second inverted clock signal RHRCounterN; the input end of the fourth flip-flop 2222 is connected with the first target state signal RHRAct1, and the clock end of the fourth flip-flop 2222 is respectively connected with the second clock signal RHRCounter is connected to the second inverted clock signal RHRCounterN, and the output terminal of the fourth flip-flop 2222 is used to output the second target state signal RHRAct2; the respective reset terminals of the third flip-flop 2221 and the fourth flip-flop 2222 are connected to the reset signal ResetN connect.
  • the reset circuit 223 is mainly used for outputting a reset signal ResetN to provide necessary signal support for the second refresh state determining circuit 222 .
  • FIG. 14 shows a schematic diagram of a specific circuit structure of the reset circuit 223 provided by an embodiment of the present disclosure.
  • the reset circuit 223 includes a seventh NOT gate 2231 and a second three-input NAND gate 2232;
  • the input terminal of the seventh NOT gate 2231 is connected to the refresh state effective signal Rfsh, and the input terminal of the second three-input NAND gate 2232 is respectively connected to the output terminal of the seventh NOT gate 2231, the word line enable pulse signal RasEnpulse and the first target state signal RHRAct1 is connected, and the output terminal of the second three-input NAND gate 2232 is used to output the reset signal ResetN.
  • the reset signal ResetN is active at low level, that is, when the reset signal ResetN is at low level, the third flip-flop 2221 and the fourth flip-flop 2222 are reset.
  • the change logic is:
  • the first adjacent word line is refreshed during the first refresh cycle. Specifically, when the first word line is turned on, the first target state signal RHRAct1 changes to an active state, and the second target state signal RHRAct2 remains in an inactive state.
  • the word line activation instruction is not received between the first refresh cycle and the next refresh cycle, that is, there is no word line activation between the first refresh cycle and the next refresh cycle, and at this time in the next refresh cycle
  • the first target state signal RHRAct1 remains valid
  • the second target state signal RHRAct2 remains invalid
  • a word line activation command is received between the first refresh cycle and the next refresh cycle, and in the first refresh cycle
  • the reset signal ResetN is active, and the first target state signal RHRAct1 and the second target state signal RHRAct2 are both deactivated.
  • both the first target state signal RHRAct1 and the second target state signal RHRAct2 are reset to the invalid state, and the specific reset process can be realized by circuits with various principles, and the embodiments of the present disclosure will not expand describe.
  • the refresh state of the first adjacent word line and the second adjacent word line can be accurately recorded, and subsequent refresh processing can be performed in a targeted manner to avoid the first adjacent word line
  • a word line activation command is inserted between the refresh of the word line and the refresh of the second adjacent word line, thereby causing a problem of errors.
  • FIGS. 6-8 and FIGS. 11-13 are only one possible structure of the corresponding circuits, and those skilled in the art can add, delete, and modify corresponding circuit elements according to actual application scenarios of different circuits.
  • the preset hammer refresh signal can be provided by the detection circuit, and the first target state signal and the second target state signal can be provided by the state counting circuit, so as to realize the foregoing hammer refresh method.
  • An embodiment of the present disclosure provides a hammer refresh circuit, including a detection circuit for determining a hammer refresh trigger signal and a refresh execution signal; and when the hammer refresh trigger signal indicates that a hammer refresh for a target word line is received instruction and the refresh execution signal indicates that the hammer refresh instruction is not completed, output a preset hammer refresh signal in a valid state; wherein, the valid state of the preset hammer refresh signal indicates that it is within the first refresh cycle Executing the hammer refresh command, and the valid state of the preset hammer refresh signal will continue to the next period of the first refresh cycle if the hammer refresh command is not completed within the first refresh cycle A refresh cycle.
  • the preset hammer refresh signal can be provided by the detection circuit.
  • the valid state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh instruction can be completed within one refresh cycle; In some cases, the valid state of the preset hammer refresh signal will last until the next refresh cycle, so that the hammer refresh instruction can be completed in two refresh cycles, which can not only save bandwidth resources, but also improve the accuracy of the hammer refresh.
  • FIG. 15 shows a schematic structural diagram of a semiconductor memory 30 provided by an embodiment of the present disclosure.
  • the semiconductor memory 30 includes at least a hammer refresh circuit 20 .
  • the semiconductor memory 30 includes at least the hammer refresh circuit 20, it can output a preset hammer refresh signal.
  • the valid state of the preset hammer refresh signal lasts for one refresh cycle, and the hammer refresh can be completed within one refresh cycle. command; in the case of occasional errors, the valid state of the preset hammer refresh signal will continue to the next refresh cycle, so that the hammer refresh command can be completed in two refresh cycles, which can save bandwidth resources and improve hammer Refresh correctness.
  • An embodiment of the present disclosure provides a hammer refresh method, a hammer refresh circuit, and a semiconductor memory, which determine a hammer refresh instruction for a target word line; and set a preset hammer refresh signal to be valid according to the hammer refresh instruction. state; wherein, the valid state of the preset hammer refresh signal indicates that the hammer refresh instruction is executed in the first refresh cycle; if it is detected that the hammer refresh instruction is not completed within the first refresh cycle, Then, the valid state of the preset hammer refresh signal is extended to the next refresh period of the first refresh period.
  • the valid state of the preset hammer refresh signal lasts for one refresh cycle, so that the hammer refresh instruction is completed within one refresh cycle; in the case of occasional errors, the valid state of the preset hammer refresh signal It will continue until the next refresh cycle, so that the hammer refresh instruction can be completed in two refresh cycles, which can not only save bandwidth resources, but also improve the accuracy of the hammer refresh.

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Abstract

一种锤击刷新方法、锤击刷新电路及半导体存储器，该方法包括：确定针对目标字线的锤击刷新指令(S101)；根据锤击刷新指令，将预设锤击刷新信号置为有效状态；其中，预设锤击刷新信号的有效状态指示在第一刷新周期中执行锤击刷新指令(S102)；若检测到在第一刷新周期内未完成锤击刷新指令，则将预设锤击刷新信号的有效状态延续至第一刷新周期的下一刷新周期(S103)。

Description

一种锤击刷新方法、锤击刷新电路及半导体存储器
相关申请的交叉引用
本公开基于申请号为202111399125.2、申请日为2021年11月19日、发明名称为“一种锤击刷新方法、锤击刷新电路及半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种锤击刷新方法、锤击刷新电路及半导体存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成，且不同的存储单元需要经由字线和位线进行选中操作。也就是说，DRAM中存在大量字线，这些字线相邻排列，在某一字线受到锤式攻击(Row Hammer)时，与该字线相邻的字线可能会产生错误。在相关技术中，在检测到锤式攻击后会对受影响的字线进行刷新处理。然而，该刷新处理需要借助于两个刷新指令完成，占用了带宽资源，而且容易导致刷新错误。
发明内容
本公开提供了一种锤击刷新方法、锤击刷新电路及半导体存储器，能够减少锤击刷新过程所占用的带宽资源，而且提高刷新正确性。
第一方面，本公开实施例提供了一种锤击刷新方法，该方法包括：
确定针对目标字线的锤击刷新指令；
根据锤击刷新指令，将预设锤击刷新信号置为有效状态；其中，预设锤击刷新信号的有效状态指示在第一刷新周期中执行锤击刷新指令；
若检测到在第一刷新周期内未完成锤击刷新指令，则将预设锤击刷新信号的有效状态延续至第一刷新周期的下一刷新周期。
在一些实施例中，该方法还包括：若检测到完成锤击刷新指令时，将预设锤击刷新信号置为无效状态。
在一些实施例中，锤击刷新指令指示刷新目标字线的第一相邻字线和目标字线的第二相邻字线；
相应地，该方法还包括：在第一刷新周期中，判断第一相邻字线和第二相邻字线是否被全部刷新；若第一相邻字线被刷新且第二相邻字线未被刷新，则确定在第一刷新周期内未完成锤击刷新指令；或者若第一相邻字线和第二相邻字线全部被刷新，则确定在第一刷新周期内完成锤击刷新指令。
在一些实施例中，该方法还包括：确定第一目标状态信号和第二目标状态信号；其中，第一目标状态信号用于记录第一相邻字线的刷新状态，第二目标状态信号用于记 录第二相邻字线的刷新状态；在对第一相邻字线进行刷新时，将第一目标状态信号置为有效状态，并将第二目标状态信号置为无效状态；在对第二相邻字线进行刷新时，将第一目标状态信号置为无效状态，将第二目标状态信号置为有效状态。
在一些实施例中，在检测到在第一刷新周期内未完成锤击刷新指令情况下，该方法还包括：判断是否接收到字线激活指令；若判断结果为是，则将第一目标状态信号和第二目标状态信号均置为无效状态。
在一些实施例中，该方法还包括：判断预设锤击刷新信号是否处于有效状态；在预设锤击刷新信号处于有效状态的情况下，确定第一目标状态信号和第二目标状态信号；根据第一目标状态信号和第二目标状态信号，对目标字线的相邻字线进行字线刷新处理。
在一些实施例中，所述根据第一目标状态信号和第二目标状态信号，对目标字线的相邻字线进行字线刷新处理，包括：在第一目标状态信号和第二目标状态信号均处于无效状态的情况下，对第一相邻字线和第二相邻字线分别进行字线刷新处理；在第一目标状态信号处于有效状态且第二目标状态信号处于无效状态的情况下，对第二相邻字线进行两次字线刷新处理。
第二方面，本公开实施例提供了一种锤击刷新电路，包括：
检测电路，用于确定锤击刷新触发信号和刷新执行信号；以及
在锤击刷新触发信号指示接收到针对目标字线的锤击刷新指令且刷新执行信号指示锤击刷新指令未完成时，输出处于有效状态的预设锤击刷新信号；
其中，预设锤击刷新信号的有效状态指示在第一刷新周期内执行锤击刷新指令，且预设锤击刷新信号的有效状态在第一刷新周期内未完成锤击刷新指令的情况下将延续至第一刷新周期的下一刷新周期。
在一些实施例中，刷新执行信号包括初次刷新执行信号和刷新脉冲信号；
相应地，检测电路包括第一时钟电路、第一刷新状态确定电路和控制信号输出电路；其中，第一刷新状态确定电路，用于根据锤击刷新触发信号、第一时钟信号和第一反相时钟信号，确定第一刷新状态信号和第二刷新状态信号；第一时钟电路，用于根据第一刷新状态信号、初次刷新执行信号和刷新脉冲信号，确定第一时钟信号和第一反相时钟信号；控制信号输出电路，用于根据锤击刷新触发信号和第二刷新状态信号，确定预设锤击刷新信号；其中，锤击刷新指令指示对目标字线的第一相邻字线和目标字线的第二相邻字线进行字线刷新处理，初次刷新执行信号用于指示每一个刷新周期中第一次发生的字线刷新处理，刷新脉冲信号用于指示每一个刷新周期中每一次发生的字线刷新处理。
在一些实施例中，第一时钟电路包括第一二输入与非门、第二二输入与非门和第一非门；其中，第一二输入与非门的输入端分别与第一刷新状态信号和初次刷新执行信号连接；第二二输入与非门的输入端分别与第一二输入与非门的输出端和刷新脉冲信号连接，第二二输入与非门的输出端用于输出第一反相时钟信号；第一非门的输入端与第一反相时钟信号连接，第一非门的输出端用于输出第一时钟信号。
在一些实施例中，第一刷新状态确定电路包括第一二输入或非门、第三二输入与非门、第二非门、第一触发器和第二触发器；其中，第一二输入或非门的输入端分别与第一刷新状态信号和第二刷新状态信号连接，第三二输入与非门的输入端分别与第一二输入或非门的输出端和锤击刷新触发信号连接，第二非门的输入端分别与第三二输入与非门的输出端连接；第一触发器的输入端与第二非门的输出端连接，第一触发器的时钟端分别与第一时钟信号和第一反相时钟信号连接，第一触发器的输出端用于输出第一刷新状态信号；第二触发器的输入端与第一刷新状态信号连接，第二触发器的时钟端分别 与第一时钟信号和第一反相时钟信号连接，第二触发器的输出端用于输出第二刷新状态信号。
在一些实施例中，控制信号输出电路包括第三非门、第四二输入与非门和第四非门；其中，第三非门的输入端与第二刷新状态信号连接，第四二输入与非门的输入端分别与第三非门的输出端和锤击刷新触发信号连接；第四非门的输入端与第四二输入与非门的输出端连接，且第四非门的输出端用于输出预设锤击刷新信号。
在一些实施例中，锤击刷新电路还包括状态计数电路；状态计数电路，用于接收预设锤击刷新信号和字线状态信号，并根据预设锤击刷新信号和字线状态信号，确定第一目标状态信号和第二目标状态信号；其中，第一目标状态信号用于记录第一相邻字线的刷新状态，第二目标状态信号用于记录第二相邻字线的刷新状态。
在一些实施例中，字线状态信号包括刷新状态有效信号和字线开启脉冲信号；状态计数电路包括第二时钟电路、第二刷新状态确定电路和复位电路；其中，第二时钟电路，用于根据预设锤击刷新信号、刷新状态有效信号和字线开启脉冲信号，确定第二时钟信号和第二反相时钟信号的；复位电路，用于根据刷新状态有效信号、字线开启脉冲信号和第一目标状态信号，确定复位信号；第二刷新状态确定电路，用于根据第二时钟信号、第二反相时钟信号和复位信号，确定第一目标状态信号和第二目标状态信号；其中，刷新状态有效信号指示是否处于一个刷新周期中，字线开启脉冲信号指示任意字线的开启。
在一些实施例中，第二时钟电路包括第一三输入与非门和第五非门；其中，第一三输入与非门的输入端分别与预设锤击刷新信号、刷新状态有效信号和字线开启脉冲信号连接，第一三输入与非门的输出端用于输出第二反相时钟信号；第五非门的输入端与第一三输入与非门的输出端连接，第五非门的输出端用于输出第二时钟信号。
在一些实施例中，第二刷新状态确定电路包括第三触发器、第四触发器和第六非门；第三触发器的输入端通过第六非门与第三触发器的输出端连接，且第三触发器的输出端用于输出第一目标状态信号；第三触发器的时钟端分别与第二时钟信号和第二反相时钟信号连接；第四触发器的输入端与第一目标状态信号连接，第四触发器的时钟端分别与第二时钟信号和第二反相时钟信号连接，且第四触发器的输出端用于输出第二目标状态信号；第三触发器和第四触发器各自的复位端均与复位信号连接。
在一些实施例中，复位电路包括第七非门和第二三输入与非门；第七非门的输入端与刷新状态有效信号连接，第二三输入与非门的输入端分别与第七非门的输出端、字线开启脉冲信号和第一目标状态信号连接，第二三输入与非门的输出端用于输出复位信号。
第三方面，本公开实施例提供了一种半导体存储器，包括如第二方面所述的锤击刷新电路。
本公开实施例提供了一种锤击刷新方法、锤击刷新电路及半导体存储器，确定针对目标字线的锤击刷新指令；根据所述锤击刷新指令，将预设锤击刷新信号置为有效状态；其中，所述预设锤击刷新信号的有效状态指示在第一刷新周期中执行所述锤击刷新指令；若检测到在所述第一刷新周期内未完成所述锤击刷新指令，则将所述预设锤击刷新信号的有效状态延续至所述第一刷新周期的下一刷新周期。这样，在正常情况下，预设锤击刷新信号的有效状态持续一个刷新周期，从而通过一个刷新周期内完成锤击刷新指令；在出现偶发错误的情况下，预设锤击刷新信号的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，既能够节省带宽资源，而且能够提高锤击刷新的正确性。
附图说明
图1A为相关技术提供的一种锤击刷新的过程示意图；
图1B为相关技术提供的另一种锤击刷新的过程示意图；
图2为相关技术提供的又一种锤击刷新的过程示意图；
图3为本公开实施例提供的一种锤击刷新方法的流程示意图；
图4为本公开实施例提供的一种锤击刷新电路的结构示意图；
图5为本公开实施例提供的一种检测电路的结构示意图；
图6为本公开实施例提供的一种第一时钟电路的具体电路结构示意图；
图7为本公开实施例提供的一种第一刷新状态确定电路的具体电路结构示意图；
图8为本公开实施例提供的一种控制信号输出电路的具体电路结构示意图；
图9为本公开实施例提供的一种检测电路的信号时序示意图；
图10为本公开实施例提供的另一种锤击刷新电路的结构示意图；
图11为本公开实施例提供的一种状态计数电路的结构示意图；
图12为本公开实施例提供的一种第二时钟电路的具体电路结构示意图；
图13为本公开实施例提供的一种第二刷新状态确定电路的具体电路结构示意图；
图14为本公开实施例提供的一种复位电路的具体电路结构示意图；
图15为本公开实施例提供的一种半导体存储器的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
以下对本公开实施例中涉及到的英文词汇及其缩写进行说明。
Row Hammer：锤式攻击，或称为行锤击
Dynamic Random Access Memory，DRAM：动态随机存取存储器；
Synchronous Dynamic Random Access Memory，SDRAM：同步动态随机存储器；
Memory Array：存储阵列
Word Line，WL：字线
Bit Line，BL：位线
RHR：预设锤击刷新信号
RHRact1：第一目标状态信号
RHRact2：第二目标状态信号
RHRStart：锤击刷新触发信号
Refreshpulse1：初次刷新执行信号
RefPulseCounter：刷新脉冲信号
RHRCk：第一时钟信号
RHRCkN：第一反相时钟信号
RHRState1：第一刷新状态信号
RHRState2：第二刷新状态信号
Rfsh：刷新状态有效信号
RasEnpulse：字线开启脉冲信号
RHRCounter：第二时钟信号
RHRCounterN：第二反相时钟信号
ResetN：复位信号。
应理解，动态随机存取存储器是计算机中常用的半导体存储器件，由许多重复的存储单元组成Memory Array，且不同的存储单元需要经由字线和位线进行选中操作。
目前，由于存储单元越来越密集，字线之间的距离越来越小，导致相邻字线之间的电容耦合增大。此时，如果重复激活字线(也称为目标行)，有可能导致两个相邻字线(也称为受害行)受到电磁干扰，从而受害行上的存储单元发生电荷丢失现象，最终这些存储单元可能在受害行的下一次刷新之前丢失数据。以上情况被称为Row Hammer。
也就是说，当一根字线受到Row Hammer攻击，与这根字线相邻的两根字线会受到很大的干扰。因此，为了消除锤式攻击的影响，在检测到目标行在经受锤式攻击时，需要对目标行两侧的受害行进行刷新，称为锤击刷新(Row Hammer Refresh)。
为方便说明，将这两根WL(即受害行)的地址对应称为Ra和Rb，对这两个地址的刷新操作称为RHRa和RHRb。参见图1A，其示出了相关技术提供的一种锤击刷新的过程示意图。参见图1B，其示出了相关技术提供的另一种锤击刷新的过程示意图。在图1A和图1B中，ActCmd是指字线激活命令，PreCmd是指字线预充命令(Pre)，REFCmdA是指第一个刷新命令，REFCmdB是指第二个刷新命令。另外，完成一个刷新命令所需要的时间也称为一个刷新周期。
在一种相关技术中，如图1A所示，相邻字线的刷新需要涉及到两个刷新命令，这不仅占用了带宽资源，还容易导致一些错误。在另一种相关技术中，如图1B所示，相邻字线的刷新在一个刷新命令中完成，但是这种方法某些偶发的情况下也有可能导致RHR的错误。
以一个刷新命令完成锤击刷新过程为例，对可能出现的偶发错误进行说明。参见图2，其示出了相关技术提供的又一种锤击刷新方法的过程示意图。如图2所示，在接收到锤击刷新指令后，RHR信号为有效状态，以指示Memory Array在刷新命令(REFCmd1等)中进行锤击刷新。在这里，刷新命令对应两次脉冲，即1 st Pulse和2 nd Pulse，从而经由这两次脉冲分别执行RHRa和RHRb，以便在一个刷新命令中完成锤击刷新。然而，如果某些非法的操作导致刷新命令REFCmd1的第二次脉冲(2 nd Pulse)出现了缺失，则会出现RHRa和RHRb分开在两个Refresh命令中执行的情况，进而导致RHRa和RHRb之间可能出现字线激活(Active)、字线预充(Precharge)等操作，即在锤击刷新还没有完成的情况下又发生了字线激活或字线预充等操作，这种情况是需要避免的。
基于此，本公开实施例提供了一种锤击刷新方法，确定针对目标字线的锤击刷新指令；根据所述锤击刷新指令，将预设锤击刷新信号置为有效状态；其中，所述预设锤击刷新信号的有效状态指示在第一刷新周期中执行所述锤击刷新指令；若检测到在所述第 一刷新周期内未完成所述锤击刷新指令，则将所述预设锤击刷新信号的有效状态延续至所述第一刷新周期的下一刷新周期。这样，在正常情况下，预设锤击刷新信号的有效状态持续一个刷新周期，从而通过一个刷新周期内完成锤击刷新指令；在出现偶发错误的情况下，预设锤击刷新信号的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，既能够节省带宽资源，而且能够提高锤击刷新的正确性。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图3，其示出了本公开实施例提供的一种锤击刷新方法的流程示意图。如图3所示，该方法可以包括：
S101：确定针对目标字线的锤击刷新指令。
需要说明的是，本公开实施例提供的锤击刷新方法应用于半导体存储器件，例如DRAM、SDRAM等，能够更好地对遭受Row Hammer攻击的字线进行刷新。
在这里，目标字线是指Row Hammer攻击中的目标行，第一相邻字线和第二相邻字线是指Row Hammer攻击中的受害行。
对半导体存储器件来说，在检测到针对目标字线的Row Hammer攻击后，生成一针对目标字线的锤击刷新指令，以指示对第一相邻字线进行刷新和对第二相邻字线进行刷新，避免第一相邻字线和第二相邻字线发生数据丢失的问题。
在这里，判定Row Hammer攻击的方式可参照相关技术，本公开实施例不做赘述。
S102：根据锤击刷新指令，将预设锤击刷新信号置为有效状态；其中，预设锤击刷新信号的有效状态指示在第一刷新周期中执行锤击刷新指令。
需要说明的是，在半导体存储器件中，设置一专门用于指示存储阵列(Memory Array)进行锤击刷新操作的预设锤击刷新信号。换句话说，若预设锤击刷新信号有效，则Memory Array需要针对指定的字线进行锤击刷新，若预设锤击刷新信号无效，则Memory Array不需要进行锤击刷新。
根据锤击刷新指令，将预设锤击刷新信号置为有效，以便在第一刷新周期中执行刷新指令。在这里，刷新周期可以理解为用于执行刷新操作的时间周期，具体是指接收到刷新命令之后且未接收到下一操作指令之前的时间，即一个刷新周期与一个刷新命令相对应。第一刷新周期可以是指预设锤击刷新信号处于有效状态之后最近的刷新周期。
S103：若检测到在第一刷新周期内未完成锤击刷新指令，则将预设锤击刷新信号的有效状态延续至第一刷新周期的下一刷新周期。
需要说明的是，在正常情况下，第一刷新周期能够对第一相邻字线和第二相邻字线进行刷新，一完成锤击刷新指令。但是如果出现偶发错误，第一刷新周期可能无法完成锤击刷新指令，需要将预设锤击刷新信号的有效状态延续至第一刷新周期的下一刷新周期，从而在两个刷新周期内完成锤击刷新指令。
应理解，在半导体存储器件中，不仅存在刷新周期，还会存在其他操作周期，所以第一刷新周期和下一刷新周期并不是时间上连续的。
在一些实施例中，若检测到完成锤击刷新指令时，将预设锤击刷新信号置为无效状态。
需要说明的是，如果第一刷新周期就完成锤击刷新指令，则在第一刷新周期结束之后就将预设锤击刷新信号置为无效状态，此时通过一个刷新命令就完成锤击刷新过程；反之，如果第一刷新周期并没有完成锤击刷新指令，则预设锤击刷新信号的有效状态仍将持续至第一刷新周期的下一刷新周期，从而下一刷新周期继续执行锤击刷新过程，此时通过两个刷新命令完成锤击刷新过程。
也就是说，在一种相关技术中，预设锤击刷新信号的有效状态会固定持续两个刷新周期，从而在两个刷新命令中完成一个锤击刷新指令，但是这样占用的带宽较大，浪费 资源；在另一种相关技术中，预设锤击刷新信号的有效状态会固定持续一个刷新周期，从而在一个刷新命令中完成一个锤击刷新指令，但是可能由于偶发错误导致刷新失败。
在本公开实施例中，提供了一个能够进行自动纠错的锤击刷新方法，在正常情况下，预设锤击刷新信号的有效状态持续一个刷新周期，从而通过一个刷新周期内完成锤击刷新指令；在出现偶发错误的情况下，预设锤击刷新信号的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，不仅能够节省带宽资源，而且能够提高锤击刷新的正确性。
还需要说明的是锤击刷新指令指示刷新目标字线的第一相邻字线和目标字线的第二相邻字线。
相应地，在一些实施例中，该方法还可以包括：
在第一刷新周期中，判断第一相邻字线和第二相邻字线是否被全部刷新；
若第一相邻字线被刷新且第二相邻字线未被刷新，则确定在第一刷新周期内未完成锤击刷新指令；或者
若第一相邻字线和第二相邻字线全部被刷新，则确定在第一刷新周期内完成锤击刷新指令。
也就是说，锤击刷新指令包括对目标字线两侧的第一相邻字线和第二相邻字线分别进行刷新。因此，通过第一相邻字线和第二相邻字线的刷新状态，判断第一刷新周期内是否完成该锤击刷新指令。
在一些实施例中，设置第一目标状态信号和第二目标状态信号，分别应用于记录第一相邻字线和第二相邻字线的状态。该方法还可以包括：
确定第一目标状态信号和第二目标状态信号；其中，第一目标状态信号用于记录第一相邻字线的刷新状态，第二目标状态信号用于记录第二相邻字线的刷新状态；
在对第一相邻字线进行刷新时，将第一目标状态信号置为有效状态，并将第二目标状态信号置为无效状态；
在对第二相邻字线进行刷新时，将第一目标状态信号置为无效状态，将第二目标状态信号置为有效状态。
需要说明的是，应理解，第一目标状态信号和第二目标状态信号的初始状态均为无效。在接到锤击刷新指令后，对第一相邻字线进行刷新，此时第一目标状态信号跳转为有效，第二目标状态信号依然为无效；最后，对第二相邻字线进行刷新，第一目标状态信号重新跳转为无效，第二目标状态信号跳转为有效，锤击刷新指令完成。
另外，在锤击刷新指令完成后，第一目标状态信号和第二目标状态信号会再次复位为无效状态，其具体复位过程可采用多种原理的电路进行实现，本公开实施例不作展开描述。
除了上述情况，第一相邻字线和第二相邻字线的刷新操作之间还可能插入了字线激活操作。也就是说，第一刷新周期只完成了第一相邻字线的刷新，而且第一刷新周期结束后接收到了字线激活指令，从而进入了激活操作周期，后续又再次进入下一刷新周期，并在下一刷新周期内完成了对第二相邻字线的操作。这种情况很容易导致处理错误，本公开实施例针对这种情况单独记录以便后续处理。示例性地，这种情况下，第一目标状态信号和第二目标状态信号会共同被置为无效。
因此，在一些实施例中，在检测到在第一刷新周期内未完成锤击刷新指令情况下，该方法还可以包括：
判断是否接收到字线激活指令；
若判断结果为是，则将第一目标状态信号和第二目标状态信号均置为无效状态。
这样，某一刷新周期开始时，若第一目标状态信号和第二目标状态信号无效，则存在两种可能：上一锤击刷新指令正常完成，上一锤击刷新指令未完成且接收到字线激活指令。应理解，以上两种可能后续可进行同样的处理，所以不再进行细分。某一刷新周期开始时，若第一目标状态信号有效，第二目标状态信号无效，则上一锤击刷新指令未完成且未接收到字线激活指令。
这样，通过第一目标状态信号和第二目标状态信号能够区分中偶发错误时是否中间插入了字线激活指令，以便后续进行针对性处理。
还需要说明的是，字线激活指令可以是对Memory Array中任一字线的激活指令，并不局限于目标字线、第一相邻字线和第二相邻字线。
在一些实施例中，该方法还可以包括：
在预设锤击刷新信号处于有效状态的情况下，确定第一目标状态信号和第二目标状态信号；
根据第一目标状态信号和第二目标状态信号，对目标字线的相邻字线进行字线刷新处理。
需要说明的是，在预设锤击刷新信号有效时，需要根据第一目标状态信号和第二目标状态信号确定进行刷新处理的具体步骤。
具体地，所述根据第一目标状态信号和第二目标状态信号，对目标字线的相邻字线进行字线刷新处理，可以包括：
在第一目标状态信号和第二目标状态信号均处于无效状态的情况下，对第一相邻字线和第二相邻字线分别进行字线刷新处理；
在第一目标状态信号处于有效状态且第二目标状态信号处于无效状态的情况下，对第二相邻字线进行两次字线刷新处理。
需要说明的是，在出现偶发错误的情况下，在下一刷新周期开始时，若第一目标状态信号和第二目标状态信号均无效，则对第一相邻字线和第二相邻字线分别刷新，以避免第一相邻字线和第二相邻字线的刷新过程中被插入字线激活操作；若第一目标状态信号有效且第二目标状态信号无效，则对第二相邻字线进行两次刷新。
换句话说，针对某一刷新周期，至少存在以下两种情况：
情况一：在某一刷新周期开始时，预设锤击刷新信号处于有效状态，且第一目标状态信号和第二目标状态信号均无效，该种情况存在两种可能：(1)本刷新周期接收到锤击刷新指令；(2)上一刷新周期接收到锤击刷新指令，但是上一刷新周期由于偶发错误未能完成锤击刷新指令，且上一刷新周期与本刷新周期之间出现了字线激活指令。针对以上两种可能，均需要在本刷新周期执行对第一相邻字线的刷新和第二相邻字线的刷新。
情况二：在某一刷新周期开始时，预设锤击刷新信号处于有效状态，且第一目标状态信号有效，第二目标状态信号无效，说明本刷新周期的上一刷新周期接收到锤击刷新指令，但是由于偶发错误上一刷新周期仅执行了对第一相邻字线的刷新，且在上一刷新周期和本刷新周期之间未接收到字线激活指令。此时，可以直接重复对第二相邻字线进行字线刷新处理，完成上一刷新周期未完成的锤击刷新指令。
在这里，对于情况二，并不选择对两个字线分别进行一次刷新的原因包括：对某一字线进行两次刷新仅需要开启一个字线，流程简单、功耗低；电路设计的复杂性降低，该部分请参见后续关于锤击刷新电路的说明。
当然，在另一些实施例中，情况二也可以采用对第一相邻字线和第二相邻字线分别刷新的方式。
另外，在本公开实施例中，有效状态和无效状态的定义可以根据实际应用场景选择。例如，某一信号的有效状态可以是指该信号处于高电平状态，某一信号的有效状态可以是指该信号处于低电平状态；或者某一信号的有效状态可以是指该信号处于低电平状态，某一信号的有效状态可以是指该信号处于高电平状态。
综上所述，本公开实施例提供了一种锤击刷新方法，具有自动纠错的功能。锤击刷新方法借助于预设锤击刷新信号、第一目标状态信号和第二目标状态信号完成。这样，一方面，在正常情况下，预设锤击刷新信号的有效状态持续一个刷新周期，能够通过一个刷新周期内完成锤击刷新指令；在出现偶发错误的情况下，预设锤击刷新信号的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，不仅能够节省带宽资源，而且能够保证锤击刷新的顺利完成；另一方面，第一目标状态信号和第二目标状态信号用于记录第一相邻字线和第二相邻字线的刷新状态，以及在第一相邻字线刷新后且第二相邻字线刷新前是否接收到字线激活指令，以便后续针对性的进行处理，避免第一相邻字线和第二相邻字线的刷新之间插入字线激活指令，提高锤击刷新的正确性。
本公开实施例提供了一种锤击刷新方法，确定针对目标字线的锤击刷新指令；根据锤击刷新指令，将预设锤击刷新信号置为有效状态；其中，预设锤击刷新信号的有效状态指示在第一刷新周期中执行锤击刷新指令；若检测到在第一刷新周期内未完成锤击刷新指令，则将预设锤击刷新信号的有效状态延续至第一刷新周期的下一刷新周期。这样，在正常情况下，预设锤击刷新信号的有效状态持续一个刷新周期，能够通过一个刷新周期内完成锤击刷新指令；在出现偶发错误的情况下，预设锤击刷新信号的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，既能够节省带宽资源，而且能够提高锤击刷新的正确性。
在本公开的另一实施例中，参见图4，其示出了本公开实施例提供的一种锤击刷新电路20的结构示意图。如图4所示，锤击刷新电路20包括检测电路21，用于确定锤击刷新触发信号RHRStart和刷新执行信号；以及
在锤击刷新触发信号RHRStart指示接收到针对目标字线的锤击刷新指令且刷新执行信号指示锤击刷新指令未完成时，输出处于有效状态的预设锤击刷新信号RHR。
需要说明的是，本公开实施例提供的锤击刷新电路20应用于半导体存储器件，例如DRAM、SDRAM等，能够更好地对遭受Row Hammer攻击的字线进行刷新。
在本公开实施例中，锤击刷新电路20包括检测电路21，检测电路21的输入端为锤击刷新触发信号RHRStart和刷新执行信号，其输出端为预设锤击刷新信号RHR。其中，锤击刷新触发信号RHR的不同状态能够指示是否接收到针对目标字线的锤击刷新指令；刷新执行信号的不同状态能够指示锤击刷新指令是否完成。
在这里，预设锤击刷新信号RHR的有效状态指示在第一刷新周期内执行锤击刷新指令，且预设锤击刷新信号RHR的有效状态在第一刷新周期内未完成锤击刷新指令的情况下将延续至第一刷新周期的下一刷新周期。
也就是说，在接收到针对目标字线的锤击刷新指令且该锤击刷新指令没有执行完成的情况下，检测电路21会持续输出处于有效状态的预设锤击刷新信号RHR，以指示存储阵列执行相关的锤击刷新处理；除此之外，在没有接收到针对目标字线的锤击刷新指令时，或者锤击刷新指令已完成时，检测电路21会续输出处于无效状态的预设锤击刷新信号RHR。这样，在正常情况下，预设锤击刷新信号的有效状态持续一个刷新周期，能够通过一个刷新周期内完成锤击刷新指令；在出现偶发错误的情况下，预设锤击刷新信号的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，既能够节省带宽资源，而且能够提高锤击刷新的正确性。
在这里，锤击刷新指令指示对目标字线的第一相邻字线和目标字线的第二相邻字线进行字线刷新处理，即一个锤击刷新指令包括两次字线刷新处理。
在一些实施例中，刷新执行信号包括初次刷新执行信号Refreshpulse1和刷新脉冲信号RefPulseCounter。初次刷新执行信号Refreshpulse1用于指示每一个刷新周期中第一次发生的字线刷新处理，刷新脉冲信号RefPulseCounter用于指示每一个刷新周期中每一次发生的字线刷新处理。
相应地，参见图5，其示出了本公开实施例提供的一种检测电路21的结构示意图。如图5所示，检测电路21包括第一时钟电路211、第一刷新状态确定电路212和控制信号输出电路213；其中，
第一刷新状态确定电路212，用于根据锤击刷新触发信号RHRStart、第一时钟信号RHRCk和第一反相时钟信号RHRCkN，确定第一刷新状态信号RHRState1和第二刷新状态信号RHRState2；
第一时钟电路211，用于根据第一刷新状态信号RHRState1、初次刷新执行信号Refreshpulse1和刷新脉冲信号RefPulseCounter，确定第一时钟信号RHRCk和第一反相时钟信号RHRCkN；
控制信号输出电路213，用于根据锤击刷新触发信号RHRStart和第二刷新状态信号RHRState2，确定预设锤击刷新信号RHR。
需要说明的是，检测电路21至少包括以下三部分：第一时钟电路211、第一刷新状态确定电路212和控制信号输出电路213。其中，
(1)第一时钟电路211，主要用于输出第一时钟信号RHRCk和第一反相时钟信号RHRCkN，从而为后续的第一刷新状态确定电路212提供必要的信号支持。
示例性地，参见图6，其示出了本公开实施例提供的一种第一时钟电路211的具体电路结构示意图。如图6所示，第一时钟电路包括第一二输入与非门2111、第二二输入与非门2112和第一非门2113；其中，
第一二输入与非门的2111输入端分别与第一刷新状态信号RHRState1和初次刷新执行信号Refreshpulse1连接；第二二输入与非门2112的输入端分别与第一二输入与非门2111的输出端和刷新脉冲信号RefPulseCounter连接，第二二输入与非门2112的输出端用于输出第一反相时钟信号RHRCkN；第一非门2113的输入端与第一反相时钟信号RHRCkN连接，第一非门2113的输出端用于输出第一时钟信号RHRCk。
(2)第一刷新状态确定电路212，主要用于输出第一刷新状态信号RHRState1和第二刷新状态信号RHRState2，以记录第一相邻字线和第二相邻字线的刷新状态，为后续的控制信号输出电路213提供必要的信号支持。
示例性地，参见图7，其示出了本公开实施例提供的一种第一刷新状态确定电路212的具体电路结构示意图。如图7所示，第一刷新状态确定电路212包括第一二输入或非门2121、第三二输入与非门2122、第二非门2123、第一触发器2124和第二触发器2125；其中，
第一二输入或非门2121的输入端分别与第一刷新状态信号RHRState1和第二刷新状态信号RHRState2连接，第三二输入与非门2122的输入端分别与第一二输入或非门2121的输出端和锤击刷新触发信号RHRStart连接，第二非门2123的输入端分别与第三二输入与非门2122的输出端连接；第一触发器2124的输入端与第二非门2123的输出端连接，第一触发器2124的时钟端分别与第一时钟信号RHRCk和第一反相时钟信号RHRCkN连接，第一触发器2124的输出端用于输出第一刷新状态信号RHRState1；第二触发器2125的输入端与第一刷新状态信号RHRState1连接，第二触发器2125的时钟 端分别与第一时钟信号RHRCk和第一反相时钟信号RHRCkN连接，第二触发器2125的输出端用于输出第二刷新状态信号RHRState2。
另外，第一触发器2124和第二触发器2125各自的复位端与一信号RST连接，用于第一刷新状态信号和第二刷新状态信号的复位。
(3)控制信号输出电路213，主要用于预设锤击刷新信号RHR。
示例性地，参见图8，其示出了本公开实施例提供的一种控制信号输出电路213的具体电路结构示意图。如图8所示，控制信号输出电路213包括第三非门2131、第四二输入与非门2132和第四非门2133；其中，
第三非门2131的输入端与第二刷新状态信号RHRState2连接，第四二输入与非门2132的输入端分别与第三非门2131的输出端和锤击刷新触发信号RHRStart连接；第四非门2133的输入端与第四二输入与非门2132的输出端连接，且第四非门2133的输出端用于输出预设锤击刷新信号RHR。
从以上来看，借助于第一刷新状态确定电路212、第一时钟电路211和控制信号输出电路213，能够根据刷新执行信号Refreshpulse1、刷新脉冲信号RefPulseCounter和锤击刷新触发信号RHRStart，确定出第一刷新状态信号RHRState1和第二刷新状态信号RHRState2，最终输出预设锤击刷新信号RHR。
在一种具体地实施例中，对于以上电路，初次刷新执行信号Refreshpulse1在刷新周期中的第一次脉冲(该脉冲用于开启字线)时处于有效状态，在其他时候处于无效状态；刷新脉冲信号RefPulseCounter在刷新周期中的每一次脉冲时都会产生一个方波，
RHRStart在接收到锤击刷新指令后产生上升沿，在锤击刷新指令结束后产生下降沿，其他信号的变化方式可经由具体的电路元件推知。
示例性地，以下提供一种具体场景，以便说明第一时钟电路211、第一刷新状态确定电路212和控制信号输出电路213的信号处理逻辑。
场景说明：对于锤击刷新指令，第一刷新周期(即REFCmd1对应的刷新周期)内第一次脉冲(1 st pulse)正常执行，但是第二次脉冲(2 nd pulse)由于偶发错误缺失，导致第一刷新周期仅执行了RHRa，需要在下一刷新周期再次执行一次RHRa和RHRb。
信号处理逻辑：参见图9，其示出了本公开实施例提供的一种检测电路21的信号时序示意图。如图9所示，
首先，在接收到锤击刷新指令后，RHRStart变化为高电平(即有效状态)，RHR随之变化为高电平，以指示对第一相邻字线和第二相邻字线进行刷新处理；
其次，在第一刷新周期的1 st Pulse时，对第一相邻字线进行字线刷新处理，即RHRa。另外，在1 st Pulse期间，Refreshpulse1为高电平，且RefPulseCounter在每个Pulse的地址被锁存后产生一个方波，从而导致第一时钟电路输出的RHRCkN(图中未示出)和RHRCk发生状态变化，且RHRCkN和RHRCk经过第一刷新状态电路处理后导致RHRState1状态发生变化。具体地，RHRState1在RHRa的过程中由低电平变化为高电平，以记录完成对第一相邻字线的刷新；
又次，由于第一刷新周期的2 nd Pulse缺失，所以RefPulseCounte不会再次产生方波，所以RHRState1和RHRState2均没有发生变化，RHRStart和RHR的有效状态将持续至下一刷新周期(即接收到REFCmd2命令后且未接收到新命令前)。
再次，在下一刷新周期的1 st Pulse和2 nd Pulse分别执行一次RHRa和RHRb。此时，Refreshpulse1仅在1 st Pulse期间处于高电平状态，RefPulseCounter针对每个Pulse均产生一次方波，从而RHRCkN、RHRCk均随之变化，此时RHRState1将在RefPulseCounter第二次方波的下降沿由高电平变化为低电平，反之，RHRState2将在RefPulseCounter第二次方波的下降沿由低电平变化为高电平，以指示完成对第二相邻字线的刷新。
最后，由于RHRStart仍保持高电平，RHRState2的由低电平变为高电平，所以RHR信号由高电平变化为低电平，而RHRStart将与2 nd Pulse的下降沿一起由高电平变化为低电平。
这样，在出现偶发错误的情况下，预设锤击刷新信号RHR的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，既能够节省带宽资源，而且能够提高锤击刷新的正确性。
应理解，对于锤击刷新指令，对第一相邻字线和第二相邻字线的刷新操作之间需要避免字线激活指令。也就是说，如果对第一相邻字线进行刷新后且在对第二相邻字线进行刷新前接收到了字线激活指令，那么需要记录下来后续进行处理。
因此，在一些实施例中，参见图10，其示出了本公开实施例提供的另一种锤击刷新电路20的结构示意图。如图10所示，锤击刷新电路20还包括状态计数电路22；
状态计数电路22，用于接收预设锤击刷新信号RHR和字线状态信号，并根据预设锤击刷新信号RHR和字线状态信号，确定第一目标状态信号RHRAct1和第二目标状态信号RHRAct2；
需要说明的是，状态计数电路22用于输出第一目标状态信号RHRAct1和第二目标状态信号RHRAct2，从而记录当前的锤击刷新进程。具体地，第一目标状态信号RHRAct1用于记录第一相邻字线的刷新状态，第二目标状态信号RHRAct2用于记录第二相邻字线的刷新状态。
在一些实施例中，字线状态信号包括刷新状态有效信号Rfsh和字线开启脉冲信号RasEnpulse，刷新状态有效信号Rfsh指示是否处于一个刷新周期中，字线开启脉冲信号RasEnpulse指示任意字线的开启。
也就是说，如果当前时间Memory Array正处于一个刷新周期中，则刷新状态有效信号Rfsh处于有效状态，如果当前时间存储阵列处于激活、预充、待机等其他操作周期中，则刷新状态有效信号Rfsh处于无效状态。另外，在任意字线的开启期间字线开启脉冲信号RasEnpulse产生一个方波。
相应地，参见图11，其示出了本公开实施例提供的一种状态计数电路22的结构示意图。如图11所示，状态计数电路22包括第二时钟电路221、第二刷新状态确定电路222和复位电路223；其中，
第二时钟电路221，用于根据预设锤击刷新信号RHR、刷新状态有效信号Rfsh和字线开启脉冲信号RasEnpulse，确定第二时钟信号RHRCounter和第二反相时钟信号的RHRCounterN；
复位电路223，用于根据刷新状态有效信号Rfsh、字线开启脉冲信号RasEnpulse和第一目标状态信号RHRAct1，确定复位信号ResetN；
第二刷新状态确定电路222，用于根据第二时钟信号RHRCounter、第二反相时钟信号RHRCounterN和复位信号ResetN，确定第一目标状态信号RHRAct1和第二目标状态信号RHRAct2；
需要说明的是，状态计数电路22至少包括以下三部分：第二时钟电路221、第二刷新状态确定电路222和复位电路223。其中，
(1)第二时钟电路221，主要用于输出第二时钟信号RHRCounter和第二反相时钟信号RHRCounterN，从而为后续的第二刷新状态确定电路222提供必要的信号支持。
示例性地，参见图12，其示出了本公开实施例提供的一种第二时钟电路221的具体电路结构示意图。如图12所示，第二时钟电路221包括第一三输入与非门2211和第五非门2212；其中，
第一三输入与非门2211的输入端分别与预设锤击刷新信号RHR、刷新状态有效信号Rfsh和字线开启脉冲信号RasEnpulse连接，第一三输入与非门2211的输出端用于输出第二反相时钟信号RHRCounterN；第五非门2212的输入端与第一三输入与非门2211的输出端连接，第五非门2212的输出端用于输出第二时钟信号RHRCounter。
(2)第二刷新状态确定电路222，主要用于输出第一目标状态信号RHRAct1和第二刷新状态信号RHRAct2，以记录第一相邻字线和第二相邻字线的刷新状态。
示例性地，参见图13，其示出了本公开实施例提供的一种第二刷新状态确定电路222的具体电路结构示意图。如图13所示，第二刷新状态确定电路222包括第三触发器2221、第四触发器2222和第六非门2223；
第三触发器2221的输入端通过第六非门2223与第三触发器2221的输出端连接，且第三触发器2221的输出端用于输出第一目标状态信号RHRAct1；第三触发器2221的时钟端分别与第二时钟信号RHRCounter和第二反相时钟信号RHRCounterN连接；第四触发器2222的输入端与第一目标状态信号RHRAct1连接，第四触发器2222的时钟端分别与第二时钟信号RHRCounter和第二反相时钟信号RHRCounterN连接，且第四触发器2222的输出端用于输出第二目标状态信号RHRAct2；第三触发器2221和第四触发器2222各自的复位端均与复位信号ResetN连接。
(3)复位电路223，主要用于输出复位信号ResetN，为第二刷新状态确定电路222提供必要的信号支持。
示例性地，参见图14，其示出了本公开实施例提供的复位电路223的具体电路结构示意图。如图14所示，复位电路223包括第七非门2231和第二三输入与非门2232；
第七非门2231的输入端与刷新状态有效信号Rfsh连接，第二三输入与非门2232的输入端分别与第七非门2231的输出端、字线开启脉冲信号RasEnpulse和第一目标状态信号RHRAct1连接，第二三输入与非门2232的输出端用于输出复位信号ResetN。
特别地，在本公开实施例中，复位信号ResetN为低电平有效，即复位信号ResetN处于低电平时，第三触发器2221和第四触发器2222复位。
应理解，第一目标状态信号RHRAct1和第二目标状态信号RHRAct2的初始状态均为无效状态。对于第一目标状态信号RHRAct1和第二目标状态信号RHRAct2，其变化逻辑为：
在正常情况下，为了完成锤击刷新指令，需要在第一刷新周期内依次完成对第一相邻字线和第二相邻字线的刷新。此时，在开启第一字线时，第一目标状态信号RHRAct1变化为有效，第二目标状态信号RHRAct2仍为无效；在开启第二字线时，第一目标状态信号RHRAct1变化为无效，第二目标状态信号RHRAct2变化为有效；
在出现偶发错误的情况下，在第一刷新周期内仅完成对第一相邻字线的刷新。具体地，在开启第一字线时，第一目标状态信号RHRAct1变化为有效状态，第二目标状态信号RHRAct2仍为无效状态。然后，存在两种可能：(1)第一刷新周期和下一刷新周期之间未接收到字线激活指令，即第一刷新周期和下一刷新周期之间不存在字线开启，此时在下一刷新周期开始时，第一目标状态信号RHRAct1仍保持为有效，第二目标状态信号RHRAct2保持无效；(2)第一刷新周期和下一刷新周期之间接收到字线激活指令，在第一刷新周期和下一刷新周期之间存在字线开启，此时复位信号ResetN会呈现有效，此时第一目标状态信号RHRAct1和第二目标状态信号RHRAct2均被置为无效。
另外，在完成锤击刷新指令后，第一目标状态信号RHRAct1和第二目标状态信号RHRAct2均被复位为无效状态，其具体复位过程可采用多种原理的电路进行实现，本公开实施例不作展开描述。
这样，通过第一目标状态信号RHRAct1和第二目标状态信号RHRAct2，可以准确记录第一相邻字线和第二相邻字线的刷新状态，后续可以针对性进行刷新处理，避免第一相邻字线的刷新和第二相邻字线的刷新之间插入字线激活指令，从而导致错误的问题。
基于前述的锤击刷新电路，能够确定预设锤击刷新信号RHR、第一目标状态信号RHRAct1和第二目标状态信号RHRAct2，进而根据这些信号确定具体的锤击刷新处理过程，至少包括以下两种情况：
情况一：在某一刷新周期开始时，预设锤击刷新信号处于有效状态，且第一目标状态信号无效，第二目标状态信号无效，该种情况存在两种可能：(1)本刷新周期接收到锤击刷新指令；(2)上一刷新周期接收到锤击刷新指令，但是上一刷新周期由于偶发错误未能完成锤击刷新指令，且上一刷新周期与本刷新周期之间出现了字线激活指令。针对以上两种可能，均需要在本刷新周期执行对第一相邻字线的刷新和第二相邻字线的刷新。
情况二：在某一刷新周期开始时，预设锤击刷新信号处于有效状态，且第一目标状态信号有效，第二目标状态信号无效，说明本刷新周期的上一刷新周期接收到锤击刷新指令，但是由于偶发错误上一刷新周期仅执行了对第一相邻字线的刷新，且在上一刷新周期和本刷新周期之间未接收到字线激活指令。此时，可以直接重复对第二相邻字线进行字线刷新处理，完成上一刷新周期未完成的锤击刷新指令。
也就是说，基于本公开实施例提供的锤击刷新电路，能够提供一种带自动纠错的在一个Refresh命令(相当于一个刷新周期)中完成Row Hammer刷新的方法：
(1)如果出现第一个Refresh命令中的RHRb缺失的情况，就把表征Row Hammer Refresh的信号RHR延续到下一个Refresh命令；
(2)当两次Refresh命令之间出现Active命令，则重置RHR状态计数器(第一触发器和第二触发器)；具体地，如果出现第一个Refresh命令中的RHRb缺失的情况，且两次Refresh命令之间出现Active命令，这时RHRAct1＝1，Rfsh＝0，同时存储阵列在执行Active命令时需要开启WL Pulse，从而触发RasEnPulse，进而改变ResetN的状态，重置RHR状态计数器；
(3)在第二个Refresh命令中完成RHRa和RHRb。
另外，在出现第一个Refresh命令中的RHRb缺失，且两次Refresh命令之间没有出现Active命令，那么在在第二个Refresh命令中做两次RHRb。
另外，图6～8、图11～图13仅仅为相应电路的一种可能结构，本领域技术人员可根据不同电路的实际应用场景增删以及修改相应的电路元件。
这样，通过检测电路能够提供预设锤击刷新信号，通过状态计数电路能够提供第一目标状态信号和第二目标状态信号，以实现前述的锤击刷新方法。
本公开实施例提供了一种锤击刷新电路，包括检测电路，用于确定锤击刷新触发信号和刷新执行信号；以及在所述锤击刷新触发信号指示接收到针对目标字线的锤击刷新指令且所述刷新执行信号指示所述锤击刷新指令未完成时，输出处于有效状态的预设锤击刷新信号；其中，所述预设锤击刷新信号的有效状态指示在第一刷新周期内执行所述锤击刷新指令，且所述预设锤击刷新信号的有效状态在所述第一刷新周期内未完成所述锤击刷新指令的情况下将延续至所述第一刷新周期的下一刷新周期。这样，通过检测电路能够提供预设锤击刷新信号，在正常情况下，预设锤击刷新信号的有效状态持续一个刷新周期，能够通过一个刷新周期内完成锤击刷新指令；在出现偶发错误的情况下，预设锤击刷新信号的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，不仅能够节省带宽资源，而且能够提高锤击刷新的正确性。
在本公开的又一实施例中，参见图15，其示出了本公开实施例提供的一种半导体存储器30的结构示意图。如图15所示，该半导体存储器30至少包括锤击刷新电路20。
由于半导体存储器30至少包括锤击刷新电路20，能够输出预设锤击刷新信号，在正常情况下，预设锤击刷新信号的有效状态持续一个刷新周期，能够通过一个刷新周期内完成锤击刷新指令；在出现偶发错误的情况下，预设锤击刷新信号的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，既能够节省带宽资源，而且能够提高锤击刷新的正确性。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种锤击刷新方法、锤击刷新电路及半导体存储器，确定针对目标字线的锤击刷新指令；根据所述锤击刷新指令，将预设锤击刷新信号置为有效状态；其中，所述预设锤击刷新信号的有效状态指示在第一刷新周期中执行所述锤击刷新指令；若检测到在所述第一刷新周期内未完成所述锤击刷新指令，则将所述预设锤击刷新信号的有效状态延续至所述第一刷新周期的下一刷新周期。这样，在正常情况下，预设锤击刷新信号的有效状态持续一个刷新周期，从而通过一个刷新周期内完成锤击刷新指令；在出现偶发错误的情况下，预设锤击刷新信号的有效状态会持续至下一刷新周期，从而通过两个刷新周期完成锤击刷新指令，既能够节省带宽资源，而且能够提高锤击刷新的正确性。

Claims (18)

  1. 一种锤击刷新方法，所述方法包括：
    确定针对目标字线的锤击刷新指令；
    根据所述锤击刷新指令，将预设锤击刷新信号置为有效状态；其中，所述预设锤击刷新信号的有效状态指示在第一刷新周期中执行所述锤击刷新指令；
    若检测到在所述第一刷新周期内未完成所述锤击刷新指令，则将所述预设锤击刷新信号的有效状态延续至所述第一刷新周期的下一刷新周期。
  2. 根据权利要求1所述的锤击刷新方法，其中，所述方法还包括：
    若检测到完成所述锤击刷新指令时，将所述预设锤击刷新信号置为无效状态。
  3. 根据权利要求2所述的锤击刷新方法，其中，所述锤击刷新指令指示刷新所述目标字线的第一相邻字线和所述目标字线的第二相邻字线；
    所述方法还包括：
    在所述第一刷新周期中，判断所述第一相邻字线和所述第二相邻字线是否被全部刷新；
    若所述第一相邻字线被刷新且所述第二相邻字线未被刷新，则确定在所述第一刷新周期内未完成所述锤击刷新指令；或者
    若所述第一相邻字线和所述第二相邻字线全部被刷新，则确定在所述第一刷新周期内完成所述锤击刷新指令。
  4. 根据权利要求3所述的锤击刷新方法，其中，所述方法还包括：
    确定第一目标状态信号和第二目标状态信号；其中，所述第一目标状态信号用于记录所述第一相邻字线的刷新状态，所述第二目标状态信号用于记录所述第二相邻字线的刷新状态；
    在对所述第一相邻字线进行刷新时，将所述第一目标状态信号置为有效状态，并将所述第二目标状态信号置为无效状态；
    在对所述第二相邻字线进行刷新时，将所述第一目标状态信号置为无效状态，将所述第二目标状态信号置为有效状态。
  5. 根据权利要求4所述的锤击刷新方法，其中，在检测到在所述第一刷新周期内未完成所述锤击刷新指令情况下，所述方法还包括：
    判断是否接收到字线激活指令；
    若判断结果为是，则将所述第一目标状态信号和所述第二目标状态信号均置为无效状态。
  6. 根据权利要求5所述的锤击刷新方法，其中，所述方法还包括：
    在所述预设锤击刷新信号处于有效状态的情况下，确定第一目标状态信号和第二目标状态信号；
    根据所述第一目标状态信号和所述第二目标状态信号，对所述目标字线的相邻字线进行字线刷新处理。
  7. 根据权利要求6所述的锤击刷新方法，其中，所述根据所述第一目标状态信号和所述第二目标状态信号，对所述目标字线的相邻字线进行字线刷新处理，包括：
    在所述第一目标状态信号和所述第二目标状态信号均处于无效状态的情况下，对所述第一相邻字线和所述第二相邻字线分别进行字线刷新处理；
    在所述第一目标状态信号处于有效状态且所述第二目标状态信号处于无效状态的情况下，对所述第二相邻字线进行两次字线刷新处理。
  8. 一种锤击刷新电路，包括：
    检测电路，用于确定锤击刷新触发信号和刷新执行信号；以及
    在所述锤击刷新触发信号指示接收到针对目标字线的锤击刷新指令且所述刷新执行信号指示所述锤击刷新指令未完成时，输出处于有效状态的预设锤击刷新信号；
    其中，所述预设锤击刷新信号的有效状态指示在第一刷新周期内执行所述锤击刷新指令，且所述预设锤击刷新信号的有效状态在所述第一刷新周期内未完成所述锤击刷新指令的情况下将延续至所述第一刷新周期的下一刷新周期。
  9. 根据权利要求8所述的锤击刷新电路，其中，所述刷新执行信号包括初次刷新执行信号和刷新脉冲信号；相应地，所述检测电路包括第一时钟电路、第一刷新状态确定电路和控制信号输出电路；其中，
    所述第一刷新状态确定电路，用于根据所述锤击刷新触发信号、第一时钟信号和第一反相时钟信号，确定第一刷新状态信号和第二刷新状态信号；
    所述第一时钟电路，用于根据所述第一刷新状态信号、所述初次刷新执行信号和所述刷新脉冲信号，确定所述第一时钟信号和所述第一反相时钟信号；
    所述控制信号输出电路，用于根据所述锤击刷新触发信号和所述第二刷新状态信号，确定所述预设锤击刷新信号；
    其中，所述锤击刷新指令指示对所述目标字线的第一相邻字线和所述目标字线的第二相邻字线进行字线刷新处理，所述初次刷新执行信号用于指示每一个刷新周期中第一次发生的字线刷新处理，所述刷新脉冲信号用于指示每一个刷新周期中每一次发生的字线刷新处理。
  10. 根据权利要求9所述的锤击刷新电路，其中，所述第一时钟电路包括第一二输入与非门、第二二输入与非门和第一非门；其中，
    所述第一二输入与非门的输入端分别与所述第一刷新状态信号和所述初次刷新执行信号连接；
    所述第二二输入与非门的输入端分别与所述第一二输入与非门的输出端和所述刷新脉冲信号连接，所述第二二输入与非门的输出端用于输出所述第一反相时钟信号；
    所述第一非门的输入端与所述第一反相时钟信号连接，所述第一非门的输出端用于输出所述第一时钟信号。
  11. 根据权利要求9所述的锤击刷新电路，其中，所述第一刷新状态确定电路包括第一二输入或非门、第三二输入与非门、第二非门、第一触发器和第二触发器；其中，
    所述第一二输入或非门的输入端分别与所述第一刷新状态信号和所述第二刷新状态信号连接，所述第三二输入与非门的输入端分别与所述第一二输入或非门的输出端和所述锤击刷新触发信号连接，所述第二非门的输入端分别与所述第三二输入与非门的输出端连接；
    所述第一触发器的输入端与所述第二非门的输出端连接，所述第一触发器的时钟端分别与所述第一时钟信号和所述第一反相时钟信号连接，所述第二触发器的输出端用于输出所述第一刷新状态信号；
    所述第二触发器的输入端与所述第一刷新状态信号连接，所述第二触发器的时钟端分别与所述第一时钟信号和所述第一反相时钟信号连接，所述第二触发器的输出端用于输出所述第二刷新状态信号。
  12. 根据权利要求9所述的锤击刷新电路，其中，所述控制信号输出电路包括第三非门、第四二输入与非门和第四非门；其中，
    所述第三非门的输入端与所述第二刷新状态信号连接，所述第四二输入与非门的输入端分别与所述第三非门的输出端和所述锤击刷新触发信号连接；
    所述第四非门的输入端与所述第四二输入与非门的输出端连接，且所述第四非门的输出端用于输出所述预设锤击刷新信号。
  13. 根据权利要求9所述的锤击刷新电路，其中，所述锤击刷新电路还包括状态计数电路；
    所述状态计数电路，用于接收所述预设锤击刷新信号和字线状态信号，并根据所述预设锤击刷新信号和字线状态信号，确定第一目标状态信号和第二目标状态信号；
    其中，所述第一目标状态信号用于记录所述第一相邻字线的刷新状态，所述第二目标状态信号用于记录所述第二相邻字线的刷新状态。
  14. 根据权利要求13所述的锤击刷新电路，其中，所述字线状态信号包括刷新状态有效信号和字线开启脉冲信号；所述状态计数电路包括第二时钟电路、第二刷新状态确定电路和复位电路；其中，
    所述第二时钟电路，用于根据所述预设锤击刷新信号、所述刷新状态有效信号和所述字线开启脉冲信号，确定第二时钟信号和第二反相时钟信号的；
    所述复位电路，用于根据所述刷新状态有效信号、所述字线开启脉冲信号和所述第一目标状态信号，确定复位信号；
    所述第二刷新状态确定电路，用于根据所述第二时钟信号、所述第二反相时钟信号和所述复位信号，确定所述第一目标状态信号和所述第二目标状态信号；
    其中，所述刷新状态有效信号指示是否处于一个刷新周期中，所述字线开启脉冲信号指示任意字线的开启。
  15. 根据权利要求14所述的锤击刷新电路，其中，所述第二时钟电路包括第一三输入与非门和第五非门；其中，
    所述第一三输入与非门的输入端分别与所述预设锤击刷新信号、所述刷新状态有效信号和所述字线开启脉冲信号连接，所述第一三输入与非门的输出端用于输出所述第二反相时钟信号；
    所述第五非门的输入端与所述第一三输入与非门的输出端连接，所述第五非门的输出端用于输出所述第二时钟信号。
  16. 根据权利要求14所述的锤击刷新电路，其中，所述第二刷新状态确定电路包括第三触发器、第四触发器和第六非门；
    所述第三触发器的输入端通过所述第六非门与所述第三触发器的输出端连接，且所述第三触发器的输出端用于输出所述第一目标状态信号；所述第三触发器的时钟端分别与所述第二时钟信号和所述第二反相时钟信号连接；
    所述第四触发器的输入端与所述第一目标状态信号连接，所述第四触发器的时钟端分别与所述第二时钟信号和所述第二反相时钟信号连接，且所述第四触发器的输出端用于输出所述第二目标状态信号；
    所述第三触发器和所述第四触发器各自的复位端均与所述复位信号连接。
  17. 根据权利要求14所述的锤击刷新电路，其中，所述复位电路包括第七非门和第二三输入与非门；
    所述第七非门的输入端与所述刷新状态有效信号连接，所述第二三输入与非门的输入端分别与所述第七非门的输出端、所述字线开启脉冲信号和所述第一目标状态信号连接，所述第二三输入与非门的输出端用于输出所述复位信号。
  18. 一种半导体存储器，包括如权利要求8至17任一项所述的锤击刷新电路。
PCT/CN2022/072108 2021-11-19 2022-01-14 一种锤击刷新方法、锤击刷新电路及半导体存储器 Ceased WO2023087533A1 (zh)

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