WO2023088013A1 - 碳化硅半导体器件及其制作方法 - Google Patents

碳化硅半导体器件及其制作方法 Download PDF

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WO2023088013A1
WO2023088013A1 PCT/CN2022/125793 CN2022125793W WO2023088013A1 WO 2023088013 A1 WO2023088013 A1 WO 2023088013A1 CN 2022125793 W CN2022125793 W CN 2022125793W WO 2023088013 A1 WO2023088013 A1 WO 2023088013A1
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Prior art keywords
epitaxial layer
layer
region
trench
well region
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French (fr)
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袁俊
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Hubei Jiufengshan Laboratory
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Hubei Jiufengshan Laboratory
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Priority claimed from CN202111363503.1A external-priority patent/CN114141627B/zh
Priority claimed from CN202122827400.8U external-priority patent/CN216120213U/zh
Application filed by Hubei Jiufengshan Laboratory filed Critical Hubei Jiufengshan Laboratory
Priority to EP22894550.7A priority Critical patent/EP4376056A4/en
Priority to JP2024506177A priority patent/JP7698787B2/ja
Publication of WO2023088013A1 publication Critical patent/WO2023088013A1/zh
Priority to US18/426,392 priority patent/US20240170540A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/159—Shapes

Definitions

  • the present application relates to the technical field of semiconductor devices, and more specifically, to a silicon carbide (SiC) semiconductor device and a manufacturing method thereof.
  • SiC silicon carbide
  • Silicon carbide semiconductor devices have become a major development direction in the semiconductor field due to their excellent characteristics in high-power applications.
  • the present application provides a silicon carbide semiconductor device and a manufacturing method thereof, the scheme is as follows:
  • a method for manufacturing a silicon carbide semiconductor device comprising:
  • An epitaxial wafer includes: a semiconductor substrate; a first epitaxial layer disposed on the surface of the semiconductor substrate; a second epitaxial layer disposed on the surface of the first epitaxial layer away from the semiconductor substrate; a third epitaxial layer on a surface of the second epitaxial layer facing away from the first epitaxial layer;
  • a gate is formed within the trench.
  • the second epitaxial layer has a region to be implanted and a well region of the first layer surrounding the region to be implanted;
  • forming a well region, a source region and a trench in the third epitaxial layer including:
  • a second-layer well region, a third-layer well region and a source region are sequentially formed in the third epitaxial layer; the second-layer well region is located between the first-layer well region and the third-layer well region Between the well regions, the source region is located on the side of the third layer well region away from the second layer well region;
  • the groove is formed in the surface of the third epitaxial layer facing away from the second epitaxial layer; the bottom of the groove is located between the second epitaxial layer and the well region of the third layer;
  • both the source region and the third-layer well region are in contact with the sidewall of the trench; the second-layer well region has a distance from the sidewall of the trench.
  • the manufacturing method of the epitaxial wafer includes:
  • the doping type of the first epitaxial layer is the same as that of the third epitaxial layer, and is inversely doped with the second epitaxial layer.
  • the above preparation method it also includes:
  • a metal drain is formed on the surface of the semiconductor substrate away from the first epitaxial layer.
  • the present application also provides a silicon carbide semiconductor device prepared as described above, including:
  • An epitaxial wafer comprising: a semiconductor substrate; a first epitaxial layer arranged on the surface of the semiconductor substrate; a second epitaxial layer arranged on the surface of the first epitaxial layer away from the semiconductor substrate; a third epitaxial layer on the surface of the second epitaxial layer away from the first epitaxial layer;
  • the second epitaxial layer in the doped region is inversely doped, formed by ion implantation based on the trench;
  • a gate disposed in the trench.
  • the second epitaxial layer has a region to be implanted and a first layer well region surrounding the region to be implanted;
  • the third epitaxial layer has a second layer well region, a first layer well region Three-layer well region and the source region;
  • the second-layer well region is located between the first-layer well region and the third-layer well region, and the source region is located away from the third-layer well region
  • the source region and the third-layer well region are in contact with the sidewall of the trench;
  • the second-layer well region has a distance from the sidewall of the trench ;
  • the trench is located in the surface of the third epitaxial layer facing away from the semiconductor substrate;
  • the bottom of the trench is located between the second epitaxial layer and the well region of the third layer;
  • the thickness of the third epitaxial layer is not more than 1 ⁇ m; the distance between the bottom of the trench and the first epitaxial layer is less than 1 ⁇ m.
  • the width of the trench satisfies a uniform condition.
  • the width of the trench gradually increases in a direction from the bottom of the trench to the opening.
  • the width of the doped region is not greater than the width of the trench.
  • the doping type of the doped region, the first epitaxial layer and the third epitaxial layer are the same;
  • the doping concentration of the doped region is greater than the doping concentration of the first epitaxial layer and the third epitaxial layer.
  • the epitaxial wafer includes: a semiconductor substrate; a first epitaxial layer disposed on the surface of the semiconductor substrate; a second epitaxial layer on one side surface of the semiconductor substrate; a third epitaxial layer disposed on a side surface of the second epitaxial layer away from the first epitaxial layer.
  • the gate is formed by the trench provided on the third epitaxial layer, and ion implantation can be performed in the second epitaxial layer based on the trench before forming the gate, so that in the second epitaxial layer Forming a doped region of the inverse type to the second epitaxial layer solves the problem that it is inconvenient to form a relatively deep doped region in silicon carbide semiconductor power devices.
  • Fig. 1 is a structural schematic diagram of a DMOSFET
  • Fig. 2 is a structural representation of a UMOSFET
  • Figure 3 is a waveform diagram of the voltage overshoot and oscillation phenomenon at the moment of MOSFET switching
  • 4-10 are process flow charts of a method for manufacturing a silicon carbide semiconductor device provided in an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a silicon carbide semiconductor device provided in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of the main current paths of the silicon carbide semiconductor device shown in FIG. 10 at the moment of turn-on;
  • Fig. 13 is a schematic diagram of equivalent parasitic parameters of the silicon carbide semiconductor device shown in Fig. 12;
  • Fig. 14 is a layout of a silicon carbide semiconductor device provided in an embodiment of the present application in terms of trench design and ion implantation area in a doped region.
  • SiC vertical power MOSFET devices mainly include lateral double-diffused DMOSFET and UMOSFET with vertical gate groove structure.
  • Figure 1 is a structural schematic diagram of a DMOSFET, including: an n+ (n-type heavily doped) substrate 2; an n- (n-type lightly doped) drift region 3 disposed on the surface of the substrate 2 a p-type well region 4 located in the drift region 3; and a source region 5 located in the p-type well region, the source region 5 includes an n+ doped region 51 and a p+ (p-type heavily doped) doped region 52.
  • a gate dielectric layer 7 is disposed on the surface of the drift region 3
  • a gate 8 is disposed on the surface of the gate dielectric layer 7 .
  • a drain 1 is provided on a surface of the substrate 2 away from the drift region 3 .
  • the DMOSFET structure adopts planar diffusion technology, uses refractory materials, such as polysilicon gate as a mask, and defines the p base region and n+ source region with the edge of the polysilicon gate.
  • refractory materials such as polysilicon gate as a mask
  • the name of DMOS comes from this double diffusion process.
  • the surface channel region is formed by utilizing the difference in lateral diffusion of the p-type base region and the n+ source region.
  • Figure 2 is a schematic structural diagram of a UMOSFET.
  • the difference from the structure shown in Figure 1 is that a U-shaped groove is arranged in the UMOSFET, and the surface of the U-shaped groove is covered with a gate dielectric layer 7, and the gate 8 is filled with in the U-shaped groove.
  • the UMOSFET with vertical gate trench structure is named after the U-shaped trench structure.
  • the U-shaped trench structure is formed in the gate region by reactive ion etching.
  • the U-shaped trench structure has a higher channel density (the channel density is defined as the channel width of the active region), which makes the on-state characteristic resistance of the device significantly reduced.
  • FIG. 3 shows the instantaneous voltage overshoot and The waveform diagram of the oscillation phenomenon, based on Figure 3, it can be seen that the instantaneous overvoltage on the current path of the device increases the loss of the switching process; or due to changes in power loads, etc., a large surge voltage is formed. Pressure protection is also very important.
  • the ion implantation depth is limited, which makes many targeted trench gate protection structures and anti-surge designs difficult to realize in terms of technology.
  • the depth of the trench used to form the gate is more than 1 ⁇ m-2 ⁇ m, because the gate structure in the trench must be protected, and the actual manufacturing process of the buried protection structure cannot be directly completed by ion implantation. This is because in the silicon carbide process, ions The implantation depth is difficult to exceed 1 ⁇ m.
  • the required doping regions are generally formed in the previously formed epitaxial layer by etching and ion implantation, and then two P-type epitaxial layers with specific structures are formed, resulting in complex manufacturing process and high manufacturing cost.
  • Figure 4- Figure 10 is a process flow chart of a silicon carbide semiconductor device manufacturing method provided in the embodiment of the present application.
  • the manufacturing method includes:
  • Step S11 As shown in FIG. 4, an epitaxial wafer is provided, and the epitaxial wafer includes: a semiconductor substrate 10; a first epitaxial layer 11 disposed on the surface of the semiconductor substrate 10; The second epitaxial layer 12 on one side surface of the semiconductor substrate 10; the third epitaxial layer 13 disposed on the side surface of the second epitaxial layer 12 away from the first epitaxial layer 11.
  • the epitaxial wafer is a silicon carbide epitaxial wafer, and each epitaxial layer on the semiconductor substrate 10 and its surface is made of silicon carbide material.
  • Step S12 As shown in FIGS. 5-8 , forming a well region, a source region 15 and a trench 20 in the third epitaxial layer 13;
  • Step S13 As shown in FIG. 9 , based on the trench 20, ion implantation is performed in the second epitaxial layer 12 to form a doped region 17 that is inverse to the second epitaxial layer 12; the doped a region 17 runs through said second epitaxial layer 12;
  • Step S14 as shown in FIG. 10 , forming a gate 18 in the trench 20 .
  • FIG. 10 only shows a cell structure of the semiconductor device.
  • the semiconductor device may be a silicon carbide MOSFET device.
  • the semiconductor device may have multiple cell structures.
  • the number of cells and the layout mode can be set according to requirements, which are not specifically limited in this embodiment of the present application.
  • the manufacturing method of the epitaxial wafer includes: sequentially epitaxially forming the first epitaxial layer 11, the second epitaxial layer 12, and the third epitaxial layer on the surface of the semiconductor substrate 10. layer 13; wherein, the doping type of the first epitaxial layer 11 is the same as that of the third epitaxial layer 13, and is inversely doped with the second epitaxial layer 12.
  • the semiconductor substrate 10 can be set to be an n+ type doped silicon carbide substrate, the first epitaxial layer 11 and the third epitaxial layer 13 are both n-type doped silicon carbide epitaxial layers, and the second epitaxial layer Layer 12 is a p-type doped silicon carbide epitaxial layer. If so, the p-type doped second epitaxial layer 12 is a buried layer, and the epitaxial wafer with the buried layer is cleverly used, and the trench 20 required by the gate 8 is used to perform ion implantation to form a doped region 17, thereby solving the problem. The shielding of the trench gate structure and the difficulty of the silicon carbide material implantation process are overcome. Moreover, the doped region 17 can form a modulating JFET structure in the current path of the device, which can automatically adjust the device resistance and self-locking protection effect while having a smaller device cell size.
  • the well region structure includes: a first layer well region 141 , a second layer well region 142 and a third layer well region 143 .
  • the second epitaxial layer 12 has a region to be implanted and a first layer well region 141 surrounding the region to be implanted; the region to be implanted is used to form the doped region 17 .
  • step S12 a well region, a source region 15 and a trench 20 are formed in the third epitaxial layer 13, including:
  • a second-layer well region 142 , a third-layer well region 143 and a source region 15 are sequentially formed in the third epitaxial layer 13 ;
  • the region 142 is located between the first-layer well region 141 and the third-layer well region 143 , and the source region 15 is located on a side of the third-layer well region 143 away from the second-layer well region 142 .
  • ion implantation is performed based on the mask layer 01 to form a second-layer well region 142 in the third epitaxial layer 13 , and the second-layer well region 142 surrounds a non-implantation region.
  • a required non-implantation region is formed based on the patterned mask layer 01 .
  • the vertical projections of the trench 20 and the doped region 17 are both in the non-implantation region, and have a distance from the non-implantation region in a direction parallel to the epitaxial wafer (ie, the horizontal direction in FIGS. 5-8 ). Further, as shown in FIG.
  • the third well region 143 is formed on the second well region 142 by ion implantation again, and the third well region 143 covers the second well region 142 and the surrounding non-implantation region . Further, as shown in FIG. 7 , the source region 15 is formed on the third layer well region 143 by ion implantation again.
  • the trench 20 is formed in the surface of the third epitaxial layer 13 facing away from the second epitaxial layer 12; the bottom of the trench 20 is located in the second epitaxial layer 12 and the third-layer well region 143 .
  • both the source region 15 and the third-layer well region 143 are in contact with the sidewall of the trench 20; when the source region 15 is formed by ion implantation, the ion implantation region covers the region for forming the trench 20, Therefore, after the trenches are formed subsequently, the unremoved source regions 15 can directly contact the sidewalls of the trenches 20 .
  • the third-layer well region 143 is formed by ion implantation, the ion-implanted region covers the region used to form the trench 20, so after the subsequent formation of the trench, the unremoved third-layer well region 143 can directly contact the trench. 20 sidewall contacts.
  • the second layer well region 142 has a distance from the sidewall of the trench 20 .
  • the size of the non-implanted region surrounded by the second-layer well region 142 is set to be larger than the size of the trench 20, and the vertical projection of the trench 20 is set to be located in the non-implanted region, and it is connected to the non-implanted region There is a distance, that is, the second-layer well region 142 may not be in contact with the sidewall of the trench 20 , so that there is a distance between them.
  • the preparation method also includes:
  • a metal drain 19 is formed on the surface of the semiconductor substrate 10 away from the first epitaxial layer 11 .
  • the source region 15 includes a first region 151 and a second region 152 with opposite doping types, and the source region 15 is in contact with both the first region 151 and the second region 152 . It can be set that the first region 151 is an n+ type doped region, and the second region 152 is a p+ type doped region.
  • the well region structure includes three layers, namely, the first layer well region 141 , the second layer well region 142 and the third layer well region 143 .
  • the uppermost well region 143 of the third layer is located on the left and right sides of the trench 20 and is in contact with the sidewall of the trench 20 .
  • the second layer well region 142 of the middle layer includes two parts located on the left and right sides of the trench 20 and not in contact with the sidewall of the trench 20 .
  • the lowermost well region 141 of the first layer is located under the trench 20 and has no contact with the trench 20 .
  • the distance between the left and right parts of the second-layer well region 142 and the vertical central axis of the cellular structure is greater than the distance between the left and right parts of the first-layer well region 141 and the vertical central axis of the cellular structure.
  • the vertical central axis of the cell structure is the central axis of the trench 20 , as shown by the dotted line in FIG. 10 , the first well region 141 is closer to the central axis than the second well region 142 .
  • a specific JFET structure can be formed on the current path between the source and drain through the doped region 17, and the conduction characteristics of the JFET structure can be determined by the pattern design and ion implantation concentration of the doped region 17 and Graphical profiles are optimally tuned to improve semiconductor device performance.
  • the technical solution of the present application solves the shielding of the gate oxide structure of the SiC trench MOSFET and the deep implantation in the silicon carbide material by skillfully involving the second epitaxial layer 12 and the doped region 17 penetrating through the second epitaxial layer 12 in the epitaxial wafer.
  • the doped region 17 can also introduce a JFET structure that can be modulated by ion implantation on the current path of the device, while automatically adjusting the on-resistance and self-locking protection effect of the device, it can also maintain a relatively high Small device cell size.
  • the silicon carbide semiconductor device formed based on the manufacturing method described in the embodiment of the present application has at least the following beneficial effects:
  • the silicon carbide semiconductor device can introduce a JFET structure into the current path of the cell structure, automatically adjust the device on-resistance and self-locking protection effect while maintaining a small device cell size, and the conduction characteristics of the JFET structure
  • the pattern design, ion implantation concentration, and pattern profile of the doping region 17 are optimized and adjusted, so that the design and process are flexible and have good manufacturability.
  • the depletion regions on both sides can be automatically extended under a large surge voltage to increase the JFET structure.
  • the on-resistance is equivalent to a buffer circuit structure that suppresses the surge peak by itself; at the same time, when the surge voltage is too large, the depleted regions on both sides continue to expand and overlap each other, which acts as a blockade effect and protects the gate on the inner trench surface.
  • the polar dielectric layer plays a certain role in the protection of peak voltage overvoltage.
  • JFET structure Although the introduction of the JFET structure will increase a certain on-resistance, it has the effect of switch buffer and surge voltage self-suppression.
  • the silicon carbide semiconductor device can increase the self-suppression resistance of the device to surge voltage and overvoltage, and avoid damage to the device and impairment of reliability caused by the time delay in the actual action of the overvoltage protection circuit and the overcurrent protection circuit.
  • it also buffers the peak jitter in the circuit switching process and reduces the switching loss; it can reduce the buffer circuit and buffer circuit structure in the circuit design, and reduce discrete components, thereby reducing costs and reducing actual modules. volume, enhanced reliability.
  • FIG. 10 Another embodiment of the present application also provides a silicon carbide semiconductor device, which can be prepared by using the manufacturing method described in the above-mentioned embodiment, and its structure can be shown in Figure 10, including:
  • An epitaxial wafer comprising: a semiconductor substrate 10; a first epitaxial layer 11 disposed on the surface of the semiconductor substrate 10; a second epitaxial layer disposed on the surface of the first epitaxial layer 11 away from the semiconductor substrate 10 layer 12; a third epitaxial layer 13 disposed on the surface of the second epitaxial layer 12 facing away from the first epitaxial layer 11;
  • the doped region 17 running through the second epitaxial layer 12, the doped region 17 and the second epitaxial layer are inversely doped, and formed by ion implantation based on the trench;
  • a gate 18 is disposed within the trench.
  • the gate 18 includes a filling medium filling the trench and a metal gate located on the surface of the filling medium.
  • the surface of the trench has a gate dielectric layer, and after the gate dielectric layer is formed, a gate 18 is formed in the trench.
  • the filling medium may be polysilicon or the like.
  • a doped region 17 is formed before forming the gate dielectric layer in the trench.
  • the second epitaxial layer 12 has a region to be implanted and a first layer well region 141 surrounding the region to be implanted;
  • the third epitaxial layer 13 has a second layer well region 142, a third layer well region 142 and the source region 15;
  • the second layer well region 142 is located between the first layer well region 141 and the third layer well region 143, and the source region 15 is located in the third layer well region 143
  • the side away from the second-layer well region 142; the source region 15 and the third-layer well region 143 are in contact with the sidewall of the trench;
  • the bottom of the trench is located in the second epitaxial between the layer 12 and the third-layer well region 143;
  • the second-layer well region 142 is located on both sides of the trench, and has a distance from the sidewall of the trench.
  • the thickness of the third epitaxial layer 13 is not more than 1 ⁇ m, so that the ion implantation depths of the second layer well region 142 and the third layer well region 143 are not more than 1 ⁇ m, and the carbonization can be achieved by ion implantation.
  • the second-layer well region 142 and the third-layer well region 143 are formed in the third epitaxial layer 13 of silicon material without causing lattice damage.
  • the distance between the bottom of the trench and the first epitaxial layer 11 is less than 1 ⁇ m, so that when ion implantation is performed based on the trench to form the doped region 17, the ion implantation depth of the doped region 17 is less than 1 ⁇ m, the doped region 17 can be formed in the second epitaxial layer 12 of the silicon carbide material by ion implantation without causing lattice damage.
  • the doped region 17 has a non-zero distance from the bottom of the trench.
  • the width of the groove satisfies the uniform condition, that is, the width of the groove is the same in this direction Or approximately the same, that is, the grooves are rectangular grooves.
  • the second epitaxial layer 12 is an epitaxial layer with a uniform thickness, and setting the width of the trench to meet the uniform condition facilitates the formation of the doped region 17 with a uniform width in the direction.
  • the structure of the electronic device may also be as shown in FIG. 11 , which is a schematic structural diagram of a silicon carbide semiconductor device provided in an embodiment of the present application.
  • This manner is different from the structure shown in FIG. 10 in that, in the The bottom of the groove points in the direction of the opening, and the width of the groove increases gradually, that is, the groove is a V-shaped groove or an inverted trapezoidal groove. If it is a V-shaped trench, the doped region 17 has a V-shaped structure. If it is an inverted trapezoidal trench, when the ion implantation window is larger than the bottom of the trench, the doped region is an inverted trapezoidal structure as shown in Figure 11. If the ion implantation window Not larger than the bottom of the trench, and the doped region has a rectangular structure.
  • the width of the doped region 17 is not greater than the width of the trench, so that ion implantation can be performed based on the trench to form the doped region 17, so as to reduce the depth of ion implantation,
  • the doping types of the doped region 17 , the first epitaxial layer 11 and the third epitaxial layer 13 are the same.
  • the silicon carbide semiconductor device is NMOS.
  • the semiconductor substrate 10 is an n+ type substrate
  • the first epitaxial layer 11 and the third epitaxial layer 13 are n-type doped
  • the second epitaxial layer 12 is p-type doped
  • the impurity region 17 is n-type doped.
  • the relationship between the doping concentration is n+>n>n-, p+>p>p-.
  • n-, n and n+ are the same type doping, all of which are the first type doping.
  • p-, p and p+ are the same type of doping, all of which are the second type of doping.
  • the first type doping and the second type doping are anti-type doping.
  • the silicon carbide semiconductor device can also be PMOS.
  • the doping type can be set based on requirements to form NMOS or PMOS.
  • the doping concentration of the doping region 17 is greater than the doping concentration of the first epitaxial layer 11 and the third epitaxial layer 13 .
  • the doped region 17 is n+ type doped.
  • Figure 12 is a schematic diagram of the main current path of the silicon carbide semiconductor device shown in Figure 10 at the moment of turn-on.
  • the doped region 17 forms the JFET structure. Due to the rapid change of the current, a high-frequency peak voltage is generated in the circuit, and at the same time, due to the rapid change of the voltage on the current path, the depletion region of the JFET structure (the region between the left and right dashed curves in Figure 12) corresponds to different voltages Changes will rapidly expand or contract, and the JFET structure is now equivalent to a parallel structure of a variable resistance R and a junction capacitance C, as shown in Figure 13, which is the equivalent of the silicon carbide semiconductor device shown in Figure 12 Schematic diagram of parasitic parameters.
  • only a single cell structure is used to illustrate the silicon carbide semiconductor device.
  • multiple cellular structures can be fabricated simultaneously based on a wafer-level process, and then the wafer is divided to form the silicon carbide semiconductor device, and the silicon carbide semiconductor device has multiple cellular structures.
  • FIG. 14 is a layout of a silicon carbide semiconductor device provided in the embodiment of the present application in the trench design and ion implantation area of the doped region.
  • the implantation window of the doped region 17 is located in the trench 20, and the JFET structure
  • the channel characteristics of the doped region 17 can be adjusted by the pattern design of the doping region 17, the ion implantation concentration and the pattern profile design.
  • the implantation window area of the doped region 17 may be smaller than or equal to the area of the trench 20 .

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  • Junction Field-Effect Transistors (AREA)

Abstract

本申请公开了一种碳化硅半导体器件及其制作方法，外延片包括：半导体基底；设置在所述半导体基底表面的第一外延层；设置在所述第一外延层背离所述半导体基底一侧表面的第二外延层；设置在所述第二外延层背离所述第一外延层一侧表面的第三外延层。通过设置在第三外延层上的沟槽形成栅极，而且还能够基于形成栅极之前的所述沟槽，在所述第二外延层中进行离子注入，以在所述第二外延层中形成与所述第二外延层反型的掺杂区，解决了碳化硅半导体功率器件不便于形成较大深度掺杂区的难题。

Description

碳化硅半导体器件及其制作方法
本申请要求于2021年11月17日提交中国专利局、申请号为202111363503.1、发明名称为“碳化硅半导体器件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请要求于2021年11月17日提交中国专利局、申请号为202122827400.8、发明名称为“碳化硅半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件技术领域，更具体的说，涉及一种碳化硅(SiC)半导体器件及其制作方法。
背景技术
随着科学技术的不断发展，越来越多的电子设备被广泛的应用于人们的日常生活以及工作当中，为人们的日常生活以及工作带来了巨大的便利，成为当今人们不可或缺的重要工具。
电子设备实现各种功能的主要结构是集成电路，而半导体器件是集成电路的重要组成电子元件。碳化硅半导体器件由于其在高功率应用领域的优良特性，成为半导体领域的一个主要发展方向。
由于碳化硅材料的特性，如果要实现较大注入深度的掺杂，高能量的离子注入会导致其晶格损伤，故现有制作方法中，在制作具有较大深度掺杂区的碳化硅半导体器件时，需要在外延片的制作过程中，先通过刻蚀以及离子注入在先形成的外延层内形成所需掺杂区，然后形成后续外延层。
发明内容
有鉴于此，本申请提供了一种碳化硅半导体器件及其制作方法，方案如下：
一种碳化硅半导体器件的制作方法，包括：
提供一外延片，所述外延片包括：半导体基底；设置在所述半导体基底表面的第一外延层；设置在所述第一外延层背离所述半导体基底一侧表面的第二外延层；设置在所述第二外延层背离所述第一外延层一侧表面的第三外延层；
在所述第三外延层内形成阱区、源区以及沟槽；
基于所述沟槽，在所述第二外延层中进行离子注入，形成与所述第二外延层反型的掺杂区；所述掺杂区贯穿所述第二外延层；
在所述沟槽内形成栅极。
优选的，在上述制作方法中，所述第二外延层具有待注入区以及包围所述待注入区的第一层阱区；
在所述第三外延层内形成阱区、源区以及沟槽，包括：
通过离子注入，在所述第三外延层内依次形成第二层阱区、第三层阱区以及源区；所述第二层阱区位于所述第一层阱区与所述第三层阱区之间，所述源区位于所述第三层阱区背离所述第二层阱区的一侧；
在所述第三外延层背离所述第二外延层的一侧表面内形成所述沟槽；所述沟槽的底部位于所述第二外延层与所述第三层阱区之间；
其中，所述源区以及所述第三层阱区均与所述沟槽的侧壁接触；所述第二 层阱区与所述沟槽的侧壁具有间距。
优选的，在上述制作方法中，所述外延片的制作方法包括：
在所述半导体基底表面依次外延形成所述第一外延层、所述第二外延层以及所述第三外延层；
其中，所述第一外延层与所述第三外延层的掺杂类型相同，且与所述第二外延层为反型掺杂。
优选的，在上述制作方法中，还包括：
形成与所述源区连接的金属源极；
在所述半导体基底背离所述第一外延层的一侧表面形成金属漏极。
本申请还提供了一种如上述制作方法制备的碳化硅半导体器件，包括：
外延片，所述外延片包括：半导体基底；设置在所述半导体基底表面的第一外延层；设置在所述第一外延层背离所述半导体基底一侧表面的第二外延层；设置在所述第二外延层背离所述第一外延层一侧表面的第三外延层；
设置在所述第三外延层内的阱区、源区以及沟槽；
贯穿所述第二外延层的掺杂区，所述掺杂区所述第二外延层为反型掺杂，基于所述沟槽通过离子注入形成；
设置在所述沟槽内的栅极。
优选的，在上述碳化硅半导体器件中，所述第二外延层具有待注入区以及包围所述待注入区的第一层阱区；所述第三外延层内具有第二层阱区、第三层阱区以及所述源区；所述第二层阱区位于所述第一层阱区与所述第三层阱区之 间，所述源区位于所述第三层阱区背离所述第二层阱区的一侧；所述源区以及所述第三层阱区均与所述沟槽的侧壁接触；所述第二层阱区与所述沟槽的侧壁具有间距；所述沟槽位于所述第三外延层背离所述半导体基底的一侧表面内；所述沟槽的底部位于所述第二外延层与所述第三层阱区之间；
所述第三外延层的厚度不超过1μm；所述沟槽的底部与所述第一外延层的距离小于1μm。
优选的，在上述碳化硅半导体器件中，在所述沟槽的底部指向开口的方向上，所述沟槽的宽度满足均匀条件。
优选的，在上述碳化硅半导体器件中，在所述沟槽的底部指向开口的方向上，所述沟槽的宽度逐渐增大。
优选的，在上述碳化硅半导体器件中，所述掺杂区的宽度不大于所述沟槽的宽度。
优选的，在上述碳化硅半导体器件中，所述掺杂区、所述第一外延层与所述第三外延层的掺杂类型相同；
所述掺杂区的掺杂浓度大于所述第一外延层与所述第三外延层的掺杂浓度。
通过上述描述可知，本申请技术方案提供的碳化硅半导体器件及其制作方法中，外延片包括：半导体基底；设置在所述半导体基底表面的第一外延层；设置在所述第一外延层背离所述半导体基底一侧表面的第二外延层；设置在所述第二外延层背离所述第一外延层一侧表面的第三外延层。通过设置在第三外 延层上的沟槽形成栅极，而且还能够基于形成栅极之前的所述沟槽，在所述第二外延层中进行离子注入，以在所述第二外延层中形成与所述第二外延层反型的掺杂区，解决了碳化硅半导体功率器件不便于形成较大深度掺杂区的难题。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本申请可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本申请所能产生的功效及所能达成的目的下，均应仍落在本申请所揭示的技术内容得能涵盖的范围内。
图1为一种DMOSFET的结构示意图；
图2为一种UMOSFET的结构示意图；
图3为MOSFET开关瞬间的电压过冲及震荡现象的波形图；
图4-图10为本申请实施例提供的一种碳化硅半导体器件制作方法的工艺流程图；
图11为本申请实施例提供的一种碳化硅半导体器件的结构示意图；
图12为图10所示碳化硅半导体器件在开通瞬间的主要电流通路示意；
图13为图12所示碳化硅半导体器件等效寄生参数示意图；
图14为本申请实施例提供的一种碳化硅半导体器件在沟槽设计与掺杂区 离子注入面积的版图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请中的实施例进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
SiC材料因其优良特性，在高功率方面具有强大的吸引力，成为高性能功率MOSFET的理想材料之一。SiC垂直功率MOSFET器件主要有横向型的双扩散DMOSFET以及垂直栅槽结构的UMOSFET。
如图1所示，图1为一种DMOSFET的结构示意图，包括：n+(n型重掺杂)的基底2；设置在基底2表面上的n-(n型轻掺杂)的漂移区3；位于漂移区3内的p型阱区4；以及位于p型阱区内的源区5，源区5包括n+掺杂区51和p+(p型重掺杂)掺杂区52。漂移区3表面上设置有栅极介质层7，栅极介质层7表面上具有栅极8。基底2背离漂移区3的一侧表面具有漏极1。
DMOSFET结构采用了平面扩散技术，采用难熔材料，如多晶硅栅作掩膜，用多晶硅栅的边缘定义p基区和n+源区。DMOS的名称就源于这种双扩散工艺。利用p型基区和n+源区的侧面扩散差异来形成表面沟道区域。
如图2所示，图2为一种UMOSFET的结构示意图，与图1所示结构不同在于，UMOSFET中设置有U型槽，U型槽的表面覆盖有栅极介质层7，栅极8填充在U型槽内。垂直栅槽结构的UMOSFET，其命名源于U型沟槽结构。该U型沟槽结构利用反应离子刻蚀在栅区形成。U型沟槽结构具有较高的沟道密度(沟道密度定义为有源区沟道宽度)，这使得器件的开态特征电阻显著减小。
平面型SiC MOSFET经过行业内多年的研究，已经有一些厂商率先推出了商业化产品。对于普通横向型DMOSFET结构而言，现代技术进步已经达到了缩小MOS元胞尺寸而无法降低导通电阻的程度，主要原因是由于JFET颈区电阻的限制，即使采用更小的光刻尺寸，单位面积导通电阻也难以降到2mΩ·cm 2，而沟槽结构可以有效解决这个问题。U型沟槽结构如图2所示，其采用了在存储器存储电容制各工艺中沟槽刻蚀技术，使导电沟道从横向变为纵向，相比普通结构消除了JFET颈电阻，大大增加了元胞密度，提高了功率半导体的电流处理能力。
然而，SiC UMOSFET在实际工艺制作和应用中仍然存在几个问题：
1)SiC漂移区的高电场导致栅极介质层上的电场很高，这个问题在槽角处加剧，从而在高漏极电压下造成栅极介质层迅速击穿；对于恶劣环境的静电效应以及电路中的高压尖峰耐受能力差。
2)由于SiC功率MOSFET主要应用在高压高频大电流领域，电路中的寄生参数会使得在高频开关过程中产生尖峰毛刺，如图3所示，图3为MOSFET开关瞬间的电压过冲及震荡现象的波形图，基于图3可知，造成器件电流通路上的瞬时过压同时增加了开关过程的损耗；或由于功率负载等变化形成大的浪涌电压，因此MOSFET抗浪涌电压能力和过压保护也非常重要。
因为常规MOSFET器件本身并不具备抗浪涌电压自抑制能力和过压保护能力，往往需要在实际应用中设计复杂的缓冲电路，浪涌电压抑制电路和过压保护电路。而这种外部匹配的抑制和过压保护电路往往有时间上的延迟，实际开关过程中的高频尖峰电压浪涌仍然由器件本身承受，有时会导致器件沟道区 的击穿失效，以及栅结构和电极欧姆接触区域的逐渐失效，引起器件可靠性问题。
3)离子注入深度有限，导致很多针对性的沟槽栅极保护结构和抗浪涌设计从工艺上难以实现。一般用于形成栅极的沟槽深度在1μm-2μm以上，因为要保护沟槽内栅极结构，掩埋型保护结构的实际制作工艺无法直接用离子注入完成，这是由于碳化硅工艺里，离子注入深度很难超过1μm。现有技术一般是先通过刻蚀以及离子注入在先形成的外延层内形成所需掺杂区，然后形成两层特定结构的P型外延层，导致制作工艺复杂，且制作成本较高。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
如图4-图10所示，图4-图10为本申请实施例提供的一种碳化硅半导体器件制作方法的工艺流程图，该制作方法包括：
步骤S11：如图4所示，提供一外延片，所述外延片包括：半导体基底10；设置在所述半导体基底10表面的第一外延层11；设置在所述第一外延层11背离所述半导体基底10一侧表面的第二外延层12；设置在所述第二外延层12背离所述第一外延层11一侧表面的第三外延层13。
其中，所述外延片为碳化硅外延片，所述半导体基底10及其表面的各个外延层均为碳化硅材料。
步骤S12：如图5-图8所示，在所述第三外延层13内形成阱区、源区15以及沟槽20；
步骤S13：如图9所示，基于所述沟槽20，在所述第二外延层12中进行 离子注入，形成与所述第二外延层12反型的掺杂区17；所述掺杂区17贯穿所述第二外延层12；
步骤S14：如图10所示，在所述沟槽20内形成栅极18。
其中，图10中仅是示出了半导体器件的一个元胞结构。所述半导体器件可以为碳化硅MOSFET器件。实际产品中，所述半导体器件可以具有多个元胞结构。可以根据需求设置元胞数量以及布局方式，本申请实施例对此不作具体限定。
本申请实施例所述制作方法中，所述外延片的制作方法包括：在所述半导体基底10表面依次外延形成所述第一外延层11、所述第二外延层12以及所述第三外延层13；其中，所述第一外延层11与所述第三外延层13的掺杂类型相同，且与所述第二外延层12为反型掺杂。
可以设置所述半导体基底10为n+型掺杂的碳化硅基底，所述第一外延层11以及所述第三外延层13均为n-型掺杂的碳化硅外延层，所述第二外延层12为p型掺杂的碳化硅外延层。如是，p型掺杂的第二外延层12为掩埋层，巧妙的采用具有该掩埋层的外延片，利用栅极8所需的沟槽20，进行离子注入，形成掺杂区17，从而解决了沟槽栅极结构的屏蔽以及碳化硅材料注入工艺的难度。而且所述掺杂区17可以在器件电流通路中形成可以调制的JFET结构，自动调节器件电阻和自锁保护效应的同时还能够具有较小的器件元胞尺寸。
所述半导体器件中，阱区结构包括：第一层阱区141、第二层阱区142和第三层阱区143。所述第二外延层12具有待注入区以及包围所述待注入区的第一层阱区141；所述待注入区用于形成所述掺杂区17。
步骤S12中，在所述第三外延层13内形成阱区、源区15以及沟槽20，包括：
首先，如图5-图7所示，通过离子注入，在所述第三外延层13内依次形成第二层阱区142、第三层阱区143以及源区15；所述第二层阱区142位于所述第一层阱区141与所述第三层阱区143之间，所述源区15位于所述第三层阱区143背离所述第二层阱区142的一侧。
具体的，如图5所示，基于掩膜层01，进行离子注入，在第三外延层13内形成第二层阱区142，第二层阱区142包围一非注入区。基于图形化的所述掩膜层01形成所需的非注入区。沟槽20以及掺杂区17的垂直投影均在该非注入区内，且在平行于所述外延片的方向(即图5-图8的水平方向)上，与该非注入区具有间距。进一步的，如图6所示，再次通过离子注入，在第二层阱区142上形成第三层阱区143，第三层阱区143覆盖第二层阱区142及其包围的非注入区。进一步的，如图7所示，再次通过离子注入，在第三层阱区143上形成源区15。
然后，如图8所示，在所述第三外延层13背离所述第二外延层12的一侧表面内形成所述沟槽20；所述沟槽20的底部位于所述第二外延层12与所述第三层阱区143之间。
其中，所述源区15以及所述第三层阱区143均与所述沟槽20的侧壁接触；通过离子注入形成源区15时，离子注入区覆盖用于形成沟槽20的区域，故后续形成沟槽后，可以使得未被去除的源区15直接和沟槽20的侧壁接触。同样，通过离子注入形成第三层阱区143时，离子注入区覆盖用于形成沟槽20的区 域，故后续形成沟槽后，可以使得未被去除的第三层阱区143直接和沟槽20的侧壁接触。
所述第二层阱区142与所述沟槽20的侧壁具有间距。设置所述第二层阱区142所包围的非注入区的尺寸大于所述沟槽20的尺寸，设置所述沟槽20的垂直投影位于所述非注入区内，且与所述非注入区具有间距，即可以使得所述第二层阱区142与所述沟槽20的侧壁不接触，使得二者之间具有间距。
如图10所示，所述制作方法还包括：
形成与所述源区15连接的金属源极21；
在所述半导体基底10背离所述第一外延层11的一侧表面形成金属漏极19。
所述源区15包括掺杂类型相反的第一区域151和第二区域152，所述源区15与第一区域151和第二区域152均接触。可以设置第一区域151是n+型掺杂区，第二区域152为p+型掺杂区。
本申请实施例所述制作方法形成的碳化硅半导体器件中，阱区结构包括三层，分别为第一层阱区141、第二层阱区142和第三层阱区143。最上层的第三层阱区143位于沟槽20左右两侧，且和沟槽20的侧壁接触。中间层的第二层阱区142包括位于沟槽20左右两侧的两部分，且与沟槽20的侧壁不接触。最下层的第一层阱区141位于沟槽20下方，与沟槽20无接触。
第二层阱区142的左右两部分与元胞结构竖向中轴线之间的距离大于第一层阱区141的左右两部分与元胞结构竖向中轴线之间的距离，具体的，元胞结构竖向中轴线为沟槽20的中轴线，如图10中虚线所示，相对于第二层阱区 142，第一层阱区141更靠近所述中轴线。
可以通过所述掺杂区17可以在源漏极之间的电流路径上形成一个特定的JFET结构，且JFET结构的导通特性，可以通过所述掺杂区17的图形设计和离子注入浓度及图形轮廓进行优化调整，以提高半导体器件的性能。
本申请技术方案通过在外延片中巧妙的涉及第二外延层12以及贯穿第二外延层12的所述掺杂区17，解决了SiC沟槽MOSFET栅氧结构的屏蔽和碳化硅材料中深注入工艺的难题，同时，所述掺杂区17还可以在器件的电流通路上引入了可以通过离子注入调制的JFET结构，在自动调节器件导通电阻和自锁保护效应的同时，还能够保持较小器件元胞尺寸。
通过上述描述可知，基于本申请实施例所述制作方法形成的碳化硅半导体器件至少具有如下有益效果：
所述碳化硅半导体器件能够在元胞结构的电流通路上引入一JFET结构，自动调节器件导通电阻和自锁保护效应的同时还能够保持较小器件元胞尺寸，并且JFET结构的导通特性由所述掺杂区17的图形设计和离子注入浓度及图形轮廓进行优化调整，设计和工艺灵活，具有较好的可制造性。
利用具有掩埋层(第二外延层12)的外延片和由所述掺杂区17注入调制的JFET结构，在大的浪涌电压下可以自动扩展两侧的耗尽区从而增大JFET结构的导通电阻，相当于一个缓冲器电路结构自行抑制浪涌尖峰；同时在浪涌电压过大时，两侧耗尽区域继续扩展而相互重叠，起到封锁效应，保护内部的沟槽表面的栅极介质层，起到一定的尖峰电压过压保护作用。
虽然在引入JFET结构会增加一定的导通电阻，却具有了开关缓冲和浪涌电压自抑制效果。
所述碳化硅半导体器件能增加器件对于浪涌电压和过电压的自抑制抗性，避免过压保护电路和过流保护电路由于实际作用上的时延造成的器件损坏和可靠性的减损。
同时也对电路开关过程中的尖峰抖动起到缓冲作用，减小开关损耗；可以减少电路设计中的缓冲电路及缓冲器电路结构，减少离散性的元器件，从而降低成本，也减少了实际模块体积，增强可靠性。
基于上述实施例，本申请另一实施例还提供了一种碳化硅半导体器件，可以采用上述实施例所述制作方法制备所述碳化硅半导体器件，其结构可以如图10所示，包括：
外延片，所述外延片包括：半导体基底10；设置在所述半导体基底10表面的第一外延层11；设置在所述第一外延层11背离所述半导体基底10一侧表面的第二外延层12；设置在所述第二外延层12背离所述第一外延层11一侧表面的第三外延层13；
设置在所述第三外延层内的阱区、源区15以及沟槽；
贯穿所述第二外延层12的掺杂区17，所述掺杂区17与所述第二外延层为反型掺杂，基于所述沟槽通过离子注入形成；
设置在所述沟槽内的栅极18。栅极18包括填充沟槽的填充介质以及位于填充介质表面的金属栅极。所述沟槽表面具有栅极介质层，形成栅极介质层后，在所述沟槽内形成栅极18。填充介质可以为多晶硅等。在所述沟槽内形成栅 极介质层前，形成掺杂区17。
其中，所述第二外延层12具有待注入区以及包围所述待注入区的第一层阱区141；所述第三外延层13内具有第二层阱区142、第三层阱区142以及所述源区15；所述第二层阱区142位于所述第一层阱区141与所述第三层阱区143之间，所述源区15位于所述第三层阱区143背离所述第二层阱区142的一侧；所述源区15以及所述第三层阱区143均与所述沟槽的侧壁接触；所述沟槽的底部位于所述第二外延层12与所述第三层阱区143之间；所述第二层阱区142位于所述沟槽的两侧，与所述沟槽的侧壁具有间距。
所述碳化硅半导体器件中，所述第三外延层13的厚度不超过1μm，这样第二层阱区142和第三层阱区143的离子注入深度均不超过1μm，能够通过离子注入在碳化硅材料的第三外延层13内形成第二层阱区142和第三层阱区143，且不造成晶格损伤。
本申请实施例中，所述沟槽的底部与所述第一外延层11的距离小于1μm，以使得基于沟槽进行离子注入形成掺杂区17时，使得掺杂区17的离子注入深度小于1μm，，能够通过离子注入在碳化硅材料的第二外延层12内形成掺杂区17，且不造成晶格损伤。掺杂区17和沟槽底部具有非零间距。
可选的，在所述沟槽的底部指向开口的方向(图10中由下至上的方向)上，所述沟槽的宽度满足均匀条件，即所述沟槽的宽度在该方向上均相同或是近似相同，也就是说，所述沟槽为矩形沟槽。一般的第二外延层12为厚度均匀的外延层，设置所述沟槽的宽度满足均匀条件，便于形成在所述方向上宽度均匀的掺杂区17。
其他方式中，所述电子设备的结构还可以如图11所示，图11为本申请实施例提供的一种碳化硅半导体器件的结构示意图，该方式与图10所示结构不同在于，在所述沟槽的底部指向开口的方向上，所述沟槽的宽度逐渐增大，即所述沟槽为V型槽或是倒梯形槽。如果是V型沟槽，掺杂区17为V型结构，如果为倒梯形沟槽，在离子注入窗口大于沟槽底部时，掺杂区如图11所示为倒梯形结构，如果离子注入窗口不大于沟槽底部，掺杂区为矩形结构。
本申请实施例中，所述掺杂区17的宽度不大于所述沟槽的宽度，以便于能够基于所述沟槽进行离子注入形成所述掺杂区17，以降低离子注入的深度，
所述掺杂区17、所述第一外延层11与所述第三外延层13的掺杂类型相同。
所述碳化硅半导体器件为NMOS。所述半导体基底10为n+型基底，所述第一外延层11与所述第三外延层13均为n-型掺杂，所述第二外延层12为p-型掺杂，所述掺杂区17为n型掺杂。本申请实施例中，掺杂浓度大小关系为n+＞n＞n-，p+＞p＞p-。n-、n和n+为同型掺杂，都是第一类型掺杂。p-、p和p+为同型掺杂，都是第二类型掺杂。第一类型掺杂与第二类型掺杂为反型掺杂。
显然，所述碳化硅半导体器件还可以为PMOS。可以基于需求设置掺杂类型，以形成NMOS或是PMOS。
所述掺杂区17的掺杂浓度大于所述第一外延层11与所述第三外延层13的掺杂浓度。所述掺杂区17为n+型掺杂。
如图12所示，图12为图10所示碳化硅半导体器件在开通瞬间的主要电流通 路示意，源漏极之间具有电流通路，图12所示中间虚线曲线表示电路通路，电流通过经过基于掺杂区17形成的JFET结构。由于电流迅速变化，在电路中产生高频尖峰电压，而与此同时由于电流通路上电压迅速变化，JFET结构的耗尽区域(图12中左右两条虚线曲线之间的区域)对应不同的电压变化情况，会迅速扩展或是收缩，JFET结构此时等效为一个可变电阻R和一个结电容C的并联结构，如图13所示，图13为图12所示碳化硅半导体器件等效寄生参数示意图。
通过具体的电路应用及器件电学模型模拟，选取合适的第二外延层12厚度d以及掺杂浓度，以及掺杂区17离子注入结构的图形设计和浓度及图形轮廓设计来优化调整，就可以得到合适的寄生参数值(所需的可变电阻R和一个结电容C)，对实际应用于不同开关频率电路模块中时，起到有效的电压尖峰抑制作用，同时减小开通损耗。
本申请实施例中仅是以单个元胞结构对碳化硅半导体器件进行说明。显然在制作所述半导体器件时可以基于晶圆级工艺同时制作多个元胞结构，然后分割晶圆形成所述碳化硅半导体器件，所述碳化硅半导体器件具有多个元胞结构。
如图14所示，图14为本申请实施例提供的一种碳化硅半导体器件在沟槽设计与掺杂区离子注入面积的版图，掺杂区17的注入窗口位于沟槽20内，JFET结构的通道特性，可以由掺杂区17的图形设计、离子注入浓度以及图形轮廓设计进行调整。掺杂区17的注入窗口面积可以小于或是等于沟槽20的面积。
本说明书中各个实施例采用递进、或并列、或递进和并列结合的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
需要说明的是，在本申请的描述中，需要理解的是，术语“上”、“下”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。当一个组件被认为是“连接”另一个组件，它可以是直接连接到另一个组件或者可能同时存在居中设置的组件。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种碳化硅半导体器件的制作方法，其特征在于，包括：
    提供一外延片，所述外延片包括：半导体基底；设置在所述半导体基底表面的第一外延层；设置在所述第一外延层背离所述半导体基底一侧表面的第二外延层；设置在所述第二外延层背离所述第一外延层一侧表面的第三外延层；
    在所述第三外延层内形成阱区、源区以及沟槽；
    基于所述沟槽，在所述第二外延层中进行离子注入，形成与所述第二外延层反型的掺杂区；所述掺杂区贯穿所述第二外延层；
    在所述沟槽内形成栅极。
  2. 根据权利要求1所述的制作方法，其特征在于，所述第二外延层具有待注入区以及包围所述待注入区的第一层阱区；
    在所述第三外延层内形成阱区、源区以及沟槽，包括：
    通过离子注入，在所述第三外延层内依次形成第二层阱区、第三层阱区以及源区；所述第二层阱区位于所述第一层阱区与所述第三层阱区之间，所述源区位于所述第三层阱区背离所述第二层阱区的一侧；
    在所述第三外延层背离所述第二外延层的一侧表面内形成所述沟槽；所述沟槽的底部位于所述第二外延层与所述第三层阱区之间；
    其中，所述源区以及所述第三层阱区均与所述沟槽的侧壁接触；所述第二层阱区与所述沟槽的侧壁具有间距。
  3. 根据权利要求1所述的制作方法，其特征在于，所述外延片的制作方法包括：
    在所述半导体基底表面依次外延形成所述第一外延层、所述第二外延层以及所述第三外延层；
    其中，所述第一外延层与所述第三外延层的掺杂类型相同，且与所述第二外延层为反型掺杂。
  4. 根据权利要求1-3任一项所述的制作方法，其特征在于，还包括：
    形成与所述源区连接的金属源极；
    在所述半导体基底背离所述第一外延层的一侧表面形成金属漏极。
  5. 一种如权利要求1-4任一项所述制作方法制备的碳化硅半导体器件，其特征在于，包括：
    外延片，所述外延片包括：半导体基底；设置在所述半导体基底表面的第一外延层；设置在所述第一外延层背离所述半导体基底一侧表面的第二外延层；设置在所述第二外延层背离所述第一外延层一侧表面的第三外延层；
    设置在所述第三外延层内的阱区、源区以及沟槽；
    贯穿所述第二外延层的掺杂区，所述掺杂区所述第二外延层为反型掺杂，基于所述沟槽通过离子注入形成；
    设置在所述沟槽内的栅极。
  6. 根据权利要求5所述的碳化硅半导体器件，其特征在于，所述第二外延层具有待注入区以及包围所述待注入区的第一层阱区；所述第三外延层内具 有第二层阱区、第三层阱区以及所述源区；所述第二层阱区位于所述第一层阱区与所述第三层阱区之间，所述源区位于所述第三层阱区背离所述第二层阱区的一侧；所述源区以及所述第三层阱区均与所述沟槽的侧壁接触；所述第二层阱区与所述沟槽的侧壁具有间距；所述沟槽位于所述第三外延层背离所述半导体基底的一侧表面内；所述沟槽的底部位于所述第二外延层与所述第三层阱区之间；
    所述第三外延层的厚度不超过1μm；所述沟槽的底部与所述第一外延层的距离小于1μm。
  7. 根据权利要求5所述的碳化硅半导体器件，其特征在于，在所述沟槽的底部指向开口的方向上，所述沟槽的宽度满足均匀条件。
  8. 根据权利要求5所述的碳化硅半导体器件，其特征在于，在所述沟槽的底部指向开口的方向上，所述沟槽的宽度逐渐增大。
  9. 根据权利要求5所述的碳化硅半导体器件，其特征在于，所述掺杂区的宽度不大于所述沟槽的宽度。
  10. 根据权利要求5所述的碳化硅半导体器件，其特征在于，所述掺杂区、所述第一外延层与所述第三外延层的掺杂类型相同；
    所述掺杂区的掺杂浓度大于所述第一外延层与所述第三外延层的掺杂浓度。
PCT/CN2022/125793 2021-11-17 2022-10-18 碳化硅半导体器件及其制作方法 Ceased WO2023088013A1 (zh)

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