WO2023093604A1 - 太阳能电池以及太阳能电池的制备方法 - Google Patents

太阳能电池以及太阳能电池的制备方法 Download PDF

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WO2023093604A1
WO2023093604A1 PCT/CN2022/132504 CN2022132504W WO2023093604A1 WO 2023093604 A1 WO2023093604 A1 WO 2023093604A1 CN 2022132504 W CN2022132504 W CN 2022132504W WO 2023093604 A1 WO2023093604 A1 WO 2023093604A1
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solar cell
silicon substrate
layer
reflection film
passivation
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French (fr)
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蒋秀林
陈斌
段光亮
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JA Solar Technology Yangzhou Co Ltd
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JA Solar Technology Yangzhou Co Ltd
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Priority to EP22897687.4A priority patent/EP4407695A4/en
Publication of WO2023093604A1 publication Critical patent/WO2023093604A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H10F77/315—Coatings for devices having potential barriers for photovoltaic cells the coatings being antireflective or having enhancing optical properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/129—Passivating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/215—Geometries of grid contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates to a solar cell and a method for preparing the solar cell.
  • PERC Passivated Emitter and Rear Cell, Passivated Emitter and Rear Cell
  • solar cells are passivated with a silicon oxide layer on the back surface of the silicon substrate, with local openings to achieve point contact to reduce the area of the non-passivated area, through local metal contact , greatly reducing the recombination speed of the back surface, while improving the light reflection of the back surface and improving the conversion efficiency of the solar cell.
  • Passivated contact solar cells (such as TOPCon (Tunnel Oxide Passivated Contact, tunneling oxidation passivated contact) solar cells) adopt a passivated contact structure composed of a tunneling silicon oxide layer and a doped polysilicon layer, which can effectively reduce surface recombination. Composite with metal contacts to improve the conversion efficiency of the battery.
  • silver metal has the advantages of good conductivity, low work function, good solderability, and not easy to form deep level defects in silicon, whether it is PERC solar cells or passivated contact solar cells
  • silver paste is used to realize metallization .
  • the production cost of solar cells is relatively high; at the same time, since it is often necessary to corrode part of the silicon through the glass frit in the silver paste to form an ohmic contact, the junction depth requirements for diffusion Deeper, if it is used to passivate contact cells, a thicker polysilicon layer is required.
  • the technical problem to be solved in the present disclosure is to provide a solar cell and a method for preparing the solar cell.
  • the present disclosure provides a method for preparing a solar cell, comprising:
  • Step 101 sequentially forming a tunneling silicon oxide layer, an N-type doped polysilicon layer, and a passivation anti-reflection film on the back of the N-type silicon substrate;
  • Step 102 groove the passivation anti-reflection film on the back surface, and form a nickel metal layer in the grooved area;
  • Step 103 printing back fine grid electrodes on the nickel metal layer, and printing rear main grid electrodes on the rear passivation antireflection film, wherein the rear fine grid electrodes are electrically connected to the rear main grid electrodes.
  • step 103 includes:
  • Step 3-1 printing the back fine grid electrode on the nickel metal layer, and performing the first drying treatment, wherein the temperature of the first drying treatment is 100-300°C;
  • Step 3-2 printing the rear main gate electrode on the rear passivation anti-reflection film, and performing a second drying treatment, wherein the temperature of the second drying treatment is 100-250° C.
  • the back fine grid electrode is made of aluminum metal, and the back bus grid electrode is made of silver metal.
  • step 101 before step 101, it also includes:
  • the back surface of the N-type silicon substrate is sequentially subjected to texturing treatment and polishing treatment.
  • step 101 includes:
  • Step 1-1 forming a tunnel silicon oxide layer on the back side of the N-type silicon substrate
  • Step 1-2 forming an intrinsic polysilicon layer on the tunneling silicon oxide layer
  • Step 1-3 performing N-type doping on the intrinsic polysilicon layer to form an N-type doped polysilicon layer
  • Steps 1-4 forming a rear passivation anti-reflection film on the N-type doped polysilicon layer.
  • the method further includes:
  • Step 104 performing boron diffusion treatment on the front side of the N-type silicon substrate to form a P+ emitter
  • Step 105 forming a front passivation anti-reflection film on the front side of the N-type silicon substrate, and the front passivation anti-reflection film covers the P+ emitter;
  • Step 106 printing front metal electrodes on the front passivation anti-reflection film.
  • step 104 further include:
  • the rear passivation antireflection film includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride
  • the front passivation antireflection film Including at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.
  • step 102 includes:
  • Step 2-1 slotting the passivation anti-reflection film on the back side, and forming a nickel metal layer in the slotting area;
  • Step 2-2 performing a first annealing treatment on the nickel metal layer, forming a nickel-silicon alloy layer between the nickel metal layer and the N-type doped polysilicon layer; wherein, the temperature of the annealing treatment is 200-400° C., and the annealing treatment time is 10s ⁇ 300s.
  • an embodiment of the present disclosure provides a solar cell, which is prepared by using the preparation method provided in the first aspect above.
  • FIG. 1 is a schematic flow diagram of a method for preparing a solar cell according to the present disclosure
  • Fig. 2 shows the structural diagram of the solar cell after the front metal electrode is prepared
  • Fig. 3 shows the structural diagram of the solar cell after grooved on the back passivation anti-reflection film
  • Fig. 4 shows the structural diagram of the solar cell after forming the nickel metal layer
  • Figure 5 shows the pattern of the back fine grid electrode
  • Figure 6 shows a schematic diagram of the solar cell after forming the back fine grid electrode and the back main grid electrode
  • Figure 7 shows the back fine grid electrode and the pattern of the rear fine grid electrode
  • FIG. 8 is a schematic flow chart of yet another method for fabricating a solar cell according to the present disclosure.
  • 1-N-type silicon substrate 2-tunneling silicon oxide layer; 3-intrinsic polysilicon layer; 4-N-type doped polysilicon layer; 5-back passivation anti-reflection film; 6-nickel metal layer; 7-back Metal electrode; 7a-back fine grid electrode; 7b-back main grid electrode; 8-P+ emitter; 9-front passivation anti-reflection film; 10-front metal electrode.
  • ohmic contact refers to the contact between metal and semiconductor, and the resistance value of the contact surface is much smaller than the resistance of the semiconductor itself, so that when the component operates, most of the voltage drop is in the active area instead of the contact surface.
  • the ohmic contact refers to the ohmic contact between the back fine gate electrode and the N-type doped polysilicon layer.
  • the glass body in the silver paste easily penetrates through the thinner polysilicon layer. Therefore, in the existing method, a thicker polysilicon film is required, which increases the manufacturing cost of the solar cell. It also increases parasitic light absorption and reduces light utilization efficiency.
  • FIG. 1 is a schematic diagram of the main flow of a solar cell manufacturing method.
  • the preparation method of the solar cell may include the following steps:
  • Step 101 sequentially forming a tunneling silicon oxide layer 2, an N-type doped polysilicon layer 4 and a rear passivation anti-reflection film 5 on the back of the N-type silicon substrate 1;
  • Step 102 groove the passivation anti-reflection film 5 on the back surface, and form a nickel metal layer 6 in the grooved area;
  • Step 103 printing the back fine grid electrode 7 a on the nickel metal layer 6 , and printing the rear main grid electrode 7 b on the rear passivation antireflection film 5 , wherein the rear fine grid electrode 7 a is electrically connected to the rear main gate electrode 7 b.
  • the front side of the N-type silicon substrate 1 refers to the side of the N-type silicon substrate facing sunlight after the N-type silicon substrate is used to make a solar cell, that is, the light-receiving side of the N-type silicon substrate that is irradiated by sunlight.
  • the back side of the N-type silicon substrate 1 refers to the side facing away from sunlight, that is, the backlight side opposite to the light-receiving side of the N-type silicon substrate 1 .
  • the back surface of the N-type silicon substrate 1 is sequentially subjected to texturing treatment and polishing treatment. Specifically, after the texturing process, a pyramid-like structure or a honeycomb-like structure is formed on the back surface of the N-type silicon substrate 1 .
  • texturing is the process of pre-cleaning the surface of the silicon substrate and corroding it into a pyramid-like or honeycomb-like structure with strong alkali or strong acid.
  • the purpose of texturing can not only reduce the reflectivity of the surface and remove the damaged layer, but also form a light trap (anti-reflection texture) inside the battery, using the light trapping principle to increase the effective length of light moving in the silicon substrate , which is conducive to the absorption of light by the silicon substrate, thereby improving the conversion efficiency of solar cells.
  • the polishing treatment is performed on the back surface of the N-type silicon substrate 1 .
  • the polishing treatment is to smooth the pyramid-like structure or honeycomb-like structure formed after the back of the N-type silicon substrate 1 is textured, so as to promote the passivation of the crystalline silicon surface on the back of the N-type silicon substrate 1, thereby improving battery efficiency.
  • the front surface of the N-type silicon substrate 1 can also be textured.
  • the above method further includes:
  • Step 104 performing boron diffusion treatment on the front side of the N-type silicon substrate 1 to form a p-n junction to obtain a P+ emitter 8 .
  • a specific embodiment may include: after texturing the front side of the N-type silicon substrate 1 , performing boron diffusion treatment on the front side of the N-type silicon substrate 1 to form a p-n junction to obtain a P+ emitter 8 . Due to the winding plating phenomenon in this process, part of the p-n junction and borosilicate glass will be formed on the back side of the N-type silicon substrate 1, so after forming the P+ emitter 8 on the front side of the N-type silicon substrate 1, it is necessary to use The HF solution removes the p-n junction and borosilicate glass on the back side of the N-type silicon substrate 1 .
  • the specific implementation may include:
  • a tunnel silicon oxide layer 2 is formed on the back surface of the N-type silicon substrate 1 .
  • the thickness of the tunneling silicon oxide layer 2 is any one of 1-2 nm, for example, 1.0 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2.0 nm. Based on the quantum tunneling effect, since the thickness of the tunneling silicon oxide layer is relatively thin, carriers in the silicon substrate can pass through the layer and be collected.
  • high temperature thermal oxidation, nitric acid oxidation, ozone oxidation or CVD (chemical vapor deposition) method can be used to form the tunnel silicon oxide layer 2; specifically, when high temperature thermal oxidation is used on the N-type silicon substrate
  • the deposition temperature is 500-700°C.
  • a tunneling silicon oxide layer 2 is simultaneously formed on the P+ emitter 8 formed on the front side of the N-type silicon substrate 1, so as to facilitate subsequent formation of an N-type doped polysilicon layer on the back side of the N-type silicon substrate 1 4, to avoid contamination of the positive P+ emitter.
  • an intrinsic polysilicon layer 3 is formed on the tunneling silicon oxide layer 2 .
  • the intrinsic polysilicon layer 3 can be formed by LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition) or PVD (Physical Vapor Deposition, physical vapor deposition).
  • the thickness of the intrinsic polysilicon layer 3 is any one of 120-200 nm, for example, 120 nm, 150 nm, 180 nm, 200 nm.
  • the thickness of the intrinsic polysilicon layer 3 is any one of 80-150 nm.
  • the thinner polysilicon layer can not only reduce the consumption of the deposition process, thereby reducing the cost, but also reduce the parasitic light absorption of the polysilicon layer, thereby improving the utilization efficiency of light.
  • an intrinsic polysilicon layer 3 is formed on the front surface of the N-type silicon substrate 1 .
  • N-type doping is performed on the intrinsic polysilicon layer 3 on the back side of the N-type silicon substrate 1 to form an N-type doped polysilicon layer 4.
  • N-type doping treatment can be performed on the intrinsic polysilicon layer 3 by means of ion implantation, so as to form the N-type doped polysilicon layer 4 .
  • N-type doping includes, for example, phosphorus doping; the silicon wafer can also be placed in a phosphorus diffusion furnace tube for phosphorus diffusion at a diffusion temperature of 700-900° C. to form an N-type doped polysilicon layer 4 on the back.
  • the passivation contact structure composed of the tunneling silicon oxide layer 2 and the N-type doped polysilicon layer 4, the surface recombination and metal contact recombination can be effectively reduced while ensuring the passage of carriers, and the conversion efficiency of the battery can be improved.
  • the front side of the N-type silicon substrate 1 is cleaned by wrap-around plating, and the intrinsic polysilicon formed on the front side is removed by using a strong alkali solution. layer; tunneling silicon oxide layer 2; and then using HF solution to remove the front tunneling silicon oxide layer 2 and borosilicate glass, wherein the strong alkali solution can be potassium hydroxide solution or sodium hydroxide solution.
  • the borosilicate glass on the front side is produced during the boron diffusion process on the front side of the N-type silicon substrate 1 .
  • a rear passivation antireflection film 5 is formed on the N-type doped polysilicon layer 4 .
  • the rear passivation antireflection film 5 includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.
  • the above method further includes:
  • Step 105 forming a front passivation antireflection film 9 on the front surface of the N-type silicon substrate 1 , and the front passivation antireflection film 9 covers the P+ emitter 8 .
  • the front passivation anti-reflection film 9 and the back passivation anti-reflection film 5 can be formed simultaneously.
  • the front passivation antireflection film 9 includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.
  • Step 106 printing the front metal electrode 10 on the front passivation anti-reflection film 9 .
  • FIG. 2 shows a structural view of the solar cell after the front metal electrode is prepared.
  • the specific implementation manner may include:
  • step 2-1 grooves are made on the passivation anti-reflection film 5 on the back surface, and a nickel metal layer 6 is formed in the grooved area.
  • FIG. 3 shows the structure diagram of the solar cell after grooves are made on the passivation anti-reflection film on the back;
  • FIG. 4 shows the structure diagram of the solar cell after the nickel metal layer is formed.
  • Step 2-2 performing a first annealing treatment on the nickel metal layer 6 to form a nickel-silicon alloy layer between the nickel metal layer 6 and the N-type doped polysilicon layer 4; wherein, the temperature of the annealing treatment is 200-400° C.
  • the processing time is from 10s to 300s.
  • step 102 nickel and silicon are used to form a nickel-silicon alloy layer to enhance the bonding force between the metal grid line and silicon, which helps to ensure that the N-type doped polysilicon layer is not damaged during the subsequent preparation of the metal electrode by printing the paste, To ensure the passivation effect of the passivation contact structure.
  • step 2-1 specific implementation methods may include:
  • an ultraviolet picosecond laser with a wavelength of 355nm to make grooves on the back passivation anti-reflection film 5
  • use inkjet technology inkjet printing technology
  • electroplating technology to inkjet the conductive nickel paste in the grooved area
  • a nickel metal layer 6 is formed inside, and then annealing is performed, and a nickel-silicon alloy layer is formed between the nickel metal layer 6 and the N-type doped polysilicon layer 4 during the annealing process.
  • the formed nickel-silicon alloy layer can increase the bonding force between metal grid lines and silicon
  • the annealing temperature is 200-400°C
  • the annealing time is 10s-300s; in a preferred embodiment, the annealing temperature is 250-350°C, The annealing time is 30s-120s, and the thickness of the nickel-silicon alloy layer is 10-30nm.
  • the ultraviolet picosecond laser is used to slot the passivated anti-reflection film 5 on the back side, which effectively reduces the damage to the passivated anti-reflection film 5 on the back side during the slotting process.
  • the specific implementation may include:
  • Step 3-1 printing the back fine grid electrode 7a on the nickel metal layer 6, and performing a first drying treatment, wherein the temperature of the first drying treatment is 100-300°C;
  • Step 3-2 printing the rear main grid electrode 7b on the rear passivation anti-reflection film 5, and performing a second drying treatment, so that the rear main grid electrode 7b is electrically connected to the rear fine grid electrode 7a, wherein the second baking
  • the temperature of the dry treatment is 100-250°C.
  • the back fine gate electrode 7a is made of aluminum metal
  • the back main gate electrode 7b is made of silver metal.
  • FIG. 5 shows the pattern of the rear fine-grid electrode
  • Fig. 6 shows a schematic diagram of the solar cell after forming the back metal electrode (including the back fine grid electrode and the back main grid electrode);
  • Fig. 7 shows the pattern of the back fine grid electrode and the back fine grid electrode.
  • a tunneling silicon oxide layer, an N-type doped polysilicon layer, and a passivation anti-reflection film are sequentially formed on the back of an N-type silicon substrate; Grooves are made on the anti-reflective film, and a nickel metal layer is formed in the grooved area; then, the back fine grid electrode is printed on the nickel metal layer, and the back main grid electrode is printed on the back passivation anti-reflection film, wherein the back fine grid electrode is connected with the back main grid electrode.
  • the gate electrode forms an electrical connection, so as to ensure the bonding force between the metal gate line and silicon, avoid the damage of the paste to the thin polysilicon layer during use, and ensure the passivation effect of the passivation contact structure.
  • the manufacturing cost of the solar cell is reduced, the parasitic light absorption is reduced, the utilization efficiency of light is improved, and the efficiency of the solar cell is improved.
  • aluminum metal is used for the back fine grid electrode, which also reduces the silver consumption required for preparing the back metal electrode, and effectively reduces the preparation cost of the solar cell.
  • the embodiment of the present disclosure also provides a method for preparing a solar cell.
  • the preparation method of the solar cell may include the following steps:
  • Step 201 performing boron diffusion treatment on the front side of the N-type silicon substrate 1 to form a P+ emitter 8;
  • Step 202 sequentially forming a tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 4 on the back side of the N-type silicon substrate 1;
  • Step 203 forming a front passivation anti-reflection film 9 and a back passivation anti-reflection film 5 on the front and back of the N-type silicon substrate 1 respectively; the front passivation anti-reflection film 9 covers the P+ emitter 8;
  • Step 204 printing the front metal electrode 10 on the front passivation anti-reflection film 9;
  • Step 205 groove the passivation anti-reflection film 5 on the back surface, and form a nickel metal layer 6 in the grooved area;
  • Step 206 printing the rear fine grid electrode 7 a on the nickel metal layer 6 , and printing the rear main grid electrode 7 b on the rear passivation antireflection film 5 , wherein the rear fine grid electrode 7 a is electrically connected to the rear main gate electrode 7 b.
  • step 201 further includes: performing texturing treatment on the front and back sides of the N-type silicon substrate 1 , and performing polishing treatment on the back side of the N-type silicon substrate 1 .
  • step 201 after forming the P+ emitter 8 on the front side of the N-type silicon substrate 1 in step 201, it is necessary to use HF solution to remove the p-n junction and borosilicate glass on the back side of the N-type silicon substrate 1 .
  • the tunneling silicon oxide layer 2 and the intrinsic polysilicon layer 3 are formed on the back side of the N-type silicon substrate 1, the tunneling silicon oxide layer 2 and the intrinsic polysilicon layer 3 are also formed on the front side of the N-type silicon substrate 1.
  • Intrinsic polysilicon layer 3 in a preferred embodiment, before step 203, sodium hydroxide solution or potassium hydroxide solution is used to remove the intrinsic polysilicon layer 3 formed on the front side of the N-type silicon substrate 1, and HF solution is used to remove the intrinsic polysilicon layer 3 formed on the front side. Tunneling through silicon oxide layers and borosilicate glass.
  • the solar cell includes: an N-type silicon substrate 1, a tunneling silicon oxide layer 2, an N-type doped polysilicon layer 4, and a rear passivation anti-reflection film 5 arranged sequentially from top to bottom; wherein,
  • a nickel metal layer 6 is formed in the grooved area of the back passivation antireflection film 5, and a back fine gate electrode 7a and a back main gate electrode 7b are formed on the nickel metal layer 6, wherein the back fine gate electrode 7a and the back main gate electrode 7b forms an electrical connection.
  • the front side of the N-type silicon substrate 1 of the solar cell is further provided with a P+ emitter 8, a front passivation anti-reflection film 9 and a front metal electrode 10 in sequence.
  • the material of the back fine grid electrode 7 a is aluminum metal; the material of the rear fine grid electrode 7 a is silver metal.
  • Step A1 providing an N-type silicon substrate 1 , performing texturing treatment on the front and back sides of the N-type silicon substrate 1 , and performing polishing treatment on the back side of the N-type silicon substrate 1 .
  • Step B1 performing boron diffusion treatment on the front side of the N-type silicon substrate 1 to form a P+ emitter 8 .
  • Step C1 removing the p-n junction and borosilicate glass on the back of the N-type silicon substrate 1 by using HF acid solution.
  • Step D1 Form a tunneling silicon oxide layer 2 with a thickness of 1-2 nm on the back surface of the N-type silicon substrate 1 by high temperature thermal oxidation.
  • Step E1 forming an intrinsic polysilicon layer 3 on the tunneling silicon oxide layer 2 on the back side of the N-type silicon substrate 1 by LPCVD/PVD.
  • Step F1 doping the intrinsic polysilicon layer 3 on the back side with phosphorus by ion implantation, and performing annealing to form an N-type doped polysilicon layer 4, wherein the N-type doped polysilicon layer has a thickness of Between 80 and 200nm.
  • Step G1 removing the borosilicate glass on the front side of the N-type silicon substrate 1 by HF acid solution.
  • Step H1 forming a front passivation anti-reflection film 9 on the front side of the N-type silicon substrate 1 , and forming a back passivation anti-reflection film 5 on the back side of the N-type silicon substrate 1 .
  • the front passivation anti-reflection film and the back passivation anti-reflection film are at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.
  • Step I1 Prepare the front metal electrode 10 on the front passivation anti-reflection film 9 .
  • Step J1 Groove the rear passivation anti-reflection film 5 by using an ultraviolet picosecond laser with a wavelength of 355nm to obtain the structure shown in Figure 3, and then form a nickel metal layer 6 in the grooved area to obtain the structure shown in Figure 4 Structure.
  • Step K1 Perform the first annealing treatment on the nickel metal layer 6, and form a nickel-silicon alloy layer between the nickel metal layer 6 and the N-type doped polysilicon layer 4; wherein, the temperature of the annealing treatment is 200-400° C. The time ranges from 10s to 300s.
  • Step L1 printing aluminum paste on the nickel metal layer 6, and performing drying treatment in the range of 100-300° C. to prepare the rear fine grid electrode 7a;
  • Step M1 Printing silver paste on the back passivation anti-reflection film 5, and drying it in the range of 100-250°C to prepare the back main gate electrode 7b, and obtain the structure shown in Figure 6. Among them, the back main gate electrode 7b is obtained.
  • the gate electrode 7b is electrically connected to the rear fine gate electrode 7a.
  • Step A2-C2 consistent with step A1-C1 provided in Example 1.
  • Step D2 Form a tunneling silicon oxide layer 2 with a thickness of 1-2 nm on the back and front of the N-type silicon substrate 1 by high temperature thermal oxidation method.
  • Step E2 forming an intrinsic polysilicon layer 3 on the back and front tunnel silicon oxide layers 2 of the N-type silicon substrate 1 by LPCVD/PVD.
  • Step F2 doping the intrinsic polysilicon layer 3 on the back side with phosphorus by ion implantation, and performing annealing to form an N-type doped polysilicon layer 4, wherein the N-type doped polysilicon layer has a thickness of 80- Between 200nm.
  • Step G2 removing the intrinsic polysilicon layer 3 on the front side of the N-type silicon substrate 1 with potassium hydroxide solution or sodium hydroxide solution, and then removing the tunneling silicon oxide layer 2 and borosilicate glass on the front side with HF acid solution.
  • Step H2 forming a front passivation antireflection film 9 on the front surface of the N-type silicon substrate 1 , and forming a rear passivation antireflection film 5 on the back surface of the N-type silicon substrate 1 .
  • the front passivation anti-reflection film and the back passivation anti-reflection film are at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.
  • Step I2 Prepare the front metal electrode 10 on the front passivation anti-reflection film 9 .
  • Step J2 Use an ultraviolet picosecond laser with a wavelength of 355nm to groove the passivation anti-reflection film 5 on the back to obtain the structure shown in Figure 3, and then form a nickel metal layer 6 in the grooved area to obtain the structure shown in Figure 4 Structure.
  • Step K2 Perform the first annealing treatment on the nickel metal layer 6, and form a nickel-silicon alloy layer between the nickel metal layer 6 and the N-type doped polysilicon layer 4; wherein, the temperature of the annealing treatment is 200-400° C. The time ranges from 10s to 300s.
  • Step L2 printing aluminum paste on the nickel metal layer 6, and performing drying treatment in the range of 100-300° C. to prepare the rear fine grid electrode 7a;
  • Step M2 Printing silver paste on the back passivation anti-reflection film 5, and drying it in the range of 100-250°C to prepare the back main gate electrode 7b, and obtain the structure shown in Figure 6. Among them, the back main gate electrode 7b is obtained.
  • the gate electrode 7b is electrically connected to the rear fine gate electrode 7a.
  • step D3 nitric acid oxidation is used to form a tunneling silicon oxide layer 2 with a thickness of 1-2 nm on the back and front of the N-type silicon substrate 1. .
  • step F4 the silicon wafer is placed in the phosphorus diffusion furnace tube to carry out phosphorus diffusion.
  • the diffusion temperature is 700-900° C. heteropolysilicon layer (4).

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Abstract

本申请公开了一种太阳能电池以及太阳能电池的制备方法。该太阳能电池的制备方法包括：在N型硅衬底的背面依次形成隧穿氧化硅层、N型掺杂多晶硅层和背面钝化减反膜；在背面钝化减反膜上开槽，在开槽区域形成镍金属层；在镍金属层上印刷背面细栅电极，在背面钝化减反膜上印刷背面主栅电极，其中，背面细栅电极与背面主栅电极形成电连接。

Description

太阳能电池以及太阳能电池的制备方法
相关申请的交叉引用
本申请要求享有2021年11月23日提交的发明名称为“一种太阳能电池以及太阳能电池的制备方法”的中国专利申请202111396218.X的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分或全部。
技术领域
本公开涉及一种太阳能电池以及太阳能电池的制备方法。
背景技术
PERC(Passivated Emitterand Rear Cell，钝化发射极背面接触技术)太阳能电池在硅衬底的背表面采用氧化硅层钝化，局部开孔实现点接触以减少非钝化区域的面积，通过局部金属接触，大大降低了背表面的复合速度，同时提升了背表面的光反射，提高了太阳能电池的转换效率。钝化接触太阳能电池(如TOPCon(Tunnel Oxide Passivated Contact，隧穿氧化钝化接触)太阳能电池)中采用了由隧穿氧化硅层和掺杂多晶硅层组成的钝化接触结构，可以有效降低表面复合和金属接触复合，提高电池的转换效率。
由于银金属具备导电性好、功函数低、可焊性好、不易在硅中形成深能级缺陷等优点，无论是PERC太阳能电池，还是钝化接触太阳能电池，均使用银浆来实现金属化。但，由于银在地壳中含量低，价格比较高，导致太阳能电池的制作成本偏高；同时，由于常需要通过银浆中的玻璃料腐蚀部分硅来形成欧姆接触，因此对扩散的结深要求比较深，如果用于钝化接触电池，则要求较厚的多晶硅层。若采用铝浆替代银浆以降低成本，铝浆中的玻璃料在高温条件下与硅进行反应时，也难以保证不破坏薄的多晶硅层。而较厚的多晶硅层不仅增加太 阳能电池的制造成本，还增加了寄生光吸收，降低了光的利用效率，限制了太阳能电池的效率。
发明内容
有鉴于此，本公开所要解决的技术问题在于，提供一种太阳能电池以及太阳能电池的制备方法。
为了实现上述目的，本公开提供以下技术方案：
第一方面，本公开提供一种太阳能电池的制备方法，包括：
步骤101，在N型硅衬底的背面依次形成隧穿氧化硅层、N型掺杂多晶硅层和背面钝化减反膜；
步骤102，在背面钝化减反膜上开槽，在开槽区域形成镍金属层；
步骤103，在镍金属层上印刷背面细栅电极，在背面钝化减反膜上印刷背面主栅电极，其中，背面细栅电极与背面主栅电极形成电连接。
根据本公开的一个或多个实施例，步骤103包括：
步骤3-1，在镍金属层上印刷背面细栅电极，并进行第一烘干处理，其中，第一烘干处理的温度为100～300℃；
步骤3-2，在背面钝化减反膜上印刷背面主栅电极，并进行第二烘干处理，其中，第二烘干处理的温度为100～250℃。
根据本公开的一个或多个实施例，背面细栅电极为铝金属，背面主栅电极为银金属。
根据本公开的一个或多个实施例，在步骤101之前还包括：
对N型硅衬底的背面依次进行制绒处理和抛光处理。
根据本公开的一个或多个实施例，步骤101包括：
步骤1-1，在N型硅衬底的背面形成隧穿氧化硅层；
步骤1-2，在隧穿氧化硅层上形成本征多晶硅层；
步骤1-3，对本征多晶硅层进行N型掺杂，形成N型掺杂多晶硅层；
步骤1-4，在N型掺杂多晶硅层上形成背面钝化减反膜。
根据本公开的一个或多个实施例，该方法还包括：
步骤104，对N型硅衬底的正面进行硼扩散处理，形成P+发射极；
步骤105，在N型硅衬底的正面形成正面钝化减反膜，正面钝化减反膜覆盖P+发射极；
步骤106，在正面钝化减反膜印刷正面金属电极。
根据本公开的一个或多个实施例，在步骤104之后，还包括：
对N型硅衬底的正面进行绕镀清洗。
根据本公开的一个或多个实施例，背面钝化减反膜包括氧化铝、氧化硅、氧化镓、氮化硅、氮化铝、氮氧化硅中的至少一种，正面钝化减反膜包括氧化铝、氧化硅、氧化镓、氮化硅、氮化铝、氮氧化硅中的至少一种。
根据本公开的一个或多个实施例，步骤102包括：
步骤2-1，在背面钝化减反膜上开槽，在开槽区域形成镍金属层；
步骤2-2，对镍金属层进行第一退火处理，在镍金属层与N型掺杂多晶硅层之间形成镍硅合金层；其中，退火处理的温度为200～400℃，退火处理的时间为10s～300s。
第二方面，本公开实施例提供一种太阳能电池，该太阳能电池采用根据上述第一方面提供的制备方法制备。
附图说明
图1是根据本公开的太阳能电池的制备方法的流程示意图；
图2示出了制备完成正面金属电极后的太阳能电池的结构图；
图3示出了在背面钝化减反膜上开槽后的太阳能电池的结构图；
图4示出了形成镍金属层后的太阳能电池的结构图；
图5示出了背面细栅电极的图案；
图6示出了形成背面细栅电极和背面主栅电极后的太阳能电池的示意图；
图7示出了背面细栅电极和背面细栅电极的图案；
图8是根据本公开又一种太阳能电池的制备方法的流程示意图。
附图标记如下：
1-N型硅衬底；2-隧穿氧化硅层；3-本征多晶硅层；4-N型掺杂多晶硅层；5-背面钝化减反膜；6-镍金属层；7-背面金属电极；7a-背面细栅电极；7b-背面主栅电极；8-P+发射极；9-正面钝化减反膜；10-正面金属电极。
具体实施方式
在本公开中，欧姆接触是指金属与半导体的接触，而其接触面的电阻值远小于半导体本身的电阻，使得组件操作时，大部分的电压降在活动区而不在接触面。在本申请中，欧姆接触指背面细栅电极与N型掺杂多晶硅层欧姆接触。
如上所述，在采用银浆制备金属电极的过程中，银浆中的玻璃体容易贯穿较薄的多晶硅层，因此现有方法中需要采取较厚的多晶硅薄膜，存在增加了太阳能电池的制造成本，还增加了寄生光吸收，降低了光的利用效率等问题。
为了解决以上问题，本公开实施例提供一种太阳能电池的制备方法。其中，图1为太阳能电池的制备方法的主要流程的示意图。如图1所示，该太阳能电池的制备方法可包括如下步骤：
步骤101，在N型硅衬底1的背面依次形成隧穿氧化硅层2、N型掺杂多晶硅层4和背面钝化减反膜5；
步骤102，在背面钝化减反膜5上开槽，在开槽区域形成镍金属层6；
步骤103，在镍金属层6上印刷背面细栅电极7a，在背面钝化减反膜5上印刷背面主栅电极7b，其中，背面细栅电极7a与背面主栅电极7b形成电连接。
其中，N型硅衬底1的正面是指，在应用N型硅衬底制作成太阳能电池后，N型硅衬底朝向太阳光的一面，即N型硅衬底的接受太阳光照射的受光面，相反，N型硅衬底1的背面是指，背向太阳光的一面，即与N型硅衬底1的受光面相反的背光面。
在步骤101之前，具体的实施方式还可包括：
对N型硅衬底1的背面依次进行制绒处理和抛光处理。具体地，制绒处理后在N型硅衬底1的背面形成类金字塔状结构或类蜂窝状结构。在太阳能电池表面的处理中，制绒是将硅衬底表面进行预清洗并用强碱或强酸腐蚀成类似金字塔状或蜂窝状结构的过程。制绒的目的不仅可以降低表面的反射率，去除损伤层，而且还可以在电池的内部形成光陷阱(减反射绒面)，利用陷光原理，增加了光线在硅衬底内运动的有效长度，有利于硅衬底对光线的吸收，从而提高太阳电池的转换效率。在对N型硅衬底1的背面进行制绒处理后，对N型硅衬底1的背面进行抛光处理。抛光处理即对N型硅衬底1背面制绒后形成的类金字塔状结构或类蜂窝状结构进行平滑处理，以促进N型硅衬底1的背面的晶体硅表面钝化，从而提升电池效率。一个优选实施例中，在对N型硅衬底1的背面进行制绒处理的同时，还可以对N型硅衬底1的正面进行制绒处理。
进一步地，根据本公开实施例，上述方法还包括：
步骤104，对N型硅衬底1的正面进行硼扩散处理，形成p-n结，得到P+发射极8。
具体实施例可以包括：对N型硅衬底1的正面进行制绒处理之后，针对N型硅衬底1的正面进行硼扩散处理，形成p-n结，得到P+发射极8。由于在此过程中会出现绕镀现象，在N型硅衬底1的背面会形成部分p-n结和硼硅玻璃，因此在对N型硅衬底1的正面形成P+发射极8之后，需要采用HF溶液去除N型硅衬底1的背面的p-n结和硼硅玻璃。
针对上述步骤101，具体的实施方式可包括：
步骤1-1，在N型硅衬底1的背面形成隧穿氧化硅层2。其中，隧穿氧化硅层2的厚度为1～2nm中的任意一个值，例如为1.0nm、1.2nm、1.5nm、1.8nm、2.0nm。基于量子隧穿效应，该厚度的隧穿氧化硅层由于厚度较薄，硅衬底中的载流子可以穿过该层而被收集。一个实施例，可采用高温热氧化法、硝酸氧化法、臭氧氧化法或CVD(化学气相沉积)法来形成隧穿氧化硅层2；具体地，当采用高温热氧化法在N型硅衬底1的背面沉积形成隧穿氧化硅层2时，沉积温度为500-700℃。一个优选的实施例，在N型硅衬底1的正面形成的P+发射极8上同时形成隧穿氧化硅层2，以便于后续在N型硅衬底1的背面形成N型掺杂多晶硅层4时，避免正面的P+发射极受到污染。
步骤1-2，在隧穿氧化硅层2上形成本征多晶硅层3。具体地，可以LPCVD(Low Pressure Chemical Vapor Deposition，低压力化学气相沉积法)或PVD(Physical Vapor Deposition，物理气相沉积)形成本征多晶硅层3。本征多晶硅层3的厚度为120～200nm中的任意一个值，例如为120nm、150nm、180nm、200nm。优选地，本征多晶硅层3的厚度为80～150nm中的任意一个值。较薄的多晶硅层不仅可以减少沉积工艺的消耗量，从而降低成本，还减少了多晶硅层的寄生光吸收，从而提高了光的利用效率。一个优选的实施例，在N型硅衬底1的正面形成本征多晶硅层3。
步骤1-3，对N型硅衬底1的背面的本征多晶硅层3进行N型掺 杂，形成N型掺杂多晶硅层4。具体地，可以通过离子注入方式对本征多晶硅层3进行N型掺杂处理，以形成N型掺杂多晶硅层4。N型掺杂例如包括磷掺杂；还可以将硅片放置于磷扩散炉管中，进行磷扩散，扩散温度为700-900℃，在背面形成N型掺杂多晶硅层4。通过隧穿氧化硅层2和N型掺杂多晶硅层4组成的钝化接触结构，可以在保证载流子通过的情况下，有效降低表面复合和金属接触复合，提高电池的转换效率。
根据本公开实施例，在N型硅衬底1的背面形成N型掺杂多晶硅层4之后，对N型硅衬底1的正面进行绕镀清洗，采用强碱溶液去除正面形成的本征多晶硅层；隧穿氧化硅层2；再采用HF溶液去除正面的隧穿氧化硅层2和硼硅玻璃，其中，强碱溶液可以为氢氧化钾溶液或者氢氧化钠溶液。正面的硼硅玻璃是在对N型硅衬底1的正面进行硼扩散处理的过程中产生的。
步骤1-4，在N型掺杂多晶硅层4上形成背面钝化减反膜5。背面钝化减反膜5包括氧化铝、氧化硅、氧化镓、氮化硅、氮化铝、氮氧化硅中的至少一种。
进一步地，根据本公开实施例，上述方法还包括：
步骤105，在N型硅衬底1的正面形成正面钝化减反膜9，正面钝化减反膜9覆盖P+发射极8。
具体地，正面钝化减反膜9可以与背面钝化减反膜5同时形成。正面钝化减反膜9包括氧化铝、氧化硅、氧化镓、氮化硅、氮化铝、氮氧化硅中的至少一种。
步骤106，在正面钝化减反膜9印刷正面金属电极10。其中，图2示出了制备完成正面金属电极后的太阳能电池的结构图。
针对上述步骤102，具体的实施方式可包括：
步骤2-1，在背面钝化减反膜5上开槽，在开槽区域形成镍金属层6。其中，图3示出了在背面钝化减反膜上开槽后的太阳能电池的结构图；图4示出了形成镍金属层后的太阳能电池的结构图。
步骤2-2，对镍金属层6进行第一退火处理，在镍金属层6与N型掺杂多晶硅层4之间形成镍硅合金层；其中，退火处理的温度为200～400℃，退火处理的时间为10s～300s。
步骤102中，利用镍与硅形成镍硅合金层，增强金属栅线与硅之间的结合力，有助于保证后续通过印刷浆料制备金属电极的过程中不破坏N型掺杂多晶硅层，以确保钝化接触结构的钝化效果。
针对上述步骤2-1，具体的实施方式可包括：
首先，采用波长355nm的紫外皮秒激光器在背面钝化减反膜5上开槽，采用inkjet技术(喷墨印刷技术)在开槽区域喷墨印刷导电镍浆，或者采用电镀技术在开槽区域内形成镍金属层6，然后进行退火处理，在退火处理过程中在镍金属层6与N型掺杂多晶硅层4之间形成镍硅合金层。其中，所形成的镍硅合金层可以增加金属栅线和硅之间的结合力，退火温度为200～400℃，退火时间为10s～300s；一个优选的实施例，退火温度250-350℃，退火时间为30s-120s，镍硅合金层的厚度为10～30nm。采用紫外皮秒激光器在背面钝化减反膜5上进行开槽，有效减少了开槽过程中对背面钝化减反膜5造成的损伤。
针对上述步骤103，具体的实施方式可包括：
步骤3-1，在镍金属层6上印刷背面细栅电极7a，并进行第一烘干处理，其中，第一烘干处理的温度为100～300℃；
步骤3-2，在背面钝化减反膜5上印刷背面主栅电极7b，并进行第二烘干处理，使得背面主栅电极7b与背面细栅电极7a形成电连接，其中，第二烘干处理的温度为100～250℃。
具体地，背面细栅电极7a为铝金属，背面主栅电极7b为银金属。
针对上述步骤3-1至步骤3-2，具体的实施方式可包括：
首先，在镍金属层6上印刷低温铝浆，并100～300℃的温度区间内进行低温烘干，形成背面细栅电极7a，其中，图5示出了背面细栅电极的图案；然后，在背面钝化减反膜5上印刷低温银浆，在100～250℃的温度区间内进行低温烘干，形成背面主栅电极7b，其中，背面主栅电极7b与背面细栅电极7a形成电连接，其中，图6示出了形成背面金属电极(包括背面细栅电极和背面主栅电极)后的太阳能电池的示意图；图7示出了背面细栅电极和背面细栅电极的图案。
本公开实施例提供的太阳能电池制备方法，由于通过在N型硅衬底的背面依次形成隧穿氧化硅层、N型掺杂多晶硅层和背面钝化减反膜；再通过在背面钝化减反膜上开槽，在开槽区域形成镍金属层；然后在镍金属层上印刷背面细栅电极，在背面钝化减反膜上印刷背面主栅电极，其中，背面细栅电极与背面主栅电极形成电连接，从而实现了在保证金属栅线与硅之间结合力的同时，避免浆料在使用过程中对较薄的多晶硅层的破坏，确保了钝化接触结构的钝化效果，降低了太阳能电池的制造成本，减少了寄生光吸收，提高了光的利用效率，提高了太阳能电池的效率。
同时，背面细栅电极采用铝金属，还降低了制备背面金属电极所需的银耗量，有效降低了太阳能电池的制备成本。
本公开实施例还提供了一种太阳能电池的制备方法。如图8所示，该太阳能电池的制备方法可包括如下步骤：
步骤201，对N型硅衬底1的正面进行硼扩散处理，形成P+发射极8；
步骤202，在N型硅衬底1的背面依次形成隧穿氧化硅层2、N型 掺杂多晶硅层4；
步骤203，在N型硅衬底1的正面和背面分别形成正面钝化减反膜9和背面钝化减反膜5；正面钝化减反膜9覆盖P+发射极8；
步骤204，在正面钝化减反膜9上印刷正面金属电极10；
步骤205，在背面钝化减反膜5上开槽，在开槽区域形成镍金属层6；
步骤206，在镍金属层6上印刷背面细栅电极7a，在背面钝化减反膜5上印刷背面主栅电极7b，其中，背面细栅电极7a与背面主栅电极7b形成电连接。
具体地，一个可选的实施例，在步骤201之前，还包括：对N型硅衬底1的正面和背面进行制绒处理，并对N型硅衬底1的背面进行抛光处理。一个可选的实施例，在步骤201对N型硅衬底1的正面形成P+发射极8之后，需要采用HF溶液去除N型硅衬底1背面的p-n结和硼硅玻璃。一个可选的实施例，在N型硅衬底1的背面形成隧穿氧化硅层2和本征多晶硅层3的同时，在N型硅衬底1的正面也形成隧穿氧化硅层2和本征多晶硅层3；一个优选的实施例，在步骤203之前，采用氢氧化钠溶液或者氢氧化钾溶液去除N型硅衬底1的正面形成的本征多晶硅层3，采用HF溶液去除正面的隧穿氧化硅层和硼硅玻璃。
本公开的另一方面还包括通过以上太阳能电池制备方法制备的太阳能电池。该太阳能电池包括：从上到下顺序设置的N型硅衬底1、隧穿氧化硅层2、N型掺杂多晶硅层4、背面钝化减反膜5；其中，
背面钝化减反膜5的开槽区域中形成有镍金属层6，在镍金属层6上形成有背面细栅电极7a和背面主栅电极7b，其中背面细栅电极7a和背面主栅电极7b形成电连接。
进一步地，根据本公开实施例，上述太阳能电池的N型硅衬底1的正面还依次设置有P+发射极8、正面钝化减反膜9和正面金属电极 10。
本公开中，上述背面细栅电极7a的材料为铝金属；背面细栅电极7a的材料为银金属。
下面以几个具体实施例详细说明本公开提供的太阳能电池制备方法和其得到的太阳能电池。
实施例1
步骤A1：提供一种N型硅衬底1，对N型硅衬底1的正面和背面进行制绒处理，并对N型硅衬底1的背面进行抛光处理。
步骤B1：对N型硅衬底1的正面进行硼扩散处理，形成P+发射极8。
步骤C1：通过HF酸溶液去除N型硅衬底1背面的p-n结和硼硅玻璃。
步骤D1：通过高温热氧化法在N型硅衬底1的背面形成厚度为1～2nm的隧穿氧化硅层2。
步骤E1：通过LPCVD/PVD在N型硅衬底1背面的隧穿氧化硅层2上形成本征多晶硅层3。
步骤F1：将掺杂元素磷通过离子注入方式对背面的本征多晶硅层3进行掺杂处理，并进行退火，以形成N型掺杂多晶硅层4，其中，该N型掺杂多晶硅层的厚度在80～200nm之间。
步骤G1：通过HF酸溶液去除N型硅衬底1正面的硼硅玻璃。
步骤H1：在N型硅衬底1的正面形成正面钝化减反膜9，在N型硅衬底1的背面形成背面钝化减反膜5。其中，正面钝化减反膜和背面钝化减反膜均为氧化铝、氧化硅、氧化镓、氮化硅、氮化铝、氮氧化硅中的至少一种。
步骤I1：在正面钝化减反膜9上制备正面金属电极10。
步骤J1：通过采用波长355nm的紫外皮秒激光器在背面钝化减反膜5上开槽，得到如图3所示的结构，然后在开槽区域形成镍金属层6，得到如图4所示的结构。
步骤K1：对镍金属层6进行第一退火处理，在镍金属层6与N型掺杂多晶硅层4之间形成镍硅合金层；其中，退火处理的温度为200～400℃，退火处理的时间为10s～300s。
步骤L1：在镍金属层6上印刷铝浆，并在100～300℃范围内进行烘干处理，制备得到背面细栅电极7a；
步骤M1：在背面钝化减反膜5上印刷银浆，并在100～250℃范围内进行烘干处理，制备得到背面主栅电极7b，得到如图6所示的结构.其中，背面主栅电极7b与背面细栅电极7a形成电连接。
实施例2
步骤A2-C2：与实施例1提供的步骤A1-C1一致。
步骤D2：通过高温热氧化法在N型硅衬底1的背面和正面分别形成厚度为1～2nm的隧穿氧化硅层2。
步骤E2：通过LPCVD/PVD在N型硅衬底1背面和正面的隧穿氧化硅层2上形成本征多晶硅层3。
步骤F2：将磷通过离子注入方式对背面的本征多晶硅层3进行掺杂处理，并进行退火，以形成N型掺杂多晶硅层4，其中，该N型掺杂多晶硅层的厚度在80～200nm之间。
步骤G2：通过氢氧化钾溶液或氢氧化钠溶液去除N型硅衬底1正面的本征多晶硅层3，再用HF酸溶液去除正面的隧穿氧化硅层2和硼硅玻璃。
步骤H2：在N型硅衬底1的正面形成正面钝化减反膜9，在N型硅衬底1的背面形成背面钝化减反膜5。其中，正面钝化减反膜和背面钝化减反膜均为氧化铝、氧化硅、氧化镓、氮化硅、氮化铝、氮氧化硅中的至少一种。
步骤I2：在正面钝化减反膜9上制备正面金属电极10。
步骤J2：通过采用波长355nm的紫外皮秒激光器在背面钝化减反膜5上开槽，得到如图3所示的结构，然后在开槽区域形成镍金属层6，得到如图4所示的结构。
步骤K2：对镍金属层6进行第一退火处理，在镍金属层6与N型掺杂多晶硅层4之间形成镍硅合金层；其中，退火处理的温度为200～400℃，退火处理的时间为10s～300s。
步骤L2：在镍金属层6上印刷铝浆，并在100～300℃范围内进行烘干处理，制备得到背面细栅电极7a；
步骤M2：在背面钝化减反膜5上印刷银浆，并在100～250℃范围内进行烘干处理，制备得到背面主栅电极7b，得到如图6所示的结构.其中，背面主栅电极7b与背面细栅电极7a形成电连接。
实施例3
该实施例的各个步骤与实施例2的各步骤一致，只是在步骤D3中采用硝酸氧化的方式，在N型硅衬底1的背面和正面形成厚度为1～2nm的隧穿氧化硅层2。
实施例4
该实施例的各个步骤与实施例2的各步骤一致，只是在步骤F4中采用将硅片放置于磷扩散炉管中，进行磷扩散，扩散温度为700-900℃，在背面形成N型掺杂多晶硅层(4)。
以上步骤所提供的介绍，只是用于帮助理解本公开的方法、结构及核心思想。对于本技术领域内的普通技术人员来说，在不脱离本公开原理的前提下，还可以对本公开进行若干改进和修饰，这些改进和修饰也同样属于本公开权利要求保护范围之内。

Claims (10)

  1. 一种太阳能电池的制备方法，包括：
    步骤101，在N型硅衬底(1)的背面依次形成隧穿氧化硅层(2)、N型掺杂多晶硅层(4)和背面钝化减反膜(5)；
    步骤102，在所述背面钝化减反膜(5)上开槽，在开槽区域形成镍金属层(6)；
    步骤103，在所述镍金属层(6)上印刷背面细栅电极(7a)，在所述背面钝化减反膜(5)上印刷背面主栅电极(7b)，其中，所述背面细栅电极(7a)与所述背面主栅电极(7b)形成电连接。
  2. 根据权利要求1所述的太阳能电池的制备方法，其中，所述步骤103包括：
    步骤3-1，在所述镍金属层(6)上印刷背面细栅电极(7a)，并进行第一烘干处理，其中，所述第一烘干处理的温度为100～300℃；
    步骤3-2，在所述背面钝化减反膜(5)上印刷背面主栅电极(7b)，并进行第二烘干处理，其中，所述第二烘干处理的温度为100～250℃。
  3. 根据权利要求2所述的太阳能电池的制备方法，其中，
    所述背面细栅电极(7a)为铝金属，所述背面主栅电极(7b)为银金属。
  4. 根据权利要求1所述的太阳能电池的制备方法，其中，在所述步骤101之前还包括：
    对所述N型硅衬底(1)的背面依次进行制绒处理和抛光处理。
  5. 根据权利要求1所述的太阳能电池的制备方法，其中，所述步骤101包括：
    步骤1-1，在所述N型硅衬底(1)的背面形成隧穿氧化硅层(2)；
    步骤1-2，在所述隧穿氧化硅层(2)上形成本征多晶硅层(3)；
    步骤1-3，对所述本征多晶硅层(3)进行N型掺杂，形成N型掺杂多晶硅层(4)；
    步骤1-4，在所述N型掺杂多晶硅层(4)上形成背面钝化减反膜(5)。
  6. 根据权利要求1所述的太阳能电池的制备方法，进一步包括：
    步骤104，对所述N型硅衬底(1)的正面进行硼扩散处理，形成P+发射极(8)；
    步骤105，在所述N型硅衬底(1)的正面形成正面钝化减反膜(9)，所述正面钝化减反膜(9)覆盖所述P+发射极(8)；
    步骤106，在所述正面钝化减反膜(9)印刷正面金属电极(10)。
  7. 根据权利要求6所述的太阳能电池的制备方法，其中，在所述步骤104之后，还包括：
    对所述N型硅衬底(1)的正面进行绕镀清洗。
  8. 根据权利要求6所述的太阳能电池的制备方法，其中，
    所述背面钝化减反膜(5)包括氧化铝、氧化硅、氧化镓、氮化硅、氮化铝、氮氧化硅中的至少一种，所述正面钝化减反膜(9)包括氧化铝、氧化硅、氧化镓、氮化硅、氮化铝、氮氧化硅中的至少一种。
  9. 根据权利要求1所述的太阳能电池的制备方法，其中，所述步骤102包括：
    步骤2-1，在所述背面钝化减反膜(5)上开槽，在开槽区域形成镍金属层(6)；
    步骤2-2，对所述镍金属层(6)进行第一退火处理，在所述镍金属层(6)与所述N型掺杂多晶硅层(4)之间形成镍硅合金层；其中，所述退火处理的温度为200～400℃，所述退火处理的时间为10s～300s。
  10. 一种太阳能电池，采用根据权利要求1-9任一项所述的制备方法制备。
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