WO2023098436A1 - 交织与调制方法、装置及系统 - Google Patents

交织与调制方法、装置及系统 Download PDF

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WO2023098436A1
WO2023098436A1 PCT/CN2022/130890 CN2022130890W WO2023098436A1 WO 2023098436 A1 WO2023098436 A1 WO 2023098436A1 CN 2022130890 W CN2022130890 W CN 2022130890W WO 2023098436 A1 WO2023098436 A1 WO 2023098436A1
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column
bits
constellation
ring
constellation point
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English (en)
French (fr)
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王晓鲁
李榕
罗禾佳
王俊
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP22900241.5A priority Critical patent/EP4418577A4/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851—Systems using a satellite or space-based relay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851—Systems using a satellite or space-based relay
    • H04B7/18513—Transmission in a satellite or space-based system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851—Systems using a satellite or space-based relay
    • H04B7/18517—Transmission equipment in earth stations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/18578—Satellite systems for providing broadband data service to individual earth stations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H04L1/0058—Block-coded modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations

Definitions

  • the embodiments of the present application relate to the communication field, and in particular to interleaving and modulation methods, devices and systems.
  • the future wireless communication network needs to provide wider service coverage while meeting the service requirements of various industries.
  • the traditional terrestrial mobile communication network has limited coverage and cannot meet people's needs for obtaining information at any time and any place.
  • the current mode based on base station coverage to provide ultra-wide-area coverage poses huge challenges in terms of economy and feasibility for scenarios such as remote areas, deserts, oceans, and air.
  • satellite communication Compared with the traditional terrestrial mobile communication network, satellite communication has significant advantages such as global coverage, long-distance transmission, flexible networking, convenient deployment and no geographical restrictions, and can be used as an effective supplement to traditional networks.
  • the present application provides an interleaving and modulation method, device and system, which can improve transmission reliability, thereby improving the decoding performance of the receiving end.
  • a method for interleaving and modulation may be executed by the transmitting end device, or may be executed by components of the transmitting end device, such as a processor, a chip, or a chip system of the transmitting end device, or may be implemented by The logical module or software implementation of all or part of the functions of the sending end device.
  • the method includes: acquiring bits to be interleaved.
  • the first interleaving is performed on the bits to be interleaved to obtain the interleaved bits.
  • the interleaved bits are modulated to obtain modulation symbols. Send the modulation symbol.
  • the first interleaving includes: writing the bits to be interleaved into the first matrix column by column according to the first sequence, and reading the bits to be interleaved row by row from the first matrix according to the second sequence.
  • the number of columns of the first matrix is the modulation order M, and M is greater than or equal to 3.
  • the first bit read out row by row is the most significant bit MSB, and the Mth bit is the least significant bit LSB.
  • the modulation mode used is the second-generation satellite digital video broadcasting DVB-S28 phase-shift keying PSK.
  • the first order is the third column-the second column-the first column of the first matrix
  • the second order is the first column-the second column-the third column of the first matrix
  • the first order is the second column-the third column-the first column of the first matrix
  • the second order is the first column-the second column-the third column of the first matrix
  • the first order is the first column-the second column-the third column of the first matrix
  • the second order is the second column-the third column-the first column of the first matrix
  • this application proposes a new interleaving method.
  • this interleaving method can map the system bits to bits with higher reliability for transmission, thereby improving transmission reliability and system decoding performance. For example, when M is equal to 3, based on the interleaving scheme, systematic bits can be mapped to bit0 for transmission.
  • bit0 has higher reliability than bit2, so when the system bit is transmitted in bit0, the transmission reliability of the system bit can be improved, thereby improving the decoding performance of the system.
  • the modulation method used is DVB-S2 16 amplitude phase shift keying APSK.
  • the second order is the first column-second column-third column-fourth column of the first matrix.
  • the first sequence is the fourth column-the third column-the second column-the first column of the first matrix.
  • the first sequence is the fourth column-the third column-the first column-the second column of the first matrix.
  • the first order is the third column-the fourth column-the second column-the first column of the first matrix.
  • the first sequence is the third column-the fourth column-the first column-the second column of the first matrix.
  • the system bit can be mapped to bit0 or bit1 for transmission.
  • bit0 and bit1 have higher reliability than bit3, so when the system bit is transmitted in bit0 or bit1, the transmission reliability and decoding performance of the system bit can be improved.
  • the modulation method used is DVB-S2 32APSK.
  • the second order is the first column-second column-third column-fourth column-fifth column of the first matrix.
  • the first sequence is the fourth column-third column-second column-first column-fifth column of the first matrix.
  • the first sequence is the fourth column-second column-third column-first column-fifth column of the first matrix.
  • the first sequence is the fourth column-third column-second column-fifth column-first column of the first matrix.
  • the first sequence is the fourth column-second column-third column-fifth column-first column of the first matrix.
  • the system bit can be mapped to bit1 for transmission.
  • bit1 has higher reliability than bit4, so when the system bit is transmitted in bit1, the transmission reliability and decoding performance of the system bit can be improved.
  • a method for interleaving and modulation is provided, which can be performed by the transmitting device, or by components of the transmitting device, such as a processor, a chip, or a chip system of the transmitting device, and can also be implemented by The logical module or software implementation of all or part of the functions of the sending end device.
  • the method includes: acquiring bits to be interleaved.
  • the first interleaving is performed on the bits to be interleaved to obtain the interleaved bits.
  • the interleaved bits are modulated to obtain modulation symbols. Send the modulation symbol.
  • the first interleaving includes: writing the bits to be interleaved into the first matrix column by column in order from left to right, and reading the bits to be interleaved row by row from the first matrix in order from left to right.
  • the number of columns of the first matrix is the modulation order M, and M is greater than or equal to 3.
  • the first bit read out row by row is the most significant bit MSB, and the Mth bit is the least significant bit LSB.
  • the constellation diagram used for modulation includes 2 M constellation points, and the 2 M constellation points are distributed on N rings, and the constellation points on at least one of the N rings satisfy the principle of Gray mapping, and N is a positive integer.
  • this application proposes a new constellation diagram.
  • the constellation diagram When the constellation diagram is used in combination with the interleaving mode in NR, it can improve the transmission reliability of system bits, and further improve the decoding performance of the system.
  • the bit corresponding to the first constellation point is 0011. Taking the first constellation point as a reference, and following the clockwise direction, the bits corresponding to the remaining three constellation points on the first ring are: 0111, 1111, and 1011, respectively.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0001, 0101, 0100, 0110, 1110, 1100, 1101, 1001, 1000, 1010, 0010.
  • the bit corresponding to the first constellation point is 0011. Taking the first constellation point as a reference, and following the clockwise direction, the bits corresponding to the remaining three constellation points on the first ring are: 0111, 1111, and 1011, respectively.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0010, 0110, 0100, 0101, 1101, 1100, 1110, 1010, 1000, 1001, 0001.
  • the bit corresponding to the first constellation point is 0011. Taking the first constellation point as a reference, and following the clockwise direction, the bits corresponding to the remaining three constellation points on the first ring are: 1011, 1111, and 0111, respectively.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0001, 1001, 1000, 1010, 1110, 1100, 1101, 0101, 0100, 0110, 0010.
  • the bit corresponding to the first constellation point is 0011. Taking the first constellation point as a reference, and following the clockwise direction, the bits corresponding to the remaining three constellation points on the first ring are: 1011, 1111, and 0111, respectively.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0010, 1010, 1000, 1001, 1101, 1100, 1110, 0110, 0100, 0101, 0001.
  • the bits corresponding to the first constellation point are 00011. Taking the first constellation point as a reference, the bits corresponding to the remaining three constellation points on the first ring are: 00111, 01111, and 01011 in a clockwise direction.
  • the bit corresponding to the second constellation point is 00000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 00001, 00101, 00100, 00110, 01110, 01100, 01101, 01001, 01000, 01010, 00010.
  • the bit corresponding to the third constellation point is 10011.
  • the bits corresponding to the remaining 15 constellation points on the third ring are: 10000, 10001, 10101, 10100, 10111, 10110, 11110, 11111, 11100, 11101, 11001, 11000, 11011, 11010, 10010.
  • the bits corresponding to the first constellation point are 00101. Taking the first constellation point as a reference, the bits corresponding to the remaining three constellation points on the first ring are: 00111, 01111, and 01101 in a clockwise direction.
  • the bit corresponding to the second constellation point is 00000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 00001, 00011, 00010, 00110, 01110, 01010, 01011, 01001, 01000, 01100, 00100.
  • the bit corresponding to the third constellation point is 10101.
  • the bits corresponding to the remaining 15 constellation points on the third ring are: 10000, 10001, 10011, 10010, 10111, 10110, 11110, 11111, 11010, 11011, 11001, 11000, 11101, 11100, 10100.
  • the bit corresponding to the first constellation point is 10010. Taking the first constellation point as a reference, the bits corresponding to the remaining three constellation points on the first ring are: 10110, 11110, and 11010 in a clockwise direction.
  • the bit corresponding to the second constellation point is 00000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 10000, 10100, 00100, 00110, 01110, 01100, 11100, 11000, 01000, 01010, 00010.
  • the bit corresponding to the third constellation point is 10011. Taking the third constellation point as the reference and clockwise, the bits corresponding to the remaining 15 constellation points on the third ring are: 00001, 10001, 10101, 00101, 10111, 00111, 01111, 11111, 01101, 11101, 11001, 01001, 11011, 01011, 00011.
  • the bit corresponding to the first constellation point is 10100. Taking the first constellation point as a reference, the bits corresponding to the remaining three constellation points on the first ring are: 10110, 11110, and 11100 in a clockwise direction.
  • the bit corresponding to the second constellation point is 00000. Based on the second constellation point, in a clockwise direction, the bits corresponding to the remaining 11 constellation points on the second ring are: 10000, 10010, 00010, 00110, 01110, 01010, 11010, 11000, 01000, 01100, 00100.
  • the bit corresponding to the third constellation point is 10101.
  • the bits corresponding to the remaining 15 constellation points on the third ring are: 00001, 10001, 10011, 00011, 10111, 00111, 01111, 11111, 01011, 11011, 11001, 01001, 11101, 01101, 00101.
  • the bits to be interleaved are coded bits; or, the bits to be interleaved are bits after second interleaving is performed on the coded bits.
  • the second interleaving includes: performing random or pseudo-random interleaving on the last N-X bits of the coded bits; X is greater than or equal to the number of systematic bits, and N is the number of coded bits the number of bits.
  • the bits to be interleaved are the bits after the second interleaving of the encoded bits, it is equivalent to performing two interleaves on the sending end device, which can reduce the fluctuation range of the mapping probability of the constellation points and improve the decoding performance .
  • a method for interleaving and demodulation may be executed by the receiving end device, or may be executed by components of the receiving end device, such as a processor, a chip, or a chip system of the receiving end device, or may be performed by A logic module or software implementation that realizes all or part of the functions of the receiver device.
  • the method includes receiving modulation symbols.
  • the modulation symbols are demodulated to obtain the LLR sequence to be deinterleaved.
  • the first deinterleaving is performed on the LLR sequence to be deinterleaved to obtain the first LLR sequence after deinterleaving.
  • the information bits are determined according to the deinterleaved first LLR sequence.
  • the first deinterleaving includes: writing the LLR sequences to be deinterleaved into the second matrix row by row according to the second order, and reading out the LLR sequences from the second matrix column by column according to the first order.
  • the number of columns of the second matrix is the modulation order M, and M is greater than or equal to 3.
  • the first bit written row by row is the most significant bit MSB, and the Mth bit is the least significant bit LSB.
  • the modulation mode corresponding to the demodulation is the second generation satellite digital video broadcasting DVB-S2 8 phase shift keying PSK;
  • the first order is the third column-the second column-the first column of the second matrix
  • the second order is the first column-the second column-the third column of the second matrix
  • the first order is the second column-the third column-the first column of the second matrix
  • the second order is the first column-the second column-the third column of the second matrix
  • the first sequence is the first column-second column-third column of the second matrix
  • the second sequence is the second column-third column-first column of the second matrix
  • the modulation mode corresponding to demodulation is DVB-S2 16 amplitude phase shift keying APSK; the second order is the first column-second column-third column of the second matrix - the fourth column.
  • the first sequence is the fourth column-third column-second column-first column of the second matrix.
  • the first sequence is the fourth column-the third column-the first column-the second column of the second matrix.
  • the first order is the third column-the fourth column-the second column-the first column of the second matrix.
  • the first order is the third column-the fourth column-the first column-the second column of the second matrix.
  • the modulation mode corresponding to demodulation is DVB-S2 32APSK; the second order is the first column-second column-third column-fourth column-the five columns.
  • the first sequence is the fourth column-third column-second column-first column-fifth column of the second matrix.
  • the first sequence is the fourth column-second column-third column-first column-fifth column of the second matrix.
  • the first sequence is the fourth column-third column-second column-fifth column-first column of the second matrix.
  • the first sequence is the fourth column-second column-third column-fifth column-first column of the second matrix.
  • the technical effect brought by the third aspect or any possible design of the third aspect can refer to the technical effect brought by the first aspect or the corresponding design of the first aspect, and will not be repeated here.
  • a method for interleaving and demodulation may be executed by the receiving end device, or may be executed by a component of the receiving end device, such as a processor, a chip, or a chip system of the receiving end device, or may be performed by a device that can A logic module or software implementation that realizes all or part of the functions of the receiver device.
  • the method includes receiving modulation symbols.
  • the modulation symbols are demodulated to obtain the LLR sequence to be deinterleaved.
  • the first deinterleaving is performed on the LLR sequence to be deinterleaved to obtain the first LLR sequence after deinterleaving.
  • the information bits are determined according to the deinterleaved first LLR sequence.
  • the first deinterleaving includes: writing the second matrix row-by-row in a left-to-right order, and reading column-by-column from the second matrix in a left-to-right order.
  • the number of columns of the second matrix is the modulation order M, and M is greater than or equal to 3.
  • the first bit written row by row is the most significant bit MSB, and the Mth bit is the least significant bit LSB.
  • the constellation diagram used for demodulation includes 2 M constellation points, and the 2 M constellation points are distributed on N rings, and the constellation points on at least one of the N rings satisfy the principle of Gray mapping, and N is positive integer.
  • the bit corresponding to the first constellation point is 0011. Taking the first constellation point as a reference, and following the clockwise direction, the bits corresponding to the remaining three constellation points on the first ring are: 0111, 1111, and 1011, respectively.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0001, 0101, 0100, 0110, 1110, 1100, 1101, 1001, 1000, 1010, 0010.
  • the bit corresponding to the first constellation point is 0011. Taking the first constellation point as a reference, and following the clockwise direction, the bits corresponding to the remaining three constellation points on the first ring are: 0111, 1111, and 1011, respectively.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0010, 0110, 0100, 0101, 1101, 1100, 1110, 1010, 1000, 1001, 0001.
  • the bit corresponding to the first constellation point is 0011. Taking the first constellation point as a reference, and following the clockwise direction, the bits corresponding to the remaining three constellation points on the first ring are: 1011, 1111, and 0111, respectively.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0001, 1001, 1000, 1010, 1110, 1100, 1101, 0101, 0100, 0110, 0010.
  • the bit corresponding to the first constellation point is 0011. Taking the first constellation point as a reference, and following the clockwise direction, the bits corresponding to the remaining three constellation points on the first ring are: 1011, 1111, and 0111, respectively.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0010, 1010, 1000, 1001, 1101, 1100, 1110, 0110, 0100, 0101, 0001.
  • the bits corresponding to the first constellation point are 00011. Taking the first constellation point as a reference, the bits corresponding to the remaining three constellation points on the first ring are: 00111, 01111, and 01011 in a clockwise direction.
  • the bit corresponding to the second constellation point is 00000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 00001, 00101, 00100, 00110, 01110, 01100, 01101, 01001, 01000, 01010, 00010.
  • the bit corresponding to the third constellation point is 10011.
  • the bits corresponding to the remaining 15 constellation points on the third ring are: 10000, 10001, 10101, 10100, 10111, 10110, 11110, 11111, 11100, 11101, 11001, 11000, 11011, 11010, 10010.
  • the bits corresponding to the first constellation point are 00101. Taking the first constellation point as a reference, the bits corresponding to the remaining three constellation points on the first ring are: 00111, 01111, and 01101 in a clockwise direction.
  • the bit corresponding to the second constellation point is 00000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 00001, 00011, 00010, 00110, 01110, 01010, 01011, 01001, 01000, 01100, 00100.
  • the bit corresponding to the third constellation point is 10101.
  • the bits corresponding to the remaining 15 constellation points on the third ring are: 10000, 10001, 10011, 10010, 10111, 10110, 11110, 11111, 11010, 11011, 11001, 11000, 11101, 11100, 10100.
  • the bit corresponding to the first constellation point is 10010. Taking the first constellation point as a reference, the bits corresponding to the remaining three constellation points on the first ring are: 10110, 11110, and 11010 in a clockwise direction.
  • the bit corresponding to the second constellation point is 00000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 10000, 10100, 00100, 00110, 01110, 01100, 11100, 11000, 01000, 01010, 00010.
  • the bit corresponding to the third constellation point is 10011. Taking the third constellation point as the reference and clockwise, the bits corresponding to the remaining 15 constellation points on the third ring are: 00001, 10001, 10101, 00101, 10111, 00111, 01111, 11111, 01101, 11101, 11001, 01001, 11011, 01011, 00011.
  • the bit corresponding to the first constellation point is 10100. Taking the first constellation point as a reference, the bits corresponding to the remaining three constellation points on the first ring are: 10110, 11110, and 11100 in a clockwise direction.
  • the bit corresponding to the second constellation point is 00000. Based on the second constellation point, in a clockwise direction, the bits corresponding to the remaining 11 constellation points on the second ring are: 10000, 10010, 00010, 00110, 01110, 01010, 11010, 11000, 01000, 01100, 00100.
  • the bit corresponding to the third constellation point is 10101.
  • the bits corresponding to the remaining 15 constellation points on the third ring are: 00001, 10001, 10011, 00011, 10111, 00111, 01111, 11111, 01011, 11011, 11001, 01001, 11101, 01101, 00101.
  • determining the information bits according to the deinterleaved first LLR sequence includes: decoding the deinterleaved first LLR sequence to obtain the information bits.
  • determining information bits according to the deinterleaved first LLR sequence includes: performing second deinterleaving on the deinterleaved first LLR sequence to obtain deinterleaved the second LLR sequence after deinterleaving; and decode the second LLR sequence after deinterleaving to obtain information bits.
  • the second deinterleaving includes: performing deinterleaving on the last N-X elements of the first LLR sequence in a preset order, where N is the number of information bits, and X Greater than or equal to the number of systematic bits.
  • the technical effect brought by the fourth aspect or any possible design of the fourth aspect can refer to the technical effect brought by the second aspect or the corresponding design of the second aspect, and will not be repeated here.
  • a communication device for implementing the above various methods.
  • the communication device may be the sending end device in the above first aspect or the second aspect, or a device including the above sending end device, or a device included in the above sending end device, such as a chip; or, the communication device may be the above first
  • the communication device includes a corresponding module, unit, or means (means) for implementing the above method, and the module, unit, or means can be implemented by hardware, software, or by executing corresponding software on hardware.
  • the hardware or software includes one or more modules or units corresponding to the above functions.
  • the communication device may include a transceiver module and a processing module.
  • the transceiver module which may also be referred to as a transceiver unit, is configured to implement the sending and/or receiving functions in any of the above aspects and any possible implementation manners thereof.
  • the transceiver module may be composed of a transceiver circuit, a transceiver, a transceiver or a communication interface.
  • the processing module may be used to implement the processing functions in any of the above aspects and any possible implementation manners thereof.
  • the transceiver module includes a sending module and a receiving module, respectively configured to implement the sending and receiving functions in any of the above aspects and any possible implementations thereof.
  • a communication device including: a processor and a memory; the memory is used to store computer instructions, and when the processor executes the instructions, the communication device executes the method described in any one of the above aspects.
  • the communication device may be the sending end device in the above first aspect or the second aspect, or a device including the above sending end device, or a device included in the above sending end device, such as a chip; or, the communication device may be the above first
  • a communication device including: a processor and a communication interface; the communication interface is used to communicate with modules other than the communication device; the processor is used to execute computer programs or instructions, so that the communication device Perform the method described in any one of the above aspects.
  • the communication device may be the sending end device in the above first aspect or the second aspect, or a device including the above sending end device, or a device included in the above sending end device, such as a chip; or, the communication device may be the above first
  • a communication device including: a logic circuit and an interface circuit; the interface circuit is used to input and/or output information; the logic circuit is used to execute the method described in any one of the above aspects to generate the interface
  • the information output by the circuit, and/or, the information input by the interface circuit is processed.
  • the communication device may be the sending end device in the above first aspect or the second aspect, or a device including the above sending end device, or a device included in the above sending end device, such as a chip; or, the communication device may be the above first The receiver device in the third aspect or the fourth aspect, or a device including the above receiver device, or a device included in the above receiver device, such as a chip.
  • the output information is a modulation symbol.
  • the input information is a modulation symbol.
  • Processing the input information includes: demodulating the modulation symbols to obtain a log-likelihood ratio (LLR) sequence to be deinterleaved.
  • LLR log-likelihood ratio
  • the first deinterleaving is performed on the LLR sequence to be deinterleaved to obtain the first LLR sequence after deinterleaving.
  • the information bits are determined according to the deinterleaved first LLR sequence.
  • a communication device including: an interface circuit and a processor, the interface circuit is a code/data read and write interface circuit, and the interface circuit is used to receive computer-executed instructions (computer-executed instructions are stored in a memory, possibly read directly from the memory, or possibly through other devices) and transmit to the processor; the processor is used to execute computer-executed instructions to enable the communication device to perform the method described in any aspect above.
  • the communication device may be the sending end device in the above first aspect or the second aspect, or a device including the above sending end device, or a device included in the above sending end device, such as a chip; or, the communication device may be the above first The receiver device in the third aspect or the fourth aspect, or a device including the above receiver device, or a device included in the above receiver device, such as a chip.
  • a communication device including: at least one processor; the processor is configured to execute computer programs or instructions, so that the communication device executes the method described in any aspect above.
  • the communication device may be the sending end device in the above first aspect or the second aspect, or a device including the above sending end device, or a device included in the above sending end device, such as a chip; or, the communication device may be the above first
  • the communication device includes a memory for storing necessary program instructions and data.
  • the memory can be coupled to the processor, or it can be independent of the processor.
  • the communication device may be a chip or a chip system.
  • the device When the device is a system-on-a-chip, it may consist of chips, or may include chips and other discrete devices.
  • a computer-readable storage medium is provided. Instructions are stored in the computer-readable storage medium. When the computer-readable storage medium is run on a communication device, the communication device can execute the method described in any aspect above.
  • a computer program product containing instructions, which, when run on a communication device, enables the communication device to execute the method described in any one of the above aspects.
  • the above-mentioned sending action/function can be understood as output, and the above-mentioned receiving action/function can be understood as input.
  • the technical effects brought by any one of the design methods from the fifth aspect to the twelfth aspect can refer to the technical effects brought about by the different design methods in the first aspect or the second aspect or the third aspect or the fourth aspect , which will not be repeated here.
  • a communication system includes the sending end device and the receiving end device described in the above aspects.
  • Fig. 1 is the constellation diagram of a kind of DVB-S2 8PSK that the application provides;
  • Fig. 2 is the constellation diagram of a kind of DVB-S2 16APSK that the application provides;
  • Fig. 3 is the constellation diagram of a kind of DVB-S2 32APSK that the application provides;
  • Fig. 4 is the bit reliability emulation figure of a kind of DVB-S2 8PSK that the application provides;
  • Fig. 5 is the bit reliability emulation figure of a kind of DVB-S2 16APSK that the application provides;
  • Fig. 6 is the bit reliability emulation figure of a kind of DVB-S2 32APSK that the application provides;
  • FIG. 7 is a schematic diagram of data processing of an NR sending end provided by the present application.
  • FIG. 8 is a schematic diagram of an interleaving method of an NR sending end provided by the present application.
  • FIG. 9 is a schematic diagram of a deinterleaving method of an NR receiving end provided by the present application.
  • FIG. 10 is a schematic diagram of interleaving of LDPC coded bits provided by the present application.
  • FIG. 11 is a schematic structural diagram of a communication system provided by the present application.
  • FIG. 12 is a schematic structural diagram of another communication system provided by the present application.
  • FIG. 13 is a schematic structural diagram of a terminal device and a network device provided by the present application.
  • FIG. 14 is a schematic flowchart of an interleaving and modulation method provided by the present application.
  • FIG. 15 is a schematic diagram of an interleaving method provided by the present application when the modulation order is equal to 3;
  • Figure 16a is a BLER performance simulation diagram of different interleaving modes when the modulation order is equal to 3 provided by the present application;
  • Figure 16b is a schematic diagram of another interleaving method when the modulation order is equal to 3 provided by the present application.
  • FIG. 17 is a schematic diagram of another interleaving method provided by the present application when the modulation order is equal to 3;
  • FIG. 18 is a schematic diagram of another interleaving method provided by the present application when the modulation order is equal to 3;
  • FIG. 19 is a schematic diagram of an interleaving method provided by the present application when the modulation order is equal to 4.
  • FIG. 20 is a BLER performance simulation diagram of different interleaving modes provided by the present application when the modulation order is equal to 4.
  • FIG. 21 is a schematic diagram of another interleaving method provided by the present application when the modulation order is equal to 4.
  • FIG. 22 is a schematic diagram of another interleaving method provided by the present application when the modulation order is equal to 4.
  • FIG. 23 is a schematic diagram of another interleaving method provided by the present application when the modulation order is equal to 4.
  • FIG. 24 is a schematic diagram of an interleaving method provided by the present application when the modulation order is equal to 5;
  • FIG. 25 is a BLER performance simulation diagram of different interleaving modes provided by the present application when the modulation order is equal to 5;
  • FIG. 26 is a schematic diagram of another interleaving method provided by the present application when the modulation order is equal to 5;
  • Fig. 27 is a schematic diagram of another interleaving method provided by the present application when the modulation order is equal to 5;
  • FIG. 28 is a schematic diagram of another interleaving method provided by the present application when the modulation order is equal to 5;
  • FIG. 29 is a schematic flowchart of another interleaving and modulation method provided by the present application.
  • FIG. 30 is a constellation diagram provided by the present application when the modulation order is equal to 3;
  • FIG. 31 is a BLER performance simulation diagram of different constellation diagrams provided by the present application when the modulation order is equal to 3;
  • FIG. 32 is another constellation diagram provided by the present application when the modulation order is equal to 3;
  • FIG. 33 is another constellation diagram when the modulation order is equal to 3 provided by the present application.
  • Figure 34 is another constellation diagram when the modulation order is equal to 3 provided by this application.
  • Figure 35 is a constellation diagram when the modulation order is equal to 4 provided by the present application.
  • FIG. 36 is another constellation diagram provided by the present application when the modulation order is equal to 4.
  • Fig. 37 is another constellation diagram provided by the present application when the modulation order is equal to 4.
  • Fig. 38 is another constellation diagram provided by the present application when the modulation order is equal to 4.
  • Figure 39 is a constellation diagram when the modulation order is equal to 5 provided by the present application.
  • FIG. 40 is another constellation diagram provided by the present application when the modulation order is equal to 5;
  • Figure 41 is another constellation diagram when the modulation order is equal to 5 provided by this application.
  • Figure 42 is another constellation diagram when the modulation order is equal to 5 provided by this application.
  • FIG. 43 is a schematic diagram of a two-stage interleaving method provided by the present application.
  • Fig. 44 is a schematic diagram of another two-level interleaving method provided by the present application.
  • Fig. 45 is a BLER performance simulation diagram of a two-stage interleaving mode provided by the present application when the modulation order is equal to 5;
  • FIG. 46 is a BLER performance simulation diagram of another two-stage interleaving mode provided by the present application when the modulation order is equal to 5;
  • Fig. 47 is a BLER performance simulation diagram of another two-stage interleaving mode provided by the present application when the modulation order is equal to 5;
  • FIG. 48 is a schematic structural diagram of a sending end device provided by the present application.
  • FIG. 49 is a schematic structural diagram of a receiver device provided by the present application.
  • plural means two or more than two.
  • At least one of the following or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • at least one item (piece) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect. Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity and execution order, and words such as “first” and “second” do not necessarily limit the difference.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. To be precise, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner for easy understanding.
  • references to "an embodiment” throughout the specification mean that a particular feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, various embodiments are not necessarily referring to the same embodiment throughout the specification. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It can be understood that in various embodiments of the present application, the serial numbers of the processes do not mean the order of execution, and the execution order of the processes should be determined by their functions and internal logic, and should not be used in the embodiments of the present application. The implementation process constitutes no limitation.
  • NTN Non-terrestrial network
  • NTN communication includes satellite communication, air to ground (ATG) communication, etc.
  • ATG air to ground
  • NTN can be divided into low altitude platform (low altitude platform, LAP) subnetwork (LAP subnetwork), high altitude platform (high altitude platform, HAP) subnetwork (HAP subnetwork), and Satellite communication subnetwork (SATCOM subnetwork).
  • LAP low altitude platform
  • HAP subnetwork high altitude platform
  • SATCOM subnetwork Satellite communication subnetwork
  • the base station or base station function is deployed on a low-altitude flight platform 0.1km to 1km away from the ground to provide coverage for terminal devices, such as drones; in the HAP subnetwork, the base station or base station function is deployed in a high-altitude flight 1km to 50km away from the ground The platform provides coverage for terminal equipment, such as aircraft; in SATCOM subnetwork, base stations or base station functions are deployed on satellites above 50km from the ground to provide coverage for terminal equipment.
  • satellite communication systems can be divided into the following three types according to different orbital heights: high-orbit (geostationary earth orbit, GEO) satellite communication system, also known as geostationary orbit satellite system; medium-orbit (medium earth orbit, MEO) satellite communication system system and low earth orbit (LEO) satellite communication system.
  • GEO geostationary earth orbit
  • MEO medium-orbit satellite communication system
  • LEO low earth orbit
  • GEO satellites are also generally called geostationary orbit satellites, with an orbital altitude of 35,786 kilometers (km).
  • the main advantage of GEO satellite communication is that it is relatively ground-stationary and provides a large coverage area.
  • its disadvantages are also relatively prominent, such as: 1) The distance between the earth and the earth is too large, requiring a larger-diameter antenna; 2) The transmission delay is relatively large, about 0.5 seconds, which cannot meet the needs of real-time services; 3) Orbit Resources are relatively tight, launch costs are high and they cannot provide coverage to polar regions.
  • MEO satellite communication The orbit height of MEO satellite is 2000 ⁇ 35786km.
  • MEO satellite communication global coverage can be achieved with a relatively small number of satellites, but its transmission delay is higher than that of LEO satellite communication.
  • MEO satellite communication is mainly used for positioning and navigation.
  • the orbital height of LEO satellites is 300-2000km.
  • the orbital height of LEO satellites is lower than that of MEO satellites and GEO satellites.
  • the data transmission delay is small, the power loss is smaller, and the launch cost is relatively lower. Therefore, LEO satellite communication has made considerable progress in recent years and has attracted much attention.
  • PSK phase-shift keying
  • APSK amplitude phase-shift keying
  • DVB-S2 second-generation satellite digital video broadcasting
  • Fig. 1 shows the constellation diagram of 8PSK in the current DVB-S2 standard.
  • the black dot is a constellation point (or can also be described as a symbol), corresponding to 3 bits (bit), which can be expressed as bit2, bit1, and bit0 according to the bits from high to low.
  • the projection of constellation points on the horizontal axis represents the peak amplitude of the in-phase component
  • the projection on the vertical axis represents the peak amplitude of the quadrature component.
  • the length of the line (or vector) from the constellation point to the dot represents the peak amplitude of the signal
  • the angle between the line and the horizontal axis represents the phase.
  • a constellation diagram may also be called a constellation map, and the two may be replaced with each other, which is not specifically limited in this application.
  • Fig. 2 shows a constellation diagram of 16APSK in the DVB-S2 standard, where each constellation point corresponds to 4 bits, which can be expressed as bit3, bit2, bit1, and bit0 according to the order of the bits from high to low.
  • Fig. 3 shows the constellation diagram of 32APSK in the DVB-S2 standard, where each constellation point corresponds to 5 bits, which can be expressed as bit4, bit3, bit2, bit1, bit0 according to the bits from high to low.
  • AWGN additive white Gaussian noise
  • BER bit error ratio
  • SNR signal-to-noise ratio
  • FIG. 5 a simulation result of bit reliability of the constellation diagram shown in FIG. 2 is shown.
  • SNR signal-to-noise ratio
  • FIG. 6 a simulation result of bit reliability for the constellation diagram shown in FIG. 3 is shown. It can be seen from the simulation results that in the 32APSK working SNR range, when 10.8dB ⁇ SNR ⁇ 20.5dB, the reliability of bit3 of 32APSK is the highest, followed by bit2 and bit1, and the reliability of bit4 and bit0 is poor.
  • bit reliability sorting can be shown in Table 1 below. That is, the reliability of middle and low bits of 8PSK, 16APSK, and 32APSK is high, and the reliability of high bits is low.
  • New radio new radio, NR
  • FIG. 7 it is a schematic diagram of data processing at the NR originating end.
  • the source bits (bit source) are added with cyclic redundancy check (cyclical redundancy check, CRC) information, and then undergo low density parity check code (low density parity check code, LDPC) encoding to obtain LDPC coded bits.
  • CRC cyclic redundancy check
  • LDPC low density parity check code
  • constellation mapping After bit interleaving (bit interleaver) and scrambling (scrambler) are performed on the LDPC coded bits, constellation mapping is performed.
  • inverse discrete Fourier transform (inverse discrete fourier transform, IDFT) is performed to obtain a baseband orthogonal frequency division multiplexing (OFDM) signal, and a cyclic prefix (CP) is added to the baseband ODFM signal post launch.
  • IDFT inverse discrete Fourier transform
  • OFDM orthogonal frequency division multiplexing
  • CP cyclic prefix
  • the NR protocol uses row-column interleaving, and uses row-column interleaving to discretize local burst errors into random errors, thereby improving decoding performance.
  • the systematic bits refer to the bits input to the encoder.
  • the systematic bits refer to the bits input to the LDPC encoder.
  • the systematic bits may be the bits after CRC is added to the source bits.
  • NR uses quadrature amplitude modulation (quadrature amplitude modulation, QAM), such as 16QAM, 64QAM. In this modulation mode, higher bits and lower bits have higher reliability.
  • QAM quadrature amplitude modulation
  • the row-column interleaving in the row-column interleaving, first write the LDPC coded bits into the bit matrix column by column, and the column number of the bit matrix is the modulation order (16QAM corresponds to the modulation order 4), the writing order is from the leftmost column to the rightmost column, which can be expressed as [W-1 2 3 4]. After that, read out the bit matrix line by line, and read each line from left to right to form a bit stream, which can be expressed as [R-1 2 3 4].
  • the leftmost bit of each row of bits is the most significant bit (most significant bit, MSB), and the rightmost bit is the least significant bit (least significant bit, LSB).
  • FIG. 9 is a schematic diagram of deinterleaving at the receiving end.
  • the order of de-interleaving and interleaving is reversed. First write the matrix row by row from left to right, and then read it column by column from left to right.
  • FIG. 10 it is a schematic diagram of the composition of LDPC encoded bits, that is, after LDPC encoding, systematic bits come first and non-systematic bits follow.
  • the NR-based interleaving method can map the systematic bits of the LDPC coded bits to high-order bits.
  • high-order bits and low-order bits have higher reliability, therefore, in NR, systematic bits can be mapped to high-order bits to obtain better decoding performance.
  • the present application provides a data processing method
  • the data processing method may include an interleaving and modulation method applied to a sending end device, and a deinterleaving and demodulation method applied to a receiving end device.
  • This method can improve the decoding performance of the system when the NR protocol is adapted to the satellite communication, thereby improving the transmission reliability.
  • the technical solutions of the embodiments of the present application can be used in various communication systems, such as: orthogonal frequency-division multiple access (OFDMA), single carrier frequency-division multiple access (single carrier FDMA, SC-FDMA), satellite Communication system, NTN system, Internet of things (IoT) system, or future evolved communication system, etc.
  • OFDMA orthogonal frequency-division multiple access
  • single carrier frequency-division multiple access single carrier frequency-division multiple access
  • SC-FDMA single carrier frequency-division multiple access
  • the technical solution of the embodiment of the present application can be applied to various communication scenarios, for example, it can be applied to one or more of the following communication scenarios: enhanced mobile broadband (eMBB), ultra-reliable low-latency communication (ultra reliable low latency communication (URLLC), machine type communication (machine type communication, MTC), large-scale machine type communication (massive machine type communication, mMTC), device-to-device (device-to-device, D2D), vehicle to network (vehicle to everything, V2X), or IoT and other communication scenarios.
  • eMBB enhanced mobile broadband
  • URLLC ultra-reliable low-latency communication
  • MTC machine type communication
  • MTC massive-scale machine type communication
  • mMTC massive machine type communication
  • D2D device-to-device
  • V2X vehicle to everything
  • IoT and other communication scenarios IoT and other communication scenarios.
  • the technical solutions of the embodiments of the present application can also be applied to long-distance communication scenarios, such as satellite communication scenarios where the distance between terminal devices and network devices is constantly changing, or other long-distance communication scenarios, etc., without limitation.
  • FIG. 11 it is a schematic structural diagram of a communication system provided by the present application.
  • the communication system includes a sending end device and a receiving end device.
  • the sending end device may be a terminal device, and correspondingly, the receiving end device is a network device; or, the sending end device may be a network device, and correspondingly, the receiving end device is a terminal device; or, the sending end device and the receiving end device The devices are both terminal devices; or, both the sending-end device and the receiving-end device are network devices.
  • the communication system includes at least one network device 30 and one or more terminal devices 40 connected to the network device 30 as an example for illustration. It should be understood that the numbers of terminal devices and network devices in FIG. 12 are only examples, and may be more or less.
  • the terminal device 40 can be used as the sending end device, and correspondingly, the network device 30 can be used as the receiving end device; or, the terminal device 40 can be used as the receiving end device, and correspondingly, the network device 30 can be used as the receiving end device. 30 as the sending end device.
  • the network device 30 in the embodiment of the present application may be deployed on a high-altitude platform or a satellite.
  • the network device 30 is a device for connecting the terminal device 40 to a wireless network.
  • the network device 30 may be a node in a wireless access network, may also be called a base station, and may also be called a wireless access network ( radio access network, RAN) node (or device).
  • RAN radio access network
  • the network equipment may include an evolved base station (NodeB or eNB or e-NodeB, evolutional Node B) in a long term evolution (long term evolution, LTE) system or an evolved LTE system (LTE-Advanced, LTE-A), such as Traditional macro base station eNB and micro base station eNB in heterogeneous network scenarios.
  • a next generation node B (next generation node B, gNB) in the NR system may be included.
  • transmission reception point transmission reception point
  • home base station for example, home evolved NodeB, or home Node B, HNB
  • base band unit base band unit, BBU
  • base band pool BBU pool or WiFi access Access point (access point, AP) and so on.
  • it may include a centralized unit (centralized unit, CU) and/or a distributed unit (distributed unit, DU) in a cloud access network (cloud radio access network, CloudRAN) system.
  • cloud access network cloud radio access network, CloudRAN
  • it can include base stations in NTN, that is, they can be deployed on high-altitude platforms or satellites.
  • network equipment can be used as layer 1 (L1) relays, or as base stations, or as DUs, or as Access to integrated access and backhual (IAB) nodes.
  • the network device may be a device that implements a base station function in IoT, such as a device that implements a base station function in V2X, D2D, or machine to machine (M2M), which is not limited in this embodiment of the present application.
  • the base station in the embodiment of the present application may include various forms of base stations, for example: macro base stations, micro base stations (also called small stations), relay stations, access points, home base stations, TRPs, transmitting point (transmitting point) , TP), mobile switching center, etc., which are not specifically limited in this embodiment of the present application.
  • the terminal device 40 in this embodiment of the present application may be a device for implementing wireless communication functions, such as a terminal or a chip that may be used in a terminal.
  • the terminal may be user equipment (user equipment, UE), access terminal, terminal unit, terminal station, mobile station, mobile station, Remote station, remote terminal, mobile device, wireless communication device, terminal agent or terminal device, etc.
  • An access terminal may be a cellular telephone, a cordless telephone, a session initiation protocol (SIP) telephone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a Functional handheld devices, computing devices or other processing devices connected to wireless modems, vehicle-mounted devices or wearable devices, virtual reality (virtual reality, VR) terminal equipment, augmented reality (augmented reality, AR) terminal equipment, industrial control (industrial Wireless terminals in control, wireless terminals in self driving, wireless terminals in remote medical, wireless terminals in smart grid, wireless terminals in transportation safety Terminals, wireless terminals in smart cities, wireless terminals in smart homes, etc.
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • the terminal may be a terminal with a communication function in IoT, such as a terminal in V2X (such as a vehicle networking device), a terminal in D2D communication, or a terminal in M2M communication.
  • Terminals can be mobile or fixed.
  • the network device 30 and the terminal device 40 in the embodiment of the present application may also be referred to as communication devices, which may be a general-purpose device or a dedicated device, which is not specifically limited in the embodiment of the present application.
  • FIG. 13 it is a schematic structural diagram of a network device 30 and a terminal device 40 provided in this embodiment of the present application.
  • the terminal device 40 includes at least one processor (in FIG. 13, it is illustrated by including a processor 401 as an example) and at least one transceiver (in FIG. 13, it is illustrated by an example by including a transceiver 403 ).
  • the terminal device 40 may also include at least one memory (in FIG. 13, a memory 402 is used as an example for illustration), at least one output device (in FIG. 13, an output device 404 is used as an example) description) and at least one input device (in FIG. 13, an input device 405 is used as an example for illustration).
  • a communication line may include a path for transferring information between the above-mentioned components.
  • the processor 401 can be a general-purpose central processing unit (central processing unit, CPU), a microprocessor, a specific application integrated circuit (application-specific integrated circuit, ASIC), or one or more integrated circuits used to control the execution of the program program of this application. circuit.
  • the processor 401 may also include multiple CPUs, and the processor 401 may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.
  • a processor herein may refer to one or more devices, circuits, or processing cores for processing data such as computer program instructions.
  • the memory 402 may be a device having a storage function. For example, it may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or other types of memory that can store information and instructions
  • a dynamic storage device can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired program code in the form of instructions or data structures and can be stored by a computer Any other medium, but not limited to it.
  • the memory 402 may exist independently and be connected to the processor 401 through a communication line.
  • the memory 402 can also be integrated with the processor 401 .
  • the memory 402 is used to store computer-executed instructions for implementing the solution of the present application, and the execution is controlled by the processor 401 .
  • the processor 401 is configured to execute computer-executed instructions stored in the memory 402, so as to implement the methods described in the embodiments of the present application.
  • the computer-executed instructions in the embodiments of the present application may also be referred to as application program codes or computer program codes, which are not specifically limited in the embodiments of the present application.
  • Transceiver 403 may use any transceiver-like device for communicating with other devices or communication networks.
  • the transceiver 403 may include a transmitter (transmitter, Tx) and a receiver (receiver, Rx).
  • Output device 404 is in communication with processor 401 and may display information in a variety of ways.
  • the output device 404 may be a liquid crystal display (liquid crystal display, LCD), a light emitting diode (light emitting diode, LED) display device, a cathode ray tube (cathode ray tube, CRT) display device, or a projector (projector), etc.
  • the input device 405 communicates with the processor 401 and can receive user input in various ways.
  • the input device 405 may be a mouse, a keyboard, a touch screen device, or a sensing device, among others.
  • the network device 30 includes at least one processor (in FIG. 13, a processor 301 is used as an example for illustration) and at least one transceiver (in FIG. 13, a transceiver 303 is used as an example for illustration).
  • the network device 30 may also include at least one memory (in FIG. 13, a memory 302 is used as an example for illustration) and at least one network interface (in FIG. 13, a network interface 304 is used as an example Be explained).
  • the processor 301, the memory 302, the transceiver 303 and the network interface 304 are connected through communication lines.
  • the network interface 304 is used to connect to the core network equipment through a link (such as an S1 interface), or connect to a network interface of other network equipment (not shown in FIG.
  • the structure shown in FIG. 13 does not constitute a specific limitation on the network device 30 or the terminal device 40 .
  • the network device 30 or the terminal device 40 may include more or fewer components than those shown in FIG. 13 , or combine some components, or split some components, or different components layout.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • the sending end device and/or the receiving end device may perform some or all of the steps in the embodiment of the present application, these steps or operations are only examples, and the embodiment of the present application may also perform other operations or Variations for various operations.
  • each step may be performed in a different order presented in the embodiment of the present application, and it may not be necessary to perform all operations in the embodiment of the present application.
  • a data processing method provided by an embodiment of the present application includes an interleaving and modulation method applied to a device at a sending end, and a method of deinterleaving and demodulation applied to a device at a receiving end.
  • the method comprises the steps of:
  • the device at the sending end acquires bits to be interleaved.
  • the bits to be interleaved may be coded bits.
  • the bits to be interleaved are bits obtained by performing the second interleaving on the coded bits. Details will be described in subsequent embodiments, and will not be repeated here.
  • the encoded bits refer to bits obtained by encoding bits input to the encoder by the encoder.
  • the coded bits may be LDPC coded bits, or may be other types of coded bits, such as polar codes or turbo codes, and the application does not specifically limit the type of coded bits.
  • the device at the sending end performs first interleaving on the bits to be interleaved to obtain interleaved bits.
  • the first interleaving includes: writing the bits to be interleaved into the first matrix column by column in a first order, and reading out the bits from the first matrix row by row in a second order.
  • the number of columns of the first matrix is the modulation order M, and M is greater than or equal to 3.
  • the first bit read out row by row is the MSB, and the Mth bit is the LSB.
  • each row of bits read constitutes a bit stream.
  • the leftmost bit of each row of bits is the MSB, and the rightmost bit is the LSB.
  • the number N of bits to be interleaved cannot be divisible by M
  • the number of rows of the first matrix can be in, Indicates rounding down.
  • the bits to be interleaved bits may not participate in the first interleaving.
  • the number of rows of the first matrix can be in, Indicates rounding up.
  • the bits to be interleaved can be supplemented 0, and then perform the first interleaving on the bits after the 0 complement.
  • the first interleaving may include: writing the bits to be interleaved row by row into the first matrix according to the third order, and reading out the bits from the first matrix column by column according to the fourth order.
  • the number of rows of the first matrix is the modulation order M, and M is greater than or equal to 3.
  • the first bit read out column by column is the MSB and the last bit is the LSB.
  • the columns of the first order may be replaced with rows to obtain the third order.
  • Columns of the second order are replaced by rows to obtain the fourth order.
  • the device at the sending end modulates the interleaved bits to obtain modulation symbols.
  • the modulation mode used by the device at the sending end may be a related modulation mode defined in the DVB-S2 standard.
  • the device at the sending end sends modulation symbols.
  • the receiver device receives the modulation symbols.
  • the sending the modulation symbol by the device at the sending end may include: outputting the modulation symbol by a modulation module of the device at the sending end. After the modulation module outputs modulation symbols, other modules of the transmitting end device may perform IDFT on the modulation symbols and add a cyclic prefix to generate a transmission signal, and send the transmission signal to the receiving end device.
  • the device at the receiving end may receive the signal after the transmission signal is transmitted through the channel, and perform operations such as removing CP and DFT on the received signal to obtain modulation symbols. That is, receiving the modulation symbols by the receiver device may include: receiving (or inputting) the modulation symbols by a demodulation module of the receiver device.
  • the device at the receiving end demodulates the modulation symbols to obtain a logarithmic likelihood ratio (logarithm likelihood ratio, LLR) sequence to be deinterleaved.
  • LLR logarithmic likelihood ratio
  • the modulation mode corresponding to the demodulation is the modulation mode used by the device at the sending end in step S1403. It will be described in subsequent embodiments, and will not be repeated here.
  • the device at the receiving end performs first deinterleaving on the LLR sequence to be deinterleaved to obtain a first deinterleaved LLR sequence.
  • the first deinterleaving includes: writing the LLR sequences to be deinterleaved into the second matrix row by row according to the second order, and reading them out from the second matrix column by column according to the first order.
  • the number of columns of the second matrix is the modulation order M, and the number of rows of the second matrix can refer to the relevant description of the first matrix, which will not be repeated here.
  • the first bit written row by row is the MSB, and the Mth bit is the LSB.
  • the device at the receiving end determines information bits according to the deinterleaved first LLR sequence.
  • the device at the receiving end may decode the deinterleaved first LLR sequence to obtain information bits.
  • the device at the receiving end may perform second deinterleaving on the deinterleaved first LLR sequence to obtain a deinterleaved second LLR sequence. Decoding the deinterleaved second LLR sequence to obtain information bits. Details will be described in subsequent embodiments, and will not be repeated here.
  • the receiver device can obtain the content sent by the sender device, so that it can perform corresponding processing according to the content, which is not specifically limited in this application.
  • the columns of the first matrix are sorted from left to right, the leftmost column is the first column, the rightmost column is the Mth column, and the numbers are column 1 and column 2 in sequence , ..., column M.
  • M columns of the first matrix may correspond to M bits.
  • the first column corresponds to the highest bit
  • the Mth column corresponds to the lowest bit.
  • the first order and the second order may have the following two situations:
  • the first order is associated with the bit reliability of the bits in the modulation scheme.
  • the bit corresponding to the column of the first bit to be interleaved can be the bit with the highest bit reliability, and the bit reliability corresponding to the column of the next bit to be interleaved is next or equal to it, and so on , the bit reliability corresponding to the column in which the bit to be interleaved is written last is the lowest.
  • the second order may be the arrangement order of the columns of the first matrix. For example, when M is equal to 3, the second order is the first column-second column-third column of the first matrix.
  • the first order is the arrangement order of the columns of the first matrix.
  • the first sequence is the first column-second column-third column of the first matrix.
  • the second order is associated with the bit reliability of the bits in the modulation scheme.
  • the bit corresponding to the first read column can be the bit with the highest bit reliability, the bit reliability of the bit corresponding to the next read column is second or equal to it, and so on, the last read column The corresponding bit has the lowest bit reliability.
  • the modulation method used when the transmitting end device performs modulation in the above step S1403 is DVB-S2 8PSK, and the constellation diagram is as shown in Figure 1.
  • the first sequence and the second sequence in the above steps S1402 and S1406 can be implemented in the following three ways:
  • the first order is the third column-second column-first column of the first matrix, which can be expressed as [W-3 2 1].
  • the second order is the first column-second column-third column of the first matrix, which can be expressed as [R-1 2 3].
  • the implementation of the method 11 belongs to the first case above.
  • the third column - the second column - the first column of the first matrix correspond to bit0, bit1, bit2 of DVB-S2 8PSK respectively.
  • FIG. 15 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 11. Assuming that the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 and the systematic bits are a 0 a 1 a 2 , according to the interleaving pattern shown in Figure 15, the sending end device will be interleaved After the bits of the first matrix are written column by column, the third column of the first matrix is written into a 0 a 1 a 2 , the second column is written into a 3 a 4 a 5 , and the first column is written into a 6 a 7 a 8 . Subsequently, a 6 a 3 a 0 is read in the first row, a 7 a 4 a 1 is read in the second row, and a 8 a 5 a 2 is read in the third row.
  • bit0 has higher reliability than bit2, so when the system bit is transmitted in bit0, the transmission reliability of the system bit can be improved, and then the decoding performance of the system can be improved.
  • FIG 16a shows the block error rate (block error rate, BLER) performance comparison between the NR interleaving mode and the interleaving mode shown in mode 11 when the modulation mode is DVB-S2 8PSK.
  • BLER block error rate
  • 240:40:1160 in Table 2 indicates that the minimum value of the number of system bits is 240, and the increment is incremented by 40 until it reaches the maximum value of 1160.
  • the LDPC codes in Table 2 are the bits to be interleaved.
  • K in FIG. 16a is the number of systematic bits
  • N is the number of bits to be interleaved
  • M is the modulation order.
  • the SNR of the interleaving scheme 11 shown in Figure 15 is 0.1 ⁇ 1.2dB lower than that of the NR interleaving scheme, that is, for the same BLER, the SNR requirement of the interleaving scheme 11 shown in Figure 15 lower. That is to say, the BLER performance can be improved by 0.1 to 1.2 dB when the interleaving method 11 shown in Fig. 15 is used.
  • the third sequence may be the third row-the second row-the first row of the first matrix. That is, first write in the third row, then write in the second row, and finally write in the first row.
  • the fourth sequence may be the first row-the second row-the third row of the first matrix, that is, when each column is read, the first row is read first, then the second row, and finally the third row.
  • each column is read in left-to-right order. That is, first read the first row-second row-third row of the first column, then read the first row-second row-third row of the second column, and finally read the first row-second row of the third column -The third row.
  • the interleaving pattern is shown in Figure 16b.
  • the sending end device will After the bits are written into the first matrix column by column, a 0 a 1 a 2 is written in the third row of the first matrix, a 3 a 4 a 5 is written in the second row, and a 6 a 7 a 8 is written in the first row. Subsequently, the first column reads a 6 a 3 a 0 , the second column reads a 7 a 4 a 1 , and the third column reads a 8 a 5 a 2 .
  • each implementation of the first sequence and the second sequence may correspond to an implementation of the third sequence and the fourth sequence, and reference may be made to the above step S1402 and related descriptions in mode 11. No further details will be given later.
  • the first order is the second column-third column-first column of the first matrix, which can be expressed as [W-2 3 1].
  • the second order is the first column-second column-third column of the first matrix, which can be expressed as [R-1 2 3].
  • FIG. 17 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 12.
  • the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 and the systematic bits are a 0 a 1 a 2
  • the sending end device will be interleaved
  • a 0 a 1 a 2 is written in the second column of the first matrix
  • a 3 a 4 a 5 is written in the third column
  • a 6 a 7 a 8 is written in the first column .
  • a 6 a 0 a 3 is read in the first row
  • a 7 a 1 a 4 is read in the second row
  • a 8 a 2 a 5 is read in the third row.
  • bit1 Based on the interleaving scheme, the systematic bit can be mapped on bit1 for transmission.
  • bit1 In DVB-S2 8PSK modulation, bit1 has higher reliability than bit2, so the system bit transmission in bit1 can improve the transmission reliability of system bits compared with bit2 transmission, and then improve the decoding performance of the system.
  • the first order is the first column-second column-third column of the first matrix, which can be expressed as [W-1 2 3].
  • the second order is the second column-third column-first column of the first matrix, which can be expressed as [R-2 3 1].
  • FIG. 18 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 13. Assuming that the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 and the systematic bits are a 0 a 1 a 2 , according to the interleaving pattern shown in Figure 18, the sending end device will be interleaved After the bits of the first matrix are written column by column, the first column of the first matrix is written into a 0 a 1 a 2 , the second column is written into a 3 a 4 a 5 , and the third column is written into a 6 a 7 a 8 . Subsequently, a 3 a 6 a 0 is read in the first row, a 4 a 7 a 1 is read in the second row, and a 5 a 8 a 2 is read in the third row.
  • the system bit can be mapped to the lowest bit for transmission.
  • DVB-S2 8PSK modulation low-order bits and high-order bits have higher reliability, so that the transmission reliability of system bits can be improved in the lowest-order transmission of system bits compared with high-order bits, and then the reliability of the system can be improved. decoding performance.
  • the modulation method used by the transmitting end device in the above step S1403 for modulation is DVB-S2 16APSK, and the constellation diagram is shown in Figure 2.
  • the first sequence and the second sequence in the above steps S1402 and S1406 can be implemented in the following four ways:
  • the first order is the fourth column-third column-second column-first column of the first matrix, which can be expressed as [W-4 3 2 1].
  • the second order is the first column-second column-third column-fourth column of the first matrix, which can be expressed as [R-1 2 3 4].
  • FIG. 19 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 21.
  • the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 and the systematic bits are a 0 a 1 a 2 .
  • the transmitting device After the transmitting device writes the bits to be interleaved into the first matrix column by column, the fourth column of the first matrix is written into a 0 a 1 a 2 , the third column is written into a 3 a 4 a 5 , and the second column is written into a 6 a 7 a 8 , write a 9 a 10 a 11 in the first column.
  • the first row reads a 9 a 6 a 3 a 0
  • the second row reads a 10 a 7 a 4 a 1
  • the third row reads a 11 a 8 a 5 a 2 .
  • bit0 has higher reliability than bit3, so when the system bit is transmitted in bit0, the transmission reliability of the system bit can be improved, thereby improving the decoding performance of the system.
  • the SNR of the interleaving method 21 is 0.1-0.7dB lower than that of the NR interleaving method, that is, for the same BLER, the interleaving method 21 has lower requirements on the SNR. That is to say, when the interleaving mode 21 is adopted, the BLER performance can be improved by 0.1-0.7 dB.
  • the first order is the fourth column-third column-first column-second column of the first matrix, which can be expressed as [W-4 3 1 2].
  • the second order is the first column-second column-third column-fourth column of the first matrix, which can be expressed as [R-1 2 3 4].
  • FIG. 21 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 22.
  • the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 and the systematic bits are a 0 a 1 a 2 .
  • the transmitting device After the transmitting device writes the bits to be interleaved into the first matrix column by column, the fourth column of the first matrix is written into a 0 a 1 a 2 , the third column is written into a 3 a 4 a 5 , and the second column is written into a 9 a 10 a 11 , write a 6 a 7 a 8 in the first column.
  • the first row reads a 6 a 9 a 3 a 0
  • the second row reads a 7 a 10 a 4 a 1
  • the third row reads a 8 a 11 a 5 a 2 .
  • bit0 has higher reliability than bit3, so when the system bit is transmitted in bit0, the transmission reliability of the system bit can be improved, thereby improving the decoding performance of the system.
  • the first order is the third column-fourth column-second column-first column of the first matrix, which can be expressed as [W-3 4 2 1].
  • the second order is the first column-second column-third column-fourth column of the first matrix, which can be expressed as [R-1 2 3 4].
  • FIG. 22 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 23.
  • the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 and the systematic bits are a 0 a 1 a 2 , according to the interleaving pattern shown in Figure 22,
  • the transmitting device writes the bits to be interleaved into the first matrix column by column
  • the fourth column of the first matrix is written into a 3 a 4 a 5
  • the third column is written into a 0 a 1 a 2
  • the second column is written into a 6 a 7 a 8 , write a 9 a 10 a 11 in the first column.
  • the first row reads a 9 a 6 a 0 a 3
  • the second row reads a 10 a 7 a 1 a 4
  • the third row reads a 11 a 8 a 2 a 5 .
  • bit1 has higher reliability than bit3 or bit2, so when the system bit is transmitted in bit1, the transmission reliability of the system bit can be improved, thereby improving the decoding performance of the system.
  • the first order is the third column-fourth column-first column-second column of the first matrix, which can be expressed as [W-3 4 1 2].
  • the second order is the first column-second column-third column-fourth column of the first matrix, which can be expressed as [R-1 2 3 4].
  • FIG. 23 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 24.
  • the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 and the systematic bits are a 0 a 1 a 2 .
  • the transmitting device After the transmitting device writes the bits to be interleaved into the first matrix column by column, the fourth column of the first matrix is written into a 3 a 4 a 5 , the third column is written into a 0 a 1 a 2 , and the second column is written into a 9 a 10 a 11 , write a 6 a 7 a 8 in the first column.
  • the first row reads a 6 a 9 a 0 a 3
  • the second row reads a 7 a 10 a 1 a 4
  • the third row reads a 8 a 11 a 2 a 5 .
  • the system bit can also be mapped to bit1 for transmission, thereby improving the transmission reliability of the system bit and further improving the decoding performance of the system.
  • the modulation method used by the transmitting end device in the above step S1403 for modulation is DVB-S2 32APSK, and the constellation diagram is shown in Figure 3.
  • the first sequence and the second sequence in the above steps S1402 and S1406 can be implemented in the following four ways:
  • the first sequence is the fourth column-third column-second column-first column-fifth column of the first matrix, which can be expressed as [W-4 3 2 1 5].
  • the second order is the first column-second column-third column-fourth column-fifth column of the first matrix, which can be expressed as [R-1 2 3 4 5].
  • FIG. 24 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 31.
  • the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14
  • the systematic bits are a 0 a 1 a 2
  • the interleaving pattern after the transmitting device writes the bits to be interleaved into the first matrix column by column, the fourth column of the first matrix is written into a 0 a 1 a 2 , and the third column is written into a 3 a 4 a 5 , write a 6 a 7 a 8 in the second column, a 9 a 10 a 11 in the first column, and a 12 a 13 a 14 in the fifth column.
  • the first row reads a 9 a 6 a 3 a 0 a 12
  • the second row reads a 10 a 7 a 4 a 1 a 13
  • the third row reads a 11 a 8 a 5 a 2 a 14 .
  • bit1 Based on the interleaving scheme, the systematic bits can be mapped to bit1 for transmission. It can be seen from Table 1 that in DVB-S2 32APSK modulation, bit1 has higher reliability than bit4, so when the system bit is transmitted in bit1, the transmission reliability of the system bit can be improved, and then the decoding performance of the system can be improved.
  • the SNR of the interleaving method 31 is 0.1-0.25dB lower than that of the NR interleaving method, that is, for the same BLER, the interleaving method 31 has lower requirements on the SNR. That is to say, when the interleaving mode 31 is adopted, the BLER performance can be improved by 0.1-0.5 dB.
  • the first order is the fourth column-second column-third column-first column-fifth column of the first matrix, which can be expressed as [W-4 2 3 1 5].
  • the second order is the first column-second column-third column-fourth column-fifth column of the first matrix, which can be expressed as [R-1 2 3 4 5].
  • FIG. 26 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 32.
  • the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14
  • the systematic bits are a 0 a 1 a 2
  • the interleaving pattern after the transmitting device writes the bits to be interleaved into the first matrix column by column, the fourth column of the first matrix is written into a 0 a 1 a 2 , and the second column is written into a 3 a 4 a 5 , write a 9 a 10 a 11 in the first column, a 6 a 7 a 8 in the third column, and a 12 a 13 a 14 in the fifth column.
  • the first row reads a 9 a 6 a 3 a 0 a 12
  • the second row reads a 10 a 4 a 7 a 1 a 13
  • the third row reads a 11 a 5 a 8 a 2 a 14 .
  • the systematic bit can also be mapped to bit1 for transmission. Therefore, the transmission reliability of system bits can be improved, and the decoding performance of the system can be further improved.
  • the first sequence is the fourth column-third column-second column-fifth column-first column of the first matrix, which can be expressed as [W-4 3 2 5 1].
  • the second order is the first column-second column-third column-fourth column-fifth column of the first matrix, which can be expressed as [R-1 2 3 4 5].
  • FIG. 27 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in Mode 33.
  • the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14
  • the systematic bits are a 0 a 1 a 2
  • the interleaving pattern after the transmitting device writes the bits to be interleaved into the first matrix column by column, the fourth column of the first matrix is written into a 0 a 1 a 2 , and the third column is written into a 3 a 4 a 5 , write a 6 a 7 a 8 in the second column, a 9 a 10 a 11 in the fifth column, and a 13 a 14 a 15 in the first column.
  • the first row reads a 13 a 6 a 3 a 0 a 9
  • the second row reads a 14 a 7 a 4 a 1 a 10
  • the third row reads a 15 a 8 a 5 a 2 a 11 .
  • the first sequence is the fourth column-second column-third column-fifth column-first column of the first matrix, which can be expressed as [W-4 2 3 5 1].
  • the second order is the first column-second column-third column-fourth column-fifth column of the first matrix, which can be expressed as [R-1 2 3 4 5].
  • FIG. 28 it shows the pattern of column-by-column writing and row-by-row reading by the sending-end device described in mode 34.
  • the bits to be interleaved are a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14
  • the systematic bits are a 0 a 1 a 2
  • the interleaving pattern after the transmitting device writes the bits to be interleaved into the first matrix column by column, the fourth column of the first matrix is written into a 0 a 1 a 2 , and the second column is written into a 3 a 4 a 5 , write a 6 a 7 a 8 in the third column, a 9 a 10 a 11 in the fifth column, and a 13 a 14 a 15 in the first column.
  • the first row reads a 13 a 3 a 6 a 0 a 9
  • the second row reads a 14 a 4 a 7 a 1 a 10
  • the third row reads a 15 a 5 a 8 a 2 a 11 .
  • the system bit can also be mapped to bit1 for transmission, so that the transmission reliability of the system bit can be improved, and thus the decoding performance of the system can be improved.
  • the modulation method used by the sending end device is a derivative method based on DVB-S2
  • the first sequence or the second sequence can also be changed accordingly to adapt to the derivative method, so that the system bits can be mapped in bit transmission.
  • the first order corresponding to the derivation method can be: DVB-S2
  • the sequence of columns corresponding to bit2 and bit1 is exchanged.
  • the first sequence corresponding to DVB-S2 8PSK is the third column-second column-first column
  • the third column-second column-first column corresponds to bit0, bit1, bit2, after swapping, the first sequence corresponding to this derivation method can be: the third column-the first column-the second column.
  • the second sequence is still the first column-second column-third column of the first matrix. That is to say, the first order changes with the exchange of values of different bits corresponding to each constellation point, and the second order remains unchanged.
  • the second order may be changed according to the exchange of the values of different bits corresponding to each constellation point in a similar manner, and the first order remains unchanged.
  • the second sequence corresponding to the derivation method can be: DVB-S2
  • the sequence of columns corresponding to bit2 and bit1 is exchanged.
  • the second sequence corresponding to DVB-S2 8PSK is the first column-second column-third column, and the first column-second column-third column corresponds to bit2, bit1,
  • the second sequence corresponding to this derivation method can be: second column-first column-third column. The first order does not change.
  • the present application proposes a new interleaving method.
  • the interleaving method is used in combination with the modulation method in satellite communication, the system bits can be mapped to bits with higher reliability for transmission, thereby improving transmission reliability and The decoding performance of the system.
  • another data processing method provided by the embodiment of the present application includes an interleaving and modulation method applied to a sending-end device, and a de-interleaving and demodulation method applied to a receiving-end device.
  • the method comprises the steps of:
  • the device at the sending end acquires bits to be interleaved.
  • the bits to be interleaved may be coded bits.
  • the bits to be interleaved are the bits after performing the second interleaving on the coded bits. Reference may be made to relevant descriptions in the above step S1401, which will not be repeated here.
  • the device at the sending end performs first interleaving on the bits to be interleaved to obtain interleaved bits.
  • the first interleaving includes: writing the bits to be interleaved into the first matrix column by column in order from left to right, and reading out the bits from the first matrix row by row in order from left to right.
  • the number of columns of the first matrix is the modulation order M, and M is greater than or equal to 3.
  • the first bit read out row by row is the MSB, and the Mth bit is the LSB.
  • the device at the sending end modulates the interleaved bits to obtain modulation symbols.
  • the constellation diagram used for modulation includes 2 M constellation points, and the 2 M constellation points are distributed on N rings, and the constellation points on at least one of the N rings satisfy the principle of Gray mapping, and N is positive integer.
  • the device at the sending end sends modulation symbols.
  • the receiver device receives the modulation symbols.
  • step S2904 for the related implementation of step S2904, reference may be made to the detailed description in the above step S1404, which will not be repeated here.
  • the device at the receiving end demodulates the modulation symbols to obtain an LLR sequence to be deinterleaved.
  • the constellation diagram of the modulation mode corresponding to the demodulation is the constellation diagram described in step S2903.
  • the device at the receiving end performs first deinterleaving on the LLR sequence to be deinterleaved to obtain a first deinterleaved LLR sequence.
  • the first deinterleaving includes: writing the LLR sequence to be deinterleaved into the second matrix row by row in order from left to right, and reading out from the second matrix column by row in order from left to right.
  • the number of columns of the second matrix is the modulation order M, and the number of rows of the second matrix can refer to the relevant description of the first matrix, which will not be repeated here.
  • the first bit written row by row is the MSB, and the Mth bit is the LSB.
  • the device at the receiving end determines information bits according to the deinterleaved first LLR sequence.
  • step S2907 for related implementation of step S2907, reference may be made to the detailed description in the above step S1407, which will not be repeated here.
  • the constellation diagram in the above step S2903 includes 8 constellation points, and the 8 constellation points are evenly distributed on a circle.
  • the distribution of 8 constellation points can be implemented in the following four ways:
  • Mode 41 As shown in FIG. 30 , the phase corresponding to the first constellation point is ⁇ /4.
  • the bit corresponding to the first constellation point is 000.
  • the bits corresponding to the remaining seven constellation points are: 010, 011, 111, 110, 100, 101, and 001, respectively.
  • FIG. 31 shows a comparison of BLER performance when using the first interleaving described in step S2902 , using the DVB-S28PSK shown in FIG. 2 and the constellation shown in way 41.
  • the simulation conditions are shown in Table 5 below.
  • the SNR of using the constellation diagram shown in Figure 30 is 0.1 ⁇ 1.2dB lower than that of using the constellation diagram shown in Figure 2, that is, the BLER performance when using the constellation diagram shown in Figure 30 can be Increase 0.1 ⁇ 1.2dB.
  • Mode 42 As shown in FIG. 32 , the phase corresponding to the first constellation point is ⁇ /4. The bit corresponding to the first constellation point is 000. Taking the first constellation point as a reference and clockwise, the bits corresponding to the remaining seven constellation points are: 100, 101, 111, 110, 010, 011, and 001.
  • Mode 43 As shown in FIG. 33 , the phase corresponding to the first constellation point is ⁇ /8.
  • the bit corresponding to the first constellation point is 000.
  • the bits corresponding to the remaining seven constellation points are: 010, 011, 111, 110, 100, 101, and 001.
  • Mode 44 As shown in FIG. 34 , the phase corresponding to the first constellation point is ⁇ /8.
  • the bit corresponding to the first constellation point is 000.
  • the bits corresponding to the remaining seven constellation points are: 100, 101, 111, 110, 010, 011, and 001.
  • the constellation diagram in the above step S2903 includes 16 constellation points, 4 constellation points in the 16 constellation points are evenly distributed on the first ring, and the other 12 constellation points are evenly distributed on the second ring. on the ring.
  • the first circular ring and the second circular ring are concentric rings.
  • the phase corresponding to the first constellation point on the first ring and the second constellation point on the second ring is ⁇ /4.
  • the distribution of 16 constellation points can be implemented in the following four ways:
  • the bit corresponding to the first constellation point is 0011.
  • the bits corresponding to the remaining 3 constellation points on the first ring are: 0111 , 1111, 1011.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0001, 0101, 0100, 0110, 1110, 1100, 1101, 1001, 1000, 1010, 0010.
  • the phases corresponding to 0011 and 0000 are ⁇ /4, and the phases corresponding to 0001 are ⁇ /12.
  • R1 represents the radius of the first circular ring, and R2 represents the radius of the second circular ring.
  • the bit corresponding to the first constellation point is 0011, taking the first constellation point as a reference, and clockwise, the bits corresponding to the remaining 3 constellation points on the first ring are: 0111 , 1111, 1011.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0010, 0110, 0100, 0101, 1101, 1100, 1110, 1010, 1000, 1001, 0001.
  • the phases corresponding to 0011 and 0000 are ⁇ /4, and the phases corresponding to 0010 are ⁇ /12.
  • R1 represents the radius of the first circular ring, and R2 represents the radius of the second circular ring.
  • the constellation diagram shown in FIG. 36 can be obtained by exchanging the values of bit0 and bit1 in the constellation diagram shown in FIG. 35 .
  • the bit corresponding to the first constellation point is 0011, taking the first constellation point as a reference, and following the clockwise direction, the bits corresponding to the remaining 3 constellation points on the first ring are: 1011 , 1111, 0111.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0001, 1001, 1000, 1010, 1110, 1100, 1101, 0101, 0100, 0110, 0010.
  • the phases corresponding to 0011 and 0000 are ⁇ /4, and the phases corresponding to 0001 are ⁇ /12.
  • R1 represents the radius of the first circular ring, and R2 represents the radius of the second circular ring.
  • the constellation diagram shown in FIG. 37 can be obtained by exchanging the values of bit2 and bit3 in the constellation diagram shown in FIG. 35 .
  • the bit corresponding to the first constellation point is 0011, taking the first constellation point as a reference, and clockwise, the bits corresponding to the remaining 3 constellation points on the first ring are: 1011 , 1111, 0111.
  • the bit corresponding to the second constellation point is 0000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 0010, 1010, 1000, 1001, 1101, 1100, 1110, 0110, 0100, 0101, 0001.
  • the phases corresponding to 0011 and 0000 are ⁇ /4, and the phases corresponding to 0010 are ⁇ /12.
  • R1 represents the radius of the first circular ring, and R2 represents the radius of the second circular ring.
  • the constellation diagram shown in FIG. 38 may be obtained by exchanging the values of bit0 and bit1 and the values of bit2 and bit3 in the constellation diagram shown in FIG. 35 .
  • the constellation diagram in the above step S2903 includes 32 constellation points, 4 constellation points in the 32 constellation points are evenly distributed on the first ring, and the other 12 constellation points are evenly distributed on the second ring. On the ring, the remaining 16 constellation points are evenly distributed on the third ring.
  • the first circular ring, the second circular ring, and the third circular ring are concentric rings.
  • the phases corresponding to the first constellation point on the first ring, the second constellation point on the second ring, and the third constellation point on the third ring are ⁇ /4.
  • the distribution of 32 constellation points can be implemented in the following four ways:
  • the bit corresponding to the first constellation point is 00011.
  • the bits corresponding to the remaining 3 constellation points on the first ring are: 00111 , 01111, 01011.
  • the bit corresponding to the second constellation point is 00000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 00001, 00101, 00100, 00110, 01110, 01100, 01101, 01001, 01000, 01010, 00010.
  • the bit corresponding to the third constellation point is 10011.
  • the bits corresponding to the remaining 15 constellation points on the third ring are: 10000, 10001, 10101, 10100, 10111, 10110, 11110, 11111, 11100, 11101, 11001, 11000, 11011, 11010, 10010.
  • the phases corresponding to 00011, 00000, and 10011 are ⁇ /4, and the phases corresponding to 00001 are ⁇ /12.
  • R1 represents the radius of the first circular ring
  • R2 represents the radius of the second circular ring
  • R3 represents the radius of the third circular ring.
  • the bit corresponding to the first constellation point is 00101.
  • the bits corresponding to the remaining 3 constellation points on the first ring are respectively: 00111 , 01111, 01101.
  • the bit corresponding to the second constellation point is 00000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 00001, 00011, 00010, 00110, 01110, 01010, 01011, 01001, 01000, 01100, 00100.
  • the bit corresponding to the third constellation point is 10101.
  • the bits corresponding to the remaining 15 constellation points on the third ring are: 10000, 10001, 10011, 10010, 10111, 10110, 11110, 11111, 11010, 11011, 11001, 11000, 11101, 11100, 10100.
  • the phases corresponding to 00101, 00000, and 10101 are ⁇ /4, and the phases corresponding to 00001 are ⁇ /12.
  • R1 represents the radius of the first circular ring
  • R2 represents the radius of the second circular ring
  • R3 represents the radius of the third circular ring.
  • the constellation diagram shown in FIG. 40 can be obtained by exchanging the values of bit2 and bit1 in the constellation diagram shown in FIG. 39 .
  • Mode 63 As shown in Figure 41, the bit corresponding to the first constellation point is 10010. Taking the first constellation point as the reference and clockwise, the bits corresponding to the remaining 3 constellation points on the first ring are respectively: 10110 , 11110, 11010.
  • the bit corresponding to the second constellation point is 00000.
  • the bits corresponding to the remaining 11 constellation points on the second ring are: 10000, 10100, 00100, 00110, 01110, 01100, 11100, 11000, 01000, 01010, 00010.
  • the bit corresponding to the third constellation point is 10011. Taking the third constellation point as the reference and clockwise, the bits corresponding to the remaining 15 constellation points on the third ring are: 00001, 10001, 10101, 00101, 10111, 00111, 01111, 11111, 01101, 11101, 11001, 01001, 11011, 01011, 00011.
  • the phases corresponding to 10010, 00000, and 10011 are ⁇ /4, and the phases corresponding to 10000 are ⁇ /12.
  • R1 represents the radius of the first circular ring
  • R2 represents the radius of the second circular ring
  • R3 represents the radius of the third circular ring.
  • the constellation diagram shown in FIG. 41 can be obtained by exchanging the values of bit0 and bit4 in the constellation diagram shown in FIG. 39 .
  • the bit corresponding to the first constellation point is 10100, taking the first constellation point as the reference, and following the clockwise direction, the bits corresponding to the remaining 3 constellation points on the first ring are respectively: 10110 , 11110, 11100.
  • the bit corresponding to the second constellation point is 00000. Based on the second constellation point, in a clockwise direction, the bits corresponding to the remaining 11 constellation points on the second ring are: 10000, 10010, 00010, 00110, 01110, 01010, 11010, 11000, 01000, 01100, 00100.
  • the bit corresponding to the third constellation point is 10101.
  • the bits corresponding to the remaining 15 constellation points on the third ring are: 00001, 10001, 10011, 00011, 10111, 00111, 01111, 11111, 01011, 11011, 11001, 01001, 11101, 01101, 00101.
  • the phases corresponding to 10100, 00000, and 10101 are ⁇ /4, and the phases corresponding to 10000 are ⁇ /12.
  • R1 represents the radius of the first circular ring
  • R2 represents the radius of the second circular ring
  • R3 represents the radius of the third circular ring.
  • the constellation diagram shown in FIG. 42 can be obtained by exchanging the values of bit0 and bit4, and the values of bit2 and bit1 in the constellation diagram shown in FIG. 39 .
  • a new modulation method (or constellation mapping method) is proposed.
  • This modulation method is interleaved with the NR method (that is, write column by column from left to right, and then row by row from left to right)
  • the NR method that is, write column by column from left to right, and then row by row from left to right
  • the second interleaving in step S1401 and step S2901 may include: performing random interleaving or pseudo-random interleaving on the last N-X bits of coded bits.
  • X is greater than or equal to the number of systematic bits, and N is the number of coded bits. That is, in the second interleaving, the first X bits do not participate in the interleaving, and the sequence remains unchanged.
  • X may be equal to N divided by the modulation order M.
  • the device at the sending end performs interleaving on coded bits twice to obtain interleaved bits.
  • the interleaved bits are subsequently modulated.
  • the first interleaving may be the interleaving manner described in step S1401.
  • the modulation method uses the modulation method in DVB-S2.
  • the first interleaving may be the interleaving manner described in step S2901.
  • the modulation method described in step S2903 is used.
  • the sending-end device and the receiving-end device may negotiate or set a pseudo-random interleaving sequence.
  • the pseudo-random interleaving sequence used by the device at the sending end may be as follows, where the numbers are bit indexes and are used to indicate the positions of the bits. For example, 123 represents the 123rd bit among 300 bits, and 99 represents the 99th bit among 300 bits.
  • the second deinterleaving in the above step S1407 and step S2907 may include: performing deinterleaving on the last N-X elements of the first LLR sequence in a preset order.
  • the preset order is the order of pseudo-random interleaving or random interleaving used by the sending end.
  • FIG 45 shows the BLER performance simulation results when the modulation order M is equal to 5
  • the transmitting end performs the second interleaving and the first interleaving on the encoded bits, and 32APSK modulation is used.
  • the simulation conditions are shown in Table 6 below.
  • the SNR of the interleaving method shown in Figure 44 is 0.5 ⁇ 1dB lower than that of the NR interleaving method, that is, the BLER performance when using the interleaving method shown in Figure 44 It can be increased by 0.5 ⁇ 1dB.
  • Table 7 it shows that the systematic bits added with CRC are subjected to LDPC encoding, the second interleaving and the first interleaving, and after scrambling, the constellation map shown in Figure 3 is used to map the modulation symbols, different constellations Mapping probabilities for points.
  • Table 8 it shows the mapping probabilities of different constellation points in the scenario where modulation symbols are obtained by using the constellation map shown in FIG.
  • the number K of systematic bits in Table 7 and Table 8 is equal to 1404 (including 16-bit CRC), and the number N of coded bits is equal to 11940.
  • LDPC encoding adopts BG2 matrix.
  • mapping probability of the 32 constellation points fluctuates in the range of 2.45% to 4.02%, that is, the mapping probability distribution is quite different, and there is a problem of uneven constellation mapping, which leads to the degradation of system decoding performance.
  • the methods and/or steps implemented by the receiver device may also be implemented by components (such as processors, chips, chip systems, circuits, logic modules, or implemented by software); the methods and/or steps implemented by the sending device may also be implemented by components (such as processors, chips, chip systems, circuits, logic modules, or software) that can be used in the sending device.
  • the present application also provides a communication device, which is used to implement the above various methods.
  • the communication device may be the receiving end device in the above method embodiment, or a device including the above receiving end device, or a component that can be used for the receiving end device; or, the communication device may be the sending end device in the above method embodiment , or a device including the above-mentioned sending-end device, or a component that can be used for the sending-end device.
  • the communication device includes hardware structures and/or software modules corresponding to each function.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software in combination with the units and algorithm steps of each example described in the embodiments disclosed herein. Whether a certain function is executed by hardware or computer software drives hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.
  • the embodiments of the present application may divide the communication device into functional modules according to the above method embodiments.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. It should be noted that the division of modules in the embodiment of the present application is schematic, and is only a logical function division, and there may be other division methods in actual implementation.
  • FIG. 48 shows a schematic structural diagram of a sending end device 480 .
  • the sending device 480 includes a processing module 4801 and a transceiver module 4802 .
  • the sending end device 480 may further include a storage module (not shown in FIG. 48 ) for storing program instructions and data.
  • the transceiver module 4802 also referred to as a transceiver unit, is used to implement sending and/or receiving functions.
  • the transceiver module 4802 may be composed of a transceiver circuit, a transceiver, a transceiver or a communication interface.
  • the transceiving module 4802 may include a receiving module and a sending module, which are respectively used to perform the receiving and sending steps performed by the sending device in the above method embodiments, and/or used to support the steps described herein Other processes of the technology; the processing module 4801 can be used to execute the processing steps (such as determination, acquisition, generation, etc.) other processes.
  • the processing module 4801 is configured to obtain the bits to be interleaved; the processing module 4801 is also configured to perform first interleaving on the bits to be interleaved to obtain the interleaved bits, and the first interleaving includes: column-by-column the bits to be interleaved in a first order Write the first matrix, and read it row by row from the first matrix according to the second order; the number of columns of the first matrix is the modulation order M, and M is greater than or equal to 3; the first bit read row by row is the most significant Bit MSB, the Mth bit is the least significant bit LSB; the processing module 4801 is also used to modulate the interleaved bits to obtain modulation symbols; the transceiver module 4802 is used to send modulation symbols.
  • the processing module 4801 is used to obtain the bits to be interleaved; the processing module 4801 is also used to perform first interleaving on the bits to be interleaved to obtain the interleaved bits. Sequentially write the first matrix column by column, and read from the first matrix row by row in the order from left to right; the number of columns of the first matrix is the modulation order M, and M is greater than or equal to 3; One bit is the most significant bit MSB, and the Mth bit is the least significant bit LSB; the processing module 4801 is also used to modulate the interleaved bits to obtain modulation symbols; the constellation diagram used for modulation includes 2M constellation points, 2 M constellation points are distributed on N rings, the constellation points on at least one of the N rings meet the principle of Gray mapping, and N is a positive integer; the transceiver module 4802 is used to send modulation symbols.
  • the sending end device 480 is presented in the form of dividing various functional modules in an integrated manner.
  • Module here may refer to a specific application-specific integrated circuit (ASIC), circuit, processor and memory that execute one or more software or firmware programs, integrated logic circuits, and/or other functions that can provide the above functions device.
  • ASIC application-specific integrated circuit
  • the sender device when the sender device is a terminal device, those skilled in the art can imagine that the sender device 480 may take the form of the terminal device 40 shown in FIG. 13 .
  • the function/implementation process of the processing module 4801 in FIG. 48 can be implemented by the processor 401 in the terminal device 40 shown in FIG. 13 calling the computer-executed instructions stored in the memory 402.
  • the function/implementation process of 4802 may be implemented by the transceiver 403 in the terminal device 40 shown in FIG. 13 .
  • the sender device when the sender device is a network device, those skilled in the art can imagine that the sender device 480 may take the form of the network device 30 shown in FIG. 13 .
  • the function/implementation process of the processing module 4801 in FIG. 48 can be implemented by the processor 301 in the network device 30 shown in FIG. 13 calling the computer-executed instructions stored in the memory 302.
  • the function/implementation process of 4802 may be implemented by the transceiver 303 in the network device 30 shown in FIG. 13 .
  • the function/implementation process of the transceiver module 4802 can be realized through the input and output interface (or communication interface) of the chip or the chip system, and the processing module 4801
  • the function/implementation process of may be realized by a processor (or processing circuit) of a chip or a chip system.
  • the sending end device 480 provided in this embodiment can execute the above method, the technical effect it can obtain can refer to the above method embodiment, which will not be repeated here.
  • FIG. 49 shows a schematic structural diagram of a receiving end device 490 .
  • the receiver device 490 includes a processing module 4901 and a transceiver module 4902 .
  • the receiver device 490 may further include a storage module (not shown in FIG. 49 ) for storing program instructions and data.
  • the transceiver module 4902 also referred to as a transceiver unit, is used to implement sending and/or receiving functions.
  • the transceiver module 4902 may be composed of a transceiver circuit, a transceiver, a transceiver or a communication interface.
  • the transceiving module 4902 may include a receiving module and a sending module, which are respectively used to perform the receiving and sending steps performed by the receiving end device in the above method embodiments, and/or used to support the steps described herein Other processes of the technology; the processing module 4901 can be used to execute the steps of the processing category (such as determining, acquiring, generating, etc.) other processes.
  • the transceiver module 4902 is used to receive modulation symbols; the processing module 4901 is used to demodulate the modulation symbols to obtain the log likelihood ratio LLR sequence to be deinterleaved; the processing module 4901 is also used to process the LLR sequence to be deinterleaved
  • the first deinterleaving is to obtain the first LLR sequence after deinterleaving, the first deinterleaving includes: writing the second matrix row by row according to the second order, and reading column by column from the second matrix according to the first order; the second matrix The number of columns is the modulation order M, and M is greater than or equal to 3; the first bit written row by row is the most significant bit MSB, and the Mth bit is the least significant bit LSB; the processing module 4901 is also used for deinterleaving according to After the first LLR sequence determines the information bits.
  • the transceiver module 4902 is used to receive modulation symbols; the processing module 4901 is used to demodulate the modulation symbols to obtain the log likelihood ratio LLR sequence to be deinterleaved; the processing module 4901 is also used to process the LLR sequence to be deinterleaved
  • the first de-interleaving obtains the first LLR sequence after de-interleaving; the first de-interleaving includes: writing the second matrix row by row in the order from left to right, and writing the second matrix column by column in the order from left to right Read; the number of columns of the second matrix is the modulation order M, and M is greater than or equal to 3; the first bit written row by row is the most significant bit MSB, and the Mth bit is the least significant bit LSB; processing module 4901, It is also used to determine information bits according to the first LLR sequence after deinterleaving; wherein, the constellation diagram used for demodulation includes 2 M constellation points, and the 2 M constellation points are distributed on N rings, and the N rings The constellation
  • the processing module 4901 is configured to determine information bits according to the deinterleaved first LLR sequence, including: the processing module 4901 is configured to decode the deinterleaved first LLR sequence to obtain information bits.
  • the processing module 4901 is configured to determine information bits according to the deinterleaved first LLR sequence, including: the processing module 4901 is configured to perform second deinterleaving on the deinterleaved first LLR sequence to obtain the deinterleaved first LLR sequence the second LLR sequence; the processing module 4901 is also configured to decode the deinterleaved second LLR sequence to obtain information bits.
  • the receiver device 490 is presented in the form of dividing various functional modules in an integrated manner.
  • Module here may refer to a specific application-specific integrated circuit (ASIC), circuit, processor and memory that execute one or more software or firmware programs, integrated logic circuits, and/or other functions that can provide the above functions device.
  • ASIC application-specific integrated circuit
  • the receiving end device when the receiving end device is a network device, those skilled in the art can imagine that the receiving end device 490 may take the form of the network device 30 shown in FIG. 13 .
  • the function/implementation process of the processing module 4901 in FIG. 49 can be implemented by the processor 301 in the network device 30 shown in FIG. 13 calling the computer-executed instructions stored in the memory 302.
  • the function/implementation process of 4902 may be realized by the transceiver 303 in the network device 30 shown in FIG. 13 .
  • the receiving end device when the receiving end device is a terminal device, those skilled in the art can imagine that the receiving end device 490 may take the form of the terminal device 40 shown in FIG. 13 .
  • the function/implementation process of the processing module 4901 in FIG. 49 can be implemented by the processor 401 in the terminal device 40 shown in FIG. 13 calling the computer-executed instructions stored in the memory 402.
  • the function/implementation process of 4902 may be implemented by the transceiver 403 in the terminal device 40 shown in FIG. 13 .
  • the function/implementation process of the transceiver module 4902 can be realized through the input and output interface (or communication interface) of the chip or the chip system, and the processing module 4901
  • the function/implementation process of may be realized by a processor (or processing circuit) of a chip or a chip system.
  • the receiver device 490 provided in this embodiment can execute the above-mentioned method, the technical effect it can obtain can refer to the above-mentioned method embodiment, and details are not repeated here.
  • the embodiments of the present application further provide a communication device, where the communication device includes a processor, configured to implement the method in any one of the foregoing method embodiments.
  • the communication device further includes a memory.
  • the memory is used to store necessary program instructions and data, and the processor can call the program code stored in the memory to instruct the communication device to execute the method in any one of the above method embodiments.
  • the memory may not be in the communication device.
  • the communication device further includes an interface circuit, the interface circuit is a code/data read and write interface circuit, and the interface circuit is used to receive computer-executed instructions (computer-executed instructions are stored in the memory, and may be directly read from memory read, or possibly through other devices) and transferred to the processor.
  • the interface circuit is a code/data read and write interface circuit, and the interface circuit is used to receive computer-executed instructions (computer-executed instructions are stored in the memory, and may be directly read from memory read, or possibly through other devices) and transferred to the processor.
  • the communication device further includes a communication interface, where the communication interface is used to communicate with modules other than the communication device.
  • the communication device may be a chip or a system-on-a-chip.
  • the communication device may consist of a chip, or may include a chip and other discrete devices, which is not specifically limited in this embodiment of the present application.
  • the embodiment of the present application also provides a communication device, the communication device includes an interface circuit and a logic circuit, the interface circuit is used to input and/or output information; the logic circuit is used to perform any of the above
  • the methods in the method embodiments process input information and/or generate output information.
  • the output information is a modulation symbol.
  • the input information is a modulation symbol.
  • Processing the input information includes: demodulating the modulation symbols to obtain a log likelihood ratio LLR sequence to be deinterleaved.
  • the first deinterleaving is performed on the LLR sequence to be deinterleaved to obtain the first LLR sequence after deinterleaving.
  • the information bits are determined according to the deinterleaved first LLR sequence.
  • the sending-end device and the receiving-end device described in the embodiment of the present application can also be realized by using the following: one or more field programmable gate arrays (field programmable gate array, FPGA), Programmable logic device (PLD), controller, state machine, gate logic, discrete hardware components, any other suitable circuit, or any combination of circuits capable of performing the various functions described throughout this application.
  • field programmable gate array field programmable gate array, FPGA
  • PLD Programmable logic device
  • controller state machine
  • gate logic discrete hardware components
  • discrete hardware components any other suitable circuit, or any combination of circuits capable of performing the various functions described throughout this application.
  • the present application also provides a computer-readable storage medium, on which a computer program or instruction is stored, and when the computer program or instruction is executed by a computer, the functions of any one of the above method embodiments are realized.
  • the present application also provides a computer program product, which implements the functions of any one of the above method embodiments when executed by a computer.
  • the systems, devices and methods described in this application can also be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Components shown as units may or may not be physical units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • a software program it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server, or data center Transmission to another website site, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or may be a data storage device including one or more servers, data centers, etc. that can be integrated with the medium.
  • the available medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (solid state disk, SSD)), etc.
  • the computer may include the aforementioned apparatus.

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Abstract

本申请提供交织与调制方法、装置及系统，能够提高传输可靠性。该方法包括：发送端装置获取待交织的比特，对待交织的比特进行第一交织，得到交织后的比特；对交织后的比特进行调制，得到调制符号，并发送该调制符号。接收端装置接收调制符号后，按照与发送端相应的解调方式和解交织方式对调制符号进行解调和解交织，得到LLR，根据该LLR确定信息比特。其中，第一交织包括：将待交织的比特按照第一顺序逐列写入第一矩阵，并按照第二顺序从第一矩阵逐行读出。第一矩阵的列数为调制阶数M，M大于或等于3。逐行读出的第一个比特为MSB，第M个比特为LSB。M等于3时的一种实现中，第一顺序为第三列-第二列-第一列，第二顺序为第一列-第二列-第三列。

Description

交织与调制方法、装置及系统
本申请要求于2021年12月02日提交国家知识产权局、申请号为202111473306.5、申请名称为“交织与调制方法、装置及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信领域，尤其涉及交织与调制方法、装置及系统。
背景技术
未来无线通信网络需要在满足各行各业的业务需求的同时提供更广的业务覆盖。然而，传统的地面移动通信网络的覆盖能力有限，不能满足人们在任意时间、任意地点获取信息的需求。此外，当前基于基站覆盖的模式来提供超广域的覆盖对于偏远地区、沙漠、海洋和空中等场景存在经济性和可行性方面的巨大挑战。
相对于传统的地面移动通信网络，卫星通信具有全球覆盖、远距离传输、组网灵活、部署方便和不受地理位置限制等显著优点，可以作为传统网络的有效补充。
目前，为了将卫星通信技术与地面通信相融合以达到更好的效果，各研究机构和标准组织正在研究将新无线(new radio，NR)协议适配到卫星通信。然而，在将NR的交织方式适配到卫星设备支持的相移键控(phase-shift keying，PSK)或幅度相移键控(amplitude phase shift keying，APSK)调制时，存在传输可靠性较低的问题。
发明内容
本申请提供一种交织与调制方法、装置及系统，能够提高传输可靠性，从而提高接收端的译码性能。
第一方面，提供了交织与调制方法，该方法可以由发送端装置执行，也可以由发送端装置的部件，例如发送端装置的处理器、芯片、或芯片系统等执行，还可以由能实现全部或部分发送端装置功能的逻辑模块或软件实现。该方法包括：获取待交织的比特。对待交织的比特进行第一交织，得到交织后的比特。对交织后的比特进行调制，得到调制符号。发送该调制符号。第一交织包括：将待交织的比特按照第一顺序逐列写入第一矩阵，并按照第二顺序从第一矩阵逐行读出。第一矩阵的列数为调制阶数M，M大于或等于3。逐行读出的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB。
在一种可能的设计中，M等于3时：调制使用的方式为第二代卫星数字视频广播DVB-S28相移键控PSK。
第一顺序为第一矩阵的第三列-第二列-第一列，第二顺序为第一矩阵的第一列-第二列-第三列。
或者，第一顺序为第一矩阵的第二列-第三列-第一列，第二顺序为第一矩阵的第一列-第二列-第三列。
或者，第一顺序为第一矩阵的第一列-第二列-第三列，第二顺序为第一矩阵的第二列-第三列-第一列。
基于该方案，本申请提出新的交织方式，该交织方式在与卫星通信中的调制方式结合使用时，可以将系统比特映射在具有较高可靠性的比特位传输，从而提高传输可靠性和系统的 译码性能。例如，在M等于3时，基于该交织方案，可以将系统比特映射在bit0传输。而在DVB-S2 8PSK调制中，bit0较bit2具有更高的可靠性，从而系统比特在bit0传输时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
在一种可能的设计中，M等于4时，调制使用的方式为DVB-S2 16幅度相移键控APSK。第二顺序为第一矩阵的第一列-第二列-第三列-第四列。
第一顺序为第一矩阵的第四列-第三列-第二列-第一列。
或者，第一顺序为第一矩阵的第四列-第三列-第一列-第二列。
或者，第一顺序为第一矩阵的第三列-第四列-第二列-第一列。
或者，第一顺序为第一矩阵的第三列-第四列-第一列-第二列。
基于该可能的设计，可以将系统比特映射在bit0或bit1传输。由于DVB-S2 16APSK调制中，bit0、bit1较bit3具有更高的可靠性，从而系统比特在bit0或bit1传输时，可以提高系统比特的传输可靠性和译码性能。
在一种可能的设计中，M等于5时，调制使用的方式为DVB-S2 32APSK。第二顺序为第一矩阵的第一列-第二列-第三列-第四列-第五列。
第一顺序为第一矩阵的第四列-第三列-第二列-第一列-第五列。
或者，第一顺序为第一矩阵的第四列-第二列-第三列-第一列-第五列。
或者，第一顺序为第一矩阵的第四列-第三列-第二列-第五列-第一列。
或者，第一顺序为第一矩阵的第四列-第二列-第三列-第五列-第一列。
基于该可能的设计，可以将系统比特映射在bit1传输。由于DVB-S2 32APSK调制中，bit1较bit4具有更高的可靠性，从而系统比特在bit1传输时，可以提高系统比特的传输可靠性和译码性能。
第二方面，提供了交织与调制方法，该方法可以由发送端装置执行，也可以由发送端装置的部件，例如发送端装置的处理器、芯片、或芯片系统等执行，还可以由能实现全部或部分发送端装置功能的逻辑模块或软件实现。该方法包括：获取待交织的比特。对待交织的比特进行第一交织，得到交织后的比特。对交织后的比特进行调制，得到调制符号。发送该调制符号。第一交织包括：将待交织的比特按照从左到右的顺序逐列写入第一矩阵，并按照从左到右的顺序从第一矩阵逐行读出。第一矩阵的列数为调制阶数M，M大于或等于3。逐行读出的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB。调制使用的星座图包括2 M个星座点，2 M个星座点分布在N个圆环上，N个圆环中的至少一个圆环上的星座点满足格雷映射的原则，N为正整数。
基于该方案，本申请提出新的星座图，该星座图在与NR中的交织方式结合使用时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
在一种可能的设计中，M等于3时，8个星座点均匀分布在一个圆环上。第一星座点对应的相位为π/4或π/8，第一星座点对应的比特为000；以第一星座点为基准，按照顺时针方向，剩余7个星座点对应的比特分别为：010、011、111、110、100、101、001，或者，分别为：100、101、111、110、010、011、001。
基于该可能的设计，在调制阶数M等于3时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
在一种可能的设计中，M等于4时，16个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分布在第二圆环上，第一圆环和第二圆环为同心环；第一圆环上的第一星座点和第二圆环上的第二星座点对应的相位为π/4。其中：
第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0001、0101、0100、0110、1110、1100、1101、1001、1000、1010、0010。
或者，
第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0010、0110、0100、0101、1101、1100、1110、1010、1000、1001、0001。
或者，
第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0001、1001、1000、1010、1110、1100、1101、0101、0100、0110、0010。
或者，
第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0010、1010、1000、1001、1101、1100、1110、0110、0100、0101、0001。
基于该可能的设计，在调制阶数M等于4时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
在一种可能的设计中，M等于5时，32个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分布在第二圆环上，剩余16个星座点均匀分布在第三圆环上，第一圆环、第二圆环、和第三圆环为同心环；第一圆环上的第一星座点、第二圆环上的第二星座点、和第三圆环上的第三星座点对应的相位为π/4。其中：
第一星座点对应的比特为00011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01011。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：00001、00101、00100、00110、01110、01100、01101、01001、01000、01010、00010。
第三星座点对应的比特为10011，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10101、10100、10111、10110、11110、11111、11100、11101、11001、11000、11011、11010、10010。
或者，
第一星座点对应的比特为00101，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01101。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上 的剩余11个星座点对应的比特分别为：00001、00011、00010、00110、01110、01010、01011、01001、01000、01100、00100。
第三星座点对应的比特为10101，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10011、10010、10111、10110、11110、11111、11010、11011、11001、11000、11101、11100、10100。
或者，
第一星座点对应的比特为10010，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11010。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：10000、10100、00100、00110、01110、01100、11100、11000、01000、01010、00010。
第三星座点对应的比特为10011，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10101、00101、10111、00111、01111、11111、01101、11101、11001、01001、11011、01011、00011。
或者，
第一星座点对应的比特为10100，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11100。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：10000、10010、00010、00110、01110、01010、11010、11000、01000、01100、00100。
第三星座点对应的比特为10101，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10011、00011、10111、00111、01111、11111、01011、11011、11001、01001、11101、01101、00101。
基于该可能的设计，在调制阶数M等于5时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
结合第一方面或第二方面，在一种可能的设计中，待交织的比特为编码比特；或者，待交织的比特为对编码比特进行第二交织后的比特。
结合第一方面或第二方面，在一种可能的设计中，第二交织包括：对编码比特的后N-X个比特进行随机或伪随机交织；X大于或等于系统比特的个数，N为编码比特的个数。
基于该可能的设计，在待交织的比特为对编码比特进行第二交织后的比特时，相当于发送端装置进行了两次交织，可以降低星座点的映射概率的波动范围，提高译码性能。
第三方面，提供了解交织与解调方法，该方法可以由接收端装置执行，也可以由接收端装置的部件，例如接收端装置的处理器、芯片、或芯片系统等执行，还可以由能实现全部或部分接收端装置功能的逻辑模块或软件实现。该方法包括：接收调制符号。对调制符号进行解调，得到待解交织的对数似然比LLR序列。对待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列。根据解交织后的第一LLR序列确定信息比特。第一解交织包括：将待解交织的LLR序列按照第二顺序逐行写入第二矩阵，并按照第一顺序从第二矩阵逐列读出。第二矩阵的列数为调制阶数M，M大于或等于3。逐行写入的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB。
在一种可能的设计中，M等于3时：解调对应的调制方式为第二代卫星数字视频广播DVB-S2 8相移键控PSK；
第一顺序为第二矩阵的第三列-第二列-第一列，第二顺序为第二矩阵的第一列-第二列-第三列。
或者，第一顺序为第二矩阵的第二列-第三列-第一列，第二顺序为第二矩阵的第一列-第二列-第三列。
或者，第一顺序为第二矩阵的第一列-第二列-第三列，第二顺序为第二矩阵的第二列-第三列-第一列。
在一种可能的设计中，M等于4时，解调对应的调制方式为DVB-S2 16幅度相移键控APSK；第二顺序为第二矩阵的第一列-第二列-第三列-第四列。
第一顺序为第二矩阵的第四列-第三列-第二列-第一列。
或者，第一顺序为第二矩阵的第四列-第三列-第一列-第二列。
或者，第一顺序为第二矩阵的第三列-第四列-第二列-第一列。
或者，第一顺序为第二矩阵的第三列-第四列-第一列-第二列。
在一种可能的设计中，M等于5时，解调对应的调制方式为DVB-S2 32APSK；第二顺序为第二矩阵的第一列-第二列-第三列-第四列-第五列。
第一顺序为第二矩阵的第四列-第三列-第二列-第一列-第五列。
或者，第一顺序为第二矩阵的第四列-第二列-第三列-第一列-第五列。
或者，第一顺序为第二矩阵的第四列-第三列-第二列-第五列-第一列。
或者，第一顺序为第二矩阵的第四列-第二列-第三列-第五列-第一列。
其中，第三方面或第三方面的任一可能的设计所带来的技术效果可参考第一方面或第一方面相应的设计所带来的技术效果，在此不再赘述。
第四方面，提供了解交织与解调方法，该方法可以由接收端装置执行，也可以由接收端装置的部件，例如接收端装置的处理器、芯片、或芯片系统等执行，还可以由能实现全部或部分接收端装置功能的逻辑模块或软件实现。该方法包括：接收调制符号。对调制符号进行解调，得到待解交织的对数似然比LLR序列。对待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列。根据解交织后的第一LLR序列确定信息比特。第一解交织包括：按照从左到右的顺序逐行写入第二矩阵，并按照从左到右的顺序从第二矩阵逐列读出。第二矩阵的列数为调制阶数M，M大于或等于3。逐行写入的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB。其中，解调使用的星座图包括2 M个星座点，2 M个星座点分布在N个圆环上，N个圆环中的至少一个圆环上的星座点满足格雷映射的原则，N为正整数。
在一种可能的设计中，M等于3时，8个星座点均匀分布在一个圆环上。第一星座点对应的相位为π/4或π/8，第一星座点对应的比特为000；以第一星座点为基准，按照顺时针方向，剩余7个星座点对应的比特分别为：010、011、111、110、100、101、001，或者，分别为：100、101、111、110、010、011、001。
在一种可能的设计中，M等于4时，16个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分布在第二圆环上，第一圆环和第二圆环为同心环；第一圆环上的第一星座点和第二圆环上的第二星座点对应的相位为π/4。其中：
第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0001、0101、0100、0110、1110、1100、1101、1001、 1000、1010、0010。
或者，
第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0010、0110、0100、0101、1101、1100、1110、1010、1000、1001、0001。
或者，
第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0001、1001、1000、1010、1110、1100、1101、0101、0100、0110、0010。
或者，
第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0010、1010、1000、1001、1101、1100、1110、0110、0100、0101、0001。
在一种可能的设计中，M等于5时，32个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分布在第二圆环上，剩余16个星座点均匀分布在第三圆环上，第一圆环、第二圆环、和第三圆环为同心环；第一圆环上的第一星座点、第二圆环上的第二星座点、和第三圆环上的第三星座点对应的相位为π/4。其中：
第一星座点对应的比特为00011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01011。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：00001、00101、00100、00110、01110、01100、01101、01001、01000、01010、00010。
第三星座点对应的比特为10011，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10101、10100、10111、10110、11110、11111、11100、11101、11001、11000、11011、11010、10010。
或者，
第一星座点对应的比特为00101，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01101。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：00001、00011、00010、00110、01110、01010、01011、01001、01000、01100、00100。
第三星座点对应的比特为10101，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10011、10010、10111、10110、11110、11111、11010、11011、11001、11000、11101、11100、10100。
或者，
第一星座点对应的比特为10010，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11010。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：10000、10100、00100、00110、01110、01100、11100、11000、01000、01010、00010。
第三星座点对应的比特为10011，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10101、00101、10111、00111、01111、11111、01101、11101、11001、01001、11011、01011、00011。
或者，
第一星座点对应的比特为10100，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11100。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：10000、10010、00010、00110、01110、01010、11010、11000、01000、01100、00100。
第三星座点对应的比特为10101，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10011、00011、10111、00111、01111、11111、01011、11011、11001、01001、11101、01101、00101。
结合第三方面或第四方面，在一种可能的设计中，根据解交织后的第一LLR序列确定信息比特，包括：对解交织后的第一LLR序列进行译码，得到信息比特。
结合第三方面或第四方面，在一种可能的设计中，根据解交织后的第一LLR序列确定信息比特，包括：对解交织后的第一LLR序列进行第二解交织，得到解交织后的第二LLR序列；对解交织后的第二LLR序列进行译码，得到信息比特。
结合第三方面或第四方面，在一种可能的设计中，第二解交织包括：对第一LLR序列的后N-X个元素按照预设顺序进行解交织，N为信息比特的个数，X大于或等于系统比特的个数。
其中，第四方面或第四方面的任一可能的设计所带来的技术效果可参考第二方面或第二方面相应的设计所带来的技术效果，在此不再赘述。
第五方面，提供了一种通信装置用于实现上述各种方法。该通信装置可以为上述第一方面或第二方面中的发送端装置，或者包含上述发送端装置的设备，或者上述发送端装置中包含的装置，比如芯片；或者，该通信装置可以为上述第三方面或第四方面中的接收端装置，或者包含上述接收端装置的设备，或者上述接收端装置中包含的装置，比如芯片。所述通信装置包括实现上述方法相应的模块、单元、或手段(means)，该模块、单元、或means可以通过硬件实现，软件实现，或者通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块或单元。
在一种可能的设计中，该通信装置可以包括收发模块和处理模块。该收发模块，也可以称为收发单元，用以实现上述任一方面及其任意可能的实现方式中的发送和/或接收功能。该收发模块可以由收发电路，收发机，收发器或者通信接口构成。该处理模块，可以用于实现上述任一方面及其任意可能的实现方式中的处理功能。
在一些可能的设计中，收发模块包括发送模块和接收模块，分别用于实现上述任一方面及其任意可能的实现方式中的发送和接收功能。
第六方面，提供了一种通信装置，包括：处理器和存储器；该存储器用于存储计算机指 令，当该处理器执行该指令时，以使该通信装置执行上述任一方面所述的方法。该通信装置可以为上述第一方面或第二方面中的发送端装置，或者包含上述发送端装置的设备，或者上述发送端装置中包含的装置，比如芯片；或者，该通信装置可以为上述第三方面或第四方面中的接收端装置，或者包含上述接收端装置的设备，或者上述接收端装置中包含的装置，比如芯片。
第七方面，提供一种通信装置，包括：处理器和通信接口；该通信接口，用于与该通信装置之外的模块通信；所述处理器用于执行计算机程序或指令，以使该通信装置执行上述任一方面所述的方法。该通信装置可以为上述第一方面或第二方面中的发送端装置，或者包含上述发送端装置的设备，或者上述发送端装置中包含的装置，比如芯片；或者，该通信装置可以为上述第三方面或第四方面中的接收端装置，或者包含上述接收端装置的设备，或者上述接收端装置中包含的装置，比如芯片。
第八方面，提供一种通信装置，包括：逻辑电路和接口电路；该接口电路，用于输入和/或输出信息；该逻辑电路用于执行上述任一方面所述的方法，生成所述接口电路输出的信息，和/或，对所述接口电路输入的信息进行处理。该通信装置可以为上述第一方面或第二方面中的发送端装置，或者包含上述发送端装置的设备，或者上述发送端装置中包含的装置，比如芯片；或者，该通信装置可以为上述第三方面或第四方面中的接收端装置，或者包含上述接收端装置的设备，或者上述接收端装置中包含的装置，比如芯片。
结合第八方面，在一种可能的设计中，该通信装置用于实现上述发送端装置的功能时：输出的信息为调制符号。
结合第八方面，在一种可能的设计中，该通信装置用于实现上述接收端装置的功能时：输入的信息为调制符号。对输入的信息进行处理，包括：对调制符号进行解调，得到待解交织的对数似然比(LLR)序列。对待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列。根据解交织后的第一LLR序列确定信息比特。
第九方面，提供了一种通信装置，包括：接口电路和处理器，该接口电路为代码/数据读写接口电路，该接口电路用于接收计算机执行指令(计算机执行指令存储在存储器中，可能直接从存储器读取，或可能经过其他器件)并传输至该处理器；处理器用于执行计算机执行指令以使该通信装置执行上述任一方面所述的方法。该通信装置可以为上述第一方面或第二方面中的发送端装置，或者包含上述发送端装置的设备，或者上述发送端装置中包含的装置，比如芯片；或者，该通信装置可以为上述第三方面或第四方面中的接收端装置，或者包含上述接收端装置的设备，或者上述接收端装置中包含的装置，比如芯片。
第十方面，提供了一种通信装置，包括：至少一个处理器；所述处理器用于执行计算机程序或指令，以使该通信装置执行上述任一方面所述的方法。该通信装置可以为上述第一方面或第二方面中的发送端装置，或者包含上述发送端装置的设备，或者上述发送端装置中包含的装置，比如芯片；或者，该通信装置可以为上述第三方面或第四方面中的接收端装置，或者包含上述接收端装置的设备，或者上述接收端装置中包含的装置，比如芯片。
在一种可能的设计中，该通信装置包括存储器，该存储器，用于保存必要的程序指令和数据。该存储器可以与处理器耦合，或者，也可以独立于该处理器。
在一种可能的设计中，该通信装置可以是芯片或芯片系统。该装置是芯片系统时，可以由芯片构成，也可以包含芯片和其他分立器件。
第十一方面，提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在通信装置上运行时，使得通信装置可以执行上述任一方面所述的方法。
第十二方面，提供了一种包含指令的计算机程序产品，当其在通信装置上运行时，使得该通信装置可以执行上述任一方面所述的方法。
可以理解的是，第五方面至第十二方面中任一方面提供的通信装置是芯片时，上述的发送动作/功能可以理解为输出，上述的接收动作/功能可以理解为输入。
其中，第五方面至第十二方面中任一种设计方式所带来的技术效果可参见上述第一方面或第二方面或第三方面或第四方面中不同设计方式所带来的技术效果，在此不再赘述。
第十三方面，提供一种通信系统，该通信系统包括上述方面所述的发送端装置和接收端装置。
附图说明
图1为本申请提供的一种DVB-S2 8PSK的星座图；
图2为本申请提供的一种DVB-S2 16APSK的星座图；
图3为本申请提供的一种DVB-S2 32APSK的星座图；
图4为本申请提供的一种DVB-S2 8PSK的比特可靠性仿真图；
图5为本申请提供的一种DVB-S2 16APSK的比特可靠性仿真图；
图6为本申请提供的一种DVB-S2 32APSK的比特可靠性仿真图；
图7为本申请提供的一种NR发送端的数据处理示意图；
图8为本申请提供的一种NR发送端的交织方式示意图；
图9为本申请提供的一种NR接收端的解交织方式示意图；
图10为本申请提供的一种LDPC编码比特的交织示意图；
图11为本申请提供的一种通信系统的结构示意图；
图12为本申请提供的另一种通信系统的结构示意图；
图13为本申请提供的一种终端设备和网络设备的结构示意图；
图14为本申请提供的一种交织与调制方法的流程示意图；
图15为本申请提供的一种调制阶数等于3时的交织方式示意图；
图16a为本申请提供的一种调制阶数等于3时不同交织方式的BLER性能仿真图；
图16b为本申请提供的另一种调制阶数等于3时交织方式示意图；
图17为本申请提供的又一种调制阶数等于3时的交织方式示意图；
图18为本申请提供的再一种调制阶数等于3时的交织方式示意图；
图19为本申请提供的一种调制阶数等于4时的交织方式示意图；
图20为本申请提供的一种调制阶数等于4时不同交织方式的BLER性能仿真图；
图21为本申请提供的另一种调制阶数等于4时的交织方式示意图；
图22为本申请提供的又一种调制阶数等于4时的交织方式示意图；
图23为本申请提供的再一种调制阶数等于4时的交织方式示意图；
图24为本申请提供的一种调制阶数等于5时的交织方式示意图；
图25为本申请提供的一种调制阶数等于5时不同交织方式的BLER性能仿真图；
图26为本申请提供的另一种调制阶数等于5时的交织方式示意图；
图27为本申请提供的又一种调制阶数等于5时的交织方式示意图；
图28为本申请提供的再一种调制阶数等于5时的交织方式示意图；
图29为本申请提供的另一种交织与调制方法的流程示意图；
图30为本申请提供的一种调制阶数等于3时的星座图；
图31为本申请提供的一种调制阶数等于3时不同星座图的BLER性能仿真图；
图32为本申请提供的另一种调制阶数等于3时的星座图；
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图34为本申请提供的再一种调制阶数等于3时的星座图
图35为本申请提供的一种调制阶数等于4时的星座图；
图36为本申请提供的另一种调制阶数等于4时的星座图；
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图38为本申请提供的再一种调制阶数等于4时的星座图；
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图40为本申请提供的另一种调制阶数等于5时的星座图；
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图42为本申请提供的再一种调制阶数等于5时的星座图；
图43为本申请提供的一种两级交织的交织方式示意图；
图44为本申请提供的另一种两级交织的交织方式示意图；
图45为本申请提供的一种调制阶数等于5时两级交织方式的BLER性能仿真图；
图46为本申请提供的另一种调制阶数等于5时两级交织方式的BLER性能仿真图；
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图48为本申请提供的一种发送端装置的结构示意图；
图49为本申请提供的一种接收端装置的结构示意图。
具体实施方式
在本申请的描述中，除非另有说明，“/”表示前后关联的对象是一种“或”的关系，例如，A/B可以表示A或B；本申请中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A，B可以是单数或者复数。
在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，便于理解。
可以理解，说明书通篇中提到的“实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各个实施例未必指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。可以理解，在本申请的各种实施例中，各过程的序号的大小并不意味着执行顺序的先后，各过程 的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
可以理解，在本申请中，“…时”以及“若”均指在某种客观情况下会做出相应的处理，并非是限定时间，且也不要求实现时要有判断的动作，也不意味着存在其它限定。
可以理解，本申请实施例中的一些可选的特征，在某些场景下，可以不依赖于其他特征，比如其当前所基于的方案，而独立实施，解决相应的技术问题，达到相应的效果，也可以在某些场景下，依据需求与其他特征进行结合。相应的，本申请实施例中给出的装置也可以相应的实现这些特征或功能，在此不予赘述。
本申请中，除特殊说明外，各个实施例之间相同或相似的部分可以互相参考。在本申请中各个实施例、以及各实施例中的各个实施方式/实施方法/实现方法中，如果没有特殊说明以及逻辑冲突，不同的实施例之间、以及各实施例中的各个实施方式/实施方法/实现方法之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例、以及各实施例中的各个实施方式/实施方法/实现方法中的技术特征根据其内在的逻辑关系可以组合形成新的实施例、实施方式、实施方法、或实现方法。以下所述的本申请实施方式并不构成对本申请保护范围的限定。
为了方便理解本申请实施例的技术方案，首先给出本申请相关技术的简要介绍如下。
1、非地面网络(non-terrestrial network，NTN)通信：
NTN通信包括卫星通信、空对地(air to ground，ATG)通信等。按照承载基站或基站功能的平台距离地面的高度，NTN可以分为低空平台(low altitude platform，LAP)子网(LAP subnetwork)、高空平台(high altitude platform，HAP)子网(HAP subnetwork)、以及卫星通信子网(SATCOM subnetwork)。
LAP subnetwork中，基站或基站功能部署于距离地面0.1km至1km的低空飞行平台上为终端设备提供覆盖，例如无人机；HAP subnetwork中，基站或基站功能部署于距离地面1km至50km的高空飞行平台上为终端设备提供覆盖，例如飞机；SATCOM subnetwork中，基站或基站功能部署于距离地面50km以上的卫星上为终端设备提供覆盖。
进一步的，根据轨道高度的不同可以将卫星通信系统区分为如下三种：高轨(geostationary earth orbit，GEO)卫星通信系统，也称同步轨道卫星系统；中轨(medium earth orbit，MEO)卫星通信系统和低轨(low earth orbit,LEO)卫星通信系统。
GEO卫星一般又称为静止轨道卫星，轨道高度为35786千米(km)。GEO卫星通信的主要优点是相对地面静止并且提供很大的覆盖面积。然而其缺点也相对突出，如：1)与地球之间的距离过大，需要较大口径的天线；2)传输时延较大，约0.5秒左右，无法满足实时业务的需求；3)轨道资源相对紧张，发射成本高并且无法为两极地区提供覆盖。
MEO卫星的轨道高度为2000～35786km。在MEO卫星通信中，使用相对较少的卫星数目即可以实现全球覆盖，但是其传输时延相比LEO卫星通信较高。MEO卫星通信主要用于定位导航。
LEO卫星的轨道高度在300～2000km，LEO卫星的轨道高度低于MEO卫星和GEO卫星的轨道高度，数据传播时延小，功率损耗更小，发射成本相对更低。因此LEO卫星通信在近年来取得了长足进展，备受关注。
传统卫星通信标准通常采用单载波加相移键控(phase-shift keying，PSK)或幅度相移键控(amplitude phase shift keying，APSK)调制的通信体制，利用单载波和PSK/APSK组合的低峰均功率比(peak to average power ratio，PAPR)特性，提高功放效率与发射功率。例如，在第二代卫星数字视频广播(digital video broadcasting-satellite second generation，DVB-S2)标准中采用单载波加8PSK或16APSK或32APSK调制组合的通信体制。
示例性的，图1示出了目前DVB-S2标准中8PSK的星座图。其中，黑色点为星座点(或者也可以描述为一个符号)，对应3个比特(bit)，按照比特位从高到低可以表示为bit2、bit1、bit0。星座点在横轴上的投影表示同相成分的峰值振幅，在纵轴的投影表示正交成分的峰值振幅。星座点到圆点的连线(或称为向量)的长度表示信号的峰值振幅，该连线和水平轴之间的角度表示相位。
本申请中，星座图也可以称为星座映射图，二者可以相互替换，本申请对此不作具体限定。
图2示出了DVB-S2标准中16APSK的星座图，其中每个星座点对应4个比特，按照比特位从高到低可以表示为bit3、bit2、bit1、bit0。图3示出了DVB-S2标准中32APSK的星座图，其中每个星座点对应5个比特，按照比特位从高到低可以表示为bit4、bit3、bit2、bit1、bit0。其他可参考图1对应的相关描述，在此不再赘述。
参见图4，示出了对图1所示的星座图的比特可靠性的仿真结果。其中，AWGN指加性高斯白噪声(additive white gaussian noise，AWGN)，即在AWGN信道中进行仿真；BER指误比特率(bit error ratio，BER)；SNR指信噪比(signal-to-noise ratio，SNR)。从该仿真结果可以看出，8PSK的低位比特(bit1，bit0)较高位比特(bit2)具有更高的可靠性，即在同样的SNR下，低位比特的BER低于高位比特的BER。
参见图5，示出了对图2所示的星座图的比特可靠性的仿真结果。从该仿真结果可以看出，在16APSK的工作信噪比(signal-to-noise ratio，SNR)区间，当SNR≤16dB时，16APSK的低位比特(bit1，bit0)较高位比特(bit3，bit2)具有更高的可靠性。
参见图6，示出了对图3所示的星座图的比特可靠性的仿真结果。从该仿真结果可以看出，在32APSK的工作信噪比区间，当10.8dB<SNR≤20.5dB时，32APSK的bit3的可靠性最高，bit2、bit1次之，bit4、bit0的可靠性较差。
结合图4、图5、图6，8PSK、16APSK、32APSK下，比特的可靠性排序可以如下表1所示。即8PSK、16APSK、32APSK的中低位比特的可靠性较高，高位比特的可靠性较低。
表1
Figure PCTCN2022130890-appb-000001
2、新无线(new radio，NR)交织与映射：
如图7所示，为NR发端的数据处理示意图。其中，源比特(bit source)添加循环冗余校验(cyclical redundancy check，CRC)信息后，经过低密度奇偶校验码(low density parity check code，LDPC)编码，得到LDPC编码比特。
之后对LDPC编码比特进行比特交织(bit interleaver)和加扰(scrambler)后，进行星座映射(constellation mapping)。
星座映射后进行逆离散傅里叶变换(inverse discrete fourier transform，IDFT)得到基带正交频分复用(orthogonal frequency division multiplexing，OFDM)信号，并对基带ODFM信号添加循环前缀(cyclic prefix，CP)后发射。
其中，为了对抗突发干扰，NR协议使用行列交织，利用行列交织将局部突发差错离散成随机差错，从而提高译码性能。
本申请中，系统比特指输入编码器的比特，例如，在LDPC编码中，系统比特即为输入LDPC编码器的比特。基于图7所示的示例，系统比特可以为源比特添加CRC后的比特。
在星座映射时，NR使用正交振幅调制(quadrature amplitude modulation，QAM)，例如16QAM、64QAM。在该调制方式下，高位比特较低位比特具体更高的可靠性。
示例性的，以调制方式为16QAM为例，如图8所示，在行列交织中，首先将LDPC编码比特逐列写入比特矩阵，比特矩阵的列数为调制阶数(16QAM对应调制阶数4)，写入顺序为从最左侧列到最右侧列，可以表示为[W-1 2 3 4]。之后，对比特矩阵做逐行读出，从左向右读出每一行组成比特流，可以表示为[R-1 2 3 4]。其中，每行比特的最左侧比特是最高有效比特(most significant bit，MSB)，最右侧比特是最低有效比特(least significant bit，LSB)。
以LDPC编码比特表示为a 0a 1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11为例，根据图8所示的交织方式，第一列写入a 0a 1a 2，第二列写入a 3a 4a 5，第三列写入a 6a 7a 8，第四列写入a 9a 10a 11。随后，第一行读出a 0a 3a 6a 9，第二行读出a 1a 4a 7a 10，第三行读出a 2a 5a 8a 11。由于最左侧比特是MSB，最右侧比特是LSB，从而行列交织后，a 0、a 1、a 2能够在高位传输。
相应的，如图9所示为接收端解交织的示意图。解交织和交织的顺序相反，首先按照由左向右的顺序逐行写入矩阵，然后按照从左向右的顺序逐列读出。
如图10所示，LDPC编码比特的构成示意图，即LDPC编码后，系统比特在前，非系统比特在后。该场景下，基于NR的交织方式可以将LDPC编码比特的系统比特映射到高位比特。此外，又由于QAM调制方式中，高位比特较低位比特具体更高的可靠性，因此在NR中，能够将系统比特映射至高位比特以获得更好的译码性能。
然而，通过上述表1可知，8PSK、16APSK、32APSK的中低位比特的可靠性较高，高位比特的可靠性较低，其与NR交织结合使用时，系统比特在可靠性较低的高位比特中传输，导致系统比特不能得到很好的保护，降低系统译码性能，传输可靠性较低。
基于此，本申请提供一种数据处理方法，该数据处理方法可以包括应用于发送端装置的交织与调制方法，以及应用于接收端装置的解交织与解调方法。该方法在NR协议与卫星通信适配时，能够提高系统的译码性能，从而提高传输可靠性。
本申请实施例的技术方案可用于各种通信系统，例如：正交频分多址(orthogonal frequency-division multiple access，OFDMA)、单载波频分多址(single carrier FDMA，SC-FDMA)、卫星通信系统、NTN系统、物联网(internet of things，IoT)系统、或未来演进的通信系统等。术语“系统”可以和“网络”相互替换。
本申请实施例的技术方案可以应用于各种通信场景，例如可以应用于以下通信场景中的一种或多种：增强移动宽带(enhanced mobile broadband，eMBB)、超可靠低时延通信(ultra reliable low latency communication，URLLC)、机器类型通信(machine type communication，MTC)、大规模机器类型通信(massive machine type communications，mMTC)、设备到设备(device-to-device，D2D)、车联网(vehicle to everything，V2X)、或IoT等通信场景。
本申请实施例的技术方案还可以应用于远距离通信场景中，如应用于终端设备与网络设备之间的距离不断发生变化的卫星通信场景，或其他远距离通信场景等，不予限制。
上述适用本申请的通信系统仅是举例说明，适用本申请的通信系统不限于此，在此统一说明，以下不再赘述。
参见图11，为本申请提供的一种通信系统的结构示意图。该通信系统包括发送端装置和 接收端装置。
可选的，发送端装置可以为终端设备，相应的，接收端装置为网络设备；或者，发送端装置可以为网络设备，相应的，接收端装置为终端设备；或者，发送端装置和接收端装置均为终端设备；或者，发送端装置和接收端装置均为网络设备。
示例性的，如图12所示，示出了本申请提供的通信系统的一种可能的结构图。图12中以该通信系统包括至少一个网络设备30，以及与该网络设备30连接的一个或多个终端设备40为例进行说明。应理解，图12中的终端设备和网络设备的数量仅是举例，还可以更多或者更少。
示例性的，在图12所示的通信系统中，终端设备40可以作为发送端装置，相应的，网络设备30作为接收端装置；或者，终端设备40可以作为接收端装置，相应的，网络设备30作为发送端装置。
可选的，本申请实施例中的网络设备30可以部署于高空平台或者卫星。该网络设备30，是一种将终端设备40接入到无线网络的设备，所述网络设备30可以为无线接入网中的节点，又可以称为基站，还可以称为无线接入网(radio access network，RAN)节点(或设备)。
例如，网络设备可以包括长期演进(long term evolution，LTE)系统或演进的LTE系统(LTE-Advanced，LTE-A)中的演进型基站(NodeB或eNB或e-NodeB，evolutional Node B)，如传统的宏基站eNB和异构网络场景下的微基站eNB。或者，可以包括NR系统中的下一代节点B(next generation node B，gNB)。或者，可以包括传输接收点(transmission reception point，TRP)、家庭基站(例如，home evolved NodeB，或home Node B，HNB)、基带单元(base band unit，BBU)、基带池BBU pool，或WiFi接入点(access point，AP)等。或者，可以包括云接入网(cloud radio access network，CloudRAN)系统中的集中式单元(centralized unit，CU)和/或分布式单元(distributed unit，DU)。或者，可以包括NTN中的基站，即可以部署于高空平台或者卫星，在NTN中，网络设备可以作为层1(L1)中继(relay)，或者可以作为基站，或者可以作为DU，或者可以作为接入回传一体化(integrated access and backhual，IAB)节点。或者，网络设备可以是IoT中实现基站功能的设备，例如V2X、D2D、或者机器到机器(machine to machine，M2M)中实现基站功能的设备，本申请实施例并不限定。
可选的，本申请实施例中的基站可以包括各种形式的基站，例如：宏基站、微基站(也称为小站)、中继站、接入点、家庭基站、TRP、发射点(transmitting point，TP)、移动交换中心等，本申请实施例对此不作具体限定。
可选的，本申请实施例中的终端设备40，可以是用于实现无线通信功能的设备，例如终端或者可用于终端中的芯片等。其中，终端可以是5G网络或者未来演进的公共陆地移动网络(public land mobile network，PLMN)中的用户设备(user equipment，UE)、接入终端、终端单元、终端站、移动站、移动台、远方站、远程终端、移动设备、无线通信设备、终端代理或终端装置等。接入终端可以是蜂窝电话、无绳电话、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字处理(personal digital assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备或可穿戴设备，虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等。或者，终端可以是IoT中具有通信 功能的终端，例如V2X中的终端(例如车联网设备)、D2D通信中的终端、或者M2M通信中的终端等。终端可以是移动的，也可以是固定的。
可选的，本申请实施例中的网络设备30与终端设备40也可以称之为通信装置，其可以是一个通用设备或者是一个专用设备，本申请实施例对此不作具体限定。
可选的，如图13所示，为本申请实施例提供的网络设备30和终端设备40的结构示意图。
其中，终端设备40包括至少一个处理器(图13中示例性的以包括一个处理器401为例进行说明)和至少一个收发器(图13中示例性的以包括一个收发器403为例进行说明)。可选的，终端设备40还可以包括至少一个存储器(图13中示例性的以包括一个存储器402为例进行说明)、至少一个输出设备(图13中示例性的以包括一个输出设备404为例进行说明)和至少一个输入设备(图13中示例性的以包括一个输入设备405为例进行说明)。
处理器401、存储器402和收发器403通过通信线路相连接。通信线路可包括一通路，用于在上述组件之间传送信息。
处理器401可以是通用中央处理器(central processing unit，CPU)、微处理器、特定应用集成电路(application-specific integrated circuit，ASIC)，或者一个或多个用于控制本申请方案程序执行的集成电路。在具体实现中，作为一种实施例，处理器401也可以包括多个CPU，并且处理器401可以是单核(single-CPU)处理器或多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路或用于处理数据(例如计算机程序指令)的处理核。
存储器402可以是具有存储功能的装置。例如可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备、随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器402可以是独立存在，通过通信线路与处理器401相连接。存储器402也可以和处理器401集成在一起。
其中，存储器402用于存储执行本申请方案的计算机执行指令，并由处理器401来控制执行。具体的，处理器401用于执行存储器402中存储的计算机执行指令，从而实现本申请实施例中所述的方法。
可选的，本申请实施例中的计算机执行指令也可以称之为应用程序代码或者计算机程序代码，本申请实施例对此不作具体限定。
收发器403可以使用任何收发器一类的装置，用于与其他设备或通信网络通信。收发器403可以包括发射机(transmitter，Tx)和接收机(receiver，Rx)。
输出设备404和处理器401通信，可以以多种方式来显示信息。例如，输出设备404可以是液晶显示器(liquid crystal display，LCD)，发光二极管(light emitting diode，LED)显示设备，阴极射线管(cathode ray tube，CRT)显示设备，或投影仪(projector)等。
输入设备405和处理器401通信，可以以多种方式接收用户的输入。例如，输入设备405可以是鼠标、键盘、触摸屏设备或传感设备等。
网络设备30包括至少一个处理器(图13中示例性的以包括一个处理器301为例进行说明)和至少一个收发器(图13中示例性的以包括一个收发器303为例进行说明)。可选的，网络设备30还可以包括至少一个存储器(图13中示例性的以包括一个存储器302为例进行 说明)和至少一个网络接口(图13中示例性的以包括一个网络接口304为例进行说明)。其中，处理器301、存储器302、收发器303和网络接口304通过通信线路相连接。网络接口304用于通过链路(例如S1接口)与核心网设备连接，或者通过有线或无线链路(例如X2接口)与其它网络设备的网络接口进行连接(图13中未示出)，本申请实施例对此不作具体限定。另外，处理器301、存储器302和收发器303的相关描述可参考终端设备40中处理器401、存储器402和收发器403的描述，在此不再赘述。
可以理解的是，图13所示的结构并不构成对网络设备30或终端设备40的具体限定。比如，在本申请另一些实施例中，网络设备30或终端设备40可以包括比图13所示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
下面将结合附图，以发送端装置和接收端装置之间的交互为例，对本申请实施例提供的交织与调制方法进行展开说明。
可以理解的，本申请实施例中，发送端装置和/或接收端装置可以执行本申请实施例中的部分或全部步骤，这些步骤或操作仅是示例，本申请实施例还可以执行其它操作或者各种操作的变形。此外，各个步骤可以按照本申请实施例呈现的不同的顺序来执行，并且有可能并非要执行本申请实施例中的全部操作。
如图14所示，为本申请实施例提供的一种数据处理方法，包括应用于发送端装置的交织与调制方法，以及应用于接收端装置的解交织与解调方法。该方法包括如下步骤：
S1401、发送端装置获取待交织的比特。
作为一种可能的实现，待交织的比特可以为编码比特。
作为另一种可能的实现，待交织的比特为对编码比特进行第二交织后的比特。将在后续实施例中进行详细说明，在此不予赘述。
可选的，编码比特是指通过编码器对输入编码器的比特进行编码后得到的比特。示例性的，编码比特可以为LDPC编码比特，或者可以是其他类型的编码比特，例如polar码或turbo码等，本申请对编码比特的类型不作具体限定。
S1402、发送端装置对待交织的比特进行第一交织，得到交织后的比特。
作为一种可能的实现，第一交织包括：将待交织的比特按照第一顺序逐列写入第一矩阵，并按照第二顺序从第一矩阵逐行读出。该场景下，第一矩阵的列数为调制阶数M，M大于或等于3。逐行读出的第一个比特为MSB，第M个比特为LSB。第一顺序和第二顺序将在后续实施例中详细说明，在此不予赘述。
可选的，读取的每一行比特组成比特流。其中每行比特的最左侧比特为MSB，最右侧比特为LSB。
可选的，在待交织的比特的个数N不能整除M时，第一矩阵的行数可以为
Figure PCTCN2022130890-appb-000002
其中，
Figure PCTCN2022130890-appb-000003
表示向下取整。该场景下，待交织的比特的后
Figure PCTCN2022130890-appb-000004
个比特可以不参与第一交织。
或者，第一矩阵的行数可以为
Figure PCTCN2022130890-appb-000005
其中，
Figure PCTCN2022130890-appb-000006
表示向上取整。该场景下，可以在待交织的比特后补
Figure PCTCN2022130890-appb-000007
个0，再对补0后的比特进行第一交织。
作为另一种可能的实现，第一交织可以包括：将待交织的比特按照第三顺序逐行写入第 一矩阵，并按照第四顺序从第一矩阵中逐列读出。该场景下，第一矩阵的行数为调制阶数M，M大于或等于3。逐列读出的第一个比特为MSB，最后一个比特为LSB。示例性的，可以将第一顺序的列替换成行得到第三顺序。第二顺序的列替换成行得到第四顺序。
S1403、发送端装置对交织后的比特进行调制，得到调制符号。
可选的，发送端装置使用的调制方式可以为DVB-S2标准中定义的相关调制方式。
S1404、发送端装置发送调制符号。相应的，接收端装置接收调制符号。
可选的，发送端装置发送调制符号，可以包括：发送端装置的调制模块输出调制符号。调制模块输出调制符号后，发送端装置的其他模块可以对调制符号进行IDFT并添加循环前缀等处理后生成发送信号，并向接收端装置发送该发送信号。
相应的，接收端装置可以接收该发送信号经过信道传输后的信号，并对接收到的信号进行去除CP、DFT等操作得到调制符号。即接收端装置接收调制符号，可以包括：接收端装置的解调模块接收(或输入)调制符号。
S1405、接收端装置对调制符号进行解调，得到待解交织的对数似然比(logarithm likelihood ratio，LLR)序列。
可以理解的，该解调对应的调制方式即为步骤S1403中发送端装置使用的调制方式。将在后续实施例中进行说明，在此不予赘述。
S1406、接收端装置对待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列。
其中，第一解交织包括：将待解交织的LLR序列按照第二顺序逐行写入第二矩阵，并按照第一顺序从第二矩阵逐列读出。第二矩阵的列数为调制阶数M，第二矩阵的行数可参考第一矩阵的相关说明，在此不再赘述。逐行写入的第一个比特为MSB，第M个比特为LSB。
S1407、接收端装置根据解交织后的第一LLR序列确定信息比特。
作为一种可能的实现，接收端装置可以对解交织后的第一LLR序列进行译码，得到信息比特。
作为另一种可能的实现，接收端装置可以对解交织后的第一LLR序列进行第二解交织，得到解交织后的第二LLR序列。对解交织后的第二LLR序列进行译码，得到信息比特。将在后续实施例中进行详细说明，在此不予赘述。
可选的，接收端装置确定信息比特后，便可获取发送端装置发送的内容，从而可以根据该内容进行相应处理，本申请对此不作具体限定。
以上对本申请提供的数据处理方法的整体流程进行了说明。下面对交织与调制方式进行详细说明。
可选的，本申请实施例中，第一矩阵的列从左至右依次排序，最左侧的列为第一列，最右侧的列为第M列，依次编号为列1，列2，…，列M。
可选的，发送端装置使用DVB-S2调制方式的情况下，将待交织的比特按照第一顺序逐列写入第一矩阵时，第一矩阵的M列可以对应M个比特位。其中，第一列对应最高比特位，第M列对应最低比特位。例如，M等于3时，第一列对应bit2，第二列对应bit1，第三列对应bit0。该场景下，第一顺序和第二顺序可能存在以下两种情况：
情况一、第一顺序与调制方式中比特的比特可靠性关联。例如，首个写入待交织的比特的列对应的比特可以为具有最高比特可靠性的比特，下一个写入待交织的比特的列对应的比特可靠性次之或与之相等，以此类推，最后写入待交织的比特的列对应的比特可靠性最低。相应的，第二顺序可以为第一矩阵的列的排列顺序。例如，M等于3时，第二顺序为第一矩 阵的第一列-第二列-第三列。
情况二、第一顺序为第一矩阵的列的排列顺序。例如，M等于3时，第一顺序为第一矩阵的第一列-第二列-第三列。第二顺序与调制方式中比特的比特可靠性关联。例如，首个读取的列对应的比特可以为具有最高比特可靠性的比特，下一个读取的列对应的比特的比特可靠性次之或与之相等，以此类推，最后读取的列对应的比特的比特可靠性最低。
下面对使用DVB-S2调制方式，调制阶数M等于3、4、5时，第一顺序和第二顺序的具体实现分别进行详细说明。
调制阶数M等于3时，上述步骤S1403中发送端装置进行调制时使用的调制方式为DVB-S2 8PSK，星座图如图1所示。上述步骤S1402和S1406中的第一顺序和第二顺序可以存在如下三种实现方式：
方式11、第一顺序为第一矩阵的第三列-第二列-第一列，可以表示为[W-3 2 1]。第二顺序为第一矩阵的第一列-第二列-第三列，可以表示为[R-1 2 3]。
可选的，该方式11的实现属于上述情况一。第一矩阵的第三列-第二列-第一列分别对应DVB-S2 8PSK的bit0、bit1、bit2。
参见图15，示出了方式11所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8，系统比特为a 0a 1a 2，根据图15所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第三列写入a 0a 1a 2，第二列写入a 3a 4a 5，第一列写入a 6a 7a 8。随后，第一行读出a 6a 3a 0，第二行读出a 7a 4a 1，第三行读出a 8a 5a 2。
基于该交织方案，可以将系统比特映射在bit0传输。由表1可知DVB-S2 8PSK调制中，bit0较bit2具有更高的可靠性，从而系统比特在bit0传输时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
如图16a所示，示出了调制方式为DVB-S2 8PSK的情况下，采用NR的交织方式与采用方式11所示的交织方式时的误块率(block error rate，BLER)性能对比。其中，仿真条件如下表2所示。
表2
Figure PCTCN2022130890-appb-000008
表2中的240:40:1160表示系统比特个数的最小取值为240，以40为步长递增，直至递增到最大取值1160。表2中的LDPC编码即为待交织的比特。图16a中的K为系统比特的个数，N为待交织的比特的个数，M为调制阶数。根据图16a可得，在相同的BLER下，图15所示的交织方式11比NR交织方式的SNR低0.1～1.2dB，即对于相同的BLER，图15所示的交织方式11对SNR的要求更低。也就是说，采用图15所示的交织方式11时BLER性能 可以提高0.1～1.2dB。
可选的，第一顺序和第二顺序为方式11所示时，第三顺序可以为第一矩阵的第三行-第二行-第一行。即先在第三行写入，再在第二行写入，最后在第一行写入。在每行写入时，按照从左到右的顺序写入。第四顺序可以为第一矩阵的第一行-第二行-第三行，即在每列读出时，先读第一行，再读第二行，最后读第三行。此外，按照从左到右的顺序读取每一列。即先读第一列的第一行-第二行-第三行，再读第二列的第一行-第二行-第三行，最后读第三列的第一行-第二行-第三行。交织图样如图16b所示。
示例性的，假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8，系统比特为a 0a 1a 2，发送端装置按照第三顺序将待交织的比特逐列写入第一矩阵后，第一矩阵的第三行写入a 0a 1a 2，第二行写入a 3a 4a 5，第一行写入a 6a 7a 8。随后，第一列读出a 6a 3a 0，第二列读出a 7a 4a 1，第三列读出a 8a 5a 2。
可以理解的，本申请实施例中，第一顺序和第二顺序的每一种实现均可以对应第三顺序和第四顺序的一种实现，可参考上述步骤S1402以及方式11中的相关描述，后续不再详细赘述。
方式12、第一顺序为第一矩阵的第二列-第三列-第一列，可以表示为[W-2 3 1]。第二顺序为第一矩阵的第一列-第二列-第三列，可以表示为[R-1 2 3]。
参见图17，示出了方式12所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8，系统比特为a 0a 1a 2，根据图17所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第二列写入a 0a 1a 2，第三列写入a 3a 4a 5，第一列写入a 6a 7a 8。随后，第一行读出a 6a 0a 3，第二行读出a 7a 1a 4，第三行读出a 8a 2a 5。
基于该交织方案，可以将系统比特映射在bit1上传输。由于DVB-S2 8PSK调制中，bit1较bit2具有更高的可靠性，从而系统比特在bit1传输相比于在bit2传输，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
方式13、第一顺序为第一矩阵的第一列-第二列-第三列，可以表示为[W-1 2 3]。第二顺序为第一矩阵的第二列-第三列-第一列，可以表示为[R-2 3 1]。
参见图18，示出了方式13所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8，系统比特为a 0a 1a 2，根据图18所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第一列写入a 0a 1a 2，第二列写入a 3a 4a 5，第三列写入a 6a 7a 8。随后，第一行读出a 3a 6a 0，第二行读出a 4a 7a 1，第三行读出a 5a 8a 2。
基于该交织方案，由于逐行读出的第一个比特为MSB，第M个比特为LSB，从而可以将系统比特映射在最低位传输。又由于DVB-S2 8PSK调制中，低位比特较高位比特具有更高的可靠性，从而系统比特在最低位传输相比于在高位比特传输，可以提高系统比特的传输可靠性，进而够提高系统的译码性能。
调制阶数M等于4时，上述步骤S1403中发送端装置进行调制时使用的调制方式为DVB-S2 16APSK，星座图如图2所示。上述步骤S1402和S1406中的第一顺序和第二顺序可以存在如下四种实现方式：
方式21、第一顺序为第一矩阵的第四列-第三列-第二列-第一列，可以表示为[W-4 3 2 1]。第二顺序为第一矩阵的第一列-第二列-第三列-第四列，可以表示为[R-1 2 3 4]。
参见图19，示出了方式21所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11，系统比特为a 0a 1a 2，根据图19所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第四列写入a 0a 1a 2，第三列写入a 3a 4a 5，第二列写入a 6a 7a 8，第一列写入a 9a 10a 11。随后，第一行读出a 9a 6a 3a 0，第二行读出a 10a 7a 4a 1， 第三行读出a 11a 8a 5a 2。
基于该交织方案，可以将系统比特映射在最低位传输。由于DVB-S2 16APSK调制中，bit0较bit3具有更高的可靠性，从而系统比特在bit0传输时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
如图20所示，示出了调制方式为DVB-S2 16PSK的情况下，采用NR的交织方式与采用方式21所示的交织方式时的BLER性能对比。其中，仿真条件如下表3所示。
表3
Figure PCTCN2022130890-appb-000009
表3和图20中的相关参数可参考表2和图16a的相关说明，在此不再赘述。根据图20可得，在相同的BLER下，交织方式21比NR交织方式的SNR低0.1～0.7dB，即对于相同的BLER，交织方式21对SNR的要求更低。也就是说，采用交织方式21时BLER性能可以提高0.1～0.7dB。
方式22、第一顺序为第一矩阵的第四列-第三列-第一列-第二列，可以表示为[W-4 3 1 2]。第二顺序为第一矩阵的第一列-第二列-第三列-第四列，可以表示为[R-1 2 3 4]。
参见图21，示出了方式22所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11，系统比特为a 0a 1a 2，根据图21所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第四列写入a 0a 1a 2，第三列写入a 3a 4a 5，第二列写入a 9a 10a 11，第一列写入a 6a 7a 8。随后，第一行读出a 6a 9a 3a 0，第二行读出a 7a 10a 4a 1，第三行读出a 8a 11a 5a 2。
基于该交织方案，也可以将系统比特映射在最低位传输。由于DVB-S2 16APSK调制中，bit0较bit3具有更高的可靠性，从而系统比特在bit0传输时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
方式23、第一顺序为第一矩阵的第三列-第四列-第二列-第一列，可以表示为[W-3 4 2 1]。第二顺序为第一矩阵的第一列-第二列-第三列-第四列，可以表示为[R-1 2 3 4]。
参见图22，示出了方式23所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11，系统比特为a 0a 1a 2，根据图22所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第四列写入a 3a 4a 5，第三列写入a 0a 1a 2，第二列写入a 6a 7a 8，第一列写入a 9a 10a 11。随后，第一行读出a 9a 6a 0a 3，第二行读出a 10a 7a 1a 4，第三行读出a 11a 8a 2a 5。
基于该交织方案，可以将系统比特映射在bit1传输。由于DVB-S2 16APSK调制中，bit1 较bit3或bit2具有更高的可靠性，从而系统比特在bit1传输时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
方式24、第一顺序为第一矩阵的第三列-第四列-第一列-第二列，可以表示为[W-3 4 1 2]。第二顺序为第一矩阵的第一列-第二列-第三列-第四列，可以表示为[R-1 2 3 4]。
参见图23，示出了方式24所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11，系统比特为a 0a 1a 2，根据图23所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第四列写入a 3a 4a 5，第三列写入a 0a 1a 2，第二列写入a 9a 10a 11，第一列写入a 6a 7a 8。随后，第一行读出a 6a 9a 0a 3，第二行读出a 7a 10a 1a 4，第三行读出a 8a 11a 2a 5。
基于该交织方案，也可以将系统比特映射在bit1传输，从而可以提高系统比特的传输可靠性，进而提高系统的译码性能。
调制阶数M等于5时，上述步骤S1403中发送端装置进行调制时使用的调制方式为DVB-S2 32APSK，星座图如图3所示。上述步骤S1402和S1406中的第一顺序和第二顺序可以存在如下四种实现方式：
方式31、第一顺序为第一矩阵的第四列-第三列-第二列-第一列-第五列，可以表示为[W-4 3 2 1 5]。第二顺序为第一矩阵的第一列-第二列-第三列-第四列-第五列，可以表示为[R-1 2 3 4 5]。
参见图24，示出了方式31所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11a 12a 13a 14，系统比特为a 0a 1a 2，根据图24所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第四列写入a 0a 1a 2，第三列写入a 3a 4a 5，第二列写入a 6a 7a 8，第一列写入a 9a 10a 11，第五列写入a 12a 13a 14。随后，第一行读出a 9a 6a 3a 0a 12，第二行读出a 10a 7a 4a 1a 13，第三行读出a 11a 8a 5a 2a 14。
基于该交织方案，可以将系统比特映射在bit1传输。由表1可知，DVB-S2 32APSK调制中，bit1较bit4具有更高的可靠性，从而系统比特在bit1传输时，可以提高系统比特的传输可靠性，进而提高系统的译码性能。
如图25所示，示出了调制方式为DVB-S2 32APSK的情况下，采用NR的交织方式与采用方式31所示的交织方式时的BLER性能对比。其中，仿真条件如下表4所示。
表4
Figure PCTCN2022130890-appb-000010
表4和图25中的相关参数可参考表2和图16a的相关说明，在此不再赘述。根据图25 可得，在相同的BLER下，交织方式31比NR交织方式的SNR低0.1～0.25dB，即对于相同的BLER，交织方式31对SNR的要求更低。也就是说，采用交织方式31时BLER性能可以提高0.1～0.5dB。
方式32、所述第一顺序为所述第一矩阵的第四列-第二列-第三列-第一列-第五列，可以表示为[W-4 2 3 1 5]。第二顺序为第一矩阵的第一列-第二列-第三列-第四列-第五列，可以表示为[R-1 2 3 4 5]。
参见图26，示出了方式32所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11a 12a 13a 14，系统比特为a 0a 1a 2，根据图26所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第四列写入a 0a 1a 2，第二列写入a 3a 4a 5，第一列写入a 9a 10a 11，第三列写入a 6a 7a 8，第五列写入a 12a 13a 14。随后，第一行读出a 9a 6a 3a 0a 12，第二行读出a 10a 4a 7a 1a 13，第三行读出a 11a 5a 8a 2a 14。
基于该交织方案，也可以将系统比特映射在bit1传输。从而可以提高系统比特的传输可靠性，进而提高系统的译码性能。
方式33、所述第一顺序为所述第一矩阵的第四列-第三列-第二列-第五列-第一列，可以表示为[W-4 3 2 5 1]。第二顺序为第一矩阵的第一列-第二列-第三列-第四列-第五列，可以表示为[R-1 2 3 4 5]。
参见图27，示出了方式33所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11a 12a 13a 14，系统比特为a 0a 1a 2，根据图27所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第四列写入a 0a 1a 2，第三列写入a 3a 4a 5，第二列写入a 6a 7a 8，第五列写入a 9a 10a 11，第一列写入a 13a 14a 15。随后，第一行读出a 13a 6a 3a 0a 9，第二行读出a 14a 7a 4a 1a 10，第三行读出a 15a 8a 5a 2a 11。
方式34、所述第一顺序为所述第一矩阵的第四列-第二列-第三列-第五列-第一列，可以表示为[W-4 2 3 5 1]。第二顺序为第一矩阵的第一列-第二列-第三列-第四列-第五列，可以表示为[R-1 2 3 4 5]。
参见图28，示出了方式34所述的发送端装置逐列写入和逐行读出的图样。假设待交织的比特为a 0a 1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11a 12a 13a 14，系统比特为a 0a 1a 2，根据图28所示的交织图样，发送端装置将待交织的比特逐列写入第一矩阵后，第一矩阵的第四列写入a 0a 1a 2，第二列写入a 3a 4a 5，第三列写入a 6a 7a 8，第五列写入a 9a 10a 11，第一列写入a 13a 14a 15。随后，第一行读出a 13a 3a 6a 0a 9，第二行读出a 14a 4a 7a 1a 10，第三行读出a 15a 5a 8a 2a 11。
基于上述方式32、33、34，也可以将系统比特映射在bit1传输，从而可以提高系统比特的传输可靠性，进而提高系统的译码性能。
可选的，若发送端装置使用的调制方式为基于DVB-S2的衍生方式，第一顺序或第二顺序也可以进行相应变化以适应该衍生方式，使得系统比特能够映射在具有较高可靠性的比特位传输。
示例性的，以DVB-S2 8PSK为例，若衍生方式为将图1所示星座图的bit2的值和bit1的值互换，那么该衍生方式对应的第一顺序可以为：将DVB-S2 8PSK对应的第一顺序中对应bit2和bit1的列的顺序互换后的顺序。例如上述方式11中，DVB-S2 8PSK对应的第一顺序为第三列-第二列-第一列，第三列-第二列-第一列分别对应DVB-S2 8PSK的bit0、bit1、bit2，互换后，该衍生方式对应的第一顺序可以为：第三列-第一列-第二列。第二顺序仍为第一矩阵的第一列-第二列-第三列。也就是说，第一顺序随每个星座点对应的不同比特位的取值的互换而变化，第二顺序不变。
或者，可以按照类似方式随每个星座点对应的不同比特位的取值的互换而改变第二顺序，第一顺序保持不变。
示例性的，以DVB-S2 8PSK为例，若衍生方式为将图1所示星座图的bit2的值和bit1的值互换，那么该衍生方式对应的第二顺序可以为：将DVB-S2 8PSK对应的第一顺序中对应bit2和bit1的列的顺序互换后的顺序。例如上述方式11中，DVB-S2 8PSK对应的第二顺序为第一列-第二列-第三列，第一列-第二列-第三列分别对应DVB-S2 8PSK的bit2、bit1、bit0，互换后，该衍生方式对应的第二顺序可以为：第二列-第一列-第三列。第一顺序不变。
上述实施例中，本申请提出新的交织方式，该交织方式在与卫星通信中的调制方式结合使用时，可以将系统比特映射在具有较高可靠性的比特位传输，从而提高传输可靠性和系统的译码性能。
如图29所示，为本申请实施例提供的另一种数据处理方法，包括应用于发送端装置的交织与调制方法，以及应用于接收端装置的解交织与解调方法。该方法包括如下步骤：
S2901、发送端装置获取待交织的比特。
可选的，待交织的比特可以为编码比特。或者，待交织的比特为对编码比特进行第二交织后的比特。可参考上述步骤S1401中的相关说明，在此不再赘述。
S2902、发送端装置对待交织的比特进行第一交织，得到交织后的比特。
其中，第一交织包括：将待交织的比特按照从左到右的顺序逐列写入第一矩阵，并按照从左到右的顺序从第一矩阵逐行读出。该场景下，第一矩阵的列数为调制阶数M，M大于或等于3。逐行读出的第一个比特为MSB，第M个比特为LSB。第一矩阵的行数可参考上述步骤S1402中的相关说明，在此不再赘述。
S2903、发送端装置对交织后的比特进行调制，得到调制符号。
其中，调制使用的星座图包括2 M个星座点，该2 M个星座点分布在N个圆环上，N个圆环中的至少一个圆环上的星座点满足格雷映射的原则，N为正整数。
S2904、发送端装置发送调制符号。相应的，接收端装置接收调制符号。
其中，步骤S2904的相关实现，可参考上述步骤S1404中的详细说明，在此不再赘述。
S2905、接收端装置对调制符号进行解调，得到待解交织的LLR序列。
可以理解的，该解调对应的调制方式的星座图即为步骤S2903中描述的星座图。
S2906、接收端装置对待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列。
其中，第一解交织包括：将待解交织的LLR序列按照从左到右的顺序逐行写入第二矩阵，并按照从左到右的顺序从第二矩阵逐列读出。第二矩阵的列数为调制阶数M，第二矩阵的行数可参考第一矩阵的相关说明，在此不再赘述。逐行写入的第一个比特为MSB，第M个比特为LSB。
S2907、接收端装置根据解交织后的第一LLR序列确定信息比特。
其中，步骤S2907的相关实现，可参考上述步骤S1407中的详细说明，在此不再赘述。
下面对发送端装置使用第一交织，调制阶数M等于3、4、5时，S2903中的星座图分别进行详细说明。
调制阶数M等于3时，上述步骤S2903中的星座图包括8个星座点，8个星座点均匀分布在一个圆环上。示例性的，8个星座点的分布可以存在如下四种实现方式：
方式41、如图30所示，第一星座点对应的相位为π/4。第一星座点对应的比特为000。以第一星座点为基准，按照顺时针方向，剩余7个星座点对应的比特分别为：010、011、111、 110、100、101、001。
如图31所示，示出了采用步骤S2902所述的第一交织的情况下，使用图2所示的DVB-S28PSK和方式41所示的星座图时的BLER性能对比。其中，仿真条件如下表5所示。
表5
Figure PCTCN2022130890-appb-000011
表5和图32中的相关参数可参考表2和图16a的相关说明，在此不再赘述。根据图32可得，在相同的BLER下，采用图30所示的星座图比采用图2所示的星座图的SNR低0.1～1.2dB，即采用图30所示的星座图时BLER性能可以提高0.1～1.2dB。
方式42、如图32所示，第一星座点对应的相位为π/4。第一星座点对应的比特为000。以第一星座点为基准，按照顺时针方向，剩余7个星座点对应的比特分别为：100、101、111、110、010、011、001。
方式43、如图33所示，第一星座点对应的相位为π/8。第一星座点对应的比特为000。以第一星座点为基准，按照顺时针方向，剩余7个星座点对应的比特分别为：010、011、111、110、100、101、001。
方式44、如图34所示，第一星座点对应的相位为π/8。第一星座点对应的比特为000。以第一星座点为基准，按照顺时针方向，剩余7个星座点对应的比特分别为：100、101、111、110、010、011、001。
可以理解的，上述方式41、方式42、方式43、以及方式44所述的星座图中，第一圆环上的星座点满足格雷映射的原则。
调制阶数M等于4时，上述步骤S2903中的星座图包括16个星座点，16个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分别在第二圆环上。第一圆环和第二圆环为同心环。第一圆环上的第一星座点和第二圆环上的第二星座点对应的相位为π/4。
示例性的，16个星座点的分布可以存在如下四种实现方式：
方式51、如图35所示，第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0001、0101、0100、0110、1110、1100、1101、1001、1000、1010、0010。
如图35所示，0011和0000对应的相位为π/4，0001对应的相位为π/12。R1表示第一圆环的半径，R2表示第二圆环的半径。
方式52、如图36所示，第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0010、0110、0100、0101、1101、1100、1110、1010、1000、1001、0001。
如图36所示，0011和0000对应的相位为π/4，0010对应的相位为π/12。R1表示第一圆环的半径，R2表示第二圆环的半径。图36所示的星座图可以是将图35所示的星座图中，bit0和bit1的值互换得到的。
方式53、如图37所示，第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0001、1001、1000、1010、1110、1100、1101、0101、0100、0110、0010。
如图37所示，0011和0000对应的相位为π/4，0001对应的相位为π/12。R1表示第一圆环的半径，R2表示第二圆环的半径。图37所示的星座图可以是将图35所示的星座图中，bit2和bit3的值互换得到的。
方式54、如图38所示，第一星座点对应的比特为0011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111。
第二星座点对应的比特为0000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：0010、1010、1000、1001、1101、1100、1110、0110、0100、0101、0001。
如图38所示，0011和0000对应的相位为π/4，0010对应的相位为π/12。R1表示第一圆环的半径，R2表示第二圆环的半径。图38所示的星座图可以是将图35所示的星座图中，bit0和bit1的值互换、以及bit2和bit3的值互换得到的。
可以理解的，上述方式51、方式52、方式53、以及方式54所述的星座图中，第一圆环和第二圆环上的星座点均满足格雷映射的原则。
调制阶数M等于5时，上述步骤S2903中的星座图包括32个星座点，32个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分布在第二圆环上，剩余16个星座点均匀分布在第三圆环上。第一圆环、第二圆环、和第三圆环为同心环。第一圆环上的第一星座点、第二圆环上的第二星座点、和第三圆环上的第三星座点对应的相位为π/4。示例性的，32个星座点的分布可以存在如下四种实现方式：
方式61、如图39所示，第一星座点对应的比特为00011，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01011。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：00001、00101、00100、00110、01110、01100、01101、01001、01000、01010、00010。
第三星座点对应的比特为10011，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10101、10100、10111、10110、11110、11111、11100、11101、11001、11000、11011、11010、10010。
如图39所示，00011、00000、和10011对应的相位为π/4，00001对应的相位为π/12。R1表示第一圆环的半径，R2表示第二圆环的半径，R3表示第三圆环的半径。
方式62、如图40所示，第一星座点对应的比特为00101，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01101。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：00001、00011、00010、00110、01110、01010、01011、01001、01000、01100、00100。
第三星座点对应的比特为10101，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10011、10010、10111、10110、11110、11111、11010、11011、11001、11000、11101、11100、10100。
如图40所示，00101、00000、和10101对应的相位为π/4，00001对应的相位为π/12。R1表示第一圆环的半径，R2表示第二圆环的半径，R3表示第三圆环的半径。图40所示的星座图可以是将图39所示的星座图中，bit2和bit1的值互换得到的。
方式63、如图41所示，第一星座点对应的比特为10010，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11010。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：10000、10100、00100、00110、01110、01100、11100、11000、01000、01010、00010。
第三星座点对应的比特为10011，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10101、00101、10111、00111、01111、11111、01101、11101、11001、01001、11011、01011、00011。
如图41所示，10010、00000、和10011对应的相位为π/4，10000对应的相位为π/12。R1表示第一圆环的半径，R2表示第二圆环的半径，R3表示第三圆环的半径。图41所示的星座图可以是将图39所示的星座图中，bit0和bit4的值互换得到的。
方式64、如图42所示，第一星座点对应的比特为10100，以第一星座点为基准，按照顺时针方向，第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11100。
第二星座点对应的比特为00000，以第二星座点为基准，按照顺时针方向，第二圆环上的剩余11个星座点对应的比特分别为：10000、10010、00010、00110、01110、01010、11010、11000、01000、01100、00100。
第三星座点对应的比特为10101，以第三星座点为基准，按照顺时针方向，第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10011、00011、10111、00111、01111、11111、01011、11011、11001、01001、11101、01101、00101。
如图42所示，10100、00000、和10101对应的相位为π/4，10000对应的相位为π/12。R1表示第一圆环的半径，R2表示第二圆环的半径，R3表示第三圆环的半径。图42所示的星座图可以是将图39所示的星座图中，bit0和bit4的值互换、以及bit2和bit1的值互换得到的。
可以理解的，上述方式61、方式62、方式63、以及方式64所述的星座图中，第一圆环和第二圆环上的星座点满足格雷映射的原则。
上述图29所示的实施例中，提出新的调制方式(或星座映射方式)，该调制方式在与NR中的交织方式(即从左到右逐列写入，再从左到右逐行读出)结合使用时，可以将具有较高的BLER性能，从而可以提高传输可靠性和系统的译码性能。
可选的，上述步骤S1401和步骤S2901中的第二交织可以包括：对编码比特的后N-X个比特进行随机交织或伪随机交织。X大于或等于系统比特的个数，N为编码比特的个数。即 在第二交织中，前X个比特不参与交织，顺序不变。示例性的，在码率较低，例如码率低于1/5时，X可以等于N除以调制阶数M。
也就是说，如图43所示，发送端装置对编码比特进行两次交织，得到交织后的比特。后续对该交织后的比特进行调制。
可以理解的，第一交织可以为步骤S1401所述的交织方式。相应的，调制方式使用DVB-S2中的调制方式。例如，参见图44，调制阶数M等于5时，第一交织采用上述方式31。或者，第一交织可以为步骤S2901所述的交织方式。相应的，调制方式使用步骤S2903所述的调制方式。
示例性的，以系统比特的个数K等于352，编码比特的个数N等于2640，调制阶数M等于5为例，假设X＝N/M＝528，则编码比特的前528的顺序不变，后N-X＝2112个进行伪随机交织。
在伪随机交织时，发送端装置可以将后2112个比特分段，每个比特分段包括Y(以300为例)个比特，分段数为
Figure PCTCN2022130890-appb-000012
分段后剩余的2112-300×7＝12个比特可以不进行交织。最终将前528个比特，分段伪随机交织后的2100个比特，和剩余不交织的12个比特作为待交织的比特。
可选的，发送端装置和接收端装置可以协商约定或设定伪随机交织的顺序。例如，在分段长度为300时，发送端装置使用的伪随机交织顺序可以如下所示，其中的数字为比特的索引，用于指示比特的位置。例如123表示300个比特中的第123个比特，99表示300个比特中的第99个比特。
[123,99,174,294,244,281,32,40,22,261,175,34,152,92,170,91,146,119,190,112,127,241,165,35,6,265,121,271,228,160,236,55,148,3,96,166,136,269,68,16,140,135,69,115,11,101,54,105,296,176,218,30,133,291,186,149,224,45,184,216,77,280,211,235,60,217,219,113,214,254,171,249,147,292,150,163,74,78,72,62,70,229,129,266,232,242,107,134,51,33,7,86,182,237,212,196,221,103,38,238,278,267,100,157,58,76,205,143,81,172,259,187,159,202,89,42,162,28,258,128,145,164,230,151,17,239,223,131,220,194,41,227,120,47,195,111,180,250,98,213,300,80,284,14,193,247,255,156,46,295,155,273,56,283,299,63,240,197,198,144,253,104,93,204,117,252,8,181,67,84,139,208,90,97,169,290,248,138,83,59,210,231,106,233,286,79,287,142,209,256,188,5,201,48,179,177,272,108,53,29,21,25,257,52,268,185,109,37,279,64,31,49,234,298,275,270,246,178,27,282,183,110,61,88,50,87,26,43,124,192,274,94,189,161,19,102,200,44,264,130,15,243,289,203,73,1,125,199,173,36,116,82,71,215,23,141,288,126,137,207,262,293,65,277,158,153,276,285,225,2,132,263,114,4,18,85,222,245,75,191,24,95,206,167,154,39,168,13,9,66,20,57,122,251,10,12,297,226,260,118]。
基于前述第二交织，上述步骤S1407和步骤S2907中的第二解交织可以包括：对第一LLR序列的后N-X个元素按照预设顺序进行解交织。该预设顺序即为发送端使用的伪随机交织或随机交织的顺序。
参见图45、图46、图47，示出了调制阶数M等于5，发送端对编码比特进行第二交织和第一交织，采用32APSK调制时的BLER性能仿真结果。仿真条件如下表6所示。
表6
Figure PCTCN2022130890-appb-000013
Figure PCTCN2022130890-appb-000014
表6和图45、图46、图47中的相关参数可参考表2和图16a的相关说明，在此不再赘述。根据图45、图46、图47可得，在相同的BLER下，采用图44所示的交织方式比采用NR交织方式的SNR低0.5～1dB，即采用图44所示的交织方式时BLER性能可以提高0.5～1dB。
此外，参见表7，示出了添加CRC的系统比特经过LDPC编码以及第二交织和第一交织，并通过加扰后，采用图3所示的星座图映射得到调制符号的场景下，不同星座点的映射概率。
表7
星座点 概率(％) 星座点 概率(％) 星座点 概率(％) 星座点 概率(％)
0 3.14 8 3.09 16 3.12 24 3.12
1 3.11 9 3.16 17 3.12 25 3.11
2 3.11 10 3.14 18 3.11 26 3.15
3 3.15 11 3.13 19 3.09 27 3.13
4 3.10 12 3.12 20 3.13 28 3.12
5 3.12 13 3.14 21 3.14 29 3.14
6 3.09 14 3.13 22 3.12 30 3.10
7 3.15 15 3.15 23 3.14 31 3.13
参见表8，示出了添加CRC的系统比特经过LDPC编码以及NR交织加扰后，采用图3所示的星座图映射得到调制符号的场景下，不同星座点的映射概率。其中，表7和表8中系统比特的个数K等于1404(包括16比特CRC)，编码比特的个数N等于11940。LDPC编码采用BG2矩阵。
表8
星座点 概率(％) 星座点 概率(％) 星座点 概率(％) 星座点 概率(％)
0 4.03 8 2.97 16 3.04 24 2.46
1 2.98 9 4.02 17 2.45 25 3.06
2 3.04 10 2.46 18 4.03 26 3.01
3 2.45 11 3.02 19 2.99 27 4.01
4 4.01 12 2.98 20 3.05 28 2.45
5 2.98 13 4.00 21 2.46 29 3.03
6 3.04 14 2.45 22 4.02 30 2.99
7 2.45 15 3.04 23 2.97 31 4.02
由表8可得，32个星座点的映射概率的波动范围为2.45％～4.02％，即映射概率分布差异较大，存在星座映射不均匀的问题，从而导致系统译码性能下降。
由表7可得，采用两次交织时，32个星座点的映射概率相近，波动范围在3.09％～3.16％，相比于表7所示的结果得到很大改善。也就是说，采用两次交织可以降低星座点的映射概率的波动范围，提高译码性能。
可以理解的是，以上各个实施例中，由接收端装置实现的方法和/或步骤，也可以由可用于该接收端装置的部件(例如处理器、芯片、芯片系统、电路、逻辑模块、或软件)实现；由发送端装置实现的方法和/或步骤，也可以有可用于该发送端装置的部件(例如处理器、芯片、芯片系统、电路、逻辑模块、或软件)实现。
上述主要从各个装置之间交互的角度对本申请提供的方案进行了介绍。相应的，本申请还提供了通信装置，该通信装置用于实现上述各种方法。该通信装置可以为上述方法实施例中的接收端装置，或者包含上述接收端装置的设备，或者为可用于接收端装置的部件；或者，该通信装置可以为上述方法实施例中的发送端装置，或者包含上述发送端装置的设备，或者为可用于发送端装置的部件。
可以理解的是，该通信装置为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法实施例对通信装置进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在一种实施场景下，以通信装置为上述方法实施例中的发送端装置为例，图48示出了一种发送端装置480的结构示意图。该发送端装置480包括处理模块4801和收发模块4802。
在一些实施例中，该发送端装置480还可以包括存储模块(图48中未示出)，用于存储程序指令和数据。
在一些实施例中，收发模块4802，也可以称为收发单元用以实现发送和/或接收功能。该收发模块4802可以由收发电路，收发机，收发器或者通信接口构成。
在一些实施例中，收发模块4802，可以包括接收模块和发送模块，分别用于执行上述方法实施例中由发送端装置执行的接收和发送类的步骤，和/或用于支持本文所描述的技术的其它过程；处理模块4801，可以用于执行上述方法实施例中由发送端装置执行的处理类(例如确定、获取、生成等)的步骤，和/或用于支持本文所描述的技术的其它过程。
作为一种可能的实现：
处理模块4801，用于获取待交织的比特；处理模块4801，还用于对待交织的比特进行第一交织，得到交织后的比特，第一交织包括：将待交织的比特按照第一顺序逐列写入第一矩阵，并按照第二顺序从第一矩阵逐行读出；第一矩阵的列数为调制阶数M，M大于或等于3； 逐行读出的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB；处理模块4801，还用于对交织后的比特进行调制，得到调制符号；收发模块4802，用于发送调制符号。
作为另一种可能的实现：
处理模块4801，用于获取待交织的比特；处理模块4801，还用于对待交织的比特进行第一交织，得到交织后的比特，第一交织包括：将待交织的比特按照从左到右的顺序逐列写入第一矩阵，并按照从左到右的顺序从第一矩阵逐行读出；第一矩阵的列数为调制阶数M，M大于或等于3；逐行读出的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB；处理模块4801，还用于对交织后的比特进行调制，得到调制符号；调制使用的星座图包括2 M个星座点，2 M个星座点分布在N个圆环上，N个圆环中的至少一个圆环上的星座点满足格雷映射的原则，N为正整数；收发模块4802，用于发送调制符号。
其中，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
在本申请中，该发送端装置480以采用集成的方式划分各个功能模块的形式来呈现。这里的“模块”可以指特定专用集成电路(application-specific integrated circuit，ASIC)，电路，执行一个或多个软件或固件程序的处理器和存储器，集成逻辑电路，和/或其他可以提供上述功能的器件。
在一些实施例中，在硬件实现上，发送端装置为终端设备时，本领域的技术人员可以想到该发送端装置480可以采用图13所示的终端设备40的形式。
作为一种示例，图48中的处理模块4801的功能/实现过程可以通过图13所示的终端设备40中的处理器401调用存储器402中存储的计算机执行指令来实现，图48中的收发模块4802的功能/实现过程可以通过图13所示的终端设备40中的收发器403来实现。
在一些实施例中，在硬件实现上，发送端装置为网络设备时，本领域的技术人员可以想到该发送端装置480可以采用图13所示的网络设备30的形式。
作为一种示例，图48中的处理模块4801的功能/实现过程可以通过图13所示的网络设备30中的处理器301调用存储器302中存储的计算机执行指令来实现，图48中的收发模块4802的功能/实现过程可以通过图13所示的网络设备30中的收发器303来实现。
在一些实施例中，当图48中的发送端装置480是芯片或芯片系统时，收发模块4802的功能/实现过程可以通过芯片或芯片系统的输入输出接口(或通信接口)实现，处理模块4801的功能/实现过程可以通过芯片或芯片系统的处理器(或者处理电路)实现。
由于本实施例提供的发送端装置480可执行上述方法，因此其所能获得的技术效果可参考上述方法实施例，在此不再赘述。
在一种实施场景下，以通信装置为上述方法实施例中的接收端装置为例，图49示出了一种接收端装置490的结构示意图。该接收端装置490包括处理模块4901和收发模块4902。
在一些实施例中，该接收端装置490还可以包括存储模块(图49中未示出)，用于存储程序指令和数据。
在一些实施例中，收发模块4902，也可以称为收发单元用以实现发送和/或接收功能。该收发模块4902可以由收发电路，收发机，收发器或者通信接口构成。
在一些实施例中，收发模块4902，可以包括接收模块和发送模块，分别用于执行上述方法实施例中由接收端装置执行的接收和发送类的步骤，和/或用于支持本文所描述的技术的其它过程；处理模块4901，可以用于执行上述方法实施例中由接收端装置执行的处理类(例如确定、获取、生成等)的步骤，和/或用于支持本文所描述的技术的其它过程。
作为一种可能的实现：
收发模块4902，用于接收调制符号；处理模块4901，用于对调制符号进行解调，得到待解交织的对数似然比LLR序列；处理模块4901，还用于对待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列，第一解交织包括：按照第二顺序逐行写入第二矩阵，并按照第一顺序从第二矩阵逐列读出；第二矩阵的列数为调制阶数M，M大于或等于3；逐行写入的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB；处理模块4901，还用于根据解交织后的第一LLR序列确定信息比特。
作为另一种可能的实现：
收发模块4902，用于接收调制符号；处理模块4901，用于对调制符号进行解调，得到待解交织的对数似然比LLR序列；处理模块4901，还用于对待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列；第一解交织包括：按照从左到右的顺序逐行写入第二矩阵，并按照从左到右的顺序从第二矩阵逐列读出；第二矩阵的列数为调制阶数M，M大于或等于3；逐行写入的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB；处理模块4901，还用于根据解交织后的第一LLR序列确定信息比特；其中，解调使用的星座图包括2 M个星座点，2 M个星座点分布在N个圆环上，N个圆环中的至少一个圆环上的星座点满足格雷映射的原则，N为正整数。
可选的，处理模块4901，用于根据解交织后的第一LLR序列确定信息比特，包括：处理模块4901，用于对解交织后的第一LLR序列进行译码，得到信息比特。
可选的，处理模块4901，用于根据解交织后的第一LLR序列确定信息比特，包括：处理模块4901，用于对解交织后的第一LLR序列进行第二解交织，得到解交织后的第二LLR序列；处理模块4901，还用于对解交织后的第二LLR序列进行译码，得到信息比特。
其中，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
在本申请中，该接收端装置490以采用集成的方式划分各个功能模块的形式来呈现。这里的“模块”可以指特定专用集成电路(application-specific integrated circuit，ASIC)，电路，执行一个或多个软件或固件程序的处理器和存储器，集成逻辑电路，和/或其他可以提供上述功能的器件。
在一些实施例中，在硬件实现上，接收端装置为网络设备时，本领域的技术人员可以想到该接收端装置490可以采用图13所示的网络设备30的形式。
作为一种示例，图49中的处理模块4901的功能/实现过程可以通过图13所示的网络设备30中的处理器301调用存储器302中存储的计算机执行指令来实现，图49中的收发模块4902的功能/实现过程可以通过图13所示的网络设备30中的收发器303来实现。
在一些实施例中，在硬件实现上，接收端装置为终端设备时，本领域的技术人员可以想到该接收端装置490可以采用图13所示的终端设备40的形式。
作为一种示例，图49中的处理模块4901的功能/实现过程可以通过图13所示的终端设备40中的处理器401调用存储器402中存储的计算机执行指令来实现，图49中的收发模块4902的功能/实现过程可以通过图13所示的终端设备40中的收发器403来实现。
在一些实施例中，当图49中的接收端装置490是芯片或芯片系统时，收发模块4902的功能/实现过程可以通过芯片或芯片系统的输入输出接口(或通信接口)实现，处理模块4901的功能/实现过程可以通过芯片或芯片系统的处理器(或者处理电路)实现。
由于本实施例提供的接收端装置490可执行上述方法，因此其所能获得的技术效果可参 考上述方法实施例，在此不再赘述。
在一些实施例中，本申请实施例还提供一种通信装置，该通信装置包括处理器，用于实现上述任一方法实施例中的方法。
作为一种可能的实现方式，该通信装置还包括存储器。该存储器，用于保存必要的程序指令和数据，处理器可以调用存储器中存储的程序代码以指令该通信装置执行上述任一方法实施例中的方法。当然，存储器也可以不在该通信装置中。
作为另一种可能的实现方式，该通信装置还包括接口电路，该接口电路为代码/数据读写接口电路，该接口电路用于接收计算机执行指令(计算机执行指令存储在存储器中，可能直接从存储器读取，或可能经过其他器件)并传输至该处理器。
作为又一种可能的实现方式，该通信装置还包括通信接口，该通信接口用于与该通信装置之外的模块通信。
可以理解的是，该通信装置可以是芯片或芯片系统，该通信装置是芯片系统时，可以由芯片构成，也可以包含芯片和其他分立器件，本申请实施例对此不作具体限定。
在一些实施例中，本申请实施例还提供了一种通信装置，该通信装置包括接口电路和逻辑电路，该接口电路用于输入和/或输出信息；该逻辑电路，用于执行上述任一方法实施例中的方法，对输入的信息进行处理和/或生成输出的信息。
作为一种可能的实现，该通信装置用于实现上述发送端装置的功能时：输出的信息为调制符号。
作为一种可能的实现，该通信装置用于实现上述接收端装置的功能时：输入的信息为调制符号。对输入的信息进行处理，包括：对调制符号进行解调，得到待解交织的对数似然比LLR序列。对待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列。根据解交织后的第一LLR序列确定信息比特。
作为一种可能的产品形态，本申请实施例所述的发送端装置和接收端装置，还可以使用下述来实现：一个或多个现场可编程门阵列(field programmable gate array，FPGA)、可编程逻辑器件(programmable logic device，PLD)、控制器、状态机、门逻辑、分立硬件部件、任何其它适合的电路、或者能够执行本申请通篇所描述的各种功能的电路的任意组合。
本申请还提供了一种计算机可读存储介质，其上存储有计算机程序或指令，该计算机程序或指令被计算机执行时实现上述任一方法实施例的功能。
本申请还提供了一种计算机程序产品，该计算机程序产品被计算机执行时实现上述任一方法实施例的功能。
本领域普通技术人员可以理解，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
可以理解，本申请中描述的系统、装置和方法也可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，即可以位于一个地方，或者也可以分布到多个网络单元上。作为单元显示的部件可以是或者也可以不是物理单元。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或者数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可以用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)，光介质(例如，DVD)、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。本申请实施例中,计算机可以包括前面所述的装置。
尽管在此结合各实施例对本申请进行了描述，然而，在实施所要求保护的本申请过程中，本领域技术人员通过查看所述附图、公开内容、以及所附权利要求书，可理解并实现所述公开实施例的其他变化。在权利要求中，“包括”(comprising)一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。单个处理器或其他单元可以实现权利要求中列举的若干项功能。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (25)

  1. 一种交织与调制方法，其特征在于，所述方法包括：
    获取待交织的比特；
    对所述待交织的比特进行第一交织，得到交织后的比特，所述第一交织包括：将所述待交织的比特按照第一顺序逐列写入第一矩阵，并按照第二顺序从所述第一矩阵逐行读出；所述第一矩阵的列数为调制阶数M，所述M大于或等于3；所述逐行读出的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB；
    对所述交织后的比特进行调制，得到调制符号；
    发送所述调制符号；
    其中，所述M等于3时：所述调制使用的方式为第二代卫星数字视频广播DVB-S2 8相移键控PSK；
    所述第一顺序为所述第一矩阵的第三列-第二列-第一列，所述第二顺序为所述第一矩阵的第一列-第二列-第三列；
    或者，所述第一顺序为所述第一矩阵的第二列-第三列-第一列，所述第二顺序为所述第一矩阵的第一列-第二列-第三列；
    或者，所述第一顺序为所述第一矩阵的第一列-第二列-第三列，所述第二顺序为所述第一矩阵的第二列-第三列-第一列。
  2. 根据权利要求1所述的方法，其特征在于，所述M等于4时，所述调制使用的方式为DVB-S2 16幅度相移键控APSK；所述第二顺序为所述第一矩阵的第一列-第二列-第三列-第四列；
    所述第一顺序为所述第一矩阵的第四列-第三列-第二列-第一列；
    或者，所述第一顺序为所述第一矩阵的第四列-第三列-第一列-第二列；
    或者，所述第一顺序为所述第一矩阵的第三列-第四列-第二列-第一列；
    或者，所述第一顺序为所述第一矩阵的第三列-第四列-第一列-第二列。
  3. 根据权利要求1或2所述的方法，其特征在于，所述M等于5时，所述调制使用的方式为DVB-S2 32APSK；所述第二顺序为所述第一矩阵的第一列-第二列-第三列-第四列-第五列；
    所述第一顺序为所述第一矩阵的第四列-第三列-第二列-第一列-第五列；
    或者，所述第一顺序为所述第一矩阵的第四列-第二列-第三列-第一列-第五列；
    或者，所述第一顺序为所述第一矩阵的第四列-第三列-第二列-第五列-第一列；
    或者，所述第一顺序为所述第一矩阵的第四列-第二列-第三列-第五列-第一列。
  4. 一种交织与调制方法，其特征在于，所述方法包括：
    获取待交织的比特；
    对所述待交织的比特进行第一交织，得到交织后的比特，所述第一交织包括：将所述待交织的比特按照从左到右的顺序逐列写入第一矩阵，并按照从左到右的顺序从所述第一矩阵逐行读出；所述第一矩阵的列数为调制阶数M，所述M大于或等于3；所述逐行读出的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB；
    对所述交织后的比特进行调制，得到调制符号；所述调制使用的星座图包括2 M个星座点，所述2 M个星座点分布在N个圆环上，所述N个圆环中的至少一个圆环上的星座点满足格雷映射的原则，N为正整数；
    发送所述调制符号。
  5. 根据权利要求4所述的方法，其特征在于，所述M等于3时，所述8个星座点均匀分布在一个圆环上；
    第一星座点对应的相位为π/4或π/8，所述第一星座点对应的比特为000；以所述第一星座点为基准，按照顺时针方向，剩余7个星座点对应的比特分别为：010、011、111、110、100、101、001，或者，分别为：100、101、111、110、010、011、001。
  6. 根据权利要求4或5所述的方法，其特征在于，所述M等于4时，所述16个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分布在第二圆环上，所述第一圆环和所述第二圆环为同心环；所述第一圆环上的第一星座点和所述第二圆环上的第二星座点对应的相位为π/4；
    其中：
    所述第一星座点对应的比特为0011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011；
    所述第二星座点对应的比特为0000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：0001、0101、0100、0110、1110、1100、1101、1001、1000、1010、0010；
    或者，
    所述第一星座点对应的比特为0011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011；
    所述第二星座点对应的比特为0000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：0010、0110、0100、0101、1101、1100、1110、1010、1000、1001、0001；
    或者，
    所述第一星座点对应的比特为0011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111；
    所述第二星座点对应的比特为0000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：0001、1001、1000、1010、1110、1100、1101、0101、0100、0110、0010；
    或者，
    所述第一星座点对应的比特为0011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111；
    所述第二星座点对应的比特为0000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：0010、1010、1000、1001、1101、1100、1110、0110、0100、0101、0001。
  7. 根据权利要求4-6中任一项所述的方法，其特征在于，所述M等于5时，所述32个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分布在第二圆环上，剩余16个星座点均匀分布在第三圆环上，所述第一圆环、所述第二圆环、和所述第三圆环为同心环；所述第一圆环上的第一星座点、所述第二圆环上的第二星座点、和所述第三圆环上的第三星座点对应的相位为π/4；
    其中：
    所述第一星座点对应的比特为00011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01011；
    所述第二星座点对应的比特为00000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：00001、00101、00100、00110、01110、01100、01101、01001、01000、01010、00010；
    所述第三星座点对应的比特为10011，以所述第三星座点为基准，按照顺时针方向，所述第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10101、10100、10111、10110、11110、11111、11100、11101、11001、11000、11011、11010、10010；
    或者，
    所述第一星座点对应的比特为00101，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01101；
    所述第二星座点对应的比特为00000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：00001、00011、00010、00110、01110、01010、01011、01001、01000、01100、00100；
    所述第三星座点对应的比特为10101，以所述第三星座点为基准，按照顺时针方向，所述第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10011、10010、10111、10110、11110、11111、11010、11011、11001、11000、11101、11100、10100；
    或者，
    所述第一星座点对应的比特为10010，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11010；
    所述第二星座点对应的比特为00000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：10000、10100、00100、00110、01110、01100、11100、11000、01000、01010、00010；
    所述第三星座点对应的比特为10011，以所述第三星座点为基准，按照顺时针方向，所述第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10101、00101、10111、00111、01111、11111、01101、11101、11001、01001、11011、01011、00011；
    或者，
    所述第一星座点对应的比特为10100，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11100；
    所述第二星座点对应的比特为00000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：10000、10010、00010、00110、01110、01010、11010、11000、01000、01100、00100；
    所述第三星座点对应的比特为10101，以所述第三星座点为基准，按照顺时针方向，所述第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10011、00011、10111、00111、01111、11111、01011、11011、11001、01001、11101、01101、00101。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，所述待交织的比特为编码比特；或者，所述待交织的比特为对编码比特进行第二交织后的比特。
  9. 根据权利要求8所述的方法，其特征在于，所述第二交织包括：对所述编码比特的后N-X个比特进行随机或伪随机交织；所述X大于或等于系统比特的个数，所述N为所述编码比特的个数。
  10. 一种解交织与解调方法，其特征在于，所述方法包括：
    接收调制符号；
    对所述调制符号进行解调，得到待解交织的对数似然比LLR序列；
    对所述待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列，所述第一解交织包括：将所述待解交织的LLR序列按照第二顺序逐行写入第二矩阵，并按照第一顺序从所述第二矩阵逐列读出；所述第二矩阵的列数为调制阶数M，所述M大于或等于3；所述逐行写入的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB；
    根据所述解交织后的第一LLR序列确定信息比特；
    其中，所述M等于3时：所述解调对应的调制方式为第二代卫星数字视频广播DVB-S2 8相移键控PSK；
    所述第一顺序为所述第二矩阵的第三列-第二列-第一列，所述第二顺序为所述第二矩阵的第一列-第二列-第三列；
    或者，所述第一顺序为所述第二矩阵的第二列-第三列-第一列，所述第二顺序为所述第二矩阵的第一列-第二列-第三列；
    或者，所述第一顺序为所述第二矩阵的第一列-第二列-第三列，所述第二顺序为所述第二矩阵的第二列-第三列-第一列。
  11. 根据权利要求10所述的方法，其特征在于，所述M等于4时，所述解调对应的调制方式为DVB-S2 16幅度相移键控APSK；所述第二顺序为所述第二矩阵的第一列-第二列-第三列-第四列；
    所述第一顺序为所述第二矩阵的第四列-第三列-第二列-第一列；
    或者，所述第一顺序为所述第二矩阵的第四列-第三列-第一列-第二列；
    或者，所述第一顺序为所述第二矩阵的第三列-第四列-第二列-第一列；
    或者，所述第一顺序为所述第二矩阵的第三列-第四列-第一列-第二列。
  12. 根据权利要求10或11所述的方法，其特征在于，所述M等于5时，所述解调对应的调制方式为DVB-S2 32APSK；所述第二顺序为所述第二矩阵的第一列-第二列-第三列-第四列-第五列；
    所述第一顺序为所述第二矩阵的第四列-第三列-第二列-第一列-第五列；
    或者，所述第一顺序为所述第二矩阵的第四列-第二列-第三列-第一列-第五列；
    或者，所述第一顺序为所述第二矩阵的第四列-第三列-第二列-第五列-第一列；
    或者，所述第一顺序为所述第二矩阵的第四列-第二列-第三列-第五列-第一列。
  13. 一种解交织与解调方法，其特征在于，所述方法包括：
    接收调制符号；
    对所述调制符号进行解调，得到待解交织的对数似然比LLR序列；
    对所述待解交织的LLR序列进行第一解交织，得到解交织后的第一LLR序列；所述第一解交织包括：按照从左到右的顺序逐行写入第二矩阵，并按照从左到右的顺序从所述第二矩阵逐列读出；所述第二矩阵的列数为调制阶数M，所述M大于或等于3；所述逐行写入的第一个比特为最高有效比特MSB，第M个比特为最低有效比特LSB；
    根据所述解交织后的第一LLR序列确定信息比特；
    其中，所述解调使用的星座图包括2 M个星座点，所述2 M个星座点分布在N个圆环上，所述N个圆环中的至少一个圆环上的星座点满足格雷映射的原则，N为正整数。
  14. 根据权利要求13所述的方法，其特征在于，所述M等于3时，所述8个星座点均匀分布在一个圆环上；
    第一星座点对应的相位为π/4或π/8，所述第一星座点对应的比特为000；以所述第一星座点为基准，按照顺时针方向，剩余7个星座点对应的比特分别为：010、011、111、110、 100、101、001，或者，分别为：100、101、111、110、010、011、001。
  15. 根据权利要求13或14所述的方法，其特征在于，所述M等于4时，所述16个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分布在第二圆环上，所述第一圆环和所述第二圆环为同心环；所述第一圆环上的第一星座点和所述第二圆环上的第二星座点对应的相位为π/4；
    其中：
    所述第一星座点对应的比特为0011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011；
    所述第二星座点对应的比特为0000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：0001、0101、0100、0110、1110、1100、1101、1001、1000、1010、0010；
    或者，
    所述第一星座点对应的比特为0011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：0111、1111、1011；
    所述第二星座点对应的比特为0000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：0010、0110、0100、0101、1101、1100、1110、1010、1000、1001、0001；
    或者，
    所述第一星座点对应的比特为0011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111；
    所述第二星座点对应的比特为0000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：0001、1001、1000、1010、1110、1100、1101、0101、0100、0110、0010；
    或者，
    所述第一星座点对应的比特为0011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：1011、1111、0111；
    所述第二星座点对应的比特为0000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：0010、1010、1000、1001、1101、1100、1110、0110、0100、0101、0001。
  16. 根据权利要求13-15中任一项所述的方法，其特征在于，所述M等于5时，所述32个星座点中的4个星座点均匀分布在第一圆环上，另外12个星座点均匀分布在第二圆环上，剩余16个星座点均匀分布在第三圆环上，所述第一圆环、所述第二圆环、和所述第三圆环为同心环；所述第一圆环上的第一星座点、所述第二圆环上的第二星座点、和所述第三圆环上的第三星座点对应的相位为π/4；
    其中：
    所述第一星座点对应的比特为00011，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01011；
    所述第二星座点对应的比特为00000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：00001、00101、00100、00110、01110、01100、01101、01001、01000、01010、00010；
    所述第三星座点对应的比特为10011，以所述第三星座点为基准，按照顺时针方向，所 述第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10101、10100、10111、10110、11110、11111、11100、11101、11001、11000、11011、11010、10010；
    或者，
    所述第一星座点对应的比特为00101，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：00111、01111、01101；
    所述第二星座点对应的比特为00000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：00001、00011、00010、00110、01110、01010、01011、01001、01000、01100、00100；
    所述第三星座点对应的比特为10101，以所述第三星座点为基准，按照顺时针方向，所述第三圆环上剩余的15个星座点对应的比特分别为：10000、10001、10011、10010、10111、10110、11110、11111、11010、11011、11001、11000、11101、11100、10100；
    或者，
    所述第一星座点对应的比特为10010，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11010；
    所述第二星座点对应的比特为00000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：10000、10100、00100、00110、01110、01100、11100、11000、01000、01010、00010；
    所述第三星座点对应的比特为10011，以所述第三星座点为基准，按照顺时针方向，所述第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10101、00101、10111、00111、01111、11111、01101、11101、11001、01001、11011、01011、00011；
    或者，
    所述第一星座点对应的比特为10100，以所述第一星座点为基准，按照顺时针方向，所述第一圆环上的剩余3个星座点对应的比特分别为：10110、11110、11100；
    所述第二星座点对应的比特为00000，以所述第二星座点为基准，按照顺时针方向，所述第二圆环上的剩余11个星座点对应的比特分别为：10000、10010、00010、00110、01110、01010、11010、11000、01000、01100、00100；
    所述第三星座点对应的比特为10101，以所述第三星座点为基准，按照顺时针方向，所述第三圆环上剩余的15个星座点对应的比特分别为：00001、10001、10011、00011、10111、00111、01111、11111、01011、11011、11001、01001、11101、01101、00101。
  17. 根据权利要求10-16任一项所述的方法，其特征在于，所述根据所述解交织后的第一LLR序列确定信息比特，包括：
    对所述解交织后的第一LLR序列进行译码，得到所述信息比特。
  18. 根据权利要求10-16任一项所述的方法，其特征在于，所述根据所述解交织后的第一LLR序列确定信息比特，包括：
    对所述解交织后的第一LLR序列进行第二解交织，得到解交织后的第二LLR序列；
    对所述解交织后的第二LLR序列进行译码，得到所述信息比特。
  19. 根据权利要求18所述的方法，其特征在于，所述第二解交织包括：对所述第一LLR序列的后N-X个元素按照预设顺序进行解交织，所述N为所述信息比特的个数，所述X大于或等于系统比特的个数。
  20. 一种通信装置，其特征在于，包括用于执行如权利要求1-9中任一项所述方法的模块，或者，包括用于执行如权利要求10-19中任一项所述方法的模块。
  21. 一种通信装置，其特征在于，所述通信装置包括：处理器；
    所述处理器，用于执行存储器中存储的计算机程序或指令，以使所述通信装置执行如权利要求1-9中任一项所述的方法，或者，以使所述通信装置执行如权利要求10-19中任一项所述的方法。
  22. 一种通信装置，其特征在于，所述通信装置包括：接口电路和逻辑电路；
    所述接口电路，用于输入和/或输出信息；
    所述逻辑电路用于执行权利要求1-9中任一项所述的方法，生成所述接口电路输出的信息；或者执行权利要求10-19中任一项所述的方法，对所述接口电路输入的信息进行处理。
  23. 一种计算机可读存储介质，其特征在于，用于存储指令，当所述指令被执行时，如权利要求1-9中任一项所述的方法被实现，或者，如权利要求10-19中任一项所述的方法被实现。
  24. 一种计算机程序产品，其特征在于，当所述计算机程序产品在通信装置上运行时，如权利要求1-9中任一项所述的方法被实现，或者，如权利要求10-19中任一项所述的方法被实现。
  25. 一种通信系统，其特征在于，所述通信系统包括用于执行如权利要求1-9中任一项所述方法的通信装置，以及用于执行如权利要求10-19中任一项所述方法的通信装置。
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