WO2023123103A1 - 确定性流传输方法及设备 - Google Patents

确定性流传输方法及设备 Download PDF

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Publication number
WO2023123103A1
WO2023123103A1 PCT/CN2021/142636 CN2021142636W WO2023123103A1 WO 2023123103 A1 WO2023123103 A1 WO 2023123103A1 CN 2021142636 W CN2021142636 W CN 2021142636W WO 2023123103 A1 WO2023123103 A1 WO 2023123103A1
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Prior art keywords
time slot
scheduling
queue
data packet
periodic
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PCT/CN2021/142636
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English (en)
French (fr)
Inventor
郭道荣
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New H3C Technologies Co Ltd
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New H3C Technologies Co Ltd
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Priority to EP21969471.8A priority Critical patent/EP4336900A4/en
Priority to PCT/CN2021/142636 priority patent/WO2023123103A1/zh
Priority to CN202180004331.0A priority patent/CN116530141A/zh
Priority to JP2023574856A priority patent/JP7685077B2/ja
Priority to US18/568,346 priority patent/US12432159B2/en
Publication of WO2023123103A1 publication Critical patent/WO2023123103A1/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6235—Variable service order
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • H04L43/106—Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/28—Flow control; Congestion control in relation to timing considerations
    • H04L47/283—Flow control; Congestion control in relation to timing considerations in response to processing delays, e.g. caused by jitter or round trip time [RTT]

Definitions

  • This application relates to network communication technology, in particular to a method and device for deterministic traffic (DT: Deterministic Traffic) transmission.
  • DT Deterministic Traffic
  • Deterministic Network can provide deterministic service functions for carried services in a network domain. These deterministic business functions may include delay, packet loss rate, etc. Taking the deterministic network based on the local area network, that is, the time-sensitive network (TSN: Time Sensitive Network) as an example, in TSN, the transmission time on the entire forwarding path at the forwarding level is ensured by using Cyclic Queuing and Forwarding (CQF: Cyclic Queuing and Forwarding) Delay confirmation and so on.
  • TSN Time Sensitive Network
  • the application applies to the controller for deterministic transmission requirements. After calculation, the controller finds that there are sufficient transmission resources, and then allocates a transmission path for the application, and at the same time sends the information of the path to the network node of the application.
  • the network node receives the data that needs to be forwarded. After the data packet is packetized, the information of each node in the path is added to the packet, including the node ID of the node in the path, the sending interface of the node, and the cycle to be sent is specified in the node.
  • the forwarding layer of the node takes out the corresponding interface and cycle information, and stores the data packet into the cycle-mapped queue. Nodes transmit to each queue of CSQF in a certain cycle cycle, one queue per cycle.
  • a service flow with deterministic service functions such as delay and packet loss rate transmitted in a deterministic network is called a deterministic flow.
  • deterministic flow For other service flows other than deterministic flows, combined with existing forwarding devices such as software forwarding devices or hardware forwarding devices based on switching chips or NPs, etc., according to the best-effort forwarding method, other service flows that are different from deterministic flows can be forwarded. Traffic flows are called best effort flows.
  • the present application provides a deterministic stream transmission method and device to absorb intra-node jitter in the process of deterministic stream scheduling.
  • An embodiment of the present application provides a deterministic stream transmission method, the method is applied to a network node, and the method includes:
  • the target time slot number query the time slot scheduling cycle mapping table of the outgoing interface of the data packet, and determine the target cycle scheduling queue corresponding to the target time slot number; wherein, the time slot scheduling cycle mapping table is based on the Intra-node jitter determination of the network node described above is used to record the mapping relationship between the time slot number and the queue number of the periodic scheduling queue;
  • the embodiment of the present application also provides an electronic device.
  • the electronic device includes: a processor and a machine-readable storage medium; the machine-readable storage medium stores machine-executable instructions that can be executed by the processor; the processor is configured to execute the machine-executable instructions to achieve the above Steps of the disclosed method.
  • this embodiment determines the mapping relationship between the time slot number and the queue number of the periodic scheduling queue according to the jitter within the node of the network node to construct a time slot scheduling cycle mapping table, which effectively absorbs the deterministic flow scheduling Intra-node jitter in the process.
  • FIG. 1 is a flowchart of a deterministic stream transmission method provided in an embodiment of the present application
  • Figure 2 is a schematic diagram of the arrival time of the data packet and the enqueuing cycle of User1;
  • Figure 3 is a schematic diagram of the periodic queue being scheduled when the data packet of User1 arrives;
  • FIG. 4 is a schematic diagram of an implementation process for determining a target time slot number corresponding to a data packet arrival time provided by an embodiment of the present application
  • FIG. 5 is a schematic diagram of an implementation process for determining the queue number of the periodic scheduling queue corresponding to the time slot number provided by the embodiment of the present application;
  • FIG. 6 is a schematic diagram of an implementation flow for determining a scheduling offset provided by an embodiment of the present application.
  • Figure 7 is a schematic diagram of a calendar schedule
  • FIG. 8 is a schematic diagram of the distribution of time slots for deterministic service contracting
  • Fig. 9 is a schematic diagram of a time slot update table
  • FIG. 10 is a schematic flowchart of a deterministic stream transmission method provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of an intra-node delay decomposition of a forwarding model of a deterministic flow data packet by an edge node in the CSQF domain provided by an embodiment of the present application;
  • Fig. 12 is a schematic diagram of the forwarding model of the distributed device Switch Process provided by the embodiment of the present application.
  • FIG. 13 is a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present application.
  • FIG. 1 is a flowchart of a deterministic stream transmission method provided by an embodiment of the present application. This process is applied to network nodes.
  • the embodiment of the present application does not specifically limit the specific structural form of the network node.
  • it can be a low-end router, etc., or it can be a high-end router that has high performance requirements and supports more CPU cores, and a network processor-based (NP: Network Process) forwarding high-end, core routers, etc.
  • NP Network Process
  • the process may include the following steps:
  • Step 101 when it is determined that the received data packet belongs to a deterministic flow, and the data packet does not carry CSQF domain scheduling information, determine the target time slot number corresponding to the arrival time of the data packet.
  • the deterministic stream attribute is not fixed, and the current specification does not provide specific specifications, but is set according to actual needs, such as setting the value of fields such as Differentiated Services Code Point (DSCP: Differentiated Services Code Point) to represent deterministic sexual properties.
  • DSCP Differentiated Services Code Point
  • This embodiment does not specifically limit the deterministic flow attribute.
  • the deterministic flow attribute is set and applied to step 101, it can be identified whether the current data packet carries the deterministic flow attribute, and if so, it is identified that the current data packet belongs to the deterministic flow.
  • the current node is an edge node of the CSQF domain depending on whether the data packet carries CSQF domain scheduling information.
  • the CSQF domain scheduling information may include information indicating which periodic scheduling queue of the outbound interface of the data packet the data packet needs to be scheduled to.
  • the node when it is determined that the received data packet belongs to the deterministic flow and the data packet does not carry CSQF domain scheduling information, the node may be determined as the edge node of the CSQF domain.
  • the jitter of end-to-end data transmission in order to realize the deterministic flow is within 2 scheduling cycles (which can be recorded as 2T)
  • the deterministic flow of a specific user is always at a specific node. Forwarding is performed at a specified cycle, but different services have different packet sending cycles.
  • the Internet of Vehicles is 150us cycle
  • industrial control is 250us cycle.
  • the forwarding node is divided into 8 cycles (Cycle 0 ⁇ 7) and time slices with a duration of T (T length is 10us) for periodic scheduling and forwarding, correspondingly implementing 8 periodic scheduling queues Queue 0 ⁇ 7.
  • T length is 10us
  • a specific user always forwards in a specified cycle at a specific node, as shown in Figure 2, assuming that User1 is fixed at the edge node of the CSQF domain to forward at Cycle0, that is, enter Queue0. At the same time, it is assumed that when the first packet arrives, it is the Cycle7 of the last big cycle that is being scheduled.
  • the first packet enters Queue0 just right, that is, when the first packet arrives, the queue corresponding to the last round of Cycle7 is being scheduled, and Queue0 will be scheduled after one cycle; after 150us, the second packet of User1 is received, and this The queue corresponding to Cycle6 is being scheduled, but because it is specified to enter queue 0, compared to the first packet, the second packet introduces scheduling jitter for one cycle; similarly, after another 150us, when the third packet arrives, it is scheduling Cycle5 exactly , thus introducing 2 periods of jitter, .... As shown in Figure 3, when packets 1 to 8 arrive, the corresponding relationship between the cycle numbers being scheduled, according to these relationships, it can be seen that there is a maximum of 7 cycles of jitter.
  • the analysis of the delay jitter within the network node can be determined based on the forwarding model of the deterministic flow data packet by the edge node of the CSQF domain. This part will be illustrated below with reference to FIG.
  • the deterministic flow data packets received by the edge nodes of the CSQF domain are no longer in a specific node according to the deterministic flow of a specific user, but always in the specified Scheduling is carried out in the way of periodic forwarding, but the corresponding time slot number (which can be called the target time slot number) can be determined according to the arrival time of the deterministic flow data packet, and the period of the deterministic flow data packet can be determined based on the time slot number dispatch queue.
  • how the network node determines the target time slot number corresponding to the arrival time of the data packet may refer to the implementation process described in the example shown in FIG. 4 below, which will not be repeated here.
  • the situation that the network node receives the deterministic flow data packet as the edge node of the CSQF domain may include:
  • the network node is the edge node connected to the non-deterministic network domain in the CSQF domain, and receives the data packet of the deterministic flow;
  • the network node is an edge node connected to a non-wide-area deterministic network (such as TSN) in the wide-area deterministic network, and receives a data packet of a deterministic flow;
  • a non-wide-area deterministic network such as TSN
  • the network node forwards the relay node for the ultra-long path CSQF of the wide-area deterministic network, and receives the data packet of the deterministic flow.
  • the next-hop node can be called the wide-area deterministic network ultra-long path CSQF forwarding relay node.
  • the first forwarding node outside the coverage of the label number of the ultra-long path CSQF forwarding relay node in the wide-area deterministic network can also be used as a new ultra-long-path CSQF forwarding relay node in the wide-area deterministic network.
  • Step 102 according to the target time slot number, query the time slot scheduling cycle mapping table of the outgoing interface of the data packet, and determine the target cycle scheduling queue corresponding to the target time slot number.
  • a time slot scheduling cycle mapping table can be implemented in the input interface processing unit, and the time slot scheduling cycle mapping table can be used to record the queue of the time slot number and the cycle scheduling queue
  • the mapping relationship between the time slot number and the queue number of the periodic scheduling queue can be considered during the establishment of the mapping relationship between the time slot number and the queue number of the periodic scheduling queue. Inner jitter.
  • the establishment of the mapping relationship between the time slot number and the queue number of the periodic scheduling queue that is, the construction process of the slot scheduling periodic mapping table, can refer to the implementation process described in FIG. 5 below as an example, and will not be repeated here.
  • the time slot scheduling period mapping table of the outgoing interface of the data packet can be queried to determine the queue number of the periodical scheduling queue mapped to the target time slot number, and the period The periodic scheduling queue identified by the queue number of the scheduling queue is determined as the periodic scheduling queue corresponding to the target time slot number (may be referred to as the target periodic scheduling queue).
  • Step 103 scheduling the data packet to the target periodic scheduling queue of the outgoing interface of the data packet.
  • the data packet may be scheduled to the target periodic scheduling queue of the outgoing interface of the data packet.
  • the method shown in Figure 1 determines the mapping relationship between the time slot number and the queue number of the periodic scheduling queue according to the jitter in the node of the network node to construct the time slot scheduling periodic mapping table, so that the network node determines that the received data packet belongs to In the case of a deterministic flow, and the data packet does not carry CSQF domain scheduling information, according to the target time slot number corresponding to the arrival time of the data packet, query the time slot scheduling period mapping table of the outgoing interface of the data packet to determine the
  • the target periodic scheduling queue corresponding to the arrival time of the data packet that is, the periodic scheduling queue of the data packet is determined according to the arrival time of the deterministic flow data packet, instead of being at a specific node according to the deterministic flow of a specific user, it is always at a specified period Scheduling is carried out in the way of forwarding, which effectively absorbs the intra-node jitter in the process of deterministic flow scheduling.
  • FIG. 4 is a schematic diagram of an implementation flow of determining a target time slot number corresponding to a data packet arrival time provided by an embodiment of the present application.
  • the process may include the following steps:
  • Step 401 acquire the receiving time stamp of the data packet.
  • the receiving timestamp of the data packet can be the receiving timestamp stamped by the hardware on the received data packet.
  • Some hardware does not support the scenario of timestamping, and the system clock of the node can also be obtained at the forwarding processing entry, as Received timestamp of the packet.
  • Step 402 converting the receiving time stamp of the data packet into the number of time slots.
  • Step 403 Determine the target time slot number corresponding to the arrival time of the data packet according to the number of time slots and the number of time slots in the time slot scheduling cycle mapping table.
  • the target time slot number corresponding to the arrival time of the data packet can be obtained by taking the remainder of the number of time slots obtained by converting the received time stamp of the data packet from the number of time slots in the time slot scheduling cycle mapping table.
  • TimeSlotNum_Remainder (TimeSlotNum&0xFF), or (TimeSlotNum%256)
  • TimeSlotNum_Remainder is the target time slot number corresponding to the arrival time of the data packet.
  • the time slot scheduling periodic mapping table can be queried based on the keyword TimeSlotNum_Remainder to obtain the queue number of the corresponding periodic scheduling queue.
  • the queue number of the periodic scheduling queue is the periodic scheduling that the data packet needs to enter in the network node The queue number of the queue.
  • mapping relationship between the time slot number recorded in the time slot scheduling cycle mapping table of the outgoing interface and the queue number of the periodic scheduling queue can be determined in the following manner:
  • the scheduling offset is determined according to the intra-node jitter of the network node.
  • the time slot scheduling cycle mapping table may also be called a calendar scheduling table (calendar).
  • the calendar schedule may include the following information and characteristics:
  • Time slot number (Calendar_Slot);
  • the queue number (Calendar_Que_No) of the periodic scheduling queue mapped to the time slot number.
  • the number of time slots in the calendar scheduling table is an integer multiple of the number of periodic scheduling queues. For example, when the number of periodic scheduling queues is 8, the number of time slots in the calendar scheduling table is 8N (N is a positive integer), for example, the number of time slots in the calendar scheduling table is 256.
  • FIG. 5 is a schematic diagram of an implementation flow of determining the queue number of the periodic scheduling queue corresponding to the time slot number provided by the embodiment of the present application.
  • the process can include:
  • Step 501 for any time slot number, take the remainder of the sum of the time slot number and the scheduling offset by the number of periodic scheduling queues on the outbound interface, to obtain a first remainder result.
  • Step 502 Determine the first remainder result as the queue number of the periodic scheduling queue corresponding to the time slot number.
  • the periodic scheduling queue corresponding to the time slot number may be determined according to the sum of the time slot number and the scheduling offset. Since the sum of the time slot number and the scheduling offset may be greater than the number of periodic scheduling queues, the sum of the time slot number and the scheduling offset can be used to calculate the remainder of the number of periodic scheduling queues, The remainder result (that is, the first remainder result) is determined as the queue number of the periodic scheduling queue corresponding to the time slot number.
  • the queue number Calendar_Que_No of the periodic scheduling queue corresponding to the time slot number can be determined in the following manner:
  • Calendar_Que_No (Calendar_Slot+Schedule_Offset) % Que_Num.
  • Calendar_Slot is the time slot number
  • Schedule_Offset is the scheduling offset
  • Que_Num is the number of periodic scheduling queues.
  • the scheduling offset can be used to represent the period corresponding to the period corresponding to the data packet received by the input forwarding processing unit in time slot 0 and entering the CSQF periodic scheduling queue of the current node relative to the first period of the CSQF of the current node
  • the determination method of the offset refer to the implementation process illustrated in FIG. 6 below, which will not be repeated here.
  • FIG. 6 is a schematic diagram of an implementation flow of determining a scheduling offset provided by an embodiment of the present application.
  • the process of determining the scheduling offset may include:
  • Step 601 Determine the periodic scheduling queue of the output interface that the output interface processing unit is scheduling when the test message arrives at the output interface processing unit according to the receiving time stamp of the test message at the input forwarding processing unit.
  • the periodic measurement and calibration method can be used to determine the periodic scheduling queue of the output interface that the output interface processing unit is scheduling when the test message is sent from the input forwarding processing unit and arrives at the output interface processing unit.
  • Step 602 Determine the optimal periodic scheduling queue of the test message according to the periodic scheduling queue of the outgoing interface being scheduled by the output interface processing unit and the intra-node jitter of the network node.
  • the next periodic scheduling queue of the periodic scheduling queue of the outgoing interface being scheduled by the output interface processing unit is a test message Best for entering periodic dispatch queues.
  • test message is sent from the input forwarding processing unit, there will be a certain delay jitter in the process of dispatching the test message into the queue by the output interface processing unit (that is, the jitter in the node of the above-mentioned network nodes), therefore, it can be based on The delay jitter offsets the periodic scheduling queue that the test message needs to enter, so as to obtain the optimal periodic scheduling queue of the test message.
  • the periodic scheduling queue of the output interface being scheduled by the output interface processing unit is queue 2
  • the above-mentioned delay jitter is 30us
  • one time slot is 10us
  • Step 603 Determine the scheduling offset according to the optimal periodic scheduling queue, the number of periodic scheduling queues of the outbound interface, and the time slot number corresponding to the receiving time stamp of the test message at the input forwarding processing unit.
  • the optimal scheduling queue corresponding to the time slot number corresponding to the receiving time stamp of the test message input to the forwarding processing unit can be determined, that is, the corresponding relationship between a time slot number and the optimal scheduling queue can be obtained.
  • the optimal scheduling queue corresponding to the 0 time slot can be determined.
  • the queue number of the optimal scheduling queue is Can be used as the scheduling offset above.
  • the test message (also referred to as the test data packet) can be constructed by the CPU, and transparently transmitted to the input forwarding processing unit through the internal processing channel, and the input forwarding processing unit can According to the system time of receiving the test message, the test message is received with a time stamp, and when the test message arrives at the output interface processing unit, the output interface processing unit is scheduling the output of the test message according to the received time stamp.
  • the periodic scheduling queue of the interface when the scheduling offset is determined.
  • the test message can also be constructed by the input forwarding processing unit.
  • the input forwarding processing unit can construct the test message when receiving the test command.
  • the input forwarding processing unit can construct the test message according to the system
  • the time is the receiving time stamp of the test message, and the periodic scheduling queue of the outgoing interface of the test message that the output interface processing unit is scheduling when the test message arrives at the output interface processing unit is determined according to the receiving time stamp.
  • the input forwarding processing unit receives the test message, or, after constructing the test message, it can be processed according to the same processing method as the deterministic flow data packet arrives at the input forwarding processing unit of the edge node of the CSQF domain
  • the test data packet is forwarded by the method, so as to realize the simulation of the forwarding process of the deterministic flow data packet by the edge node of the CSQF domain.
  • the input interface processing unit stamps the receiving time stamp on the data packet, and determines the corresponding time slot number (i.e. the above target time slot number), and perform the mapping of the periodic scheduling queue according to the above method, but because the time delay for the data packet to reach the input forwarding processing unit through the input interface processing unit is usually very small, and the jitter is also very small Therefore, the scheduling offset obtained by testing in the above manner can more accurately absorb the jitter in the node.
  • the receiving time stamp of the test message it can be subtracted from A fixed time (corresponding to the time delay for the message to arrive at the input forwarding processing unit through the input interface processing unit) to obtain the receiving time stamp of the test message.
  • the scheduling offset is determined according to the optimal periodic scheduling queue, the number of periodic scheduling queues of the outbound interface, and the time slot number corresponding to the receiving time stamp of the test message at the input forwarding processing unit, including:
  • the third remainder result is determined as the scheduling offset.
  • time slot number corresponding to the receiving time stamp of the test message at the input forwarding processing unit is the time slot between the time slot number corresponding to the receiving time stamp of the test message at the input forwarding processing unit and time slot 0
  • the time slot difference should be consistent with the difference between the queue number of the optimal periodic scheduling queue of the test message and the queue number of the optimal periodic scheduling queue of time slot 0.
  • the queue number of the optimal periodic scheduling queue of the test message corresponds to n time slots
  • the queue number of the optimal periodic scheduling queue of the test message is RQ
  • the queue number of the optimal periodic scheduling queue corresponding to the 0 time slot The number should be the periodic scheduling queue after the periodic scheduling queue RQ rolls back n cycles.
  • n may be greater than the number of cycles, therefore, the number of periodic scheduling queues of the outbound interface can be subtracted by n to obtain the remainder result (that is, the second remainder result), and the optimal The periodic scheduling queue RQ rolls back the second remainder result for a period.
  • RQ may be smaller than the second remainder result
  • the obtained queue number of the periodic scheduling queue is subtracted from the number of the periodic scheduling queues of the outbound interface, and the subtracted result (that is, the third subtracted result) is the scheduling offset.
  • scheduling offset Schedule_Offset can be determined through the following strategy:
  • Schedule_Offset (RQ+Que_Num-(n%Que_Num))%Que_Num
  • the time slot number 43 corresponding to the sending time stamp of the test message is mapped to the periodic scheduling queue 6 . Since the time slot difference between time slot number 43 and time slot 0 is 43, the queue number of the optimal periodic scheduling queue corresponding to time slot 0, that is, the value of Schedule_Offset can be calculated by the following strategy (assuming that the output of the test message The number of periodic scheduling queues for the interface is 15):
  • a time slot update table is needed to adjust the time slot number corresponding to the arrival time of each deterministic flow.
  • the number of periodic scheduling queues is 10
  • the number of time slots in the time slot scheduling periodic table is 100
  • the period of user User1 sending data packets in Fig. 8 is 730us (ie 73 scheduling cycles)
  • the time slot number corresponding to the arrival time of the first data packet of the user is 53
  • the time slot number corresponding to the arrival time of the second data packet is 26.
  • time slot table in Figure 9 can be Updating, updating the time slot number of the data packet whose arrival time corresponds to the time slot number 72 and 74 to 73, that is, scheduling the data packet to the periodic scheduling queue corresponding to the 73 time slot.
  • Calendar_Slot is the time slot number calculated according to the received timestamp of the data packet; Calendar_Slot_Replace is the updated time slot number.
  • the edge nodes connected to the non-deterministic network domain in the CSQF domain before the deterministic flow reaches the node, there may be situations that need to cross the non-deterministic network domain, resulting in the time slot of the same deterministic flow reaching the node. There are some jitters. In order to eliminate these jitters, the shaping of the input deterministic flow is realized. For the data packets of the same deterministic flow, when the time slot number corresponding to the arrival time of the node is several adjacent time slot numbers , which can be updated to map to the same slot number.
  • the time slot numbers corresponding to the arrival time of the deterministic flow include 0, 1 and 2, and all of them can be mapped to the time slot number 2 to implement shaping of the deterministic flow.
  • the flow of the deterministic stream transmission method may be as shown in FIG. 10 .
  • the process may include the following steps:
  • Step 1001 if it is determined that the received data packet belongs to a deterministic flow and the data packet does not carry CSQF domain scheduling information, determine the target time slot number corresponding to the arrival time of the data packet.
  • Step 1002 query the time slot update table of the service flow to which the data packet belongs based on the target time slot number, and obtain the updated time slot number.
  • Step 1003 query the time slot scheduling cycle mapping table of the outbound interface of the data packet, and determine the target cycle scheduling queue corresponding to the time slot where the data packet arrives.
  • Step 1004 schedule the data packet to the target periodic scheduling queue of the outgoing interface of the data packet.
  • the received deterministic The flows are all from the deterministic domain, and there is usually no need to shape the deterministic flows, and there will be no situation where some time slots are used very little while other time slots are used too much; in addition, for wide area In the deterministic network, the edge nodes connected to the non-wide-area deterministic network (such as TSN), or the ultra-long-path CSQF forwarding relay nodes in the wide-area deterministic network usually have a large number of deterministic flows that need to be processed.
  • the edge node connected to the non-deterministic network domain in the CSQF domain may issue a time slot update table for each deterministic flow.
  • FIG. 11 is a schematic diagram of an intra-node delay decomposition of a forwarding model of a deterministic flow data packet by an edge node in a CSQF domain provided by an embodiment of the present application.
  • the forwarding process of deterministic flow packets in the edge nodes of the CSQF domain includes:
  • Input process distribution process, exchange process, mapping process, periodic scheduling process, and output process. in:
  • Input Process used for input timestamp anchoring.
  • the input process is mainly a function of the hardware controller, which realizes the anchoring of the input timestamp.
  • Distribution process used for cache distribution.
  • the distribution process may be implemented by a hardware controller, or by software.
  • Switch Process used for intra-node forwarding related processing.
  • the switching process may include software processing, and the microcode of the NP cooperates with the hardware unit to implement a pipeline.
  • the switching process may also include the switching process of input interface board -> network board -> output interface board.
  • FIG. 12 please refer to the implementation process described in the example shown in FIG. 12 below, which will not be repeated here.
  • Mapping process used to map deterministic flow packets to periodic scheduling queues according to the period.
  • mapping process requires the participation of software (or NP microcode) or Field Programmable Gate Array (FPGA: Field Programmable Gate Array), which must have a programmable capability to provide implementation flexibility.
  • software or NP microcode
  • FPGA Field Programmable Gate Array
  • Scheduled by Cycle It is used to schedule the periodic scheduling queue according to the scheduling cycle, and send the data in the sending cycle queue to the highest priority hardware queue reserved for configuration.
  • the output process can be configured to reserve the highest priority hardware queue as the hardware queue for sending deterministic traffic, and add the output time stamp.
  • the Switch Process processing delay is uncertain, involving queuing within the node, and may vary as much as 20us to 50us.
  • the Switch Process processing delay may include an input forwarding processing unit (taking Ingress NP as an example in Fig.
  • the processing delay of the switching unit (Fabric is taken as an example in Figure 12) and the output forwarding processing unit (Egress NP is taken as an example in Figure 12) may reach more than 20us after the jitter in the middle is superimposed.
  • the two stages of Mapping and Schedule by Cycle are all implemented by the output interface processing unit (take FPGA2 as an example in Figure 12), and the message enters the input interface processing unit (taken by FPGA1 as an example) to the output interface processing unit for Mapping processing, there is a large uncertain delay jitter (that is, the above-mentioned intra-node jitter).
  • FPGA1 and FPGA2 may be different FPGAs, and may also be the same FPGA (for example, for a traffic loopback or a scenario where the same FPGA implements multiple external ports).
  • the scheduling offset can be determined through testing in the above manner.
  • the scheduling offset when the scheduling offset is determined, it can be determined that when the test message arrives at FPGA2, the test message that FPGA2 is scheduling The periodic scheduling queue of the outbound interface of the text, and according to the periodic scheduling queue, and the delay within the node, such as 30us, determine the optimal periodic scheduling queue of the test message, according to the queue number of the optimal periodic scheduling queue, and, test The time slot number corresponding to the receiving time stamp of the message in the Ingress NP, according to the above method, determines the scheduling offset.
  • the electronic device includes a processor and a machine-readable storage medium; the machine-readable storage medium stores information that can be read by the processor.
  • Executed machine-executable instructions; the processor is configured to execute the machine-executable instructions to implement the methods disclosed in the above examples of the present application.
  • the processor executes machine-executable instructions to realize: when it is determined that the received data packet belongs to a deterministic flow, and the data packet does not carry CSQF domain scheduling information, determine that the arrival time of the data packet corresponds to The target time slot number; according to the target time slot number, query the time slot scheduling period mapping table of the outgoing interface of the data packet, and determine the target period scheduling queue corresponding to the target time slot number; wherein, the time slot The scheduling period mapping table is determined according to the jitter within the node of the network node, and is used to record the mapping relationship between the time slot number and the queue number of the periodic scheduling queue; schedule the data packet to the target periodic scheduling of the outgoing interface of the data packet queue.
  • the processor executes machine-executable instructions to realize: obtaining the receiving timestamp of the data packet; converting the receiving timestamp of the data packet into the number of time slots; according to the number of time slots, and the The number of time slots in the time slot scheduling cycle mapping table is used to determine the target time slot number corresponding to the arrival time of the data packet.
  • the processor executes machine-executable instructions to realize: for any outbound interface that supports queuing and forwarding CSQF at a specified period, determine the time slot number recorded in the time slot scheduling period mapping table of the outbound interface in the following manner Mapping relationship with the queue number of the periodic scheduling queue: For any time slot number, according to the time slot number, scheduling offset, and the number of periodic scheduling queues of the outbound interface, determine the corresponding periodic scheduling queue of the time slot number A queue number; wherein, the scheduling offset is determined according to the intra-node jitter of the network node.
  • the processor executes machine-executable instructions to realize: taking the remainder of the sum of the time slot number and the scheduling offset from the number of periodic scheduling queues of the outbound interface to obtain the first remainder Result: determining the first remainder result as the queue number of the periodic scheduling queue corresponding to the time slot number.
  • the processor executes machine-executable instructions to: determine the scheduling offset in the following manner: according to the receiving time stamp of the test message at the input forwarding processing unit, determine that the test message arrives at the output interface processing unit , the periodic scheduling queue of the outgoing interface that the output interface processing unit is scheduling; according to the periodic scheduling queue of the outgoing interface that the output interface processing unit is scheduling, and the internal jitter of the network node, determine the number of the test message
  • the optimal periodic scheduling queue according to the optimal periodic scheduling queue, the quantity of the periodic scheduling queue of the outgoing interface, and the time slot number corresponding to the receiving time stamp of the test message at the input forwarding processing unit, determine the scheduling Offset.
  • the processor executes machine-executable instructions to implement: take the remainder of the number of the periodic scheduling queue from the time slot number corresponding to the receiving time stamp of the test message input to the forwarding processing unit, and obtain the second Take the remainder result; sum the queue number of the optimal periodic scheduling queue and the quantity of the periodic scheduling queue of the outgoing interface to obtain a summation result; calculate the difference between the summation result and the second remainder result
  • the value is modulo the number of periodic scheduling queues of the outbound interface to obtain a third modulo result; and the third modulo result is determined as the scheduling offset.
  • the processor further executes machine-executable instructions to realize: according to the target time slot number, query the time slot update table of the service flow to which the data packet belongs to obtain an updated time slot number; time slot number, query the time slot scheduling cycle mapping table of the outbound interface of the data packet, and determine the target cycle scheduling queue corresponding to the time slot where the data packet arrives.
  • the forwarding process of the deterministic flow data packet in the edge node of the CSQF domain includes:
  • Input process distribution process, exchange process, mapping process, periodic scheduling process, and output process;
  • the input process is used for input timestamp anchoring
  • the distribution process is used for cache distribution
  • the exchange process is used to perform intra-node forwarding related processing
  • mapping process is used to map the deterministic flow data packet to the periodic scheduling queue according to the period
  • the periodic scheduling process is used to schedule the periodic scheduling queue according to the scheduling cycle, and send the data in the sending cycle queue to the configuration reserved highest priority hardware queue;
  • the output process is used for hardware send processing.
  • the intra-node jitter of the network node includes processing delay jitter of the switching process.
  • the embodiment of the present application also provides a non-transitory machine-readable storage medium storing computer-executable instructions, such as the machine-readable storage medium in FIG. 13 , the computer-executable instructions can be obtained by The processor 801 in the electronic device shown in FIG. 13 executes to implement the method for analyzing data streams described above.
  • the above-mentioned machine-readable storage medium may be any electronic, magnetic, optical or other physical storage device, which may contain or store information, such as executable instructions, data, and so on.
  • the machine-readable storage medium can be: RAM (Radom Access Memory, random access memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as CD, DVD, etc.), or similar storage media, or a combination of them.
  • a typical implementing device is a computer, which may take the form of a personal computer, laptop computer, cellular phone, camera phone, smart phone, personal digital assistant, media player, navigation device, e-mail device, game control device, etc. desktops, tablets, wearables, or any combination of these.
  • embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • these computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means,
  • the instruction means implements the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operational steps are performed on the computer or other programmable equipment to produce computer-implemented processing, so that the information executed on the computer or other programmable equipment
  • the instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

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Abstract

本申请提供了确定性流传输方法及设备。该方法包括：在确定接收到的数据包属于确定性流，且该数据包中未携带CSQF域调度信息的情况下，确定所述数据包的到达时间对应的目标时隙号；依据所述目标时隙号，查询所述数据包的出接口的时隙调度周期映射表，确定所述目标时隙号对应的目标周期调度队列；其中，所述时隙调度周期映射表依据所述网络节点的节点内抖动确定，用于记录时隙号与周期调度队列的队列号的映射关系；将所述数据包调度到所述数据包的出接口的目标周期调度队列。通过本申请实施例，可以有效吸收确定性流调度过程中的节点内抖动。

Description

确定性流传输方法及设备 技术领域
本申请涉及网络通信技术，特别涉及确定性流(DT：Deterministic Traffic)传输方法及设备。
背景技术
确定性网络(DetNet：Deterministic Network)可以在一个网络域内为承载的业务提供确定性业务功能。这些确定性业务功能可包括时延、丢包率等。以基于局域网实现的确定性网络即时间敏感型网络(TSN：Time Sensitive Network)为例，在TSN中通过采用周期排队转发(CQF：Cyclic Queuing and Forwarding)确保转发层面上整个转发路径上的传输时延确定等。
为了实现广域网的确定性传输，业界基于CQF提出了基于分段路由实现指定周期排队转发(CSQF：Cycle Specified Queuing and Forwarding)。
CSQF方案中存在一个全局控制器，该控制器收集各个节点的信息，包括发送能力，接口，周期数，节点内最大抖动等。应用向控制器申请确定性传输需求，控制器经过计算后，发现有足够的传输资源，便为应用分配传输路径，同时把路径的信息下发给应用的网络节点，网络节点接收到需要转发的数据包packet后，在packet中添加路径中每个节点的信息，包括节点在路径中的节点标识，该节点的发送接口，在该节点中指定要发送的周期。数据到了某节点后，该节点的转发层取出相应的接口和周期信息，把该数据包存入周期映射的队列。节点按一定的周期循环对CSQF的各个队列进行每周期一个队列轮转地发送。
为便于描述，确定性网络中传输的具有确定性业务功能比如时延、丢包率等的业务流称为确定性流。而针对不同于确定性流的其他业务流，结合现有转发设备比如软件转发设备或者基于交换芯片或NP实现的硬件转发设备等按照尽力而为转发的方式，可将不同于确定性流的其他业务流称为尽力而为流。
发明内容
本申请提供了确定性流传输方法及设备，以吸收确定性流调度过程中的节点内抖动。
本申请实施例提供一种确定性流传输方法，该方法应用于网络节点，该方法包括：
在确定接收到的数据包属于确定性流，且该数据包中未携带CSQF调度信息的情况下，确定所述数据包的到达时间对应的目标时隙号；
依据所述目标时隙号，查询所述数据包的出接口的时隙调度周期映射表，确定所述目标时隙号对应的目标周期调度队列；其中，所述时隙调度周期映射表依据所述网络节点的节点内抖动确定，用于记录时隙号与周期调度队列的队列号的映射关系；
将所述数据包调度到所述数据包的出接口的目标周期调度队列。
本申请实施例还提供了一种电子设备。该电子设备包括：处理器和机器可读存储介质；所述机器可读存储介质存储有能够被所述处理器执行的机器可执行指令；所述处理 器用于执行机器可执行指令，以实现上述公开的方法的步骤。
由以上技术方案可以看出，本实施例通过依据网络节点的节点内抖动确定时隙号与周期调度队列的队列号的映射关系，以构建时隙调度周期映射表，有效吸收了确定性流调度过程中的节点内抖动。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为本申请实施例提供的确定性流传输方法流程图；
图2为User1的数据包到达时间与入队列周期示意图；
图3为User1的数据包到达时正在调度的周期队列示意图；
图4为本申请实施例提供的确定数据包到达时间对应的目标时隙号的实现流程示意图；
图5为本申请实施例提供的确定时隙号对应的周期调度队列的队列号的实现流程示意图；
图6为本申请实施例提供的确定调度偏移量的实现流程示意图；
图7为日历调度表的示意图；
图8为确定性业务发包时隙分布示意图；
图9为时隙更新表的示意图；
图10为本申请实施例提供的确定性流的传输方法流程示意图；
图11为本申请实施例提供的CSQF域的边缘节点对确定性流数据包的转发模型的节点内时延分解示意图；
图12为本申请实施例提供的分布式设备Switch Process的转发模型示意图；
图13为本申请实施例提供的电子设备的硬件结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
为了使本领域技术人员更好地理解本申请实施例提供的技术方案，并使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请实施例提供的技术方案进行说明。
下面结合附图对本申请实施例提供的确定性流传输方法进行描述：
参见图1，图1为本申请实施例提供的确定性流传输方法流程图。该流程应用于网络节点。本申请实施例并不具体限定该网络节点的具体结构形式，比如可为中低端路由器等，或者可为对性能要求高，支持更多CPU核的高端路由器，以及基于网络处理器(NP：Network Process)转发的高端、核心路由器等，本实施例并不具体限定，以让本申请实施例具有广泛的适用性和扩展性。
如图1所示，该流程可以包括以下步骤：
步骤101，在确定接收到的数据包属于确定性流，且该数据包中未携带CSQF域调度信息的情况下，确定该数据包的到达时间对应的目标时隙号。
在本实施例中，对于属于确定性流的数据包，其会携带确定性流属性(DetProperty：Deterministic Property)。
示例性的，确定性流属性不是固定的，目前规范也不提供具体的指定，而是根据实际需求统筹设置，比如设置差分服务代码点(DSCP：Differentiated Services Code Point)等字段的值来表征确定性流属性。本实施例并不具体限定确定性流属性。但一旦设置好确定性流属性，应用于本步骤101，则可识别当前数据包是否携带确定性流属性，若是，则识别出当前数据包属于确定性流。
在本实施例中，在确定该数据包属于确定性流的数据包的情况下，可依赖于数据包中是否携带CSQF域调度信息，确定本节点是否作为CSQF域的边缘节点。
示例性的，该CSQF域调度信息可以包括用于指示该数据包需调度到数据包的出接口的哪一个周期调度队列的信息。
在本实施例中，在确定接收到的数据包属于确定性流，且该数据包中未携带CSQF域调度信息的情况下，可以确定本节点作为CSQF域的边缘节点。
在本实施例中，考虑到传统CQSF方案中为了实现确定性流的数据端到端传输的抖动在2个调度周期(可以记为2T)以内，特定用户的确定性流在特定节点，总是以指定的周期进行转发，但不同的业务有不同的发包周期，例如，车联网是150us周期，工业控制是250us周期，当周期性确定性流的周期宽度不是调度周期大循环的整倍数的情况下，按照该方式对确定性流进行调度会引入大量抖动。
举例来说，假设用户User1以150us周期进行发包，转发节点划分为8个周期(Cycle 0～7)时长为T(T长度为10us)的时间片进行周期调度转发，对应实现8个周期调度队列Queue 0～7。按照CSQF的实现，特定用户在特定节点，总是以指定的周期进行转发，如图2所示，假设User1在CSQF域的边缘节点固定在Cycle0进行转发，即进Queue0。同时假设第1个包到达时，正在调度的是上一轮大循环的Cycle7。第一个包进Queue0刚好，即第1个包到达时，正在调度上一轮的Cycle7对应的队列，1个周期后Queue0就会被调度到；150us后，接收到User1第2个包，此时正在调度Cycle6对应的队列，但因为指定进入队列0，相对第1个包，第2个包引入了调度抖动1个周期；类似地，再过150us，第3个包到达时正在调度Cycle5正好，因此引入了2个周期抖动，……。如图3所示，包1～8到达时，正在被调度的周期号的对应关系，根据这些关系可以看出最大有7个周期的抖动。
因此，指定特定用户入固定的某一个队列方式，虽然简单，但当用户发包周期不是大循环的整倍数时，并且与调度周期没有公约数时，引入抖动为d(队列数)-1个周期。因此，即使CSQF能保证在CSQF域内端到端2个周期的抖动，但端头结点引入的抖动也不可忽略。
此外，考虑到实际场景中，在接收到确定性流的数据包的CSQF域的边缘节点内部， 从接收到数据包到进行CSQF调度转发部件之间，会存在较大的时延抖动(可能达到20us～50us)。
示例性的，网络节点的节点内时延抖动的分析可以基于CSQF域的边缘节点对确定性流数据包的转发模型来确定，该部分将在下文中结合图11举例说明，这里不再赘述。
因而，为了解决上述确定性流边缘接入引入的大抖动问题，对于CSQF域的边缘节点接收到的确定性流数据包，不再按照特定用户的确定性流在特定节点，总是以指定的周期进行转发的方式进行调度，而是可以依据确定性流数据包的到达时间，确定对应的时隙号(可以称为目标时隙号)，并基于该时隙号确定性流数据包的周期调度队列。
在本实施例中，网络节点如何确定数据包的到达时间对应的目标时隙号可以参见下文图4举例描述的实现流程，这里不再赘述。
在本实施例中，网络节点作为CSQF域的边缘节点接收到确定性流数据包的情况可以包括：
网络节点为CSQF域中连接非确定性网络域的边缘节点，并接收到确定性流的数据包；
或者，网络节点为广域确定性网络中连通非广域确定性网络(如TSN)的边缘节点，并接收到确定性流的数据包；
或者，网络节点为广域确定性网络超长路径CSQF转发中继节点，并接收到确定性流的数据包。
其中，在CSQF超长路径场景中，假设CSQF域的边缘节点支持的标签数对应的跳数对应转发路径中的某个中间节点，对于该中间节点的下一跳节点，由于其接收到的确定性流数据包中缺乏标签信息，导致其无法依据标签信息确定接收到的确定性流数据包的周期调度队列，此时，该下一跳节点可以称为广域确定性网络超长路径CSQF转发中继节点。
同理，广域确定性网络超长路径CSQF转发中继节点的标签数覆盖范围外的第一个转发节点，也可以作为新的广域确定性网络超长路径CSQF转发中继节点。
步骤102，依据目标时隙号，查询数据包的出接口的时隙调度周期映射表，确定目标时隙号对应的目标周期调度队列。
在本实施例中，针对任一支持CSQF的出接口，可以在输入接口处理单元实现一个时隙调度周期映射表，该时隙调度周期映射表可以用于记录时隙号与周期调度队列的队列号的映射关系；其中，时隙号与周期调度队列的队列号的映射关系的建立过程中，可以考虑网络节点的节点内抖动，以通过该映射关系吸收确定性流调度过程中网络节点的节点内抖动。
在本实施例中，时隙号与周期调度队列的队列号的映射关系的建立，即时隙调度周期映射表的构建流程，可以参见下文图5举例描述的实现流程，这里不再赘述。
在本实施例中，可以基于步骤101中确定的目标时隙号，查询数据包的出接口的时隙调度周期映射表，确定目标时隙号映射的周期调度队列的队列号，并将该周期调度队列的队列号标识的周期调度队列，确定为目标时隙号对应的周期调度队列(可以称为目标周期调度队列)。
步骤103，将数据包调度到数据包的出接口的目标周期调度队列。
在本实施例中，在按照步骤101～102的方式确定了目标周期调度队列的情况下，可以将该数据包调度到数据包的出接口的目标周期调度队列。
图1所示的方法通过依据网络节点的节点内抖动确定时隙号与周期调度队列的队列号的映射关系，以构建时隙调度周期映射表，从而，网络节点在确定接收到的数据包属于确定性流，且该数据包中未携带CSQF域调度信息的情况下，依据该数据包的到达时间对应的目标时隙号，查询该数据包的出接口的时隙调度周期映射表，确定该数据包的达到时间对应的目标周期调度队列，即依据确定性流数据包的到达时间确定数据包的周期调度队列，而不再按照特定用户的确定性流在特定节点，总是以指定的周期进行转发的方式进行调度，有效吸收了确定性流调度过程中的节点内抖动。
至此，完成图1所示流程。
下面通过图4所示流程对确定数据包到达时间对应的目标时隙号的实现流程进行描述：
参见图4，图4为本申请实施例提供的确定数据包到达时间对应的目标时隙号的实现流程示意图。
如图4所示，该流程可以包括以下步骤：
步骤401，获取所述数据包的接收时间戳。
在本实施例中，数据包的接收时间戳可以是硬件对接收数据包打上的接收时间戳，某些硬件不支持打时间戳的场景，也可以在转发处理入口获得本节点的系统时钟，作为数据包的接收时间戳。
步骤402，将该数据包的接收时间戳转化为时隙数。
步骤403，依据该时隙数，以及时隙调度周期映射表中的时隙数，确定数据包到达时间对应的目标时隙号。
可选地，可以通过将数据包的接收时间戳转化得到的时隙数对时隙调度周期映射表的时隙数取余，得到数据包到达时间对应的目标时隙号。
举例来说，假设时隙调度周期映射表中的时隙数为256，数据包的接收时间戳转化为的时隙数为TimeSlotNum，则：
TimeSlotNum_Remainder＝(TimeSlotNum&0xFF)，或(TimeSlotNum％256)
其中，TimeSlotNum_Remainder即为数据包到达时间对应的目标时隙号。
示例性的，可以基于TimeSlotNum_Remainder为关键字查询时隙调度周期映射表，得到对应的周期调度队列的队列号，该周期调度队列的队列号即为该数据包在该网络节点中需要进入的周期调度队列的队列号。
至此，完成图4所示流程。
下面通过图5所示流程对确定时隙号与周期调度队列的队列号的映射关系的实现流程进行描述：
在实施例中，对于任一支持CSQF的出接口，该出接口的时隙调度周期映射表记录的时隙号与周期调度队列的队列号的映射关系，可以通过以下方式确定：
对于任一时隙号，依据该时隙号、调度偏移量，以及该出接口的周期调度队列的数量，确定该时隙号对应的周期调度队列的队列号；
其中，调度偏移量依据网络节点的节点内抖动确定。
示例性的，在本实施例中，时隙调度周期映射表也可以称为日历调度表(calendar)。
可选地，日历调度表可以包括以下信息和特征：
1、时隙号(Calendar_Slot)；
2、该时隙号映射的周期调度队列的队列号(Calendar_Que_No)。
其中，日历调度表的时隙数为周期调度队列的数量的整数倍。例如，周期调度队列的数量为8时，日历调度表的时隙数为8N(N为正整数)，如日历调度表的时隙数为256。
参见图5，图5为本申请实施例提供的确定时隙号对应的周期调度队列的队列号的实现流程示意图。
如图5所示，该流程可以包括：
步骤501，对于任一时隙号，将该时隙号与调度偏移量二者之和对该出接口的周期调度队列的数量取余，得到第一取余结果。
步骤502，将第一取余结果确定为该时隙号对应的周期调度队列的队列号。
在本实施例中，对于任一时隙号，该时隙号对应的周期调度队列可以依据该时隙号与调度偏移量二者之和确定。由于该时隙号与调度偏移量二者之和可能会大于周期调度队列的数量，因此，可以通过将该时隙号与调度偏移量二者之和对周期调度队列的数量取余，将取余结果(即第一取余结果)确定为该时隙号对应的周期调度队列的队列号。
示例性的，时隙号对应的周期调度队列的队列号Calendar_Que_No可以通过以下方式确定：
Calendar_Que_No＝(Calendar_Slot+Schedule_Offset)％Que_Num。
其中，Calendar_Slot为时隙号，Schedule_Offset为调度偏移量，Que_Num为周期调度队列的数量。
在本实施例中，调度偏移量可以用于表征输入转发处理单元在0时隙接收到的数据包，进入本节点的CSQF周期调度队列所对应的周期相对本节点CSQF的第一个周期的偏移，其确定方式可以参见下文图6举例描述的实现流程，这里不再赘述。
至此，完成图5所示流程。
下面通过图6所示流程对确定调度偏移量的实现流程进行描述：
参见图6，图6为本申请实施例提供的确定调度偏移量的实现流程示意图。
如图6所示，对于任一支持CSQF的出接口，确定调度偏移量的流程可以包括：
步骤601，依据测试报文在输入转发处理单元的接收时间戳，确定测试报文到达输出接口处理单元时，输出接口处理单元正在调度的该出接口的周期调度队列。
在本实施例中，可以利用周期测量与标定方法，确定测试报文从输入转发处理单元发出后到达输出接口处理单元时，输出接口处理单元正在调度的该出接口的周期调度队列。
步骤602，依据输出接口处理单元正在调度的该出接口的周期调度队列，以及网络节点的节点内抖动，确定测试报文的最优周期调度队列。
在本实施例中，在理想状态下，步骤601中确定的测试报文到达输出接口处理单元时，输出接口处理单元正在调度的该出接口的周期调度队列的下一个周期调度队列是测试报文最适合进入周期调度队列。
但是由于测试报文从输入转发处理单元发出，到输出接口处理单元将该测试报文调度入队这个过程中会存在一定的时延抖动(即上述网络节点的节点内抖动)，因此，可 以依据该时延抖动对测试报文需要进入的周期调度队列进行偏移，得到测试报文的最优周期调度队列。
举例来说，假设测试报文到达输出接口处理单元时，输出接口处理单元正在调度的该出接口的周期调度队列为队列2，而上述时延抖动为30us，一个时隙为10us，则可以将队列2的下一个周期调度队列(即队列3)再偏移3个队列之后的周期调度队列(队列6)，确定为该测试报文的最优调度队列。
步骤603，依据最优周期调度队列、该出接口的周期调度队列的数量，以及测试报文在输入转发处理单元的接收时间戳对应的时隙号，确定调度偏移量。
在本实施例中，基于上述步骤可以确定测试报文在输入转发处理单元的接收时间戳对应的时隙号对应的最优调度队列，即得到一个时隙号与最优调度队列的对应关系。
由于一个时隙对应一个调度周期，基于该对应关系，以及该时隙号与0时隙之间的偏移，可以确定0时隙对应的最优调度队列，该最优调度队列的队列号即可作为上述调度偏移量。
在本实施例中，在进行调度偏移量确定时，测试报文(也可以称为测试数据包)可以由CPU构造，并通过内部处理通道透传至输入转发处理单元，输入转发处理单元可以依据接收到该测试报文的系统时间为该测试报文打接收时间戳，并依据该接收时间戳确定测试报文到达输出接口处理单元时，输出接口处理单元正在调度的该测试报文的出接口的周期调度队列。
或者，测试报文也可以由输入转发处理单元构造，如输入转发处理单元可以在接收到测试命令时构造测试报文，在该情况下，输入转发处理单元可以依据测试报文构造完成时的系统时间为该测试报文打接收时间戳，并依据该接收时间戳确定测试报文到达输出接口处理单元时，输出接口处理单元正在调度的该测试报文的出接口的周期调度队列。
需要说明的是，输入转发处理单元接收到测试报文，或者，构造完成测试报文之后，可以按照与确定性流数据包到达CSQF域的边缘节点的输入转发处理单元之后的处理方式一致的处理方式对测试数据包进行转发处理，以实现CSQF域的边缘节点对确定性流数据包的转发处理的模拟。
此外，考虑到确定性流数据包的实际转发过程中，确定性流数据包到达CSQF域的边缘节点时，由输入接口处理单元为该数据包打接收时间戳，并依据该接收时间戳确定对应的时隙号(即上述目标时隙号)，并按照上述方式进行周期调度队列的映射，但由于数据包经过输入接口处理单元到达输入转发处理单元的时延通常会很小，且抖动也很小，因此，按照上述方式进行测试得到的调度偏移量可以较为准确地吸收节点内的抖动。
示例性的，为了进一步提高上述测试的准确性，对于测试报文的接收时间戳，可以在输入转发处理单元接收到测试报文，或，构造完成测试报文的系统时间的基础上，减去一个固定时间(对应报文经过输入接口处理单元到达输入转发处理单元的时延)，得到测试报文的接收时间戳。
在一个示例中，依据最优周期调度队列、该出接口的周期调度队列的数量，以及测试报文在输入转发处理单元的接收时间戳对应的时隙号，确定调度偏移量，包括：
将测试报文在输入转发处理单元的接收时间戳对应的时隙号对周期调度队列的数量取余，得到第二取余结果；
对最优周期调度队列的队列号与该出接口的周期调度队列的数量进行求和，得 到求和结果；
将求和结果与第二取余结果的差值对该出接口的周期调度序列的数量取余，得到第三取余结果；
将第三取余结果确定为调度偏移量。
示例性的，由于测试报文在输入转发处理单元的接收时间戳对应的时隙号即为测试报文在输入转发处理单元的接收时间戳对应的时隙号与0时隙之间的时隙差，该时隙差与测试报文的最优周期调度队列的队列号与0时隙的最优周期调度队列的队列号之间的差值应该是一致的。
举例来说，假设测试报文在输入转发处理单元的接收时间戳对应n时隙，测试报文的最优周期调度队列的队列号为RQ，则0时隙对应的最优周期调度队列的队列号应该为周期调度队列RQ回退n个周期后的周期调度队列。
考虑到n可能会大于周期数，因此，可以通过将n对该出接口的周期调度队列的数量进行取余，得到取余结果(即第二取余结果)，并将测试报文的最优周期调度队列RQ回退第二取余结果个周期。
又考虑到RQ可能会小于第二取余结果，因此，在对RQ进行回退时，可以先加上该出接口的周期调度队列的数量，然后再回退第二取余结果个周期，将得到的周期调度队列的队列号对该出接口的周期调度队列的数量进行取余，该取余结果(即第三取余结果)即为调度偏移量。
示例性的，调度偏移量Schedule_Offset可以通过以下策略确定：
Schedule_Offset＝(RQ+Que_Num-(n％Que_Num))％Que_Num
举例来说，假设在测试报文在输入转发处理单元的接收时间戳为xxx433us，测试报文到达输出接口处理单元时，输出接口处理单元正在调度的该测试报文的出接口的周期调度队列为队列2，则队列3是理论上测试报文最适合进入的队列，但由于测试报文从输入转发处理单元发出，到输出接口处理单元将测试报文入队会存在一定的时延抖动，假设为30us(假设一个时隙10us)，因此，测试报文的最优周期调度队列为队列2再偏移30us(即3个周期)，即队列6(即RQ＝6)。
基于此，可知测试报文的发送时间戳对应的时隙号43映射至与周期调度队列6。由于时隙号43与0时隙之间的时隙差为43，因此，0时隙对应的最优周期调度队列的队列号，即Schedule_Offset的值可以通过以下策略计算(假设测试报文的出接口的周期调度队列的数量为15)：
Schedule_Offset＝(RQ+Que_Num-(n％Que_Num))％Que_Num＝(6+15-(43％15))％15＝8
至此，完成图6所示流程。
进一步地，考虑到当存在多个确定性流接入时，可能产生多条流在相同时隙到达，导致流量冲突的情况产生。
由于流量冲突原因，部分确定性流可能无法安排到最接近的时隙，可能需要调整到临近的调度时隙(只要满足抖动需求就行)。因此，需要一个时隙更新表，对每条确定性流的到达时间对应的时隙号进行调整。
参见图7和图8，假设周期调度队列的数量为10个，时隙调度周期表(以Calendar为例)中的时隙数为100，图8中用户User1发送数据包的周期为730us(即73个调度周期)，该用户的第一个数据包的到达时间对应的时隙号为53，第二个数据包的到达时 间对应的时隙号为26。
假设该数据流的出接口的72时隙和74时隙存在流量冲突，但73时隙使用量很低(可以由控制器确定或人工监测确定)，则可以对图9中的时隙表进行更新，将到达时间对应的时隙号为72和74的数据包的时隙号更新为73，即将该数据包调度到73时隙对应的周期调度队列。
假设如图8中所示，实现10个CSQF周期队列，100个时隙的calendar。以图13中的用户USER1数据流为例，周期间隔是73个时隙(730us)，该用户第一个数据包在第53时隙，第2个包在26时隙，……。假设CSQF的同一接口的72和74时隙都有冲突，而73时隙使用量却很少(甚至没有)，则设计时隙更新表如图9所示，把本来应该在72和74时隙的数据包，都调度到73时隙对应的转发队列中。
如图9所示，Calendar_Slot为依据数据包的接收时间戳计算得到的时隙号；Calendar_Slot_Replace为更新后的时隙号。
又考虑到对于CSQF域中连接非确定性网络域的边缘节点，确定性流到达该节点之前，可能会存在需要跨越非确定性网络域的情况，导致同一确定性流到达该节点的时隙会存在一些抖动，为了消除这些抖动，实现对输入的确定性流的整形，对于同一确定性流的数据包，当其到达该节点的到达时间对应的时隙号为相邻的若干时隙号时，可以将其更新映射至同一时隙号。
例如，对于某一确定性流，该确定性流的到达时间对应的时隙号包括0、1和2，则可以将其均映射为时隙号2，实现对该确定性流的整形。
相应地，请参见图10，确定性流的传输方法流程可以如图10所示。
如图10，该流程可以包括以下步骤：
步骤1001，在确定接收到的数据包属于确定性流，且该数据包中未携带CSQF域调度信息的情况下，确定该数据包的到达时间对应的目标时隙号。
步骤1002，基于该目标时隙号查询该数据包所属业务流的时隙更新表，得到更新的时隙号。
步骤1003，依据更新的时隙号，查询数据包的出接口的时隙调度周期映射表，确定数据包到达的时隙对应的目标周期调度队列。
步骤1004，将数据包调度到数据包的出接口的目标周期调度队列。
通过生成时隙更新表，有效解决了CSQF域的边缘节点的确定性流调度时隙冲突问题，增强了CSQF的适应性，并能提高相同路径确定性流量的承载量；此外，依据时隙更新表，还可以实现针对确定性流的整形。
需要说明的是，由于对于广域确定性网络中连通非广域确定性网络(如TSN)的边缘节点，或，广域确定性网络超长路径CSQF转发中继节点，其接收到的确定性流均来自确定性域，通常不存在需要对确定性流进行整形的需求，也不会出现部分时隙使用量却很少，而另一部分时隙使用量过多的情况；此外，对于广域确定性网络中连通非广域确定性网络(如TSN)的边缘节点，或，广域确定性网络超长路径CSQF转发中继节点，其需要处理的确定性流的数量通常会较多，若针对每条确定性流均配置下发时隙更新表，会消耗巨大的资源，因此，在实际应用中，对于广域确定性网络中连通非广域确定性网络(如TSN)的边缘节点，或，广域确定性网络超长路径CSQF转发中继节点，可以不进行时隙更新表的配置和下发。
示例性的，可以在CSQF域中连接非确定性网络域的边缘节点针对每一条确定 性流下发一个时隙更新表。
下面通过图11对CSQF域的边缘节点对确定性流数据包的转发模型进行描述：
参见图11，图11为本申请实施例提供的CSQF域的边缘节点对确定性流数据包的转发模型的节点内时延分解示意图。
如图11所示，确定性流数据包在CSQF域边缘节点内的转发流程包括：
输入过程、分发过程、交换过程、映射过程、周期调度过程以及输出过程。其中：
输入过程(Input Process)：用于进行输入时间戳锚定。
示例性的，输入过程主要是硬件控制器的功能，实现输入时间戳的锚定。
分发过程(Distributing)：用于进行缓存分发。
示例性的，分发过程可以由硬件控制器实现，或通过软件实现。
交换过程(Switch Process)：用于进行节点内转发相关处理。
示例性的，交换过程可以包括软件处理，NP的微码配合硬件单元实现流水线管道。对于分布式设备，还可以包括输入接口板->网板->输出接口板的交换处理，具体实现可以参见下文图12举例描述的实现流程，这里不再赘述。
映射过程(Mapping)：用于将确定性流数据包根据周期映射到周期调度队列。
示例性的，映射过程需要软件(或NP的微码)或现场可编程门阵列(FPGA：Field Programmable Gate Array)参与，必需具备可编程能力以提供实现的灵活性。
周期调度过程(Scheduled by Cycle)：用于根据调度周期对周期调度队列进行调度，将处于发送周期队列中的数据发送给配置预留最高优先级硬件队列。
输出过程(Output Process)：用于进行硬件发送处理。
示例性的，输出过程可以通过配置预留最高优先级硬件队列作为发送确定性流量的硬件队列，打上输出时间戳。
在图11所示的多阶段时延分解中，Switch Process处理时延是不确定的，涉及节点内排队，可能多达20us～50us的差异。
以分布式设备的Switch Process处理为例。
参见图12，为本申请实施例提供的分布式设备Switch Process的转发模型示意图，如图12所示，Switch Process处理时延可以包括输入转发处理单元(图12中以Ingress NP为例)、内部交换单元(图12中以Fabric为例)以及输出转发处理单元(图12中以Egress NP为例)的处理时延，中间的抖动叠加后可能达到20us以上。
在图12所示的实现中，Mapping和Schedule by Cycle这两个阶段都是由输出接口处理单元(图12中以FPGA2为例)实现的，报文从进入输入接口处理单元(图12中以FPGA1为例)到输出接口处理单元进行Mapping处理之间，有较大的不确定时延抖动(即上述节点内抖动)。
示例性的，FPGA1和FPGA2可以为不同FPGA，也可以为相同FPGA(如针对流量环回或同一FPGA实现多个外部端口的场景)。
为了消除节点内抖动，可以按照上述方式，通过测试方式确定出调度偏移量。
举例来说，以图12所示实现为例，在进行调度偏移量确定时，可以依据测试报 文在Ingress NP的接收时间戳，确定测试报文到达FPGA2时，FPGA2正在调度的该测试报文的出接口的周期调度队列，并依据该周期调度队列，以及节点内时延，如30us，确定测试报文的最优周期调度队列，依据该最优周期调度队列的队列号，以及，测试报文在Ingress NP的接收时间戳对应的时隙号，按照上述方式，确定调度偏移量。
至此，完成本申请实施例提供的方法描述。下面对本申请实施例提供的电子设备进行描述：
参见图13，为本申请实施例提供的电子设备的硬件结构示意图，如图13所示，该电子设备包括处理器和机器可读存储介质；机器可读存储介质存储有能够被所述处理器执行的机器可执行指令；所述处理器用于执行机器可执行指令，以实现本申请上述示例公开的方法。
具体地，处理器通过执行机器可执行指令以实现：在确定接收到的数据包属于确定性流，且该数据包中未携带CSQF域调度信息的情况下，确定所述数据包的到达时间对应的目标时隙号；依据所述目标时隙号，查询所述数据包的出接口的时隙调度周期映射表，确定所述目标时隙号对应的目标周期调度队列；其中，所述时隙调度周期映射表依据所述网络节点的节点内抖动确定，用于记录时隙号与周期调度队列的队列号的映射关系；将所述数据包调度到所述数据包的出接口的目标周期调度队列。
在一个例子中，处理器通过执行机器可执行指令以实现：获取所述数据包的接收时间戳；将所述数据包的接收时间戳转化为时隙数；依据所述时隙数，以及所述时隙调度周期映射表中的时隙数，确定所述数据包到达时间对应的目标时隙号。
在一个例子中，处理器通过执行机器可执行指令以实现：对于任一支持指定周期排队转发CSQF的出接口，通过以下方式确定该出接口的所述时隙调度周期映射表记录的时隙号与周期调度队列的队列号的映射关系：对于任一时隙号，依据该时隙号、调度偏移量，以及该出接口的周期调度队列的数量，确定该时隙号对应的周期调度队列的队列号；其中，所述调度偏移量依据所述网络节点的节点内抖动确定。
在一个例子中，处理器通过执行机器可执行指令以实现：将该时隙号与所述调度偏移量二者之和对该出接口的周期调度队列的数量取余，得到第一取余结果；将所述第一取余结果确定为该时隙号对应的周期调度队列的队列号。
在一个例子中，处理器通过执行机器可执行指令以实现：通过以下方式确定调度偏移量：依据测试报文在输入转发处理单元的接收时间戳，确定所述测试报文到达输出接口处理单元时，输出接口处理单元正在调度的该出接口的周期调度队列；依据输出接口处理单元正在调度的该出接口的周期调度队列，以及所述网络节点的节点内抖动，确定所述测试报文的最优周期调度队列；依据所述最优周期调度队列、该出接口的周期调度队列的数量，以及所述测试报文在输入转发处理单元的接收时间戳对应的时隙号，确定所述调度偏移量。
在一个例子中，处理器通过执行机器可执行指令以实现：将所述测试报文在输入转发处理单元的接收时间戳对应的时隙号对所述周期调度队列的数量取余，得到第二取余结果；对所述最优周期调度队列的队列号与该出接口的周期调度队列的数量进行求和，得到求和结果；将所述求和结果与所述第二取余结果的差值对该出接口的周期调度队列的数量取余，得到第三取余结果；将所述第三取余结果确定为所述调度偏移量。
在一个例子中，处理器还通过执行机器可执行指令以实现：依据所述目标时隙号，查询该数据包所属业务流的时隙更新表，得到更新的时隙号；依据所述更新的时隙号，查询所述数据包的出接口的时隙调度周期映射表，确定所述数据包到达的时隙对应的目标周期调度队列。
在一个例子中，确定性流数据包在CSQF域边缘节点内的转发流程包括：
输入过程、分发过程、交换过程、映射过程、周期调度过程以及输出过程；其中：
所述输入过程用于进行输入时间戳锚定；
所述分发过程用于进行缓存分发；
所述交换过程用于进行节点内转发相关处理；
所述映射过程用于将确定性流数据包根据周期映射到周期调度队列；
所述周期调度过程用于根据调度周期对周期调度队列进行调度，将处于发送周期队列中的数据发送给配置预留最高优先级硬件队列；
所述输出过程用于进行硬件发送处理。
在一个例子中，网络节点的节点内抖动包括所述交换过程的处理时延抖动。
基于与上述方法同样的申请构思，本申请实施例还提供了一种存储有计算机可执行指令的非暂时性机器可读存储介质，例如图13中的机器可读存储介质，计算机可执行指令可由图13所示电子设备中的处理器801执行以实现上文描述的分析数据流的方法。
示例性的，上述机器可读存储介质可以是任何电子、磁性、光学或其它物理存储装置，可以包含或存储信息，如可执行指令、数据，等等。例如，机器可读存储介质可以是：RAM(Radom Access Memory，随机存取存储器)、易失存储器、非易失性存储器、闪存、存储驱动器(如硬盘驱动器)、固态硬盘、任何类型的存储盘(如光盘、dvd等)，或者类似的存储介质，或者它们的组合。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机，计算机的具体形式可以是个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件收发设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任意几种设备的组合。
为了描述的方便，描述以上装置时以功能分为各种单元分别描述。当然，在实施本申请时可以把各单元的功能在同一个或多个软件和/或硬件中实现。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可以由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其它可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其它可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
而且，这些计算机程序指令也可以存储在能引导计算机或其它可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令 产生包括指令装置的制造品，该指令装置实现在流程图一个流程或者多个流程和/或方框图一个方框或者多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其它可编程数据处理设备上，使得在计算机或者其它可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其它可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (11)

  1. 一种确定性流传输方法，其特征在于，该方法应用于网络节点，该方法包括：
    在确定接收到的数据包属于确定性流，且该数据包中未携带指定周期排队转发CSQF域调度信息的情况下，确定所述数据包的到达时间对应的目标时隙号；
    依据所述目标时隙号，查询所述数据包的出接口的时隙调度周期映射表，确定所述目标时隙号对应的目标周期调度队列；其中，所述时隙调度周期映射表依据所述网络节点的节点内抖动确定，用于记录时隙号与周期调度队列的队列号的映射关系；
    将所述数据包调度到所述数据包的出接口的目标周期调度队列。
  2. 根据权利要求1所述的方法，其特征在于，所述确定所述数据包到达时间对应的时隙号，包括：
    获取所述数据包的接收时间戳；
    将所述数据包的接收时间戳转化为时隙数；
    依据所述时隙数，以及所述时隙调度周期映射表中的时隙数，确定所述数据包到达时间对应的目标时隙号。
  3. 根据权利要求1所述的方法，其特征在于，对于任一支持CSQF的出接口，该出接口的所述时隙调度周期映射表记录的时隙号与周期调度队列的队列号的映射关系，通过以下方式确定：
    对于任一时隙号，依据该时隙号、调度偏移量，以及该出接口的周期调度队列的数量，确定该时隙号对应的周期调度队列的队列号；
    其中，所述调度偏移量依据所述网络节点的节点内抖动确定。
  4. 根据权利要求3所述的方法，其特征在于，所述依据该时隙号、调度偏移量，以及该出接口的周期调度队列的数量，确定该时隙号对应的周期调度队列的队列号，包括：
    将该时隙号与所述调度偏移量二者之和对该出接口的周期调度队列的数量取余，得到第一取余结果；
    将所述第一取余结果确定为该时隙号对应的周期调度队列的队列号。
  5. 根据权利要求3所述的方法，其特征在于，所述调度偏移量通过以下方式确定：
    依据测试报文在输入转发处理单元的接收时间戳，确定所述测试报文到达输出接口处理单元时，输出接口处理单元正在调度的该出接口的周期调度队列；
    依据输出接口处理单元正在调度的该出接口的周期调度队列，以及所述网络节点的节点内抖动，确定所述测试报文的最优周期调度队列；
    依据所述最优周期调度队列、该出接口的周期调度队列的数量，以及所述测试报文在输入转发处理单元的接收时间戳对应的时隙号，确定所述调度偏移量。
  6. 根据权利要求5所述的方法，其特征在于，所述依据所述最优周期调度队列、该出接口的周期调度队列的数量，以及所述测试报文在输入转发处理单元的接收时间戳对应的时隙号，确定所述调度偏移量，包括：
    将所述测试报文在输入转发处理单元的接收时间戳对应的时隙号对所述周期调度队列的数量取余，得到第二取余结果；
    对所述最优周期调度队列的队列号与该出接口的周期调度队列的数量进行求和，得到求和结果；
    将所述求和结果与所述第二取余结果的差值对该出接口的周期调度队列的数量取余，得到第三取余结果；
    将所述第三取余结果确定为所述调度偏移量。
  7. 根据权利要求1所述的方法，其特征在于，所述确定所述数据包的到达时间对应的目标时隙号之后，还包括：
    依据所述目标时隙号，查询该数据包所属业务流的时隙更新表，得到更新的时隙号；
    所述依据所述目标时隙号，查询所述数据包的出接口的时隙调度周期映射表，确定所述数据包到达的时隙对应的目标周期调度队列，包括：
    依据所述更新的时隙号，查询所述数据包的出接口的时隙调度周期映射表，确定所述数据包到达的时隙对应的目标周期调度队列。
  8. 根据权利要求1所述的方法，其特征在于，确定性流数据包在CSQF域边缘节点内的转发流程包括：
    输入过程、分发过程、交换过程、映射过程、周期调度过程以及输出过程；其中：
    所述输入过程用于进行输入时间戳锚定；
    所述分发过程用于进行缓存分发；
    所述交换过程用于进行节点内转发相关处理；
    所述映射过程用于将确定性流数据包根据周期映射到周期调度队列；
    所述周期调度过程用于根据调度周期对周期调度队列进行调度，将处于发送周期队列中的数据发送给配置预留最高优先级硬件队列；
    所述输出过程用于进行硬件发送处理。
  9. 根据权利要求8所述的方法，其特征在于，所述网络节点的节点内抖动包括所述交换过程的处理时延抖动。
  10. 一种电子设备，其特征在于，该电子设备包括：处理器和机器可读存储介质；
    所述机器可读存储介质存储有能够被所述处理器执行的机器可执行指令；
    所述处理器用于执行机器可执行指令，以实现权利要求1-9任一项的方法。
  11. 一种非暂时性机器可读存储介质，其特征在于，所述非暂时性机器可读存储介质存储有指令，所述指令促使所述处理器以实现权利要求1-9任一项的方法。
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