WO2023130883A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
WO2023130883A1
WO2023130883A1 PCT/CN2022/137301 CN2022137301W WO2023130883A1 WO 2023130883 A1 WO2023130883 A1 WO 2023130883A1 CN 2022137301 W CN2022137301 W CN 2022137301W WO 2023130883 A1 WO2023130883 A1 WO 2023130883A1
Authority
WO
WIPO (PCT)
Prior art keywords
isolation layer
layer
semiconductor
trench
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/137301
Other languages
English (en)
French (fr)
Inventor
韩清华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to EP22888619.8A priority Critical patent/EP4231342B1/en
Priority to US18/313,417 priority patent/US12431385B2/en
Publication of WO2023130883A1 publication Critical patent/WO2023130883A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • Embodiments of the present disclosure relate to but are not limited to a semiconductor structure and a manufacturing method thereof.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming a plurality of first trenches extending along a first direction in the substrate, and the first The trench forms the substrate into semiconductor layers arranged at intervals, and fills the first isolation layer in the first trench; a plurality of strips extending along the second direction are formed in the semiconductor layer and the first isolation layer.
  • the depth of the second trench is smaller than the depth of the first trench, so that the semiconductor layer is formed into a plurality of discrete semiconductor pillars and initial bit lines located under the semiconductor pillars;
  • a third trench parallel to the first trench is formed at a position lower than the second trench, and in a direction perpendicular to the sidewall of the semiconductor pillar, the width of the third trench is larger than that of the first trench.
  • the width of the second trench filling the second isolation layer in the second trench and the third trench, wherein there is a void in the second isolation layer in the third trench.
  • the width of the first trench is greater than or equal to the width of the second trench.
  • the step of forming the third groove parallel to the first groove at a position lower than the second groove includes: forming a protective layer, the protective layer is located on the second On the sidewall of the trench, and expose the top surface of the initial bit line and the top surface of the first isolation layer between the adjacent initial bit lines; use the protective layer as a mask to remove the initial bit line part of the thickness of the sidewall of the first isolation layer to form the third trench; and removing the protection layer.
  • the method before forming the protective layer, the method further includes: forming a third isolation layer, the third isolation layer is only located on the exposed sidewall surface of the trench.
  • the etching selectivity ratio between the first isolation layer and the protection layer is greater than or equal to 50.
  • the fourth isolation layer after forming the third trench and before forming the second isolation layer, further comprising: forming a fourth isolation layer on the surface of the initial bit line exposed by the third trench , and the fourth isolation layer does not change the overall shape of the third trench.
  • the fourth isolation layer after forming the fourth isolation layer and before forming the second isolation layer, further comprising: removing the fourth isolation layer located on the top surface of the initial bit line;
  • the initial bit line is silicided to form a bit line, and the material of the bit line includes a metal semiconductor compound.
  • the depth of the third trench is greater than the depth of the metal-semiconductor compound in a direction in which the semiconductor pillar points to the bit line.
  • the manufacturing method further includes: removing part of the thickness of the second isolation layer in the second trench to form a groove, the groove extending along the second direction; The insulating layer of the groove; using the insulating layer as a mask to remove the first isolation layer and the second isolation layer of the sidewall of the semiconductor column with a partial thickness, so that the semiconductor column and the semiconductor column A gap is formed between the insulating layers; in the direction perpendicular to the sidewall of the second trench, a gate dielectric layer and a word line are sequentially stacked in the gap.
  • the semiconductor pillar along the direction from the initial bit line to the semiconductor pillar, includes a first doped region, a channel region and a second doped region arranged in sequence; the groove is formed
  • the method includes patterning, and the sidewall of the groove is formed by the remaining second isolation layer, and in the direction where the first doped region points to the channel region, the depth of the groove is greater than equal to the sum of the height of the channel region and the height of the second doped region.
  • the step of forming the gap includes: using the insulating layer as a mask to remove the first isolation layer and the second isolation layer corresponding to the second doped region; forming a dielectric layer , the dielectric layer surrounds the sidewall of the second doped region and is located on the sidewall of the insulating layer, the sidewall of the dielectric layer encloses a through hole, the bottom of the through hole exposes the first isolation layer, and the The material of the dielectric layer and the material of the insulating layer are different from the material of the first isolation layer; the second isolation layer and the first isolation layer corresponding to the channel region exposed by the through hole are removed. an isolation layer to form the gap, and the remaining second isolation layer and the first isolation layer jointly surround the sidewall of the first doped region.
  • the step of forming the gap includes: using the insulating layer as a mask to remove the first isolation layer and the second doped region corresponding to the second doped region and the channel region. an isolation layer to form the gap, and the remaining second isolation layer and the first isolation layer jointly surround the sidewall of the first doped region.
  • the gate dielectric layer is located at least on the exposed sidewall of the channel region, and there is a second gap between the gate dielectric layer and the insulating layer.
  • the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate, the substrate includes a plurality of semiconductor layers arranged at intervals, and a first semiconductor layer located between adjacent semiconductor layers.
  • an isolation layer the semiconductor layer includes a bit line extending along a first direction and a semiconductor column located on the top surface of the bit line, the first isolation layer is located on the side wall of the end of the semiconductor column close to the bit line and A third trench is located between the adjacent bit lines and between the first isolation layer located between the adjacent bit lines and the first isolation layer located on the sidewall of the semiconductor pillar, And the third grooves are arranged at intervals along a second direction, the second direction is different from the first direction; the second isolation layer is located on the sidewall of the end of the semiconductor column close to the bit line and on the The surface of the bit line exposed by the third trench, and there is a gap in the second isolation layer in the third trench.
  • the semiconductor structure further includes: a gate dielectric layer surrounding at least the remaining sidewalls of the semiconductor pillars close to a partial thickness of the second isolation layer; a word line surrounding the gate dielectric layer away from all The side wall surface of the semiconductor column, and the word line extends along the second direction, and there is a space between adjacent word lines; the insulating layer at least fills the space.
  • the first isolation layer with a partial thickness of the sidewall of the initial bit line is removed to form a third trench between adjacent initial bit lines, so that in a direction perpendicular to the sidewall of the semiconductor pillar, the third trench
  • the width is greater than the width of the second trench, so when the second isolation layer is subsequently formed, the region corresponding to the third trench in the second isolation layer has a gap, and the adjacent initial bit lines are formed by the second isolation layer and the second trench.
  • the isolation structure of the gap realizes insulation. Since the relative dielectric constant of the air in the gap is much smaller than that of the second isolation layer, that is, the insulation of the air is better than that of the second isolation layer, which is beneficial to reduce the adjacent initial position.
  • the parasitic capacitance between lines reduces the influence between semiconductor pillars electrically connected to different initial bit lines, so as to improve the overall electrical performance of the semiconductor structure.
  • 1 to 24 are structural schematic diagrams corresponding to each step of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure.
  • the implementation of the present disclosure provides a semiconductor structure and a manufacturing method thereof.
  • a third trench is pre-formed between adjacent initial bit lines, so that when the second isolation layer is subsequently formed, the inside of the second isolation layer and the third trench
  • the corresponding region has a gap, and since the relative dielectric constant of the air in the gap is much smaller than that of the second isolation layer, it is beneficial to reduce the parasitic capacitance between adjacent initial bit lines and reduce the electrical connection with different initial bit lines.
  • the influence between semiconductor pillars to improve the electrical performance of the semiconductor structure as a whole.
  • FIGS. 1 to 24 are structural schematic diagrams corresponding to each step of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure. It should be noted that, in order to facilitate the description and clearly illustrate the steps of the method for fabricating the semiconductor structure, FIGS. 1 to 24 in this embodiment are all partial structural diagrams of the semiconductor structure.
  • FIG. 4 is a top view of the structure shown in Fig. 3
  • Fig. 5 is a schematic cross-sectional view of the structure shown in Fig. 4 along the first cross-sectional direction AA1
  • Fig. 6 and Fig. 7 are cross-sections of the subsequently formed intermediate structure along the first cross-sectional direction AA1
  • FIG. 8 is a schematic cross-sectional view of the subsequently formed intermediate structure along the second cross-sectional direction BB1
  • FIG. 9 is a schematic cross-sectional view of the subsequently formed intermediate structure along the third cross-sectional direction CC1.
  • a substrate 100 is provided; a plurality of first grooves 113 extending along a first direction X are formed in the substrate 100, and the first grooves 113 form the substrate 100 into semiconductor layers 101 arranged at intervals; and The first trench 113 is filled with the first isolation layer 102 .
  • providing the substrate 100 includes the following steps:
  • An initial substrate is provided, and the material type of the initial substrate can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or gallium indium.
  • the initial substrate is doped and annealed, so that the initial substrate is doped with N-type ions or P-type ions for subsequent formation of initial bit lines and semiconductor pillars on the basis of the initial substrate.
  • N-type ions may be at least one of arsenic ions, phosphorus ions or antimony ions;
  • P-type ions may be at least one of boron ions, indium ions or gallium ions.
  • a first mask layer (not shown) is formed on the initial substrate.
  • the first mask layer has a plurality of first openings separated from each other.
  • the first openings extend along a first direction X.
  • the first openings The length of is consistent with the length of the initial bit line 104 formed later.
  • the initial substrate is etched using the first mask layer as a mask to form a plurality of first trenches 113 .
  • a plurality of second trenches 123 extending along the second direction Y are formed in the semiconductor layer 101 and the first isolation layer 102, the depth of the second trenches 123 is smaller than the depth of the first trenches 113,
  • the semiconductor layer 101 is formed into a plurality of discrete semiconductor pillars 105 and initial bit lines 104 located below the semiconductor pillars 105 .
  • forming the semiconductor pillar 105 and the initial bit line 104 includes the following steps:
  • a second mask layer (not shown) is formed on the top surface of the first isolation layer 102 and the remaining initial substrate.
  • the second mask layer has a plurality of separate second openings along the first The two extend in the direction Y, and the length of the second opening is consistent with the length of the subsequently formed word line.
  • the initial substrate and the first isolation layer 102 are etched using the second mask layer as a mask. It should be noted that, after the formation of the semiconductor pillars 105 and the initial bit lines 104, the first isolation layer 102 is not only located between the adjacent initial bit lines 104 In the interval, and in the interval between adjacent semiconductor pillars 105 .
  • the depth of the second groove 123 is smaller than the depth of the first groove 113 (refer to FIG. the semiconductor column 105, and the initial bit line 104 is in contact with the first doped region I of the semiconductor column 105; the second mask layer is removed.
  • the width of the first trench 113 is greater than or equal to the width of the second trench 123 (refer to FIG. 4 ). It is beneficial to ensure that when the third trench 133 is subsequently formed (refer to FIG. 8 ), the opening of the second trench 123 is always smaller than the opening of the third trench 133, so that when the second isolation layer 132 is subsequently formed (refer to FIG. 14 ), The second isolation layer 132 having a void is formed in a corresponding region of the third trench 133 . In some examples, the ratio of the width of the first trench 113 to the width of the second trench 123 may be 1.5 ⁇ 2.
  • the method for forming the initial bit line 104, the semiconductor pillar 105 and the first isolation layer 102 includes self-aligned multiple exposure technology (SAQP, Self-Aligned Quadruple Patterning) or self-aligned double imaging technology (SADP, Self-aligned Double Patterning).
  • SAQP Self-Aligned Quadruple Patterning
  • SADP Self-aligned Double Patterning
  • the second trenches 123 are arranged at intervals along the first direction X; in the direction Z along the bottom of the second trench 123 to the top of the second trench 123, the semiconductor layer 101 includes initial bit lines arranged in sequence 104 and a semiconductor pillar 105, and the semiconductor pillar 105 includes a first doped region I, a channel region II and a second doped region III arranged in sequence. It should be noted that both the first doped region I and the second doped region III can serve as the source or drain of the subsequently formed GAA transistor having the semiconductor layer 101, and the channel region II and the gate dielectric layer and the GAA transistor corresponding to the word line.
  • the initial bit line 104 is prepared for the subsequent metal silicidation process to form the bit line.
  • the first direction X is perpendicular to the second direction Y, so that the formed semiconductor layer 101 exhibits a 4F2 (F: minimum pattern size obtainable under given process conditions) arrangement.
  • the layout method is conducive to improving the integration density of the semiconductor structure.
  • the first direction intersects the second direction, and the angle between them may be, for example, 80°, 85°, 100°, or 120°.
  • each initial bit line 104 can be in contact with at least one first doped region I.
  • the initial bit lines 104, and each initial bit line 104 is in contact with four first doped regions I as an example.
  • the number of initial bit lines 104 and each initial bit line 104 can be reasonably set according to actual electrical requirements. The number of the first doped regions I that the bit line 104 is in contact with.
  • the device formed by the semiconductor pillars 105 may be a junctionless transistor, that is, the types of doping ions in the first doped region I, the channel region II and the second doped region III are the same.
  • No junction refers to no PN junction, that is, the doping concentration of the doping ions in the first doped region I, the channel region II and the second doped region III is the same, such benefits include: on the one hand, no need The first doped region I and the second doped region III are additionally doped, thereby avoiding the problem that the doping process of the first doped region I and the second doped region III is difficult to control, especially as The size of the transistor is further reduced.
  • the doping concentration will be more difficult to control; Drain concentration gradient doping process, the phenomenon of making ultra-steep PN junctions in the nanoscale range, can avoid threshold voltage drift and leakage current increase caused by doping mutations, and is also conducive to suppressing short-channel effects, so it is useful It helps to further improve the integration density and electrical performance of semiconductor structures.
  • the additional doping here refers to the doping performed to make the doping ion types of the first doping region I and the second doping region III different from the doping ion type of the channel region II. miscellaneous.
  • both the initial bit line 104 and the semiconductor layer 101 are formed by etching the initial substrate, that is, the initial bit line 104 and the semiconductor layer 101 are formed using the same film layer structure, so that the initial The bit line 104 and the semiconductor layer 101 have an integrated structure, thereby improving the interface state defects between the initial bit line 104 and the semiconductor layer 101 and improving the performance of the semiconductor structure.
  • the top surface of the semiconductor pillar 105 may not have a polysilicon layer, that is The top surfaces of the semiconductor pillars 105 may also be exposed.
  • a third trench 133 parallel to the first trench 113 (see FIG. Above, that is, in the direction X in FIG. 3 , the width of the third trench 133 is greater than the width of the second trench 123 . It is beneficial to form voids in the region corresponding to the third trench 133 in the second isolation layer 132 when filling the second trench 123 and the third trench 133 to form the second isolation layer 132 (refer to FIG. 14 ).
  • forming the third trench 133 parallel to the first trench 113 at a position lower than the second trench 123 includes the following steps:
  • a passivation layer 125 is formed.
  • the passivation layer 125 is located on the sidewall of the second trench 123 and exposes the top surface of the initial bit line 104 and the top surface of the first isolation layer 102 between adjacent initial bit lines 104 . It should be noted that, when the top surface of the semiconductor pillar 105 has the polysilicon layer 115 , the protection layer 125 can also be located on the sidewall of the polysilicon layer 115 .
  • the passivation layer 125 is located on the sidewall surface of the second trench 123 .
  • the protective layer 125 can be formed by the following process steps: performing a deposition process to form a protective film covering the side walls and bottom of the second trench 123 and the top surface of the semiconductor pillar 105; performing etching treatment on the protective film, such as vertical dry etching, Part of the bottom surface of the second trench 123 is exposed, that is, part of the top surface of the initial bit line 104 is exposed, and the remaining protection film is used as the protection layer 125 .
  • the material of the protective film includes silicon nitride.
  • the protection layer 125 may further include: forming a third isolation layer 112 , the third isolation layer 112 is only located on the exposed sidewall surface of the second trench 123 .
  • the third isolation layer 112 and the protective layer 125 can be formed by the following process steps: first form the third isolation layer 112 on the side wall surface of the semiconductor pillar 105, and then perform a deposition process to form a second trench covering the surface of the third isolation layer 112 123 bottom surface and the protective film on the top surface of the semiconductor pillar 105; the protective film is etched, such as vertical dry etching, to expose part of the bottom surface of the second trench 123, that is, to expose the initial bit line 104 and the first isolation layer 102 part of the top surface, the remaining protective film is used as the protective layer 125.
  • the material of the protection film includes silicon nitride, and the material of the third isolation layer 112 includes silicon oxide.
  • the third isolation layer 112 can be used to protect the semiconductor pillar 105 and prevent the semiconductor pillar 105 from being silicided.
  • the part of the thickness of the first isolation layer located on the sidewall of the initial bit line 104 is removed using the protective layer 125 as a mask. 102 , to form a third trench 133 between adjacent initial bit lines 104 to prepare for subsequent formation of gaps between adjacent initial bit lines 104 .
  • a wet etching process can be used to remove the sidewall of the initial bit line 104 starting from the part of the top surface of the first isolation layer 102 exposed by the protective layer 125. Partial thickness of the first isolation layer 102 .
  • the etching selectivity ratio between the first isolation layer 102 and the protective layer 125 can be greater than or equal to 50, such as 60, 70, 100, or no etching occurs, which is beneficial to remove the initial bit line 104
  • the protection layer 125 and the structure covered by the protection layer 125 are less or not etched.
  • the protective layer 125 can be removed. It should be noted that, in the step of removing the protective layer 125 , the polysilicon layer 115 may also be removed.
  • the third isolation layer 112 can be removed together in the step of removing the protective layer 125; in other embodiments , can be removed after the initial bit line 104 is silicided, so that the semiconductor pillar 105 can be protected by the third isolation layer 112 when the initial bit line is silicided.
  • the width of the third trench 133 is greater than the width of the second trench 123 .
  • the width of the second trench 123 is narrower, which is beneficial to the second isolation layer 132 in the subsequent step of forming the second isolation layer 132 (see FIG. 14 ).
  • the ratio of the width of the formed third groove 133 to the width of the second groove 123 may be 1.1 ⁇ 4, such as 1.5, 2, 3.5, 4.
  • the manufacturing method may further include the following steps:
  • the fourth isolation layer 122 is formed on the surface of the semiconductor layer 101 exposed by the third trench 133, and the fourth isolation layer 122 does not change the third trench 133 overall appearance.
  • the protection layer 125 and the polysilicon layer 115 are removed.
  • the fourth isolation layer 122 shown in FIG. 12 to FIG. The third isolation layer 112 has also been removed, that is, the fourth isolation layer 122 not only surrounds the exposed sidewall surface of the initial bit line 104, but also is located on the top surface and part of the exposed sidewall of the semiconductor pillar 105; in other embodiments, When the third isolation layer is not removed, the fourth isolation layer surrounds the exposed sidewall surface of the original bit line and is located on the top surface of the semiconductor pillar.
  • the fourth isolation layer 122 can be formed by performing thermal oxidation treatment on the exposed surface of the semiconductor layer 101 .
  • Both the fourth isolation layers 122 are used to protect other parts of the semiconductor layer 101 and prevent other parts of the semiconductor layer 101 from being affected by the metal silicidation process when the metal silicidation process is performed on the top surface of the initial bit line 104 . Avoid other parts of the semiconductor layer 101 being treated by metal silicide; avoid subsequent adjacent semiconductor layers 101 having metal materials in addition to insulating materials, avoid excessive parasitic capacitance between adjacent semiconductor layers 101, and reduce the electrical properties of the semiconductor structure. performance.
  • the material of the semiconductor layer 101 may be silicon
  • the material of the fourth isolation layer 122 may be silicon oxide.
  • the manufacturing method may further include the following steps:
  • the fourth isolation layer 122 on the top surface of the initial bit line 104 (refer to FIG. 10) is removed. It should be noted that, in some embodiments, in the step of removing the fourth isolation layer 122 located on the top surface of the initial bit line 104, the fourth isolation layer 122 located on the top surface of the semiconductor pillar 105 is also removed; in other embodiments , the fourth isolation layer 122 on the top surface of the semiconductor pillar may also be reserved.
  • metal silicide treatment is performed on the exposed initial bit line 104 to form a bit line 114 , and the material of the bit line 114 includes a metal-semiconductor compound 124 .
  • the metal silicidation process includes: forming a metal layer (not shown) on the fourth isolation layer 122, a part of the top surface of the initial bit line 104, and a part of the top surface of the first isolation layer 102; annealing to make the metal layer react with the initial bit line 104 to form the bit line 114 ; and remove the unreacted remaining metal layer.
  • the metal silicidation process includes: directionally doping the exposed top surface of the initial bit line 104 with metal elements, and then performing annealing, which is beneficial to avoid the need to remove the metal-semiconductor compound 124 formed elsewhere.
  • the depth of the third trench 133 is greater than the depth of the metal-semiconductor compound 124 in the direction in which the semiconductor pillar 105 points to the bit line 114 .
  • the material of the region of the initial bit line 104 located directly under the first doped region I is a semiconductor material, and the part of the initial bit line 104 not covered by the first doped region I
  • the material of the region is a metal-semiconductor compound. It can be understood that, with the shrinking of the device size or the adjustment of the manufacturing process parameters, the material of the partial region of the initial bit line 104 located directly below the first doped region I is a semiconductor material, and the material located directly below the first doped region I
  • the material of the remaining area of the lower initial bit line 104 may also be a metal-semiconductor compound, where the "remaining area" is located at the periphery of the "partial area”.
  • the multiple metal-semiconductor compounds 124 in the semiconductor layer 101 are interconnected to form a part of the bit line 114 ; in other embodiments, the multiple metal-semiconductor compounds in the same bit line may also be spaced apart from each other. It should be noted that the region of the semiconductor layer 101 defined by the dotted line frame similar to the ellipse in FIG. There is no limit to the size. In other embodiments, the full thickness of the original bit line 104 may be converted to the metal-semiconductor compound 124 .
  • the manufacturing method may further include: performing metal silicide treatment on the top surface of the second doped region III, so that When the lower electrode of the capacitive structure is to be formed on the top surface of the second doped region III, the second doped region III forms an ohmic contact with the lower electrode, avoiding the direct contact between the lower electrode and the semiconductor material to form a Schottky barrier contact, The ohmic contact is beneficial to reduce the contact resistance between the second doped region III and the bottom electrode, thereby reducing the energy consumption of the semiconductor structure during operation, and improving the RC delay effect to improve the electrical performance of the semiconductor structure.
  • the metal silicide treatment on the top surface of the initial bit line 104 and the top surface of the second doped region III can be performed in the same process step, which is beneficial to simplify the process steps. In other embodiments, the metal silicide treatment on the top surface of the initial bit line 104 and the top surface of the second doped region III may also be performed in steps.
  • the material of the metal layer or the directionally doped metal element may include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum, and the metal
  • the semiconductor compound 124 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide.
  • the metal-semiconductor compound 124 has a relatively lower resistivity than the unmetallized semiconductor material, and the bitline 114 has a lower resistivity than the original bitline 104 without metallization, thereby It is beneficial to reduce the resistance of the bit line 114 itself, and reduce the contact resistance between the bit line 114 and the first doped region I, and further improve the electrical performance of the semiconductor structure.
  • the second isolation layer 132 is filled in the second trench 123 (see FIG. 3) and the third trench 133 (see FIG. 8), wherein the second isolation layer in the third trench 133 132 has a void 143 therein.
  • the method of forming the second isolation layer 132 having the void 143 includes a deposition process.
  • the width of the third trench 133 is greater than the width of the second trench 123 in the direction perpendicular to the sidewall of the semiconductor pillar 105, that is, the direction X, therefore, in the step of depositing and forming the second isolation layer 132, for The deposited material for forming the second isolation layer 132 forms a seal above the void 143 when the third trench 133 is not completely filled, thereby forming the void 143 in the second isolation layer 132 .
  • the relative permittivity of the air in the gap 143 is much smaller than the relative permittivity of the second isolation layer 132, that is, the insulation of the air is better than that of the second isolation layer 132, which is beneficial to reduce the distance between adjacent bit lines 114.
  • the parasitic capacitance reduces the influence between the semiconductor pillars 105 electrically connected to different bit lines 114, so as to improve the overall electrical performance of the semiconductor structure.
  • the manufacturing method may further include: removing part of the thickness of the second isolation layer 132 inside the second trench 123 (see FIG. 3 ) to form a groove (not shown in the figure).
  • the groove extends along the second direction Y; an insulating layer 117 filling the groove is formed; the first isolation layer 102 and the second isolation layer 132 of the sidewall of the semiconductor pillar 105 with a partial thickness are removed by using the insulating layer 117 as a mask, so as to A gap 153 is formed between the semiconductor pillar 105 and the insulating layer 117 .
  • Subsequent formation of the gate dielectric layer and word lines on the basis of the gap 153 can form a gate dielectric layer and word lines with precise dimensions in the gap 143 by self-alignment, and form high-dimensional precision without an etching process.
  • the gate dielectric layer and the word line are beneficial to simplify the steps of forming the gate dielectric layer and the word line, and by adjusting the size of the gap 143 , a small-sized gate dielectric layer and the word line can be obtained.
  • the method of forming the groove includes patterning, and the sidewall of the groove is formed by the remaining second isolation layer 132.
  • the depth of the groove is greater than or equal to that of the channel region
  • the sum of the height of II and the height of the second doped region III, that is, the bottom surface of the insulating layer 117 close to the bit line 114 is not higher than the top surface of the first doped region I away from the bit line 114 . It should be noted that, in practical applications, the depth of the insulating layer 117 may be equal to the depth of the semiconductor pillar 105 at most.
  • the material of the insulating layer 117 includes silicon nitride.
  • the second isolation layer 132 when there is a third isolation layer 112 between the sidewall of the semiconductor pillar 105 and the second isolation layer 132, when the second isolation layer 132 is patterned to form a groove, the depth corresponding to the depth of the groove Partial thickness of the second isolation layer 132 is removed, and the sidewall of the groove may also be formed by the remaining third isolation layer 112 .
  • forming the gap 153 may include the following steps:
  • the insulating layer 117 is used as a mask to remove the first isolation layer 102 and the second isolation layer 132 corresponding to the second doped region III; a dielectric layer 127 is formed, and the dielectric layer 127 surrounds the second doped region III sidewall and is located at the sidewall of the insulating layer 117, the sidewall of the dielectric layer 127 surrounds the through hole 163, the bottom of the through hole 163 exposes the first isolation layer 102, and the material of the dielectric layer 127 and the material of the insulating layer 117 are all isolated from the first isolation layer.
  • the material of layer 102 is different.
  • the material of the insulating layer 117 and the dielectric layer 127 can be silicon nitride
  • the material of the first isolation layer 102 and the material of the second isolation layer 132 can be silicon oxide, because compared with the same etching process, silicon nitride and oxide Silicon has a high etching selectivity ratio, and subsequently the first isolation layer 102 and the second isolation layer 132 can be etched using the structure jointly formed by the insulating layer 117 and the dielectric layer 127 as a mask to form the gap 153 .
  • the second isolation layer 132 and the first isolation layer 102 corresponding to the channel region II exposed by the via hole 163 (refer to FIG. 18) are removed to form a gap 153, and the second isolation layer 132 and the first isolation layer An isolation layer 102 surrounds sidewalls of the first doped region I together.
  • the through hole 163 exposes part of the top surface of the second isolation layer 132, the material of the second isolation layer 132, the material of the first isolation layer 102, and the material of the fourth isolation layer 122 are the same, and are the same as those of the insulating layer 117 and the dielectric layer. 127 are all different materials, then an etching solution can be injected into the through hole 163, and the second isolation layer 132, the first isolation layer 102 and the fourth isolation layer 122 surrounding the sidewall of the channel region II are removed by a wet etching process. , the second isolation layer 132 , the first isolation layer 102 and the fourth isolation layer 122 surrounding the sidewall of the first doped region I remain.
  • the insulating layer 117 and the dielectric layer 127 together form a supporting frame, the supporting frame is in contact with the second doped region III, and part of the supporting frame is embedded in the second isolation layer 132 .
  • the support frame has the function of supporting and fixing the semiconductor column 105, and when the etching liquid flows, it generates a squeezing force on the semiconductor column 105, which is beneficial to avoid the extrusion of the semiconductor column 105. Tilt or offset to improve the stability of the semiconductor structure; the supporting frame wraps the sidewall of the second doped region III, which is beneficial to avoid the etching solution from damaging the second doped region III.
  • forming the gap 153 may include the following steps: using the insulating layer 117 as a mask to remove the first isolation layer 102 and the second isolation layer 132 corresponding to the second doped region III and the channel region II, to form The gap 153, the remaining second isolation layer 132 and the first isolation layer 102 surround the sidewall of the first doped region I together. It should be noted that, in some embodiments, there is a fourth isolation layer 122 between the sidewall of the semiconductor pillar 105 and the second isolation layer 132, and the second isolation layer 132 and the first isolation layer corresponding to the channel region II are removed. layer 102, the fourth isolation layer 122 corresponding to the channel region II is also removed.
  • the gate dielectric layer 118 is located at least on the sidewall of the exposed channel region II, and there is a second gap between the gate dielectric layer 118 and the insulating layer 117 .
  • the method for forming the gate dielectric layer 118 includes performing thermal oxidation treatment on the exposed semiconductor pillars 105 . It should be noted that, in some embodiments, when only the first isolation layer 102 and the second isolation layer 132 corresponding to the channel region II are removed by using the insulating layer 117 as a mask, the gate dielectric layer 118 is only exposed around In other embodiments, when the insulating layer 117 is used as a mask to remove the first isolation layer 102 and the second isolation layer corresponding to the second doped region III and the channel region II layer 132, the gate dielectric layer 118 is located on the sidewalls of the second doped region III and the channel region II, and may also be located on the top surface of the second doped region III, the top surface of the second doped region III is exposed and not on the When the top surface of the second doped region III is protected by a mask, during the thermal oxidation process, a part of the second doped region III close to the top surface is also converted into silicon oxide, which can be subsequently removed
  • the step of forming the gate dielectric layer 118 includes: performing thermal oxidation treatment on the exposed sidewall of the channel region II to form the gate dielectric layer 118, and the gate dielectric layer 118 Covering the sidewall surfaces of the remaining channel region II.
  • the material of the gate dielectric layer 118 is silicon oxide.
  • the gate dielectric layer 118 covering the sidewall surface of the channel region may also be formed by a deposition process.
  • the orthographic projection of the channel region II on the bit line 114 is smaller than that of the second doped region
  • the orthographic projection of III on the bit line 114 is smaller than the orthographic projection of the first doped region I on the bit line 114, which is conducive to forming a semiconductor column 105 perpendicular to the bit line 114 and pointing to the semiconductor column 105 without using an etching process.
  • the channel region II with a smaller cross-sectional area is beneficial to improve the ability of the subsequently formed word line to control the channel region II, so that it is easier to control the turn-on or turn-off of the GAA transistor.
  • the orthographic projection of the periphery of the gate dielectric layer 118 on the bit line 114 is smaller than the orthographic projection of the periphery of the dielectric layer 127 on the bit line 114, that is, the gate dielectric layer 118 is farther away from the outer wall of the semiconductor pillar 105 than the dielectric layer 127 is farther away from the semiconductor pillar 105
  • the outer wall is closer to the semiconductor pillar 105, thereby ensuring a second gap between the gate dielectric layer 118 and the dielectric layer 127, so that subsequent word lines can surround the gate dielectric layer 118 located on the sidewall of the channel region II.
  • the gate dielectric layer 118 may be closer to the semiconductor pillar 105 than the first isolation layer 102 is farther from the outer wall of the semiconductor pillar 105 than the outer wall of the semiconductor pillar 105 .
  • the word line 128 fills the second gap, and the word line 128 is only located on the sidewall surface of the gate dielectric layer 118 corresponding to the channel region II.
  • the word line 128 may be a single-layer structure; in other embodiments, the word line may be a stacked structure.
  • the first word line is formed on part of the gate dielectric layer 118, and the first word line is also located on the top surface of the remaining isolation layer; the second word line is formed on the remaining gate dielectric layer 118, and the function of the second word line is The function value is different from the work function value of the first word line, and the first word line and the second word line are stacked in the direction Z.
  • the step of forming the first word line may include: forming an initial word line, and the initial word line fills the gap surrounded by the gate dielectric layer 118 and the insulating layer 117; removing a part of the thickness of the initial word line, and the remaining initial word line is used as the first word line .
  • the initial word line can be formed by a deposition process, and the material of the initial word line includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, cobalt, aluminum, lanthanum, copper or tungsten.
  • the initial word line is self-aligned to fill the gap surrounded by the gate dielectric layer 118 and the insulating layer 117, which is conducive to the self-aligned formation of the first word line with precise dimensions, and the size of the first word line does not need to be designed through an etching process , which is beneficial to simplify the steps of forming the first word line, and by adjusting the size of the gap, the first word line with a small size can be obtained.
  • the steps of forming the second word line are the same as the steps of forming the first word line, and will not be repeated here.
  • the second word line and the first word line together form word line 128 .
  • the size ratio of the word line reduces the work function value of the word line 128 to reduce the difference between the work function value of the word line 128 and the work function value of the semiconductor layer 101, which is beneficial to reduce the corresponding position between the word line 128 and the semiconductor layer 101.
  • the lateral electric field reduces the GIDL, which is beneficial to increase the on/off ratio of the channel region II, so as to improve the sensitivity of controlling the on/off of the channel region II; it is beneficial to reduce the threshold voltage of the transistor at the same time, through Regulating the relevant parameters of the first word line and the second word line makes the word line 128 suitable for different types of transistors, which is beneficial to reduce the manufacturing process and lower the manufacturing cost of the semiconductor structure.
  • the word line 128 includes two conductive layers with different work function values. In practical applications, there is no limit to the number of conductive layers with different work function values included in the word line.
  • a barrier layer 109 is also formed.
  • the barrier layer 109 fills the gap surrounded by the dielectric layer 127 and is located on the top of the semiconductor pillar 105, the insulating layer 117 and the dielectric layer 127. noodle.
  • the material of the barrier layer 109 includes silicon oxide, silicon nitride or silicon oxynitride.
  • the first isolation layer 102 of the partial thickness of the sidewall of the initial bit line 104 is removed to form a third trench 133 between adjacent initial bit lines 104, so that in the direction perpendicular to the sidewall of the semiconductor pillar 105, the third trench
  • the width of 133 is greater than the width of the second trench 123, so when the second isolation layer 132 is subsequently formed, the region corresponding to the third trench 133 in the second isolation layer 132 has a gap 143, and the space between adjacent initial bit lines 104 Insulation is realized by the isolation structure comprising the second isolation layer 132 and the gap 143, because the relative dielectric constant of the air in the gap 143 is much smaller than that of the second isolation layer 132, that is, the insulation of the air is better than that of the second isolation layer
  • the insulation of 132 is beneficial to reduce the parasitic capacitance between adjacent initial bit lines 104 and reduce the influence between semiconductor pillars 105 electrically connected to different initial bit lines 104, so as to improve the overall electrical performance of the semiconductor structure.
  • Another exemplary embodiment of the present disclosure also provides a semiconductor structure formed by the manufacturing method provided in the above-mentioned embodiments.
  • a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • the semiconductor structure includes: a substrate 100, the substrate 100 includes a plurality of semiconductor layers 101 arranged at intervals and a first isolation layer 102 between adjacent semiconductor layers 101, the semiconductor layer 101 includes X-extended bit line 114 and semiconductor column 105 on the top surface of bit line 114, the first isolation layer 102 is located on the side wall of the end of semiconductor column 105 close to bit line 114 and between adjacent bit lines 114, and is located on adjacent There is a third trench between the first isolation layer 102 between the bit lines 114 and the first isolation layer 102 located on the sidewall of the semiconductor pillar 105, and the third trench is arranged at intervals along the second direction Y, and the second direction Y is in line with the The first direction X is different; the second isolation layer 132 is located on the side wall of the end of the semiconductor pillar 105 close to the bit line 114 and the surface of the bit line 114 exposed by the third trench, and is located on the second isolation layer in the third trench. Layer 132 has voids 143 within it
  • the semiconductor structure may further include: a fourth isolation layer 122 located between the sidewall of the first doped region I and the second isolation layer 132 .
  • the semiconductor structure may further include: a dielectric layer 127 surrounding the sidewall of the second doped region III and located on the sidewall of the insulating layer 117 .
  • the semiconductor structure may further include: a barrier layer 109 , which fills the gap surrounded by the dielectric layer 127 and is located on the top surface jointly formed by the semiconductor pillar 105 , the insulating layer 117 and the dielectric layer 127 .
  • the dielectric layer 127 and the barrier layer 109 are formed in different steps, and the material of the dielectric layer 127 and the material of the barrier layer 109 are different; in other embodiments, the dielectric layer 127 and the barrier layer The layer 109 can be formed in the same process step, so the material of the dielectric layer 127 and the material of the barrier layer 109 are the same.
  • the material of the bit line 114 may include a metal semiconductor compound 124 .
  • the metal-semiconductor compound 124 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide.
  • the metal-semiconductor compound 124 has a relatively lower resistivity than an unmetallized semiconductor material, and the resistivity of the bitline 114 including the metal-semiconductor compound 124 is lower than that of an unmetallized bitline. Smaller, it is beneficial to reduce the resistance of the bit line 114 itself, and reduce the contact resistance between the bit line 114 and the first doped region I, and further improve the electrical performance of the semiconductor structure.
  • the semiconductor structure may further include: a gate dielectric layer 118 surrounding at least the sidewall of the remaining semiconductor pillar 105 close to the partial thickness of the second isolation layer 132; a word line 128 surrounding the gate dielectric layer 118 away from the semiconductor pillar 105 sidewall surface, and the word lines 128 extend along the second direction Y, and there are gaps between adjacent word lines 128; the insulating layer 117 at least fills up the gaps.
  • the second isolation layer 132 has a void 143 in a region corresponding to the third trench. Because the relative permittivity of the air in the gap 143 is much smaller than the relative permittivity of the second isolation layer 132, that is, the insulation of the air is better than that of the second isolation layer 132, which is beneficial to reduce the distance between adjacent bit lines 114.
  • the parasitic capacitance reduces the influence between the semiconductor pillars 105 electrically connected to different bit lines 114, so as to improve the overall electrical performance of the semiconductor structure.
  • the first isolation layer with a partial thickness of the sidewall of the initial bit line is removed to form a third trench between adjacent initial bit lines, so that the direction, the width of the third trench is larger than the width of the second trench, so when the second isolation layer is subsequently formed, the area corresponding to the third trench in the second isolation layer has a gap, and the gap between the adjacent initial bit lines Insulation is realized by the isolation structure comprising the second isolation layer and the void, because the relative permittivity of the air in the void is much smaller than that of the second isolation layer, that is, the insulation of the air is better than that of the second isolation layer, It is beneficial to reduce the parasitic capacitance between adjacent initial bit lines, and reduce the influence between semiconductor pillars electrically connected to different initial bit lines, so as to improve the overall electrical performance of the semiconductor structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

本公开实施例公布了一种半导体结构及其制造方法，涉及半导体领域，半导体结构的制造方法包括：提供基底；在基底内形成多条沿第一方向延伸的第一沟槽，第一沟槽将基底形成间隔排布的半导体层，并在第一沟槽内填充第一隔离层；在半导体层和第一隔离层内形成多条沿第二方向延伸的第二沟槽，第二沟槽的深度小于第一沟槽的深度，以将半导体层形成多个分立的半导体柱和位于半导体柱下方的初始位线；在低于第二沟槽的位置形成平行于第一沟槽的第三沟槽，在垂直于半导体柱侧壁的方向上，第三沟槽的宽度大于第二沟槽的宽度；在第二沟槽和第三沟槽内填充第二隔离层，其中，第三沟槽内的第二隔离层内具有空隙。

Description

半导体结构及其制造方法
本公开基于申请号为202210016563.4、申请日为2022年01月07日、申请名称为“半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及但不限于一种半导体结构及其制造方法。
背景技术
随着动态存储器的集成密度朝着更高的方向发展，在对动态存储器阵列结构中晶体管的排布方式以及如何缩小动态存储器阵列结构中单个功能器件的尺寸进行研究的同时，也需要提高小尺寸的功能器件的电学性能。
利用垂直的全环绕栅极(GAA，Gate-All-Around)晶体管结构作为动态存储器选择晶体管(access transistor)时，其占据的面积可以达到4F2(F：在给定工艺条件下可获得的最小图案尺寸)，原则上可以实现更高的密度效率，但是由于相邻位线之间间距的减小，相邻位线间的隔离层的尺寸也减小，相邻位线间的耦合电容对半导体结构电学性能的影响增大。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体结构及其制造方法。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制造方法，包括：提供基底；在所述基底内形成多条沿第一方向延伸的第一沟槽，所述第一沟槽将所述基底形成间隔排布的半导体层，并在所述第一沟槽内填充第一隔离层；在所述半导体层和所述第一隔离层内形成多条沿第二方向延伸的第二沟槽，所述第二沟槽的深度小于所述第一沟槽的深度，以将所述半导体层形成多个分立的半导体柱和位于所述半导体柱下方的初始位线；在低于所述第二沟槽的位置形成平行于所述第一沟槽的第三沟槽，在垂直于所述半导体柱侧壁的方向上，所述第三沟槽的宽度大于所述第二沟槽的宽度；在所述第二沟槽和所述第三沟槽内填充第二隔离层，其中，所述第三沟槽内的所述第二隔离层内具有空隙。
在一些实施例中，在垂直于所述半导体柱侧壁的方向上，所述第一沟槽的宽度大于等于所述第二沟槽的宽度。
在一些实施例中，在低于所述第二沟槽的位置形成平行于所述第一沟槽的所述第三沟槽的步骤包括：形成保护层，所述保护层位于所述第二沟槽的侧壁上，且露出所述初始位线顶面和相邻所述初始位线间的所述第一隔离层的顶面；以所述保护层为掩膜去除位于所述初始位线侧壁的部分厚度的所述第一隔离层，以形成所述第三沟槽；去除所述保护层。
在一些实施例中，在形成所述保护层之前，还包括：形成第三隔离层，所述第三隔离层仅位于所述沟槽暴露出的侧壁表面。
在一些实施例中，在同一刻蚀工艺下，所述第一隔离层和所述保护层之间的刻蚀选择比大于等于50。
在一些实施例中，在形成所述第三沟槽之后，形成所述第二隔离层之前，还包括：在所述第三沟槽暴露出的所述初始位线的表面形成第四隔离层，且所述第四隔离层不改变所述第三沟槽的整体形貌。
在一些实施例中，在形成所述第四隔离层之后，形成所述第二隔离层之前，还包括：去除位于所述初始位线顶面的所述第四隔离层；对暴露出的所述初始位线进行金属硅化处理，以形成位线，所述位线的材料包括金属半导体化合物。
在一些实施例中，在所述半导体柱指向所述位线的方向上，所述第三沟槽的深度大于所述金属半导体化合物的深度。
在一些实施例中，所述制造方法还包括：去除所述第二沟槽内部分厚度的所述第二隔离层以形成凹槽，所述凹槽沿所述第二方向延伸；形成填充满所述凹槽的绝缘层；以所述绝缘层为掩膜去除部分厚度的所述半导体柱侧壁的所述第一隔离层和所述第二隔离层，以在所述半导体柱和所述绝缘层之间 形成间隙；在垂直于所述第二沟槽侧壁的方向上，在所述间隙中依次堆叠形成栅介质层和字线。
在一些实施例中，沿所述初始位线指向所述半导体柱的方向上，所述半导体柱包括依次排列的第一掺杂区、沟道区以及第二掺杂区；形成所述凹槽的方法包括图形化处理，且所述凹槽的侧壁由剩余所述第二隔离层构成，在所述第一掺杂区指向所述沟道区的方向上，所述凹槽的深度大于等于所述沟道区的高度和所述第二掺杂区的高度之和。
在一些实施例中，形成所述间隙的步骤包括：以所述绝缘层为掩膜去除与所述第二掺杂区对应的所述第一隔离层和所述第二隔离层；形成介质层，所述介质层环绕所述第二掺杂区侧壁且位于所述绝缘层侧壁，所述介质层侧壁围成通孔，所述通孔底部露出所述第一隔离层，且所述介质层的材料和所述绝缘层的材料均与所述第一隔离层的材料不同；去除所述通孔露出的与所述沟道区对应的所述第二隔离层和所述第一隔离层，以形成所述间隙，剩余所述第二隔离层和所述第一隔离层共同环绕所述第一掺杂区侧壁。
在一些实施例中，形成所述间隙的步骤包括：以所述绝缘层为掩膜去除与所述第二掺杂区和所述沟道区对应的所述第一隔离层和所述第二隔离层，以形成所述间隙，剩余所述第二隔离层和所述第一隔离层共同环绕所述第一掺杂区侧壁。
在一些实施例中，所述栅介质层至少位于暴露出的所述沟道区的侧壁，且所述栅介质层和所述绝缘层之间具有第二间隙。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，包括：基底，所述基底包括多个间隔排布的半导体层以及位于相邻所述半导体层之间的第一隔离层，所述半导体层包括沿第一方向延伸的位线和位于所述位线顶面的半导体柱，所述第一隔离层位于所述半导体柱靠近所述位线的一端的侧壁和位于相邻所述位线之间，且位于相邻所述位线之间的所述第一隔离层与位于所述半导体柱侧壁的所述第一隔离层之间具有第三沟槽，且所述第三沟槽沿第二方向间隔设置，所述第二方向与所述第一方向不同；第二隔离层，位于所述半导体柱靠近所述位线的一端的侧壁上和所述第三沟槽暴露出的所述位线表面，且位于所述第三沟槽中的所述第二隔离层内具有空隙。
在一些实施例中，所述半导体结构还包括：栅介质层，至少环绕靠近所述第二隔离层的部分厚度的剩余所述半导体柱的侧壁；字线，环绕所述栅介质层远离所述半导体柱的侧壁表面，且所述字线沿所述第二方向延伸，相邻所述字线之间具有间隔；绝缘层，至少填充满所述间隔。
本公开实施例提供的技术方案至少具有以下优点：
上述技术方案中，去除初始位线侧壁的部分厚度的第一隔离层，以在相邻初始位线间形成第三沟槽，使得在垂直于半导体柱侧壁的方向上，第三沟槽的宽度大于第二沟槽的宽度，因此后续形成第二隔离层时，第二隔离层内与第三沟槽对应的区域具有空隙，则相邻初始位线之间由包括第二隔离层和空隙的隔离结构实现绝缘，由于空隙中空气的相对介电常数远小于第二隔离层的相对介电常数，即空气的绝缘性优于第二隔离层的绝缘性，有利于降低相邻初始位线之间的寄生电容，降低与不同初始位线电连接的半导体柱之间的影响，以提高半导体结构整体的电学性能。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1至图24为本公开一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。
附图标记说明：
100、基底；101、半导体层；113、第一沟槽；102、第一隔离层；104、初始位线；105、半导体柱；123、第二沟槽；133、第三沟槽；132、第二隔离层；112、第三隔离层；109、阻挡层；114、位线；115、多晶硅层；117、绝缘层；118、栅介质层；122、第四隔离层；124、金属半导体化合物；125、保护层；127、介质层；128、字线；143、空隙；153、间隙；163、通孔；I、第一掺杂区；II、沟道区；III、第二掺杂区。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开实施提供一种半导体结构及其制造方法，制造方法中，预先在相邻初始位线间形成第三沟槽，使得后续形成第二隔离层时，第二隔离层内与第三沟槽对应的区域具有空隙，由于空隙中空气的相对介电常数远小于第二隔离层的相对介电常数，有利于降低相邻初始位线之间的寄生电容，降低与不同初始位线电连接的半导体柱之间的影响，以提高半导体结构整体的电学性能。
本公开一实施例提供一种半导体结构的制造方法，以下将结合附图对本公开一实施例提供的半导体结构的制造方法进行详细说明。图1至图24为本公开一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。需要说明的是，为了便于描述以及清晰地示意出半导体结构制作方法的步骤，本实施例中的图1至图24均为半导体结构的局部结构示意图。
其中，图4为图3所示结构的俯视图，图5为图4所示结构沿第一截面方向AA1的剖面示意图，图6和图7为后续形成的中间结构沿第一截面方向AA1的剖面示意图，图8为后续形成的中间结构沿第二截面方向BB1的剖面示意图，图9为后续形成的中间结构沿第三截面方向CC1的剖面示意图，需要说明的是，后续将根据表述需要设置沿第一截面方向AA1的剖面示意图、沿第二截面方向BB1的剖面示意图以及沿第三截面方向CC1的剖面示意图中的一者、两者或者三者。
参考图1和图2，提供基底100；在基底100内形成多条沿第一方向X延伸的第一沟槽113，第一沟槽113将基底100形成间隔排布的半导体层101；并在第一沟槽113内填充第一隔离层102。
在一些实施例中，提供基底100包括如下步骤：
提供初始基底，初始基底的材料类型可以为元素半导体材料或者晶态无机化合物半导体材料。元素半导体材料可以硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者镓化铟等。
对初始基底进行掺杂处理以及退火处理，使得初始基底内掺杂有N型离子或P型离子，用于后续在初始基底的基础上形成初始位线和半导体柱。N型离子可以为砷离子、磷离子或者锑离子中的至少一种；P型离子可以为硼离子、铟离子或者镓离子中的至少一种。
参考图1，在初始基底上形成第一掩膜层(图中未示出)，第一掩膜层具有多个相互分立的第一开口，第一开口沿第一方向X延伸，第一开口的长度与后续形成的初始位线104的长度一致。
以第一掩膜层为掩膜刻蚀初始基底，形成多个第一沟槽113。
参考图2，去除第一掩膜层进行沉积工艺，形成覆盖初始基底顶面以及填充满第一沟槽113的第一隔离膜；对第一隔离膜进行化学机械平坦化处理至露出初始基底顶面，以形成第一隔离层102。
参考图3至图5，在半导体层101和第一隔离层102内形成多条沿第二方向Y延伸的第二沟槽123，第二沟槽123的深度小于第一沟槽113的深度，以将半导体层101形成多个分立的半导体柱105和位于半导体柱105下方的初始位线104。
继续参考图3至图5，在一些实施例中，形成半导体柱105和初始位线104包括如下步骤：
在第一隔离层102和剩余初始基底共同构成的顶面上形成第二掩膜层(图中未示出)，第二掩膜层具有多个相互分立的第二开口，第二开口沿第二方向Y延伸，第二开口的长度与后续形成的字线的长度一致。
以第二掩膜层为掩膜刻蚀初始基底和第一隔离层102，需要说明的是，形成半导体柱105和初始位线104之后，第一隔离层102不仅位于相邻初始位线104的间隔中，而且位于相邻半导体柱105的间隔中。
在方向Z上，第二沟槽123的深度小于第一沟槽113(参考图1)的深度，有利于在形成初始位线104的同时，在初始位线104的一侧形成多个相互分立的半导体柱105，且初始位线104与半导体柱105的第一掺杂区I相接触；去除第二掩膜层。
在垂直于半导体柱105侧壁的方向上，即在图3中的方向X上，第一沟槽113的宽度大于等于第二沟槽123(参考图4)的宽度。有利于保证后续形成第三沟槽133(参考图8)时，第二沟槽123的开口始终小于第三沟槽133的开口，从而在后续形成第二隔离层132(参考图14)时，在第三沟槽133的对应区域形成具有空隙的第二隔离层132。在一些例子中，第一沟槽113的宽度与第二沟槽123的宽度的比值可以为1.5～2。
形成初始位线104、半导体柱105和第一隔离层102的方法包括自对准多重曝光技术(SAQP，Self-Aligned Quadruple Patterning)或者自对准双重成像技术(SADP，Self-aligned Double Patterning)。
参考图3和图5，第二沟槽123沿第一方向X间隔设置；在沿第二沟槽123底部指向第二沟槽123顶部的方向Z上，半导体层101包括依次排列的初始位线104和半导体柱105，且半导体柱105包括依次排列的第一掺杂区I、沟道区II以及第二掺杂区III。需要说明的是，第一掺杂区I和第二掺杂区III均可以作为后续形成的具有半导体层101的GAA晶体管的源极或者漏极，沟道区II与GAA晶体管的栅介质层和字线对应。在一些实施例中，初始位线104为后续进行金属硅化处理以形成位线做准备。
参考图3和图4，在一些实施例中，第一方向X垂直于第二方向Y，使得形成的半导体层101呈现4F2(F：在给定工艺条件下可获得的最小图案尺寸)的排布方式，有利于提高半导体结构的集成密度。在其他实施例中，第一方向与第二方向相交，两者之间的夹角例如可以为80°、85°、100°、120°。
需要说明的是，在半导体层101中具有多个间隔排布的初始位线104，且每一初始位线104可与至少一个第一掺杂区I相接触，图1中以4个相互间隔的初始位线104，以及每一初始位线104与4个第一掺杂区I相接触作为示例，实际应用中，可根据实际电学需求，合理设置初始位线104的数量以及与每一初始位线104相接触的第一掺杂区I的数量。
半导体柱105构成的器件可以为无结晶体管，即第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子的类型相同。“无结”指的是无PN结，即第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子的掺杂浓度相同，这样的好处包括：一方面，无需对第一掺杂区I和第二掺杂区III进行额外的掺杂，从而避免了对第一掺杂区I和第二掺杂区III的掺杂工艺难以控制的问题，尤其是随着晶体管尺寸进一步缩小，若额外对第一掺杂区I和第二掺杂区III进行掺杂，掺杂浓度更加难以控制；另一方面，由于器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，在纳米尺度范围内制作超陡峭PN结的现象，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，还有利于抑制短沟道效应，因而有助于进一步提高半导体结构的集成密度和电学性能。可以理解的是，此处额外的掺杂指的是，为了让第一掺杂区I和第二掺杂区III的掺杂离子类型与沟道区II的掺杂离子类型不同而进行的掺杂。
请返回参考图1至图5，本实施例中，初始位线104和半导体层101均是通过刻蚀初始基底形成的，即初始位线104和半导体层101利用同一膜层结构形成，使得初始位线104和半导体层101为一体结构，从而改善初始位线104和半导体层101之间的界面态缺陷，改善半导体结构的性能。
参考图1至图5，在一些实施例中，在半导体柱105远离初始位线104的顶面还具有多晶硅层115；在其他实施例中，半导体柱105的顶面可以不具有多晶硅层，即半导体柱105的顶面也可以暴露在外。
参考图3、图6至图9，在低于第二沟槽123的位置形成平行于第一沟槽113(参考图1)的第三沟槽133，在垂直于半导体柱105侧壁的方向上，即在图3中的方向X上，第三沟槽133的宽度大于第二沟槽123的宽度。有利于后续在第二沟槽123和第三沟槽133内填充形成第二隔离层132(参考图14)时，在第二隔离层132内与第三沟槽133对应的区域形成空隙。
在一些实施例中，在低于第二沟槽123的位置形成平行于第一沟槽113的第三沟槽133包括如下步骤：
参考图6，形成保护层125，保护层125位于第二沟槽123的侧壁上，且露出初始位线104顶面和相邻初始位线104间的第一隔离层102的顶面。需要说明的是，当半导体柱105的顶面具有多晶硅层115时，保护层125还可以位于多晶硅层115的侧壁。
需要说明的是，在一些实施例中，参考图6，保护层125位于第二沟槽123的侧壁表面上。可采用以下工艺步骤形成保护层125：进行沉积工艺，形成覆盖第二沟槽123侧壁和底部以及半导体柱105顶面的保护膜；对保护膜进行刻蚀处理，例如垂直干法刻蚀，以露出第二沟槽123的部分底面，即露 出初始位线104的部分顶面，剩余保护膜作为保护层125。保护膜的材料包括氮化硅。
在另一些实施例中，参考图7，在形成保护层125之前，还可以包括：形成第三隔离层112，第三隔离层112仅位于第二沟槽123暴露出的侧壁表面。可采用以下工艺步骤形成第三隔离层112和保护层125：先在半导体柱105的侧壁表面形成第三隔离层112，然后进行沉积工艺，形成覆盖第三隔离层112表面、第二沟槽123底面以及半导体柱105顶面的保护膜；对保护膜进行刻蚀处理，例如垂直干法刻蚀，以露出第二沟槽123的部分底面，即露出初始位线104和第一隔离层102的部分顶面，剩余保护膜作为保护层125。保护膜的材料包括氮化硅，第三隔离层112的材料包括氧化硅。在后续需要对初始位线104进行金属硅化处理时，第三隔离层112可以用于保护半导体柱105，避免半导体柱105被金属硅化处理。
上述两种实施例中，结合参考图6和图8至图9，或者结合参考图7至图9，以保护层125为掩膜去除位于初始位线104侧壁的部分厚度的第一隔离层102，以在相邻初始位线104间形成第三沟槽133，为后续在相邻初始位线104之间形成空隙做准备。由于保护层125的材料与第一隔离层102的材料不同，可以采用湿法刻蚀工艺，以保护层125露出的第一隔离层102的部分顶面为起点，去除位于初始位线104侧壁的部分厚度的第一隔离层102。
在同一刻蚀工艺下，第一隔离层102和保护层125之间的刻蚀选择比可以大于等于50，例如60、70、100，或者不发生刻蚀，有利于在去除位于初始位线104侧壁的部分厚度的第一隔离层102时，保护层125以及保护层125覆盖的结构刻蚀较少或者不会被刻蚀。
例如可以去除保护层125。需要说明的是，去除保护层125的步骤中，也可以将多晶硅层115去除。当半导体柱105侧壁与保护层125之间具有第三隔离层112时，在一些实施例中，可以在去除保护层125的步骤中将第三隔离层112一并去除；在其他实施例中，可以在后续对初始位线104进行金属硅化处理的步骤之后再去除，从而在对初始位线进行金属硅化处理时，利用第三隔离层112保护半导体柱105。
在垂直于半导体柱105侧壁的方向上，第三沟槽133的宽度大于第二沟槽123的宽度。当第三沟槽133的宽度大于第二沟槽123的宽度时，第二沟槽123的宽度较窄，有利于在后续形成第二隔离层132(参考图14)的步骤中，第二隔离层132在未将第三沟槽133填充满时，已经封口，使得第二隔离层132内与第三沟槽133对应的区域具有空隙。形成的第三沟槽133的宽度与第二沟槽123的宽度的比值可以为1.1～4，例如1.5、2、3.5、4。
在一些实施例中，在形成第三沟槽133之后，在后续形成第二隔离层132之前，制造方法还可以包括如下步骤：
参考图10至图12，在形成第三沟槽133之后，在第三沟槽133暴露出的半导体层101的表面形成第四隔离层122，且第四隔离层122不改变第三沟槽133的整体相貌。
需要说明的是，在形成第三沟槽133之后，保护层125和多晶硅层115被去除，在一些实施例中，在图12至图14所示的形成第四隔离层122的步骤中，第三隔离层112也已经被去除，即第四隔离层122不仅环绕初始位线104暴露出的侧壁表面，而且位于半导体柱105的顶面和部分暴露出的侧壁；在其他实施例中，当第三隔离层没有被去除时，第四隔离层环绕初始位线暴露出的侧壁表面，以及位于半导体柱的顶面。
上述两种实施例中，第四隔离层122均可以通过对半导体层101暴露出的表面进行热氧化处理来形成。第四隔离层122均用于在对初始位线104的顶面进行金属硅化处理时，保护半导体层101的其他部分，避免半导体层101的其他部分受金属硅化处理的影响。避免半导体层101的其他部分被金属硅化处理；避免后续相邻半导体层101之间除了绝缘材料，还具有金属材料，避免相邻半导体层101之间产生过大的寄生电容，降低半导体结构的电学性能。半导体层101的材料可以为硅，则第四隔离层122的材料可以为氧化硅。
在一些实施例中，在形成第四隔离层122之后，在后续形成第二隔离层132之前，制造方法还可以包括如下步骤：
参考图13，去除位于初始位线104(参考图10)顶面的第四隔离层122。需要说明的是，在一些实施例中，去除位于初始位线104顶面的第四隔离层122的步骤中，也将位于半导体柱105顶面的第 四隔离层122去除；在其他实施例中，也可以保留位于半导体柱顶面的第四隔离层122。
继续参考图10以及图13，对暴露出的初始位线104进行金属硅化处理，以形成位线114，位线114的材料包括金属半导体化合物124。
在一些实施例中，金属硅化处理包括：在第四隔离层122上、初始位线104的部分顶面以及第一隔离层102的部分顶面上形成金属层(图中未示出)；进行退火处理，以使金属层与初始位线104进行反应，以形成位线114；去除未发生反应的剩余金属层。
在另一些实施例中，金属硅化处理包括：初始位线104露出的顶面定向地掺杂金属元素，然后进行退火，有利于避免在其他地方形成金属半导体化合物124而需要移除的情况。
在一些实施例中，在半导体柱105指向位线114的方向上，第三沟槽133的深度大于金属半导体化合物124的深度。
需要说明的是，在一些实施例中，位于第一掺杂区I正下方的初始位线104的区域的材料为半导体材料，且未被第一掺杂区I覆盖的初始位线104的部分区域的材料为金属半导体化合物。可以理解的是，随着器件尺寸的不断缩小或者制造工艺参数的调整，位于第一掺杂区I正下方的初始位线104的部分区域的材料为半导体材料，位于第一掺杂区I正下方的初始位线104的其余区域的材料也可以为金属半导体化合物，此处的“其余区域”的位置位于“部分区域”的外围。
参考图13，半导体层101中的多个金属半导体化合物124之间相互连通形成位线114的一部分；在其他实施例中，同一位线中的多个金属半导体化合物之间也可以相互间隔。需要说明的是，图13中以与椭圆形相似的虚线框所限定的半导体层101的区域为金属半导体化合物124，且在实际应用中，对相邻金属半导体化合物124之间相互接触的区域的大小不做限制。在其他实施例中，全部厚度的初始位线104可以转化为金属半导体化合物124。
在其他实施例中，当第二掺杂区III的顶面暴露在外，且没有被研磨层保护时，制造方法还可以包括：对第二掺杂区III顶面进行金属硅化处理，如此，有利于后续在第二掺杂区III顶面要形成电容结构的下电极时，第二掺杂区III与下电极构成欧姆接触，避免下电极与半导体材料直接接触而形成肖特基势垒接触，欧姆接触有利于降低第二掺杂区III与下电极之间的接触电阻，从而降低半导体结构工作时的能耗，且改善RC延迟效应，以提高半导体结构的电学性能。可以在同一工艺步骤中进行对初始位线104顶面和第二掺杂区III顶面的金属硅化处理，有利于简化工艺步骤。在其他实施例中，对初始位线104顶面和第二掺杂区III顶面的金属硅化处理也可以分步进行。
上述实施例中，以半导体层101的材料为硅为例，金属层的材料或者定向掺杂的金属元素可以包括钴、镍、钼、钛、钨、钽或者铂中的至少一种，则金属半导体化合物124包括硅化钴、硅化镍、硅化钼、硅化钛、硅化钨、硅化钽或者硅化铂中的至少一种。金属半导体化合物124相较于未金属化的半导体材料而言，具有相对更小的电阻率，相较于未被金属化处理的初始位线104而言，位线114的电阻率更小，从而有利于降低位线114自身的电阻，且降低位线114与第一掺杂区I之间的接触电阻，进一步改善半导体结构的电学性能。
参考图14至图16，在第二沟槽123(参考图3)和第三沟槽133(参考图8)内填充第二隔离层132，其中，第三沟槽133内的第二隔离层132内具有空隙143。其中，形成具有空隙143的第二隔离层132的方法包括沉积工艺。由于在垂直于半导体柱105侧壁的方向上，即方向X上，第三沟槽133的宽度大于第二沟槽123的宽度，因而，在沉积形成第二隔离层132的步骤中，用于形成第二隔离层132的沉积材料会在未完全填充满第三沟槽133时，在空隙143的上方就形成了封口，从而在第二隔离层132内形成空隙143。由于空隙143中空气的相对介电常数远小于第二隔离层132的相对介电常数，即空气的绝缘性优于第二隔离层132的绝缘性，有利于降低相邻位线114之间的寄生电容，降低与不同位线114电连接的半导体柱105之间的影响，以提高半导体结构整体的电学性能。
在一些实施例中，参考图17至图20，制造方法还可以包括：去除第二沟槽123(参考图3)内部分厚度的第二隔离层132以形成凹槽(图中未示出)，凹槽沿第二方向Y延伸；形成填充满凹槽的绝缘层117；以绝缘层117为掩膜去除部分厚度的半导体柱105侧壁的第一隔离层102和第二隔离层132，以在半导体柱105和绝缘层117之间形成间隙153。
后续在间隙153的基础上形成栅介质层和字线，则可以通过自对准的方式在空隙143中形成尺寸 精确的栅介质层和字线，无需通过刻蚀工艺即可形成高尺寸精度的栅介质层和字线，有利于简化栅介质层和字线的形成步骤，且通过调控空隙143的尺寸，即可获得小尺寸的栅介质层和字线。
形成凹槽的方法包括图形化处理，且凹槽的侧壁由剩余第二隔离层132构成，在第一掺杂区I指向沟道区II的方向上，凹槽的深度大于等于沟道区II的高度和第二掺杂区III的高度之和，即绝缘层117靠近位线114的底面不高于第一掺杂区I远离位线114的顶面。需要说明的是，在实际应用中，绝缘层117的深度最大可以等于半导体柱105的深度。绝缘层117的材料包括氮化硅。
在其他实施例中，当半导体柱105的侧壁与第二隔离层132之间还具有第三隔离层112时，图形化第二隔离层132形成凹槽时，与凹槽的深度对应的该部分厚度的第二隔离层132均被去除，则凹槽的侧壁也可以由剩余第三隔离层112构成。
在一些实施例中，形成间隙153可以包括如下步骤：
参考图17至图20，以绝缘层117为掩膜去除与第二掺杂区III对应的第一隔离层102和第二隔离层132；形成介质层127，介质层127环绕第二掺杂区III侧壁且位于绝缘层117侧壁，介质层127侧壁围成通孔163，通孔163底部露出第一隔离层102，且介质层127的材料和绝缘层117的材料均与第一隔离层102的材料不同。
绝缘层117和介质层127的材料均可以为氮化硅，第一隔离层102的材料和第二隔离层132的材料均可以为氧化硅，由于相对于同一刻蚀工艺，氮化硅和氧化硅之间具有高的刻蚀选择比，后续可以将绝缘层117和介质层127共同构成的结构作为掩膜刻蚀第一隔离层102和第二隔离层132以形成间隙153。
参考图19和图20，去除通孔163(参考图18)露出的与沟道区II对应的第二隔离层132和第一隔离层102，以形成间隙153，剩余第二隔离层132和第一隔离层102共同环绕第一掺杂区I侧壁。
需要说明的是，在一些实施例中，半导体柱105的侧壁和第二隔离层132之间还具有第四隔离层122，去除与沟道区II对应的第二隔离层132和第一隔离层102时，还去除了与沟道区II对应的第四隔离层122。
由于通孔163露出第二隔离层132的部分顶面，第二隔离层132的材料、第一隔离层102的材料以及第四隔离层122的材料相同，且与绝缘层117的材料和介质层127的材料均不同，则可以向通孔163中注入刻蚀液，通过湿法刻蚀工艺去除环绕沟道区II侧壁的第二隔离层132、第一隔离层102和第四隔离层122，保留环绕第一掺杂区I侧壁的第二隔离层132、第一隔离层102和第四隔离层122。
绝缘层117和介质层127共同组成支撑骨架，支撑骨架与第二掺杂区III相接触连接，且部分支撑骨架嵌入第二隔离层132中。在进行湿法刻蚀工艺的步骤中，支撑骨架有对半导体柱105起支撑固定的作用，当刻蚀液流动时产生对半导体柱105的挤压力，有利于避免半导体柱105受挤压发生倾斜或者偏移，以提高半导体结构的稳定性；支撑骨架包裹着第二掺杂区III侧壁，有利于避免刻蚀液对第二掺杂区III造成损伤。
在其他实施例中，形成间隙153可以包括如下步骤：以绝缘层117为掩膜去除与第二掺杂区III和沟道区II对应的第一隔离层102和第二隔离层132，以形成间隙153，剩余第二隔离层132和第一隔离层102共同环绕第一掺杂区I侧壁。需要说明的是，在一些实施例中，半导体柱105的侧壁和第二隔离层132之间还具有第四隔离层122，去除与沟道区II对应的第二隔离层132和第一隔离层102时，还去除了与沟道区II对应的第四隔离层122。
参考图21至图22，在形成间隙153(参考图20)之后，在垂直于第二沟槽123(参考图3)侧壁的方向上，即方向X上，在间隙153中依次堆叠形成栅介质层118和字线128。其中，栅介质层118至少位于暴露出的沟道区II的侧壁，且栅介质层118和绝缘层117之间具有第二间隙。
形成栅介质层118的方法包括对暴露的半导体柱105进行热氧化处理。需要说明的是，在一些实施例中，当以绝缘层117为掩膜去除的仅是与沟道区II对应的第一隔离层102和第二隔离层132时，栅介质层118仅环绕暴露出的沟道区II的侧壁；在其他实施例中，当以绝缘层117为掩膜去除的是与第二掺杂区III和沟道区II对应的第一隔离层102和第二隔离层132时，栅介质层118位于第二掺杂区III和沟道区II的侧壁，且还可以位于第二掺杂区III顶面，第二掺杂区III顶面暴露在外且未在第二掺杂区III顶面形成掩膜保护时，在热氧化处理的过程中，第二掺杂区III的靠近顶面的部分区域也转化 为氧化硅，后续可以通过刻蚀工艺去除。
在一些实施例中，由于半导体柱105的材料为硅，形成栅介质层118的步骤包括：对露出的沟道区II侧壁进行热氧化处理，以形成栅介质层118，且栅介质层118覆盖剩余沟道区II的侧壁表面。其中，栅介质层118的材料为氧化硅。在其他实施例中，也可以通过沉积工艺形成覆盖沟道区侧壁表面的栅介质层118。
由于对露出的沟道区II侧壁进行热氧化处理，则沟道区II的部分区域被转化为栅介质层118，使得沟道区II在位线114上的正投影小于第二掺杂区III在位线114上的正投影，且小于第一掺杂区I在位线114上的正投影，有利于在不采用刻蚀工艺的前提下，形成在垂直于位线114指向半导体柱105的方向Z的截面中，截面面积更加小的沟道区II，有利于提高后续形成的字线对沟道区II的控制能力，从而更容易控制GAA晶体管的导通或者关断。
栅介质层118的外围在位线114上的正投影小于介质层127的外围在位线114上的正投影，即栅介质层118远离半导体柱105的外壁相较于介质层127远离半导体柱105的外壁，更靠近半导体柱105，从而保证栅介质层118与介质层127之间具有第二间隙，使得后续字线能环绕位于沟道区II侧壁的栅介质层118。栅介质层118远离半导体柱105的外壁相较于第一隔离层102远离半导体柱105的外壁，也可以更靠近半导体柱105。字线128填充第二间隙，且字线128仅位于与沟道区II对应的栅介质层118的侧壁表面。
需要说明的是，在一些实施例中，字线128可以为单层结构；在其他实施例中，字线可以为叠层结构。
在一些实施例中，在部分栅介质层118上形成第一字线，第一字线还位于剩余隔离层顶面；在剩余栅介质层118上形成第二字线，第二字线的功函数值与第一字线的功函数值不同，且第一字线以及第二字线在方向Z上堆叠。形成第一字线的步骤可以包括：形成初始字线，初始字线填充满栅介质层118和绝缘层117围成的间隙；去除部分厚度的初始字线，剩余初始字线作为第一字线。可通过沉积工艺形成初始字线，初始字线的材料包括多晶硅、氮化钛、铝化钛、氮化钽、钽、钴、铝、镧、铜或者钨中的至少一种。
初始字线自对准地填充满栅介质层118和绝缘层117围成的间隙，有利于自对准地形成尺寸精确的第一字线，无需通过刻蚀工艺来设计第一字线的尺寸，有利于简化第一字线的形成步骤，且通过调控间隙的尺寸，即可获得小尺寸的第一字线。形成第二字线的步骤与形成第一字线的步骤相同，在此不做赘述。第二字线和第一字线共同构成字线128。
由于第二字线的功函数值与第一字线的功函数值不同，则通过调整第二字线的功函数值和第一字线的功函数值，以及第一字线相对于第二字线的尺寸比例，降低字线128的功函数值，以降低字线128的功函数值与半导体层101的功函数值之间的差异，有利于降低字线128与半导体层101相对应处的横向电场，降低GIDL，从而有利于提高沟道区II的导通/关断比例，以提高控制沟道区II导通/关断的灵敏度；有利于在降低晶体管的阈值电压的同时，通过调控第一字线和第二字线的相关参数使得字线128适用于不同类型的晶体管，从而有利于减少半导体结构的制备工序和降低制备成本。
需要说明的是，上述描述仅仅以字线128包含两层功函数值不同的导电层为示例，在实际应用中，对字线包含的功函数值不同的导电层的层数不做限制。
参考图23和图24，形成字线128之后，还形成有阻挡层109，阻挡层109填充满介质层127围成的空隙，且位于半导体柱105、绝缘层117以及介质层127共同构成的顶面。其中，阻挡层109的材料包括氧化硅、氮化硅或者氮氧化硅。
去除初始位线104侧壁的部分厚度的第一隔离层102，以在相邻初始位线104间形成第三沟槽133，使得在垂直于半导体柱105侧壁的方向上，第三沟槽133的宽度大于第二沟槽123的宽度，因此后续形成第二隔离层132时，第二隔离层132内与第三沟槽133对应的区域具有空隙143，则相邻初始位线104之间由包括第二隔离层132和空隙143的隔离结构实现绝缘，由于空隙143中空气的相对介电常数远小于第二隔离层132的相对介电常数，即空气的绝缘性优于第二隔离层132的绝缘性，有利于降低相邻初始位线104之间的寄生电容，降低与不同初始位线104电连接的半导体柱105之间的影响，以提高半导体结构整体的电学性能。
本公开另一示例性实施例还提供一种半导体结构，通过上述实施例提供的制造方法形成。以下将结合附图对本公开另一实施例提供的半导体结构进行详细说明。
参考图23和图24，半导体结构包括：基底100，基底100包括多个间隔排布的半导体层101以及位于相邻半导体层101之间的第一隔离层102，半导体层101包括沿第一方向X延伸的位线114和位于位线114顶面的半导体柱105，第一隔离层102位于半导体柱105靠近位线114的一端的侧壁和位于相邻位线114之间，且位于相邻位线114之间的第一隔离层102与位于半导体柱105侧壁的第一隔离层102之间具有第三沟槽，且第三沟槽沿第二方向Y间隔设置，第二方向Y与第一方向X不同；第二隔离层132，位于半导体柱105靠近位线114的一端的侧壁上和第三沟槽暴露出的位线114表面，且位于第三沟槽中的第二隔离层132内具有空隙143。
在一些实施例中，半导体结构还可以包括：第四隔离层122，位于第一掺杂区I侧壁与第二隔离层132之间。
在一些实施例中，半导体结构还可以包括：介质层127，环绕第二掺杂区III侧壁且位于绝缘层117侧壁。半导体结构还可以包括：阻挡层109，填充满介质层127围成的空隙，且位于半导体柱105、绝缘层117以及介质层127共同构成的顶面。需要说明的是，在一些实施例中，介质层127和阻挡层109在不同的步骤中形成，且介质层127的材料和阻挡层109的材料不同；在其他实施例中，介质层127和阻挡层109可以在同一工艺步骤中形成，则介质层127的材料和阻挡层109的材料相同。
位线114的材料可以包括金属半导体化合物124。金属半导体化合物124包括硅化钴、硅化镍、硅化钼、硅化钛、硅化钨、硅化钽或者硅化铂中的至少一种。金属半导体化合物124相较于未金属化的半导体材料而言，具有相对更小的电阻率，相较于未被金属化处理的位线而言，包括金属半导体化合物124的位线114的电阻率更小，有利于降低位线114自身的电阻，且降低位线114与第一掺杂区I之间的接触电阻，进一步改善半导体结构的电学性能。
在一些实施例中，半导体结构还可以包括：栅介质层118，至少环绕靠近第二隔离层132的部分厚度的剩余半导体柱105的侧壁；字线128，环绕栅介质层118远离半导体柱105的侧壁表面，且字线128沿第二方向Y延伸，相邻字线128之间具有间隔；绝缘层117，至少填充满间隔。
第二隔离层132内在与第三沟槽对应的区域具有空隙143。由于空隙143中空气的相对介电常数远小于第二隔离层132的相对介电常数，即空气的绝缘性优于第二隔离层132的绝缘性，有利于降低相邻位线114之间的寄生电容，降低与不同位线114电连接的半导体柱105之间的影响，以提高半导体结构整体的电学性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的 技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开提供的半导体结构及其制造方法中，去除初始位线侧壁的部分厚度的第一隔离层，以在相邻初始位线间形成第三沟槽，使得在垂直于半导体柱侧壁的方向上，第三沟槽的宽度大于第二沟槽的宽度，因此后续形成第二隔离层时，第二隔离层内与第三沟槽对应的区域具有空隙，则相邻初始位线之间由包括第二隔离层和空隙的隔离结构实现绝缘，由于空隙中空气的相对介电常数远小于第二隔离层的相对介电常数，即空气的绝缘性优于第二隔离层的绝缘性，有利于降低相邻初始位线之间的寄生电容，降低与不同初始位线电连接的半导体柱之间的影响，以提高半导体结构整体的电学性能。

Claims (15)

  1. 一种半导体结构的制造方法，包括：
    提供基底；
    在所述基底内形成多条沿第一方向延伸的第一沟槽，所述第一沟槽将所述基底形成间隔排布的半导体层，并在所述第一沟槽内填充第一隔离层；
    在所述半导体层和所述第一隔离层内形成多条沿第二方向延伸的第二沟槽，所述第二沟槽的深度小于所述第一沟槽的深度，以将所述半导体层形成多个分立的半导体柱和位于所述半导体柱下方的初始位线；
    在低于所述第二沟槽的位置形成平行于所述第一沟槽的第三沟槽，在垂直于所述半导体柱侧壁的方向上，所述第三沟槽的宽度大于所述第二沟槽的宽度；
    在所述第二沟槽和所述第三沟槽内填充第二隔离层，其中，所述第三沟槽内的所述第二隔离层内具有空隙。
  2. 如权利要求1所述的制造方法，其中，在垂直于所述半导体柱侧壁的方向上，所述第一沟槽的宽度大于等于所述第二沟槽的宽度。
  3. 如权利要求1所述的制造方法，其中，在低于所述第二沟槽的位置形成平行于所述第一沟槽的所述第三沟槽的步骤包括：
    形成保护层，所述保护层位于所述第二沟槽的侧壁上，且露出所述初始位线顶面和相邻所述初始位线间的所述第一隔离层的顶面；
    以所述保护层为掩膜去除位于所述初始位线侧壁的部分厚度的所述第一隔离层，以形成所述第三沟槽；
    去除所述保护层。
  4. 如权利要求3所述的制造方法，其中，在形成所述保护层之前，还包括：形成第三隔离层，所述第三隔离层仅位于所述沟槽暴露出的侧壁表面。
  5. 如权利要求3所述的制造方法，其中，在同一刻蚀工艺下，所述第一隔离层和所述保护层之间的刻蚀选择比大于等于50。
  6. 如权利要求3所述的制造方法，其中，在形成所述第三沟槽之后，形成所述第二隔离层之前，还包括：
    在所述第三沟槽暴露出的所述初始位线的表面形成第四隔离层，且所述第四隔离层不改变所述第三沟槽的整体形貌。
  7. 如权利要求6所述的制造方法，其中，在形成所述第四隔离层之后，形成所述第二隔离层之前，还包括：
    去除位于所述初始位线顶面的所述第四隔离层；
    对暴露出的所述初始位线进行金属硅化处理，以形成位线，所述位线的材料包括金属半导体化合物。
  8. 如权利要求7所述的制造方法，其中，在所述半导体柱指向所述位线的方向上，所述第三沟槽的深度大于所述金属半导体化合物的深度。
  9. 如权利要求1所述的制造方法，其中，所述制造方法还包括：去除所述第二沟槽内部分厚度的所述第二隔离层以形成凹槽，所述凹槽沿所述第二方向延伸；
    形成填充满所述凹槽的绝缘层；
    以所述绝缘层为掩膜去除部分厚度的所述半导体柱侧壁的所述第一隔离层和所述第二隔离层，以在所述半导体柱和所述绝缘层之间形成间隙；
    在垂直于所述第二沟槽侧壁的方向上，在所述间隙中依次堆叠形成栅介质层和字线。
  10. 如权利要求9所述的制造方法，其中，沿所述初始位线指向所述半导体柱的方向上，所述半导体柱包括依次排列的第一掺杂区、沟道区以及第二掺杂区；形成所述凹槽的方法包括图形化处理，且所述凹槽的侧壁由剩余所述第二隔离层构成，在所述第一掺杂区指向所述沟道区的方向上，所述凹槽的深度大于等于所述沟道区的高度和所述第二掺杂区的高度之和。
  11. 如权利要求10所述的制造方法，其中，形成所述间隙的步骤包括：
    以所述绝缘层为掩膜去除与所述第二掺杂区对应的所述第一隔离层和所述第二隔离层；
    形成介质层，所述介质层环绕所述第二掺杂区侧壁且位于所述绝缘层侧壁，所述介质层侧壁围成通孔，所述通孔底部露出所述第一隔离层，且所述介质层的材料和所述绝缘层的材料均与所述第一隔离层的材料不同；
    去除所述通孔露出的与所述沟道区对应的所述第二隔离层和所述第一隔离层，以形成所述间隙，剩余所述第二隔离层和所述第一隔离层共同环绕所述第一掺杂区侧壁。
  12. 如权利要求10所述的制造方法，其中，形成所述间隙的步骤包括：
    以所述绝缘层为掩膜去除与所述第二掺杂区和所述沟道区对应的所述第一隔离层和所述第二隔离层，以形成所述间隙，剩余所述第二隔离层和所述第一隔离层共同环绕所述第一掺杂区侧壁。
  13. 如权利要求11或12所述的制造方法，其中，所述栅介质层至少位于暴露出的所述沟道区的侧壁，且所述栅介质层和所述绝缘层之间具有第二间隙。
  14. 一种半导体结构，包括：
    基底，所述基底包括多个间隔排布的半导体层以及位于相邻所述半导体层之间的第一隔离层，所述半导体层包括沿第一方向延伸的位线和位于所述位线顶面的半导体柱，所述第一隔离层位于所述半导体柱靠近所述位线的一端的侧壁和位于相邻所述位线之间，且位于相邻所述位线之间的所述第一隔离层与位于所述半导体柱侧壁的所述第一隔离层之间具有第三沟槽，且所述第三沟槽沿第二方向间隔设置，所述第二方向与所述第一方向不同；
    第二隔离层，位于所述半导体柱靠近所述位线的一端的侧壁上和所述第三沟槽暴露出的所述位线表面，且位于所述第三沟槽中的所述第二隔离层内具有空隙。
  15. 如权利要求14所述的半导体结构，其中，所述半导体结构还包括：栅介质层，至少环绕靠近所述第二隔离层的部分厚度的剩余所述半导体柱的侧壁；
    字线，环绕所述栅介质层远离所述半导体柱的侧壁表面，且所述字线沿所述第二方向延伸，相邻所述字线之间具有间隔；
    绝缘层，至少填充满所述间隔。
PCT/CN2022/137301 2022-01-07 2022-12-07 半导体结构及其制造方法 Ceased WO2023130883A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP22888619.8A EP4231342B1 (en) 2022-01-07 2022-12-07 Semiconductor structure and method for manufacturing same
US18/313,417 US12431385B2 (en) 2022-01-07 2023-05-08 Semiconductor structure and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210016563.4 2022-01-07
CN202210016563.4A CN114420644A (zh) 2022-01-07 2022-01-07 半导体结构及其制造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/313,417 Continuation US12431385B2 (en) 2022-01-07 2023-05-08 Semiconductor structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2023130883A1 true WO2023130883A1 (zh) 2023-07-13

Family

ID=81272178

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/137301 Ceased WO2023130883A1 (zh) 2022-01-07 2022-12-07 半导体结构及其制造方法

Country Status (4)

Country Link
US (1) US12431385B2 (zh)
EP (1) EP4231342B1 (zh)
CN (1) CN114420644A (zh)
WO (1) WO2023130883A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119677090A (zh) * 2023-09-21 2025-03-21 长江存储科技有限责任公司 半导体器件及其制备方法、存储系统

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114420644A (zh) * 2022-01-07 2022-04-29 长鑫存储技术有限公司 半导体结构及其制造方法
CN117156841A (zh) 2022-05-20 2023-12-01 长鑫存储技术有限公司 一种半导体结构的制作方法及其结构
CN117295327A (zh) * 2022-06-15 2023-12-26 北京超弦存储器研究院 一种半导体结构及其制造方法、dram和电子设备
CN117479525A (zh) * 2022-07-22 2024-01-30 北京超弦存储器研究院 半导体器件的制作方法、半导体器件及电子设备
EP4336567A4 (en) 2022-07-28 2024-05-01 Changxin Memory Technologies, Inc. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHODS THEREFOR
CN117525110A (zh) * 2022-07-28 2024-02-06 长鑫存储技术有限公司 半导体结构及其制作方法
CN117545272A (zh) 2022-08-01 2024-02-09 长鑫存储技术有限公司 半导体结构制备方法及半导体结构
CN117545271A (zh) * 2022-08-01 2024-02-09 长鑫存储技术有限公司 半导体结构的制备方法及半导体结构
CN117580356A (zh) 2022-08-04 2024-02-20 长鑫存储技术有限公司 半导体结构及其形成方法
CN115295551A (zh) * 2022-08-04 2022-11-04 长鑫存储技术有限公司 半导体结构及其形成方法
CN117580357A (zh) 2022-08-04 2024-02-20 长鑫存储技术有限公司 半导体结构的形成方法
CN117677179A (zh) * 2022-08-15 2024-03-08 长鑫存储技术有限公司 半导体结构及其形成方法
CN115332321B (zh) * 2022-08-19 2026-04-03 长鑫存储技术有限公司 半导体结构及其形成方法
CN117677184A (zh) * 2022-08-19 2024-03-08 长鑫存储技术有限公司 半导体结构及其形成方法
WO2024060676A1 (zh) * 2022-09-21 2024-03-28 长鑫存储技术有限公司 半导体结构和半导体结构的制造方法
CN115832015B (zh) * 2022-11-23 2023-09-05 北京超弦存储器研究院 一种半导体器件及其制备方法、电子设备
CN116133430B (zh) * 2023-02-07 2026-02-13 长鑫存储技术有限公司 半导体结构及其制造方法
CN119155992B (zh) * 2023-06-08 2025-10-03 长鑫存储技术有限公司 半导体结构及其形成方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165539A (zh) * 2011-12-09 2013-06-19 爱思开海力士有限公司 形成掩埋位线的方法、具有掩埋位线的半导体器件及其制造方法
US20140061850A1 (en) * 2012-08-28 2014-03-06 SK Hynix Inc. Semiconductor device with buried bitline and method for fabricating the same
CN112992792A (zh) * 2021-02-09 2021-06-18 长鑫存储技术有限公司 半导体结构的制造方法及半导体结构
CN113035869A (zh) * 2021-02-25 2021-06-25 长鑫存储技术有限公司 半导体结构及其形成方法
CN114420644A (zh) * 2022-01-07 2022-04-29 长鑫存储技术有限公司 半导体结构及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101820022B1 (ko) * 2010-11-11 2018-01-19 삼성전자주식회사 수직 채널 트랜지스터를 갖는 반도체 소자 및 그 제조방법
KR20140003206A (ko) * 2012-06-29 2014-01-09 에스케이하이닉스 주식회사 매립비트라인을 구비한 반도체 장치 및 그 제조방법
KR101911373B1 (ko) * 2012-07-17 2018-12-31 에스케이하이닉스 주식회사 반도체 장치 제조 방법
KR102102782B1 (ko) 2013-07-24 2020-04-22 에스케이하이닉스 주식회사 멀티 레이어 게이트를 갖는 반도체 장치, 이를 포함하는 전자 장치 및 그 반도체 장치의 제조 방법
US10134739B1 (en) * 2017-07-27 2018-11-20 Globalfoundries Inc. Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array
CN113611671B (zh) * 2021-08-06 2023-04-07 长鑫存储技术有限公司 半导体结构及其制备方法
US12317473B2 (en) * 2021-11-15 2025-05-27 Changxin Memory Technologies, Inc. Semiconductor device having plurality of trenches with different depth
CN115274670A (zh) * 2022-06-21 2022-11-01 长鑫存储技术有限公司 半导体结构及其制作方法、存储器
CN117832252A (zh) * 2022-09-27 2024-04-05 长鑫存储技术有限公司 半导体结构及其读写控制方法和制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165539A (zh) * 2011-12-09 2013-06-19 爱思开海力士有限公司 形成掩埋位线的方法、具有掩埋位线的半导体器件及其制造方法
US20140061850A1 (en) * 2012-08-28 2014-03-06 SK Hynix Inc. Semiconductor device with buried bitline and method for fabricating the same
CN112992792A (zh) * 2021-02-09 2021-06-18 长鑫存储技术有限公司 半导体结构的制造方法及半导体结构
CN113035869A (zh) * 2021-02-25 2021-06-25 长鑫存储技术有限公司 半导体结构及其形成方法
CN114420644A (zh) * 2022-01-07 2022-04-29 长鑫存储技术有限公司 半导体结构及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4231342A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119677090A (zh) * 2023-09-21 2025-03-21 长江存储科技有限责任公司 半导体器件及其制备方法、存储系统

Also Published As

Publication number Publication date
EP4231342A4 (en) 2024-06-26
EP4231342A1 (en) 2023-08-23
US12431385B2 (en) 2025-09-30
CN114420644A (zh) 2022-04-29
US20230274973A1 (en) 2023-08-31
EP4231342B1 (en) 2025-06-18

Similar Documents

Publication Publication Date Title
EP4231342B1 (en) Semiconductor structure and method for manufacturing same
WO2023206846A1 (zh) 半导体结构及其制造方法
TWI806672B (zh) 半導體結構及其製作方法
CN115701211A (zh) 半导体结构及其制作方法
US12309997B2 (en) Semiconductor structure and method for fabricating same
CN116033741B (zh) 半导体结构及其制造方法
WO2023273079A1 (zh) 半导体结构及其制作方法
KR102707225B1 (ko) 반도체 구조 및 이의 제조 방법
KR102752337B1 (ko) 반도체 구조 및 제조 방법
TWI802451B (zh) 半導體結構及其製造方法
US12369295B2 (en) Semiconductor structure and manufacturing method thereof
JP7664425B2 (ja) 半導体構造及びその製造方法
US12414285B2 (en) Semiconductor structure and manufacturing method thereof
WO2023206857A1 (zh) 半导体结构及其制造方法
CN121751636A (zh) 半导体结构及其制造方法
CN116507112A (zh) 半导体结构及其制作方法
CN121751637A (zh) 半导体结构及其制造方法
CN119677090A (zh) 半导体器件及其制备方法、存储系统

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2022888619

Country of ref document: EP

Effective date: 20230511

NENP Non-entry into the national phase

Ref country code: DE

WWG Wipo information: grant in national office

Ref document number: 2022888619

Country of ref document: EP