WO2023178744A1 - 存储器及其制作方法 - Google Patents

存储器及其制作方法 Download PDF

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Publication number
WO2023178744A1
WO2023178744A1 PCT/CN2022/086419 CN2022086419W WO2023178744A1 WO 2023178744 A1 WO2023178744 A1 WO 2023178744A1 CN 2022086419 W CN2022086419 W CN 2022086419W WO 2023178744 A1 WO2023178744 A1 WO 2023178744A1
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WIPO (PCT)
Prior art keywords
layer
region
active
layers
connection
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PCT/CN2022/086419
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English (en)
French (fr)
Inventor
苏星松
肖德元
白卫平
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to EP22932804.2A priority Critical patent/EP4326026A4/en
Priority to JP2023571416A priority patent/JP7652938B2/ja
Priority to KR1020237027261A priority patent/KR102752338B1/ko
Priority to US17/882,725 priority patent/US12356605B2/en
Publication of WO2023178744A1 publication Critical patent/WO2023178744A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a memory and a manufacturing method thereof.
  • DRAM dynamic random access memory
  • Dynamic random access memory usually includes multiple memory cells. Each memory unit includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line (WL) of the dynamic random access memory. The voltage on the word line controls the turning on of the transistor. and turn off; one of the source and drain of the transistor is electrically connected to the Bit Line (BL), the other of the source and drain is electrically connected to the capacitor, and the data information is stored through the bit line or output.
  • WL word line
  • BL Bit Line
  • capacitors are usually placed horizontally to facilitate the production of capacitors with a larger slenderness ratio.
  • it is difficult to fabricate word lines adapted to them.
  • embodiments of the present disclosure provide a memory and a manufacturing method thereof to reduce the difficulty of manufacturing word lines.
  • a first aspect of the present disclosure provides a method of manufacturing a memory, which includes:
  • the stacked structure including sacrificial layers and active layers alternately stacked along a first direction;
  • Part of the stacked structure located in the first area is removed to form a plurality of first trenches spaced apart and extending in the second direction.
  • the first trenches expose the substrate to connect the laminated structure located in the first area.
  • the active layer is divided into a plurality of active pillars arranged at intervals;
  • the sacrificial layer located in the first region and the second region is removed, so that the active pillar located in the first region and the active column in the second region
  • the layers are spaced apart along the first direction, wherein the second region is adjacent to the first region;
  • a gate material layer is formed to cover the connection layer and the active pillar, and the connection layer on the same layer and the gate material layer formed on the active pillar are connected to each other, and the connection layer and the active pillar are located on different layers.
  • the connection layer and the gate material layer formed on the active pillar are isolated from each other.
  • a stacked layer structure is formed on a substrate.
  • the stacked layer structure includes sacrificial layers and active layers alternately stacked along a first direction; the sacrificial layer and part of the active layer are removed, so that The active layer located in the first area forms a plurality of active pillars arranged at intervals, and the active layer located in the second area forms a plurality of stepped connection layers; and then a gate is formed on the connection layer and the active pillar.
  • the material layer, the connection layer located on the same layer and the gate material layer formed on the active pillar are connected to each other, and the connection layer located on different layers and the gate material layer formed on the active pillar are isolated from each other.
  • the gate material layer is used as a word line.
  • the word line can be easily made and led out.
  • the end of the plurality of connection layers away from the first region is formed in a step shape
  • the end of the gate material layer covering the active pillar and the connection layer is also formed in a step shape, that is, the word line is in a step shape.
  • the step shape facilitates the production of other structures on the word line to achieve electrical connection between the word line and peripheral circuits.
  • a second aspect of the present disclosure provides a memory, the memory having an adjacent first area and a second area, the memory including: a plurality of cells located in the second area and spaced apart along a first direction. a plurality of connection layers, and one end of the plurality of connection layers away from the first region is formed into a step shape; a plurality of active pillar layers located in the first region and spaced along the first direction, each The active pillar layer is arranged on the same layer as one of the connection layers; each of the active pillar layers has a plurality of active pillars arranged at intervals, and each of the active pillars extends along the second direction; located on the connection layer The gate material layer on the layer and the active pillar, and the connection layer on the same layer and the gate material layer formed on the active pillar are connected to each other, and the connection layer on different layers and the gate material layer formed on the active pillar are isolated from each other.
  • a gate material layer is provided on the connection layer and the active pillar, and the connection layer on the same layer and the gate material layer formed on the active pillar are connected to each other, and the connections on different layers are connected to each other.
  • the gate material layer formed on the active pillar layer and the active pillar are isolated from each other.
  • the gate material layer is used as a word line.
  • the word line can be easily made and led out.
  • the end of the plurality of connection layers away from the first region is formed in a step shape
  • the end of the gate material layer covering the active pillar and the connection layer is also formed in a step shape, that is, the word line is in a step shape.
  • the step shape facilitates the production of other structures on the word line to achieve electrical connection between the word line and peripheral circuits.
  • Figure 1 is an architectural diagram of a memory in an embodiment of the present disclosure
  • Figure 2 is a flow chart of a memory manufacturing method in an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of the first region and the second region after forming a stacked structure in an embodiment of the present disclosure
  • Figure 4 is a schematic diagram of the first region and the second region after forming the first trench in an embodiment of the present disclosure
  • Figure 5 is another schematic diagram of the first region and the second region after forming the first trench in an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of the first region and the second region after forming a protective layer in an embodiment of the present disclosure
  • Figure 7 is a schematic diagram of the first region and the second region after forming the first mask layer in an embodiment of the present disclosure
  • Figure 8 is a schematic diagram of the first region and the second region after removing the sacrificial layer in an embodiment of the present disclosure
  • Figure 9 is a schematic diagram of the first region and the second region after forming the connection layer in an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of the first region and the second region after forming the gate material layer in an embodiment of the present disclosure
  • Figure 11 is a schematic diagram of the first region and the second region after forming the contact plug in an embodiment of the present disclosure
  • Figure 12 is a schematic diagram of the third region after forming a stacked structure in an embodiment of the present disclosure.
  • Figure 13 is a schematic diagram of the third region after forming a protective layer in an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of the third region after forming the first mask layer in an embodiment of the present disclosure.
  • the capacitor in order to further increase the storage capacity of the memory, the capacitor is usually placed horizontally, that is, the extension direction of the capacitor is parallel to the substrate, so as to facilitate the production of the capacitor.
  • the capacitor When the capacitor is placed horizontally, the corresponding word lines need to be rearranged, making the production of the word lines more difficult.
  • connection layer and an active pillar By forming a connection layer and an active pillar, the end of the connection layer away from the active pillar is formed into a step shape, and a gate between the connection layer and the active pillar is formed.
  • a gate material layer is formed on the electrode material layer, the connection layer on the same layer and the gate material layer formed on the active column are connected to each other, and the connection layer on different layers and the gate material layer formed on the active column are isolated from each other.
  • the gate material layer is used as a word line to facilitate production and removal, and the word line is in a stepped shape to facilitate the production of other structures on the word line to achieve electrical connection between the word line and peripheral circuits.
  • the first aspect of the disclosed embodiments provides a method of manufacturing a memory.
  • the memory includes a dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM), a static random access memory (Static Random Access Memory, referred to as SRAM), and a flash memory.
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • PRAM Phase Change Random Access Memory
  • MRAM Magnetoresistive Random Access Memory
  • the memory includes a word line 4, a bit line 1, a transistor 2 and a capacitor 3.
  • the gate of the transistor 2 is electrically connected to the word line 4, and one of the source and drain of the transistor 2 is connected to the bit line.
  • Line 1 is electrically connected, and the other line is electrically connected to capacitor 3 .
  • the word line 4 is used to control the opening or closing of the transistor 2
  • the bit line 1 is used to write data information into the capacitor 3 or read data information in the capacitor 3 .
  • both the transistor 2 and the capacitor 3 extend along the second direction (the Z direction shown in Figure 1), which is parallel to the substrate, that is, the transistor 2 and the capacitor 3 are both arranged parallel to the substrate, so as to facilitate manufacturing
  • the capacitor 3 has a large aspect ratio, thereby increasing the storage capacity of the memory.
  • Figure 2 is a flow chart of a memory manufacturing method according to an embodiment of the present disclosure.
  • the manufacturing method may include:
  • Step S10 Provide a substrate.
  • the substrate 10 can provide a supporting foundation for the structural layer on the substrate 10.
  • the material of the substrate 10 can be a semiconductor.
  • the material of the substrate 10 can be monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, Silicon carbide, silicon germanium (SiGe), germanium on insulator (Germanium on Insulator, referred to as GOI) or silicon on insulator (Silicon on Insulator, referred to as SOI), etc.
  • the substrate 10 includes a first region and a second region.
  • the first region is shown at B in FIG. 3
  • the second region is shown at A in FIG. 3 .
  • the first region and the second region The regions are adjacent, for example, the first region is adjacent to and connected to the second region.
  • a semiconductor device such as the transistor 2
  • a connection structure such as the connection layer 60 (see Figure *)
  • the semiconductor device on the first region is led out through the structure on the second region, so that the semiconductor device is electrically connected to the peripheral circuit.
  • the substrate 10 located in the first area and the substrate 10 located in the second area are integrated to facilitate providing the substrate 10 .
  • Step S20 Form a stacked structure on the substrate.
  • the stacked structure includes sacrificial layers and active layers alternately stacked along a first direction.
  • the stacked structure 20 includes a plurality of sacrificial layers 21 and a plurality of active layers 22 .
  • the plurality of sacrificial layers 21 and the plurality of active layers 22 are alternately stacked along the first direction.
  • the first direction is a direction perpendicular to the substrate 10 , such as the Y direction as shown in FIG. 3 .
  • an active layer 22 is provided between two adjacent sacrificial layers 21 , or a sacrificial layer 21 is provided between two adjacent active layers 22 , so that the sacrificial layer 21 and the active layer 22 alternate in sequence. set up. With such an arrangement, two adjacent active layers 22 can be isolated by the sacrificial layer 21, so that the active layers 22 are electrically isolated along the first direction.
  • forming the stacked structure 20 on the substrate 10 includes: forming a sacrificial layer 21 and an active layer 22 on the substrate 10 alternately and repeatedly until the stacked structure 20 is formed, and the stacked structure 20
  • the innermost layer close to the substrate 10 is the sacrificial layer 21
  • the outermost layer of the stacked structure 20 away from the substrate 10 is the active layer 22 .
  • a sacrificial layer 21 is formed on the substrate 10
  • an active layer 22 is formed on the sacrificial layer 21, and a sacrificial layer 21 is formed on the active layer 22.
  • the formation process of the active layer 22 and the sacrificial layer 21 is repeated until a required number of layers of the sacrificial layer 21 and the active layer 22 are formed.
  • the innermost layer of the stacked structure 20 close to the substrate 10 is a sacrificial layer 21 , so that the active layer 22 on the sacrificial layer 21 is spaced apart from the substrate 10 , and each active layer 22 Subsequently, transistors 2 can be formed, thereby increasing the number of transistors 2 and thereby increasing the storage capacity of the semiconductor structure.
  • the outermost layer of the stacked structure 20 away from the substrate 10 is the active layer 22. In this way, when the stacked structure 20 has the same number of active layers 22, the height of the stacked structure 20 is reduced to facilitate subsequent etching. Laminated structure 20.
  • the sacrificial layer 21 and the active layer 22 are formed on the substrate 10 through a deposition process.
  • the deposition process may include chemical vapor deposition (Chemical Vapor Deposition, CVD for short), physical vapor deposition (Physical Vapor Deposition). , referred to as PVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD), etc.
  • the sacrificial layer 21 and the active layer 22 are formed from the substrate 10 through an epitaxial growth process (Epitaxy, EPI for short).
  • the substrate 10, the active layer 22 and the sacrificial layer 21 are made of the same element, such as silicon, so that the sacrificial layer 21 is epitaxially grown on the substrate 10, the active layer 22 is epitaxially grown on the sacrificial layer 21, and The sacrificial layer 21 is epitaxially grown on the active layer 22 .
  • the substrate 10 is made of silicon
  • the active layer 22 is made of silicon
  • the sacrificial layer 21 is made of silicon germanium.
  • the material of the active layer 22 includes doped silicon.
  • the material of the active layer 22 includes N-type doped silicon to improve the electrical performance of the active layer 22 .
  • Step S30 Remove part of the stacked structure located in the first area to form a plurality of first trenches arranged at intervals and extending in the second direction.
  • the first trenches expose the substrate to separate the active layer located in the first area. Active columns arranged at multiple intervals.
  • a plurality of first trenches 51 are formed in the stacked structure 20 in the first region.
  • the plurality of first trenches 51 are spaced apart and extend in a second direction.
  • the second direction is the horizontal direction shown in FIG. 1 (Z direction), which is parallel to the substrate 10 and perpendicular to the first direction.
  • the first trench 51 penetrates the stacked structure 20 in the first region to expose the substrate 10 .
  • the first trench 51 may extend into the substrate 10 , that is, the bottom of the first trench 51 is located in the substrate 10 .
  • Such an arrangement can ensure that the first trench 51 separates the laminated structure 20 into multiple bodies, so that each active layer 22 in the laminated structure 20 is divided into a plurality of spaced-apart active pillars 50 to improve the efficiency.
  • the number of active pillars 50 increases the storage capacity of the semiconductor structure.
  • the plurality of active pillars 50 are arranged in an array, and the plurality of active pillars 50 extend along the second direction.
  • the plurality of active pillars 50 are spaced apart along the first direction and spaced apart along the third direction.
  • the third direction intersects with the first direction and is perpendicular to the second direction.
  • the third direction is a direction parallel to the substrate 10.
  • the third direction is the horizontal direction (X direction) shown in Figures 4 and 5, and the first direction, the second direction and the third direction are perpendicular to each other. .
  • This arrangement can make the active pillars 50 more compact and maximize the number of active pillars 50 arranged.
  • Active pillar 50 includes a source electrode, a drain electrode, and a channel between the source electrode and the drain electrode.
  • the shape of the active pillar 50 may be a cylinder, a prism, a cuboid or other shapes, which is not limited in the embodiments of the present disclosure.
  • removing part of the stacked structure 20 located in the first area to form a plurality of first trenches 51 spaced apart and extending in the second direction includes: etching the stacked structure 20 located in the first area to form a first The trench 51, the first trench 51 penetrates the stacked structure 20.
  • the stacked structure 20 located in the first region is etched to form a first trench 51 , and the first trench 51 penetrates the stacked structure 20 , including:
  • a first mask layer 40 is formed on the stacked structure 20, and the first mask layer 40 located in the first region has a first pattern.
  • the first mask layer 40 is formed on the stacked structure 20. Both the stacked structure 20 located in the first area and the second area are covered with the first mask layer 40.
  • the first mask layer 40 located in the first area There is a first pattern to expose part of the laminated structure 20 located in the first area, and part of the laminated structure 20 located in the second area is not exposed.
  • the stacked structure 20 located in the first region is etched to form a first trench 51 .
  • the first pattern is transferred to the stacked structure 20 located in the first region, so as to form the first trench 51 in the stacked structure 20.
  • forming the first mask layer 40 on the stacked structure 20 includes: forming a protective layer 30 on the stacked structure 20 and forming the first mask layer 40 on the protective layer 30 .
  • the stacked structure 20 is covered with a protective layer 30 , and the protective layer 30 can oxidize the silicon layer to reduce or avoid oxidation of the active layer 22 .
  • the protective layer 30 is covered with a first mask layer 40 , and the first mask layer 40 located in the first region has a first pattern.
  • etching the stacked structure 20 located in the first region includes: using the first mask layer 40 as a mask, etching the layer 20 located in the first region.
  • a region of the protective layer 30 is used to transfer the first pattern into the protective layer 30; the first mask layer 40 is removed, and the stacked structure 20 is continued to be etched with the patterned protective layer 30.
  • the layer 30 serves as a mask, and the stacked structure 20 is continuously etched to form a first trench 51 in the stacked structure 20 .
  • Step S40 Use the first trench to remove the sacrificial layer located in the first region and the second region, so that the active pillars located in the first region and the active layer in the second region are spaced apart along the first direction, wherein, The second area is adjacent to the first area.
  • using the first trench 51 to remove the sacrificial layer 21 located in the first area and the second area includes: using the first trench 51 to expose the sidewalls of the sacrificial layer 21, and wet etching.
  • the etching process removes the sacrificial layer 21 located in the first region and the second region.
  • the wet etching process has a good selectivity ratio.
  • Step S50 Remove part of the active layer located in the second area to form a plurality of step-shaped connection layers at an end of the second area away from the first area.
  • connection layer 60 part of the active layer 22 located in the second area is removed, and the remaining active layer 22 located in the second area forms the connection layer 60 .
  • the lengths of the multiple connection layers 60 decrease in sequence in the direction away from the substrate 10 . Therefore, one end of the plurality of connection layers 60 away from the first region is formed into a step shape. As shown in FIG. 9 , the step shape is upward along the first direction and upward along the third direction.
  • the first direction is perpendicular to the substrate 10 , the Y direction as shown in FIG. 9 , and the third direction is parallel to the substrate. 10 direction, X direction as shown in Figure 9.
  • a portion of the surface of the connection layer 60 of each layer is exposed to facilitate the formation of other structures on the connection layer 60 . Specifically, part of the surface of the connection layer 60 of each layer facing away from the substrate 10 is exposed, that is, the left end of the upper surface of the connection layer 60 of each layer is exposed.
  • part of the active layer 22 located in the second area is removed to form a plurality of step-shaped connection layers 60 at an end of the second area away from the first area, including: on the active layer 22 A second mask layer is formed, and the second mask layer located in the second area has a second pattern; using the second mask layer as a mask, the active layer 22 located in the second area is etched to separate the active layer 22 from the second area.
  • a plurality of step-shaped connection layers 60 are formed at one end of the first region; the second mask layer is removed.
  • each active layer 22 corresponds to a second mask layer of different sizes, and the required connection layer 60 is formed by successively shrinking the second mask layer and etching to the corresponding active layer 22.
  • a second mask layer is first formed on the active layer 22, and is used as a mask to etch to the lowermost active layer 22, so that the lowermost active layer 22 forms the connection layer 60; and then removed.
  • the portion of the second mask layer away from the first area is etched to the penultimate active layer 22 using the removed second mask layer as a mask, so that the penultimate active layer 22 is formed.
  • the lowermost layer refers to the layer of the active layer 22 that is closest to the substrate 10
  • the uppermost layer refers to the layer of the active layer 22 that is farthest from the substrate 10 .
  • Step S60 Form a gate material layer to cover the connection layer and the active pillar, and the gate material layer formed on the connection layer and the active pillar on the same layer is connected to each other, and the gate material layer is formed on the connection layer and the active pillar on different layers.
  • the layers of gate material are isolated from each other.
  • connection layer 60 arranged in the same layer and the gate material layer 70 on the active pillar 50 are connected to each other, and the connection layer 60 arranged in different layers and the gate electrode on the active pillar 50 are connected to each other.
  • the material layers 70 are isolated from each other, so that the gate material layers 70 are electrically isolated along the first direction.
  • the plurality of gate material layers 70 are in the shape of steps, and their lengths vary step by step. Specifically, the lengths of the gate material layers 70 gradually decrease in the direction away from the substrate 10 .
  • the gate material layer 70 includes a gate dielectric layer and a gate conductive layer.
  • the gate dielectric layer covers the outer peripheral surface of the active pillar 50 .
  • the gate conductive layer covers the outer peripheral surface of the gate dielectric layer and is integrated along the second direction. This part of the gate conductive layer is layer may be used for the gate of transistor 2.
  • the gate conductive layer also extends to the connection layer 60 , which covers at least two opposite surfaces of the connection layer 60 along the first direction.
  • a gate dielectric layer may also be provided between the gate conductive layer and the connection layer 60 so that the connection layer 60 and the gate dielectric layer on the active pillar 50 are formed together to facilitate the production of the gate dielectric layer.
  • the gate dielectric layer may be made of silicon oxide, and the gate conductive layer may be made of titanium nitride.
  • the gate conductive layer is used as the word line 4, and the word line 4 is easy to manufacture and easy to lead out.
  • forming the gate material layer 70 to cover the connection layer 60 and the active pillar 50 includes:
  • a gate dielectric layer is formed to cover the surface of the connection layer 60 and the active pillar 50 , and there is a gap between each connection layer 60 and the gate dielectric layer on the surface of each active pillar 50 .
  • a gate dielectric layer is deposited on the surface of the connection layer 60 and the active pillar 50 , and the gate dielectric layer covers the outer peripheral surface of the active pillar 50 , and at least covers two opposite surfaces of the connection layer 60 along the first direction, and toward The surface of the active pillar 50 .
  • active pillar 50 includes a source, a channel, and a drain
  • the gate dielectric layer is opposite the channel.
  • a gate conductive layer is deposited to cover the surface of the gate dielectric layer.
  • the gate conductive layers on the gate dielectric layers arranged on the same layer are connected to each other, and the gate conductive layers on the gate dielectric layers arranged on different layers are isolated from each other. That is, the gate conductive layer forms multiple layers, and the multiple gate conductive layers are spaced apart along the first direction.
  • Each gate conductive layer covers the surface of the gate dielectric layer arranged on the same layer and is filled between the gate dielectric layers.
  • the gate conductive layer forms the word line 4.
  • the gate conductive layer located in the first region serves as the gate electrode, which is a part of the word line 4.
  • the gate conductive layer located in the second region serves as the lead-out end of the gate electrode to connect to peripheral circuits.
  • the gate material layer 70 while forming the gate material layer 70 to cover the connection layer 60 and the active pillar 50, it also includes: forming the gate material layer 70 on the substrate 10 located in the first region and the second region, and the substrate
  • the gate material layer 70 on the 10, the gate material layer 70 on the active pillar 50, and the gate material layer 70 on the connection layer 60 are all isolated from each other.
  • there is a gap between the active pillar 50 located in the first region and the substrate 10 there is a gap between the connection layer 60 located in the second region and the substrate 10 . Therefore, before depositing the gate material layer 70 At this time, the gate material layer 70 will also cover the substrate 10 in the first and second regions.
  • the gate material layer 70 on the substrate 10 is spaced apart from the gate material layer 70 on the active pillar 50 and is connected to
  • the gate material layers 70 on layer 60 are spaced apart such that the gate material layers 70 are isolated from each other.
  • the gate material layer 70 is formed to cover the connection layer 60 and the active pillar 50 , and the gate material layer 70 formed on the connection layer 60 and the active pillar 50 at the same layer is connected to each other and located at After the connection layer 60 of different layers and the gate material layer 70 formed on the active pillar 50 are isolated from each other (step S60), it also includes: forming a plurality of contact plugs 80 arranged at intervals and extending along the first direction, each contact Plug 80 is in contact with a layer of gate material 70 located in the second region.
  • a plurality of contact plugs 80 are used to connect the gate material layer 70 to the peripheral circuit.
  • the plurality of contact plugs 80 are arranged at intervals to ensure insulation isolation between the plurality of contact plugs 80, thereby preventing the gate material from being The layers 70 interfere with each other.
  • the plurality of contact plugs 80 correspond to and contact the plurality of gate material layers 70 one by one, so that each gate material layer 70 can be electrically connected to a peripheral circuit, and the corresponding gate material layer 70 is controlled by the peripheral circuit. of transistor 2.
  • the contact plug 80 may include a first conductive part, which is a part close to the substrate 10 , and a second conductive part disposed on the first conductive part, that is, the second conductive part is a part far away from the substrate 10 .
  • the second conductive part is located on a side of the first conductive part away from the substrate 10 .
  • Each of the first conductive part and the second conductive part may include a core layer, and an outer layer covering the sides and bottom of the core layer.
  • the core layer may be an insulating layer, and its material may be silicon nitride or silicon oxide.
  • the outer layer can be a metal layer, and its material can be tungsten or titanium nitride.
  • the substrate 10 in the embodiment of the present disclosure also has a third area.
  • the third area is adjacent to the first area.
  • the third area is shown at C in Figure 11.
  • the capacitor 3 can be formed on the third area. .
  • Capacitor 3 is usually fabricated after gate material layer 70 is formed.
  • the first region and the first region of the substrate 10 are The laminated structure 20 is formed on both the second region and the third region.
  • the laminated structure 20 located in the first region subsequently forms the active pillar 50.
  • the laminated structure 20 located in the second region subsequently forms the connection layer 60.
  • the laminated structure 20 located in the third region subsequently forms the connection layer 60.
  • the stacked structure 20 subsequently forms the support layer of the capacitor 3 .
  • a protective layer 30 is formed on the laminated structure 20.
  • the first mask layer 40 is formed on the protective layer 30, it is located on the laminated structure 20 in the first region, the second region and the third region.
  • the protective layer 30 and the first mask layer 40 are both formed, and in the subsequent manufacturing process, the protective layer 30 and the first mask layer 40 located in the third region remain until the gate material layer 70 is formed. This arrangement prevents the active layer 22 in the third region from being damaged during the process of manufacturing the word line 4 .
  • a stacked structure 20 is formed on the substrate 10.
  • the stacked structure 20 includes a sacrificial layer 21 and an active layer 22 alternately stacked along a first direction; the sacrificial layer 20 is removed. layer 21 and part of the active layer 22, so that the active layer 22 located in the first region forms a plurality of spaced-apart active pillars 50, and the active layer 22 located in the second region forms a plurality of step-shaped connection layers. 60; Then, a gate material layer 70 is formed on the connection layer 60 and the active pillar 50. The connection layer 60 on the same layer and the gate material layer 70 formed on the active pillar 50 are connected to each other.
  • connection layer 60 on a different layer is connected to each other. and the gate material layer 70 formed on the active pillar 50 are isolated from each other.
  • the gate material layer 70 is used as the word line 4.
  • the connection layer 60 it is convenient to make the word line 4 and lead out the word line 4.
  • the end of the plurality of connection layers 60 away from the first region is formed in a step shape
  • the end of the gate material layer 70 covering the active pillar 50 and the connection layer 60 is also formed in a step shape. That is, the word line 4 has a stepped shape, which facilitates the production of other structures on the word line 4 to achieve electrical connection between the word line 4 and the peripheral circuit.
  • a second aspect of the embodiment of the present disclosure provides a memory.
  • the memory has an adjacent first area and a second area.
  • the first area is shown at B in Figure 11, and the second area is shown in Figure 11.
  • the first region is adjacent to the second region.
  • the first region is adjacent to and connected to the second region.
  • a semiconductor device, such as the transistor 2 may be disposed on the first region, and a connection structure, such as the connection layer 60, may be disposed on the second region.
  • the semiconductor device on the first region may be drawn out through the structure on the second region, so that the semiconductor device Electrically connected to peripheral circuits.
  • the memory includes: a plurality of connection layers 60 located in the second area and spaced apart along the first direction, and one end of the plurality of connection layers 60 away from the first area is formed into a step shape.
  • connection layers 60 are located in the second area and are stacked along the first direction.
  • the multiple connection layers 60 are spaced apart to ensure electrical isolation between the multiple connection layers 60 .
  • One end of the plurality of connection layers 60 away from the first area forms a step.
  • the left end of the plurality of connection layers 60 is shaped like a step.
  • the step shape is upward along the first direction and upward along the third direction.
  • the first direction is a direction perpendicular to the substrate 10 , such as the Y direction as shown in FIG. 11
  • the third direction is a direction parallel to the substrate 10 , X direction as shown in Figure 11.
  • the lengths of the plurality of connection layers 60 are successively reduced in a direction away from the substrate 10 , so that one end of the plurality of connection layers 60 away from the first region is formed into a step shape.
  • part of the surface of the connection layer 60 of each layer is exposed to facilitate the formation of other structures on the connection layer 60 .
  • part of the surface of the connection layer 60 of each layer facing away from the substrate 10 is exposed.
  • the memory also includes: a plurality of active pillar layers located in the first area and spaced apart along the first direction.
  • Each active pillar layer is arranged on the same layer as a connection layer 60; each active pillar layer has A plurality of active pillars 50 are arranged at intervals, and each active pillar 50 extends along the second direction.
  • multiple active pillar layers are located in the first area and are stacked along the first direction.
  • the multiple active pillar layers 50 are arranged at intervals to ensure electrical isolation between the multiple active pillar layers.
  • the plurality of active pillar layers correspond to the plurality of connection layers 60 one-to-one, and the corresponding active pillar layers and the connection layers 60 are arranged on the same layer, so as to form the gate material layer 70 on the active pillar layer and the connection layer 60 .
  • each active pillar layer includes a plurality of active pillars 50 arranged at intervals, and the plurality of active pillars 50 extend along the second direction.
  • the plurality of active pillars 50 are arranged in an array. Specifically, the plurality of active pillars 50 are arranged at intervals along the first direction and at intervals along the third direction.
  • the third direction intersects with the first direction, and both are intersected with each other.
  • the second direction is vertical.
  • the second direction is a direction parallel to the substrate 10 .
  • the second direction is the horizontal direction (Z direction) shown in FIG. 1 , and the first direction, the second direction and the third direction are perpendicular to each other.
  • the shape of the active pillar 50 may be a cylinder, a prism, a cuboid or other shapes, which is not limited in the embodiments of the present disclosure.
  • the memory also includes: a gate material layer 70 located on the connection layer 60 and the active pillar 50 , and the connection layer 60 and the gate material layer 70 formed on the active pillar 50 on the same layer are connected to each other. , the gate material layer 70 formed on the connection layer 60 and the active pillar 50 of different layers are isolated from each other.
  • connection layer 60 arranged in the same layer and the gate material layer 70 on the active pillar 50 are connected to each other, and the connection layer 60 arranged in different layers and the gate material layer 70 on the active pillar 50 are isolated from each other. So that the gate material layer 70 is electrically isolated along the first direction. Since the connection layer 60 is in the shape of steps, the plurality of gate material layers 70 are in the shape of steps, and their lengths vary stepwise, so as to facilitate the formation of other structures on the gate material layers 70, thereby drawing out the gate material layers 70. Specifically, the length of the gate material layer 70 gradually decreases along the direction away from the substrate 10 .
  • the gate material layer 70 includes a gate dielectric layer and a gate conductive layer.
  • the gate dielectric layer covers the outer peripheral surface of the active pillar 50 .
  • the gate conductive layer covers the outer peripheral surface of the gate dielectric layer and is integrated along the second direction. This part of the gate conductive layer is layer may be used for the gate of transistor 2.
  • the gate conductive layer also extends to the connection layer 60 , which covers at least two opposite surfaces of the connection layer 60 along the first direction.
  • a gate dielectric layer may also be provided between the gate conductive layer and the connection layer 60 so that the connection layer 60 and the gate dielectric layer on the active pillar 50 are formed together to facilitate the production of the gate dielectric layer.
  • the gate dielectric layer may be made of silicon oxide, and the gate conductive layer may be made of titanium nitride.
  • the gate conductive layer is used as the word line 4, and the word line 4 is easy to manufacture and easy to lead out.
  • the memory further includes: a plurality of contact plugs 80 arranged at intervals and extending along the first direction, each contact plug 80 being in contact with a gate material layer 70 located in the second region.
  • multiple contact plugs 80 are used to connect the gate material layer 70 to the peripheral circuit.
  • the multiple contact plugs 80 are arranged at intervals to ensure insulation isolation between the multiple contact plugs 80, thereby avoiding The gate material layers 70 interfere with each other.
  • the plurality of contact plugs 80 correspond to and contact the plurality of gate material layers 70 one by one, so that each gate material layer 70 can be electrically connected to a peripheral circuit, and the corresponding gate material layer 70 is controlled by the peripheral circuit. of transistor 2.
  • the contact plug 80 may include a first conductive part, which is a part close to the substrate 10 , and a second conductive part disposed on the first conductive part, that is, the second conductive part is a part far away from the substrate 10 .
  • the second conductive part is located on a side of the first conductive part away from the substrate 10 .
  • Each of the first conductive part and the second conductive part may include a core layer, and an outer layer covering the sides and bottom of the core layer.
  • the core layer may be an insulating layer, and its material may be silicon nitride or silicon oxide.
  • the outer layer can be a metal layer, and its material can be tungsten or titanium nitride.
  • the memory further has a third area, which is adjacent to the first area, and the memory further includes: a plurality of spaced-apart capacitors 3 located in the third area, the capacitors 3 extending along the second direction, And each capacitor 3 is electrically connected to an active pillar 50 .
  • the third area and the first area may be arranged along the second direction (the Z direction shown in Figure 11).
  • the third area is provided with a plurality of capacitors 3 arranged at intervals, and the plurality of capacitors 3 and a plurality of active pillars 50 are provided.
  • a gate material layer 70 is provided on the connection layer 60 and the active pillar 50 , and the connection layer 60 and the gate material layer 70 formed on the active pillar 50 on the same layer are connected to each other. , the gate material layer 70 formed on the connection layer 60 and the active pillar 50 of different layers is isolated from each other.
  • the gate material layer 70 is used as the word line 4.
  • the connection layer 60 it is convenient to make the word line 4 and connect the word line 4 to the word line 4.
  • Line 4 leads out.
  • the end of the plurality of connection layers 60 away from the first region is formed in a step shape, the end of the gate material layer 70 covering the active pillar 50 and the connection layer 60 is also formed in a step shape. That is, the word line 4 has a stepped shape, which facilitates the production of other structures on the word line 4 to achieve electrical connection between the word line 4 and the peripheral circuit.

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Abstract

本公开提供一种存储器及其制作方法，涉及半导体技术领域，用于解决字线不易制作的技术问题，该制作方法包括：在衬底上形成叠层结构，叠层结构包括沿第一方向交替堆叠设置的牺牲层和有源层；去除位于第一区域的部分叠层结构，形成多条间隔设置且沿第二方向延伸的第一沟槽，第一沟槽暴露衬底，以将位于第一区域的有源层分隔成多个间隔设置的有源柱；去除位于第一区域和第二区域的牺牲层；去除位于第二区域的部分有源层，以在第二区域远离第一区域的一端形成呈台阶状的多个连接层；形成栅极材料层包覆连接层和有源柱。栅极材料层用作字线，通过设置连接层，便于制作字线，并将字线引出。

Description

存储器及其制作方法
本公开要求于2022年03月23日提交中国专利局、申请号为202210289745.9、申请名称为“存储器及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种存储器及其制作方法。
背景技术
随着半导体技术的发展，存储器，尤其是动态随机存储器(Dynamic Random Access Memory，简称DRAM)因其具有较高的存储密度以及较快的读写速度被广泛地应用在各种电子设备中。
动态随机存储器通常包括多个存储单元，每个存储单元包括晶体管和电容器，晶体管的栅极与动态随机存储器的字线(Word Line，简称WL)电连接，通过字线上的电压控制晶体管的开启和关闭；晶体管的源极和漏极中的一极与位线(Bit Line，简称BL)电连接，源极和漏极中的另一极与电容器电连接，通过位线对数据信息进行存储或者输出。
为了进一步减小存储器的尺寸，提高其存储密度，通常将电容器水平放置，以便于制作具有更大长细比的电容器，然而，与其适配的字线制作困难。
发明内容
鉴于上述问题，本公开实施例提供一种存储器及其制作方法，用于降低字线的制作难度。
根据一些实施例，本公开第一方面提供一种存储器的制作方法，其包括：
提供衬底；
在所述衬底上形成叠层结构，所述叠层结构包括沿第一方向交替堆叠设置的牺牲层和有源层；
去除位于第一区域的部分所述叠层结构，形成多条间隔设置且沿第二方向延伸的第一沟槽，所述第一沟槽暴露所述衬底，以将位于所述第一区域的所述有源层分隔成多个间隔设置的有源柱；
利用所述第一沟槽，去除位于所述第一区域和第二区域的所述牺牲层，以使位于所述第一区域的所述有源柱和所述第二区域的所述有源层均沿所述第一方向间隔设置，其中，所述第二区域与所述第一区域相邻；
去除位于所述第二区域的部分所述有源层，以在所述第二区域远离所述第一区域的一端形成呈台阶状的多个连接层；
形成栅极材料层包覆所述连接层和所述有源柱，且位于同一层的所述连接层和所述有源柱上形成的所述栅极材料层相互连通，位于不同层的所述连接层和所述有源柱上形成的所述栅极材料层相互隔离。
本公开实施例提供的存储器的制作方法至少具有如下优点：
本公开实施例提供的存储器的制作方法中，在衬底上形成叠层结构，叠层结构包括沿第一方向交替堆叠设置的牺牲层和有源层；去除牺牲层以及部分有源层，使得位于第一区域的有源层形成多个间隔设置的有源柱，并使得位于第二区域的有源层形成呈台阶状的多个连接层；再在连接层和有源柱上形成栅极材料层，位于同一层的连接层和有源柱上形成的栅极材料层相互连通，位于不同层的连接层和有源柱上形成的栅极材料层相互隔离。栅极材料层用作字线，通过设置连接层，便于制作字线，并将字线引出。此外，由于多个连接层远离第一区域的一端形成呈台阶状，从而使得覆盖在有源柱和连接层上的栅极材料层远离第一区域的一端也形成呈台阶状，即字线呈台阶状，便于在字线上制作其他结构，以实现字线与外围电路的电性连接。
根据一些实施例，本公开第二方面提供一种存储器，所述存储器具有相邻的第一区域和第二区域，所述存储器包括：位于所述第二区域且沿第一方向间隔设置的多个连接层，且多个所述连接层远离所述第一区域的一端形成呈台阶状；位于所述第一区域且沿所述第一方向间隔设置的多个有源柱层，每个所述有源柱层与一个所述连接层同层设置；每个所述有源柱层具有多个间隔设置的有源柱，且各所述有源柱沿第二方向延伸；位于所述连接层上和所述有源柱上的栅极材料层，且位于同一层的所述连接层和所述有源柱上形成的所述栅极材料层相互连通，位于不同层的所述连接层和所述有源柱上形成的所述栅极材料层相互隔离。
本公开实施例提供的存储器至少具有如下优点：
本公开实施例提供的存储器，通过在连接层上和有源柱上设置栅极材料层，且位于同一层的连接层和有源柱上形成的栅极材料层相互连通，位于不同层的连接层和有源柱上形成的栅极材料层相互隔离。栅极材料层用作字线，通过设置连接层，便于制作字线，并将字线引出。此外，由于多个连接层远离第一区域的一端形成呈台阶状，从而使得覆盖在有源柱和连接层上的栅极材料层远离第一区域的一端也形成呈台阶状，即字线呈台阶状，便于在字线上制作其他结构，以实现字线与外围电路的电性连接。
附图说明
图1为本公开一实施例中的存储器的架构图；
图2为本公开一实施例中的存储器的制作方法的流程图；
图3为本公开一实施例中的形成叠层结构后的第一区域和第二区域的示意图；
图4为本公开一实施例中的形成第一沟槽后的第一区域和第二区域的一种示意图；
图5为本公开一实施例中的形成第一沟槽后的第一区域和第二区域的另一种示意 图；
图6为本公开一实施例中的形成保护层后的第一区域和第二区域的一种示意图；
图7为本公开一实施例中的形成第一掩膜层后的第一区域和第二区域的一种示意图；
图8为本公开一实施例中的去除牺牲层后的第一区域和第二区域的一种示意图；
图9为本公开一实施例中的形成连接层后的第一区域和第二区域的一种示意图；
图10为本公开一实施例中的形成栅极材料层后的第一区域和第二区域的一种示意图；
图11为本公开一实施例中的形成接触插塞后的第一区域和第二区域的一种示意图；
图12为本公开一实施例中的形成叠层结构后的第三区域的一种示意图；
图13为本公开一实施例中的形成保护层后的第三区域的一种示意图；
图14为本公开一实施例中的形成第一掩膜层后的第三区域的一种示意图。
具体实施方式
在相关技术中，为了进一步增加存储器的存储容量，通常将电容器水平放置，即电容器的延伸方向与衬底平行，以便于电容器的制作。当电容器水平放置时，与之相适应的字线需要重新布局，字线的制作难度较大。
有鉴于此，本公开实施例提供一种存储器及其制作方法，通过形成连接层和有源柱，且连接层远离有源柱的一端形成呈台阶状，并在连接层和有源柱的栅极材料层上形成栅极材料层，位于同一层的连接层和有源柱上形成的栅极材料层相互连通，位于不同层的连接层和有源柱上形成的栅极材料层相互隔离。栅极材料层用作字线，便于制作和出，且字线呈台阶状，便于在字线上制作其他结构，以实现字线与外围电路的电性连接。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
本公开实施例第一方面提供一种存储器的制作方法，该存储器包括动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)、静态随机存取存储器(Static Random Access Memory，简称SRAM)、快闪存储器、电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，简称EEPROM)、相变随机存取存储器(Phase Change Random Access Memory，简称PRAM))或者磁阻随机存取存储器(Magneto-resistive Random Access Memory，简称MRAM)等。本公开实施例以动态随机存取存储器为例进行说明。
参阅图1，该存储器包括字线4、位线1、晶体管2和电容器3，其中，晶体管2的栅极与字线4电性连接，晶体管2的源极和漏极中的一者与位线1电性连接，另一 者与电容器3电性连接。字线4用于控制晶体管2的打开或关闭，位线1用于将数据信息写入电容器3，或者读取电容器3中的数据信息。如图1所示，晶体管2和电容器3均沿第二方向延伸(图1所示Z方向)，该方向与衬底平行，即晶体管2和电容器3均平行于衬底设置，以便于制作较大长细比的电容器3，从而提高存储器的存储容量。
参阅图2，图2为本公开一实施例的存储器的制作方法的流程图，该制作方法可以包括：
步骤S10：提供衬底。
参阅图3，衬底10可以为衬底10上的结构层提供支撑基础，衬底10的材质可以为半导体，例如，衬底10的材质可以为单晶硅、多晶硅、无定型硅、锗、碳化硅、锗硅(Silicon Germanium,SiGe)、绝缘体上锗(Germanium on Insulator，简称GOI)或者绝缘体上硅(Silicon on Insulator，简称SOI)等。
在一些可能的实施例中，衬底10包括第一区域和第二区域，第一区域如图3中B处所示，第二区域如图3中A处所示，第一区域与第二区域相邻，例如，第一区域与第二区域相邻且连接。其中，第一区域上可以设置有半导体器件，例如晶体管2，第二区域上可以设置有连接结构，例如连接层60(参阅图*)。通过第二区域上的结构将第一区域上的半导体器件引出，以使半导体器件与外围电路电性连接。位于第一区域的衬底10和位于第二区域的衬底10为一个整体，以便于提供衬底10。
步骤S20：在衬底上形成叠层结构，叠层结构包括沿第一方向交替堆叠设置的牺牲层和有源层。
参阅图3，叠层结构20包括多个牺牲层21和多个有源层22，多个牺牲层21和多个有源层22沿第一方向交替堆叠设置。其中，第一方向为垂直于衬底10的方向，如图3所示Y方向。沿第一方向，相邻两个牺牲层21之间设置有有源层22，或者相邻两个有源层22之间设置有牺牲层21，以使得牺牲层21和有源层22依次交替设置。如此排布，通过牺牲层21可以将相邻两个有源层22隔离开来，以便于使有源层22沿第一方向电性隔离。
具体的，在衬底10上形成叠层结构20，包括：在衬底10上依次交替重复形成一层牺牲层21和一层有源层22，直至形成叠层结构20，且叠层结构20靠近衬底10的最内层为牺牲层21，叠层结构20远离衬底10的最外层为有源层22。具体的，形成叠层结构20时，在衬底10上形成一层牺牲层21，再在牺牲层21上形成一层有源层22，再在有源层22上形成一层牺牲层21，重复有源层22和牺牲层21的形成过程，直至形成所需层数的牺牲层21和有源层22。
如图3所示，叠层结构20靠近衬底10的最内层为牺牲层21，使得该牺牲层21上的有源层22与衬底10之间间隔开来，每层有源层22后续都可以形成晶体管2，增加了晶体管2的数量，从而提高半导体结构的存储容量。叠层结构20远离衬底10的最外层为有源层22，如此设置，当叠层结构20具有相同层数的有源层22时，叠层结构20的高度降低，以便于后续刻蚀叠层结构20。
在一些可能的实现方式中，在衬底10上通过沉积工艺形成牺牲层21和形成有源层22，沉积工艺可以包括化学气相沉积(Chemical Vapor Deposition，简称CVD)、 物理气相沉积(Physical Vapor Deposition，简称PVD)或者原子层沉积(Atomic Layer Deposition，简称ALD)等。
在另一些可能的实现方式中，由衬底10通过外延生长工艺(Epitaxy，简称EPI)形成牺牲层21和有源层22。具体的，衬底10、有源层22和牺牲层21具体同样的元素，例如硅元素，以在衬底10上外延生长牺牲层21，在牺牲层21上外延生长有源层22，并在有源层22上外延生长牺牲层21。示例性的，衬底10的材质包括硅，有源层22的材质包括硅，牺牲层21的材质包括锗硅。一方面便于外延生长形成有源层22和牺牲层21，另一方面牺牲层21与有源层22具有较大的选择比，后续可以单独去除牺牲层21，减少去除牺牲层21时对有源层22的损伤。优选的，有源层22的材质包括有掺杂的硅，例如，有源层22的材质包括N型掺杂的硅，以提高有源层22的电学性能。
步骤S30：去除位于第一区域的部分叠层结构，形成多条间隔设置且沿第二方向延伸的第一沟槽，第一沟槽暴露衬底，以将位于第一区域的有源层分隔成多个间隔设置的有源柱。
参阅图4，在位于第一区域的叠层结构20中形成多条第一沟槽51，多条第一沟槽51间隔设置且沿第二方向延伸，第二方向为图1所示水平方向(Z方向)，其平行于衬底10，与第一方向相垂直。第一沟槽51贯穿位于第一区域的叠层结构20，以暴露衬底10。
在一些可能的实施例中，参阅图5，第一沟槽51可以延伸至衬底10中，即第一沟槽51的槽底位于衬底10中。如此设置，可以保证第一沟槽51将叠层结构20分隔成多个分体，从而使得叠层结构20中的各有源层22均分隔成多个间隔设置的有源柱50，以提高有源柱50的数量，增加半导体结构的存储容量。
如图4和图5所示，多个有源柱50呈阵列排布，多个有源柱50沿第二方向延伸。多个有源柱50沿第一方向间隔排布，且沿第三方向间隔排布，第三方向与第一方向互相交叉，且均与第二方向垂直。其中，第三方向为平行于衬底10的方向，示例性的，第三方向为图4和图5所示水平方向(X方向)，第一方向、第二方向和第三方向两两垂直。这种排布方式，可以使有源柱50的排布更紧凑，最大程度提高有源柱50的排布数量。有源柱50包括源极、漏极，以及位于源极和漏极之间的沟道。有源柱50的形状可以是圆柱体、棱柱体、长方体或其他形状，本公开实施例中对此不是限定的。
具体的，去除位于第一区域的部分叠层结构20，形成多条间隔设置且沿第二方向延伸的第一沟槽51，包括：刻蚀位于第一区域的叠层结构20，形成第一沟槽51，第一沟槽51贯穿叠层结构20。
参阅图4至图7，在一些可能的实现方式中，刻蚀位于第一区域的叠层结构20，形成第一沟槽51，第一沟槽51贯穿叠层结构20，包括：
在叠层结构20上形成第一掩膜层40，位于第一区域的第一掩膜层40具有第一图案。第一掩膜层40形成在叠层结构20上，位于第一区域和位于第二区域的叠层结构20上均覆盖有第一掩膜层40，位于第一区域的第一掩膜层40具有第一图案，以暴露部分位于第一区域的叠层结构20，位于第二区域的叠层结构20未暴露。
以第一掩膜层40为掩膜，刻蚀位于第一区域的叠层结构20，形成第一沟槽51。通过以第一掩膜层40为掩膜刻蚀叠层结构20，从而将第一图案转移到位于第一区域的叠层结构20中，以在叠层结构20中形成第一沟槽51。
在另一些可能的实现方式中，在叠层结构20上形成第一掩膜层40，包括：在叠层结构20上形成保护层30，在保护层30上形成第一掩膜层40。参阅图4和图6，叠层结构20上覆盖有保护层30，保护层30可以氧化硅层，以减少或者避免有源层22氧化。参阅图6和图7，保护层30上覆盖有第一掩膜层40，位于第一区域的第一掩膜层40具有第一图案。
相应的，参阅图7和图5，以第一掩膜层40为掩膜，刻蚀位于第一区域的叠层结构20，包括：以第一掩膜层40为掩膜，刻蚀位于第一区域的保护层30，以将第一图案转移至保护层30中；去除第一掩膜层40，以图形化的保护层30继续刻蚀叠层结构20。也就是说，先将第一掩膜层40的第一图案转移到位于第一区域的保护层30中；再去除第一掩膜层40，以使保护层30暴露；并以图形化的保护层30为掩膜，继续刻蚀叠层结构20，以在叠层结构20中形成第一沟槽51。
步骤S40：利用第一沟槽，去除位于第一区域和第二区域的牺牲层，以使位于第一区域的有源柱和第二区域的有源层均沿第一方向间隔设置，其中，第二区域与第一区域相邻。
参阅图5和图8，第一区域和第二区域的牺牲层21完全去除，位于第一区域的有源柱50沿第一方向间隔设置，位于第二区域的有源层22沿第一方向间隔排布。在一些可能的实现方式中，利用第一沟槽51，去除位于第一区域和第二区域的牺牲层21，包括：利用第一沟槽51暴露出牺牲层21的侧壁，通过湿法刻蚀工艺去除位于第一区域和第二区域的牺牲层21。湿法刻蚀工艺具有较好的选择比，利用湿法刻蚀去除牺牲层21时，可以避免损伤暴露出来的有源层22、有源柱50以及衬底10。
步骤S50：去除位于第二区域的部分有源层，以在第二区域远离第一区域的一端形成呈台阶状的多个连接层。
参阅图9，去除位于第二区域的部分有源层22，位于第二区域剩余的有源层22形成连接层60，沿远离衬底10的方向，多个连接层60的长度依次减小，以使多个连接层60远离第一区域的一端形成呈台阶状。如图9所示，该台阶状沿第一方向向上，且沿第三方向向上，第一方向为垂直于衬底10的方向，如图9所示Y方向，第三方向为平行于衬底10的方向，如图9所示X方向。每一层的连接层60的部分表面暴露，以便于在连接层60上形成其他结构。具体的，每一层的连接层60背离衬底10的表面中，远离第一区域的部分表面暴露出来，即每一层的连接层60的上表面中的左端暴露。
在一些可能的实施例中，去除位于第二区域的部分有源层22，以在第二区域远离第一区域的一端形成呈台阶状的多个连接层60，包括：在有源层22上形成第二掩膜层，位于第二区域的第二掩膜层具有第二图案；以第二掩膜层为掩膜，刻蚀位于第二区域的有源层22，以在第二区域远离第一区域的一端形成呈台阶状的多个连接层60；去除第二掩膜层。
在上述实施例中，每层有源层22对应不同尺寸的第二掩膜层，通过逐次限缩第 二掩膜层并刻蚀至对应的有源层22，以形成所需连接层60。具体的，先在有源层22上形成第二掩膜层，以其为掩膜，刻蚀至最下层的有源层22，以使最下层的有源层22形成连接层60；再去除远离第一区域的部分第二掩膜层，以去除后的第二掩膜层为掩膜，刻蚀至倒数第二层的有源层22，以使倒数第二层的有源层22形成连接层60；……；以此类推，直至最上层的有源层22形成连接层60。其中，最下层是指有源层22中最靠近衬底10的一层，最上层是指有源层22中最远离衬底10的一层。
步骤S60：形成栅极材料层包覆连接层和有源柱，且位于同一层的连接层和有源柱上形成的栅极材料层相互连通，位于不同层的连接层和有源柱上形成的栅极材料层相互隔离。
参阅图10，形成栅极材料层70后，同层设置的连接层60和有源柱50上的栅极材料层70互相连通，异层设置的连接层60和有源柱50上的栅极材料层70相互隔离，以使栅极材料层70沿第一方向电性隔离。多个栅极材料层70呈台阶状，其长度呈阶梯变化，具体的，沿远离衬底10的方向，栅极材料层70的长度逐渐减小。
其中，栅极材料层70包括栅介质层和栅导电层，栅介质层覆盖有源柱50的外周面，栅导电层覆盖栅介质层的外周面且沿第二方向形成一体，该部分栅导电层可以用于晶体管2的栅极。如图10所示，栅导电层还延伸至连接层60，其至少覆盖连接层60沿第一方向相对的两个表面。栅导电层与连接层60之间也可以设置栅介质层，以使连接层60和有源柱50上的栅介质层一同形成，便于栅介质层的制作。栅介质层的材质可以为氧化硅，栅导电层的材质可以为氮化钛。栅导电层用作字线4，字线4易于制作且易于引出。
在一些可能的实施例中，形成栅极材料层70包覆连接层60和有源柱50，包括：
形成栅介质层覆盖连接层60和有源柱50的表面，各连接层60和各有源柱50表面上的栅介质层之间具有间隙。示例性的，在连接层60和有源柱50的表面沉积栅介质层，栅介质层覆盖有源柱50的外周面，且至少覆盖连接层60沿第一方向相对的两个表面，以及朝向有源柱50的表面。在有源柱50包括源极、沟道和漏极的实施例中，栅介质层与沟道相对。
沉积栅导电层覆盖栅介质层的表面。同层设置的栅介质层上的栅导电层相互连通，异层设置的栅介质层上的栅导电层相互隔离。即栅导电层形成多层，多层栅导电层沿第一方向间隔设置，每层栅导电层覆盖同层设置的栅介质层的表面且填充在各栅介质层之间。栅导电层形成字线4，位于第一区域的栅导电层用作栅极，栅极为字线4的一部分，位于第二区域的栅导电层作为栅极的引出端，以连接外围电路。
需要说明的是，在形成栅极材料层70包覆连接层60和有源柱50同时，还包括：在位于第一区域和第二区域的衬底10上形成栅极材料层70，衬底10上的栅极材料层70与有源柱50上的栅极材料层70、连接层60上的栅极材料层70之间均相互隔离。如图10所示，位于第一区域的有源柱50与衬底10之间具有间隙，位于第二区域的连接层60与衬底10之间具有间隙，因此，在沉积栅极材料层70时，栅极材料层70也会覆盖第一区域和第二区域的衬底10，衬底10上的栅极材料层70与有源柱50上的栅极材料层70间隔设置，且与连接层60上的栅极材料层70间隔设置，以使得各栅极材料层70均互相隔离。
在一些可能的实施例中，形成栅极材料层70包覆连接层60和有源柱50，且位于同一层的连接层60和有源柱50上形成的栅极材料层70相互连通，位于不同层的连接层60和有源柱50上形成的栅极材料层70相互隔离(步骤S60)之后，还包括：形成多个间隔设置且沿第一方向延伸的接触插塞80，每个接触插塞80与位于第二区域的一个栅极材料层70相接触。
参阅图11，多个接触插塞80用于将栅极材料层70连接至外围电路，多个接触插塞80间隔设置，以保证多个接触插塞80之间绝缘隔离，从而避免栅极材料层70之间相互干扰。多个接触插塞80与多个栅极材料层70一一对应且相接触，从而将每个栅极材料层70均可以电连接至外围电路，通过外围电路控制该栅极材料层70相对应的晶体管2。
接触插塞80可以包括第一导电部分，以及设置在第一导电部分上的第二导电部分，第一导电部分为靠近衬底10的部分，第二导电部分为远离衬底10的部分，即第二导电部分位于第一导电部分远离衬底10的一侧。第一导电部分和第二导电部分均可以包括芯层，以及覆盖芯层的侧面和底面的外层。其中，芯层可以为绝缘层，其材质可以为氮化硅或者氧化硅。外层可以为金属层，其材质可以为钨或者氮化钛。如此设置，在保证第一导电部分和第二导电部分的电性能的基础上，减少金属层的厚度，以节约成本。
需要说明的是，本公开实施例中的衬底10还具有第三区域，第三区域与第一区域相邻，第三区域如图11中C处所示，第三区域上可以形成电容器3。电容器3通常在栅极材料层70形成之后再进行制作。
具体的，参阅图12，在衬底10上形成叠层结构20，叠层结构20包括沿第一方向交替堆叠设置的牺牲层21和有源层22时，衬底10的第一区域、第二区域和第三区域上均形成叠层结构20，位于第一区域的叠层结构20后续形成有源柱50，位于第二区域的叠层结构20后续形成连接层60，位于第三区域的叠层结构20后续形成电容器3的支撑层。
参阅图13和图14，在叠层结构20上形成保护层30，在保护层30上形成第一掩膜层40时，位于第一区域、第二区域和第三区域的叠层结构20上均形成保护层30和第一掩膜层40，且在后续的制作过程中，位于第三区域的保护层30和第一掩膜层40一直保留，直至形成栅极材料层70。如此设置，以防止制作字线4过程中损伤第三区域的有源层22。
综上，本公开实施例提供的存储器的制作方法中，在衬底10上形成叠层结构20，叠层结构20包括沿第一方向交替堆叠设置的牺牲层21和有源层22；去除牺牲层21以及部分有源层22，使得位于第一区域的有源层22形成多个间隔设置的有源柱50，并使得位于第二区域的有源层22形成呈台阶状的多个连接层60；再在连接层60和有源柱50上形成栅极材料层70，位于同一层的连接层60和有源柱50上形成的栅极材料层70相互连通，位于不同层的连接层60和有源柱50上形成的栅极材料层70相互隔离。栅极材料层70用作字线4，通过设置连接层60，便于制作字线4，并将字线4引出。此外，由于多个连接层60远离第一区域的一端形成呈台阶状，从而使得覆盖在有源柱50和连接层60上的栅极材料层70远离第一区域的一端也形成呈台阶状， 即字线4呈台阶状，便于在字线4上制作其他结构，以实现字线4与外围电路的电性连接。
本公开实施例第二方面提供一种存储器，参阅图1和图11，存储器具有相邻的第一区域和第二区域，第一区域如图11中B处所示，第二区域如图11中A处所示，第一区域与第二区域相邻，例如，第一区域与第二区域相邻且连接。第一区域上可以设置有半导体器件，例如晶体管2，第二区域上可以设置有连接结构，例如连接层60，通过第二区域上的结构将第一区域上的半导体器件引出，以使半导体器件与外围电路电性连接。该存储器包括：位于第二区域且沿第一方向间隔设置的多个连接层60，且多个连接层60远离第一区域的一端形成呈台阶状。
参阅图11，多个连接层60位于第二区域，其沿第一方向堆叠设置，且多个连接层60间隔设置，以保证多个连接层60之间电性隔离。多个连接层60远离第一区域的一端形成台阶，如图11所示，多个连接层60的左端形呈台阶状。具体的，该台阶状沿第一方向向上，且沿第三方向向上，第一方向为垂直于衬底10的方向，如图11所示Y方向，第三方向为平行于衬底10的方向，如图11所示X方向。
在一些可能的示例中，参阅图11，沿远离衬底10的方向，多个连接层60的长度依次减小，以使多个连接层60远离第一区域的一端形成呈台阶状。如图11所示，每一层的连接层60的部分表面暴露，以便于在连接层60上形成其他结构。具体的，每一层的连接层60背离衬底10的表面中远离第一区域的部分表面暴露出来。
继续参阅图11，存储器还包括：位于第一区域且沿第一方向间隔设置的多个有源柱层，每个有源柱层与一个连接层60同层设置；每个有源柱层具有多个间隔设置的有源柱50，且各有源柱50沿第二方向延伸。
如图11所示，多个有源柱层位于第一区域，其沿第一方向堆叠设置，且多个有源柱层50间隔设置，以保证多个有源柱层之间电性隔离。多个有源柱层与多个连接层60一一对应，且相对应的有源柱层和连接层60同层设置，以便于在有源柱层和连接层60上形成栅极材料层70。
如图11所示，每个有源柱层包括多个间隔设置的有源柱50，多个有源柱50沿第二方向延伸。多个有源柱50呈阵列排布，具体的，多个有源柱50沿第一方向间隔排布，且沿第三方向间隔排布，第三方向与第一方向互相交叉，且均与第二方向垂直。其中，第二方向为平行于衬底10的方向，示例性的，第二方向为图1所示水平方向(Z方向)，第一方向、第二方向和第三方向两两垂直。这种排布方式，可以使有源柱50的排布更紧凑，最大程度提高有源柱50的排布数量。有源柱50的形状可以是圆柱体、棱柱体、长方体或其他形状，本公开实施例中对此不是限定的。
继续参阅图11，存储器还包括：位于连接层60上和有源柱50上的栅极材料层70，且位于同一层的连接层60和有源柱50上形成的栅极材料层70相互连通，位于不同层的连接层60和有源柱50上形成的栅极材料层70相互隔离。
如图11所示，同层设置的连接层60和有源柱50上的栅极材料层70互相连通，异层设置的连接层60和有源柱50上的栅极材料层70相互隔离，以使栅极材料层70沿第一方向电性隔离。由于连接层60层台阶状，多个栅极材料层70呈台阶状，其长 度呈阶梯变化，以便于在栅极材料层70上形成其他结构，从而将栅极材料层70引出。具体的，沿远离衬底10的方向，栅极材料层70的长度逐渐减小。
其中，栅极材料层70包括栅介质层和栅导电层，栅介质层覆盖有源柱50的外周面，栅导电层覆盖栅介质层的外周面且沿第二方向形成一体，该部分栅导电层可以用于晶体管2的栅极。如图11所示，栅导电层还延伸至连接层60，其至少覆盖连接层60沿第一方向相对的两个表面。栅导电层与连接层60之间也可以设置栅介质层，以使连接层60和有源柱50上的栅介质层一同形成，便于栅介质层的制作。栅介质层的材质可以为氧化硅，栅导电层的材质可以为氮化钛。栅导电层用作字线4，字线4易于制作且易于引出。
在一些可能的实施例中，存储器还包括：多个间隔设置且沿第一方向延伸的接触插塞80，每个接触插塞80与位于第二区域的一个栅极材料层70相接触。
具体的，参阅图11，多个接触插塞80用于将栅极材料层70连接至外围电路，多个接触插塞80间隔设置，以保证多个接触插塞80之间绝缘隔离，从而避免栅极材料层70之间相互干扰。多个接触插塞80与多个栅极材料层70一一对应且相接触，从而将每个栅极材料层70均可以电连接至外围电路，通过外围电路控制该栅极材料层70相对应的晶体管2。
接触插塞80可以包括第一导电部分，以及设置在第一导电部分上的第二导电部分，第一导电部分为靠近衬底10的部分，第二导电部分为远离衬底10的部分，即第二导电部分位于第一导电部分远离衬底10的一侧。第一导电部分和第二导电部分均可以包括芯层，以及覆盖芯层的侧面和底面的外层。其中，芯层可以为绝缘层，其材质可以为氮化硅或者氧化硅。外层可以为金属层，其材质可以为钨或者氮化钛。如此设置，在保证第一导电部分和第二导电部分的电性能的基础上，减少金属层的厚度，以节约成本。
在一些可能的实施例中，存储器还具有第三区域，第三区域与第一区域相邻，存储器还包括：位于第三区域的多个间隔设置的电容器3，电容器3沿第二方向延伸，且每个电容器3与一个有源柱50电连接。具体的，第三区域与第一区域可以沿第二方向(图11所示Z方向)排布，第三区域设置有多个间隔设置的电容器3，多个电容器3与多个有源柱50一一对应且电连接。
本公开实施例提供的存储器，通过在连接层60上和有源柱50上设置栅极材料层70，且位于同一层的连接层60和有源柱50上形成的栅极材料层70相互连通，位于不同层的连接层60和有源柱50上形成的栅极材料层70相互隔离，栅极材料层70用作字线4，通过设置连接层60，便于制作字线4，并将字线4引出。此外，由于多个连接层60远离第一区域的一端形成呈台阶状，从而使得覆盖在有源柱50和连接层60上的栅极材料层70远离第一区域的一端也形成呈台阶状，即字线4呈台阶状，便于在字线4上制作其他结构，以实现字线4与外围电路的电性连接。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材 料或者特点包含于本公开的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (18)

  1. 一种存储器的制作方法，包括：
    提供衬底；
    在所述衬底上形成叠层结构，所述叠层结构包括沿第一方向交替堆叠设置的牺牲层和有源层；
    去除位于第一区域的部分所述叠层结构，形成多条间隔设置且沿第二方向延伸的第一沟槽，所述第一沟槽暴露所述衬底，以将位于所述第一区域的所述有源层分隔成多个间隔设置的有源柱；
    利用所述第一沟槽，去除位于所述第一区域和第二区域的所述牺牲层，以使位于所述第一区域的所述有源柱和所述第二区域的所述有源层均沿所述第一方向间隔设置，其中，所述第二区域与所述第一区域相邻；
    去除位于所述第二区域的部分所述有源层，以在所述第二区域远离所述第一区域的一端形成呈台阶状的多个连接层；
    形成栅极材料层包覆所述连接层和所述有源柱，且位于同一层的所述连接层和所述有源柱上形成的所述栅极材料层相互连通，位于不同层的所述连接层和所述有源柱上形成的所述栅极材料层相互隔离。
  2. 根据权利要求1所述的制作方法，其中，沿远离所述衬底的方向，多个所述连接层的长度依次减小，以使多个所述连接层远离所述第一区域的一端形成呈台阶状。
  3. 根据权利要求1所述的制作方法，其中，在所述衬底上形成叠层结构，包括：
    在所述衬底上依次交替重复形成一层所述牺牲层和一层所述有源层，直至形成所述叠层结构，且所述叠层结构靠近所述衬底的最内层为所述牺牲层，所述叠层结构远离所述衬底的最外层为所述有源层。
  4. 根据权利要求1所述的制作方法，其中，由所述衬底通过外延生长工艺形成所述牺牲层和所述有源层。
  5. 根据权利要求4所述的制作方法，其中，所述有源层的材质包括N型掺杂的硅，所述牺牲层的材质包括锗硅。
  6. 根据权利要求1所述的制作方法，其中，去除位于所述第一区域的部分所述叠层结构，形成多条间隔设置且沿所述第二方向延伸的所述第一沟槽，包括：
    刻蚀位于所述第一区域的所述叠层结构，形成所述第一沟槽，所述第一沟槽贯穿所述叠层结构。
  7. 根据权利要求6所述的制作方法，其中，刻蚀位于所述第一区域的所述叠层结构，形成所述第一沟槽，所述第一沟槽贯穿所述叠层结构，包括：
    在所述叠层结构上形成第一掩膜层，位于所述第一区域的所述第一掩膜层具有第一图案；
    以所述第一掩膜层为掩膜，刻蚀位于所述第一区域的所述叠层结构，形成所述第一沟槽。
  8. 根据权利要求7所述的制作方法，其中，利用所述第一沟槽，去除位于所述第一区域和所述第二区域的所述牺牲层，包括：
    利用所述第一沟槽暴露出所述牺牲层的侧壁，通过湿法刻蚀工艺去除位于所述第一区域和所述第二区域的所述牺牲层。
  9. 根据权利要求7所述的制作方法，其中，在所述叠层结构上形成所述第一掩膜层，包括：
    在所述叠层结构上形成保护层，在所述保护层上形成所述第一掩膜层。
  10. 根据权利要求9所述的制作方法，其中，以所述第一掩膜层为掩膜，刻蚀位于所述第一区域的所述叠层结构，包括：
    以所述第一掩膜层为掩膜，刻蚀位于所述第一区域的所述保护层，以将所述第一图案转移至所述保护层中；
    去除所述第一掩膜层，以图形化的所述保护层继续刻蚀所述叠层结构。
  11. 根据权利要求1所述的制作方法，其中，去除位于所述第二区域的部分所述有源层，以在所述第二区域远离所述第一区域的一端形成呈台阶状的多个所述连接层，包括：
    在所述有源层上形成第二掩膜层，位于所述第二区域的所述第二掩膜层具有第二图案；
    以所述第二掩膜层为掩膜，刻蚀位于所述第二区域的所述有源层，以在所述第二区域远离所述第一区域的一端形成呈台阶状的多个所述连接层；
    去除所述第二掩膜层。
  12. 根据权利要求1所述的制作方法，其中，形成栅极材料层包覆所述连接层和所述有源柱，包括：
    形成栅介质层覆盖所述连接层和所述有源柱的表面，各所述连接层和各所述有源柱表面上的所述栅介质层之间具有间隙；
    沉积栅导电层覆盖所述栅介质层的表面。
  13. 根据权利要求12所述的制作方法，其中，同层设置的所述栅介质层上的所述栅导电层相互连通，异层设置的所述栅介质层上的所述栅导电层相互隔离。
  14. 根据权利要求12所述的制作方法，其中，在形成栅极材料层包覆所述连接层和所述有源柱同时，还包括：
    在位于所述第一区域和所述第二区域的所述衬底上形成所述栅极材料层，所述衬底上的所述栅极材料层与所述有源柱上的所述栅极材料层、所述连接层上的所述栅极材料层之间均相互隔离。
  15. 根据权利要求1所述的制作方法，其中，形成栅极材料层包覆所述连接层和所述有源柱，且位于同一层的所述连接层和所述有源柱上形成的所述栅极材料层相互连通，位于不同层的所述连接层和所述有源柱上形成的所述栅极材料层相互隔离之后，还包括：
    形成多个间隔设置且沿所述第一方向延伸的接触插塞，每个所述接触插塞与位于所述第二区域的一个所述栅极材料层相接触。
  16. 一种存储器，所述存储器具有相邻的第一区域和第二区域，所述存储器包括：
    位于所述第二区域且沿第一方向间隔设置的多个连接层，且多个所述连接层远离所述第一区域的一端形成呈台阶状；
    位于所述第一区域且沿所述第一方向间隔设置的多个有源柱层，每个所述有源柱层与一个所述连接层同层设置；每个所述有源柱层具有多个间隔设置的有源柱，且各所述有源柱沿第二方向延伸；
    位于所述连接层上和所述有源柱上的栅极材料层，且位于同一层的所述连接层和所述有源柱上形成的所述栅极材料层相互连通，位于不同层的所述连接层和所述有源柱上形成的所述栅极材料层相互隔离。
  17. 根据权利要求16所述的存储器，其中，所述存储器还具有第三区域，所述第三区域与所述第一区域相邻，所述存储器还包括：
    位于所述第三区域的多个间隔设置的电容器，所述电容器沿所述第二方向延伸，且每个所述电容器与一个所述有源柱电连接。
  18. 根据权利要求16所述的存储器，其中，所述存储器还包括：
    多个间隔设置且沿所述第一方向延伸的接触插塞，每个所述接触插塞与位于所述第二区域的一个所述栅极材料层相接触。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9449986B1 (en) * 2015-10-13 2016-09-20 Samsung Electronics Co., Ltd. 3-dimensional memory device having peripheral circuit devices having source/drain contacts with different spacings
CN107665895A (zh) * 2016-07-27 2018-02-06 三星电子株式会社 垂直存储器件及其制造方法
CN109524417A (zh) * 2018-11-27 2019-03-26 长江存储科技有限责任公司 3d nand存储器及其形成方法
CN112466881A (zh) * 2020-11-04 2021-03-09 长江存储科技有限责任公司 三维存储器及其制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101528823B1 (ko) * 2009-01-19 2015-06-15 삼성전자주식회사 반도체 메모리 소자 및 그 제조 방법
US10269620B2 (en) * 2016-02-16 2019-04-23 Sandisk Technologies Llc Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
CN110544693B (zh) * 2018-05-29 2024-05-17 长鑫存储技术有限公司 半导体存储单元的制造方法及半导体存储单元

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9449986B1 (en) * 2015-10-13 2016-09-20 Samsung Electronics Co., Ltd. 3-dimensional memory device having peripheral circuit devices having source/drain contacts with different spacings
CN107665895A (zh) * 2016-07-27 2018-02-06 三星电子株式会社 垂直存储器件及其制造方法
CN109524417A (zh) * 2018-11-27 2019-03-26 长江存储科技有限责任公司 3d nand存储器及其形成方法
CN112466881A (zh) * 2020-11-04 2021-03-09 长江存储科技有限责任公司 三维存储器及其制备方法

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