WO2023201888A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

Info

Publication number
WO2023201888A1
WO2023201888A1 PCT/CN2022/102336 CN2022102336W WO2023201888A1 WO 2023201888 A1 WO2023201888 A1 WO 2023201888A1 CN 2022102336 W CN2022102336 W CN 2022102336W WO 2023201888 A1 WO2023201888 A1 WO 2023201888A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
layer
display substrate
substrate
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/102336
Other languages
English (en)
French (fr)
Inventor
许程
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP22790435.6A priority Critical patent/EP4287810A4/en
Priority to JP2022573738A priority patent/JP2025513959A/ja
Priority to CN202280002029.6A priority patent/CN117280887A/zh
Priority to KR1020227033452A priority patent/KR20250004402A/ko
Priority to US18/020,301 priority patent/US20240276772A1/en
Publication of WO2023201888A1 publication Critical patent/WO2023201888A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80517—Multilayers, e.g. transparent multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/874—Passivation; Containers; Encapsulations including getter material or desiccant
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/878—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/879—Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • micro organic light-emitting diode (Micro-OLED) display device is a new type of OLED display device based on silicon substrate, also called silicon-based organic light-emitting diode (Micro-OLED).
  • silicon-based OLED display device Referred to as silicon-based OLED) display device.
  • Silicon-based OLED display devices have the advantages of small size and high resolution. They are manufactured using CMOS integrated circuit technology, which can realize active addressing of pixels, and can be prepared on silicon-based substrates including TCON (timing control) circuits, OCP ( Operation control) circuits and other functional circuits can achieve lightweighting.
  • Micro OLED (Micro OLED) displays have excellent display characteristics, such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, low power consumption, etc., and have broad development prospects.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a driving substrate, an anode layer, a pixel defining layer, a light-emitting functional layer, a cathode layer and a packaging layer;
  • the driving substrate includes a substrate and a driving circuit;
  • the anode layer is located on the driving substrate;
  • the pixel defining layer is located on the anode layer away from the driving substrate One side;
  • the light-emitting functional layer is located on the side of the anode layer away from the driving substrate;
  • the cathode layer is located on the side of the light-emitting functional layer away from the driving substrate;
  • the packaging layer is located on the side of the cathode layer away from the driving substrate;
  • the driving circuit includes at least one transistor, and the transistor includes a semiconductor layer, the semiconductor layer is at least partially located inside the substrate;
  • the anode layer includes a plurality of anodes,
  • the display substrate includes
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a driving substrate, including a substrate and a driving circuit; a first flat layer located on the driving circuit; and an anode layer located away from the first flat layer.
  • a driving substrate including a substrate and a driving circuit
  • a first flat layer located on the driving circuit
  • an anode layer located away from the first flat layer.
  • One side of the driving substrate a pixel defining layer, located on the side of the anode layer away from the driving substrate; a light-emitting functional layer, located on the side of the anode layer away from the driving substrate; a cathode layer, located on the side of the light-emitting function layer layer away from the side of the drive substrate; and an encapsulation layer, located on the side of the cathode layer away from the drive substrate;
  • the drive circuit includes at least one transistor, the transistor includes a semiconductor layer, and the semiconductor layer is at least partially Located inside the substrate, the anode layer includes a
  • the distances are equal, and the distance between the surface of the main body part away from the substrate and the surface of the first flat layer away from the substrate is smaller than the distance between the surface of the protrusion part away from the substrate and the first flat layer. distance away from the surface of the substrate.
  • the protruding portion is provided around the main body portion.
  • the orthographic projection of the pixel defining layer on the driving substrate overlaps with the orthographic projection of the protruding portion on the driving substrate.
  • the pixel defining layer includes a pixel defining portion, and the pixel defining portion includes: a pixel defining flat portion located between two adjacent anodes; and protruding structures, respectively located on the side of the protruding portions of two adjacent anodes away from the driving substrate, and the pixel defines a flat portion connecting the protruding structures.
  • the pixel defining portion is arranged symmetrically about the center of the spacing area between the two adjacent anodes.
  • each of the protruding structures includes: a first side wall located on a side of the protruding structure close to the center of the main body; and a second side wall, Connected to the first side wall, the second side wall is further away from the driving substrate relative to the first side wall; the slope angle of the first side wall is greater than the slope angle of the second side wall.
  • the slope angle of the first side wall ranges from 75 to 89 degrees
  • the slope angle of the second side wall ranges from 15 degrees to 15 degrees. -45 degree.
  • each of the protruding structures further includes: a third side wall located on a side of the protruding structure close to the flat portion defining the pixel, wherein the third side wall The slope angles of the three side walls are greater than the slope angle of the second side wall and smaller than the slope angle of the first side wall.
  • each of the protruding structures further includes: a third side wall located on a side of the protruding structure close to the flat portion defining the pixel, and the first side wall
  • the slope angle of the wall is ⁇
  • the slope angle of the second side wall is ⁇
  • the slope angle of the third side wall is ⁇
  • the following formula is satisfied: ⁇ .
  • the difference between the slope angle of the first side wall and the slope angle of the second side wall is equal to i of the slope angle of the third side wall. times, the value range of i is 0.8-1.2.
  • the difference between the slope angle of the first side wall and the slope angle of the second side wall is equal to the slope angle of the second side wall and the slope angle of the second side wall. j times the difference in slope angles of the three side walls, and the value range of j is 1.5-3.
  • the sum of the slope angle of the first side wall and the slope angle of the second side wall is equal to k times the slope angle of the third side wall.
  • the value range of k is 2-3.
  • the slope angle of the third side wall ranges from 45 to 60 degrees.
  • the size of the orthographic projection of the third side wall on the driving substrate in the second direction is larger than the size of the second side wall on the driving substrate.
  • the dimension of the orthographic projection of the second side wall on the driving substrate in the second direction is greater than the dimension of the first side wall on the driving substrate.
  • the size of the orthographic projection in the second direction, the second direction being the direction from the raised portion to the main body portion or the direction from the main body portion to the raised portion, the second The direction is parallel to the surface of the driving substrate away from the anode layer.
  • the size of the first side wall in the first direction is H1
  • the size of the second side wall in the first direction is H1.
  • H2 the size of the third side wall in the first direction is H3, H1, H2 and H3 satisfy the following formula:
  • the raised portion of each anode includes a fourth side wall located on a side of the raised portion close to the center of the main body, so The slope angle of the fourth side wall is greater than the slope angle of the second side wall and smaller than the slope angle of the first side wall.
  • the raised portion of each anode includes a fourth side wall located on a side of the raised portion close to the center of the main body, so The slope angle of the fourth side wall is ⁇ , and satisfies the following formula: ⁇ .
  • the protruding portion of each anode includes: a first sub-anode layer located on a side of the driving circuit away from the substrate; a second sub-anode layer; A sub-anode layer is located on a side of the first sub-anode layer away from the driving substrate; and a third sub-anode layer is located on a side of the second sub-anode layer away from the driving substrate.
  • the size of the first sub-anode layer in the second direction is larger than the size of the third sub-anode layer in the second direction
  • the The size of the third sub-anode layer in the second direction is larger than the size of the second sub-anode layer in the second direction
  • the second direction is from the protruding portion to the main body portion. direction or a direction from the main body portion to the protruding portion, the second direction is parallel to a surface of the driving substrate away from the anode layer.
  • an end of the first sub-anode layer away from the main body portion includes a raised portion, and the thickness of the raised portion in the first direction is greater than the thickness of the first sub-anode layer.
  • the average thickness of the first sub-anode layer in the first direction is greater than the thickness of the first sub-anode layer.
  • an end of the third sub-anode layer away from the main body portion is bent in a direction closer to the first sub-anode layer.
  • the protruding portion of each anode further includes: a fourth sub-anode layer located between the second sub-anode layer and the third sub-anode layer. time, the size of the fourth sub-anode layer in the second direction is smaller than the size of the second sub-anode layer in the second direction.
  • the size of the third sub-anode layer beyond the fourth sub-anode layer in the second direction is smaller than the size of the pixel defining layer in the driving direction.
  • the second sub-anode layer includes a fifth sidewall located on a side of the second sub-anode layer away from the main body
  • the fourth The sub-anode layer includes a sixth side wall located on a side of the fourth sub-anode layer away from the main body.
  • the slope angle of the fifth side wall is greater than the slope angle of the fourth side wall.
  • the sixth side wall The slope angle of the side wall is greater than the slope angle of the fourth side wall, and the slope angle of the fifth side wall is greater than the slope angle of the sixth side wall.
  • the thickness of the first sub-anode layer in the first direction is equal to the thickness of the second sub-anode layer in the first direction.
  • the ratio range is 1/15-1/5.
  • the thickness of the first sub-anode layer in the first direction is equal to the thickness of the third sub-anode layer in the first direction.
  • the ratio range is 1/3-4/5.
  • the thickness of the first sub-anode layer in the first direction and the thickness of the fourth sub-anode layer in the first direction are The ratio range is 1/24-1/8.
  • the range of the ratio of the distance between two adjacent anodes to the length of the orthographic projection of the protruding portion of the anode on the driving substrate is for 2-4.
  • the range of the ratio of the distance between two adjacent anodes to the length of the orthographic projection of the protruding portion of the anode on the driving substrate is is 2.5-3.5.
  • the protruding portion is provided around the main body portion.
  • the shape of the orthographic projection of the anode on the driving substrate includes a hexagon.
  • a display substrate provided by an embodiment of the present disclosure further includes: a reflective electrode layer located on the side of the first flat layer close to the anode layer; and a second flat layer located on the side of the reflective electrode layer close to the anode layer. side of the anode layer.
  • the reflective electrode layer is continuously provided in the pixel opening.
  • a first pore between the light-emitting functional layer and the main body part, and at least one third gap exists between the light-emitting functional layer and the pixel defining layer.
  • Two pores, the space occupied by the first pore is larger than the space occupied by the second pore.
  • the encapsulation layer includes: an inorganic encapsulation layer located on a side of the cathode layer away from the driving substrate, and the inorganic encapsulation layer includes a plurality of sub-inorganic encapsulation layers. layer.
  • a display substrate provided by an embodiment of the present disclosure, there are at least two adjacent sub-inorganic encapsulation layers made of different materials among the plurality of sub-inorganic encapsulation layers. There are at least two adjacent sub-inorganic encapsulation layers made of the same material.
  • the refraction of the plurality of sub-inorganic encapsulation layers first increases and then decreases.
  • the thickness of the plurality of sub-inorganic encapsulation layers in the first direction gradually decreases.
  • each of the sub-inorganic encapsulation layers includes: alternately arranged flat areas and double-arch spacers, and a spacer located in the flat area away from the double-arch spacers. a first arched region on the side, a second arched region located between the flat region and the double arched spacer region, and a third arched region located in the flat region away from the second arched region, The first arched area and the second arched area are arranged symmetrically about the center of the flat area.
  • the size of the flat area in the second direction is L
  • the center of the second arched area and the center of the third arched area are The distance in the second direction is a first distance D1
  • the distance between the center of the first arched area and the center of the second arched area in the second direction is a second distance D2.
  • the curvature radii of the first arched area, the second arched area and the third arched area are all R,
  • the first distance D1 satisfies the following formula:
  • the second direction is a direction from the raised portion to the main body portion or from the main body portion to the raised portion, and the second direction is parallel to the driving substrate and away from the anode layer. s surface.
  • the size of the flat area in the second direction is L
  • the center of the second arched area and the center of the third arched area are The distance in the second direction is a first distance D1
  • the distance between the center of the first arched area and the center of the second arched area in the second direction is a second distance D2.
  • the curvature radii of the first arched area, the second arched area and the third arched area are all R,
  • the first distance D1 satisfies the following formula:
  • the second direction is a direction from the raised portion to the main body portion or from the main body portion to the raised portion, and the second direction is parallel to the driving substrate and away from the anode layer. s surface.
  • the orthographic projection of the first arched area, the second arched area or the third arched area on the driving substrate is different from the The orthographic projection of the protruding portion on the driving substrate overlaps, the orthographic projection of the flat area on the driving substrate overlaps with the orthographic projection of the main body portion on the driving substrate, and the first The distance between the surface of the arched area, the second arched area or the third arched area away from the driving substrate and the driving substrate is greater than the distance between the surface of the flat area away from the driving substrate and the driving substrate. The distance between drive substrates.
  • the orthographic projection of the double-arch spacer on the drive substrate is the same as the spacer between two adjacent anodes on the drive substrate. orthographic projection overlap.
  • the plurality of sub-inorganic encapsulation layers include: a first sub-inorganic encapsulation layer, located on the side of the cathode layer away from the driving substrate; a second sub-inorganic encapsulation layer An encapsulation layer, located on the side of the first sub-inorganic encapsulation layer away from the driving substrate; a third sub-inorganic encapsulation layer, located on the side of the second sub-inorganic encapsulation layer away from the driving substrate; and a fourth sub-inorganic encapsulation layer.
  • An inorganic encapsulation layer is located on the side of the third sub-inorganic encapsulation layer away from the driving substrate.
  • the refractive index of the first sub-inorganic encapsulation layer is smaller than the refractive index of the second sub-inorganic encapsulation layer, and the refractive index of the fourth sub-inorganic encapsulation layer is The refractive index is less than the refractive index of the third sub-inorganic encapsulation layer.
  • the refractive index of the second sub-inorganic encapsulation layer is equal to the refractive index of the third sub-inorganic encapsulation layer.
  • the flat area of the first sub-inorganic encapsulation layer has a first width in the second direction
  • the second sub-inorganic encapsulation layer has a first width in the second direction
  • the flat area has a second width in the second direction
  • the flat area of the third sub-inorganic encapsulation layer has a third width in the second direction
  • the fourth sub-inorganic encapsulation layer has a third width in the second direction.
  • the flat area has a fourth width in the second direction, the first width is greater than the second width, the second width is greater than the third width, and the third width is greater than the fourth width. width.
  • the flat area of the first sub-inorganic encapsulation layer is close to the edge of the first arched area, and all areas of the second sub-inorganic encapsulation layer are close to the edge of the first arched area.
  • the flat area is close to the edge of the first arched area
  • the flat area of the third sub-inorganic encapsulation layer is close to the edge of the first arched area
  • the flat area of the fourth sub-inorganic encapsulating layer is close to the edge of the first arched area.
  • the included angle between the first connection line near the edge of the first arched area and the surface of the driving substrate away from the anode layer is the first included angle
  • the first sub-inorganic encapsulation layer The apex of the first arched region, the apex of the first arched region of the second sub-inorganic encapsulation layer, the apex of the first arched region of the third sub-inorganic encapsulation layer and the fourth
  • the angle between the second connecting line of the vertex of the first arched area of the sub-inorganic encapsulation layer and the surface of the driving substrate away from the anode layer is a second angle, and the first angle is smaller than the Describe the second angle.
  • the first included angle ranges from 60 to 85 degrees
  • the second included angle ranges from 85 to 89 degrees.
  • the intersection of the first connection line and the second connection line is located within the driving substrate.
  • the driving circuit includes: a semiconductor layer located in the substrate; a first conductive layer located on the semiconductor layer; a second conductive layer, The first conductive layer is located on the side away from the substrate; the third conductive layer is located on the side of the second conductive layer away from the substrate; and the fourth conductive layer is located on the third conductive layer. the side away from the substrate.
  • the intersection of the first connection line and the second connection line is located between the upper surface of the third conductive layer away from the substrate and the anode. between layers.
  • the intersection of the first connection line and the second connection line and the protrusion structure of the pixel defining layer are away from the upper surface of the substrate.
  • the distance between the vertices is greater than the thickness of the first sub-inorganic encapsulation layer in the first direction.
  • the intersection of the first connection line and the second connection line and the protrusion structure of the pixel defining layer are away from the upper surface of the substrate.
  • the distance between the vertices is less than the sum of the thickness of the first sub-inorganic encapsulation layer in the first direction and the thickness of the second sub-inorganic encapsulation layer in the first direction.
  • the second arched area of the first sub-inorganic encapsulation layer is close to the edge of the double-arch spacer area, and the second sub-inorganic encapsulation layer
  • the second arched area is close to the edge of the double arch spacer area
  • the second arched area of the third sub-inorganic encapsulation layer is close to the edge of the double arch spacer area
  • the fourth sub-inorganic encapsulation layer An included angle between a third connection line of the second arched area of the packaging layer close to the edge of the double-arched spacer area and a surface of the driving substrate away from the anode layer is a third included angle
  • the third included angle is The three included angles are smaller than the second included angle.
  • the intersection point of the first connection line and the three connection lines is located between the upper surface of the second conductive layer away from the substrate and the third A conductive layer is located close to the lower surface of the substrate.
  • the intersection point of the second connection line and the third connection line is located between the lower surface of the first conductive layer and the substrate.
  • the bottom is away from the lower surface of the first conductive layer.
  • the third arched area of the first sub-inorganic encapsulation layer is far away from the edge of the double-arch spacer area, the second sub-inorganic encapsulation layer
  • the third arched area is far away from the edge of the double arch spacer area
  • the third arched area of the third sub-inorganic encapsulation layer is far away from the edge of the double arch spacer area and the edge of the fourth sub-inorganic encapsulation layer
  • the included angle between the fourth connection line of the third arched area of the packaging layer away from the edge of the double-arched spacer area and the surface of the driving substrate away from the anode layer is the fourth included angle.
  • the four included angles are smaller than the second included angle.
  • the intersection of the first connection line and the fourth connection line is located on a side of the substrate away from the first conductive layer.
  • the intersection of the third connection line and the fourth connection line is located on a side of the substrate away from the first conductive layer.
  • the first arched area of the first sub-inorganic encapsulation layer has a first radius of curvature away from the upper surface of the substrate
  • the second The first arched area of the sub-inorganic encapsulation layer has a second radius of curvature away from the upper surface of the substrate
  • the first arched area of the third sub-inorganic encapsulation layer is away from the upper surface of the substrate.
  • the first arched area of the fourth sub-inorganic encapsulation layer away from the upper surface of the substrate has a fourth radius of curvature, the first radius of curvature being smaller than the second radius of curvature, The second radius of curvature is smaller than the third radius of curvature, and the third radius of curvature is smaller than the fourth radius of curvature.
  • the virtual center of the first arched area of the fourth sub-inorganic encapsulation layer is located at the edge of the first sub-inorganic encapsulation layer away from the substrate. between the upper surface and the fourth sub-inorganic encapsulation layer close to the lower surface of the substrate.
  • the first sub-inorganic encapsulation layer has a first thickness in the first direction
  • the second sub-inorganic encapsulation layer has a first thickness in the first direction.
  • the third sub-inorganic encapsulation layer has a third thickness in the first direction
  • the fourth sub-inorganic encapsulation layer has a fourth thickness in the first direction
  • the first The thickness is greater than the second thickness
  • the second thickness is greater than the third thickness
  • the third thickness is greater than the fourth thickness.
  • the ratio range of the difference between the first thickness and the second thickness and the difference between the third thickness and the fourth thickness is 1.5 -2 times.
  • the ratio of the sum of the second thickness and the third thickness to the first thickness ranges from 0.8 to 1.2.
  • the first thickness ranges from 1000 to 1200 nanometers
  • the second thickness ranges from 500 to 660 nanometers
  • the third thickness ranges from 480 nanometers to 480 nanometers. -560 nanometers
  • the fourth thickness ranges from 180 to 260 nanometers.
  • the material of the first sub-inorganic encapsulation layer includes silicon oxide and silicon oxynitride
  • the material of the second sub-inorganic encapsulation layer includes silicon nitride
  • the material of the third sub-inorganic encapsulation layer includes silicon nitride
  • the material of the fourth sub-inorganic encapsulation layer includes silicon oxide.
  • the encapsulation layer further includes: an organic encapsulation layer located on a side of the inorganic encapsulation layer away from the driving substrate, and the organic encapsulation layer includes a first region, a second region and a third region, the average thickness of the first region is less than the average thickness of the second region, the average thickness of the second region is less than the average thickness of the third region.
  • a display substrate provided by an embodiment of the present disclosure further includes: a color filter layer located on a side of the encapsulation layer away from the driving substrate.
  • the color filter layer includes a first color filter, a second color filter, and a first color filter. filter and a third color filter.
  • the first color filter and the second color filter have a first overlapping area
  • the second color filter and the second color filter have a first overlapping area
  • the third color filter has a second overlapping area
  • the third color filter and the first color filter have a third overlapping area
  • the orthographic projection of the first overlapping area, the second overlapping area and the third overlapping area on the driving substrate is different from that of the first overlapping area, the second overlapping area and the third overlapping area.
  • Orthographic projections of the protrusions on the driving substrate overlap.
  • the orthographic projection of the first overlapping area, the second overlapping area and the third overlapping area on the driving substrate is the same as the phase projection.
  • the orthographic projections of the spacing area between adjacent two anodes on the driving substrate overlap.
  • the size of the first overlapping area in the second direction is larger than the size of the second overlapping area in the second direction
  • the size of the second overlapping area in the second direction is larger than the size of the third overlapping area in the second direction.
  • the size range of the first overlapping area in the second direction is 400-600 nanometers, and the second overlapping area is in the second direction.
  • the size range in the two directions is 250-350 nanometers, and the size range of the third overlapping region in the second direction is 100-200 nanometers.
  • the average size of the first color filter in the first direction is larger than the average size of the second color filter in the first direction.
  • the average size is smaller than the average size of the third color filter in the first direction.
  • the average size of the first color filter in the first direction ranges from 2.3 to 2.6 microns
  • the second color filter ranges from 1.7 to 1.95 microns
  • the average size of the third color filter in the first direction ranges from 2.3 to 2.7 microns.
  • the average size of the first color filter in the first direction is the same as the average size of the second color filter in the first direction.
  • the ratio of the difference in the average size of the first color filter in the first direction to the difference in the average size of the third color filter in the first direction The range is 2-3.
  • the first color filter includes a first edge portion, a second edge portion and a second edge portion located between the first edge portion and the second edge portion.
  • the average size of the middle portion in the first direction is smaller than the average size of the first edge portion in the first direction and the average size of the second edge portion in the first direction. average size.
  • the first color filter includes a first contact surface that is in contact with the second color filter
  • the second color filter includes a second contact surface in contact with the third color filter
  • the third color filter includes a third contact surface in contact with the first color filter.
  • the first contact surface is perpendicular to The size of the driving substrate in the first direction is equal to the size of the second contact surface in the first direction and smaller than the size of the third contact surface in the first direction.
  • the distance between the first color filter and the surface of the driving substrate away from the anode layer is greater than the distance between the third color filter and the surface of the driving substrate.
  • the distance of the driving substrate away from the surface of the anode layer is smaller than the distance between the second color filter and the surface of the driving substrate away from the anode layer.
  • the first color filter is a red filter
  • the second color filter is a green filter
  • the third color filter The light sheet is a blue filter.
  • the material of the color filter layer includes a desiccant.
  • the color filter layer includes aluminum elements.
  • a display substrate provided by an embodiment of the present disclosure further includes: a protective layer located on a side of the color filter layer away from the driving substrate.
  • the color filter layer further includes: a black matrix located in any of the first color filter, the second color filter, and the third color filter. between two adjacent ones.
  • a display substrate provided by an embodiment of the present disclosure further includes: a glass cover plate located on a side of the color filter layer away from the driving substrate.
  • At least one embodiment of the present disclosure also provides a display device, which includes the display substrate described in any one of the above.
  • At least one embodiment of the present disclosure also provides another display device, which includes the display substrate described in any one of the above.
  • a display device provided by an embodiment of the present disclosure further includes: a counter substrate, arranged opposite to the display substrate, the counter substrate including a glass cover plate and a color filter layer located on the glass cover plate,
  • the color filter layer includes a first color filter, a second color filter and a third color filter.
  • the first color filter and the second color filter have a first overlapping area
  • the second color filter and the second color filter have a first overlapping area
  • the third color filter has a second overlapping area
  • the third color filter and the first color filter have a third overlapping area
  • the orthographic projection of the first overlapping area, the second overlapping area and the third overlapping area on the driving substrate is different from that of the first overlapping area, the second overlapping area and the third overlapping area.
  • Orthographic projections of the protrusions on the driving substrate overlap.
  • the orthographic projection and phase projection of the first overlapping area, the second overlapping area and the third overlapping area on the driving substrate are The orthographic projections of the spacing area between adjacent two anodes on the driving substrate overlap.
  • the size of the first overlapping area in the second direction is larger than the size of the second overlapping area in the second direction
  • the The size of the second overlapping area in the second direction is larger than the size of the third overlapping area in the second direction.
  • the size range of the first overlapping area in the second direction is 400-600 nanometers, and the second overlapping area is in the second direction.
  • the size range in the two directions is 250-350 nanometers, and the size range of the third overlapping region in the second direction is 100-200 nanometers.
  • the average size of the first color filter in the first direction is larger than the average size of the second color filter in the first direction.
  • the average size is smaller than the average size of the third color filter in the first direction.
  • the average size of the first color filter in the first direction ranges from 2.3 to 2.6 microns
  • the second color filter ranges from 1.7 to 1.95 microns
  • the average size of the third color filter in the first direction ranges from 2.3 to 2.7 microns.
  • the average size of the first color filter in the first direction is the same as the average size of the second color filter in the first direction.
  • the ratio of the difference in the average size of the first color filter in the first direction to the difference in the average size of the third color filter in the first direction The range is 2-3.
  • the first color filter includes a first edge portion, a second edge portion, and a second edge portion located between the first edge portion and the second edge portion.
  • the average size of the middle portion in the first direction is smaller than the average size of the first edge portion in the first direction and the average size of the second edge portion in the first direction. average size.
  • the first color filter includes a first contact surface that is in contact with the second color filter
  • the second color filter includes and a second contact surface in contact with the third color filter
  • the third color filter includes a third contact surface in contact with the first color filter.
  • the first contact surface is in contact with the first color filter.
  • the size of the driving substrate in the vertical second direction is equal to the size of the second contact surface in the second direction and smaller than the size of the third contact surface in the second direction.
  • the distance between the first color filter and the surface of the driving substrate away from the anode layer is greater than the distance between the third color filter and the surface of the driving substrate.
  • the distance of the driving substrate away from the surface of the anode layer is smaller than the distance between the second color filter and the surface of the driving substrate away from the anode layer.
  • the first color filter is a red filter
  • the second color filter is a green filter
  • the third color filter The light sheet is a blue filter.
  • the material of the color filter layer includes a desiccant.
  • the color filter layer includes aluminum elements.
  • the color filter layer further includes: a black matrix located in any of the first color filter, the second color filter, and the third color filter. between two adjacent ones.
  • FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a partial structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a partial structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 4A is a partial structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 4B is a partial structural schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a partial structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a partial structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a partial structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a first color filter in a display substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a partial structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a driving substrate provided by an embodiment of the present disclosure.
  • FIG. 12 is a partial structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 14 is a plan view of a display device according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of another display device provided by an embodiment of the present disclosure.
  • FIG. 16 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 17 is a partial cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 18 is an equivalent schematic diagram of a driving circuit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic plan view of a driving circuit in a display substrate according to an embodiment of the present disclosure.
  • FIGS. 20A-20E respectively show plan views of the layout of each layer of the display substrate shown in FIG. 19 .
  • FIG. 21 is a schematic diagram of an area of a display substrate for arranging storage capacitors according to an embodiment of the present disclosure.
  • FIG. 22 is a layout diagram of a storage capacitor in a display substrate according to an embodiment of the present disclosure.
  • Figures 23A-23D are plan views of the layer layout in Figure 22.
  • Figure 23E is a schematic cross-sectional view of a storage capacitor in a display substrate according to an embodiment of the present disclosure.
  • FIG. 24A is a block diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 24B is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 24C shows a schematic diagram of the latch-up effect formed by the pixel circuit.
  • FIG. 25A is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 25B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 24A.
  • FIG. 25C shows a signal timing diagram of the pixel circuit shown in FIG. 25B.
  • FIG. 26A is a schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • Figure 26B is a cross-sectional view along section line I-I' of Figure 26A.
  • FIG. 27A is a schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 27B is a schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • Figures 28A-28E illustrate the formation process of the substrate structure shown in Figure 27A.
  • 29A-29C are schematic diagrams of a forming process of a display substrate according to an embodiment of the present disclosure.
  • FIG. 30A is a schematic diagram of a second conductive layer in a display substrate according to an embodiment of the present disclosure.
  • FIG. 30B is a schematic diagram of a first conductive layer and a second conductive layer in a display substrate according to an embodiment of the present disclosure.
  • FIG. 31A is a schematic diagram of a third conductive layer in a display substrate according to an embodiment of the present disclosure.
  • FIG. 31B is a schematic diagram of a second conductive layer and a third conductive layer in a display substrate according to an embodiment of the present disclosure.
  • Typical large-size organic light-emitting diode (OLED) display devices reduce leakage and crosstalk by isolating the anode.
  • OLED organic light-emitting diode
  • Micro-OLED micro-organic light-emitting diode
  • leakage and crosstalk can also be reduced using the same method, due to the lower thickness of the pixel defining layer in micro-organic light-emitting diode display devices and the relatively high pixel density, Large, the same method cannot completely isolate the light-emitting layer, so that leakage and crosstalk still exist.
  • the display substrate includes a driving substrate, an anode layer, a pixel defining layer, a light-emitting functional layer, a cathode layer and a packaging layer;
  • the driving substrate includes a substrate and a driving circuit;
  • the anode layer is located on the driving substrate;
  • the pixel defining layer is located on the anode layer away from the driving substrate One side;
  • the light-emitting functional layer is located on the side of the anode layer away from the driving substrate;
  • the cathode layer is located on the side of the light-emitting functional layer away from the driving substrate;
  • the packaging layer is located on the side of the cathode layer away from the driving substrate;
  • the driving circuit includes at least one transistor, and the transistor includes a semiconductor layer, the semiconductor layer is at least partially located inside the substrate;
  • the anode layer includes a plurality of anodes,
  • the display substrate includes a plurality of pixel openings, and is located on a side of the plurality
  • Each anode includes a main body part and a protruding part, the protruding part is connected to the main body part, and the size of the protruding part in the first direction perpendicular to the driving substrate is larger than the size of the main body part in the first direction perpendicular to the driving substrate. . Therefore, the display substrate can provide a miniature display substrate, which can use a silicon-based circuit board as a driving substrate to drive the light-emitting functional layer for light-emitting display, and can also reduce and avoid crosstalk between adjacent sub-pixels.
  • FIG. 1 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a partial structural schematic view of another display substrate provided by an embodiment of the present disclosure.
  • the display substrate 500 includes a driving substrate 510, an anode layer 520, a pixel defining layer 530, a light emitting functional layer 540, a cathode layer 550 and an encapsulation layer 560;
  • the driving substrate 510 includes a substrate 512 and a driving circuit 514;
  • the anode layer 520 is located on the drive substrate 510;
  • the pixel definition layer 530 is located on the side of the anode layer 520 away from the drive substrate 510;
  • the light-emitting functional layer 540 is located on the side of the anode layer 520 away from the drive substrate 510;
  • the cathode layer 550 is located on the light-emitting functional layer 540 is away from the side of the driving substrate 510;
  • the encapsulation layer 560 is located on the side of the cathode layer 550 away from the driving substrate 510;
  • the driving circuit 514 includes at least one transistor T, the transistor T includes a semiconductor layer 102, and
  • the drive circuit can include transistors, storage capacitors, current control resistors, voltage dividing resistors and other structures; the specific circuit structure of the drive circuit can be based on actual needs. Settings are made, and the embodiments of the present disclosure do not limit this.
  • the driving substrate 510 can be a silicon-based circuit board. Since the semiconductor manufacturing process used in the silicon-based circuit board is mature, has stable performance, and has smaller size and precision, it is advantageous for manufacturing micro display devices.
  • the embodiments of the present disclosure include but are not limited to this, and other types of driving substrates may also be used as the driving substrate.
  • the anode layer 520 includes a plurality of anodes 525
  • the display substrate 500 includes a plurality of pixel openings 535
  • the plurality of pixel openings 535 are located in the film layer where the pixel defining layer 530 is located, and are Surrounded by the pixel defining layer 530
  • the plurality of pixel openings 535 are located on the side of the plurality of anodes 525 away from the driving substrate 510, and the plurality of pixel openings 535 are configured to at least overlap with the plurality of anodes 525
  • the light-emitting functional layer 540 includes a plurality of light-emitting
  • the plurality of light-emitting portions 545 are at least partially located within the plurality of pixel openings 535 and are disposed in contact with the exposed portions of the plurality of anodes 525 .
  • the driving substrate can be manufactured using a semiconductor manufacturing process, so that the pixel driving circuit for driving each pixel to emit light and display can be integrated into the driving substrate. Therefore, the display substrate can provide a miniature display substrate and has the advantages of high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption.
  • multiple anodes 525 are arranged in one-to-one correspondence with multiple pixel openings 535
  • multiple pixel openings 535 are arranged in one-to-one correspondence with multiple light-emitting portions 545 .
  • the above-mentioned "one-to-one corresponding arrangement" means that one pixel opening is provided on one anode, one light-emitting part is provided in one pixel opening, and the orthographic projection of the anode on the driving substrate and the corresponding pixel opening on the driving substrate are The orthographic projection of the pixel opening on the driving substrate at least partially overlaps with the orthographic projection of the light-emitting part on the driving substrate.
  • embodiments of the present disclosure include but are not limited to this.
  • the display substrate 100 further includes: a first flat layer 591 , a second flat layer 592 and a reflective electrode layer 593 ; the first flat layer 591 is located between the driving circuit 514 and the anode layer 520 ; The reflective electrode layer 593 is located on the side of the first flat layer 591 close to the anode layer 520 ; the second flat layer 592 is located on the side of the reflective electrode layer 593 close to the anode layer 520 .
  • reflective electrode layer 593 is continuously disposed in pixel opening 535 .
  • the display substrate further includes a color filter layer 570 located on a side of the encapsulation layer 560 away from the driving substrate 510 .
  • the color filter layer may include a plurality of color filters to achieve color display.
  • embodiments of the present disclosure include but are not limited to this, and the light-emitting functional layer can also be configured to directly emit light of different colors.
  • the display substrate 500 further includes a protective layer 580 located on a side of the color filter layer 570 away from the driving substrate 510 .
  • the protective layer 580 can protect the color filter layer 570 so that the filtering performance of the color filter layer 570 remains stable during long-term use, thereby improving the display quality of the display substrate.
  • the display substrate 500 further includes a glass cover 590 located on a side of the color filter layer 570 away from the driving substrate 510 .
  • FIG. 3 is a partial structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 4A is a partial structural diagram of another display substrate provided by an embodiment of the present disclosure. As shown in FIGS. 3 and 4A , the display substrate shown in FIG. 3 does not show a light-emitting functional layer, and the display substrate shown in FIG. 4A shows a light-emitting functional layer.
  • each anode 525 includes a main body portion 525A and a protruding portion 525B.
  • the protruding portion 525B is connected to the main body portion 525A.
  • the size of the protruding portion 525B in the first direction is larger than that of the main body portion 525A in the first direction.
  • directional size that is, the thickness of the protruding portion 525B is greater than the thickness of the main body portion 525A.
  • the distance between the surface of the first flat layer 591 at the position of the main body part 525A away from the substrate 512 and the substrate 512 is the same as the distance between the surface of the first flat layer 591 at the position of the protruding part 525B away from the substrate 512 and the substrate 512 Equally, the distance between the surface of the main body part 525A away from the substrate 512 and the surface of the first flat layer 591 away from the substrate 512 is smaller than the distance between the surface of the protruding part 525B away from the substrate 512 and the surface of the first flat layer 591 away from the substrate 512 .
  • the first direction may be a direction perpendicular to the driving substrate.
  • the size of the protruding portion 525B in the direction perpendicular to the driving substrate 510 is larger than the size of the main body portion 525A in the direction perpendicular to the driving substrate 510, it is located between the two anodes 525, And the pixel defining layer 530 overlapping the edge portion of the anode 525 may form a protrusion structure 532 corresponding to the protrusion 525 .
  • the light-emitting functional layer 540 when forming the light-emitting functional layer 540, at least part of the sub-functional layers (such as the charge generation layer) in the light-emitting functional layer 540 can be better disconnected at the position where the protruding structure 532 is located, that is, two adjacent anodes 525 correspond to At least some of the sub-functional layers in the light-emitting part 545 are not connected, thereby effectively avoiding leakage and crosstalk between adjacent sub-pixels.
  • the height of the protruding structure 532 of the pixel defining layer 530 is also higher at this time, so that it can better play the role of pixel defining and optically reduce and avoid crosstalk between adjacent sub-pixels.
  • each anode 525 includes a main body part 525A and a protruding part 525B.
  • the protruding part 525B is disposed around the main body part 525A, so that the light-emitting functional layer 540 can be better At least part of the functional layer is disconnected at the edge of the main body portion 525A.
  • the orthographic projection of pixel definition layer 530 on drive substrate 510 overlaps the orthographic projection of protrusion 525B on drive substrate 510 . Therefore, the pixel defining layer 530 can form a protruding structure 532 corresponding to the protruding portion 525 and located on a side of the protruding portion 525 away from the driving substrate 510 .
  • the pixel defining layer 530 includes a pixel defining portion 530A, which includes a pixel defining flat portion 534 and two protruding structures 532 on both sides of the pixel defining flat portion 534;
  • the defining flat portion 534 is located between two adjacent anodes 525.
  • the two protruding structures 532 are respectively located on the side of the two protruding portions 525B of the two adjacent anodes 525 away from the driving substrate 510.
  • the pixel defining flat portion 534 connects the two protruding portions 525B of the two adjacent anodes 525.
  • the protruding structures 532 are connected.
  • the pixel defining portion 530A includes both a portion located between two adjacent anodes 525 and a portion overlapping the two anodes 525; since the two adjacent anodes 525 are relatively flat, the edge portion of the anode 525
  • the above-mentioned protruding portion 525B is provided, so the portion located between two adjacent anodes 525 is formed as the above-mentioned pixel defining flat portion 534, and the portion overlapping the two anodes 525 is formed as the above-mentioned protruding structure 532.
  • the display substrate when the light-emitting functional layer 540 is formed, due to the existence of the pixel defining portion 530A, at least some of the sub-functional layers (such as the charge generation layer) in the light-emitting functional layer 540 can be better positioned in the protruding structure 532 The position is disconnected, that is, at least part of the sub-functional layers in the light-emitting portion 545 corresponding to two adjacent anodes 525 are not connected, thereby effectively avoiding leakage and crosstalk between adjacent sub-pixels.
  • the height of the protruding structure 532 at this time is also higher, so that it can better play the role of pixel definition and optically reduce and avoid crosstalk between adjacent sub-pixels.
  • the pixel defining portion 530A is symmetrically disposed about the center of the spacing area 522 between two adjacent anodes 525 . It should be noted that due to the existence of process errors, there may be differences between the two parts of the actual pixel defining part on both sides of the center of the spacer region. Therefore, the above-mentioned pixel defining part has a difference in the spacer region between two adjacent anodes.
  • the case where the center is arranged symmetrically includes the case where the coincidence rate of the two parts of the pixel defining part on both sides of the center of the separation area reaches 80%.
  • each protruding structure 532 includes a first side wall 532A and a second side wall 532B; the first side wall 532A is located at the center of the protruding structure 532 near the main body portion 525A of the anode 525
  • the second side wall 532B is connected to the first side wall 532A and is located on the side of the first side wall 532A away from the driving substrate 510 . That is to say, the second side wall 532B is farther away from the driving substrate than the first side wall 532A.
  • the above-mentioned slope angle may be the slope angle of the line connecting the two end points of the first side wall or the second side wall. .
  • the first side wall has a larger slope angle and is therefore steeper, Therefore, at least part of the sub-functional layers (eg, charge generation layer) in the light-emitting functional layer can be better disconnected at the position where the first side wall is located.
  • the sub-functional layers eg, charge generation layer
  • the display substrate provided in this example can further reduce crosstalk between adjacent sub-pixels.
  • a first pore 5471 exists between the light-emitting functional layer 540 and the main body portion 525A, and at least one second pore 5472 exists between the light-emitting functional layer 540 and the pixel defining layer 530.
  • the first pore 5471 The space occupied is larger than the space occupied by the second pore 5472.
  • the first pore 5471 and the second pore 5472 form a weak conductive region for the common layer to transfer carriers laterally, which is beneficial to reducing the lateral crosstalk of light.
  • embodiments of the present disclosure include but are not limited to this, and the light-emitting functional layer and the pixel defining layer may not form the above-mentioned second pores.
  • FIG. 4B is a partial structural schematic diagram of another display substrate provided by an embodiment of the present disclosure. As shown in FIG. 4B , the light-emitting functional layer 540 and the pixel defining layer 530 are closely adhered to each other.
  • the protruding structure 532 further includes a third side wall 532C located on a side of the protruding structure 532 away from the main body 525A.
  • the slope angle of the third side wall 532C is greater than that of the second side 532B.
  • the slope angle of the wall is smaller than the slope angle of the first side wall 532A. Therefore, the slope angle of the third side wall is relatively gentle, which can reduce or even avoid the subsequent formation of pores in the light-emitting functional layer formed on the third side wall, thus avoiding the formation of channels for water and oxygen intrusion.
  • the slope angle of the third side wall is relatively gentle, it is also convenient for the pixel defining part to form a complete integrated structure and avoid peeling off on the third side wall.
  • each protruding structure 532 further includes a third side wall 532C located on a side of the protruding structure 532 away from the main body portion 525A.
  • the slope angle of the first side wall 532A is ⁇
  • the slope angle of the second side wall 532B is ⁇
  • the slope angle of the third side wall 532C is ⁇
  • the slope angle ⁇ of the third side wall 532C is relatively gentle relative to the slope angle ⁇ of the first side wall 532A, thereby reducing or even avoiding the subsequent formation of a light-emitting functional layer on the third side wall 532C. pores are formed in the material to prevent the formation of channels for water and oxygen intrusion.
  • the slope angle ⁇ of the third side wall 532C is relatively gentle, it is also convenient for the pixel defining portion to form a complete integrated structure and avoid the peeling phenomenon on the third side wall.
  • the slope angle ⁇ of the third side wall 532C is greater than the slope angle ⁇ of the second side wall 532B, the protruding structure can be prevented from occupying a larger area and affecting the opening ratio.
  • the difference between the slope angle of the first side wall 532A and the slope angle of the second side wall 532B is equal to i times the slope angle of the third side wall, and the value of i The range is 0.8-1.2. Therefore, the protrusion structure can better achieve the above-mentioned effects of preventing crosstalk between adjacent sub-pixels, avoiding the formation of water and oxygen intrusion, and preventing the pixel defining portion from falling off.
  • the slope angle ⁇ of the first side wall, the slope angle ⁇ of the second side wall, and the slope angle ⁇ of the third side wall satisfy the following formula:
  • the value range of i is 0.8-1.2.
  • the protrusion structure can be relatively small.
  • the above-mentioned effects of preventing crosstalk between adjacent sub-pixels, avoiding water and oxygen intrusion, and preventing the pixel definition portion from falling off can be well achieved.
  • the difference between the slope angle of the first side wall 532A and the slope angle of the second side wall 532B is equal to the slope angle of the second side wall 532B and the slope angle of the third side wall 532C. j times the difference in slope angle, the value range of j is 1.5-3. Therefore, the protrusion structure can better achieve the above-mentioned effects of preventing crosstalk between adjacent sub-pixels, avoiding the formation of water and oxygen intrusion, and preventing the pixel defining portion from falling off.
  • the slope angle ⁇ of the first side wall, the slope angle ⁇ of the second side wall, and the slope angle ⁇ of the third side wall satisfy the following formula:
  • the value range of j is 1.5-3.
  • the protrusion structure can be relatively small.
  • the above-mentioned effects of preventing crosstalk between adjacent sub-pixels, avoiding water and oxygen intrusion, and preventing the pixel definition portion from falling off can be well achieved.
  • the protrusion structure can better achieve the above-mentioned effects of preventing crosstalk between adjacent sub-pixels, avoiding the formation of water and oxygen intrusion, and preventing the pixel defining portion from falling off.
  • the slope angle ⁇ of the first side wall, the slope angle ⁇ of the second side wall, and the slope angle ⁇ of the third side wall satisfy the following formula:
  • the value range of k is 2-3.
  • the protrusion structure can be relatively small.
  • the above-mentioned effects of preventing crosstalk between adjacent sub-pixels, avoiding water and oxygen intrusion, and preventing the pixel definition portion from falling off can be well achieved.
  • the slope angle of the first side wall 532A may range from 75 to 89 degrees; the slope angle of the second side wall 532B may range from 15 to 45 degrees. degree; the slope angle of the third side wall 532C may range from 45 to 60 degrees.
  • the slope angle of the first side wall 532A may range from 75 to 89 degrees; the slope angle of the second side wall 532B may range from 25 to 35 degrees. degree; the slope angle of the third side wall 532C may range from 45 to 55 degrees.
  • the size of the orthographic projection of the second side wall 532B on the driving substrate 510 in the second direction is larger than the size of the orthographic projection of the first side wall 532A on the driving substrate 510 in the second direction. Dimensions in two directions. Therefore, the protrusion structure can better disconnect the charge generation layer in the light-emitting functional layer at the position where the first side wall is located.
  • the size of the orthographic projection of the third side wall 532C on the driving substrate 510 in the second direction is greater than the size of the orthographic projection of the second side wall 532B on the driving substrate 510 in the second direction.
  • Dimensions in two directions. Therefore, the protruding structure can reduce or even avoid the subsequent formation of pores in the light-emitting functional layer formed on the third sidewall 532C, thereby avoiding the formation of channels for water and oxygen intrusion.
  • the slope angle ⁇ of the third side wall 532C is relatively gentle, it is also convenient for the pixel defining portion to form a complete integrated structure and avoid the peeling phenomenon on the third side wall.
  • the first side wall 532A has a size H1 in the first direction
  • the second side wall 532B has a size H2 in the first direction
  • the third side wall 532C has a size H1 in the first direction.
  • the size in the first direction is H3, and H1, H2 and H3 satisfy the following formula:
  • the protrusion structure can better disconnect the charge generation layer in the light-emitting functional layer at the location of the first side wall; at the same time, the protrusion structure can reduce or even avoid the subsequent formation of the light-emitting function on the third side wall.
  • the formation of pores in the layer prevents the formation of channels for water and oxygen intrusion.
  • the raised portion 525B of each anode 525 further includes a fourth side wall 525D located on a side of the raised portion 525B close to the center of the main body portion 525A.
  • the fourth side wall 525D The slope angle of is greater than the slope angle of the second side wall 532B and smaller than the slope angle of the first side wall 532A.
  • the raised portion 525B of the anode 525 includes a fourth side wall 525D located on one side of the raised portion 525B near the center of the main body portion 525A.
  • the slope angle of the fourth side wall is is ⁇ , and satisfies the following formula:
  • the raised portion 525B of each anode 525 includes: a first sub-anode layer 5251 , a second sub-anode layer 5252 , and a third sub-anode layer 5253 ; the first sub-anode layer 5251 is located on the side of the driving circuit 514 away from the substrate 512; the second sub-anode layer 5252 is located on the side of the first sub-anode layer 5251 away from the driving substrate 510; the third sub-anode layer 5253 is located on the second sub-anode layer 5252 away from the driving substrate 510 side.
  • the size of the first sub-anode layer 5251 in the second direction is greater than the size of the third sub-anode layer 5253 in the second direction, and the third sub-anode layer 5253 is in the second direction.
  • the size in the two directions is larger than the size of the second sub-anode layer 5252 in the second direction. Therefore, since the size of the third sub-anode layer in the second direction is larger than the size of the second sub-anode layer in the second direction, the edge of the third sub-anode layer lacks support, so the third sub-anode layer 5253 can be formed.
  • the curved structure 5253S bent toward the driving substrate 510 can effectively prevent the pixel defining portion from peeling off when the pixel defining portion is subsequently formed. It should be noted that since the pixel defining portion is usually made of inorganic materials, if the edge of the protruding portion is too steep, it may easily fall off.
  • the third sub-anode layer can be made of a material with poor electrical conductivity, such as indium tin oxide; at this time, since the size of the third sub-anode layer in the second direction is larger than that of the second sub-anode layer in the second direction, With the size above, the edge of the third sub-anode layer lacks support, so the third sub-anode layer can form a curved structure that bends toward the driving substrate, which can wrap the edge of the protrusion to a certain extent, and then When a defect occurs in the pixel defining portion, it can prevent the edge of the protruding portion from contacting the light-emitting functional layer, and can also avoid the occurrence of tip discharge and other phenomena.
  • a material with poor electrical conductivity such as indium tin oxide
  • the above-mentioned second direction is the direction from the protruding portion 525B to the main body portion 525A or the direction from the main body portion 525A to the protruding portion 525B, and the second direction is parallel to the direction of the surface of the driving substrate 510 away from the anode layer 520 .
  • the conductivity of the third sub-anode layer is smaller than the conductivity of the first sub-anode layer and the conductivity of the second sub-anode layer, so that it can better match the work function of the light-emitting functional layer.
  • the size of the third sub-anode layer 5253 beyond the second sub-anode layer 5252 in the second direction is smaller than the orthographic projection and protrusion of the pixel defining layer 530 on the driving substrate 510 The size of the overlapping area of the orthographic projection of the portion 525B on the drive substrate 510 in the second direction.
  • the size of the third sub-anode layer 5253 beyond the second sub-anode layer 5252 in the second direction is smaller than the orthographic projection and protrusion of the pixel defining layer 530 on the driving substrate 510
  • the size of the overlapping area of the orthographic projection of the portion 525B on the drive substrate 510 is 1/4 of the size in the second direction.
  • an end of the third sub-anode layer 5253 away from the main body portion 525A is bent in a direction closer to the first sub-anode layer 5251 , so that the third sub-anode layer can function to a certain extent. It has a wrapping effect on the edge of the protruding portion, thereby preventing the edge of the protruding portion from contacting the light-emitting functional layer when a defect occurs in the pixel defining portion, and can also avoid the occurrence of tip discharge and other phenomena.
  • the raised portion 525B of each anode 525 further includes a fourth sub-anode layer 5254 located between the second sub-anode layer 5252 and the third sub-anode layer 5253 . Therefore, the fourth sub-anode layer located at the raised portion of the anode can be retained and the fourth sub-anode layer located at the main body portion of the anode can be etched away, thereby forming the above-mentioned main body portion and raised portions with different heights.
  • the size of the fourth sub-anode layer 5254 in the second direction is smaller than the size of the second sub-anode layer 5252 in the second direction.
  • the third sub-anode layer 5253 formed on the fourth sub-anode layer 5254 can better form the curved structure 5253S, thereby effectively avoiding the peeling phenomenon of the pixel defining portion when the pixel defining portion is subsequently formed. .
  • the size of the third sub-anode layer 5253 beyond the fourth sub-anode layer 5254 in the second direction is smaller than the orthographic projection and protrusion of the pixel defining layer 530 on the driving substrate 510 The size of the overlapping area of the orthographic projection of the portion 525B on the driving substrate 510 in the second direction.
  • the second sub-anode layer 5252 includes a fifth sidewall 525E located on a side of the second sub-anode layer 525E away from the main body portion 525A
  • the fourth sub-anode layer 5254 includes a fifth sidewall 525E.
  • the six side walls 525F are located on the side of the fourth sub-anode layer 5254 away from the main body 525A; the slope angle of the fifth side wall 525E is greater than the slope angle of the fourth side wall 525D, and the slope angle of the sixth side wall 525F is greater than that of the fourth side wall.
  • the slope angle of the wall 525D and the fifth side wall 525E are greater than the slope angle of the sixth side wall 525F, thereby preventing the second sub-anode layer and the third sub-anode layer from forming a tip structure.
  • the tip discharge phenomenon can be suppressed to a certain extent, thereby improving the yield and service life of the product.
  • one end of the first sub-anode layer 5251 away from the main body portion 525A includes a raised portion 5251A, and the raised portion 5251A has a thickness greater than that of the first sub-anode in a direction perpendicular to the driving substrate 510 The average thickness of layer 5251 in the direction perpendicular to the driving substrate 510. Therefore, the protruding portion 5251A can also play a role in wrapping the edge of the protruding portion to a certain extent, thereby preventing the edge of the protruding portion from contacting the light-emitting functional layer when a defect occurs in the pixel defining portion, and also avoiding the occurrence of sharp edges. Discharge and other phenomena.
  • the raised portion 5251A of the first sub-anode layer 5251 and the curved structure 5253S of the third sub-anode layer 5253 exist at the same time, the raised portion 5251A and the bent structure 5253S can be viewed from top to bottom.
  • the two directions play a role in wrapping the edges of the protruding portion, thereby better preventing the edges of the protruding portion from contacting the light-emitting functional layer when defects occur in the pixel defining portion, and also avoiding the occurrence of tip discharge and other phenomena.
  • the embodiments of the present disclosure include but are not limited to this.
  • the raised portion 5251A of the first sub-anode layer 5251 or the curved structure 5253S of the third sub-anode layer 5253 exists alone, it can also function to a certain extent. The edge wrapping effect of the raised part.
  • the ratio of the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 to the thickness of the second sub-anode layer 5252 in the direction perpendicular to the driving substrate 510 ranges from 1/15 to 1 /5.
  • the ratio of the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 to the thickness of the third sub-anode layer 5253 in the direction perpendicular to the driving substrate 510 ranges from 1/3-4 /5.
  • the ratio of the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 to the thickness of the fourth sub-anode layer 5254 in the direction perpendicular to the driving substrate 510 ranges from 1/24 to 1 /8.
  • the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 ranges from 1 to 4 nanometers; the thickness of the second sub-anode layer 5252 in the direction perpendicular to the driving substrate 510 ranges from 15 to 15 nanometers. 22 nanometers; the thickness range of the fourth sub-anode layer 5254 in the direction perpendicular to the driving substrate 510 is 24-32 nanometers; the thickness range of the third sub-anode layer 5253 in the direction perpendicular to the driving substrate 510 is 3-5 nanometers .
  • the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 ranges from 2 to 3 nanometers; the thickness of the second sub-anode layer 5252 in the direction perpendicular to the driving substrate 510 ranges from 17 to 17 nanometers. 20 nanometers; the thickness range of the fourth sub-anode layer 5254 in the direction perpendicular to the driving substrate 510 is 26-30 nanometers; the thickness range of the third sub-anode layer 5253 in the direction perpendicular to the driving substrate 510 is 4 nanometers.
  • the ratio of the distance between two adjacent anodes 525 to the length of the orthographic projection of the protruding portion 525B of the anode 525 on the driving substrate 510 ranges from 2 to 4. That is to say, the ratio of the distance between two adjacent anodes 525 to the length of the anode 525 in the second direction ranges from 2 to 4. Therefore, the display substrate can better avoid crosstalk between adjacent sub-pixels.
  • the ratio of the distance between two adjacent anodes 525 to the length of the orthographic projection of the protruding portion 525B of the anode 525 on the driving substrate 510 ranges from 2.5 to 3.5. That is to say, the ratio of the distance between two adjacent anodes 525 to the length of the anode 525 in the second direction ranges from 2.5 to 3.5. Therefore, the display substrate can better avoid crosstalk between adjacent sub-pixels.
  • the distance between two adjacent anodes 525 ranges from 0.6 to 1 micron. That is to say, the width of the spacer area 522 may range from 0.6 to 1 micron.
  • the embodiments of the present disclosure include but are not limited to this, and the width range of the separation area can be set according to the actual situation.
  • the distance between two adjacent anodes 525 ranges from 0.7 to 0.9 microns.
  • the embodiments of the present disclosure include but are not limited to this, and the width range of the separation area can be set according to the actual situation.
  • FIG. 5 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. As shown in Figure 5, the raised portion 525B is provided around the main body portion 525A. Therefore, the display substrate can effectively avoid crosstalk between adjacent sub-pixels in any direction, so that the display substrate can be adapted to different pixel arrangement structures.
  • the shape of the orthographic projection of anode 525 on drive substrate 510 includes a hexagon.
  • embodiments of the present disclosure include but are not limited to this, and the shape of the orthographic projection of the anode 525 on the driving substrate 510 can also be other suitable shapes.
  • the pixel opening is arranged corresponding to the anode, so the shape of the orthographic projection of the pixel opening on the driving substrate is similar to the shape of the orthographic projection of the anode on the driving substrate.
  • a plurality of anodes 525 are arranged in an array on the driving substrate 510 to form anode rows 610 ; in each anode row 610 , the plurality of anodes 525 are arranged sequentially along the direction.
  • the above-mentioned second direction may be a row direction.
  • the ratio of the size of the orthographic projection of each anode 525 on the driving substrate 510 in the second direction to the distance between two adjacent anodes 525 ranges from 4 to 6.
  • the display substrate can achieve a larger aperture ratio and effectively avoid crosstalk between adjacent sub-pixels.
  • the size of the orthogonal projection of each anode 525 on the driving substrate 510 in the second direction may be 4-5 microns.
  • FIG. 6 is a partial structural diagram of another display substrate according to an embodiment of the present disclosure.
  • the protruding portion 525B of each anode 525 includes a first sub-anode layer 5251, a second sub-anode layer 5252 and a third sub-anode layer 5253; the first sub-anode layer 5251 is located on the driving The circuit 514 is located on a side away from the substrate 512; the second sub-anode layer 5252 is located on a side of the first sub-anode layer 5251 away from the driving substrate 510; and the third sub-anode layer 5253 is located on a side of the second sub-anode layer 5252 away from the driving substrate 510. side.
  • the display substrate shown in FIG. 6 does not include the fourth sub-anode layer.
  • the main body portion 525A and the protruding portion 525B of the anode 525 may have the same layer structure, that is, include the same number of film layers and the same stacking relationship, but each film layer is not limited. The thickness is the same.
  • the second sub-anode layer located on the main body portion of the anode can be partially etched, while the second sub-anode layer on the protruding portion of the anode is retained, thereby forming the main body portion and the protruding portions with height differences.
  • the size of the first sub-anode layer 5251 in the second direction is greater than the size of the third sub-anode layer 5253 in the second direction.
  • the size is larger than the size of the second sub-anode layer 5252 in the second direction; the above-mentioned second direction is the direction from the protruding portion 525B to the main body portion 525A or the direction from the main body portion 525A to the protruding portion 525B.
  • the edge of the third sub-anode layer lacks support, so the third sub-anode layer 5253 can be formed
  • the curved structure 5253S bent toward the driving substrate 510 can effectively prevent the pixel defining portion from peeling off when the pixel defining portion is subsequently formed. It should be noted that since the pixel defining portion is usually made of inorganic materials, if the edge of the protruding portion is too steep, it may easily fall off.
  • the third sub-anode layer can be made of a material with poor electrical conductivity, such as indium tin oxide; at this time, since the size of the third sub-anode layer in the second direction is larger than that of the second sub-anode layer in the second direction, With the size above, the edge of the third sub-anode layer lacks support, so the third sub-anode layer can form a curved structure that bends toward the driving substrate, which can wrap the edge of the protrusion to a certain extent, and then When a defect occurs in the pixel defining portion, it can prevent the edge of the protruding portion from contacting the light-emitting functional layer, and can also avoid the occurrence of tip discharge and other phenomena.
  • a material with poor electrical conductivity such as indium tin oxide
  • the conductivity of the third sub-anode layer is smaller than the conductivity of the first sub-anode layer and the conductivity of the second sub-anode layer.
  • the end of the third sub-anode layer 5253 away from the main body portion 525A is bent in a direction closer to the first sub-anode layer 5251 , so that the third sub-anode layer can play a role in convexing to a certain extent.
  • the wrapping effect of the edge of the raised portion can further prevent the edge of the raised portion from contacting the light-emitting functional layer when a defect occurs in the pixel defining portion, and can also avoid the occurrence of tip discharge and other phenomena.
  • the second sub-anode layer 5252 includes a fifth sidewall 525E and a sixth sidewall 525F.
  • the sixth sidewall 525F is located on a side of the fifth sidewall 525E away from the driving substrate 510 , that is, The sixth side wall 525F is further away from the driving substrate 510 than the fifth side wall 525E.
  • the slope angle of the fifth side wall 525E is greater than the slope angle of the fourth side wall 525D
  • the slope angle of the sixth side wall 525F is greater than the slope angle of the fourth side wall 525D
  • the slope angle of the fifth side wall 525E is greater than the slope angle of the sixth side wall 525F.
  • the tip discharge phenomenon can be suppressed to a certain extent, thereby improving the yield and service life of the product.
  • the third sub-anode layer located on the second sub-anode layer can form a smoother curved structure, This can better prevent the pixel defining portion from falling off.
  • one end of the first sub-anode layer 5251 away from the main body portion 525A includes a raised portion 5251A.
  • the thickness of the raised portion 5251A in a direction perpendicular to the driving substrate 510 is greater than that of the first sub-anode layer 5251 .
  • the average thickness in the direction perpendicular to the driving substrate 510. Therefore, the protruding portion 5251A can also play a role in wrapping the edge of the protruding portion to a certain extent, thereby preventing the edge of the protruding portion from contacting the light-emitting functional layer when a defect occurs in the pixel defining portion, and also avoiding the occurrence of sharp edges. Discharge and other phenomena.
  • the bulge 5251A of the first sub-anode layer 5251 and the curved structure 5253S of the third sub-anode layer 5253 can be viewed from both upper and lower directions. It plays the role of wrapping the edge of the protruding part, thereby better preventing the edge of the protruding part from contacting the light-emitting functional layer when a defect occurs in the pixel defining part, and also avoiding the occurrence of tip discharge and other phenomena.
  • the embodiments of the present disclosure include but are not limited to this.
  • the raised portion 5251A of the first sub-anode layer 5251 or the curved structure 5253S of the third sub-anode layer 5253 exists alone, it can also function to a certain extent. The edge wrapping effect of the raised part.
  • FIG. 7 is a partial structural diagram of another display substrate according to an embodiment of the present disclosure.
  • the protruding portion 525B of each anode 525 includes a first sub-anode layer 5251, a second sub-anode layer 5252, a third sub-anode layer 5253 and a fourth sub-anode layer 5254;
  • One sub-anode layer 5251 is located on the side of the driving circuit 514 away from the substrate 512;
  • the second sub-anode layer 5252 is located on the side of the first sub-anode layer 5251 away from the driving substrate 510;
  • the third sub-anode layer 5253 is located on the second sub-anode layer 5252 is away from the side of the driving substrate 510;
  • the fourth sub-anode layer 5254 is located between the second sub-anode layer 5252 and the third sub-anode layer 5253.
  • the main body portion 525A and the protruding portion 525B of the anode 525 may have the same layer structure, that is, include the same number of film layers and the same stacking relationship, but each film layer is not limited. The thickness is the same.
  • the main body portion 525A of the anode 525 also includes a first sub-anode layer 5251, a second sub-anode layer 5252, a third sub-anode layer 5253 and a fourth sub-anode layer 5254;
  • the first sub-anode layer 5251 is located away from the driving circuit 514 One side of the substrate 512;
  • the second sub-anode layer 5252 is located on the side of the first sub-anode layer 5251 away from the driving substrate 510;
  • the third sub-anode layer 5253 is located on the side of the second sub-anode layer 5252 away from the driving substrate 510;
  • the fourth sub-anode layer 5254 is located between the second sub-anode layer 5252 and the third sub-anode layer 5253.
  • the second sub-anode layer located on the main body portion of the anode can be partially etched, while the second sub-anode layer on the protruding portion of the anode is retained, thereby forming the main body portion and the protruding portions with height differences.
  • the thickness of the first sub-anode layer 5251 located at the main body portion 525A of the anode 525 in the direction perpendicular to the driving substrate 510 is the same as that of the first sub-anode layer 5251 located at the protruding portion 525B of the anode 525 .
  • the thickness in the direction perpendicular to the driving substrate 510 is the same.
  • the thickness of the third sub-anode layer 5253 located at the main body portion 525A of the anode 525 in the direction perpendicular to the driving substrate 510 is the same as that of the third sub-anode layer 5253 located at the protruding portion 525B of the anode 525 .
  • the thickness in the direction perpendicular to the driving substrate 510 is the same.
  • the thickness of the fourth sub-anode layer 5254 located at the main body portion 525A of the anode 525 in the direction perpendicular to the driving substrate 510 is the same as that of the fourth sub-anode layer 5254 located at the protruding portion 525B of the anode 525 .
  • the thickness in the direction perpendicular to the driving substrate 510 is the same.
  • the size of the first sub-anode layer 5251 in the second direction is greater than the size of the third sub-anode layer 5253 in the second direction.
  • the size is larger than the size of the second sub-anode layer 5252 in the second direction; the size of the fourth sub-anode layer 5254 in the second direction is smaller than the size of the second sub-anode layer 5252 in the second direction.
  • the above-mentioned second direction is the direction from the protruding portion 525B to the main body portion 525A or the direction from the main body portion 525A to the protruding portion 525B.
  • the second direction is parallel to the direction of the surface of the driving substrate 510 away from the anode layer 520 .
  • the third sub-anode layer 5253 formed on the fourth sub-anode layer 5254 can better form the curved structure 5253S, thereby effectively avoiding the peeling phenomenon of the pixel defining portion when the pixel defining portion is subsequently formed. .
  • the third sub-anode layer can be made of a material with poor electrical conductivity, such as indium tin oxide; at this time, since the size of the third sub-anode layer in the second direction is larger than that of the second sub-anode layer in the second direction, With the size above, the edge of the third sub-anode layer lacks support, so the third sub-anode layer can form a curved structure that bends toward the driving substrate, which can wrap the edge of the protrusion to a certain extent, and then When a defect occurs in the pixel defining portion, it can prevent the edge of the protruding portion from contacting the light-emitting functional layer, and can also avoid the occurrence of tip discharge and other phenomena.
  • a material with poor electrical conductivity such as indium tin oxide
  • the conductivity of the third sub-anode layer is smaller than the conductivity of the first sub-anode layer and the conductivity of the second sub-anode layer.
  • the end of the third sub-anode layer 5253 away from the main body portion 525A is bent in a direction closer to the first sub-anode layer 5251 , so that the third sub-anode layer can play a role in protruding to a certain extent.
  • the wrapping effect of the edge of the raised portion can further prevent the edge of the raised portion from contacting the light-emitting functional layer when a defect occurs in the pixel defining portion, and can also avoid the occurrence of tip discharge and other phenomena.
  • the second sub-anode layer 5252 includes a fifth sidewall 525E located on a side of the second sub-anode layer 525E away from the main body portion 525A
  • the fourth sub-anode layer 5254 includes a sixth sidewall. 525F, located on the side of the fourth sub-anode layer 5254 away from the main body 525A; the slope angle of the fifth side wall 525E is greater than the slope angle of the fourth side wall 525D, and the slope angle of the sixth side wall 525F is greater than that of the fourth side wall 525D.
  • the slope angle, the slope angle of the fifth side wall 525E is greater than the slope angle of the sixth side wall 525F, thereby preventing the second sub-anode layer and the third sub-anode layer from forming a tip structure.
  • the tip discharge phenomenon can be suppressed to a certain extent, thereby improving the yield and service life of the product.
  • one end of the first sub-anode layer 5251 away from the main body portion 525A includes a bulge 5251A, and the thickness of the bulge 5251A in a direction perpendicular to the driving substrate 510 is greater than that of the first sub-anode layer 5251 .
  • the bulge 5251A of the first sub-anode layer 5251 and the curved structure 5253S of the third sub-anode layer 5253 can be viewed from both upper and lower directions. It plays the role of wrapping the edge of the protruding part, thereby better preventing the edge of the protruding part from contacting the light-emitting functional layer when a defect occurs in the pixel defining part, and also avoiding the occurrence of tip discharge and other phenomena.
  • the embodiments of the present disclosure include but are not limited to this.
  • the raised portion 5251A of the first sub-anode layer 5251 or the curved structure 5253S of the third sub-anode layer 5253 exists alone, it can also function to a certain extent. The edge wrapping effect of the raised part.
  • FIG. 8 is a partial structural diagram of another display substrate according to an embodiment of the present disclosure.
  • the encapsulation layer 560 includes an inorganic encapsulation layer 710 ; the inorganic encapsulation layer 710 is located on the side of the cathode layer 550 away from the driving substrate 510 .
  • the inorganic encapsulation layer 710 includes multiple sub-inorganic encapsulation layers 7100, and there are at least two adjacent sub-inorganic encapsulation layers 7100 made of different materials among the multiple sub-inorganic encapsulation layers 7100.
  • the plurality of sub-inorganic encapsulation layers 7100 there are at least two adjacent sub-inorganic encapsulation layers 7100 made of the same material.
  • the inorganic encapsulation The layer can form a denser film layer, which can better prevent water and oxygen intrusion, thereby improving the service life of the display device.
  • each sub-inorganic encapsulation layer 7100 may be selected from at least one of silicon nitride, silicon oxide, and silicon oxynitride.
  • the refraction of the plurality of sub-inorganic encapsulation layers 7100 first increases and then decreases.
  • the emitted light emitted by the light-emitting functional layer 540 enters the sub-inorganic encapsulation layer with a larger refractive index from the sub-inorganic encapsulation layer with a smaller refractive index, the emitted light will be refracted at the interface between them, thereby reducing the diffusion angle of the emitted light.
  • the emitted light enters the sub-inorganic encapsulation layer with a larger refractive index from the sub-inorganic encapsulation layer with a smaller refractive index, and passes between them.
  • the interface is refracted, and the diffusion angle of the emitted light increases at this time.
  • the emitted light since the emitted light is already close to the light emitting surface of the display substrate, it will not cause crosstalk to adjacent sub-pixels.
  • each sub-inorganic encapsulation layer 7100 includes alternately arranged flat areas PTQ and double arch spacers JGQ, and a first arched area located on a side of the flat area PTQ away from the double arch spacers JGQ.
  • GX1 the second arched region GX2 located between the flat region PTQ and the double arched spacer region JGQ
  • the third arched region GX3 located in the flat region PTQ away from the second arched region GX2, the first arched region GX1 and the second arched region GX3.
  • the two arched areas GX2 are arranged symmetrically about the center of the flat area PTQ.
  • the orthographic projection of the first arched area GX1 , the second arched area GX2 , or the third arched area GX3 on the driving substrate 510 is the same as that of the protruding portion 525B on the driving substrate 510 .
  • the orthographic projections overlap, and the orthographic projection of the flat area PTQ on the driving substrate 510 overlaps with the orthographic projection of the main body portion 525A on the driving substrate 510 .
  • the orthographic projection of the first arched area GX1, the second arched area GX2 or the third arched area GX3 of each sub-inorganic encapsulation layer 7100 on the driving substrate 510 is the same as the orthographic projection of the protruding portion 525B on the driving substrate 510.
  • the orthographic projections overlap, and the orthographic projections of the flat areas PTQ of each sub-inorganic encapsulation layer 7100 on the driving substrate 510 overlap with the orthographic projections of the main body portion 525A on the driving substrate 510; and, the first arch of each sub-inorganic encapsulating layer 7100 overlaps.
  • the shaped area GX1 , the second arcuate area GX2 and the third arcuate area GX3 overlap with the protrusions 525B of different anodes 525 . Therefore, the light at the edge of each sub-pixel can be condensed onto the black matrix through refraction of the first arched area, the second arched area, or the third arched area, thereby avoiding crosstalk between adjacent sub-pixels.
  • the above-mentioned black matrix may be a normal black matrix or a structure formed by overlapping at least two color filters with low light transmittance and functioning as a black matrix.
  • the size of the flat area PTQ in the second direction is L
  • the distance between the center of the second arched area GX2 and the center of the third arched area GX3 in the second direction is L
  • a distance D1 the distance in the second direction between the center of the first arched area GX1 and the center of the second arched area GX2 is the second distance D2
  • the curvature radius of the arched area GX3 is R
  • the first distance D1 satisfies the following formula:
  • the crosstalk between adjacent sub-pixels can be reduced while increasing the pixel density or aperture ratio, thereby obtaining a better display effect.
  • the above-mentioned radius of curvature is the average radius of curvature, that is, the reciprocal of the average curvature of the corresponding arc.
  • the above-mentioned second direction is the direction from the protruding portion to the main body portion or the direction from the main body portion to the protruding portion, and the second direction is parallel to the surface of the driving substrate away from the anode layer.
  • the size of the flat area PTQ in the second direction is L
  • the distance between the center of the second arched area GX2 and the center of the third arched area GX3 in the second direction is L
  • a distance D1 the distance in the second direction between the center of the first arched area GX1 and the center of the second arched area GX2 is the second distance D2
  • the curvature radius of the arched area GX3 is R
  • the first distance D1 satisfies the following formula:
  • the crosstalk between adjacent sub-pixels can be reduced while increasing the pixel density or aperture ratio, thereby obtaining a better display effect.
  • the above-mentioned second direction is the direction from the protruding portion to the main body portion or the direction from the main body portion to the protruding portion, and the second direction is parallel to the surface of the driving substrate away from the anode layer.
  • the first arched region GX1 , the second arched region GX2 or the third arched region GX3 is away from the surface of the driving substrate 510 and the driving substrate 510 The distance therebetween is greater than the distance between the surface of the flat area PTQ away from the driving substrate 510 and the driving substrate 510 . Therefore, the first arched area GX1, the second arched area GX2 or the third arched area GX3 have an upwardly arched structure.
  • the orthographic projection of the double arch spacer JGQ on the driving substrate 510 overlaps with the orthographic projection of the spacer 522 between two adjacent anodes 525 on the driving substrate 510 .
  • the plurality of sub-inorganic encapsulation layers 7100 include: a first sub-inorganic encapsulation layer 711 , a second sub-inorganic encapsulation layer 712 , a third sub-inorganic encapsulation layer 713 and a fourth sub-inorganic encapsulation layer 714 ;
  • the first sub-inorganic encapsulation layer 711 is located on the side of the cathode layer 550 away from the driving substrate 510;
  • the second sub-inorganic encapsulation layer 712 is located on the side of the first sub-inorganic encapsulation layer 711 away from the driving substrate 510;
  • the third sub-inorganic encapsulation layer 713 The second sub-inorganic encapsulation layer 711 is located on the side away from the driving substrate 510 ; and the fourth sub-inorganic encapsulation layer 714 is located on the side of the third sub-inorganic encapsulation layer 713 away from the
  • the refractive index of the first sub-inorganic encapsulation layer 711 is less than the refractive index of the second sub-inorganic encapsulation layer 712
  • the refractive index of the fourth sub-inorganic encapsulation layer 714 is less than the third sub-inorganic encapsulation layer.
  • the refractive index is 713.
  • the emitted light from the light-emitting functional layer 540 enters the second sub-inorganic encapsulation layer 712 with a larger refractive index from the first sub-inorganic encapsulation layer 711 with a smaller refractive index
  • the emitted light will pass through the first sub-inorganic encapsulation layer 711
  • the interface between the second sub-inorganic encapsulation layer 712 and the second sub-inorganic encapsulation layer 712 is refracted, thereby reducing the diffusion angle of the emitted light, thereby reducing or avoiding crosstalk between adjacent sub-pixels inside the display substrate; then, the emitted light is refracted from the refractive index.
  • the larger third sub-inorganic encapsulation layer 713 enters the fourth sub-inorganic encapsulation layer 714 with a smaller refractive index, and is refracted at the interface between them. At this time, the diffusion angle of the outgoing light increases, but because the outgoing light is already close to The light-emitting surface of the display substrate will not cause crosstalk to adjacent sub-pixels.
  • the refractive index of the second sub-inorganic encapsulation layer 712 is equal to the refractive index of the third sub-inorganic encapsulation layer 713 .
  • the second sub-inorganic encapsulation layer 712 and the third sub-inorganic encapsulation layer 713 can be made of the same material.
  • embodiments of the present disclosure include, but are not limited to, the refractive index of the second sub-inorganic encapsulation layer and the refractive index of the third sub-inorganic encapsulation layer.
  • the first sub-inorganic encapsulation layer 711 and the second sub-inorganic encapsulation layer 712 are made of different materials; the fourth sub-inorganic encapsulation layer 714 and the third sub-inorganic encapsulation layer 713 can be made of different materials. Made of materials.
  • the first sub-inorganic encapsulation layer 711 is made of silicon oxide or silicon oxynitride material
  • the second sub-inorganic encapsulation layer 712 is made of silicon nitride material
  • the fourth sub-inorganic encapsulation layer 714 is made of silicon oxide material
  • the third sub-inorganic encapsulation layer 714 is made of silicon oxide material.
  • the encapsulation layer 713 is made of silicon nitride material.
  • the first sub-inorganic encapsulation layer 711 and the fourth sub-inorganic encapsulation layer 714 may be made of the same material or may be made of different materials.
  • the first sub-inorganic encapsulation layer 711 and the fourth sub-inorganic encapsulation layer 714 are both made of silicon oxide material; or the first sub-inorganic encapsulation layer 711 is made of silicon oxynitride material, and the fourth sub-inorganic encapsulation layer 714 is made of silicon oxide. Material production.
  • the first arched area GX1 of the first sub-inorganic encapsulation layer 711 has a first radius of curvature away from the upper surface of the substrate 512
  • the first arched area GX1 of the second sub-inorganic encapsulation layer 712 has a first radius of curvature.
  • the upper surface of the area GX1 away from the substrate 512 has a second radius of curvature.
  • the upper surface of the third sub-inorganic encapsulation layer 713 of the first arched area GX1 away from the substrate 512 has a third radius of curvature.
  • the upper surface of the first arched area GX1 away from the substrate 512 has a fourth radius of curvature, the first radius of curvature is smaller than the second radius of curvature, the second radius of curvature is smaller than the third radius of curvature, and the third radius of curvature is smaller than the fourth radius of curvature. That is to say, in the direction away from the driving substrate 510, the curvature radius of the first arched region of each sub-inorganic encapsulation layer gradually increases.
  • the second arched region of each sub-inorganic encapsulation layer is away from the substrate.
  • the radius of curvature of the upper surface of the bottom also gradually increases in the direction away from the driving substrate.
  • the third arched region of each sub-inorganic encapsulation layer is away from the substrate.
  • the radius of curvature of the upper surface of the bottom also gradually increases in the direction away from the driving substrate.
  • the first arched area GX1 , the second arched area GX2 and the third arched area GX3 of the first sub-inorganic encapsulation layer 711 have the same shape; the second sub-inorganic encapsulation layer 712
  • the first arched area GX1, the second arched area GX2 and the third arched area GX3 have the same shape; the first arched area GX1, the second arched area GX2 and the third arched area of the third sub-inorganic encapsulation layer 713
  • the shapes of the shaped areas GX3 are the same; the shapes of the first arcuate area GX1, the second arcuate area GX2 and the third arcuate area GX3 of the fourth sub-inorganic encapsulation layer 714 are the same.
  • the virtual center of the first arched area of the fourth sub-inorganic encapsulation layer 714 is located on the upper surface of the first sub-inorganic encapsulation layer 711 away from the substrate 512 and the fourth sub-inorganic encapsulation layer 714 close to the lower surface of substrate 512. It should be noted that the above-mentioned virtual center of the circle refers to the center of the virtual circle based on the arc of the first arched area away from the upper surface of the substrate.
  • the first sub-inorganic encapsulation layer 711 has a first thickness TH1 in a direction perpendicular to the driving substrate 510
  • the second sub-inorganic encapsulation layer 712 has a thickness in a direction perpendicular to the driving substrate 510
  • the second thickness TH2 the third sub-inorganic encapsulation layer 713 has a third thickness TH3 in the direction perpendicular to the driving substrate 510
  • the fourth sub-inorganic encapsulation layer 714 has a fourth thickness TH4 in the direction perpendicular to the driving substrate 510.
  • the first thickness TH1 is greater than the second thickness TH2, the second thickness TH2 is greater than the third thickness TH3, and the third thickness TH3 is greater than the fourth thickness TH4. That is to say, the thickness of each sub-inorganic packaging layer gradually decreases in the direction away from the driving substrate 510 .
  • the ratio of the sum of the second thickness TH2 and the third thickness TH3 to the first thickness TH1 ranges from 0.8 to 1.2; that is, the first thickness TH1, the second thickness TH2 and the first thickness TH1 are in a range of 0.8-1.2.
  • the first thickness ranges from 1000-1200 nanometers
  • the second thickness ranges from 500-660 nanometers
  • the third thickness ranges from 480-560 nanometers
  • the fourth thickness ranges from 180 nanometers to 180 nanometers. -260 nm.
  • the material of the first sub-inorganic encapsulation layer includes silicon oxide or silicon oxynitride
  • the material of the second sub-inorganic encapsulation layer includes silicon nitride
  • the material of the third sub-inorganic encapsulation layer includes silicon nitride
  • the material of the fourth sub-inorganic encapsulation layer includes silicon nitride.
  • the material of the inorganic encapsulation layer includes silicon oxide.
  • the embodiments of the present disclosure include but are not limited to this, and the material of each sub-inorganic encapsulation layer can also be other suitable materials.
  • the first thickness is 1100 nanometers
  • the second thickness is in the range of 580 nanometers
  • the third thickness is in the range of 520 nanometers
  • the fourth thickness is in the range of 220 nanometers.
  • the embodiments of the present disclosure include but are not limited to this, and the thickness of each sub-inorganic encapsulation layer can also be other values.
  • the encapsulation layer 560 further includes an organic encapsulation layer 720 located on a side of the inorganic encapsulation layer 710 away from the driving substrate 510 .
  • the organic encapsulation layer 720 includes a first region 7201, a second region 7202 and a third region 7203.
  • the average thickness of the first region 7201 is less than the average thickness of the second region 7202.
  • the average thickness of the second region 7202 is less than the average thickness of the third region 7203. thickness.
  • the organic encapsulation layer can better match the subsequently formed color filter sheets with different thicknesses.
  • the display substrate 500 further includes a color filter layer 570 , which is located on the side of the encapsulation layer 560 away from the driving substrate 510 ; the color filter layer 570 includes a first color filter 571 , the second color filter 572 and the third color filter 573.
  • the first color filter 571 , the second color filter 572 and the third color filter 573 may be color filters of different colors.
  • the first color filter 571, the second color filter 572, and the third color filter 573 may respectively have different thicknesses.
  • embodiments of the present disclosure include but are not limited to this.
  • the first overlapping area OP1 exists for the first color filter 571 and the second color filter 572 , and the second color filter 572 and the third color filter 573 exist.
  • the third color filter 573 and the first color filter 571 have a third overlapping area OP3.
  • the first overlapping area, the second overlapping area and the third overlapping area of the display substrate can all be used as a black matrix to achieve a light-shielding effect.
  • embodiments of the present disclosure include but are not limited to this.
  • Adjacent color filters may not overlap, and a black matrix is additionally formed between adjacent color filters.
  • the orthographic projection of the first overlapping area OP1 , the second overlapping area OP2 and the third overlapping area OP3 on the driving substrate 510 is spaced between two adjacent anodes 525
  • the orthographic projection of the area 522 on the driving substrate 510 overlaps, so that it can be used as a black matrix to achieve a light-shielding effect.
  • the display substrate shown in FIG. 8 only uses two color filters to overlap to form an overlapping area equivalent to a black matrix.
  • the display substrate provided by the embodiment of the present disclosure can also use three color filters. Two color filters are overlapped to form an overlapping area equivalent to a black matrix.
  • the orthographic projection of the first overlapping area OP1 , the second overlapping area OP2 , and the third overlapping area OP3 on the driving substrate 510 is the same as that of the protruding portion 525B on the driving substrate 510 .
  • the size of the first overlapping area OP1 in the second direction is larger than the size of the second overlapping area OP2 in the second direction, and the size of the second overlapping area OP2 in the second direction The size is larger than the size of the third overlapping area OP3 in the second direction.
  • the size of the first overlapping region OP1 in the second direction ranges from 400 to 600 nanometers
  • the size of the second overlapping region OP2 in the second direction ranges from 250 to 350 nanometers
  • the size range of the third overlapping region OP3 in the second direction is 100-200 nanometers.
  • the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 is larger than the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510 , and is smaller than the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510 .
  • the above-mentioned average size refers to the arithmetic average of the sizes of various parts on the color filter in a direction perpendicular to the driving substrate.
  • the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 ranges from 2.3 to 2.6 microns
  • the second color filter 572 has an average size in the direction perpendicular to the driving substrate 510
  • the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510 ranges from 1.7 to 1.95 microns
  • the average size of the third color filter 573 ranges from 2.3 to 2.7 microns in the direction perpendicular to the driving substrate 510 .
  • the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 is the same as the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510 .
  • the range of the difference and the ratio of the difference between the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 and the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510 is 2-3.
  • Figure 9 is a schematic diagram of a first color filter in a display substrate according to an embodiment of the present disclosure.
  • the first color filter 571 includes a first edge portion 571A, a second edge portion 571B, and a middle portion 571C located between the first edge portion 571A and the second edge portion 571B.
  • the middle portion The average size of 571C in the direction perpendicular to the driving substrate 510 is smaller than the average size of the first edge portion 571A in the direction perpendicular to the driving substrate 510 and the second edge portion 571B in the direction perpendicular to the driving substrate 510 .
  • the first color filter 571 includes a first contact surface 571C in contact with the second color filter 572
  • the second color filter 572 includes a first contact surface 571C with a third color filter.
  • 573 contacts the second contact surface 572C
  • the third color filter 573 includes a third contact surface 573C that contacts the first color filter 571
  • the first contact surface 571C is in a first direction perpendicular to the driving substrate 510.
  • the size is equal to the size of the second contact surface 572C in the first direction, and is smaller than the size of the third contact surface 573C in the first direction.
  • the distance between the first color filter 571 and the surface of the driving substrate 510 away from the anode layer 520 is greater than the distance between the third color filter 573 and the surface of the driving substrate 510 away from the anode layer 520 , and less than the distance between the second color filter 572 and the surface of the driving substrate 510 away from the anode layer 520 .
  • the first color filter is a red filter
  • the second color filter is a green filter
  • the third color filter is a blue filter.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first color filter, the second color filter and the third color filter may also be color filters of other colors.
  • the material of the color filter layer 570 includes a desiccant, which can prevent external water and oxygen from entering the film layer below the color filter layer.
  • color filter layer 570 includes aluminum elements.
  • the display substrate 500 further includes a protective layer 580 located on a side of the color filter layer 570 away from the driving substrate 510 .
  • the protective layer 580 can protect the color filter layer 570 so that the filtering performance of the color filter layer 570 remains stable during long-term use, thereby improving the display quality of the display substrate.
  • the display substrate 500 further includes a glass cover 590 located on the side of the color filter layer 570 away from the driving substrate 510 .
  • the flat area PTQ of the first sub-inorganic encapsulation layer 711 has a first width in the second direction
  • the flat area PTQ of the second sub-inorganic encapsulation layer 712 has a first width in the second direction.
  • Two widths, the flat area PTQ of the third sub-inorganic encapsulation layer 713 has a third width in the second direction
  • the flat area PTQ of the fourth sub-inorganic encapsulation layer 714 has a fourth width in the second direction
  • the first width is greater than the second width.
  • Two widths, the second width is greater than the third width
  • the third width is greater than the fourth width. That is, the first width, the second width, the third width and the fourth width gradually decrease.
  • FIG. 10 is a partial structural diagram of another display substrate according to an embodiment of the present disclosure. As shown in Figures 8 and 10, the flat area PTQ of the first sub-inorganic encapsulation layer 711 is close to the edge of the second arched area GX2, and the flat area PTQ of the second sub-inorganic encapsulating layer 712 is close to the edge of the second arched area GX2.
  • the flat area PTQ of the third sub-inorganic encapsulation layer 713 is close to the edge of the second arched area GX2 and the flat area PTQ of the fourth sub-inorganic encapsulating layer 714 is close to the edge of the second arched area GX2 and the first connection line L1 is connected to the drive
  • the included angle between the surfaces of the substrate 510 away from the anode layer 520 is the first included angle; the vertex of the second arched area GX2 of the first sub-inorganic encapsulation layer 711 and the first arched area GX1 of the second sub-inorganic encapsulation layer 712
  • the second connection line L2 between the vertex of the second arched area GX2 of the third sub-inorganic encapsulation layer 713 and the vertex of the second arched area GX2 of the fourth sub-inorganic encapsulation layer 714 is away from the anode layer 520 from the driving substrate 510
  • the angle between the surfaces is the second angle,
  • the first included angle ranges from 60 to 85 degrees
  • the second included angle ranges from 85 to 89 degrees.
  • the intersection point L2 of the first connection line L1 and the second connection line is located within the driving substrate 510 .
  • FIG. 11 is a schematic structural diagram of a driving substrate provided by an embodiment of the present disclosure.
  • the driving circuit 514 includes a semiconductor layer 102, a first conductive layer 301, a second conductive layer 302, a third conductive layer 303 and a fourth conductive layer 304; the semiconductor layer 102 is located in the substrate 512; A conductive layer 301 is located on the semiconductor layer 102; the second conductive layer 302 is located on the side of the first conductive layer 301 away from the substrate 512; the third conductive layer 303 is located on the side of the second conductive layer 302 away from the substrate 512; the fourth The conductive layer 304 and the third conductive layer 303 are on a side away from the substrate 512 .
  • the intersection of the first connection line L1 and the second connection line L2 is located between the upper surface of the third conductive layer 303 away from the substrate 512 and the anode layer 520 .
  • the distance between the intersection of the first connection line L1 and the second connection line L2 and the vertex of the protrusion structure 535 of the pixel definition layer 530 away from the upper surface of the substrate 512 is greater than the first sub-inorganic The thickness of the encapsulation layer 711 in the first direction.
  • the distance between the intersection of the first connection line L1 and the second connection line L2 and the vertex of the protrusion structure 535 of the pixel definition layer 530 away from the upper surface of the substrate 512 is less than the first sub-inorganic The sum of the thickness of the encapsulation layer 711 in the first direction and the thickness of the second sub-inorganic encapsulation layer 712 in the first direction.
  • the second arched region GX2 of the first sub-inorganic encapsulation layer 711 is close to the edge of the double arch spacer JGQ
  • the second arched region GX2 of the second sub-inorganic encapsulation layer 712 is close to the edge of the double arch spacer JGQ.
  • the edge of the arch separation area JGQ, the second arch area GX2 of the third sub-inorganic encapsulation layer 713 is close to the edge of the double arch separation area JGQ
  • the second arch area GX2 of the fourth sub-inorganic encapsulation layer 714 is close to the double arch separation area JGQ.
  • the angle between the third connection line L3 on the edge and the surface of the driving substrate 510 away from the anode layer 520 is the third angle
  • the third angle is smaller than the second angle.
  • the intersection of the first connection line L1 and the third connection line L3 is located on the upper surface of the second conductive layer 302 away from the substrate 512 and the lower surface of the third conductive layer 303 close to the substrate 512 between.
  • the intersection of the second connection line L2 and the third connection line L3 is located on the lower surface of the first conductive layer 301 close to the substrate 512 and the lower surface of the substrate 512 away from the first conductive layer 301 between.
  • the third arched area GX3 of the first sub-inorganic encapsulation layer 711 is away from the edge of the double arch spacer JGQ, and the third arched area GX3 of the second sub-inorganic encapsulation layer 712
  • the included angle between the fourth connection line L4 away from the edge of the double-arch spacer JGQ and the surface of the driving substrate 510 away from the anode layer 520 is the fourth included angle, and the fourth included angle is smaller than the second included angle.
  • the intersection of the first connection line L1 and the fourth connection line L4 is located on a side of the substrate 512 away from the first conductive layer 301 .
  • the intersection of the third connection line L3 and the fourth connection line L4 is located on the upper surface of the second conductive layer 302 away from the substrate 512 and the lower surface of the third conductive layer 303 close to the substrate 512 between.
  • FIG. 12 is a partial structural diagram of a display substrate according to an embodiment of the present disclosure.
  • the color filter layer 570 also includes a black matrix 574 located between any two adjacent ones of the first color filter 571 , the second color filter 572 and the third color filter 573 .
  • the orthographic projection of the black matrix 574 on the driving substrate 510 overlaps the orthographic projection of the spacing area 522 between two adjacent anodes 525 on the driving substrate 510 .
  • the display substrate 500 further includes a protective layer 580 located on a side of the color filter layer 570 away from the driving substrate 510 .
  • the protective layer 580 can protect the color filter layer 570 so that the filtering performance of the color filter layer 570 remains stable during long-term use, thereby improving the display quality of the display substrate.
  • the display substrate 500 further includes a glass cover 590 located on the side of the color filter layer 570 away from the driving substrate 510 .
  • FIG. 13 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 13 , the display device 900 includes the above-mentioned display substrate 500 . Therefore, the display device has technical effects corresponding to the beneficial technical effects of the display substrate.
  • the anode since the anode includes a main body portion and a protruding portion, and the protruding portion has a larger size in a direction perpendicular to the driving substrate than a size of the main body portion in a direction perpendicular to the driving substrate, it is located at two
  • the pixel defining layer between the anodes and overlapping the edge portion of the anode may form a protruding structure corresponding to the protruding portion.
  • the light-emitting functional layer When forming the light-emitting functional layer, at least part of the sub-functional layers (such as the charge generation layer) in the light-emitting functional layer can be better disconnected at the position where the protruding structure is located, that is, at least part of the light-emitting parts corresponding to two adjacent anodes The sub-functional layers are not connected, thus effectively avoiding leakage and crosstalk between adjacent sub-pixels.
  • the height of the protruding structure of the pixel defining layer is also higher at this time, which can better play the role of pixel defining and optically reduce and avoid crosstalk between adjacent sub-pixels. Therefore, the display substrate can also reduce or even avoid crosstalk between adjacent sub-pixels, thereby having better display quality.
  • the driving substrate in the display substrate can be manufactured using a semiconductor manufacturing process
  • the pixel driving circuit for driving each pixel to emit light and display can be integrated into the driving substrate. Therefore, the display device can provide a miniature display device and has the advantages of high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption.
  • the display device 900 may be a wearable display device, such as a smart watch, smart glasses, etc.
  • a wearable display device such as a smart watch, smart glasses, etc.
  • the embodiments of the present disclosure include but are not limited to this.
  • the display device can also be other electronic products with display functions, such as mobile phones, televisions, navigators, electronic photo albums, electronic picture frames, computer monitors, etc.
  • FIG. 14 is a plan view of a display device according to an embodiment of the present disclosure.
  • the display device 900 includes a display area 910 and a peripheral area 920 located around the display area 910 ; the peripheral area 920 of the display device 900 includes a wiring area 930 .
  • the display area 910 can be used for light-emitting display, and the wiring area 930 can be used to lead various driving lines or signal lines from the display area 910 .
  • FIG. 15 is a schematic diagram of another display device provided by an embodiment of the present disclosure.
  • the display substrate 500 included in the display device 900 does not include a color filter layer.
  • the display device 900 also includes a counter substrate 800, which is arranged opposite to the display substrate 500; the counter substrate 800 includes a glass cover 810 and a color filter layer 570 located on the glass cover 810.
  • the color filter layer 570 includes a first color filter 571 , a second color filter 572 and a third color filter 573 . Therefore, the display substrate and the counter substrate can be separately manufactured first, and then the display substrate and the counter substrate can be aligned to form the above display device.
  • the display device has technical effects corresponding to the beneficial technical effects of the display substrate.
  • the anode since the anode includes a main body portion and a protruding portion, and the protruding portion has a larger size in a direction perpendicular to the driving substrate than a size of the main body portion in a direction perpendicular to the driving substrate, it is located at two
  • the pixel defining layer between the anodes and overlapping the edge portion of the anode may form a protruding structure corresponding to the protruding portion.
  • the light-emitting functional layer When forming the light-emitting functional layer, at least part of the sub-functional layers (such as the charge generation layer) in the light-emitting functional layer can be better disconnected at the position where the protruding structure is located, that is, at least part of the light-emitting parts corresponding to two adjacent anodes The sub-functional layers are not connected, thus effectively avoiding leakage and crosstalk between adjacent sub-pixels.
  • the height of the protruding structure of the pixel defining layer is also higher at this time, which can better play the role of pixel defining and optically reduce and avoid crosstalk between adjacent sub-pixels. Therefore, the display substrate can also reduce or even avoid crosstalk between adjacent sub-pixels, thereby having better display quality.
  • the driving substrate in the display substrate can be manufactured using a semiconductor manufacturing process
  • the pixel driving circuit for driving each pixel to emit light and display can be integrated into the driving substrate. Therefore, the display device can provide a miniature display device and has the advantages of high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption.
  • the display device 900 may be a wearable display device, such as a smart watch, smart glasses, etc.
  • a wearable display device such as a smart watch, smart glasses, etc.
  • the embodiments of the present disclosure include but are not limited to this.
  • the display device can also be other electronic products with display functions, such as mobile phones, televisions, navigators, electronic photo albums, electronic picture frames, and computer monitors.
  • the first overlapping area OP1 exists for the first color filter 571 and the second color filter 572 , and the second color filter 572 and the third color filter 573 exist.
  • the third color filter 573 and the first color filter 571 have a third overlapping area OP3.
  • the first overlapping area, the second overlapping area and the third overlapping area of the display substrate can all be used as a black matrix to achieve a light-shielding effect.
  • embodiments of the present disclosure include but are not limited to this. Adjacent color filters may not overlap, and a black matrix may be additionally formed between adjacent color filters.
  • the orthographic projection of the first overlapping area OP1 , the second overlapping area OP2 and the third overlapping area OP3 on the driving substrate 510 is spaced between two adjacent anodes 525
  • the orthographic projections of areas 522 on the drive substrate 510 overlap.
  • the display substrate shown in FIG. 14 only uses two color filters to overlap to form an overlapping area equivalent to a black matrix.
  • the display substrate provided by the embodiment of the present disclosure can also use three color filters. Two color filters are overlapped to form an overlapping area equivalent to a black matrix.
  • the size of the first overlapping area OP1 in the second direction is larger than the size of the second overlapping area OP2 in the second direction, and the size of the second overlapping area OP2 in the second direction The size is larger than the size of the third overlapping area OP3 in the second direction.
  • the size of the first overlapping region OP1 in the second direction ranges from 400 to 600 nanometers
  • the size of the second overlapping region OP2 in the second direction ranges from 250 to 350 nanometers
  • the size range of the third overlapping region OP3 in the second direction is 100-200 nanometers.
  • the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 is larger than the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510 , and is smaller than the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510 .
  • the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 ranges from 2.3 to 2.6 microns
  • the second color filter 572 has an average size in the direction perpendicular to the driving substrate 510
  • the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510 ranges from 1.7 to 1.95 microns
  • the average size of the third color filter 573 ranges from 2.3 to 2.7 microns in the direction perpendicular to the driving substrate 510 .
  • the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 is the same as the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510 .
  • the range of the difference and the ratio of the difference between the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 and the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510 is 2-3.
  • the first color filter 571 includes a first edge portion 571A, a second edge portion 571B, and a middle portion between the first edge portion 571A and the second edge portion 571B.
  • the average size of the middle portion 571M in the direction perpendicular to the driving substrate 510 is smaller than the average size of the first edge portion 571A in the direction perpendicular to the driving substrate 510 and the second edge portion 571B in the direction perpendicular to the driving substrate 510 . average size on.
  • the first color filter 571 includes a first contact surface 571C in contact with the second color filter 572
  • the second color filter 572 includes a contact surface with a third color filter.
  • 573 contacts the second contact surface 572C
  • the third color filter 573 includes a third contact surface 573C that contacts the first color filter 571
  • the size of the second contact surface in the first direction is equal to and smaller than the size of the third contact surface in the first direction.
  • the distance between the first color filter 571 and the surface of the driving substrate 510 away from the anode layer 520 is greater than the distance between the third color filter 573 and the surface of the driving substrate 510 away from the anode layer 520 , and less than the distance between the second color filter 572 and the surface of the driving substrate 510 away from the anode layer 520 .
  • the first color filter is a red filter
  • the second color filter is a green filter
  • the third color filter is a blue filter.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first color filter, the second color filter and the third color filter may also be color filters of other colors.
  • the material of the color filter layer 570 includes a desiccant, which can prevent external water and oxygen from entering the film layer below the color filter layer.
  • color filter layer 570 includes aluminum elements.
  • FIG. 16 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display device 900 includes a plurality of pixel units PU arranged in an array in a display area 910 .
  • the plurality of pixel units PU may include one of the above-mentioned driving circuits and a The anode mentioned above.
  • the display device 900 further includes a row driving circuit 200 prepared in the substrate.
  • the row driving circuit 200 is configured to provide a third driving circuit to the driving circuits in the plurality of pixel units PU in the display device 900 .
  • the row driving circuit 200 is provided in the peripheral area 920 surrounding the display area 910.
  • FIG. 17 is a partial cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 500 includes a driving substrate 510 .
  • the driving substrate 510 includes a driving circuit 514 .
  • the driving circuit 514 is electrically connected to the anode 525 so that the light-emitting functional layer 540 in contact with the anode 525 emits light.
  • the anode, light-emitting functional layer, packaging layer and other structures in the display substrate shown in Figure 17 can adopt the relevant designs in the display substrate provided in the above embodiments.
  • the driving substrate 510 includes a transistor T, and the transistor T includes a gate electrode G, a source electrode S, and a drain electrode D.
  • the three electrodes respectively correspond to three electrode connection parts.
  • the gate electrode G is electrically connected to the gate electrode connecting portion 610g
  • the source electrode S is electrically connected to the source electrode connecting portion 610s
  • the drain electrode D is electrically connected to the drain electrode connecting portion 610d.
  • the three electrodes are electrically connected to the three electrode connecting portions through tungsten via holes 605 .
  • the source electrode connection portion 610s is electrically connected to the anode 525 through a tungsten via hole.
  • the source electrode connection portion 610s is electrically connected to the metal reflective layer 593 through a tungsten via hole, and at the same time, the anode 525 is electrically connected to the metal reflective layer 593 through the via hole 624a in the inorganic insulating layer 624.
  • the electrical signal provided by the power line can be transmitted to the anode 525 through the source electrode S of the transistor T, the source electrode connection portion 610s, and the metal reflective layer 593.
  • the positions of the source electrode S and the drain electrode D can be interchanged (correspondingly, the positions of the source electrode connection portion 610s and the drain electrode connection portion 610d can also be interchanged).
  • the materials of the gate electrode connection part 610g, the source electrode connection part 610s, and the drain electrode connection part 610d may include metal materials.
  • an anti-oxidation layer 607 may be provided on at least one side (eg, upper side and/or lower side) of each of the gate electrode connection portion 610g, the source electrode connection portion 610s, and the drain electrode connection portion 610d, so that It can effectively prevent these electrode connections from being oxidized and improve their conductive properties.
  • the display substrate 500 further includes a pixel defining layer 530 for defining the light-emitting functional layer 540 .
  • the pixel defining layer 530 defines the organic light-emitting functional layer 540 in its pixel opening 535 to avoid being adjacent to each other. crosstalk between sub-pixels.
  • the via hole 624 a in the inorganic insulating layer 624 may be provided between the anode 525 and the edge region of the metal reflective layer 593 .
  • the orthographic projection of the light-emitting functional layer 540 on the driving substrate 510 and the orthographic projection of the via hole 624a on the driving substrate 510 are both located within the orthographic projection of the metal reflective layer 593 on the driving substrate 510, and at the same time, the light emitting There is no overlap between the orthographic projection of the functional layer 540 on the driving substrate 510 and the orthographic projection of the via hole 624a on the driving substrate 510. Therefore, when the metal reflective layer reflects the light emitted by the light-emitting functional layer 540, the via hole 624a This reflection process has essentially no effect.
  • FIG. 18 is an equivalent schematic diagram of a driving circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 19 is a schematic plan view of a driving circuit in a display substrate according to an embodiment of the present disclosure.
  • the driving circuit 514 includes a driving transistor 140 , a first transistor 110 , a second transistor 120 and a third transistor 130 . It should be noted that in some embodiments, the driving circuit may not include the third transistor 130 , and the embodiments of the present disclosure do not limit this.
  • the driving transistor 140 includes a control electrode 143, a first electrode 141 and a second electrode 142, and the driving transistor 140 is configured to control the flow through the first electrode 141 of the driving transistor 140 according to the voltage of the control electrode 143 of the driving transistor 140. and a driving current of the second pole 142 of the driving transistor 140 for driving the light emitting element LE to emit light.
  • the light-emitting element LE can emit light of different intensities according to the size of the driving current.
  • the source and drain of the transistor used in the embodiment of the present disclosure may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, in the embodiment of the present disclosure, the first pole of all or part of the transistor is The pole and second pole are interchangeable as needed.
  • the first electrode of the transistor described in the embodiment of the present disclosure may be the source electrode, and the second electrode may be the drain electrode; or, the first electrode of the transistor may be the drain electrode, and the second electrode may be the source electrode.
  • the drain electrode and the source electrode of the second electrode of the transistor are used as examples for description, and details will not be described again.
  • the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1.
  • the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.
  • the third transistor 130 is connected to the first pole 141 of the driving transistor 140 and is configured to apply the first power supply voltage ELVDD to the first pole 141 of the driving transistor 140 in response to the light emission control signal EN.
  • the first power supply voltage ELVDD in the embodiment of the present disclosure is a high-level voltage, for example, the first power supply voltage ELVDD is 5V.
  • the first electrode 111 (eg, drain electrode) of the first transistor 110 and the first electrode 121 (eg, drain electrode) of the second transistor 120 are connected to obtain a common electrode, and The common electrode is connected to the control electrode 143 of the drive transistor 140 .
  • the first scanning signal line SL1, the second scanning signal line SL2, the data line DL, the first power supply voltage line VL1, the light emission control line EL, etc. are also provided to provide corresponding electrical signals.
  • the control electrode 113 of the first transistor 110 is configured to receive the first scan signal SCAN1 from the first scan signal line SL1, and the second electrode 112 (eg, source electrode) of the first transistor 110 is configured to receive a data signal from the data line DL. DATA.
  • the control electrode 123 of the second transistor 120 is configured to receive the second scan signal SCAN2 from the second scan signal line SL2, and the second electrode 122 (eg, source electrode) of the second transistor 120 is configured to receive the data signal from the data line DL. DATA.
  • the control electrode 133 of the third transistor 130 is configured to receive the light emission control signal EN from the light emission control line EL, and the first electrode 131 (eg, drain electrode) of the third transistor 130 is configured to receive the first power supply voltage line VL1 from the first power supply voltage line VL1.
  • the power supply voltage ELVDD, the second electrode 132 (for example, the source electrode) of the third transistor 130 and the first electrode 141 (for example, the drain electrode) of the driving transistor 140 are connected.
  • the second electrode 142 (eg, source electrode) of the driving transistor 140 is configured to be connected to the first electrode of the light emitting element LE.
  • the second electrode 142 of the driving transistor 140 may be connected to the anode of the OLED.
  • the second pole of the light emitting element LE is configured to receive the fourth power supply voltage VCOM.
  • the fourth power supply voltage VCOM in the embodiment of the present disclosure is a low-level voltage.
  • the light-emitting element LE may be an OLED.
  • the second electrodes (for example, cathodes) of the multiple light-emitting elements OLED in the multiple pixel units ) can be electrically connected together, for example, respectively connected to the same electrode or formed integrally to receive the fourth power supply voltage VCOM, that is, multiple light-emitting elements OLED in multiple pixel units adopt a common cathode connection method.
  • the light-emitting element OLED can be of various types, such as top-emitting, bottom-emitting, etc., and can emit red light, green light, blue light, or white light, etc., which are not limited in the embodiments of the present disclosure.
  • the driving circuit further includes a storage capacitor CST to store the data signal DATA written to the control electrode 143 of the driving transistor 140 , so that the driving transistor 140 can control the driving according to the voltage of the stored data signal DATA.
  • the first electrode of the storage capacitor CST is connected to the control electrode 143 of the driving transistor 140, and the second electrode of the storage capacitor CST is configured to receive the third power supply voltage AVSS.
  • the third power supply voltage AVSS in the embodiment of the present disclosure is a low-level voltage.
  • the third power supply voltage AVSS may be the same as the fourth power supply voltage VCOM.
  • the third power supply voltage AVSS and the fourth power supply voltage VCOM may both be grounded. Embodiments of the present disclosure include But not limited to this.
  • the first transistor 110 may be a P-type MOS transistor, and the second transistor 120 , the third transistor 130 and the driving transistor 140 may be N-type MOS transistors.
  • the first transistor 110 may be a P-type MOS transistor.
  • the transistor 110, the second transistor 120, the third transistor 130, and the driving transistor 140 are formed in the substrate.
  • the third stage of the first transistor 110 is configured to receive the second power supply voltage VDD.
  • the third stage of the first transistor 110 is connected to the second power supply voltage line VL2 to receive the second power supply voltage. VDD.
  • the third electrodes of the second transistor 120, the third transistor 130, and the driving transistor 140 are configured to be grounded (GND).
  • the third pole of a transistor is a pole opposite to the control electrode (gate) 113 of the transistor. This is the same in the following embodiments and will not be described again.
  • the first transistor 110 and the second transistor 120 may constitute a transmission gate switch with complementary characteristics.
  • the first scan signal SCAN1 provided to the first transistor 110 and the second scan signal SCAN2 provided to the second transistor 120 can be made to be inverse signals of each other, so that the first transistor 110 can be ensured
  • One of the second transistors 120 and the second transistor 120 is always in a conductive state at the same time, so that the data signal DATA can be transmitted to the storage capacitor CST without voltage loss, thereby improving the reliability and stability of the driving circuit.
  • the direction along the first pole 111 of the first transistor 110 to the second pole 112 of the first transistor 110 is called the first direction D1
  • the direction along the second transistor 120 The direction from the first pole 121 to the second pole 122 of the second transistor 120 is called the second direction D2
  • the direction along the first pole 131 of the third transistor 130 to the second pole 132 of the third transistor 130 is called the second direction D2.
  • the three directions D3, the direction along the first pole 141 of the driving transistor 140 to the second pole 142 of the driving transistor 140 is called the fourth direction D4.
  • the first direction in Figures 1 to 15 is different from the first direction provided in this embodiment, and the second direction in Figures 1 to 15 can be the same as the second direction provided in this embodiment, or they can different.
  • the fourth direction D4 is the lateral direction from left to right in FIG. 19 .
  • the driving transistor 140 can be configured when laying out the position of the transistor.
  • the transistors 140 are arranged along the fourth direction D4, and at the same time, at least one of the first direction D1, the second direction D2, and the third direction D3 intersects the fourth direction D4. This can make the layout of the four transistors more compact, thereby reducing the cost.
  • the layout area occupied by the display substrate 500 is reduced, thereby making it easier for the display substrate 500 to achieve high PPI.
  • the first direction D1 and the second direction D2 can both intersect with the fourth direction D4; for another example, the first direction D1, the second direction D2 and the third direction D3 can all intersect with the third direction D4.
  • the four directions D4 intersect.
  • the fourth direction D4 is the transverse direction
  • the first direction D1 , the second direction D2 and the third direction D3 are all longitudinal directions perpendicular to the transverse direction in FIG. 3 .
  • the first direction D1 and the second direction D2 are both perpendicular to the fourth direction D4; for another example, the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4. vertical.
  • this approach can make the layout of the display substrate 500 more compact, thereby further reducing the space occupied by the display substrate 500. layout area, thereby making it easier for the display substrate 500 to achieve high PPI.
  • the first transistor 110 includes a first active region 114 extending along the first direction D1 .
  • the first active region 114 includes a first electrode 111 of the first transistor 110 , a third electrode of the first transistor 110 .
  • the second transistor 120 includes a second active region 124 extending along the second direction D2.
  • the second active region 124 includes the first electrode 121 of the second transistor 120, the second electrode 122 of the second transistor 120, and the second transistor 120.
  • a channel region is formed between the first electrode 121 of the second transistor 120 and the second electrode 122 of the second transistor 120 .
  • the third transistor 130 includes a third active region 134 extending along the third direction D3.
  • the third active region 134 includes a first electrode 131 of the third transistor 130, a second electrode 132 of the third transistor 130, and a third body.
  • a channel region is formed between the first electrode 131 of the transistor 130 and the second electrode 132 of the third transistor 130.
  • the driving transistor 140 includes a fourth active region 144 extending along the fourth direction D4.
  • the fourth active region 144 includes a first electrode 141 of the fourth transistor 140, a second electrode 142 of the fourth transistor 140, and a fourth body transistor.
  • a channel region is formed between the first electrode 141 of the fourth transistor 140 and the second electrode 142 of the fourth transistor 140 .
  • the substrate in the display substrate 500 provided by the embodiment of the present disclosure is a silicon-based substrate, and the above-mentioned first active region 114 , second active region 124 , third active region 134 and fourth active region 144 They are all doped areas in the silicon-based substrate. These doped areas are obtained by, for example, ion implantation or ion diffusion.
  • P-type doping can be achieved by doping boron (B)
  • N-type doping can be achieved by doping boron (B).
  • It can be achieved by doping phosphorus (P) or arsenic (As), which is not limited in the embodiments of the present disclosure.
  • first active region 114 and second active region 124 have opposite doping types.
  • the doping type of the first active region 114 is P type
  • the doping type of the second active region 124 is N type.
  • both ends of the first active region 114 and both ends of the second active region 124 are aligned with each other in the fourth direction D4 , and for example, both ends of the first active region 114
  • the end portion and the second active area 124 are arranged adjacent to each other. In this way, the layout design of the display substrate 500 can be simplified.
  • a line connecting an edge of the first active region 114 along the first direction D1 and an edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4; the first active region 114 is aligned along the first direction D1
  • a line connecting the other edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4.
  • the driving current for the light emitting element LE in the display substrate 500 is 1 to 2 orders of magnitude smaller.
  • the current characteristics of the drive transistor 140 in the saturated state are:
  • ID is the driving current provided by the driving transistor 140
  • W/L is the width-to-length ratio of the driving transistor 140
  • K is a constant value
  • V GS4 is the voltage difference between the gate and the source of the driving transistor 140
  • V th is the threshold voltage of the drive transistor 140 .
  • the L value of the driving transistor 140 must be increased during size design, which is not conducive to reducing the layout area of the display substrate 500 using the driving transistor 140 .
  • the driving circuit 514 provided by some embodiments of the present disclosure is configured by adjusting the relative relationship between the doping concentrations of the first active region 114 , the second active region 124 , the third active region 134 and the fourth active region 144 . Adjustments can improve or avoid the above problems.
  • the doping concentration of the fourth active region 144 is smaller than the doping concentration of the third active region 134 .
  • the third active region 134 has a doping concentration of approximately 10 17 cm -3
  • the fourth active region 144 has a doping concentration of approximately 10 13 cm -3
  • the fourth active region 144 has a doping concentration higher than that of the fourth active region 144 .
  • the doping concentration of the third active region 134 is 4 orders of magnitude smaller.
  • the doping concentration of at least one of the first active region 114 and the second active region 124 is greater than the doping concentration of the third active region 134 .
  • the doping concentration of the first active region 114 and the second active region 124 is greater than the doping concentration of the third active region.
  • the doping concentration of the first active region 114 and the second active region 124 is about 10 20 cm -3 .
  • the doping concentration of the first active region 114 and the second active region 124 It is 3 orders of magnitude greater than the doping concentration of the third active region 134 .
  • the first transistor 110 and the second transistor 120 are used as switching transistors in the driving circuit, so they need to have good switching characteristics.
  • the doping concentration of the first active region 114 or/and the second active region 124 is larger, a larger driving current can be obtained and the driving current changes more quickly, so that the first transistor 110 or/and The second transistor 120 has better switching characteristics.
  • the first transistor 110 is a first semiconductor type MOS transistor
  • the second transistor, the third transistor and the driving transistor are all second semiconductor type MOS transistors.
  • the first semiconductor type and the second semiconductor type on the contrary.
  • the first semiconductor type is P type
  • the second semiconductor type is N type.
  • Embodiments of the present disclosure include but are not limited to this.
  • the display substrate 500 provided by some embodiments of the present disclosure further includes a first scanning signal line SL1 for transmitting the first scanning signal SCAN1 and a second scanning signal line SL2 for transmitting the second scanning signal SCAN2 , the first scanning signal line SL1 and the second scanning signal line SL2 are arranged in parallel.
  • the first scan signal line SL1 is connected to the control electrode 113 of the first transistor 110 to provide the first scan signal SCAN1
  • the second scan signal line SL2 is connected to the control electrode 123 of the second transistor 120 to provide the second scan signal SCAN2.
  • the extending directions of the first scanning signal line SL1 and the second scanning signal line SL2 are both parallel to the fourth direction D4.
  • the orthographic projection of the first scanning signal line SL1 on the substrate is parallel to the orthographic projection of the second scanning signal line SL2 on the substrate, for example, both are parallel to the fourth direction D4.
  • the area where the front projection of the driving circuit 514 is located on the substrate 512 is a pixel area, and the first scanning signal line SL1 and the second scanning signal line SL2 are juxtaposed to one side of the pixel area.
  • the display substrate 500 provided by some embodiments of the present disclosure also includes a data line DL for transmitting the data signal DATA.
  • the orthogonal projection of the second scanning signal line SL2 on the substrate is the same as the data line DL on the substrate. Orthographic projections overlap at least partially.
  • the second scanning signal line SL2 overlaps the data line DL in a direction perpendicular to the substrate.
  • the plane of Figure 19 can be regarded as the plane of the substrate, then it is perpendicular to the substrate, that is, perpendicular to the plane of Figure 19.
  • the data line DL does not occupy additional layout area, thereby further reducing the size of the display substrate 500 .
  • the occupied layout area is more conducive to achieving high PPI.
  • the display substrate 500 provided by some embodiments of the present disclosure further includes a first power supply voltage line VL1 for transmitting the first power supply voltage ELVDD and a light-emitting control line EL for transmitting the light-emitting control signal EN.
  • part of the extension direction of the first power supply voltage line VL1 and the light-emitting control line EL is parallel to the fourth direction D4, and the first scanning signal line SL1, the second scanning signal line SL2, the first power voltage line VL1 and the light-emitting control line EL are in The orthographic projections of the substrates are arranged sequentially along the vertical direction to the fourth direction D4.
  • the front projection of the first power supply voltage line VL1 on the substrate is located at the front projection of the second scanning signal line SL2 on the substrate.
  • the projection and luminescence control line EL is between the front projection of the substrate. Since the first power supply voltage ELVDD transmitted by the first power supply voltage line VL1 is a DC signal, and the second scanning signal SCAN2 transmitted by the second scanning signal line SL2 and the luminescence control
  • the light-emitting control signals EN transmitted on the line EL are all transition signals, so the above arrangement can effectively shield the mutual interference between the second scanning signal SCAN2 and the light-emitting control signal EN.
  • the display substrate 500 provided by some embodiments of the present disclosure further includes a second power supply voltage line VL2 for transmitting the second power supply voltage VDD, a third electrode of the first transistor 110 and the second power supply voltage line VL2 Electrically connected to receive the second supply voltage VDD.
  • the second power supply voltage VDD in the embodiment of the present disclosure is a high-level voltage, for example, the second power supply voltage is 5V.
  • the first transistor 110 is a P-type MOS transistor, and its channel region is P-type doped.
  • the third electrode opposite to the control electrode (gate electrode) 113 of the first transistor 110 receives the second power supply voltage VDD.
  • the second transistor 120, the third transistor 130 and the driving transistor 140 are all N-type MOS transistors, and their channel regions are N-type doped.
  • the third electrodes of the second transistor 120, the third transistor 130 and the driving transistor 140 are Configured for ground (GND).
  • the orthographic projection of the second power supply voltage line VL2 on the substrate is located between the orthographic projection of the first power supply voltage line VL1 on the substrate and the orthographic projection of the light emission control line EL on the substrate, and a portion of the second power supply voltage line VL2
  • the extending direction is parallel to the fourth direction D4.
  • the second power supply voltage line VL2 has a bending area when extending along the fourth direction D4; in addition, the light-emitting control line EL also has a bending area when extending along the fourth direction D4, and the The bending directions of the two power supply voltage lines VL2 and the light-emitting control lines EL are different. Adopting this wiring method can, for example, leave layout space for the first transfer electrode AE1 described below.
  • the first transistor 110 and the second transistor 120 are both disposed between the second scanning signal line SL2 and the light emission control line EL, and the first transistor 110 and the first power supply voltage line VL1 and the second power supply The voltage line VL2 intersects, and the second transistor 120 intersects the first power supply voltage line VL1 and the second power supply voltage line VL2.
  • the orthographic projection of the first active region 114 of the first transistor 110 on the substrate and the orthographic projection of the second active region 124 of the second transistor 120 on the substrate are both located at the position of the second scanning signal line SL2 on the substrate. between the orthographic projection on the substrate and the orthographic projection of the luminescence control line EL on the substrate.
  • the orthographic projection of the first active region 114 of the first transistor 110 on the substrate intersects the orthographic projection of the first power supply voltage line VL1 on the substrate, and the first active region 114 of the first transistor 110 is on the substrate.
  • the orthographic projection of V intersects the orthographic projection of the second power supply voltage line VL2 on the substrate.
  • the orthographic projection of the second active region 124 of the second transistor 120 on the substrate intersects the orthographic projection of the first power supply voltage line VL1 on the substrate, and the second active region 124 of the second transistor 120 is on the substrate.
  • the orthographic projection of V intersects the orthographic projection of the second power supply voltage line VL2 on the substrate.
  • the display substrate 500 provided by some embodiments of the present disclosure further includes a first transfer electrode AE1 disposed on the first side of the light-emitting control line EL, and extending from the first side of the light-emitting control line EL to the light-emitting control line EL.
  • the orthographic projection of the second transfer electrode AE2 on the substrate intersects the orthographic projection of the light emission control line EL on the substrate.
  • the two ends of the first transfer electrode AE1 are electrically connected to the first pole 111 of the first transistor 110 and the first pole 121 of the second transistor 120 respectively, and the first transfer electrode AE1 and the second transfer electrode AE2 are electrically connected.
  • the second transfer electrode AE2 is electrically connected to the control electrode 143 of the driving transistor 140 .
  • the extension direction of the second transfer electrode AE2 is perpendicular to the extension direction of the first transfer electrode AE1 and perpendicular to the fourth direction D4.
  • the level on the second transfer electrode AE2 may fluctuate greatly during operation of the driving circuit. This fluctuation may cause crosstalk on the first power supply voltage line VL1. generate noise.
  • the first power supply voltage line VL1 and the second transfer electrode AE2 are separated by the second power supply voltage line VL2, so that the level on the second transfer electrode AE2 can be reduced. Crosstalk caused by fluctuations on the first power supply voltage line VL1 isolates noise.
  • some embodiments of the present disclosure provide a display substrate 500 that extends the first active region 114 of the first transistor 110 and the second active region 124 of the second transistor 120 to leave room for the second power supply voltage line VL2 Wiring channels.
  • the layout size of the driving circuit (rectangular shape) provided by the embodiment of the present disclosure is approximately 4.5um ⁇ 2.9um.
  • FIGS. 20A-20E respectively show plan views of the layout of each layer of the display substrate 500 shown in FIG. 19 .
  • the layer shown in Figure 4A may be referred to as the active display (AA) layer.
  • the layer shown at 4B may be referred to as a first conductive layer, which will be further described below.
  • the material of the first conductive layer may be polysilicon.
  • FIG. 20C shows the first power supply voltage line VL1, the second power supply voltage line VL2, the light emission control line EL, the data line DL, the ground line GND, the first transfer electrode AE1, and the like.
  • the layer shown in FIG. 20C may be referred to as a first metal layer (metal1).
  • FIG. 20D shows the second transfer electrode AE2, the electrode connecting the first scanning signal line SL1 and the first transistor 110, and the electrode connecting the second scanning signal line SL2 and the second transistor 120.
  • the layer shown in FIG. 20D may be referred to as the second metal layer (metal2).
  • FIG. 20E shows the first scanning signal line SL1 and the second scanning signal line SL2.
  • the layer shown in FIG. 20E can be called a third metal layer (metal3).
  • the storage capacitor CST is not shown in FIG. 19 for clarity of illustration.
  • the storage capacitor CST shown in FIG. 18 will be further described below in conjunction with FIGS. 21-23E.
  • area 850 shown in FIG. 21 is an area where storage capacitor CST is provided. It should be noted that, for clarity of illustration, the corresponding marks of all structures are not shown in FIG. 21 , and the omitted parts can be referred to the corresponding marks in FIG. 19 .
  • FIG. 22 is a layout diagram of storage capacitor CST
  • FIG. 23A to FIG. 23D are plan views corresponding to the layout of each layer in FIG. 22
  • FIG. 23E is a schematic cross-sectional view of storage capacitor CST.
  • Figure 22 shows a 4-layer structure, which are the third metal layer metal3, the fourth metal layer metal4, the auxiliary metal layer metal4', and the fifth metal layer metal5; the first via V1 and the second via are also shown.
  • V2 the first via hole V1 and the second via hole V2 will be described below in conjunction with the cross-sectional schematic diagram, and will not be described again here.
  • FIG. 23A shows a third metal layer metal3, which is, for example, the same layer as the layer shown in FIG. 20E.
  • the third metal layer metal3 includes two parts, namely an electrode 811 serving as the first pole of the first capacitor C1 and an electrode 812 serving as the second pole of the first capacitor C1.
  • the electrode 811 is configured to receive the third power supply voltage AVSS; the electrode 812 is electrically connected to the electrode 840 in the fifth metal layer metal5 through the second via hole V2, thereby achieving electrical connection with the control electrode 143 of the driving transistor 140.
  • the electrode 811 includes a plurality of strip electrodes
  • the electrode 812 includes a plurality of strip electrodes
  • the plurality of strip electrodes of the electrode 811 and the plurality of strip electrodes of the electrode 812 are alternately arranged, and the electrodes 811 and 812 and the plurality of strip electrodes between them are arranged alternately.
  • the spacer portion forms the first capacitor C1.
  • the first capacitor C1 is a part of the storage capacitor CST.
  • the first capacitor C1 and the second capacitor C2 below are connected in parallel to form the storage capacitor CST.
  • FIG. 23B shows the electrode 820 located in the fourth metal layer metal4.
  • the electrode 820 is a planar electrode, and the electrode 820 serves as the first pole of the second capacitor C2.
  • FIG. 23C shows the electrode 830 located in the auxiliary metal layer metal4'.
  • the electrode 830 is a planar electrode, and the electrode 830 serves as the second pole of the second capacitor C2.
  • FIG. 23D shows the electrode 840 located in the fifth metal layer metal5, as well as the first via hole V1 and the second via hole V2.
  • Figure 23E shows a schematic cross-sectional view of the partial structure of the storage capacitor CST.
  • the electrode 840 located in the fifth metal layer metal5 is electrically connected to the electrode 830 located in the auxiliary metal layer metal4' through the first via V1;
  • the electrode 840 located in the fifth metal layer metal5 is electrically connected to the electrode 812 located in the third metal layer metal3 through the second via hole V2. It should be noted that the second via V2 will penetrate the fourth metal layer metal4, which is not shown in Figure 23E.
  • the electrode 820 located on the fourth metal layer metal4 and the electrode 830 located on the auxiliary metal layer metal4' and the space between them form a second capacitor C2; for example, the first capacitor C1 and the above-mentioned first capacitor C1
  • the second capacitor C2 is connected in parallel to form the storage capacitor CST.
  • an auxiliary metal layer metal4' is provided between the fourth metal layer metal4 and the fifth metal layer metal5, so that the gap between the fourth metal layer metal4 and the auxiliary metal layer metal4' can be The distance between them is, for example, about 1/10 of the distance between the fourth metal layer metal4 and the fifth metal layer metal5, so that the capacitance value per unit area of the second capacitor C2 can be effectively increased.
  • embodiments of the present disclosure also provide a display substrate 500 , including a substrate and at least one driving circuit formed on the substrate.
  • the driving circuit includes a driving transistor 140, a first transistor 110, a second transistor 120 and a third transistor 130.
  • the driving transistor 140 includes a control electrode 143, a first electrode 141 and a second electrode 142, and is configured to control the voltage flowing through the first electrode 141 and the driving transistor 140 according to the voltage of the control electrode 143 of the driving transistor 140.
  • the driving current of the second pole 142 is used to drive the light emitting element LE to emit light.
  • the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1.
  • the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.
  • the third transistor 130 is connected to the first pole 141 of the driving transistor 140 and is configured to apply the first power supply voltage ELVDD to the first pole 141 of the driving transistor 140 in response to the light emission control signal EN.
  • the display substrate 500 further includes a first scan signal line SL1 for transmitting the first scan signal SCAN1 and a second scan signal line SL2 for transmitting the second scan signal SCAN2, and a first power supply for transmitting the first power supply voltage ELVDD.
  • the voltage line VL1 and the light-emitting control line EL used to transmit the light-emitting control signal EN; the first scanning signal line SL1, the second scanning signal line SL2, the first power supply voltage line VL1 and the light-emitting control line EL are on the front projection edge of the substrate and The vertical directions of the fourth direction D4 are arranged in sequence.
  • the direction along the first pole 111 of the first transistor 110 to the second pole 112 of the first transistor 110 is the first direction D1
  • the direction along the first pole 121 of the second transistor 120 to the second pole 122 of the second transistor 120 is the first direction D1.
  • the direction is the second direction D2
  • the direction along the first pole 131 of the third transistor 130 to the second pole 132 of the third transistor 130 is the third direction D3
  • the direction along the first pole 141 of the driving transistor 140 to the driving transistor 140 is the third direction D3.
  • the direction of the second pole 142 is the fourth direction D4, and the first direction D1, the second direction D2, and the third direction D3 all intersect the fourth direction D4.
  • the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4.
  • the display substrate provided by at least one embodiment of the present disclosure can achieve a sub-pixel area of 5.45um ⁇ 13.6um through optimized layout and wiring design processing in the design, achieving high resolution (PPI) and optimization of the pixel circuit array. arrangement and have better display effect.
  • PPI high resolution
  • FIG. 24A is a block diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 10 includes a plurality of sub-pixels 100 distributed in an array, a plurality of scan lines 11 and a plurality of data lines 12 .
  • Each sub-pixel 100 includes a light-emitting element and a pixel circuit that drives the light-emitting element.
  • the plurality of scan lines 11 and the plurality of data lines 12 intersect with each other to define a plurality of pixel areas distributed in an array in the display area, and a pixel circuit of a sub-pixel 100 is provided in each pixel area.
  • the pixel circuit is, for example, a conventional pixel circuit, such as a 2T1C (ie, two transistors and a capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C, etc. nTmC (n, m are positive integers) pixel circuit, and in different embodiments,
  • the pixel circuit may further include a compensation sub-circuit, which may include an internal compensation sub-circuit or an external compensation sub-circuit.
  • the compensation sub-circuit may include a transistor, a capacitor, etc.
  • the pixel circuit may further include a reset circuit, a light emission control sub-circuit, a detection circuit, etc.
  • the display substrate may further include a gate driving subcircuit 13 and a data driving subcircuit 14 located in the non-display area.
  • the gate driving sub-circuit 13 is connected to the pixel circuit through the scanning line 11 to provide various scanning signals
  • the data driving sub-circuit 14 is connected to the pixel circuit through the data line 12 to provide data signals.
  • the positional relationship between the gate driving subcircuit 13 and the data driving subcircuit 14, the scanning line 11 and the data line 12 shown in FIG. 24A in the display substrate is just an example, and the actual arrangement position can be designed as needed.
  • the display substrate 10 may further include a control circuit (not shown).
  • the control circuit is configured to control the data driving subcircuit 14 to apply the data signal, and to control the gate driving subcircuit 14 to apply the scanning signal.
  • An example of such a control circuit is a timing control circuit (T-con).
  • the control circuit can be in various forms, for example, including a processor and a memory.
  • the memory includes executable code, and the processor runs the executable code to perform the above detection method.
  • the processor may be a central processing unit (CPU) or other form of processing device with data processing capabilities and/or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.
  • CPU central processing unit
  • PLC programmable logic controller
  • a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include, for example, random access memory (RAM) and/or cache memory (cache), etc.
  • Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.
  • One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the functions contemplated by the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium.
  • the pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a storage sub-circuit as needed, and may also include a light-emitting control sub-circuit, a reset circuit, etc. as needed.
  • Figure 24B shows a schematic diagram of a pixel circuit.
  • the pixel circuit includes a data writing sub-circuit 111 , a driving sub-circuit 112 and a storage sub-circuit 113 .
  • the data writing sub-circuit 111 is electrically connected to the first terminal of the storage sub-circuit 113 and is configured to transmit the data signal Vd to the first terminal of the storage sub-circuit 113 in response to the control signal (first control signal SEL).
  • the second terminal of the storage sub-circuit 113 is configured to receive the second power supply voltage VSS, for example.
  • the driving sub-circuit 112 includes a control electrode 150, a first electrode 151 and a second electrode 152.
  • the control electrode 150 of the driving sub-circuit is electrically connected to the first end of the memory sub-circuit.
  • the first electrode 151 of the driving sub-circuit 112 is configured to receive the first terminal of the memory sub-circuit.
  • a power supply voltage VDD, the second electrode 152 of the driving sub-circuit 112 is electrically connected to the first node S, and connected to the first electrode 121 of the light-emitting element 120.
  • the driving sub-circuit 112 is configured to drive the light-emitting element 120 to emit light in response to the voltage at the first end of the storage sub-circuit.
  • the second electrode 122 of the light-emitting element 120 is configured to receive the first common voltage Vcom1, for example.
  • the pixel circuit also includes a bias subcircuit 114.
  • the bias sub-circuit 114 includes a control terminal, a first terminal and a second terminal.
  • the control terminal of the bias sub-circuit 114 is configured to receive a bias signal; the first terminal of the bias sub-circuit 114 is configured to receive a second terminal, for example.
  • the power supply voltage VSS, the second terminal of the bias sub-circuit 114 is electrically connected to the first node S.
  • the bias signal is the second common voltage Vcom2.
  • the bias signal Vcom2 is a constant voltage signal, such as 0.8V-1V; the bias subcircuit 114 is in a normally open state under the action of the bias signal, and is configured to provide a constant current, so that it is applied to the light-emitting element
  • the voltage of 120 has a linear relationship with the data signal, which helps to achieve fine control of gray scale, thus improving the display effect. This will be further explained later in conjunction with specific circuits.
  • the gray-scale voltage written into the first electrode 121 of the light-emitting element 120 needs to change rapidly.
  • the bias subcircuit 114 can also allow the first electrode 121 of the light-emitting element 120 to change Charge is released quickly, resulting in better dynamic contrast.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • metal-oxide semiconductor field effect transistors are used as examples for explanation.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no structural difference between the source and drain.
  • one of the poles is directly described as the first pole and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages) voltage).
  • the display substrate provided by the embodiments of the present disclosure can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethylmethacrylate (PMMA), triacetylcellulose (TAC), cyclic olefin polymer (COP) and cyclic olefins Copolymer (COC), etc.
  • the embodiments of the present disclosure take a silicon substrate as an example for description, that is, the pixel structure is prepared on the silicon substrate. However, the embodiments of the present disclosure are not limited to this.
  • the pixel circuit includes a complementary metal oxide semiconductor circuit (CMOS circuit), that is, the pixel circuit is prepared on a single crystal silicon substrate. Relying on mature CMOS integrated circuit technology, silicon-based processes can achieve higher precision (for example, PPI can reach 6,500 or even more than 10,000).
  • CMOS circuit complementary metal oxide semiconductor circuit
  • the display substrate causes the first electrode 121 and the second electrode 122 of the light-emitting element 120 in the sub-pixel to be short-circuited due to process fluctuations, resulting in the voltage of the first electrode 121 of the light-emitting element 120 being too high (for example, the first common voltage Vcom1 is High potential) or too low (for example, the first common voltage Vcom1 is low potential), thus causing a latch-up effect at the first node S, causing the CMOS circuit to fail, resulting in defects such as dark lines on the display substrate.
  • the data writing sub-circuit includes a first data writing transistor P1, and the driving sub-circuit includes a driving transistor N2;
  • the first data writing transistor is a P-type metal-oxide semiconductor field effect transistor (PMOS)
  • the driving transistor N2 is an N-type metal-oxide semiconductor field effect transistor (NMOS)
  • the gate electrode, the first electrode, and the second electrode of the driving transistor N2 serve as the control electrode 150 and the first electrode of the driving subcircuit 112 respectively.
  • electrode 151 and second electrode 152 are examples of the driving transistor N2;
  • the first common voltage Vcom1 provided to the second electrode 122 of the light-emitting element 120 is at a low potential, and a short circuit occurs between the first electrode 121 and the second electrode 122 of the light-emitting element 120, it will cause the first common voltage Vcom1 to be connected to the second electrode 122 of the light-emitting element 120.
  • the potential of the second electrode of the driving transistor to which the electrode 121 is directly connected is too low.
  • FIG. 24C shows a schematic diagram of the latch-up effect formed by the pixel circuit.
  • the active area (such as the first electrode) forms two parasitic transistors Q1 and Q2 connected to each other, forming an N-P-N-P structure.
  • the PN junction ( The emitter junction) is forward biased and Q1 is turned on, which will provide a large enough current to turn on the parasitic transistor Q2, which in turn feeds back the current to the parasitic transistor Q1, forming a vicious cycle.
  • most of the current flows from VDD directly through the parasitic transistor to VSS is not controlled by the transistor gate voltage, causing the CMOS pixel circuit to fail; and the latch-up effect will cause the parasitic transistor Q2 to continuously draw current from the emitter, that is, from the data line, resulting in a circuit connected to the data line.
  • the failure of column sub-pixels causes defects such as dark lines on the display substrate, which greatly affects the display effect.
  • At least one sub-pixel further includes a resistor, the resistor is connected between the second electrode 152 of the driving sub-circuit 112 and the first electrode 121 of the light-emitting element 120, which can play a role in increasing the voltage.
  • the effect of raising or lowering the potential of the first node S can alleviate or avoid the latch-up effect, improve the reliability of the circuit, and improve the display effect.
  • FIG. 25A is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • the pixel circuit also includes a resistor 130 , the first end 131 of the resistor 130 is electrically connected to the second electrode 152 of the driving sub-circuit 112 , and the second end 132 is electrically connected to the first electrode 121 of the light-emitting element 120 .
  • the connection, that is, the second electrode 152 of the driving sub-circuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 through the resistor 130 .
  • the resistor 130 is a constant resistance or a variable resistance, or may be an equivalent resistance formed by other devices (such as transistors).
  • the resistor 130 is insulated from the control electrode 150 of the driving subcircuit 112 and is arranged in the same layer, and the resistivity of the resistor is higher than the resistivity of the control electrode of the driving subcircuit.
  • the resistor has a resistivity that is more than ten times the resistivity of the control electrode.
  • the “same layer arrangement” referred to in this disclosure refers to structures formed by two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Their materials Can be the same or different. For example, the precursor materials used to form multiple structures arranged in the same layer are the same, and the final materials formed may be the same or different.
  • the "integrated structure” in this disclosure refers to two (or more than two) structures formed through the same deposition process and patterned through the same patterning process to form connected structures. Their materials can be the same or different. .
  • the driving subcircuit control electrode and the resistor can be formed in the same patterning process, thereby saving process.
  • the materials of the resistor and the control electrode of the driving subcircuit are both polysilicon materials, and the doping concentration of the resistor is lower than that of the control electrode, so the resistor has a higher resistivity than the control electrode.
  • the resistor may be intrinsic polysilicon or lightly doped polysilicon, and the control electrode may be heavily doped polysilicon.
  • control electrode and resistor materials may be different.
  • the materials of the control electrode and the resistor may respectively include a metal and a metal oxide corresponding to the metal.
  • the metal may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials composed of combinations of the above metals.
  • the data writing sub-circuit 111 may include a transmission gate circuit composed of two complementary transistors connected in parallel with each other; the control signal includes two inverted control signals.
  • the data writing sub-circuit 111 adopts a circuit with a transmission gate structure, which can help transmit the data signal to the first end of the storage sub-circuit 113 without loss.
  • the data writing sub-circuit includes a first control electrode, a second control electrode, a first terminal and a second terminal, and the first control electrode and the second control electrode of the data writing sub-circuit are respectively configured to receive the first control signal and the second control signal, the first end of the data writing subcircuit is configured to receive the data signal, the second end of the data writing subcircuit is electrically connected to the first end of the storage subcircuit, and is configured to respond to the first control signal signal and the second control signal transmit the data signal to the first end of the memory sub-circuit.
  • the first node S does not necessarily represent an actual component, but represents a convergence point of relevant circuit connections in the circuit diagram.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the symbol SEL can represent both the control signal and the control signal terminal.
  • the symbols Vcom1 and Vcom2 can represent both the first common voltage and the second common voltage, or the first common voltage terminal and the second common voltage terminal;
  • the symbol VDD can represent both the first voltage terminal and the first power supply voltage.
  • VSS can represent both the second voltage terminal and the second power supply voltage.
  • FIG. 25B shows a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 24A.
  • the data writing sub-circuit 111 includes a first data writing transistor P1 and a second data writing transistor N1 connected in parallel with each other.
  • the first data writing transistor P1 and the second data writing transistor N1 are respectively a P-type metal-oxide semiconductor field-effect transistor (PMOS) and an N-type metal-oxide semiconductor field-effect transistor (NMOS).
  • the control signal includes a first control signal SEL and a second control signal SEL_B that are inverse to each other.
  • the gate of the first data writing transistor P1 serves as the first control electrode of the data writing sub-circuit and is configured to receive the The first control signal SEL
  • the gate of the second data writing transistor N1 serves as the second control electrode of the data writing sub-circuit, and is configured to receive the second control signal SEL_B.
  • the first pole of the second data writing transistor N1 and the first pole of the first data writing transistor P1 are electrically connected as the first end of the data writing sub-circuit and are configured to receive the data signal Vd; the second data writing transistor P1
  • the second pole of the input transistor N1 is electrically connected to the second pole of the first data writing transistor P1 as the second end of the data writing sub-circuit, and is electrically connected to the control electrode 150 of the driving sub-circuit 112 .
  • the first data writing transistor P1 and the second data writing transistor N1 have the same size and the same channel width to length ratio.
  • the data writing sub-circuit 111 takes advantage of the complementary electrical characteristics of the transistor, and has a low on-state resistance regardless of whether it transmits a high level or a low level, thereby having the advantage of electrical signal transmission integrity, and can transmit the data signal Vd without is transmitted to the first end of the storage sub-circuit 113 with loss.
  • the driving subcircuit 112 includes a driving transistor N2.
  • the driving transistor N2 is an NMOS.
  • the gate electrode, the first electrode and the second electrode of the driving transistor N2 serve as the control electrode, the first electrode and the second electrode of the driving sub-circuit 112 respectively.
  • the storage sub-circuit 113 includes a storage capacitor Cst.
  • the storage capacitor Cst includes a first capacitor electrode 141 and a second capacitor electrode 142 .
  • the first capacitor electrode 141 and the second capacitor electrode 142 serve as the third capacitor of the storage sub-circuit 113 respectively. one end and the second end.
  • the resistor 130 includes a resistor R.
  • a PN junction is formed between the second electrode 152 of the driving subcircuit 112 and the base substrate, and the resistance value of the resistor 130 is configured such that when the driving transistor N2 operates in the saturation region, that is, the pixel circuit operates to drive the light emitting element 120 When emitting light, the PN junction is turned off. In this case, even if a short circuit occurs between the two electrodes of the light-emitting element 120, due to the voltage drop on the resistor 130, the potential of the second electrode 152 can be protected, thereby avoiding the latch-up effect.
  • the light-emitting element 120 is implemented as an organic light-emitting diode (OLED).
  • the light-emitting element 120 may be an OLED with a top-emitting structure, and may emit red light, green light, blue light, or white light, etc.
  • the light-emitting element 120 is a micro OLED (Micro OLED).
  • the embodiments of the present disclosure do not limit the specific structure of the light-emitting element.
  • the first electrode 121 of the light-emitting element 120 is the anode of the OLED
  • the second electrode 122 is the cathode of the OLED, that is, the pixel circuit has a common cathode structure.
  • the embodiments of the present disclosure do not limit this. According to changes in the circuit structure, the pixel circuit may also have a common anode structure.
  • the bias sub-circuit 114 includes a bias transistor N3, and the gate electrode, the first electrode and the second electrode of the bias transistor N3 serve as the control terminal, the first terminal and the second terminal of the bias sub-circuit 114 respectively.
  • FIG. 25C shows a signal timing diagram of the pixel circuit shown in FIG. 25B.
  • the working principle of the pixel circuit shown in FIG. 25C will be described below in conjunction with the signal timing diagram shown in FIG. 25B.
  • the second data writing transistor, the driving transistor, and the bias transistor are all N-type transistors
  • the first data writing transistor is a P-type transistor.
  • the embodiment of the present disclosure does not limit this.
  • FIG. 25C shows the waveform diagram of each signal in two consecutive display periods T1 and T2.
  • the data signal Vd is a high gray-scale voltage in the display period T1 and a low gray-scale voltage in the display period T2.
  • the display process of each frame image includes a data writing stage 1 and a lighting stage 2.
  • a working process of the pixel circuit includes: in the data writing phase 1, the first control signal SEL and the second control signal SEL_B are both turn-on signals, and the first data writing transistor P1 and the second data writing transistor N1 are turned on.
  • the data signal Vd is transmitted to the gate of the driving transistor N2 through the first data writing transistor P1 and the second data writing transistor N1; in the light-emitting phase 2, the first control signal SEL and the second control signal SEL_B are both off signals, Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the driving transistor N2 operates in a saturated state with a constant current, and drives the light-emitting element 120 to emit light.
  • the data signal Vd changes from a high gray-scale voltage to a low gray-scale voltage, and the bias transistor N3 generates a stable drain current under the control of the second common voltage Vcom2.
  • the polar current can quickly discharge the charge stored in the OLED anode when the OLED display gray scale needs to change rapidly. For example, the discharge process occurs when the data is written to 1 in the display period T2. Therefore, during the light-emitting phase 2 of the display period T2, the voltage of the OLED anode decreases rapidly, thereby achieving better dynamic contrast and improving the display effect.
  • the voltage V0 is directly loaded on the first electrode 121 of the light-emitting element 120, such as the anode voltage of the OLED; when the first node S is connected to the light-emitting element 120 through the resistor 130.
  • the light-emitting element 120 is electrically connected.
  • the voltage of the first node S can be approximately equal to the voltage of the first electrode 121 of the light-emitting element 120; that is, the first electrode of the light-emitting element 120
  • the voltage of the electrode 121 has a linear relationship with the data signal (data voltage) Vd, thereby enabling fine control of the gray scale and improving the display effect.
  • the first control signal SEL and the second control signal SEL_B are differential complementary signals, with the same amplitude and opposite phases. This helps improve the anti-interference performance of the circuit.
  • the first control signal SEL and the second control signal SEL_B can be output by the same gate driving circuit unit (such as a GOA unit), thereby simplifying the circuit.
  • the display substrate 10 may further include a data driving circuit 13 and a scan driving circuit 14 .
  • the data driving circuit 13 is configured to emit a data signal, such as the above-mentioned data signal Vd, as needed (such as an image signal input to the display device).
  • the scan driving circuit 14 is configured to output various scanning signals, including, for example, the above-mentioned first control signal SEL and second control signal SEL_B, which is, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly prepared on the display substrate. ).
  • the display substrate uses a silicon substrate as the base substrate 101, and the pixel circuit, data driving circuit 13 and scan driving circuit 14 can all be integrated on the silicon substrate.
  • the data driving circuit 13 and the scanning driving circuit 14 can also be formed in the area corresponding to the display area of the display substrate, and not necessarily located in the non-display area. district.
  • the display substrate 10 further includes a control circuit (not shown).
  • the control circuit is configured to control the data driving circuit 13 to apply the data signal Vd, and to control the gate driving circuit 13 to apply various scanning signals.
  • An example of such a control circuit is a timing control circuit (T-con).
  • the control circuit can be in various forms, for example, including a processor and a memory.
  • the memory includes executable code, and the processor runs the executable code to perform the above detection method.
  • the processor may be a central processing unit (CPU) or other form of processing device with data processing capabilities and/or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.
  • CPU central processing unit
  • PLC programmable logic controller
  • a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include, for example, random access memory (RAM) and/or cache memory (cache), etc.
  • Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.
  • One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 121 may execute the functions desired by the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium, such as the electrical characteristic parameters obtained in the above detection method.
  • the following uses the pixel circuit shown in FIG. 25B as an example to illustrate the display substrate provided by at least one embodiment of the present disclosure.
  • the embodiment of the present disclosure is not limited thereto.
  • FIG. 26A is a schematic diagram of a display substrate 10 provided by at least one embodiment of the present disclosure.
  • the display substrate 10 includes a base substrate 101, and a plurality of sub-pixels 100 are located on the base substrate 101.
  • the plurality of sub-pixels 100 are arranged as a sub-pixel array.
  • the row direction of the sub-pixel array is a first direction D1 and the column direction is a second direction D2.
  • the first direction D1 and the second direction D2 intersect, for example, are orthogonal.
  • FIG. 26A exemplarily shows two rows and six columns of sub-pixels, that is, two pixel rows 20 and six pixel columns 30 , and areas of three pixel columns spaced apart from each other are respectively shown with dotted lines.
  • the base substrate 101 can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC). ), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET ), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethylmethacrylate (PMMA), triacetylcellulose (TAC), cyclic olefin polymer (COP) and cyclic olefin copolymer (COC) etc.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • PET polyacrylate
  • polyarylate polyetherimide
  • polyethersulfone polyethylene terephthalate
  • PET polyethylene
  • PE polypropylene
  • PSF polys
  • the base substrate 101 includes single crystal silicon or high-purity silicon.
  • the pixel circuit is formed on the base substrate 10 through a CMOS semiconductor process.
  • the active region of the transistor (including the channel region, first electrode and second electrode of the transistor) is formed in the base substrate 101 through a doping process, and
  • Each insulating layer is formed through a silicon oxidation process or a chemical vapor deposition process (CVD), and a plurality of conductive layers are formed through a sputtering process to form a wiring structure.
  • the active area of each transistor is located inside the base substrate 101 .
  • Figure 26B shows a cross-sectional view along section line I-I' of Figure 26A. For the sake of clarity, some traces or electrode structures that are not directly connected are omitted in FIG. 26B.
  • the display substrate 10 includes a base substrate 101 , a first insulating layer 201 , a polysilicon layer 102 , a second insulating layer 202 , a first conductive layer 301 , and a third insulating layer located on the base substrate 101 in sequence. Insulating layer 203, second conductive layer 302, fourth insulating layer 204, third conductive layer 303, fifth insulating layer 205 and fourth conductive layer 304.
  • the structure in the display substrate 10 will be described hierarchically below, and FIG. 26B will be used as a reference and will be explained together.
  • FIG. 27A shows the part of the display substrate 10 located below the first conductive layer 301, that is, the base substrate 101 and the first insulating layer 201 and polysilicon layer 102 thereon, including each transistor ( P1, N1-N3), storage capacitor Cst and resistor 130;
  • Figure 27B shows an enlarged schematic diagram of a sub-pixel 100 in Figure 27A; for the sake of clarity, the section line I in Figure 26A is also shown in Figure 27A.
  • -I'. 28A-28E illustrate the formation process of the substrate structure shown in FIG. 27A.
  • the first data writing transistor P1 and the driving transistor N2 are located on opposite sides of the storage capacitor Cst, for example, in the second direction D2 are located on opposite sides of the storage capacitor Cst.
  • this arrangement helps to increase the distance between the first data writing transistor P1 and the driving transistor N2 , thereby increasing the resistance of the parasitic circuit and further reducing the risk of the latch-up effect of the CMOS circuit.
  • the material of the second capacitor electrode 142 of the storage capacitor 140 is a conductor or a semiconductor.
  • the second capacitor electrode 142 of the storage capacitor 140 is the first region 401 of the base substrate 101; for example, the base substrate 101 is a P-type silicon-based substrate, and the second capacitor The material of the electrode 142 is P-type single crystal silicon.
  • the semiconductor first region 401 located under the first capacitor electrode 141 in the substrate 101 forms an inversion region and becomes a conductor, thereby connecting with the first region 401 on both sides of the first region 401 .
  • Contact hole areas (contact hole areas 145a, 145b shown in Figure 4B) form electrical connections. In this case, no additional doping or other processing is performed on the first region 401 .
  • the first region 401 is, for example, a conductive region in the base substrate 101 , such as a heavily doped region, so that the second capacitor electrode 142 can obtain a stable and high conductivity.
  • the base substrate 101 further includes a second region 402 , and the second region 402 is an N-type well region in the base substrate 101 .
  • the first data writing transistor P1 and the resistor 130 are disposed side by side in the second region 402 in the second direction D2. Disposing the resistor 130 made of polysilicon material in the N-type substrate helps to reduce parasitic effects and improve circuit characteristics.
  • the resistor (R) 130 and the first data writing transistor P1 are located on the same side of the second capacitor electrode 142.
  • the driving transistor N2 and the bias transistor N3 are located on the same side of the second capacitor electrode 142 .
  • the first data writing transistor P1 and the second data writing transistor P1 are arranged side by side in the first direction D1 and are symmetrical about the symmetry axis along the second direction D2.
  • the gate electrode 160 of the first data writing transistor P1 and the gate electrode 170 of the second data writing transistor N1 are arranged side by side in the first direction D1 and are symmetrical about the symmetry axis along the second direction D2.
  • the resistor 130 has a U-shaped structure, such as an asymmetric U-shaped structure, and for example, the two branches of the U-shaped structure have different lengths.
  • the second end 132 of the resistor 130 is closer to the drive transistor N2.
  • a U-shaped resistor structure helps to save the layout area occupied by the resistor, thereby improving the space utilization of the layout and helping to improve the resolution of the display substrate. For example, in the same space, a U-shaped resistor structure can increase the length of the resistor to obtain the desired resistance value.
  • the resistor 130 is designed as an asymmetric structure to rationally utilize the layout space.
  • a contact hole area 411a is designed above the shorter branch of the U-shaped resistor.
  • the contact hole area 411a is The first direction D1 is parallel to the second end 132 of the resistor 130 .
  • the contact hole region 411a is an N-type heavily doped region (N+).
  • the contact hole region 411 is used to bias the well region 401 where the first data writing transistor P1 is located, thereby avoiding threshold voltage changes caused by latch-up effects and substrate bias effects, and improving circuit stability.
  • N+ N-type heavily doped region
  • the parasitic PN junction between the two can be reverse-biased, electrically isolating the device and reducing the energy consumption of the device. Parasitic effects between devices improve the stability of the circuit.
  • the opening of the U-shaped structure faces the first capacitor electrode 141, and the first end 131 and the second end 132 of the resistor 130 are respectively located at two ends of the U-shaped structure.
  • the first end 131 of the resistor 130 is provided with a contact hole area 133 for electrical connection with the gate 150 of the driving transistor N2; the second end 132 of the resistor 130 is provided with a contact hole area 134 for electrical connection. is electrically connected to the first electrode 121 of the light emitting element 120 .
  • the material of the resistor 130 includes polysilicon material, and the contact hole regions 133 and 134 are doped regions for reducing contact resistance; the main body region of the resistor 130 except the contact hole region is, for example, an intrinsic region or a low Doped regions to obtain the desired resistance value.
  • the first capacitor electrode 141 of the storage capacitor 140 and the resistor 130 are insulated in the same layer, and both include polysilicon materials; the doping concentration of the first capacitor electrode 141 of the storage capacitor 140 is higher than that of the main body region of the resistor 130 concentration.
  • the body region of the resistor 130 is made of intrinsic polysilicon material.
  • the gate electrodes 160, 170, 150, and 180 of each transistor P1 and N1-N3 are arranged in the same layer as the first capacitor electrode 141 of the storage capacitor 140, and both include polysilicon material.
  • the gate electrode 150 of the driving transistor N2 and the first capacitor electrode 141 are connected to each other to form an integrated structure.
  • FIG. 27B also shows the active regions P1a, N1a, N2a and N3a of each transistor P1, N1-N3 respectively, and shows the first pole 161 and the second pole 162 of the first data writing transistor P1.
  • FIG. 27B also shows the gate contact region 165, the first contact region 163 and the second pole contact region 164 of the first data writing transistor P1, and the gate contact region 175, the second pole contact region 175 of the second data writing transistor N1.
  • Area 183 and second pole contact area 184 Area 183 and second pole contact area 184.
  • each first electrode contact region is a region used to form electrical contact with the corresponding first electrode
  • each second electrode contact region is a region used to form electrical contact with the corresponding second electrode contact region
  • each gate electrode contact region Regions are areas where corresponding gate electrodes are used to form electrical contacts.
  • the active area P1a of the first data writing transistor P1 and the active area N1a of the second data writing transistor N1 are arranged side by side in the first direction D1 and are symmetrical about the symmetry axis along the second direction D2.
  • the area of the active region N2a of the driving transistor N2 is larger than the area of the active regions of other transistors, and a larger width-to-length ratio can be obtained, which helps to improve the driving capability of the driving transistor N2, thus Improve display effect.
  • FIG. 27B Also shown in FIG. 27B are the contact hole regions 144 on the first capacitor electrode 141 and the contact hole regions 145a and 145b configured to be electrically connected to the second capacitor electrode 142 . As shown in FIG. 27B , at least two contact hole areas are respectively provided on the first capacitor electrode 141 and the second capacitor electrode 142 to reduce contact resistance.
  • the distribution of transistors for example, including the shape, size, etc. of each transistor
  • storage capacitors for example, including the shape, size, etc. of each transistor
  • resistors in two adjacent sub-pixels 100 in the first direction D1 is symmetrical about the symmetry axis along the second direction D2, That is, the corresponding structures in the two sub-pixels are respectively symmetrical about the symmetry axis along the second direction D2.
  • the distribution of transistors in two adjacent sub-pixels 100 in the second direction D2 is axially symmetrical with respect to the first direction.
  • This symmetrical arrangement can maximize the uniformity of process errors, thereby improving the uniformity of the display substrate.
  • this symmetrical arrangement allows some structures in the substrate that are arranged on the same layer and can be connected to each other to be formed integrally. Compared with being arranged separately, the pixel layout can be made more compact, improve space utilization, and thus improve the resolution of the display substrate. .
  • the second areas 402 of two adjacent sub-pixels 100 in the first direction D1 have an integrated structure
  • the second areas 402 of the two adjacent sub-pixels 100 in the second direction D2 have an integrated structure.
  • the first data writing transistor N1 and the resistor 130 in the four adjacent sub-pixels 100 are located in the same well region. Compared with setting up independent well regions respectively, this arrangement can make the arrangement of pixels more compact while meeting the design rules, which helps to improve the resolution of the display substrate.
  • the active areas P1a of the first data writing transistors P1 of two adjacent sub-pixels in the second direction D2 are connected to each other into an integrated structure, that is, the two first data writing transistors P1 a
  • the active region P1a of the transistor P1 is located in the same doping region A1 (P well) of the same second region 402, and the first poles of the two first data transistors P1 are connected to each other in an integrated structure to receive the same data signal. Vd.
  • the active areas N1a of the second data writing transistors N1 of two adjacent sub-pixels in the second direction D2 are connected to each other into an integrated structure, that is, the two second data writing transistors N1 a
  • the active region N1a of the transistor N1 is located in the same doped region A2 (N well) of the base substrate 101, and the first poles of the two second data writing transistors N1 are connected to each other in an integrated structure to receive the same data.
  • Signal Vd Signal
  • the gates of the first data writing transistor P1 or the gates of the second data writing transistor N2 of two sub-pixels 100 adjacent in the first direction D1 are connected to each other to form an integrated structure.
  • the gates of the first data writing transistor P1 are configured to receive the same first control signal SEL, and the gates of the second data writing transistor N1 are configured to receive the same second control signal SEL_B.
  • the first writing transistor P1 of the two sub-pixels is adjacent to the second writing transistor N1 in the first direction D1 alternately. situation. Therefore, the gates of two adjacent first data writing transistors P1 can be directly connected into an integrated structure to form the first control electrode group 191 , and the gates of adjacent second data writing transistors N1 can be directly connected into an integrated structure. structure to form the second control electrode group 192. This arrangement can make the arrangement of pixels more compact while meeting the design rules, helping to improve the resolution of the display substrate.
  • the active regions N2a of the two driving transistors N2 are connected to each other to form an integrated structure, that is, The active regions N2a of the two driving transistors N2 are located in the same doped region B (N well) of the base substrate 101, and the first poles of the two driving transistors N2 are connected to each other to form an integrated structure, forming a third control
  • the electrode group 193 is to receive the same first power supply voltage VDD; when their bias transistors N3 are adjacent, the gates of the two bias transistors N3 are connected to each other in an integrated structure to receive the same second common voltage Vcom2;
  • the active regions N3a of the two bias transistors N3 are connected to each other to form an integrated structure, that is, the active regions N3a of the two bias transistors N3 are located in the same doping region C (N well) of the base substrate 101, and
  • This arrangement can make the arrangement of pixels more compact while meeting the design rules, helping to improve the resolution of the display substrate.
  • 28A-28D illustrate the formation process of the substrate structure shown in FIG. 27A. For the sake of clarity, only two rows and two columns of sub-pixels, that is, four adjacent sub-pixels 100, are shown in the figure.
  • the formation process of the display substrate provided by the embodiment of the present disclosure is exemplified below with reference to FIGS. 28A-28D , but this is not a limitation of the present disclosure.
  • a silicon-based substrate is provided, and its material is, for example, P-type single crystal silicon.
  • N-type transistors (such as drive transistors) can be fabricated directly on the P-type silicon substrate, that is, the P-type substrate serves as the channel region of the N-type transistor, which is beneficial to taking advantage of the high speed of NMOS devices and improving circuit performance. .
  • N-type doping is performed on the P-type silicon substrate to form an N-type well region, that is, the second region 402, as a substrate for the first data writing transistor P1 and the resistor 130. end.
  • the second areas 402 of two sub-pixels adjacent in the first direction D1 may be connected to each other, and the second areas 402 of two sub-pixels adjacent in the second direction D2 may be connected to each other.
  • the undoped area on the base substrate 101 is shielded.
  • a first insulating layer 201 is formed on the base substrate 101 , and then a polysilicon layer 102 is formed on the first insulating layer 201 .
  • the first insulating layer 201 includes the gate insulating layer of each transistor and also includes the dielectric layer 104 of the storage capacitor Cst.
  • the polysilicon layer 102 includes a first capacitor electrode 141, a resistor 130, and gate electrodes 150, 160, 170, and 180 of each transistor (P1, N1-N3).
  • the gate of the first data writing transistor P1 is located in the second region 402, and the N-type well region serves as the channel region of the P-type transistor.
  • the resistor 130 is also located in the second region 402. Forming the resistor 130 of polysilicon material in the N-type substrate helps reduce parasitic effects and improve circuit characteristics. Each N-type transistor is formed directly on the P-type substrate.
  • the pattern of the polysilicon layer in the two sub-pixels adjacent in the first direction D1 is symmetrical about the symmetry axis along the second direction D2; the polysilicon layer in the two sub-pixels adjacent in the second direction D2 is symmetrical.
  • the pattern of layers is symmetrical about an axis of symmetry along the first direction D1.
  • the gates of the first data writing transistor P1 and the second data writing transistor N1 of two sub-pixels adjacent in the first direction D1 may be integrally formed respectively.
  • the first insulating layer is formed on the base substrate by a thermal oxidation method.
  • the material of the first insulating layer is silicon nitride, oxide or oxynitride.
  • a polysilicon material layer is formed on the first insulating layer through a chemical vapor deposition process (PVD), and then a photolithography process is performed on the polysilicon material layer to form the polysilicon layer 102 .
  • PVD chemical vapor deposition process
  • FIG. 28C shows the doped window region 103 of the base substrate (left image) and the doped window region 103 on the substrate structure shown in FIG. 28B (right image).
  • the doping is heavy doping to form a contact hole region for electrical connection on the base substrate.
  • the doped window region includes the source and drain regions of each transistor.
  • the doped window area also includes each contact hole area of the substrate and the contact hole area of the resistor 130, such as the contact hole areas 400a, 400b, 411a, 411b, 145a, 145b, 133, 134 shown in FIG. 27B .
  • the gate of a transistor is formed of polysilicon material, the polysilicon gate also needs to be doped.
  • a barrier layer needs to be formed to block the non-doped area and only expose the corresponding doped window area and amorphous silicon area.
  • Figure 28C only illustrates each doping window area.
  • a corresponding barrier layer/mask layer can be set up to expose the corresponding doping window area and polysilicon area for doping.
  • the material of the barrier layer/mask layer may be photoresist or oxide material.
  • a barrier layer 135 is formed corresponding to the resistor 130.
  • the resistor 130 needs to be shielded during the doping process to prevent the resistor 130 from being damaged due to doping.
  • the barrier layer 135 blocks the main body of the resistor 130 and only exposes the contact hole areas 133 and 134 at both ends of the resistor 130 .
  • the barrier layer 135 may be silicon nitride, oxide, or oxynitride, or may be a photoresist material. After the doping process is completed, the barrier layer 135 can remain in the display substrate or be removed.
  • barrier layer 135 of the resistor 130 can also be formed together with barrier layers/mask layers in other areas during doping, and the embodiments of the present disclosure are not limited to this.
  • N-type doping and P-type doping need to be performed respectively, for example, to form the source and drain regions of N-type transistors and the source and drain regions of P-type transistors.
  • a barrier layer needs to be formed to block the area where N-type doping is not performed; when performing a P-type doping process, a barrier layer needs to be formed to block the area where P-type doping is not performed.
  • the N-type doped regions SN and P-type doped regions SP are shown in FIG. 28E with different shading patterns (left image) and are shown on the substrate shown in FIG. 28D.
  • Type doped region SP (right picture).
  • the N-type doped region SN and the P-type doped region SP are also shown in FIG. 27B and may be referred to together.
  • performing an N-type doping process includes forming a barrier layer to cover the P-type doped region SP and cover the N-type doped region SN except for the doped window region and the polysilicon region, leaving only the N-type doped region SN.
  • the doped window area and the polysilicon area in the SN area that is, the overlapping area between the SN area and the doped window area 103 and the polysilicon area shown in FIG. 28C; then perform an N-type doping process.
  • the gate electrodes and the first and second electrodes of the transistors N1 - N3 can be formed through the N-type doping process, as well as the contact hole regions 411a, 411b, 145a, and 145b.
  • the N-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, boron.
  • performing a P-type doping process includes forming a barrier layer to cover the N-type doped region SN and cover the area in the P-type doped region SP except for the doped window region and the polysilicon region, leaving only the P-type doped region SP.
  • the doped window area and the polysilicon area in the SP area that is, the overlapping area between the SP area and the doped window area 103 and the polysilicon area shown in FIG. 28C; then a P-type doping process is performed.
  • the gate electrode, the first electrode and the second electrode of the transistor P1, as well as the contact holes 400a, 400b, 133, and 134 can be formed through this P-type doping process.
  • the P-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, phosphorus.
  • the polysilicon pattern can act as a mask, so that the implantation of ions into the silicon-based substrate occurs exactly on both sides of the polysilicon, thereby forming the first and second electrodes of each transistor. , achieving self-alignment.
  • the resistivity of the originally high-resistance polysilicon is reduced through the doping process, and the gate electrode of each transistor and the first capacitor electrode can be formed. Therefore, using polysilicon materials as resistor and gate materials has various beneficial effects and saves process costs.
  • the structure of the display substrate shown in FIG. 27A is formed, including each of the transistors P1, N1-N3, the resistor 130, and the storage capacitor Cst.
  • the corresponding transistors, resistors and storage capacitors Cst in two adjacent sub-pixels in the first direction D1 are respectively symmetrical about the symmetry axis along the second direction D2; in the two adjacent sub-pixels in the second direction D2
  • the corresponding transistor, resistor and storage capacitor Cst are respectively symmetrical about the symmetry axis along the first direction D1.
  • the storage capacitor Cst is a capacitor formed by a field effect. After a voltage is applied to the first capacitor electrode 141, an inversion occurs in the area of the base substrate 101 below the first capacitor electrode 141. The charge turns the lower plate of the storage capacitor Cst, that is, the second capacitor electrode 142 into a conductor.
  • the second capacitor electrode 142 may also be formed by conducting a conductive process (such as doping process) on the area of the base substrate 101 below the first capacitor electrode 141 in advance.
  • a conductive process such as doping process
  • the second insulating layer 202, the first conductive layer 301, the third insulating layer 203, the second conductive layer 302, the fourth insulating layer 204, the third conductive layer 303, and the fifth insulating layer are sequentially formed on the substrate shown in FIG. 27A. 205 and the fourth conductive layer 304 to form the display substrate shown in FIG. 26A.
  • FIG. 29A and 29B respectively show the pattern of the first conductive layer 301 and the situation in which the first conductive layer 301 is disposed on the substrate structure shown in FIG. 27A.
  • FIG. 29C shows the cross-section line IV-IV' of FIG. 29B.
  • Figure 29B also shows the via holes in the second insulating layer 202, which correspond to each contact area in Figure 27B, and are used to connect each contact hole area with the pattern in the first conductive layer 301 Electrical connection.
  • FIG. 29B shows the via holes in the second insulating layer 202, which correspond to each contact area in Figure 27B, and are used to connect each contact hole area with the pattern in the first conductive layer 301 Electrical connection.
  • a dotted box is used to illustrate the area of one sub-pixel 100; in addition, the section line II' in Figure 26A is also shown in Figure 29B. Location.
  • the pattern of the first conductive layer in two sub-pixels adjacent in the first direction D1 is symmetrical about the symmetry axis along the second direction D2; in the two sub-pixels adjacent in the second direction D2
  • the pattern of the first conductive layer is symmetrical about the symmetry axis along the first direction D1.
  • the pattern of the first conductive layer will be exemplified below by taking a sub-pixel as an example.
  • the first conductive layer 301 includes a connection electrode 313 , which is used to electrically connect the first end 131 of the resistor 130 and the second electrode 152 of the driving sub-circuit 112 .
  • the first end of the connection electrode 313 is electrically connected to the first end 131 of the resistor 130 through the via hole 225 in the second insulating layer 202 ;
  • the second end of the connection electrode 313 includes a first branch. 331 and the second branch 332, with reference to FIG. 26B, the first branch 331 is electrically connected to the first pole 151 of the driving transistor N2 through the via 226a in the second insulating layer 202, and the second branch 332 passes through the second insulating layer 202.
  • the via hole 226b in is electrically connected to the first pole 181 of the bias transistor N3.
  • the via hole 225 and the via hole 226 a are located on opposite sides of the first capacitor electrode 141 respectively; that is, the orthographic projection of the connection electrode 313 on the base substrate 101
  • the orthographic projection of the first capacitor electrode 141 on the base substrate 101 is passed through in the second direction D2.
  • At least two via holes 226a and 226b may be provided to reduce contact resistance.
  • the first conductive layer 301 further includes a connection electrode 314 that is electrically connected to the second end 132 of the resistor 130 through the via hole 229 in the second insulating layer 202 .
  • the connection electrode 314 is used to electrically connect with the first electrode 121 of the light emitting element 120 .
  • the connecting electrode 314 is L-shaped, one branch thereof is electrically connected to the second end 132 of the resistor 130 , and the other branch is used to be electrically connected to the first electrode 121 of the light-emitting element 120 .
  • the first conductive layer 301 further includes a third capacitor electrode 315 , and the third capacitor electrode 315 overlaps the first capacitor electrode 141 in a direction perpendicular to the base substrate.
  • the third capacitor electrode 315 is electrically connected to the contact hole region 145a through the via hole 227 in the second insulating layer 202 to be electrically connected to the second capacitor electrode 142; that is, in the direction perpendicular to the base substrate, the second capacitor electrode 315 is electrically connected to the contact hole region 145a.
  • the capacitor electrode 142 and the third capacitor electrode 315 are respectively located on both sides of the first capacitor electrode 141 and are electrically connected to each other, thereby forming a parallel capacitor structure and increasing the capacitance value of the storage capacitor Cst.
  • the first conductive layer 301 further includes a fourth capacitor electrode 316 , and the fourth capacitor electrode 316 is connected with the first capacitor electrode 141 and the second capacitor electrode 142 perpendicular to the base substrate. overlap in all directions.
  • the fourth capacitor electrode 316 is electrically connected to the contact hole region 145b through the via hole 228 in the second insulating layer 202 to be electrically connected to the second capacitor electrode 142.
  • the fourth capacitor electrode 316 can further increase the capacitance value of the storage capacitor Cst and improve circuit performance.
  • the third capacitor electrode 315 and the fourth capacitor electrode 316 are located on both sides of the connection electrode 313 in the first direction D1.
  • adjacent third capacitor electrodes 315 in two sub-pixels adjacent to D1 in the first direction may be integrally formed to receive the same second power supply voltage VSS.
  • Adjacent fourth capacitive electrodes 316 in two sub-pixels may be integrally formed to receive the same second power supply voltage VSS.
  • At least two via holes 227 and at least two via holes 228 can be provided to reduce contact resistance; for example, the at least two via holes 227 are arranged along the second direction D2, and the at least two via holes 228 are arranged along the second direction D2. cloth.
  • the first conductive layer 301 also includes a connection electrode 317, which is used to electrically connect the second end of the data writing sub-circuit to the first end of the storage sub-circuit, that is, the first data writing transistor P1
  • the second pole 161 of the second data writing transistor N1 and the first capacitor electrode 141 are electrically connected.
  • the connection electrode 317 includes three ends, such as a T-shaped structure. 26B, the first end of the connection electrode 317 is electrically connected to the second pole of the first data writing transistor P1 through the via hole 261a in the second insulating layer 202, and the second end of the connection electrode 317 passes through the second insulating layer 202.
  • the via hole 261b in the insulating layer 202 is electrically connected to the second electrode of the second data writing transistor N1
  • the third end of the connecting electrode 317 is electrically connected to the first capacitor electrode 141 through the via hole 261c in the second insulating layer 202.
  • connection electrode 314 and the connection electrode 317 at least partially overlap.
  • This arrangement makes the pixel layout more compact, thereby improving the space utilization of the display substrate and improving the resolution of the display substrate.
  • the first conductive layer 301 also includes a first scan line connection portion 311 and a second scan line connection portion 312.
  • the first scan line connection portion 311 is used to electrically connect with the first scan line.
  • the gate of the first data writing transistor P1 receives the first control signal SEL.
  • the second scan line connection portion 312 is used to electrically connect with the second scan line so that the gate of the second data writing transistor N1 receives the first control signal SEL_B.
  • the first scan line connection portion 311 is electrically connected to the gate of the first data writing transistor P1 through the via hole 221 in the second insulating layer 202 , and the second scan line connection portion 312 passes through the via hole 221 in the second insulating layer 202 .
  • the via hole 222 is electrically connected to the gate of the second data writing transistor N1.
  • sub-pixels adjacent in the first direction D1 share the first scan line connection part 311 or the second scan line connection part 312.
  • the first conductive layer 301 also includes a data line connection portion 245 (an example of the third connection electrode of the present disclosure).
  • the data line connection portion 245 is used to electrically connect with the data line, so that the first The first pole of the data writing transistor P1 and the first pole of the second data writing transistor N1 receive the data signal Vd transmitted by the data line.
  • the data line connecting portion 245 is electrically connected to the first electrode 161 of the first data writing transistor P1 through the via hole 223 in the second insulating layer 202 , and is electrically connected to the first electrode 161 of the first data writing transistor P1 through the hole 224 in the second insulating layer 202 .
  • the first pole 171 of the second data writing transistor N1 is electrically connected.
  • a plurality of data line connecting portions 245 are arranged at intervals in the first direction D1, for example, located at the boundary of two sub-pixel rows. For example, two adjacent sub-pixels in the second direction D2 share one data line connection portion 245 .
  • the first conductive layer 301 further includes a connection electrode 318 , which is electrically connected to the first electrode of the driving transistor N2 through the via hole 230 in the second insulating layer 202 .
  • the first conductive layer 301 also includes connection electrodes 319a, 319b, and 319c. These connection electrodes are all provided for biasing the substrate of the transistor, for example, for connecting the N-type substrate to
  • the first power supply voltage terminal is used to receive the first power supply voltage VDD (high voltage), or is used to connect the P-type substrate to the second power supply voltage terminal to receive the second power supply voltage VSS (low voltage), thereby avoiding substrate bias. effect and other parasitic effects, improving the stability of the circuit.
  • connection electrodes 319a and 319b are electrically connected to the contact hole regions 411a and 411b in the second region (N-well region) 402 of the base substrate 101 through the via holes 262a and 262b in the second insulating layer 202 respectively.
  • the connection electrodes 319a and 319b are used to be connected to the first voltage terminal VDD to bias the N-type substrate of the first data writing transistor P1.
  • the connection electrode 319c is electrically connected to the contact hole area 400a in the base substrate 101 through the via hole 262c in the second insulating layer 202.
  • the connection electrode 319c is used to be connected to the second voltage terminal VSS to write the second data.
  • the P-type substrate on which transistor N1 is located is biased.
  • the first conductive layer 301 also includes a bias voltage line 250.
  • the bias voltage line 250 extends along the first direction D1 and connects to the bias transistor through the via 263 in the second insulating layer 202.
  • the gate of N3 is electrically connected to provide the second common voltage Vcom2.
  • the first conductive layer 301 also includes a power line 260 (an example of the ninth power line of the present disclosure).
  • the power line 260 extends along the first direction D1 for transmitting the second power. Voltage VSS.
  • the power line 260 is electrically connected to the first electrode of the bias transistor N3 through the via hole 264a in the second insulating layer 202 to provide the second power supply voltage VSS, and is connected to the substrate through the via hole 264b in the second insulating layer 202
  • the contact hole region 400b in the substrate 101 is electrically connected to bias the P-type substrate (an example of the second doped region of the present disclosure) where the second data writing transistor N1 is located.
  • Figure 30A shows a schematic diagram of the second conductive layer 302.
  • Figure 30B shows the second conductive layer 302 based on the first conductive layer 301.
  • Figure 30B also shows the via hole in the third insulating layer 203.
  • the via hole in the third insulating layer 203 is used to connect the pattern in the first conductive layer 301 and the pattern in the second conductive layer 302 .
  • Figure 30B also shows the section line II' in Figure 26A correspondingly. Location.
  • the pattern of the second conductive layer in two adjacent sub-pixels in the first direction D1 is symmetrical about the symmetry axis along the second direction D2; in the two adjacent sub-pixels in the second direction D2
  • the pattern of the second conductive layer is symmetrical about the symmetry axis along the first direction D1.
  • the following takes a sub-pixel as an example to illustrate the pattern of the second conductive layer.
  • the second conductive layer 302 includes power lines 270a, 270b, 280a, and 280b extending along the first direction D1.
  • the power lines 270a and 270b are used to transmit the second power voltage VSS.
  • the power lines 280a, 270b are used to transmit the second power voltage VSS.
  • 280b is used to transmit the first power supply voltage VDD.
  • the power lines 270a, 280a, 270b, and 280b are arranged alternately one by one in the second direction D2.
  • the power line 270a (an example of the first power line of the present disclosure) passes through a plurality of via holes 235 in the third insulating layer 203 and the power line 260 in the first conductive layer 301 Electrical connection, thereby forming a parallel structure, effectively reducing the resistance on the wiring; the plurality of via holes 235 are arranged along the first direction D1.
  • the power line 270b is electrically connected to the fourth capacitor electrode 316 through the via hole 236 in the third insulating layer 203 to provide the second power supply voltage VSS; for example, the plurality of via holes 236 are arranged along the second direction D2.
  • the power line 270b is also electrically connected to the third capacitor electrode 315 through the via holes 267 in the third insulating layer 203 to provide the second power supply voltage VSS; for example, the plurality of via holes 267 are arranged along the second direction D2.
  • the average line width of the power line 270b is greater than the average line width of the power line 270a. This is due to the fourth capacitor electrically connected to the power line 270b. Both the electrode 316 and the third capacitor electrode 315 have a large area. Setting the power line 270b to have a large width can facilitate the formation of multiple connection holes 236, 267 between the fourth capacitor electrode 316 and the third capacitor electrode 315. , thereby effectively reducing contact resistance.
  • the power line 280a (an example of the second power line of the present disclosure) passes through the via hole 237 in the third insulating layer 203 and connects to the connection electrode 318 in the first conductive layer 301 (the fifth example of the present disclosure).
  • An example of a connecting electrode is electrically connected to the first electrode of the driving transistor N2 to provide the first power supply voltage VDD.
  • the power line 280b is electrically connected to the connection electrode 319a in the first conductive layer 301 through the via hole 238 in the third insulating layer 203, thereby connecting the second region (N-well region) 402 (N-well region) 402 in the base substrate 101 (the present disclosure).
  • An example of the first doped region) is subjected to high voltage bias; for example, a plurality of via holes 238 are arranged along the second direction D2.
  • the average line width of the power line 280b is greater than the average line width of the power line 280a. This is due to the connection electrode 319a electrically connected to the power line 280b. Having a larger size in the second direction D2, setting the power line 280b to have a larger width can facilitate the formation of multiple connection holes 238 with the connection electrode 319a, thereby increasing the contact area with the connection electrode 319a, effectively Reduce contact resistance.
  • the second conductive layer 302 further includes a plurality of first scan lines 210 and a plurality of second scan lines 220 extending along the first direction D1.
  • the scan line 11 shown in FIG. 24A may be the first scan line 210 or the second scan line 220.
  • the first scan line 210 is electrically connected to the first scan line connection portion 311 through the via hole 231 in the third insulating layer 203, and the second scan line 220 passes through the via hole 231 in the third insulating layer 203.
  • the via hole 232 is electrically connected to the second scan line connection portion 312 .
  • the second conductive layer 302 also includes a connection electrode 323, which is connected to the connection electrode in the first conductive layer 301 through the via hole 239 in the third insulating layer 203. 314 is electrically connected to the second end 132 of the resistor 130 .
  • the connection electrode 323 is used to electrically connect with the first electrode 121 of the light emitting element 120 .
  • the number of via holes 239 is at least two.
  • the second conductive layer 302 further includes a connection electrode 324 , which is electrically connected to the connection electrode 319b in the first conductive layer 301 through the via hole 265 in the third insulating layer 203 , to be electrically connected to the contact hole region 411b in the second region (N-well region) 402 in the base substrate 101.
  • the second conductive layer 302 further includes a connection electrode 325 that is electrically connected to the connection electrode 319c in the first conductive layer 301 through the via hole 266 in the third insulating layer 203 , to be electrically connected to the contact hole area 400a in the base substrate 101.
  • connection electrode 325 has a cross-shaped structure.
  • connection electrodes 324 and the connection electrodes 325 are alternately distributed in the first direction D1 and are located at the boundary of two sub-pixel rows.
  • the second conductive layer 302 further includes a data line connection portion 244 (an example of the fourth connection electrode of the present disclosure).
  • the data line connection portion 244 is electrically connected to the data line connection portion 245 in the first conductive layer 301 through the via hole 233 .
  • a plurality of data line connecting portions 244 are arranged at intervals in the first direction D1 , and a connecting electrode 324 or a connecting electrode 325 is provided between every two adjacent data line connecting portions 244 .
  • the data line connection portion 244 is located at the boundary of two sub-pixel rows. For example, two adjacent sub-pixels in the second direction D2 share one data line connection portion 244 .
  • the data line connection portions 244 located in each column of sub-pixels are alternately located on both sides of the data line connection portion 245, and are connected to the data lines through via holes 233, 234 respectively.
  • the first end and the second end of the connection part 245 are electrically connected in order to connect the data line connection part 245 to different data lines.
  • Figure 31A shows a schematic diagram of the third conductive layer 303.
  • Figure 31B shows the third conductive layer 303 based on the second conductive layer 302.
  • Figure 31B also shows the via hole in the fourth insulating layer 204.
  • the via hole in the fourth insulating layer 204 is used to connect the pattern in the second conductive layer 302 and the pattern in the third conductive layer 303 .
  • Figure 31A shows a schematic diagram of the third conductive layer 303.
  • Figure 31B shows the third conductive layer 303 based on the second conductive layer 302.
  • Figure 31B also shows the via hole in the fourth insulating layer 204.
  • the via hole in the fourth insulating layer 204 is used to connect the pattern in the second conductive layer 302 and the pattern in the third conductive layer 303 .
  • Figure 31A shows a schematic diagram of the third conductive layer 303.
  • Figure 31B shows the third conductive layer 303 based on the second conductive layer 302.
  • Figure 31B also shows the
  • the third conductive layer 303 includes a plurality of data lines extending along the second direction D2, and the data lines are used to be connected to the first end of the data writing sub-circuit in the sub-pixel to provide the data signal Vd.
  • the plurality of data lines include a plurality of first data lines 241 and a plurality of second data lines 242.
  • the first data lines 241 and the second data lines 242 are arranged alternately one by one in the first direction D1. cloth.
  • the data line 12 shown in FIG. 24A may be the first data line 241 or the second data line 242.
  • each data line group includes a first data line 241 and a second data line 242.
  • each sub-pixel column is connected to a data line group, that is, a first data line 241 and a second data line 242 are connected; that is, one column of sub-pixels is driven by two data lines. This helps reduce the load on each data line, thereby improving the driving capability of the data line, reducing signal delay, and improving the display effect.
  • the first data line 241 passes through the via hole 403 in the fourth insulating layer 204 and the data line in the second conductive layer 302 shown in FIG. 30B between the first row of sub-pixels and the second row of sub-pixels.
  • the connection portion 244 is electrically connected to provide data signals to the first and second rows of sub-pixels;
  • the second data line 242 passes through the via hole 404 in the fourth insulating layer 204 and is connected to the second conductive layer 302 shown in FIG. 30B
  • the data line connection portion 244 located between the third row of sub-pixels and the fourth row of sub-pixels is electrically connected to provide data signals to the third and fourth rows of sub-pixels.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

本发明属于显示领域，涉及一种显示基板和显示装置。该显示基板包括驱动基板、阳极层、像素限定层、发光功能层、阴极层和封装层；驱动电路包括至少一个晶体管，晶体管包括半导体层，半导体层至少部分位于衬底内部；阳极层包括多个阳极，显示基板包括多个像素开口，且位于多个阳极远离驱动基板的一侧；多个像素开口被配置为与多个阳极至少存在交叠；各阳极包括主体部和凸起部，凸起部与主体部相连，凸起部在垂直于驱动基板的方向上的尺寸大于主体部在垂直于驱动基板的方向上的尺寸；发光功能层包括多个发光部，多个发光部与多个阳极的主体部接触设置。由此，该显示基板可减少和避免相邻子像素之间的串扰。

Description

显示基板和显示装置
本申请要求于2022年04月22日递交的中国专利申请202210423991.9号的优先权，在此全文引用上述PCT申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，微型有机发光二极管(Micro Organic Light-Emitting Diode，简称Micro-OLED)显示装置是一种以硅基板为衬底的新型OLED显示装置，又叫做硅基有机发光二极管(简称硅基OLED)显示装置。硅基OLED显示装置具有体积小、分辨率高等优点，其采用CMOS集成电路工艺制备，可以实现像素的有源寻址，并且可以在硅基衬底上制备包括TCON(时序控制)电路、OCP(操作控制)电路等多种功能电路，可以实现轻量化。
微型OLED(Micro OLED)显示器具有优秀的显示特性，例如分辨率高、亮度高、色彩丰富、驱动电压低、响应速度快、功耗低等，具有广阔的发展前景。
发明内容
本公开实施例提供一种显示基板和显示装置。该显示基板包括驱动基板、阳极层、像素限定层、发光功能层、阴极层和封装层；驱动基板包括衬底和驱动电路；阳极层位于驱动基板上；像素限定层位于阳极层远离驱动基板的一侧；发光功能层位于阳极层远离驱动基板的一侧；阴极层位于发光功能层远离驱动基板的一侧；封装层位于阴极层远离驱动基板的一侧；驱动电路包括至少一个晶体管，晶体管包括半导体层，半导体层至少部分位于衬底内部；阳极层包括多个阳极，显示基板包括多个像素开口，多个像素开口位于像素限定层之中，且位于多个阳极远离驱动基板的一侧，多个像素开口被配置为与多个阳极至少存在交叠；各阳极包括主体部和凸起部，凸起部设置在主体部的周边，凸起部在垂直于驱动基板的方向上的尺寸大于主体部在垂 直于驱动基板的方向上的尺寸，发光功能层包括多个发光部，多个发光部位于多个像素开口之内，且与多个阳极的所述主体部接触设置。由此，该显示基板可有效地避免相邻子像素之间的漏电和串扰。
本公开至少一个实施例提供一种显示基板，其包括：驱动基板，包括衬底和驱动电路；第一平坦层，位于所述驱动电路上；阳极层，位于所述第一平坦层远离所述驱动基板的一侧；像素限定层，位于所述阳极层远离所述驱动基板的一侧；发光功能层，位于所述阳极层远离所述驱动基板的一侧；阴极层，位于所述发光功能层远离所述驱动基板的一侧；以及封装层，位于所述阴极层远离所述驱动基板的一侧；所述驱动电路包括至少一个晶体管，所述晶体管包括半导体层，所述半导体层至少部分位于所述衬底内部，所述阳极层包括多个阳极，所述显示基板包括多个像素开口，且位于所述多个阳极远离所述驱动基板的一侧，所述多个像素开口被配置为与所述多个阳极至少存在交叠；各所述阳极包括主体部和凸起部，所述凸起部与所述主体部相连，所述凸起部第一方向上的尺寸大于所述主体部在所述第一方向上的尺寸，所述发光功能层包括多个发光部，所述多个发光部与所述多个阳极的所述主体部接触设置，所述主体部所在位置处的所述第一平坦层远离所述衬底的表面与所述衬底的距离与所述凸起部所在位置处的所述第一平坦层远离所述衬底的表面与所述衬底的距离相等，所述主体部远离所述衬底的表面与所述第一平坦层远离所述衬底的表面的距离小于所述凸起部远离所述衬底的表面与所述第一平坦层远离所述衬底的表面的距离。
例如，在本公开一实施例提供的一种显示基板中，所述凸起部设置在所述主体部的周边。
例如，在本公开一实施例提供的一种显示基板中，所述像素限定层在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影交叠。
例如，在本公开一实施例提供的一种显示基板中，所述像素限定层包括像素限定部，所述像素限定部包括：像素限定平坦部，位于相邻的两个所述阳极之间；以及突起结构，分别位于相邻两个所述阳极的所述凸起部远离所述驱动基板的一侧，所述像素限定平坦部将所述突起结构相连。
例如，在本公开一实施例提供的一种显示基板中，所述像素限定部关于所述相邻两个所述阳极之间的间隔区的中心呈对称设置。
例如，在本公开一实施例提供的一种显示基板中，各所述突起结构包 括：第一侧壁，位于所述突起结构靠近所述主体部的中心的一侧；以及第二侧壁，与所述第一侧壁相连，所述第二侧壁相对于所述第一侧壁，更远离所述驱动基板；所述第一侧壁的坡度角大于所述第二侧壁的坡度角。
例如，在本公开一实施例提供的一种显示基板中，所述第一侧壁的坡度角的取值范围为75-89度，所述第二侧壁的坡度角的取值范围为15-45度。
例如，在本公开一实施例提供的一种显示基板中，各所述突起结构还包括：第三侧壁，位于所述突起结构靠近所述像素限定平坦部的一侧，其中，所述第三侧壁的坡度角大于所述第二侧壁的坡度角，且小于所述第一侧壁的坡度角。
例如，在本公开一实施例提供的一种显示基板中，各所述突起结构还包括：第三侧壁，位于所述突起结构靠近所述像素限定平坦部的一侧，所述第一侧壁的坡度角为α，所述第二侧壁的坡度角为β，所述第三侧壁的坡度角为γ，并满足下列公式：β<γ<α。
例如，在本公开一实施例提供的一种显示基板中，所述第一侧壁的坡度角与所述第二侧壁的坡度角的差值等于所述第三侧壁的坡度角的i倍，i的取值范围为0.8-1.2。
例如，在本公开一实施例提供的一种显示基板中，所述第一侧壁的坡度角α，所述第二侧壁的坡度角β，所述第三侧壁的坡度角γ满足下列公式：(α-β)＝i*γ，i的取值范围为0.8-1.2。
例如，在本公开一实施例提供的一种显示基板中，所述第一侧壁的坡度角与所述第二侧壁的坡度角的差值等于所述第二侧壁的坡度角与第三侧壁的坡度角的差值的j倍，j的取值范围为1.5-3。
例如，在本公开一实施例提供的一种显示基板中，所述第一侧壁的坡度角α，所述第二侧壁的坡度角β，所述第三侧壁的坡度角γ满足下列公式：(α-β)＝j*(γ-β)，j的取值范围为1.5-3。
例如，在本公开一实施例提供的一种显示基板中，所述第一侧壁的坡度角与所述第二侧壁的坡度角之和等于所述第三侧壁的坡度角的k倍，k的取值范围为2-3。
例如，在本公开一实施例提供的一种显示基板中，所述第三侧壁的坡度角的取值范围为45-60度。
例如，在本公开一实施例提供的一种显示基板中，所述第三侧壁在所述 驱动基板上的正投影在第二方向上的尺寸大于所述第二侧壁在所述驱动基板上的正投影在所述第二方向上的尺寸，所述第二侧壁在所述驱动基板上的正投影在第二方向上的尺寸大于所述第一侧壁在所述驱动基板上的正投影在所述第二方向上的尺寸，所述第二方向为从所述凸起部到所述主体部的方向或从所述主体部到所述凸起部的方向，所述第二方向平行于所述驱动基板远离所述阳极层的表面。
例如，在本公开一实施例提供的一种显示基板中，所述第一侧壁在所述第一方向上的尺寸为H1，所述第二侧壁在所述第一方向上的尺寸为H2，所述第三侧壁在所述第一方向上的尺寸为H3，H1、H2和H3满足下列公式：
H3*cosγ>H2*cosβ>H1*cosα。
例如，在本公开一实施例提供的一种显示基板中，各所述阳极的所述凸起部包括第四侧壁，位于所述凸起部靠近所述主体部的中心的一侧，所述第四侧壁的坡度角大于所述第二侧壁的坡度角，且小于所述第一侧壁的坡度角。
例如，在本公开一实施例提供的一种显示基板中，各所述阳极的所述凸起部包括第四侧壁，位于所述凸起部靠近所述主体部的中心的一侧，所述第四侧壁的坡度角为δ，且满足以下公式：β<δ<α。
例如，在本公开一实施例提供的一种显示基板中，各所述阳极的所述凸起部包括：第一子阳极层，位于所述驱动电路远离所述衬底的一侧；第二子阳极层，位于所述第一子阳极层远离所述驱动基板的一侧；以及第三子阳极层，位于所述第二子阳极层远离所述驱动基板的一侧。
例如，在本公开一实施例提供的一种显示基板中，所述第一子阳极层在第二方向上的尺寸大于所述第三子阳极层在所述第二方向上的尺寸，所述第三子阳极层在所述第二方向上的尺寸大于所述第二子阳极层在所述第二方向上的尺寸，所述第二方向为从所述凸起部到所述主体部的方向或从所述主体部到所述凸起部的方向，所述第二方向平行于所述驱动基板远离所述阳极层的表面。
例如，在本公开一实施例提供的一种显示基板中，所述第一子阳极层远离所述主体部的一端包括隆起部，所述隆起部在所述第一方向上的厚度大于所述第一子阳极层在所述第一方向上的平均厚度。
例如，在本公开一实施例提供的一种显示基板中，所述第三子阳极层远 离所述主体部的一端向靠近所述第一子阳极层的方向弯曲。
例如，在本公开一实施例提供的一种显示基板中，各所述阳极的所述凸起部还包括：第四子阳极层，位于所述第二子阳极层和第三子阳极层之间，所述第四子阳极层在所述第二方向上的尺寸小于所述第二子阳极层在所述第二方向上的尺寸。
例如，在本公开一实施例提供的一种显示基板中，所述第三子阳极层在所述第二方向上超出所述第四子阳极层的尺寸小于所述像素限定层在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影的交叠区域在所述第二方向上的尺寸。
例如，在本公开一实施例提供的一种显示基板中，所述第二子阳极层包括第五侧壁，位于所述第二子阳极层远离所述主体部的一侧，所述第四子阳极层包括第六侧壁，位于所述第四子阳极层远离所述主体部的一侧，所述第五侧壁的坡度角大于所述第四侧壁的坡度角，所述第六侧壁的坡度角大于所述第四侧壁的坡度角，所述第五侧壁的坡度角大于所述第六侧壁的坡度角。
例如，在本公开一实施例提供的一种显示基板中，所述第一子阳极层在所述第一方向上的厚度与所述第二子阳极层在所述第一方向上的厚度之比的范围在1/15-1/5。
例如，在本公开一实施例提供的一种显示基板中，所述第一子阳极层在所述第一方向上的厚度与所述第三子阳极层在所述第一方向上的厚度之比的范围在1/3-4/5。
例如，在本公开一实施例提供的一种显示基板中，所述第一子阳极层在所述第一方向上的厚度与所述第四子阳极层在所述第一方向上的厚度之比的范围在1/24-1/8。
例如，在本公开一实施例提供的一种显示基板中，相邻两个所述阳极之间的距离与所述阳极的凸起部在所述驱动基板上的正投影的长度之比的范围为2-4。
例如，在本公开一实施例提供的一种显示基板中，相邻两个所述阳极之间的距离与所述阳极的凸起部在所述驱动基板上的正投影的长度之比的范围为2.5-3.5。
例如，在本公开一实施例提供的一种显示基板中，所述凸起部围绕所述主体部设置。
例如，在本公开一实施例提供的一种显示基板中，所述阳极在所述驱动基板上的正投影的形状包括六边形。
例如，本公开一实施例提供的一种显示基板还包括：反射电极层，位于所述第一平坦层靠近所述阳极层的一侧；以及第二平坦层，位于所述反射电极层靠近所述阳极层的一侧。
例如，在本公开一实施例提供的一种显示基板中，所述反射电极层在所述像素开口中连续设置。
例如，在本公开一实施例提供的一种显示基板中，所述发光功能层与所述主体部之间存在第一孔隙，所述发光功能层与所述像素限定层之间存在至少一个第二孔隙，所述第一孔隙占据的空间大于所述第二孔隙占据的空间。
例如，在本公开一实施例提供的一种显示基板中，所述封装层包括：无机封装层，位于所述阴极层远离所述驱动基板的一侧，所述无机封装层包括多个子无机封装层。
例如，在本公开一实施例提供的一种显示基板中，所述多个子无机封装层之中至少存在两个相邻的采用不同的材料制作的子无机封装层，所述多个子无机封装层中至少存在两个相邻的采用相同的材料制作的子无机封装层。
例如，在本公开一实施例提供的一种显示基板中，在远离所述驱动基板的方向上，所述多个子无机封装层的折射率先增大后减小。
例如，在本公开一实施例提供的一种显示基板中，在远离所述驱动基板的方向上，所述多个子无机封装层在所述第一方向上的厚度逐渐减小。
例如，在本公开一实施例提供的一种显示基板中，各所述子无机封装层包括：交替设置的平坦区和双拱间隔区、位于所述平坦区远离所述双拱间隔区的一侧的第一拱形区、位于所述平坦区和所述双拱间隔区之间的第二拱形区、以及位于所述平坦区远离所述第二拱形区的第三拱形区，所述第一拱形区和所述第二拱形区关于所述平坦区的中心对称设置。
例如，在本公开一实施例提供的一种显示基板中，所述平坦区在第二方向上的尺寸为L，所述第二拱形区的中心和所述第三拱形区的中心在所述第二方向上的距离为第一距离D1，所述第一拱形区的中心和所述第二拱形区的中心在所述第二方向上的距离为第二距离D2，所述第一拱形区、所述第二拱形区和所述第三拱形区的曲率半径均为R，
所述第一距离D1满足以下公式：
D2≤(L+D1)<(L+R)，
所述第二方向为从所述凸起部到所述主体部的方向或从所述主体部到所述凸起部的方向，所述第二方向平行于所述驱动基板远离所述阳极层的表面。
例如，在本公开一实施例提供的一种显示基板中，所述平坦区在第二方向上的尺寸为L，所述第二拱形区的中心和所述第三拱形区的中心在所述第二方向上的距离为第一距离D1，所述第一拱形区的中心和所述第二拱形区的中心在所述第二方向上的距离为第二距离D2，所述第一拱形区、所述第二拱形区和所述第三拱形区的曲率半径均为R，
所述第一距离D1满足以下公式：
(L+D1)≤D2<(L+R)，
所述第二方向为从所述凸起部到所述主体部的方向或从所述主体部到所述凸起部的方向，所述第二方向平行于所述驱动基板远离所述阳极层的表面。
例如，在本公开一实施例提供的一种显示基板中，所述第一拱形区、所述第二拱形区或所述第三拱形区在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影交叠，所述平坦区在所述驱动基板上的正投影与所述主体部在所述驱动基板上的正投影交叠，所述第一拱形区、所述第二拱形区或所述第三拱形区远离所述驱动基板的表面与所述驱动基板之间的距离大于所述平坦区远离所述驱动基板的表面与所述驱动基板之间的距离。
例如，在本公开一实施例提供的一种显示基板中，所述双拱间隔区在所述驱动基板上的正投影与相邻两个所述阳极之间的间隔区在所述驱动基板上的正投影交叠。
例如，在本公开一实施例提供的一种显示基板中，所述多个子无机封装层包括：第一子无机封装层，位于所述阴极层远离所述驱动基板的一侧；第二子无机封装层，位于所述第一子无机封装层远离所述驱动基板的一侧；第三子无机封装层，位于所述第二子无机封装层远离所述驱动基板的一侧；以及第四子无机封装层，位于所述第三子无机封装层远离所述驱动基板的一侧。
例如，在本公开一实施例提供的一种显示基板中，所述第一子无机封装层的折射率小于所述第二子无机封装层的折射率，所述第四子无机封装层的 折射率小于所述第三子无机封装层的折射率。
例如，在本公开一实施例提供的一种显示基板中，所述第二子无机封装层的折射率与所述第三子无机封装层的折射率相等。
例如，在本公开一实施例提供的一种显示基板中，所述第一子无机封装层的所述平坦区在所述第二方向上具有第一宽度，所述第二子无机封装层的所述平坦区在所述第二方向上具有第二宽度，所述第三子无机封装层的所述平坦区在所述第二方向上具有第三宽度，所述第四子无机封装层的所述平坦区在所述第二方向上具有第四宽度，所述第一宽度大于所述第二宽度，所述第二宽度大于所述第三宽度，所述第三宽度大于所述第四宽度。
例如，在本公开一实施例提供的一种显示基板中，所述第一子无机封装层的所述平坦区靠近所述第一拱形区的边缘、所述第二子无机封装层的所述平坦区靠近所述第一拱形区的边缘、所述第三子无机封装层的所述平坦区靠近所述第一拱形区的边缘和所述第四子无机封装层的所述平坦区靠近所述第一拱形区的边缘的第一连线与所述驱动基板远离所述阳极层的表面之间的夹角为第一夹角，所述第一子无机封装层的所述第一拱形区的顶点、所述第二子无机封装层的所述第一拱形区的顶点、所述第三子无机封装层的所述第一拱形区的顶点和所述第四子无机封装层的所述第一拱形区的顶点的第二连线与所述驱动基板远离所述阳极层的表面之间的夹角为第二夹角，所述第一夹角小于所述第二夹角。
例如，在本公开一实施例提供的一种显示基板中，所述第一夹角的范围为60-85度，所述第二夹角的范围为85-89度。
例如，在本公开一实施例提供的一种显示基板中，所述第一连线和所述第二连线的交点位于所述驱动基板之内。
例如，在本公开一实施例提供的一种显示基板中，所述驱动电路包括：半导体层，位于所述衬底之中；第一导电层，位于所述半导体层上；第二导电层，位于所述第一导电层远离所述衬底的一侧；第三导电层，位于所述第二导电层远离所述衬底的一侧；以及第四导电层，位于所述第三导电层远离所述衬底的一侧。
例如，在本公开一实施例提供的一种显示基板中，所述第一连线和所述第二连线的交点位于所述第三导电层远离所述衬底的上表面与所述阳极层之间。
例如，在本公开一实施例提供的一种显示基板中，所述第一连线与所述第二连线的交点与所述像素限定层的所述突起结构远离所述衬底的上表面的顶点之间距离大于所述第一子无机封装层在所述第一方向上的厚度。
例如，在本公开一实施例提供的一种显示基板中，所述第一连线与所述第二连线的交点与所述像素限定层的所述突起结构远离所述衬底的上表面的顶点之间距离小于所述第一子无机封装层在所述第一方向上的厚度和所述第二子无机封装层在所述第一方向上的厚度之和。
例如，在本公开一实施例提供的一种显示基板中，所述第一子无机封装层的所述第二拱形区靠近所述双拱间隔区的边缘、所述第二子无机封装层的所述第二拱形区靠近所述双拱间隔区的边缘、所述第三子无机封装层的所述第二拱形区靠近所述双拱间隔区的边缘和所述第四子无机封装层的所述第二拱形区靠近所述双拱间隔区的边缘的第三连线与所述驱动基板远离所述阳极层的表面之间的夹角为第三夹角，所述第三夹角小于所述第二夹角。
例如，在本公开一实施例提供的一种显示基板中，所述第一连线和所述三连线的交点位于所述第二导电层远离所述衬底的上表面与所述第三导电层靠近所述衬底的下表面之间。
例如，在本公开一实施例提供的一种显示基板中，所述第二连线和所述第三连线的交点位于所述第一导电层靠近所述衬底的下表面与所述衬底远离所述第一导电层的下表面之间。
例如，在本公开一实施例提供的一种显示基板中，所述第一子无机封装层的所述第三拱形区远离所述双拱间隔区的边缘、所述第二子无机封装层的所述第三拱形区远离所述双拱间隔区的边缘、所述第三子无机封装层的所述第三拱形区远离所述双拱间隔区的边缘和所述第四子无机封装层的所述第三拱形区远离所述双拱间隔区的边缘的第四连线与所述驱动基板远离所述阳极层的表面之间的夹角为第四夹角，所述第四夹角小于所述第二夹角。
例如，在本公开一实施例提供的一种显示基板中，所述第一连线与所述第四连线的交点位于所述衬底远离所述第一导电层的一侧。
例如，在本公开一实施例提供的一种显示基板中，所述第三连线与所述第四连线的交点位于所述衬底远离所述第一导电层的一侧。
例如，在本公开一实施例提供的一种显示基板中，所述第一子无机封装层的所述第一拱形区远离所述衬底的上表面具有第一曲率半径，所述第二子 无机封装层的所述第一拱形区远离所述衬底的上表面具有第二曲率半径，所述第三子无机封装层的所述第一拱形区远离所述衬底的上表面具有第三曲率半径，所述第四子无机封装层的所述第一拱形区远离所述衬底的上表面具有第四曲率半径，所述第一曲率半径小于所述第二曲率半径，所述第二曲率半径小于所述第三曲率半径，所述第三曲率半径小于所述第四曲率半径。
例如，在本公开一实施例提供的一种显示基板中，所述第四子无机封装层的所述第一拱形区的虚设圆心位于所述第一子无机封装层远离所述衬底的上表面和所述第四子无机封装层靠近所述衬底的下表面之间。
例如，在本公开一实施例提供的一种显示基板中，所述第一子无机封装层在所述第一方向上具有第一厚度，所述第二子无机封装层在所述第一方向上具有第二厚度，所述第三子无机封装层在所述第一方向上具有第三厚度，所述第四子无机封装层在所述第一方向上具有第四厚度，所述第一厚度大于所述第二厚度，所述第二厚度大于所述第三厚度，所述第三厚度大于所述第四厚度。
例如，在本公开一实施例提供的一种显示基板中，所述第一厚度与所述第二厚度的差值和所述第三厚度与所述第四厚度的差值的比例范围为1.5-2倍。
例如，在本公开一实施例提供的一种显示基板中，所述第二厚度和所述第三厚度之和与所述第一厚度的比例范围为0.8-1.2。
例如，在本公开一实施例提供的一种显示基板中，所述第一厚度的范围为1000-1200纳米，所述第二厚度的范围为500-660纳米，所述第三厚度的范围480-560纳米，所述第四厚度的范围为180-260纳米。
例如，在本公开一实施例提供的一种显示基板中，所述第一子无机封装层的材料包括氧化硅和氮氧化硅，所述第二子无机封装层的材料包括氮化硅，所述第三子无机封装层的材料包括氮化硅，所述第四子无机封装层的材料包括氧化硅。
例如，在本公开一实施例提供的一种显示基板中，所述封装层还包括：有机封装层，位于所述无机封装层远离所述驱动基板的一侧，所述有机封装层包括第一区域、第二区域和第三区域，所述第一区域的平均厚度小于所述第二区域的平均厚度，所述第二区域的平均厚度小于所述第三区域的平均厚度。
例如，本公开一实施例提供的一种显示基板还包括：彩膜层，位于所述封装层远离所述驱动基板的一侧，所述彩膜层包括第一彩色滤光片、第二彩色滤光片和第三彩色滤光片。
例如，在本公开一实施例提供的一种显示基板中，所述第一彩色滤光片和所述第二彩色滤光片存在第一交叠区，所述第二彩色滤光片和所述第三彩色滤光片存在第二交叠区，所述第三彩色滤光片和所述第一彩色滤光片存在第三交叠区。
例如，在本公开一实施例提供的一种显示基板中，所述第一交叠区、所述第二交叠区和所述第三交叠区在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影交叠。
例如，在本公开一实施例提供的一种显示基板中，所述第一交叠区、所述第二交叠区和所述第三交叠区在所述驱动基板上的正投影与相邻两个所述阳极之间的间隔区在所述驱动基板上的正投影交叠。
例如，在本公开一实施例提供的一种显示基板中，所述第一交叠区在所述第二方向上的尺寸大于所述第二交叠区在所述第二方向上的尺寸，所述第二交叠区在所述第二方向上的尺寸大于所述第三交叠区在所述第二方向上的尺寸。
例如，在本公开一实施例提供的一种显示基板中，所述第一交叠区在所述第二方向上的尺寸范围为400-600纳米，所述第二交叠区在所述第二方向上的尺寸范围为250-350纳米，所述第三交叠区在所述第二方向上的尺寸范围为100-200纳米。
例如，在本公开一实施例提供的一种显示基板中，所述第一彩色滤光片在所述第一方向上的平均尺寸大于所述第二彩色滤光片在所述第一方向上的平均尺寸，且小于所述第三彩色滤光片在所述第一方向上的平均尺寸。
例如，在本公开一实施例提供的一种显示基板中，所述第一彩色滤光片在所述第一方向上的平均尺寸的范围为2.3-2.6微米，所述第二彩色滤光片在所述第一方向上的平均尺寸的范围为1.7-1.95微米，所述第三彩色滤光片在所述第一方向上的平均尺寸的范围为2.3-2.7微米。
例如，在本公开一实施例提供的一种显示基板中，所述第一彩色滤光片在所述第一方向上的平均尺寸与所述第二彩色滤光片在所述第一方向上的平均尺寸的差值和所述第一彩色滤光片在所述第一方向上的平均尺寸与所述第 三彩色滤光片在所述第一方向上的平均尺寸的差值之比的范围为2-3。
例如，在本公开一实施例提供的一种显示基板中，所述第一彩色滤光片包括第一边缘部、第二边缘部和位于所述第一边缘部和所述第二边缘部之间的中间部，所述中间部在所述第一方向上的平均尺寸小于所述第一边缘部在所述第一方向上的平均尺寸和所述第二边缘部在所述第一方向上的平均尺寸。
例如，在本公开一实施例提供的一种显示基板中，所述第一彩色滤光片包括与所述第二彩色滤光片接触的第一接触面，所述第二彩色滤光片包括与所述第三彩色滤光片接触的第二接触面，所述第三彩色滤光片包括与所述第一彩色滤光片接触的第三接触面，所述第一接触面在垂直于所述驱动基板的第一方向上的尺寸与所述第二接触面在所述第一方向上的尺寸相等，且小于所述第三接触面在所述第一方向上的尺寸。
例如，在本公开一实施例提供的一种显示基板中，所述第一彩色滤光片与所述驱动基板远离所述阳极层的表面的距离大于所述第三彩色滤光片与所述驱动基板远离所述阳极层的表面的距离，且小于所述第二彩色滤光片与所述驱动基板远离所述阳极层的表面的距离。
例如，在本公开一实施例提供的一种显示基板中，所述第一彩色滤光片为红色滤光片，所述第二彩色滤光片为绿色滤光片，所述第三彩色滤光片为蓝色滤光片。
例如，在本公开一实施例提供的一种显示基板中，所述彩膜层的材料包括干燥剂。
例如，在本公开一实施例提供的一种显示基板中，所述彩膜层包括铝元素。
例如，本公开一实施例提供的一种显示基板还包括：保护层，位于所述彩膜层远离所述驱动基板的一侧。
例如，在本公开一实施例提供的一种显示基板中，所述彩膜层还包括：黑矩阵，位于第一彩色滤光片、第二彩色滤光片和第三彩色滤光片中任意相邻的两个之间。
例如，本公开一实施例提供的一种显示基板还包括：玻璃盖板，位于所述彩膜层远离所述驱动基板的一侧。
本公开至少一个实施例还提供一种显示装置，其包括上述任一项所述的 显示基板。
本公开至少一个实施例还提供另一种显示装置，其包括上述任一项所述的显示基板。
例如，本公开一实施例提供的一种显示装置还包括：对置基板，与所述显示基板相对设置，所述对置基板包括玻璃盖板和位于所述玻璃盖板上的彩膜层，所述彩膜层包括所述彩膜层包括第一彩色滤光片、第二彩色滤光片和第三彩色滤光片。
例如，在本公开一实施例提供的一种显示装置中，所述第一彩色滤光片和所述第二彩色滤光片存在第一交叠区，所述第二彩色滤光片和所述第三彩色滤光片存在第二交叠区，所述第三彩色滤光片和所述第一彩色滤光片存在第三交叠区。
例如，在本公开一实施例提供的一种显示装置中，所述第一交叠区、所述第二交叠区和所述第三交叠区在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影交叠。
例如，在本公开一实施例提供的一种显示装置中，所述第一交叠区、所述第二交叠区和所述第三交叠区在所述驱动基板上的正投影与相邻两个所述阳极之间的间隔区在所述驱动基板上的正投影交叠。
例如，在本公开一实施例提供的一种显示装置中，所述第一交叠区在第二方向上的尺寸大于所述第二交叠区在所述第二方向上的尺寸，所述第二交叠区在所述第二方向上的尺寸大于所述第三交叠区在所述第二方向上的尺寸。
例如，在本公开一实施例提供的一种显示装置中，所述第一交叠区在所述第二方向上的尺寸范围为400-600纳米，所述第二交叠区在所述第二方向上的尺寸范围为250-350纳米，所述第三交叠区在所述第二方向上的尺寸范围为100-200纳米。
例如，在本公开一实施例提供的一种显示装置中，所述第一彩色滤光片在所述第一方向上的平均尺寸大于所述第二彩色滤光片在所述第一方向上的平均尺寸，且小于所述第三彩色滤光片在所述第一方向上的平均尺寸。
例如，在本公开一实施例提供的一种显示装置中，所述第一彩色滤光片在所述第一方向上的平均尺寸的范围为2.3-2.6微米，所述第二彩色滤光片在所述第一方向上的平均尺寸的范围为1.7-1.95微米，所述第三彩色滤光片在 所述第一方向上的平均尺寸的范围为2.3-2.7微米。
例如，在本公开一实施例提供的一种显示装置中，所述第一彩色滤光片在所述第一方向上的平均尺寸与所述第二彩色滤光片在所述第一方向上的平均尺寸的差值和所述第一彩色滤光片在所述第一方向上的平均尺寸与所述第三彩色滤光片在所述第一方向上的平均尺寸的差值之比的范围为2-3。
例如，在本公开一实施例提供的一种显示装置中，所述第一彩色滤光片包括第一边缘部、第二边缘部和位于所述第一边缘部和所述第二边缘部之间的中间部，所述中间部在所述第一方向上的平均尺寸小于所述第一边缘部在所述第一方向上的平均尺寸和所述第二边缘部在所述第一方向上的平均尺寸。
例如，在本公开一实施例提供的一种显示装置中，所述第一彩色滤光片包括与所述第二彩色滤光片接触的第一接触面，所述第二彩色滤光片包括与所述第三彩色滤光片接触的第二接触面，所述第三彩色滤光片包括与所述第一彩色滤光片接触的第三接触面，所述第一接触面在与所述驱动基板垂直的第二方向上的尺寸与所述第二接触面在所述第二方向上的尺寸相等，且小于所述第三接触面在所述第二方向上的尺寸。
例如，在本公开一实施例提供的一种显示装置中，所述第一彩色滤光片与所述驱动基板远离所述阳极层的表面的距离大于所述第三彩色滤光片与所述驱动基板远离所述阳极层的表面的距离，且小于所述第二彩色滤光片与所述驱动基板远离所述阳极层的表面的距离。
例如，在本公开一实施例提供的一种显示装置中，所述第一彩色滤光片为红色滤光片，所述第二彩色滤光片为绿色滤光片，所述第三彩色滤光片为蓝色滤光片。
例如，在本公开一实施例提供的一种显示装置中，所述彩膜层的材料包括干燥剂。
例如，在本公开一实施例提供的一种显示装置中，所述彩膜层包括铝元素。
例如，在本公开一实施例提供的一种显示装置中，所述彩膜层还包括：黑矩阵，位于第一彩色滤光片、第二彩色滤光片和第三彩色滤光片中任意相邻的两个之间。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种显示基板的平面示意图。
图2为本公开一实施例提供的另一种显示基板的局部结构示意图。
图3为本公开一实施例提供的另一种显示基板的局部结构示意图。
图4A为本公开一实施例提供的另一种显示基板的局部结构示意图。
图4B为本公开一实施例提供的另一种显示基板的局部结构示意图。
图5为本公开一实施例提供的一种显示基板的平面示意图。
图6为本公开一实施例提供的另一种显示基板的局部结构示意图。
图7为本公开一实施例提供的另一种显示基板的局部结构示意图。
图8为本公开一实施例提供的另一种显示基板的局部结构示意图。
图9为本公开一实施例提供的一种显示基板中的第一彩色滤光片的示意图。
图10为本公开一实施例提供的另一种显示基板的局部结构示意图。
图11为本公开一实施例提供的一种驱动基板的结构示意图。
图12为本公开一实施例提供的另一种显示基板的局部结构示意图。
图13为本公开一实施例提供的一种显示装置的示意图。
图14为本公开一实施例提供的一种显示装置的平面图。
图15为本公开一实施例提供的另一种显示装置的示意图。
图16为本公开一实施例提供的一种显示基板的平面示意图。
图17为本公开一实施例提供的一种显示基板的局部剖面示意图。
图18为本公开一实施例提供的一种显示基板中驱动电路的等效示意图。
图19为本公开一实施例提供的一种显示基板中驱动电路的平面示意图。
图20A-20E分别示出了图19中所示的显示基板的各层布局的平面图。
图21为本公开一实施例提供的一种显示基板用于设置存储电容的区域的示意图。
图22为本公开一实施例提供的一种显示基板中存储电容的布局图。
图23A-图23D为图22中的各层布局的平面图。
图23E为本公开一实施例提供的一种显示基板中的存储电容的截面示意 图。
图24A为本公开一实施例提供的一种显示基板的框图。
图24B为本公开一实施例提供的一种像素电路的示意图。
图24C示出了该像素电路形成闩锁效应的示意图。
图25A为本公开一实施例提供的另一种像素电路的示意图。
图25B为图24A所示像素电路的一种具体实现示例的电路图。
图25C示出了图25B所示像素电路的信号时序图。
图26A为本公开一实施例提供的另一种显示基板的示意图。
图26B为图26A沿剖面线I-I’的剖视图。
图27A为本公开一实施例提供的另一种显示基板的示意图。
图27B为本公开一实施例提供的另一种显示基板的示意图。
图28A-图28E为图27A所示的基板结构的形成过程。
图29A-29C为本公开一实施例提供的一种显示基板的形成过程的示意图。
图30A为本公开一实施例提供的一种显示基板中第二导电层的示意图。
图30B本公开一实施例提供的一种显示基板中第一导电层和第二导电层的示意图。
图31A为本公开一实施例提供的一种显示基板中的第三导电层的示意图。
图31B为本公开一实施例提供的一种显示基板中第二导电层和第三导电层的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来 区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
通常的大尺寸有机发光二极管(OLED)显示装置通过将阳极隔离的方式来降低漏电和串扰。然而，在微型有机发光二极管(Micro-OLED)显示装置中，采用同样的方式虽然也可降低漏电和串扰，但是由于微型有机发光二极管显示装置中的像素限定层的厚度较低，并且像素密度较大，采用同样的方式不能彻底地隔离发光层，从而使得漏电和串扰现象仍然存在。
对此，本公开实施例提供一种显示基板和显示装置。该显示基板包括驱动基板、阳极层、像素限定层、发光功能层、阴极层和封装层；驱动基板包括衬底和驱动电路；阳极层位于驱动基板上；像素限定层位于阳极层远离驱动基板的一侧；发光功能层位于阳极层远离驱动基板的一侧；阴极层位于发光功能层远离驱动基板的一侧；封装层位于阴极层远离驱动基板的一侧；驱动电路包括至少一个晶体管，晶体管包括半导体层，半导体层至少部分位于衬底内部；阳极层包括多个阳极，显示基板包括多个像素开口，且位于多个阳极远离驱动基板的一侧，多个像素开口被配置为与多个阳极至少存在交叠；发光功能层包括多个发光部，多个发光部与多个阳极被暴露的部分接触设置。各阳极包括主体部和凸起部，凸起部与所述主体部相连，凸起部在垂直于驱动基板的第一方向上的尺寸大于主体部在垂直于驱动基板的第一方向上的尺寸。由此，该显示基板可提供一种微型的显示基板，可利用硅基电路板作为驱动基板来驱动发光功能层进行发光显示，并且还可减少和避免相邻子像素之间的串扰。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图1为本公开一实施例提供的一种显示基板的平面示意图；图2为本公开一实施例提供的另一种显示基板的局部结构示意图。
如图1和图2所示，该显示基板500包括驱动基板510、阳极层520、像素限定层530、发光功能层540、阴极层550和封装层560；驱动基板510包括衬底512和驱动电路514；阳极层520位于驱动基板510上；像素限定层 530位于阳极层520远离驱动基板510的一侧；发光功能层540位于阳极层520远离驱动基板510的一侧；阴极层550位于发光功能层540远离驱动基板510的一侧；封装层560位于阴极层550远离驱动基板510的一侧；驱动电路514包括至少一个晶体管T，晶体管T包括半导体层102，半导体层102至少部分位于衬底512内部。也就是说，衬底512部分可作为半导体层。需要说明的是，图1和图2中并未示出驱动电路的全部结构，驱动电路可以包括晶体管、存储电容、控流电阻、分压电阻等结构；驱动电路的具体电路结构可以根据实际需要进行设置，本公开的实施例对此不作限制。
例如，该驱动基板510可为硅基电路板，由于硅基电路板所采用的半导体制作工艺成熟，性能稳定，且具有较小的尺寸和精度，因此有利于制作微型显示装置。当然，本公开实施例包括但不限于此，驱动基板也可采用其他类型的驱动基板。
在一些示例中，如图1和图2所示，阳极层520包括多个阳极525，显示基板500包括多个像素开口535，多个像素开口535位于像素限定层530所在的膜层，且被像素限定层530包围；多个像素开口535位于多个阳极525远离驱动基板510的一侧，多个像素开口535被配置为与多个阳极525至少存在交叠；发光功能层540包括多个发光部545，多个发光部545至少部分位于多个像素开口535之内，且与多个阳极525被暴露的部分接触设置。由此，多个阳极可驱动多个发光部进行发光显示。
在本公开实施例提供的显示基板中，驱动基板可采用半导体制作工艺进行制作，从而可将用于驱动各个像素进行发光和显示的像素驱动电路集成在驱动基板之中。由此，该显示基板可提供一种微型的显示基板，并具有分辨率高、亮度高、色彩丰富、驱动电压低、响应速度快、功耗低等优点。
在一些示例中，如图1和图2所示，多个阳极525与多个像素开口535一一对应设置，多个像素开口535与多个发光部545一一对应设置。需要说明的是，上述的“一一对应设置”是指一个阳极上设置一个像素开口，一个像素开口中设置一个发光部，并且阳极在驱动基板上的正投影与对应的像素开口在驱动基板上的正投影至少部分重叠，像素开口在驱动基板上的正投影与发光部在驱动基板上的正投影至少部分重叠。当然，本公开实施例包括但不限于此。
在一些示例中，如图2所示，该显示基板100还包括：第一平坦层591、 第二平坦层592和反射电极层593；第一平坦层591位于驱动电路514和阳极层520之间；反射电极层593位于第一平坦层591靠近阳极层520的一侧；第二平坦层592位于反射电极层593靠近阳极层520的一侧。
在一些示例中，如图2所示，反射电极层593在像素开口535中连续设置。
在一些示例中，如图1和图2所示，该显示基板还包括彩膜层570，位于封装层560远离驱动基板510的一侧。当发光功能层被配置为发白光时，彩膜层可包括多个彩色滤光片，以实现彩色显示。当然，本公开实施例包括但不限于此，发光功能层也可被配置为直接发不同颜色的光。
在一些示例中，如图1和图2所示，该显示基板500还包括保护层580，位于彩膜层570远离驱动基板510的一侧。保护层580可以起到保护彩膜层570的效果，使得彩膜层570的滤光性能在长期使用过程中保持稳定，从而可提高显示基板的显示质量。
在一些示例中，如图1和图2所示，该显示基板500还包括玻璃盖板590，位于彩膜层570远离驱动基板510的一侧。
图3为本公开一实施例提供的另一种显示基板的局部结构示意图。图4A为本公开一实施例提供的另一种显示基板的局部结构示意图。如图3和图4A所示，图3所示的显示基板没有示出发光功能层，图4A所示的显示基板中示出了发光功能层。
如图3和图4A所示，各阳极525包括主体部525A和凸起部525B，凸起部525B与主体部525A相连，凸起部525B在第一方向上的尺寸大于主体部525A在第一方向上的尺寸；也就是说，凸起部525B的厚度大于主体部525A的厚度。主体部525A所在位置处的第一平坦层591远离衬底512的表面与衬底512的距离与凸起部525B所在位置处的第一平坦层591远离衬底512的表面与衬底512的距离相等，主体部525A远离衬底512的表面与第一平坦层591远离衬底512的表面的距离小于凸起部525B远离衬底512的表面与第一平坦层591远离衬底512的表面的距离。需要说明的是，第一方向可为垂直于驱动基板的方向。
在该示例提供的显示基板中，由于凸起部525B在垂直于驱动基板510的方向上的尺寸大于主体部525A在垂直于驱动基板510的方向上的尺寸，因此位于两个阳极525之间，且与阳极525的边缘部分交叠的像素限定层530可 形成与凸起部525对应的突起结构532。由此，在形成发光功能层540时，发光功能层540中的至少部分子功能层(例如电荷产生层)可更好地在突起结构532所在的位置断开，即相邻两个阳极525对应的发光部545中的至少部分子功能层不连接，从而可有效地避免相邻子像素之间的漏电和串扰。另一方面，此时的像素限定层530的突起结构532的高度也更高，从而可更好地起到像素限定的作用，从光学上减少和避免相邻子像素之间的串扰。
在一些示例中，如图3和图4A所示，各阳极525包括主体部525A和凸起部525B，凸起部525B设置在主体部525A的周边，从而可更好地使得发光功能层540中的至少部分功能层在主体部525A的边缘断开。
在一些示例中，如图3和图4A所示，像素限定层530在驱动基板510上的正投影与凸起部525B在驱动基板510上的正投影交叠。由此，像素限定层530可形成与凸起部525对应的，且位于凸起部525远离驱动基板510的一侧的突起结构532。
在一些示例中，如图3和图4A所示，像素限定层530包括像素限定部530A，像素限定部530A包括像素限定平坦部534和像素限定平坦部534两侧的两个突起结构532；像素限定平坦部534位于相邻的两个阳极525之间，两个突起结构532分别位于相邻两个阳极525的两个凸起部525B远离驱动基板510的一侧，像素限定平坦部534将两个突起结构532相连。也就是说，像素限定部530A既包括位于相邻两个阳极525之间的部分和与两个阳极525交叠的部分；由于相邻两个阳极525之间比较平坦，而阳极525的边缘部分设置有上述的凸出部525B，因此位于相邻两个阳极525之间的部分形成为上述像素限定平坦部534，而与两个阳极525交叠的部分形成为上述的突起结构532。
在该示例提供的显示基板中，在形成发光功能层540时，由于像素限定部530A的存在，发光功能层540中的至少部分子功能层(例如电荷产生层)可更好地在突起结构532所在的位置断开，即相邻两个阳极525对应的发光部545中的至少部分子功能层不连接，从而可有效地避免相邻子像素之间的漏电和串扰。另一方面，此时的突起结构532的高度也更高，从而可更好地起到像素限定的作用，从光学上减少和避免相邻子像素之间的串扰。
在一些示例中，如图3和图4A所示，像素限定部530A关于相邻两个阳极525之间的间隔区522的中心呈对称设置。需要说明的是，由于工艺误差 的存在，实际的像素限定部在间隔区的中心的两侧的两个部分可能存在差异，因此上述的像素限定部关于相邻两个阳极之间的间隔区的中心呈对称设置的情形包括像素限定部在间隔区的中心的两侧的两个部分重合率达到80％的情况。
在一些示例中，如图3和图4A所示，各突起结构532包括第一侧壁532A和第二侧壁532B；第一侧壁532A位于突起结构532靠近阳极525的主体部525A的中心的一侧，第二侧壁532B与第一侧壁532A相连且位于第一侧壁532A远离驱动基板510的一侧，也就是说，第二侧壁532B相对于第一侧壁532A，更远离驱动基板510；第一侧壁532A的坡度角大于第二侧壁532B的坡度角。需要说明的是，由于实际工艺中第一侧壁或第二侧壁可能并非标准的平面，因此上述的坡度角可为第一侧壁或第二侧壁的两个端点的连线的坡度角。
在该示例提供的显示基板中，在形成发光功能层的过程中，由于第一侧壁的坡度角大于第二侧壁的坡度角，第一侧壁具有较大的坡度角，因此更加陡峭，从而可更好地使得发光功能层中的至少部分子功能层(例如电荷产生层)在第一侧壁所在的位置断开。另一方面，由于第二侧壁的坡度角小于第一侧壁的坡度角，可形成一个平缓的平台，第二侧壁可对发光功能层的材料起到引导的作用，使得发光功能层在阳极被像素开口暴露的部分和突起结构相邻的位置形成接触不良的区域，从而可减少发光功能层在阳极被像素开口暴露的部分和突起结构相邻的位置的发光亮度。由此，该示例提供的显示基板可进一步降低相邻子像素之间的串扰。
在一些示例中，如图4A所示，发光功能层540与主体部525A之间存在第一孔隙5471，发光功能层540与像素限定层530之间存在至少一个第二孔隙5472，第一孔隙5471占据的空间大于第二孔隙5472占据的空间。由此，第一孔隙5471和第二孔隙5472形成了共同层横向传递载流子的弱传导区，有益于降低光的横向串扰。当然，本公开实施例包括但不限于此，发光功能层与像素限定层也可不形成上述的第二孔隙。
图4B为本公开一实施例提供的另一种显示基板的局部结构示意图。如图4B所示，发光功能层540与像素限定层530之间紧密贴合。
在一些示例中，如图3和图4A所示，突起结构532还包括第三侧壁532C，位于突起结构532远离主体部525A的一侧，第三侧壁532C的坡度角 大于532B第二侧壁的坡度角，且小于第一侧壁532A的坡度角。由此，第三侧壁的坡度角较为平缓，从而可减少甚至避免后续在第三侧壁上形成的发光功能层中形成孔隙，进而避免形成水氧入侵的通道。另一方面，由于第三侧壁的坡度角较为平缓，因此也便于像素限定部形成完整的一体结构，避免在第三侧壁产生脱落(Peeling)现象。
在一些示例中，如图3和图4A所示，各突起结构532还包括第三侧壁532C，第三侧壁532C位于突起结构532远离主体部525A的一侧。此时，第一侧壁532A的坡度角为α，第二侧壁532B的坡度角为β，第三侧壁532C的坡度角为γ，并满足下列公式：
β<γ<α。在该示例提供的显示基板中，第三侧壁532C的坡度角γ相对于第一侧壁532A的坡度角α较为平缓，从而可减少甚至避免后续在第三侧壁532C上形成的发光功能层中形成孔隙，进而避免形成水氧入侵的通道。另一方面，由于第三侧壁532C的坡度角γ较为平缓，因此也便于像素限定部形成完整的一体结构，避免在第三侧壁产生脱落(Peeling)现象。另一方面，由于第三侧壁532C的坡度角γ大于第二侧壁532B的坡度角β，因此可避免突起结构占用较大的面积，避免影响开口率。
在一些示例中，如图3和图4A所示，第一侧壁532A的坡度角与第二侧壁532B的坡度角的差值等于第三侧壁的坡度角的i倍，i的取值范围为0.8-1.2。由此，该突起结构可较好地实现上述的防止相邻子像素之间的串扰、避免形成水氧入侵、避免像素限定部产生脱落现象的效果。
在一些示例中，如图3和图4A所示，第一侧壁的坡度角α，第二侧壁的坡度角β，第三侧壁的坡度角γ满足下列公式：
(α-β)＝i*γ，
其中，i的取值范围为0.8-1.2。
在该示例提供的显示基板中，由于第一侧壁的坡度角α，第二侧壁的坡度角β，第三侧壁的坡度角γ满足上述公式所限定的大小关系，该突起结构可较好地实现上述的防止相邻子像素之间的串扰、避免形成水氧入侵、避免像素限定部产生脱落现象的效果。
在一些示例中，如图3和图4A所示，第一侧壁532A的坡度角与第二侧壁532B的坡度角的差值等于第二侧壁532B的坡度角与第三侧壁532C的坡度角的差值的j倍，j的取值范围为1.5-3。由此，该突起结构可较好地实现上 述的防止相邻子像素之间的串扰、避免形成水氧入侵、避免像素限定部产生脱落现象的效果。
在一些示例中，如图3和图4A所示，第一侧壁的坡度角α，第二侧壁的坡度角β，第三侧壁的坡度角γ满足下列公式：
(α-β)＝j*(γ-β)，
其中，j的取值范围为1.5-3。
在该示例提供的显示基板中，由于第一侧壁的坡度角α，第二侧壁的坡度角β，第三侧壁的坡度角γ满足上述公式所限定的大小关系，该突起结构可较好地实现上述的防止相邻子像素之间的串扰、避免形成水氧入侵、避免像素限定部产生脱落现象的效果。
在一些示例中，如图3和图4A所示，第一侧壁532A的坡度角与第二侧壁532B的坡度角之和等于第三侧壁532C的坡度角的k倍，k的取值范围为2-3。由此，该突起结构可较好地实现上述的防止相邻子像素之间的串扰、避免形成水氧入侵、避免像素限定部产生脱落现象的效果。
在一些示例中，如图3和图4A所示，第一侧壁的坡度角α，第二侧壁的坡度角β，第三侧壁的坡度角γ满足下列公式：
(α+β)＝k*γ-β，
其中，k的取值范围为2-3。
在该示例提供的显示基板中，由于第一侧壁的坡度角α，第二侧壁的坡度角β，第三侧壁的坡度角γ满足上述公式所限定的大小关系，该突起结构可较好地实现上述的防止相邻子像素之间的串扰、避免形成水氧入侵、避免像素限定部产生脱落现象的效果。
在一些示例中，如图3和图4A所示，第一侧壁532A的坡度角的取值范围可为75-89度；第二侧壁532B的坡度角的取值范围可为15-45度；第三侧壁532C的坡度角的取值范围可为45-60度。
在一些示例中，如图3和图4A所示，第一侧壁532A的坡度角的取值范围可为75-89度；第二侧壁532B的坡度角的取值范围可为25-35度；第三侧壁532C的坡度角的取值范围可为45-55度。
在一些示例中，如图3和图4A所示，第二侧壁532B在驱动基板510上的正投影在第二方向上的尺寸大于第一侧壁532A在驱动基板510上的正投影在第二方向上的尺寸。由此，该突起结构可更好地在第一侧壁所在的位置使 得发光功能层中电荷产生层的断开。
在一些示例中，如图3和图4A所示，第三侧壁532C在驱动基板510上的正投影在第二方向上的尺寸大于第二侧壁532B在驱动基板510上的正投影在第二方向上的尺寸。由此，该突起结构可减少甚至避免后续在第三侧壁532C上形成的发光功能层中形成孔隙，进而避免形成水氧入侵的通道。另一方面，由于第三侧壁532C的坡度角γ较为平缓，因此也便于像素限定部形成完整的一体结构，避免在第三侧壁产生脱落(Peeling)现象。
在一些示例中，如图3和图4A所示，第一侧壁532A在第一方向上的尺寸为H1，第二侧壁532B在第一方向上的尺寸为H2，第三侧壁532C在第一方向上的尺寸为H3，H1、H2和H3满足下列公式：
H3*cosγ>H2*cosβ>H1*cosα。
由此，该突起结构可更好地在第一侧壁所在的位置使得发光功能层中电荷产生层的断开；同时，该突起结构可减少甚至避免后续在第三侧壁上形成的发光功能层中形成孔隙，进而避免形成水氧入侵的通道。
在一些示例中，如图3和图4A所示，各阳极525的凸起部525B还包括第四侧壁525D，位于凸起部525B靠近主体部525A的中心的一侧，第四侧壁525D的坡度角大于第二侧壁532B的坡度角，且小于第一侧壁532A的坡度角。
在一些示例中，如图3和图4A所示，阳极525的凸起部525B包括第四侧壁525D，位于凸起部525B靠近主体部525A的中心的一侧，第四侧壁的坡度角为δ，且满足以下公式：
β<δ<α。
在一些示例中，如图3和图4A所示，各阳极525的凸起部525B包括：第一子阳极层5251、第二子阳极层5252和第三子阳极层5253；第一子阳极层5251位于驱动电路514远离衬底512的一侧；第二子阳极层5252位于第一子阳极层5251远离驱动基板510的一侧；第三子阳极层5253位于第二子阳极层5252远离驱动基板510的一侧。
在一些示例中，如图3和图4A所示，第一子阳极层5251在第二方向上的尺寸大于第三子阳极层5253在第二方向上的尺寸，第三子阳极层5253在第二方向上的尺寸大于第二子阳极层5252在第二方向上的尺寸。由此，由于第三子阳极层在第二方向上的尺寸大于第二子阳极层在第二方向上的尺寸， 第三子阳极层的边缘缺少支撑，因此可使得第三子阳极层5253形成向驱动基板510弯曲的弯曲结构5253S，在后续形成像素限定部时，可有效地避免像素限定部产生脱落(Peeling)现象。需要说明的是，由于像素限定部通常采用无机材料制作，如果凸起部的边缘过于陡峭，则容易产生脱落现象。
另一方面，第三子阳极层可采用导电性能较差的材料制作，例如氧化铟锡；此时，由于第三子阳极层在第二方向上的尺寸大于第二子阳极层在第二方向上的尺寸，第三子阳极层的边缘缺少支撑，因此可使得第三子阳极层形成向驱动基板弯曲的弯曲结构，从而可在一定程度上起到对于凸起部的边缘的包裹作用，进而可在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。
例如，上述的第二方向为从凸起部525B到主体部525A的方向或者从主体部525A到凸起部525B的方向，第二方向平行于驱动基板510远离阳极层520的表面的方向。
例如，第三子阳极层的导电率小于第一子阳极层的导电率和第二子阳极层的导电率，从可更好地与发光功能层的功函数进行匹配。
在一些示例中，如图3和图4A所示，第三子阳极层5253在第二方向上超出第二子阳极层5252的尺寸小于像素限定层530在驱动基板510上的正投影与凸起部525B在驱动基板510上的正投影的交叠区域在第二方向上的尺寸。
在一些示例中，如图3和图4A所示，第三子阳极层5253在第二方向上超出第二子阳极层5252的尺寸小于像素限定层530在驱动基板510上的正投影与凸起部525B在驱动基板510上的正投影的交叠区域在第二方向上的尺寸的1/4。
在一些示例中，如图3和图4A所示，第三子阳极层5253远离主体部525A的一端向靠近第一子阳极层5251的方向弯曲，从而第三子阳极层可在一定程度上起到对于凸起部的边缘的包裹作用，进而可在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。
在一些示例中，如图3和图4A所示，各阳极525的凸起部525B还包括第四子阳极层5254，位于第二子阳极层5252和第三子阳极层5253之间。由此，可通过将位于阳极的凸起部的第四子阳极层保留，而将位于阳极的主体部的第四子阳极层刻蚀掉，从而可形成上述的具有高度差异的主体部和凸起 部。
在一些示例中，如图3和图4A所示，第四子阳极层5254在第二方向上的尺寸小于第二子阳极层5252在第二方向上的尺寸。由此，形成在第四子阳极层5254上的第三子阳极层5253可更好地形成弯曲结构5253S，从而在后续形成像素限定部时，可有效地避免像素限定部产生脱落(Peeling)现象。
在一些示例中，如图3和图4A所示，第三子阳极层5253在第二方向上超出第四子阳极层5254的尺寸小于像素限定层530在驱动基板510上的正投影与凸起部525B在驱动基板510上的正投影的交叠区域在所述第二方向上的尺寸。
在一些示例中，如图3和图4A所示，第二子阳极层5252包括第五侧壁525E，位于第二子阳极层525E远离主体部525A的一侧，第四子阳极层5254包括第六侧壁525F，位于第四子阳极层5254远离主体部525A的一侧；第五侧壁525E的坡度角大于第四侧壁525D的坡度角，第六侧壁525F的坡度角大于第四侧壁525D的坡度角，第五侧壁525E的坡度角大于第六侧壁525F的坡度角，从而避免第二子阳极层和第三子阳极层形成尖端结构。由此，可在一定程度上抑制尖端放电现象，从而可以提高产品的良率和使用寿命。
在一些示例中，如图3和图4A所示，第一子阳极层5251远离主体部525A的一端包括隆起部5251A，隆起部5251A在垂直于驱动基板510的方向上的厚度大于第一子阳极层5251在垂直于驱动基板510的方向上的平均厚度。由此，隆起部5251A也可在一定程度上起到对于凸起部的边缘的包裹作用，进而可在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。
在一些示例中，如图3和图4A所示，当第一子阳极层5251的隆起部5251A和第三子阳极层5253的弯曲结构5253S同时存在时，隆起部5251A和弯曲结构5253S可从上下两个方向起到将凸起部的边缘包裹的作用，进而可更好地在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。需要说明的是，本公开实施例包括但不限于此，当第一子阳极层5251的隆起部5251A或第三子阳极层5253的弯曲结构5253S单独存在时，也可在一定程度上起到将凸起部的边缘包裹作用。
在一些示例中，第一子阳极层5251在垂直于驱动基板510的方向上的厚度与第二子阳极层5252在垂直于驱动基板510的方向上的厚度之比的范围在 1/15-1/5。
在一些示例中，第一子阳极层5251在垂直于驱动基板510的方向上的厚度与第三子阳极层5253在垂直于驱动基板510的方向上的厚度之比的范围在1/3-4/5。
在一些示例中，第一子阳极层5251在垂直于驱动基板510的方向上的厚度与第四子阳极层5254在垂直于驱动基板510的方向上的厚度之比的范围在1/24-1/8。
在一些示例中，第一子阳极层5251在垂直于驱动基板510的方向上的厚度范围为1-4纳米；第二子阳极层5252在垂直于驱动基板510的方向上的厚度范围为15-22纳米；第四子阳极层5254在垂直于驱动基板510的方向上的厚度范围为24-32纳米；第三子阳极层5253在垂直于驱动基板510的方向上的厚度范围为3-5纳米。
在一些示例中，第一子阳极层5251在垂直于驱动基板510的方向上的厚度范围为2-3纳米；第二子阳极层5252在垂直于驱动基板510的方向上的厚度范围为17-20纳米；第四子阳极层5254在垂直于驱动基板510的方向上的厚度范围为26-30纳米；第三子阳极层5253在垂直于驱动基板510的方向上的厚度范围为4纳米。
在一些示例中，相邻两个阳极525之间的距离与阳极525的凸起部525B在驱动基板510上的正投影的长度之比的范围为2-4。也就是说，相邻两个阳极525之间的距离与阳极525在第二方向上的长度之比的范围为2-4。由此，该显示基板可更好地避免相邻子像素之间的串扰。
在一些示例中，相邻两个阳极525之间的距离与阳极525的凸起部525B在驱动基板510上的正投影的长度之比的范围为2.5-3.5。也就是说，相邻两个阳极525之间的距离与阳极525在第二方向上的长度之比的范围为2.5–3.5。由此，该显示基板可更好地避免相邻子像素之间的串扰。
在一些示例中，相邻两个阳极525之间的距离范围为0.6-1微米。也就是说，间隔区522的宽度范围可在0.6-1微米。当然，本公开实施例包括但不限于此，间隔区的宽度范围可根据实际情况进行设置。
在一些示例中，相邻两个阳极525的距离范围为0.7-0.9微米。当然，本公开实施例包括但不限于此，间隔区的宽度范围可根据实际情况进行设置。
图5为本公开一实施例提供的一种显示基板的平面示意图。如图5所 示，凸起部525B围绕主体部525A设置。由此，该显示基板可有效地避免在任何方向上相邻的子像素之间的串扰，从而使得该显示基板可适应于不同的像素排列结构。
在一些示例中，如图5所示，阳极525在驱动基板510上的正投影的形状包括六边形。当然，本公开实施例包括但不限于此，阳极525在驱动基板510上的正投影的形状也可为其他合适的形状。需要说明的是，像素开口与阳极对应设置，因此像素开口在驱动基板上的正投影的形状与阳极在驱动基板上的正投影的形状相似。
在一些示例中，如图5所示，多个阳极525在驱动基板510上呈阵列排布，以形成阳极行610；在各阳极行610中，多个阳极525沿方向依次排布。
在一些示例中，如图5所示，上述的第二方向可为行方向。此时，各阳极525在驱动基板510上的正投影在第二方向上的尺寸与相邻两个阳极525之间的距离的比值范围在4-6。由此，该显示基板可实现较大的开口率，并有效地避免相邻子像素之间的串扰。
在一些示例中，如图5所示，各阳极525在驱动基板510上的正投影在第二方向上的尺寸可为4-5微米。
图6为本公开一实施例提供的另一种显示基板的局部结构示意图。如图6所示，如图6所示，各阳极525的凸起部525B包括第一子阳极层5251、第二子阳极层5252和第三子阳极层5253；第一子阳极层5251位于驱动电路514远离衬底512的一侧；第二子阳极层5252位于第一子阳极层5251远离驱动基板510的一侧；第三子阳极层5253位于第二子阳极层5252远离驱动基板510的一侧。与图3和图4A所示的显示基板不同的是，图6所示的显示基板不包括第四子阳极层。
在一些示例中，如图6所示，阳极525的主体部525A与凸起部525B可具有相同的层结构，即包括同样数量的多个膜层和同样的层叠关系，但不限定各个膜层的厚度相同。此时，可通过将位于阳极的主体部的第二子阳极层部分刻蚀，而保留阳极的凸起部的第二子阳极层，从而形成具有高度差异的主体部和凸起部。
在一些示例中，如图6所示，第一子阳极层5251在第二方向上的尺寸大于第三子阳极层5253在第二方向上的尺寸，第三子阳极层5253在第二方向上的尺寸大于第二子阳极层5252在第二方向上的尺寸；上述的第二方向为从 凸起部525B到主体部525A的方向或者从主体部525A到凸起部525B的方向，第二方向平行于驱动基板510远离阳极层520的表面的方向。由此，由于第三子阳极层在第二方向上的尺寸大于第二子阳极层在第二方向上的尺寸，第三子阳极层的边缘缺少支撑，因此可使得第三子阳极层5253形成向驱动基板510弯曲的弯曲结构5253S，在后续形成像素限定部时，可有效地避免像素限定部产生脱落(Peeling)现象。需要说明的是，由于像素限定部通常采用无机材料制作，如果凸起部的边缘过于陡峭，则容易产生脱落现象。
另一方面，第三子阳极层可采用导电性能较差的材料制作，例如氧化铟锡；此时，由于第三子阳极层在第二方向上的尺寸大于第二子阳极层在第二方向上的尺寸，第三子阳极层的边缘缺少支撑，因此可使得第三子阳极层形成向驱动基板弯曲的弯曲结构，从而可在一定程度上起到对于凸起部的边缘的包裹作用，进而可在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。
例如，第三子阳极层的导电率小于第一子阳极层的导电率和第二子阳极层的导电率。
在一些示例中，如图6所示，第三子阳极层5253远离主体部525A的一端向靠近第一子阳极层5251的方向弯曲，从而第三子阳极层可在一定程度上起到对于凸起部的边缘的包裹作用，进而可在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。
在一些示例中，如图6所示，第二子阳极层5252包括第五侧壁525E和第六侧壁525F，第六侧壁525F位于第五侧壁525E远离驱动基板510的一侧，即第六侧壁525F相比与第五侧壁525E更远离驱动基板510。第五侧壁525E的坡度角大于第四侧壁525D的坡度角，第六侧壁525F的坡度角大于第四侧壁525D的坡度角，第五侧壁525E的坡度角大于第六侧壁525F的坡度角，从而避免第二子阳极层形成尖端结构。由此，可在一定程度上抑制尖端放电现象，从而可以提高产品的良率和使用寿命。另外，通过在第二子阳极层5252的边缘形成包括第五侧壁和第六侧壁的阶梯形结构，可使得位于第二子阳极层上的第三子阳极层形成更加平滑的弯曲结构，从而可更好地防止像素限定部发生脱落现象。
在一些示例中，如图6所示，第一子阳极层5251远离主体部525A的一端包括隆起部5251A，隆起部5251A在垂直于驱动基板510的方向上的厚度 大于第一子阳极层5251在垂直于驱动基板510的方向上的平均厚度。由此，隆起部5251A也可在一定程度上起到对于凸起部的边缘的包裹作用，进而可在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。
在一些示例中，如图6所示，当第一子阳极层5251的隆起部5251A和第三子阳极层5253的弯曲结构5253S同时存在时，隆起部5251A和弯曲结构5253S可从上下两个方向起到将凸起部的边缘包裹的作用，进而可更好地在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。需要说明的是，本公开实施例包括但不限于此，当第一子阳极层5251的隆起部5251A或第三子阳极层5253的弯曲结构5253S单独存在时，也可在一定程度上起到将凸起部的边缘包裹作用。
图7为本公开一实施例提供的另一种显示基板的局部结构示意图。如图7所示，如图7所示，各阳极525的凸起部525B包括第一子阳极层5251、第二子阳极层5252、第三子阳极层5253和第四子阳极层5254；第一子阳极层5251位于驱动电路514远离衬底512的一侧；第二子阳极层5252位于第一子阳极层5251远离驱动基板510的一侧；第三子阳极层5253位于第二子阳极层5252远离驱动基板510的一侧；第四子阳极层5254位于第二子阳极层5252和第三子阳极层5253之间。
在一些示例中，如图7所示，阳极525的主体部525A与凸起部525B可具有相同的层结构，即包括同样数量的多个膜层和同样的层叠关系，但不限定各个膜层的厚度相同。此时，阳极525的主体部525A同样包括第一子阳极层5251、第二子阳极层5252、第三子阳极层5253和第四子阳极层5254；第一子阳极层5251位于驱动电路514远离衬底512的一侧；第二子阳极层5252位于第一子阳极层5251远离驱动基板510的一侧；第三子阳极层5253位于第二子阳极层5252远离驱动基板510的一侧；第四子阳极层5254位于第二子阳极层5252和第三子阳极层5253之间。此时，可通过将位于阳极的主体部的第二子阳极层部分刻蚀，而保留阳极的凸起部的第二子阳极层，从而形成具有高度差异的主体部和凸起部。
例如，如图7所示，位于阳极525的主体部525A的第一子阳极层5251在垂直于驱动基板510的方向上的厚度与位于阳极525的凸起部525B的第一子阳极层5251在垂直于驱动基板510的方向上的厚度相同。
例如，如图7所示，位于阳极525的主体部525A的第三子阳极层5253在垂直于驱动基板510的方向上的厚度与位于阳极525的凸起部525B的第三子阳极层5253在垂直于驱动基板510的方向上的厚度相同。
例如，如图7所示，位于阳极525的主体部525A的第四子阳极层5254在垂直于驱动基板510的方向上的厚度与位于阳极525的凸起部525B的第四子阳极层5254在垂直于驱动基板510的方向上的厚度相同。
在一些示例中，如图7所示，第一子阳极层5251在第二方向上的尺寸大于第三子阳极层5253在第二方向上的尺寸，第三子阳极层5253在第二方向上的尺寸大于第二子阳极层5252在第二方向上的尺寸；第四子阳极层5254在第二方向上的尺寸小于第二子阳极层5252在第二方向上的尺寸。上述的第二方向为从凸起部525B到主体部525A的方向或者从主体部525A到凸起部525B的方向，第二方向平行于驱动基板510远离阳极层520的表面的方向。由此，形成在第四子阳极层5254上的第三子阳极层5253可更好地形成弯曲结构5253S，从而在后续形成像素限定部时，可有效地避免像素限定部产生脱落(Peeling)现象。
另一方面，第三子阳极层可采用导电性能较差的材料制作，例如氧化铟锡；此时，由于第三子阳极层在第二方向上的尺寸大于第二子阳极层在第二方向上的尺寸，第三子阳极层的边缘缺少支撑，因此可使得第三子阳极层形成向驱动基板弯曲的弯曲结构，从而可在一定程度上起到对于凸起部的边缘的包裹作用，进而可在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。
例如，第三子阳极层的导电率小于第一子阳极层的导电率和第二子阳极层的导电率。
在一些示例中，如图7所示，第三子阳极层5253远离主体部525A的一端向靠近第一子阳极层5251的方向弯曲，从而第三子阳极层可在一定程度上起到对于凸起部的边缘的包裹作用，进而可在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。
在一些示例中，如图7所示，第二子阳极层5252包括第五侧壁525E，位于第二子阳极层525E远离主体部525A的一侧，第四子阳极层5254包括第六侧壁525F，位于第四子阳极层5254远离主体部525A的一侧；第五侧壁525E的坡度角大于第四侧壁525D的坡度角，第六侧壁525F的坡度角大于第 四侧壁525D的坡度角，第五侧壁525E的坡度角大于第六侧壁525F的坡度角，从而避免第二子阳极层和第三子阳极层形成尖端结构。由此，可在一定程度上抑制尖端放电现象，从而可以提高产品的良率和使用寿命。
在一些示例中，如图7所示，第一子阳极层5251远离主体部525A的一端包括隆起部5251A，隆起部5251A在垂直于驱动基板510的方向上的厚度大于第一子阳极层5251在垂直于驱动基板510的方向上的平均厚度。由此，隆起部5251A也可在一定程度上起到对于凸起部的边缘的包裹作用，进而可在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。
在一些示例中，如图7所示，当第一子阳极层5251的隆起部5251A和第三子阳极层5253的弯曲结构5253S同时存在时，隆起部5251A和弯曲结构5253S可从上下两个方向起到将凸起部的边缘包裹的作用，进而可更好地在像素限定部出现缺陷时防止凸起部的边缘与发光功能层接触，也可避免产生尖端放电等现象。需要说明的是，本公开实施例包括但不限于此，当第一子阳极层5251的隆起部5251A或第三子阳极层5253的弯曲结构5253S单独存在时，也可在一定程度上起到将凸起部的边缘包裹作用。
图8为本公开一实施例提供的另一种显示基板的局部结构示意图。如图8所示，封装层560包括无机封装层710；无机封装层710位于阴极层550远离驱动基板510的一侧。
在一些示例中，如图8所示，无机封装层710包括多个子无机封装层7100，多个子无机封装层7100之中至少存在两个相邻的采用不同的材料制作的子无机封装层7100，多个子无机封装层7100中至少存在两个相邻的采用相同的材料制作的子无机封装层7100。通过在多个子无机封装层7100之间设置至少两个相邻的采用不同的材料制作的子无机封装层7100和至少两个相邻的采用相同的材料制作的子无机封装层7100，该无机封装层可形成更加致密的膜层，从而可更好地防止水氧入侵，进而可提高该显示装置的使用寿命。
例如，各个子无机封装层7100的材料可选自氮化硅、氧化硅、氮氧化硅中的至少一种。
在一些示例中，如图8所示，在远离驱动基板510的方向上，多个子无机封装层7100的折射率先增大后减小。发光功能层540发出的出射光从折射率较小的子无机封装层进入折射率较大的子无机封装层时，出射光会在它们 之间的界面发生折射，从而可降低出射光扩散角度，从而可在显示基板的内部减少或避免相邻子像素之间的串扰；然后，出射光再从折射率较大的子无机封装层进入折射率较小的子无机封装层，并在它们之间的界面发生折射，此时出射光的扩散角度增大，但是由于出射光已经接近显示基板的出光面，不会对相邻子像素造成串扰。
在一些示例中，如图8所示，各子无机封装层7100包括交替设置的平坦区PTQ和双拱间隔区JGQ、位于平坦区PTQ远离双拱间隔区JGQ的一侧的第一拱形区GX1、位于平坦区PTQ和双拱间隔区JGQ之间的第二拱形区GX2、以及位于平坦区PTQ远离第二拱形区GX2的第三拱形区GX3，第一拱形区GX1和第二拱形区GX2关于平坦区PTQ的中心对称设置。
在一些示例中，如图8所示，第一拱形区GX1、第二拱形区GX2或第三拱形区GX3在驱动基板510上的正投影与凸起部525B在驱动基板510上的正投影交叠，平坦区PTQ在驱动基板510上的正投影与主体部525A在驱动基板510上的正投影交叠。也就是说，各个子无机封装层7100的第一拱形区GX1、第二拱形区GX2或第三拱形区GX3在驱动基板510上的正投影与凸起部525B在驱动基板510上的正投影交叠，各个子无机封装层7100的平坦区PTQ在驱动基板510上的正投影与主体部525A在驱动基板510上的正投影交叠；并且，各个子无机封装层7100的第一拱形区GX1、第二拱形区GX2和第三拱形区GX3与不同的阳极525的凸起部525B交叠。由此，各个子像素边缘的光可经过第一拱形区、第二拱形区或第三拱形区的折射而会聚到黑矩阵上，从而可避免相邻子像素之间的串扰。需要说明的是，上述的黑矩阵可为通常的黑矩阵或者至少两个彩色滤光片交叠而形成的光透过率较低，并起到黑矩阵的作用的结构。
在一些示例中，如图8所示，平坦区PTQ在第二方向上的尺寸为L，第二拱形区GX2的中心和第三拱形区GX3的中心在第二方向上的距离为第一距离D1，第一拱形区GX1的中心和第二拱形区GX2的中心在第二方向上的距离为第二距离D2，第一拱形区GX1、第二拱形区GX2和第三拱形区GX3的曲率半径均为R，第一距离D1满足以下公式：
D2≤(L+D1)<(L+R)。
在本示例提供的显示基板中，通过使得第一距离D1满足上述的公式，可在提高像素密度或者开口率的同时，降低相邻子像素之间的串扰，从而可获 得一个较好的显示效果。需要说明的是，上述的曲率半径为平均曲率半径，即对应弧线的平均曲率的倒数。例如，上述的第二方向为从凸起部到主体部的方向或从主体部到凸起部的方向，第二方向平行于驱动基板远离阳极层的表面。
在一些示例中，如图8所示，平坦区PTQ在第二方向上的尺寸为L，第二拱形区GX2的中心和第三拱形区GX3的中心在第二方向上的距离为第一距离D1，第一拱形区GX1的中心和第二拱形区GX2的中心在第二方向上的距离为第二距离D2，第一拱形区GX1、第二拱形区GX2和第三拱形区GX3的曲率半径均为R，第一距离D1满足以下公式：
(L+D1)≤D2<(L+R)。
在本示例提供的显示基板中，通过使得第一距离D1满足上述的公式，可在提高像素密度或者开口率的同时，降低相邻子像素之间的串扰，从而可获得一个较好的显示效果。
例如，上述的第二方向为从凸起部到主体部的方向或从主体部到凸起部的方向，第二方向平行于驱动基板远离阳极层的表面。
在一些示例中，如图8所示，在各子无机封装层7100中，第一拱形区GX1、第二拱形区GX2或第三拱形区GX3远离驱动基板510的表面与驱动基板510之间的距离大于平坦区PTQ远离驱动基板510的表面与驱动基板510之间的距离。由此，第一拱形区GX1、第二拱形区GX2或第三拱形区GX3为向上拱起的结构。
在一些示例中，如图8所示，双拱间隔区JGQ在驱动基板510上的正投影与相邻两个阳极525之间的间隔区522在驱动基板510上的正投影交叠。
在一些示例中，如图8所示，多个子无机封装层7100包括：第一子无机封装层711、第二子无机封装层712、第三子无机封装层713和第四子无机封装层714；第一子无机封装层711位于阴极层550远离驱动基板510的一侧；第二子无机封装层712位于第一子无机封装层711远离驱动基板510的一侧；第三子无机封装层713位于第二子无机封装层711远离驱动基板510的一侧；以及第四子无机封装层714位于第三子无机封装层713远离驱动基板510的一侧。
在一些示例中，如图8所示，第一子无机封装层711的折射率小于第二子无机封装层712的折射率，第四子无机封装层714的折射率小于第三子无 机封装层713的折射率。由此，发光功能层540发出的出射光从折射率较小的第一子无机封装层711进入折射率较大的第二子无机封装层712时，出射光会在第一子无机封装层711和第二子无机封装层712之间的界面发生折射，从而可降低出射光扩散角度，从而可在显示基板的内部减少或避免相邻子像素之间的串扰；然后，出射光再从折射率较大的第三子无机封装层713进入折射率较小的第四子无机封装层714，并在它们之间的界面发生折射，此时出射光的扩散角度增大，但是由于出射光已经接近显示基板的出光面，不会对相邻子像素造成串扰。
在一些示例中，如图8所示，第二子无机封装层712的折射率与第三子无机封装层713的折射率相等。此时，第二子无机封装层712和第三子无机封装层713可采用相同的材料制作。当然，本公开实施例包括但不限于此，第二子无机封装层的折射率与第三子无机封装层的折射率也可不等。
在一些示例中，如图8所示，第一子无机封装层711和第二子无机封装层712采用不同的材料制作；第四子无机封装层714和第三子无机封装层713可采用不同的材料制作。
例如，第一子无机封装层711采用氧化硅或氮氧化硅材料制作，第二子无机封装层712采用氮化硅材料制作；第四子无机封装层714采用氧化硅材料制作，第三子无机封装层713采用氮化硅材料制作。
在一些示例中，如图8所示，第一子无机封装层711和第四子无机封装层714可采用相同的材料制作，也可采用不同的材料制作。
例如，第一子无机封装层711和第四子无机封装层714均采用氧化硅材料制作；或者，第一子无机封装层711采用氮氧化硅材料制作，第四子无机封装层714采用氧化硅材料制作。
在一些示例中，如图8所示，第一子无机封装层711的第一拱形区GX1远离衬底512的上表面具有第一曲率半径，第二子无机封装层712的第一拱形区GX1远离衬底512的上表面具有第二曲率半径，第三子无机封装层713的第一拱形区GX1远离衬底512的上表面具有第三曲率半径，第四子无机封装层714的第一拱形区GX1远离衬底512的上表面具有第四曲率半径，第一曲率半径小于第二曲率半径，第二曲率半径小于第三曲率半径，第三曲率半径小于第四曲率半径。也就是说，在远离驱动基板510的方向上，各个子无机封装层的第一拱形区的曲率半径逐渐增大。
在一些示例中，如图8所示，与各子无机封装层的第一拱形区远离衬底的上表面的曲率半径满足的关系类似，各子无机封装层的第二拱形区远离衬底的上表面的曲率半径在远离驱动基板的方向上也逐渐增大。
在一些示例中，如图8所示，与各子无机封装层的第一拱形区远离衬底的上表面的曲率半径满足的关系类似，各子无机封装层的第三拱形区远离衬底的上表面的曲率半径在远离驱动基板的方向上也逐渐增大。
在一些示例中，如图8所示，第一子无机封装层711的第一拱形区GX1，第二拱形区GX2和第三拱形区GX3的形状相同；第二子无机封装层712的第一拱形区GX1，第二拱形区GX2和第三拱形区GX3的形状相同；第三子无机封装层713的第一拱形区GX1，第二拱形区GX2和第三拱形区GX3的形状相同；第四子无机封装层714的第一拱形区GX1，第二拱形区GX2和第三拱形区GX3的形状相同。
在一些示例中，如图8所示，第四子无机封装层714的第一拱形区的虚设圆心位于第一子无机封装层711远离衬底512的上表面和第四子无机封装层714靠近衬底512的下表面之间。需要说明的是，上述的虚设圆心是指以第一拱形区远离衬底的上表面的弧线作虚拟圆形的圆心。
在一些示例中，如图8所示，第一子无机封装层711在垂直于驱动基板510的方向上具有第一厚度TH1，第二子无机封装层712在垂直于驱动基板510的方向上具有第二厚度TH2，第三子无机封装层713在垂直于驱动基板510的方向上具有第三厚度TH3，第四子无机封装层714在垂直于驱动基板510的方向上具有第四厚度TH4，第一厚度TH1大于第二厚度TH2，第二厚度TH2大于第三厚度TH3，第三厚度TH3大于第四厚度TH4。也就是说，在远离驱动基板510的方向上，各个子无机封装层的厚度逐渐减小。
在一些示例中，如图8所示，第一厚度TH1与第二厚度TH2的差值和第三厚度TH3与第四厚度TH4的差值的比例范围为1.5-2倍；也就是说，第一厚度TH1、第二厚度TH2、第三厚度TH3和第四厚度TH4满足以下公式：TH1-TH2＝m*(TH3-TH4)，m的取值范围为1.2-2。由此，该显示基板可更好地避免相邻子像素产生串扰。
在一些示例中，如图8所示，第二厚度TH2和第三厚度TH3之和与第一厚度TH1的比例范围为0.8-1.2；也就是说，第一厚度TH1、第二厚度TH2和第三厚度TH3满足以下公式：(TH2+TH3)＝n*TH1，n的取值范围为0.8- 1.2。由此，该显示基板可更好地避免相邻子像素产生串扰。
在一些示例中，如图8所示，第一厚度的范围为1000-1200纳米，第二厚度的范围为500-660纳米，第三厚度的范围480-560纳米，第四厚度的范围为180-260纳米。
在一些示例中，第一子无机封装层的材料包括氧化硅或氮氧化硅，第二子无机封装层的材料包括氮化硅，第三子无机封装层的材料包括氮化硅，第四子无机封装层的材料包括氧化硅。当然，本公开实施例包括但不限于此，各个子无机封装层的材料也可为其他合适的材料。
在一些示例中，第一厚度为1100纳米，第二厚度的范围为580纳米，第三厚度的范围520纳米，第四厚度的范围为220纳米。当然，本公开实施例包括但不限于此，各个子无机封装层的厚度还可为其他数值。
在一些示例中，如图8所示，封装层560还包括有机封装层720，有机封装层720位于无机封装层710远离驱动基板510的一侧。有机封装层720包括第一区域7201、第二区域7202和第三区域7203，第一区域7201的平均厚度小于第二区域7202的平均厚度，第二区域7202的平均厚度小于第三区域7203的平均厚度。由此，该有机封装层可更好地与后续形成的具有不同厚度的彩膜片进行匹配。
在一些示例中，如图8所示，该显示基板500还包括彩膜层570，彩膜层570位于封装层560远离驱动基板510的一侧；彩膜层570包括第一彩色滤光片571、第二彩色滤光片572和第三彩色滤光片573。
例如，第一彩色滤光片571、第二彩色滤光片572和第三彩色滤光片573可为不同颜色的彩色滤光片。
例如，第一彩色滤光片571、第二彩色滤光片572和第三彩色滤光片573可分别具有不同的厚度。当然，本公开实施例包括但不限于此。
在一些示例中，如图8所示，第一彩色滤光片571和第二彩色滤光片572存在第一交叠区OP1，第二彩色滤光片572和第三彩色滤光片573存在第二交叠区OP2，第三彩色滤光片573和第一彩色滤光片571存在第三交叠区OP3。当两个不同颜色的滤光片产生交叠时，交叠区的光透过率较低，因此可作为黑矩阵进行使用。由此，该显示基板的第一交叠区、第二交叠区和第三交叠区均可作为黑矩阵使用，起到遮光的效果。当然，本公开实施例包括但不限于此，相邻的彩色滤光片也可不交叠，额外在相邻的彩色滤光片之间形 成黑矩阵。
在一些示例中，如图8所示，第一交叠区OP1、第二交叠区OP2和第三交叠区OP3在驱动基板510上的正投影与相邻两个阳极525之间的间隔区522在驱动基板510上的正投影交叠，从而可作为黑矩阵使用，起到遮光的效果。需要说明的是，图8所示的显示基板仅采用了两个彩色滤光片进行交叠的方式来形成相当于黑矩阵的交叠区，但是本公开实施例提供的显示基板还可采用三个彩色滤光片进行交叠的方式来形成相当于黑矩阵的交叠区。
在一些示例中，如图8所示，第一交叠区OP1、第二交叠区OP2和第三交叠区OP3在驱动基板510上的正投影与凸起部525B在驱动基板510上的正投影交叠。
在一些示例中，如图8所示，第一交叠区OP1在第二方向上的尺寸大于第二交叠区OP2在第二方向上的尺寸，第二交叠区OP2在第二方向上的尺寸大于第三交叠区OP3在第二方向上的尺寸。
在一些示例中，如图8所示，第一交叠区OP1在第二方向上的尺寸范围为400-600纳米，第二交叠区OP2在第二方向上的尺寸范围为250-350纳米，第三交叠区OP3在第二方向上的尺寸范围为100-200纳米。
在一些示例中，如图8所示，第一彩色滤光片571在垂直于驱动基板510的方向上的平均尺寸大于第二彩色滤光片572在垂直于驱动基板510的方向上的平均尺寸，且小于第三彩色滤光片573在垂直于驱动基板510的方向上的平均尺寸。需要说明的是，上述的平均尺寸是指彩色滤光片上各个部分在垂直于驱动基板的方向上的尺寸的算术平均值。
在一些示例中，如图8所示，第一彩色滤光片571在垂直于驱动基板510的方向上的平均尺寸的范围为2.3-2.6微米，第二彩色滤光片572在垂直于驱动基板510的方向上的平均尺寸的范围为1.7-1.95微米，第三彩色滤光片573在垂直于驱动基板510的方向上的平均尺寸的范围为2.3-2.7微米。
在一些示例中，如图8所示，第一彩色滤光片571在垂直于驱动基板510的方向上的平均尺寸与第二彩色滤光片572在垂直于驱动基板510的方向上的平均尺寸的差值和第一彩色滤光片571在垂直于驱动基板510的方向上的平均尺寸与第三彩色滤光片573在垂直于驱动基板510的方向上的平均尺寸的差值之比的范围为2-3。
图9为本公开一实施例提供的一种显示基板中的第一彩色滤光片的示意 图。如图8和图9所示，第一彩色滤光片571包括第一边缘部571A、第二边缘部571B和位于第一边缘部571A和第二边缘部571B之间的中间部571C，中间部571C在垂直于驱动基板510的方向上的平均尺寸小于第一边缘部571A在垂直于驱动基板510的方向上的平均尺寸和第二边缘部571B在垂直于驱动基板510的方向上的平均尺寸。
在一些示例中，如图8所示，第一彩色滤光片571包括与第二彩色滤光片572接触的第一接触面571C，第二彩色滤光片572包括与第三彩色滤光片573接触的第二接触面572C，第三彩色滤光片573包括与第一彩色滤光片571接触的第三接触面573C，第一接触面571C在垂直于驱动基板510的第一方向上的尺寸与第二接触面572C在第一方向上的尺寸相等，且小于第三接触面573C在第一方向上的尺寸。
在一些示例中，如图8所示，第一彩色滤光片571与驱动基板510远离阳极层520的表面的距离大于第三彩色滤光片573与驱动基板510远离阳极层520的表面的距离，且小于第二彩色滤光片572与驱动基板510远离阳极层520的表面的距离。
在一些示例中，如图8所示，第一彩色滤光片为红色滤光片，第二彩色滤光片为绿色滤光片，第三彩色滤光片为蓝色滤光片。当然，本公开实施例包括但不限于此，第一彩色滤光片、第二彩色滤光片和第三彩色滤光片也可为其他颜色的彩色滤光片。
在一些示例中，彩膜层570的材料包括干燥剂，从而可起到防止外界水氧进入彩膜层下方的膜层的效果。
在一些示例中，彩膜层570包括铝元素。
在一些示例中，如图8所示，该显示基板500还包括保护层580，位于彩膜层570远离驱动基板510的一侧。保护层580可以起到保护彩膜层570的效果，使得彩膜层570的滤光性能在长期使用过程中保持稳定，从而可提高显示基板的显示质量。
在一些示例中，如图8所示，该显示基板500还包括玻璃盖板590，位于彩膜层570远离驱动基板510的一侧。
在一些示例中，如图8所示，第一子无机封装层711的平坦区PTQ在第二方向上具有第一宽度，第二子无机封装层712的平坦区PTQ在第二方向上具有第二宽度，第三子无机封装层713的平坦区PTQ在第二方向上具有第三 宽度，第四子无机封装层714的平坦区PTQ在第二方向上具有第四宽度，第一宽度大于第二宽度，第二宽度大于第三宽度，第三宽度大于第四宽度。也就是说，第一宽度、第二宽度、第三宽度和第四宽度逐渐减小。
图10为本公开一实施例提供的另一种显示基板的局部结构示意图。如图8和图10所示，第一子无机封装层711的平坦区PTQ靠近第二拱形区GX2的边缘、第二子无机封装层712的平坦区PTQ靠近第二拱形区GX2的边缘、第三子无机封装层713的平坦区PTQ靠近第二拱形区GX2的边缘和第四子无机封装层714的平坦区PTQ靠近第二拱形区GX2的边缘的第一连线L1与驱动基板510远离阳极层520的表面之间的夹角为第一夹角；第一子无机封装层711的第二拱形区GX2的顶点、第二子无机封装层712的第一拱形区GX1的顶点、第三子无机封装层713的第二拱形区GX2的顶点和第四子无机封装层714的第二拱形区GX2的顶点的第二连线L2与驱动基板510远离阳极层520的表面之间的夹角为第二夹角，第一夹角小于第二夹角。
在一些示例中，如图8和图10所示，第一夹角的范围为60-85度，第二夹角的范围为85-89度。
在一些示例中，如图8和图10所示，第一连线L1和第二连线的L2交点位于驱动基板510之内。
图11为本公开一实施例提供的一种驱动基板的结构示意图。如图11所示，该驱动电路514包括半导体层102、第一导电层301、第二导电层302、第三导电层303和第四导电层304；半导体层102位于衬底512之中；第一导电层301位于半导体层102上；第二导电层302位于第一导电层301远离衬底512的一侧；第三导电层303位于第二导电层302远离衬底512的一侧；第四导电层304第三导电层303远离衬底512的一侧。
在一些示例中，如图11所示，第一连线L1和第二连线L2的交点位于第三导电层303远离衬底512的上表面与阳极层520之间。
在一些示例中，如图11所示，第一连线L1与第二连线L2的交点与像素限定层530的突起结构535远离衬底512的上表面的顶点之间距离大于第一子无机封装层711在第一方向上的厚度。
在一些示例中，如图11所示，第一连线L1与第二连线L2的交点与像素限定层530的突起结构535远离衬底512的上表面的顶点之间距离小于第一子无机封装层711在第一方向上的厚度和第二子无机封装层712在第一方向 上的厚度之和。
在一些示例中，如图11所示，第一子无机封装层711的第二拱形区GX2靠近双拱间隔区JGQ的边缘、第二子无机封装层712的第二拱形区GX2靠近双拱间隔区JGQ的边缘、第三子无机封装层713的第二拱形区GX2靠近双拱间隔区JGQ的边缘和第四子无机封装层714的第二拱形区GX2靠近双拱间隔区JGQ的边缘的第三连线L3与驱动基板510远离阳极层520的表面之间的夹角为第三夹角，第三夹角小于第二夹角。
在一些示例中，如图11所示，第一连线L1和第三连线L3的交点位于第二导电层302远离衬底512的上表面与第三导电层303靠近衬底512的下表面之间。
在一些示例中，如图11所示，第二连线L2和第三连线L3的交点位于第一导电层301靠近衬底512的下表面与衬底512远离第一导电层301的下表面之间。
在一些示例中，如图11所示，第一子无机封装层711的第三拱形区GX3远离双拱间隔区JGQ的边缘、所述第二子无机封装层712的第三拱形区GX3远离双拱间隔区JGQ的边缘、所述第三子无机封装层713的第三拱形区GX3远离双拱间隔区JGQ的边缘和所述第四子无机封装层714的第三拱形区GX3远离双拱间隔区JGQ的边缘的第四连线L4与驱动基板510远离阳极层520的表面之间的夹角为第四夹角，第四夹角小于第二夹角。
在一些示例中，如图11所示，第一连线L1与第四连线L4的交点位于衬底512远离第一导电层301的一侧。
在一些示例中，如图11所示，第三连线L3与第四连线L4的交点位于第二导电层302远离衬底512的上表面与第三导电层303靠近衬底512的下表面之间。
图12为本公开一实施例提供的一种显示基板的局部结构示意图。如图12所示，彩膜层570还包括黑矩阵574，位于第一彩色滤光片571、第二彩色滤光片572和第三彩色滤光片573中任意相邻的两个之间。
在一些示例中，如图12所示，黑矩阵574在驱动基板510上的正投影与相邻两个阳极525之间的间隔区522在驱动基板510上的正投影交叠。
在一些示例中，如图12所示，该显示基板500还包括保护层580，位于彩膜层570远离驱动基板510的一侧。保护层580可以起到保护彩膜层570 的效果，使得彩膜层570的滤光性能在长期使用过程中保持稳定，从而可提高显示基板的显示质量。
在一些示例中，如图12所示，该显示基板500还包括玻璃盖板590，位于彩膜层570远离驱动基板510的一侧。
本公开一实施例还提供一种显示装置，包括上述任一项所述的显示基板。图13为本公开一实施例提供的一种显示装置的示意图。如图13所示，该显示装置900包括上述的显示基板500。由此，该显示装置具有与显示基板的有益技术效果对应的技术效果。
例如，在该显示基板中，由于阳极包括主体部和凸起部，并且凸起部在垂直于驱动基板的方向上的尺寸大于主体部在垂直于驱动基板的方向上的尺寸，因此位于两个阳极之间，且与阳极的边缘部分交叠的像素限定层可形成与凸起部对应的突起结构。在形成发光功能层时，发光功能层中的至少部分子功能层(例如电荷产生层)可更好地在突起结构所在的位置断开，即相邻两个阳极对应的发光部中的至少部分子功能层不连接，从而可有效地避免相邻子像素之间的漏电和串扰。另一方面，此时的像素限定层的突起结构的高度也更高，从而可更好地起到像素限定的作用，从光学上减少和避免相邻子像素之间的串扰。由此，该显示基板也可减少甚至避免相邻子像素之间的串扰，因而具有较好的显示品质。
又例如，由于显示基板中的驱动基板可采用半导体制作工艺进行制作，从而可将用于驱动各个像素进行发光和显示的像素驱动电路集成在驱动基板之中。由此，该显示装置可提供一种微型的显示装置，并具有分辨率高、亮度高、色彩丰富、驱动电压低、响应速度快、功耗低等优点。
例如，该显示装置900可为可穿戴显示装置，例如智能手表、智能眼镜等。当然，本公开实施例包括但不限于此，该显示装置也可为其他具有显示功能的电子产品，例如手机、电视、导航仪、电子相册、电子画框、电脑显示器等。
图14为本公开一实施例提供的一种显示装置的平面图。如图14所示，该显示装置900包括显示区910和位于显示区910周围的周边区920；该显示装置900的周边区920包括走线区930。显示区910可用于进行发光显示，而走线区930可用于将各种驱动线或者信号线从显示区910引出。
图15为本公开一实施例提供的另一种显示装置的示意图。如图15所 示，该显示装置900包括的显示基板500不包括彩膜层。此时，该显示装置900还包括对置基板800，对置基板800与显示基板500相对设置；对置基板800包括玻璃盖板810和位于玻璃盖板810上的彩膜层570，彩膜层570包括第一彩色滤光片571、第二彩色滤光片572和第三彩色滤光片573。由此，可先分别制作显示基板和对置基板，然后再将显示基板和对置基板对准，从而形成上述的显示装置。并且，该显示装置具有与显示基板的有益技术效果对应的技术效果。
例如，在该显示基板中，由于阳极包括主体部和凸起部，并且凸起部在垂直于驱动基板的方向上的尺寸大于主体部在垂直于驱动基板的方向上的尺寸，因此位于两个阳极之间，且与阳极的边缘部分交叠的像素限定层可形成与凸起部对应的突起结构。在形成发光功能层时，发光功能层中的至少部分子功能层(例如电荷产生层)可更好地在突起结构所在的位置断开，即相邻两个阳极对应的发光部中的至少部分子功能层不连接，从而可有效地避免相邻子像素之间的漏电和串扰。另一方面，此时的像素限定层的突起结构的高度也更高，从而可更好地起到像素限定的作用，从光学上减少和避免相邻子像素之间的串扰。由此，该显示基板也可减少甚至避免相邻子像素之间的串扰，因而具有较好的显示品质。
又例如，由于显示基板中的驱动基板可采用半导体制作工艺进行制作，从而可将用于驱动各个像素进行发光和显示的像素驱动电路集成在驱动基板之中。由此，该显示装置可提供一种微型的显示装置，并具有分辨率高、亮度高、色彩丰富、驱动电压低、响应速度快、功耗低等优点。
例如，该显示装置900可为可穿戴显示装置，例如智能手表、智能眼镜等。当然，本公开实施例包括但不限于此，该显示装置也可为其他具有显示功能的电子产品，例如手机、电视、导航仪、电子相册、电子画框、电脑显示器。
在一些示例中，如图15所示，第一彩色滤光片571和第二彩色滤光片572存在第一交叠区OP1，第二彩色滤光片572和第三彩色滤光片573存在第二交叠区OP2，第三彩色滤光片573和第一彩色滤光片571存在第三交叠区OP3。当两个不同颜色的滤光片产生交叠时，交叠区的光透过率较低，因此可作为黑矩阵进行使用。由此，该显示基板的第一交叠区、第二交叠区和第三交叠区均可作为黑矩阵使用，起到遮光的效果。当然，本公开实施例包括但 不限于此，相邻的彩色滤光片也可不交叠，额外在相邻的彩色滤光片之间形成黑矩阵。
在一些示例中，如图15所示，第一交叠区OP1、第二交叠区OP2和第三交叠区OP3在驱动基板510上的正投影与相邻两个阳极525之间的间隔区522在驱动基板510上的正投影交叠。需要说明的是，图14所示的显示基板仅采用了两个彩色滤光片进行交叠的方式来形成相当于黑矩阵的交叠区，但是本公开实施例提供的显示基板还可采用三个彩色滤光片进行交叠的方式来形成相当于黑矩阵的交叠区。
在一些示例中，如图15所示，第一交叠区OP1在第二方向上的尺寸大于第二交叠区OP2在第二方向上的尺寸，第二交叠区OP2在第二方向上的尺寸大于第三交叠区OP3在第二方向上的尺寸。
在一些示例中，如图15所示，第一交叠区OP1在第二方向上的尺寸范围为400-600纳米，第二交叠区OP2在第二方向上的尺寸范围为250-350纳米，第三交叠区OP3在第二方向上的尺寸范围为100-200纳米。
在一些示例中，如图15所示，第一彩色滤光片571在垂直于驱动基板510的方向上的平均尺寸大于第二彩色滤光片572在垂直于驱动基板510的方向上的平均尺寸，且小于第三彩色滤光片573在垂直于驱动基板510的方向上的平均尺寸。
在一些示例中，如图15所示，第一彩色滤光片571在垂直于驱动基板510的方向上的平均尺寸的范围为2.3-2.6微米，第二彩色滤光片572在垂直于驱动基板510的方向上的平均尺寸的范围为1.7-1.95微米，第三彩色滤光片573在垂直于驱动基板510的方向上的平均尺寸的范围为2.3-2.7微米。
在一些示例中，如图15所示，第一彩色滤光片571在垂直于驱动基板510的方向上的平均尺寸与第二彩色滤光片572在垂直于驱动基板510的方向上的平均尺寸的差值和第一彩色滤光片571在垂直于驱动基板510的方向上的平均尺寸与第三彩色滤光片573在垂直于驱动基板510的方向上的平均尺寸的差值之比的范围为2-3。
在一些示例中，如图10和图15所示，第一彩色滤光片571包括第一边缘部571A、第二边缘部571B和位于第一边缘部571A和第二边缘部571B之间的中间部571M，中间部571M在垂直于驱动基板510的方向上的平均尺寸小于第一边缘部571A在垂直于驱动基板510的方向上的平均尺寸和第二边缘 部571B在垂直于驱动基板510的方向上的平均尺寸。
在一些示例中，如图15所示，第一彩色滤光片571包括与第二彩色滤光片572接触的第一接触面571C，第二彩色滤光片572包括与第三彩色滤光片573接触的第二接触面572C，第三彩色滤光片573包括与第一彩色滤光片571接触的第三接触面573C，第一接触面在垂直于驱动基板510的第一方向上的尺寸与第二接触面在第一方向上的尺寸相等，且小于第三接触面在第一方向上的尺寸。
在一些示例中，如图15所示，第一彩色滤光片571与驱动基板510远离阳极层520的表面的距离大于第三彩色滤光片573与驱动基板510远离阳极层520的表面的距离，且小于第二彩色滤光片572与驱动基板510远离阳极层520的表面的距离。
在一些示例中，如图15所示，第一彩色滤光片为红色滤光片，第二彩色滤光片为绿色滤光片，第三彩色滤光片为蓝色滤光片。当然，本公开实施例包括但不限于此，第一彩色滤光片、第二彩色滤光片和第三彩色滤光片也可为其他颜色的彩色滤光片。
在一些示例中，彩膜层570的材料包括干燥剂，从而可起到防止外界水氧进入彩膜层下方的膜层的效果。
在一些示例中，彩膜层570包括铝元素。
本公开至少一个实施例还提供一种显示基板。图16为本公开一实施例提供的一种显示基板的平面示意图。如图16所示，该显示装置900包括设置在显示区域910中的呈阵列排布的多个像素单元PU，例如，该多个像素单元PU中的至少一个可以包括一个上述的驱动电路和一个上述的阳极。
例如，如图16所示，该显示装置900还包括制备在衬底中的行驱动电路200，该行驱动电路200被配置为向显示装置900中的多个像素单元PU中的驱动电路提供第一扫描信号SCAN1、第二扫描信号SCAN2以及发光控制信号EN。例如，该行驱动电路200设置在围绕显示区域910的周边区域920中。
本公开至少一个实施例还提供一种显示基板。图17为本公开一实施例提供的一种显示基板的局部剖面示意图。如图17所示，该显示基板500包括驱动基板510，该驱动基板510包括驱动电路514，该驱动电路514与阳极525电连接，以用于与阳极525接触的发光功能层540发光。需要说明的是，图 17所示的显示基板中阳极、发光功能层、封装层等结构可采用上述实施例提供的显示基板中的相关设计。
例如，如图17所示，该驱动基板510包括晶体管T，晶体管T包括栅电极G、源电极S和漏电极D。三个电极分别对应三个电极连接部。例如，栅电极G与栅电极连接部610g电连接，源电极S与源电极连接部610s电连接，漏电极D与漏电极连接部610d电连接。例如，三个电极均是通过钨过孔605与三个电极连接部对应电连接。
例如，如图17所示，源电极连接部610s通过钨过孔与阳极525电连接。例如，源电极连接部610s通过钨过孔与金属反射层593电连接，同时，阳极525通过无机绝缘层624中的过孔624a与金属反射层593电连接。在晶体管T处于导通状态，由电源线提供的电信号可经过晶体管T的源电极S、源电极连接部610s、金属反射层593传输到阳极525。由于阳极525与阴极550之间形成电压差，在二者之间形成电场，空穴和电子被注入到发光功能层540中，发光功能层540在该电场作用下发光。可以理解的是，晶体管T中，源电极S和漏电极D的位置可互换(对应地，源电极连接部610s和漏电极连接部610d的位置也可互换)。
例如，栅电极连接部610g、源电极连接部610s和漏电极连接部610d的材料可以包括金属材料。例如，如图17所示，在栅电极连接部610g、源电极连接部610s和漏电极连接部610d每个的至少一侧(例如上侧和/或下侧)可以设置抗氧化层607，这样能有效防止这些电极连接部被氧化，提高其导电性能。
例如，如图17所示，该显示基板500还包括用于限定发光功能层540的像素限定层530，该像素限定层530将有机发光功能层540限定在其像素开口535中，避免彼此相邻的子像素之间的串扰。
需要说明的是，在图17所示的显示基板500中，无机绝缘层624中的过孔624a可以设置在阳极525与金属反射层593的边缘区域之间。例如，在一些示例中，发光功能层540在驱动基板510上的正投影和过孔624a在驱动基板510上的正投影均位于金属反射层593在驱动基板510上的正投影内，同时，发光功能层540在驱动基板510上的正投影和过孔624a在驱动基板510上的正投影之间不存在交叠，从而金属反射层对发光功能层540发出的光进行反射时，过孔624a对该反射过程基本没有影响。
图18为本公开一实施例提供的一种显示基板中驱动电路的等效示意图；图19为本公开一实施例提供的一种显示基板中驱动电路的平面示意图。如图18和图19所示，该驱动电路514包括驱动晶体管140、第一晶体管110、第二晶体管120以及第三晶体管130。需要说明的是，在一些实施例中，驱动电路也可以不包括第三晶体管130，本公开的实施例对此不作限定。
例如，驱动晶体管140包括控制极143、第一极141和第二极142，且该驱动晶体管140被配置为根据驱动晶体管140的控制极143的电压，控制流经驱动晶体管140的第一极141和驱动晶体管140的第二极142的用于驱动发光元件LE发光的驱动电流。发光元件LE可以根据驱动电流的大小发出不同强度的光。
需要说明的是，本公开的实施例中采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开的实施例中所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。以下各实施例以晶体管的第一极为漏极，第二极为源极为例进行说明，不再赘述。
例如，第一晶体管110连接到驱动晶体管140的控制极143，且被配置为响应于第一扫描信号SCAN1将数据信号DATA写入驱动晶体管140的控制极143。
例如，第二晶体管120连接到驱动晶体管140的控制极143，且被配置为响应于第二扫描信号SCAN2将数据信号DATA写入驱动晶体管140的控制极143。
例如，第三晶体管130连接到驱动晶体管140的第一极141，且被配置为响应于发光控制信号EN将第一电源电压ELVDD施加到驱动晶体管140的第一极141。例如，本公开的实施例中的第一电源电压ELVDD为高电平电压，例如，第一电源电压ELVDD为5V。
如图18所示，在一些实施例中，第一晶体管110的第一极111(例如，漏极)以及第二晶体管120的第一极121(例如，漏极)连接以得到公共电极，并通过该公共电极与驱动晶体管140的控制极143连接。
在上述实施例中，还提供了第一扫描信号线SL1、第二扫描信号线SL2、数据线DL、第一电源电压线VL1以及发光控制线EL等以提供相应的电信号。第一晶体管110的控制极113被配置为从第一扫描信号线SL1接收第一扫描信号SCAN1，第一晶体管110的第二极112(例如，源极)被配置为从数据线DL接收数据信号DATA。第二晶体管120的控制极123被配置为从第二扫描信号线SL2接收第二扫描信号SCAN2，第二晶体管120的第二极122(例如，源极)被配置为从数据线DL接收数据信号DATA。第三晶体管130的控制极133被配置为从发光控制线EL接收发光控制信号EN，第三晶体管130的第一极131(例如，漏极)被配置为从第一电源电压线VL1接收第一电源电压ELVDD，第三晶体管130的第二极132(例如，源极)和驱动晶体管140的第一极141(例如，漏极)连接。
驱动晶体管140的第二极142(例如，源极)被配置为和发光元件LE的第一极连接。例如，当发光元件LE为OLED时，驱动晶体管140的第二极142可以和该OLED的阳极连接。例如，该发光元件LE的第二极被配置为接收第四电源电压VCOM。例如，本公开的实施例中的第四电源电压VCOM为低电平电压。
例如，在本公开的实施例中，发光元件LE可以采用OLED，当多个像素单元构成显示面板中的像素阵列时，多个像素单元中的多个发光元件OLED的第二极(例如，阴极)可以电连接在一起，例如分别连接到同一个电极或一体形成，以接收第四电源电压VCOM，即多个像素单元中的多个发光元件OLED采用共阴极连接方式。
例如，发光元件OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图18所示，驱动电路还包括存储电容CST，以存储写入到驱动晶体管140的控制极143的数据信号DATA，从而使得驱动晶体管140可以根据该存储的数据信号DATA的电压控制驱动发光元件LE的驱动电流的大小。存储电容CST的第一极和驱动晶体管140的控制极143连接，存储电容CST的第二极被配置为接收第三电源电压AVSS。例如，本公开的实施例中的第三电源电压AVSS为低电平电压。需要说明的是，在本公开的实施例中，第三电源电压AVSS可以和第四电源电压VCOM相同，例如，第三电源电压AVSS可以和第四电源电压VCOM均接地，本公开的实施例包括但不限于 此。
如图18所示，在本公开的一些实施例中，第一晶体管110可以采用P型MOS晶体管，第二晶体管120、第三晶体管130以及驱动晶体管140可以采用N型MOS晶体管，例如，第一晶体管110、第二晶体管120、第三晶体管130以及驱动晶体管140形成在衬底中。
例如，如图18所示，第一晶体管110的第三级被配置为接收第二电源电压VDD，例如，第一晶体管110的第三级和第二电源电压线VL2连接以接收第二电源电压VDD。
例如，第二晶体管120、第三晶体管130以及驱动晶体管140的第三极被配置为接地(GND)。需要说明的是，在本公开的实施例中，一个晶体管的第三极为与该晶体管的控制极(栅极)113相对的一极，以下各实施例与此相同，不再赘述。
在本公开的实施例中，由于第一晶体管110和第二晶体管120采用具有相反半导体型的MOS晶体管，所以第一晶体管110和第二晶体管120可以构成具有互补特性的传输门开关。在这种情形中，例如，可以使得提供至第一晶体管110的第一扫描信号SCAN1和提供至第二晶体管120的第二扫描信号SCAN2彼此互为反相信号，这样就可以保证第一晶体管110和第二晶体管120在同一时刻总有一个处于导通状态，从而可以没有电压损失地将数据信号DATA传输至存储电容CST，从而可以提高该驱动电路的可靠性和稳定性。
如图19所示，在本公开的实施例中，将沿第一晶体管110的第一极111至第一晶体管110的第二极112的方向称为第一方向D1，将沿第二晶体管120的第一极121至第二晶体管120的第二极122的方向称为第二方向D2，将沿第三晶体管130的第一极131至第三晶体管130的第二极132的方向称为第三方向D3，将沿驱动晶体管140的第一极141至驱动晶体管140的第二极142的方向称为第四方向D4。需要说明的是，图1-图15中的第一方向与本实施例提供的第一方向不同，图1-图15中的第二方向与本实施例提供的第二方向可以相同，也可以不同。
例如，第一方向D1和第二方向D2中的至少一个和第四方向D4相交。例如，在驱动电路包括第三晶体管130的情形下，第一方向D1、第二方向D2以及第三方向D3中的至少一个和第四方向D4相交。例如，第四方向D4为图19中从左至右的横向方向。
在驱动电路中，由于驱动晶体管140的尺寸相对于其它开关晶体管(例如，第一晶体管110、第二晶体管120以及第三晶体管130)一般较大，所以在布局晶体管的位置时，可以将该驱动晶体管140沿第四方向D4布置，同时使得第一方向D1、第二方向D2以及第三方向D3中的至少一个和第四方向D4相交，这样可以使得四个晶体管的布局更紧凑，从而可以减小该显示基板500所占用的布局面积，从而可以使得该显示基板500更易于实现高PPI。
在本公开的一些实施例中，可以使得第一方向D1和第二方向D2均和第四方向D4相交；又例如，可以使得第一方向D1、第二方向D2以及第三方向D3均和第四方向D4相交。例如，如图19所示，第四方向D4为横向方向，第一方向D1、第二方向D2以及第三方向D3均为图3中的与横向方向垂直的纵向方向。
例如，在本公开的一些实施中，第一方向D1和第二方向D2均和第四方向D4垂直；又例如，第一方向D1、第二方向D2以及第三方向D3均和第四方向D4垂直。对于显示装置的显示区域中的多个像素单元按照多行多列方式排布的情形，采用这种方式可以使得该显示基板500的布局更紧凑，从而可以进一步减小该显示基板500所占用的布局面积，从而可以使得该显示基板500更易于实现高PPI。
例如，如图19所示，第一晶体管110包括沿第一方向D1延伸的第一有源区114，第一有源区114包括第一晶体管110的第一极111、第一晶体管110的第二极112、以及第一晶体管110的第一极111和第一晶体管110的第二极112之间形成的沟道区。
第二晶体管120包括沿第二方向D2延伸的第二有源区124，第二有源区124包括第二晶体管120的第一极121、第二晶体管120的第二极122、以及第二晶体管120的第一极121和第二晶体管120的第二极122之间形成的沟道区。
第三晶体管130包括沿第三方向D3延伸的第三有源区134，第三有源区134包括第三晶体管130的第一极131、第三晶体管130的第二极132、以及第三体管130的第一极131和第三晶体管130的第二极132之间形成的沟道区。
驱动晶体管140包括沿第四方向D4延伸的第四有源区144，第四有源区144包括第四晶体管140的第一极141、第四晶体管140的第二极142、以及 第四体管140的第一极141和第四晶体管140的第二极142之间形成的沟道区。
例如，本公开的实施例提供的显示基板500中的衬底为硅基衬底，上述第一有源区114、第二有源区124、第三有源区134和第四有源区144均为硅基衬底中的掺杂区，这些掺杂区例如通过离子注入工艺或离子扩散工艺得到，对于非晶硅，P型掺杂可以通过掺杂硼(B)实现，N型掺杂可以通过掺杂磷(P)或砷(As)实现，本公开的实施例对此不作限制。
例如，在本公开的一些实施例中，第一有源区114与第二有源区124的掺杂类型相反。例如，第一有源区114的掺杂类型为P型，第二有源区124的掺杂类型为N型。
如图19所示，第一有源区114的两个端部和第二有源区124的两个端部在第四方向D4上彼此对齐，并且例如，第一有源区114的两个端部和第二有源区124彼此相邻布置。采用这种方式可以简化该显示基板500的布局设计。
第一有源区114沿第一方向D1的一个边缘与第二有源区124沿第二方向D2的一个边缘的连线和第四方向D4平行；第一有源区114沿第一方向D1的另一个边缘与第二有源区124沿第二方向D2的另一个边缘的连线和第四方向D4平行。采用这种方式可以简化该显示基板500的布局设计。
与用于非显示用途的硅基模拟CMOS电路相比，本公开的实施例提供的显示基板500中的用于发光元件LE的驱动电流要小1到2个数量级。驱动晶体管140在饱和状态下的电流特性为：
Figure PCTCN2022102336-appb-000001
其中，I D为驱动晶体管140提供的驱动电流，W/L为驱动晶体管140的宽长比，K为一常数值，V GS4为驱动晶体管140的栅极和源极之间的电压差，V th为驱动晶体管140的阈值电压。
由上面的公式可以看出，要实现较低的驱动电流，则驱动晶体管140在尺寸设计时就要增大L值，这不利于减小采用该驱动晶体管140的显示基板500的布局面积。
本公开的一些实施例提供的驱动电路514通过对第一有源区114、第二有源区124、第三有源区134以及第四有源区144的掺杂浓度之间的相对关系 进行调整，可以改善或避免上述问题。
例如，第四有源区144的掺杂浓度小于第三有源区134的掺杂浓度。例如，第三有源区134的掺杂浓度约为10 17cm -3，第四有源区144的掺杂浓度约为10 13cm -3，第四有源区144的掺杂浓度比第三有源区134的掺杂浓度小4个数量级。本公开的实施例通过降低第四有源区144的掺杂浓度，在不改变驱动晶体管140的尺寸(例如，宽长比W/L不变)的情形下，可以使得驱动晶体管140输出更小的驱动电流，输出的驱动电流的变化更平缓，从而使得采用该驱动晶体管140的驱动电路驱动发光元件LE(例如，OLED)进行发光时的灰阶值可以获得较好的均匀性。
例如，在本公开的一些实施例提供的显示基板500中，第一有源区114以及第二有源区124中的至少一个的掺杂浓度大于第三有源区134的掺杂浓度。
例如，第一有源区114以及第二有源区124的掺杂浓度均大于第三有源区的掺杂浓度。例如，第一有源区114以及第二有源区124的掺杂浓度约为10 20cm -3，在这种情形下，第一有源区114以及第二有源区124的掺杂浓度比第三有源区134的掺杂浓度大3个数量级。
如图18所示，第一晶体管110和第二晶体管120在驱动电路里是用作开关晶体管的，所以需要具有良好的开关特性。当第一有源区114或/和第二有源区124的掺杂浓度较大时，可以获得较大的驱动电流且该驱动电流的变化更快速，从而使得该第一晶体管110或/和第二晶体管120具有更好的开关特性。
例如，在本公开的实施例中，第一晶体管110为第一半导体型MOS晶体管，第二晶体管、第三晶体管以及驱动晶体管均为第二半导体型MOS晶体管，第一半导体型和第二半导体型相反。例如，第一半导体型为P型，第二半导体型为N型，本公开的实施例包括但不限于此。
如图19所示，本公开的一些实施例提供的显示基板500还包括用于传输第一扫描信号SCAN1的第一扫描信号线SL1以及用于传输第二扫描信号SCAN2的第二扫描信号线SL2，第一扫描信号线SL1与第二扫描信号线SL2平行设置。
例如，第一扫描信号线SL1和第一晶体管110的控制极113连接以提供第一扫描信号SCAN1，第二扫描信号线SL2和第二晶体管120的控制极123 连接以提供第二扫描信号SCAN2。
例如，第一扫描信号线SL1以及第二扫描信号线SL2的延伸方向均与第四方向D4平行。第一扫描信号线SL1在衬底的正投影与第二扫描信号线SL2在衬底的正投影平行，例如，均和第四方向D4平行。
例如，驱动电路514在衬底512的正投影所在的区域为像素区域，第一扫描信号线SL1和第二扫描信号线SL2并列位于像素区域的一侧。
如图19所示，本公开的一些实施例提供的显示基板500还包括用于传输数据信号DATA的数据线DL，第二扫描信号线SL2在衬底的正投影与数据线DL在衬底的正投影至少部分重叠。例如，第二扫描信号线SL2与数据线DL在垂直于衬底的方向上重叠。例如，如图19所示，可以把图19所在的平面看做衬底所在的平面，则垂直于衬底即垂直于图19所在的平面。本公开的实施例通过使得第二扫描信号线SL2与数据线DT在垂直于衬底的方向上重叠，可以使得该数据线DL不占用额外的布局面积，从而可以进一步减小该显示基板500所占用的布局面积，更有利于实现高PPI。
如图19所示，本公开的一些实施例提供的显示基板500还包括用于传输第一电源电压ELVDD的第一电源电压线VL1以及用于传输发光控制信号EN的发光控制线EL。
例如，第一电源电压线VL1和发光控制线EL的部分延伸方向与第四方向D4平行，第一扫描信号线SL1、第二扫描信号线SL2、第一电源电压线VL1以及发光控制线EL在衬底的正投影沿与第四方向D4的垂直方向依次排布。
需要说明的是，在本公开的一些实施例提供的显示基板500中，如图19所示，使得第一电源电压线VL1在衬底的正投影位于第二扫描信号线SL2在衬底的正投影和发光控制线EL在衬底的正投影之间，由于第一电源电压线VL1传输的第一电源电压ELVDD为直流信号，而第二扫描信号线SL2传输的第二扫描信号SCAN2以及发光控制线EL传输的发光控制信号EN均为跳变信号，所以采用上述排布方式可以有效屏蔽第二扫描信号SCAN2与发光控制信号EN之间的相互干扰。
如图19所示，本公开的一些实施例提供的显示基板500还包括用于传输第二电源电压VDD的第二电源电压线VL2，第一晶体管110的第三极和第二电源电压线VL2电连接以接收第二电源电压VDD。例如，本公开的实施例中 的第二电源电压VDD为高电平电压，例如，第二电源电压为5V。
例如，第一晶体管110为P型MOS晶体管，其沟道区为P型掺杂。如图19所示，与第一晶体管110的控制极(栅极)113相对的第三极接收第二电源电压VDD。例如，第二晶体管120、第三晶体管130以及驱动晶体管140均为N型MOS晶体管，其沟道区为N型掺杂，第二晶体管120、第三晶体管130以及驱动晶体管140的第三极均配置为接地(GND)。
例如，第二电源电压线VL2在衬底的正投影位于第一电源电压线VL1在衬底的正投影以及发光控制线EL在衬底的正投影之间，且第二电源电压线VL2的部分延伸方向与第四方向D4平行。
如图19所示，第二电源电压线VL2在沿第四方向D4延伸时，有一个弯折区域；另外，发光控制线EL在沿第四方向D4延伸时，也有一个弯折区域，且第二电源电压线VL2与发光控制线EL的弯折方向不同。采用这种走线方式例如可以为下文中描述的第一转接电极AE1留出布局空间。
例如，如图19所示，第一晶体管110以及第二晶体管120均设置在第二扫描信号线SL2与发光控制线EL之间，且第一晶体管110和第一电源电压线VL1以及第二电源电压线VL2相交，且第二晶体管120和第一电源电压线VL1以及第二电源电压线VL2相交。
例如，第一晶体管110的第一有源区114在衬底上的正投影以及第二晶体管120的第二有源区124在衬底上的正投影均位于第二扫描信号线SL2在衬底上的正投影与发光控制线EL在衬底上的正投影之间。
第一晶体管110的第一有源区114在衬底上的正投影与第一电源电压线VL1在衬底上的正投影相交，且第一晶体管110的第一有源区114在衬底上的正投影与第二电源电压线VL2在衬底上的正投影相交。
第二晶体管120的第二有源区124在衬底上的正投影与第一电源电压线VL1在衬底上的正投影相交，且第二晶体管120的第二有源区124在衬底上的正投影与第二电源电压线VL2在衬底上的正投影相交。
如图19所示，本公开的一些实施例提供的显示基板500还包括设置在发光控制线EL的第一侧的第一转接电极AE1，以及从发光控制线EL的第一侧延伸至发光控制线EL的第二侧的第二转接电极AE2。
例如，第二转接电极AE2在衬底的正投影与发光控制线EL在衬底上的正投影交叉。第一转接电极AE1的两个端部分别和第一晶体管110的第一极 111以及第二晶体管120的第一极121电连接，第一转接电极AE1和第二转接电极AE2电连接，且第二转接电极AE2和驱动晶体管140的控制极143电连接。
例如，第二转接电极AE2的延伸方向与第一转接电极AE1的延伸方向垂直，并且和第四方向D4垂直。
由于第二转接电极AE2连接存储电容CST，驱动电路在工作中该第二转接电极AE2上的电平可能会有较大的波动，该波动可能会对第一电源电压线VL1造成串扰，产生噪声。在本公开的实施例提供的显示基板500中，利用第二电源电压线VL2将第一电源电压线VL1和第二转接电极AE2间隔开，从而可以降低第二转接电极AE2上的电平波动对第一电源电压线VL1造成的串扰，隔绝噪声。
另外，本公开的一些实施例提供的显示基板500通过延长第一晶体管110的第一有源区114以及延长第二晶体管120的第二有源区124，从而为第二电源电压线VL2留出布线通道。
例如，本公开的实施例提供的驱动电路(矩形形状)的布局尺寸大致为4.5um×2.9um。
图20A-20E分别示出了图19中所示的显示基板500的各层布局的平面图。
图20A示出了第一晶体管110的第一有源区114、第二晶体管120的第二有源区124、第三晶体管130的第三有源区134以及驱动晶体管140的第四有源区144，可以将图4A示出的层称为有效显示(AA)层。
图20B示出了第一晶体管110的控制极113、第二晶体管120的控制极123、第三晶体管130的控制极133以及驱动晶体管140的控制极143。可以将4B示出的层称为第一导电层，下文中将对第一导电层进一步描述。例如，第一导电层的材料可以采用多晶硅。
图20C示出了第一电源电压线VL1、第二电源电压线VL2、发光控制线EL、数据线DL、接地线GND、第一转接电极AE1等。可以将图20C示出的层称为第一金属层(metal1)。
图20D示出了第二转接电极AE2、连接第一扫描信号线SL1与第一晶体管110的电极、连接第二扫描信号线SL2与第二晶体管120的电极。可以将图20D示出的层称为第二金属层(metal2)。
图20E示出了第一扫描信号线SL1以及第二扫描信号线SL2，可以将图20E示出的层称为第三金属层(metal3)。
需要说明的是，在本公开的实施例中为了示意清楚在图19中并没有示意出存储电容CST，下面结合图21-图23E对图18中的所示出的存储电容CST进行进一步描述。
如图21所示，图21中所示的区域850为设置存储电容CST的区域。需要说明的是，为了示意清楚，图21中并没有示出全部结构的对应标记，省略的部分可以参考图19中的对应标记。
图22为存储电容CST的布局图，图23A-图23D为对应图22的各层布局的平面图，图23E为存储电容CST的截面示意图。
图22示出了4层结构，分别为第三金属层metal3、第四金属层metal4、辅助金属层metal4'、第五金属层metal5；另外还示出了第一过孔V1以及第二过孔V2，在下文中将结合截面示意图对第一过孔V1以及第二过孔V2进行描述，这里不再赘述。
例如，图23A示出了第三金属层metal3，例如，该第三金属层和图20E中示出的层是同一层。如图23A所示，该第三金属层metal3包括两部分，分别为充当第一电容C1的第一极的电极811和充当第一电容C1的第二极的电极812。例如，电极811被配置为接收第三电源电压AVSS；电极812通过第二过孔V2和第五金属层metal5中的电极840电连接，从而实现和驱动晶体管140的控制极143电连接。
电极811包括多个条状电极，电极812包括多个条状电极，电极811的多个条状电极和电极812的多个条状电极相互交替排布，且电极811和电极812以及之间的间隔部分形成第一电容C1。例如，该第一电容C1为存储电容CST的一部分，例如，该第一电容C1和下文中的第二电容C2并联从而形成存储电容CST。
例如，图23B示出了位于第四金属层metal4的电极820，例如，电极820为一个面状电极，该电极820充当第二电容C2的第一极。
例如，图23C示出了位于辅助金属层metal4'的电极830，例如，电极830为一个面状电极，该电极830充当第二电容C2的第二极。
例如，图23D示出了位于第五金属层metal5的电极840，以及第一过孔V1和第二过孔V2。
图23E示出了上述存储电容CST的部分结构的截面示意图，如图23E所示，位于第五金属层metal5的电极840通过第一过孔V1和位于辅助金属层metal4'的电极830电连接；另外，位于第五金属层metal5的电极840通过第二过孔V2和位于第三金属层metal3的电极812电连接。需要说明的是，第二过孔V2会贯穿第四金属层metal4，图23E中未示出。
如图23E所示，位于第四金属层metal4的电极820和位于辅助金属层metal4'的电极830以及之间的间隔部分形成第二电容C2；例如，上文中所述的第一电容C1以及该第二电容C2并联共同构成存储电容CST。
在本公开的实施例中，如图23E所示，在第四金属层metal4和第五金属层metal5之间设置辅助金属层metal4'，从而可以使得第四金属层metal4与辅助金属层metal4'之间的间距例如为第四金属层metal4与第五金属层metal5之间的间距的约1/10，从而可以有效地增大该第二电容C2单位面积内的电容值。
如图18和图19所示，本公开的实施例还提供一种显示基板500，包括衬底以及形成在衬底上的至少一个驱动电路。驱动电路包括驱动晶体管140、第一晶体管110、第二晶体管120以及第三晶体130。
驱动晶体管140包括控制极143、第一极141和第二极142，且被配置为，根据驱动晶体管140的控制极143的电压，控制流经驱动晶体管140的第一极141和驱动晶体管140的第二极142的用于驱动发光元件LE发光的驱动电流。
第一晶体管110连接到驱动晶体管140的控制极143，且被配置为响应于第一扫描信号SCAN1将数据信号DATA写入驱动晶体管140的控制极143。第二晶体管120连接到驱动晶体管140的控制极143，且被配置为响应于第二扫描信号SCAN2将数据信号DATA写入驱动晶体管140的控制极143。第三晶体管130连接到驱动晶体管140的第一极141，且被配置为响应于发光控制信号EN将第一电源电压ELVDD施加到驱动晶体管140的第一极141。
该显示基板500还包括用于传输第一扫描信号SCAN1的第一扫描信号线SL1以及用于传输第二扫描信号SCAN2的第二扫描信号线SL2，用于传输第一电源电压ELVDD的第一电源电压线VL1以及用于传输发光控制信号EN的发光控制线EL；第一扫描信号线SL1、第二扫描信号线SL2、第一电源电压线VL1以及发光控制线EL在衬底的正投影沿与第四方向D4的垂直方向依 次排布。
例如，沿第一晶体管110的第一极111至第一晶体管110的第二极112的方向为第一方向D1，沿第二晶体管120的第一极121至第二晶体管120的第二极122的方向为第二方向D2，沿第三晶体管130的第一极131至第三晶体管130的第二极132的方向为第三方向D3，沿驱动晶体管140的第一极141至驱动晶体管140的第二极142的方向为第四方向D4，第一方向D1、第二方向D2以及第三方向D3均和第四方向D4相交。例如，第一方向D1、第二方向D2以及第三方向D3均和第四方向D4垂直。
本公开至少一个实施例提供的显示基板，通过设计中的优化的布图布线设计处理，可以实现5.45um×13.6um的亚像素面积，实现了高的分辨率(PPI)和像素电路阵列的优化排布，并具有较好的显示效果。
图24A是本公开至少一实施例提供的显示基板的框图。如图24A所示，该显示基板10包括阵列分布的多个子像素100、多条扫描线11和多条数据线12。每个子像素100包括发光元件和驱动该发光元件的像素电路。多条扫描线11和多条数据线12彼此交叉在显示区中定义出阵列分布的多个像素区，每个像素区中设置一个子像素100的像素电路。该像素电路例如为常规的像素电路，例如为2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C等nTmC(n、m为正整数)像素电路，并且不同的实施例中，该像素电路还可以进一步包括补偿子电路，该补偿子电路包括内部补偿子电路或外部补偿子电路，补偿子电路可以包括晶体管、电容等。例如，根据需要，该像素电路还可以进一步包括复位电路、发光控制子电路、检测电路等。例如，该显示基板还可以包括位于非显示区中的栅极驱动子电路13和数据驱动子电路14。该栅极驱动子电路13通过扫描线11与像素电路连接以提供各种扫描信号，该数据驱动子电路14通过数据线12与像素电路连接以提供数据信号。其中，图24A中示出的栅极驱动子电路13和数据驱动子电路14，扫描线11和数据线12在显示基板中的位置关系只是示例，实际的排布位置可以根据需要进行设计。
例如，显示基板10还可以包括控制电路(未示出)。例如，该控制电路配置为控制数据驱动子电路14施加该数据信号，以及控制栅极驱动子电路施加该扫描信号。该控制电路的一个示例为时序控制电路(T-con)。控制电路可以为各种形式，例如包括处理器和存储器，存储器包括可执行代码，处理器 运行该可执行代码以执行上述检测方法。
例如，处理器可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储装置可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据。
该像素电路根据需要可以包括驱动子电路、数据写入子电路、补偿子电路和存储子电路，根据需要还可以包括发光控制子电路、复位电路等。
图24B示出了一种像素电路的示意图。如图24B所示，该像素电路包括数据写入子电路111、驱动子电路112和存储子电路113。
数据写入子电路111与存储子电路113的第一端电连接，并配置为响应于控制信号(第一控制信号SEL)将数据信号Vd传输至存储子电路113的第一端。存储子电路113的第二端例如配置为接收第二电源电压VSS。
驱动子电路112包括控制电极150、第一电极151和第二电极152，驱动子电路的控制电极150与存储子电路的第一端电连接，驱动子电路112的第一电极151配置为接收第一电源电压VDD，驱动子电路112的第二电极152与第一节点S电连接，并与发光元件120的第一电极121连接。驱动子电路112配置为响应于存储子电路的第一端的电压驱动发光元件120发光。该发光元件120的第二电极122例如配置为接收第一公共电压Vcom1。
在本公开至少一些实施例中，如图24B所示，该像素电路还包括偏置子电路114。该偏置子电路114包括控制端、第一端和第二端，该偏置子电路114的控制端配置为接收偏置信号；该偏置子电路114的第一端例如配置为接收第二电源电压VSS，该偏置子电路114的第二端与第一节点S电连接。例如该偏置信号为第二公共电压Vcom2。例如，该偏置信号Vcom2为恒定电压信号，例如为0.8V-1V；该偏置子电路114在该偏置信号的作用下为常开状态，配置为提供恒定电流，从而使得施加至发光元件120的电压与数据信号 成线性关系，有助于对灰阶实现精细的控制，从而提高显示效果。后文将结合具体电路对此进行进一步说明。
例如，当数据信号(电压)Vd由高变低时，写入发光元件120的第一电极121的灰阶电压需要快速变化，该偏置子电路114还可以允许发光元件120的第一电极121迅速地释放电荷，从而实现较好的动态对比度。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以金属-氧化物半导体场效应晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。
本公开实施例提供的显示基板可以采用刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。本公开的实施例均以硅基板为例进行说明，也即像素结构制备于硅基板上，然而，本公开实施例对此不作限制。
例如，该像素电路包括互补型金属氧化物半导体电路(CMOS电路)，也即该像素电路制备于单晶硅衬底基板上。有赖于成熟的CMOS集成电路技术，硅基工艺可以实现较高的精度(例如PPI可以达到6500甚至一万以上)。
例如，当显示基板由于工艺波动导致子像素中的发光元件120的第一电极121与第二电极122发生短路，导致发光元件120的第一电极121的电压过高(例如第一公共电压Vcom1为高电位)或过低(例如第一公共电压 Vcom1为低电位)，从而在第一节点S处引发闩锁效应，造成CMOS电路失效，导致显示基板出现暗线等不良。
在一些示例中，例如，该数据写入子电路包括第一数据写入晶体管P1，驱动子电路包括驱动晶体管N2；例如，第一数据写入晶体管为P型金属-氧化物半导体场效应晶体管(PMOS)，驱动晶体管N2为N型金属-氧化物半导体场效应晶体管(NMOS)，该驱动晶体管N2的栅极、第一极、第二极分别作为该驱动子电路112的控制电极150、第一电极151和第二电极152。在这种情形，例如当提供给发光元件120的第二电极122的第一公共电压Vcom1为低电位，且发光元件120的第一电极121与第二电极122发生短路，将导致与该第一电极121直接连接的驱动晶体管的第二极的电位过低。
图24C示出了该像素电路形成闩锁效应的示意图。该驱动晶体管N2的N型有源区(如第二极)、P型硅基衬底、该第一数据写入晶体管P1所在的N型阱区以及该第一数据写入晶体管P1的P型有源区(如第一极)形成彼此连接的两个寄生晶体管Q1、Q2，构成的N-P-N-P结构。当驱动晶体管N2的第二极(也即第一节点S处)的电位过低，导致该驱动晶体管N2的第二极(N型重掺杂区)与P型衬底之间的PN结(发射结)正偏，Q1导通，会提供足够大的电流使得寄生晶体管Q2导通，又反过来向寄生晶体管Q1反馈电流，形成恶性循环，最后导致大部分的电流从VDD直接通过寄生晶体管到VSS，而不受晶体管栅压的控制，造成CMOS像素电路失效；并且该闩锁效应会导致寄生晶体管Q2不断从发射极，也即从数据线上抽取电流，从而导致与该数据线连接的一列子像素失效，造成显示基板出现暗线等不良，极大地影响了显示效果。
在本公开至少一些实施例中，至少一个子像素还包括电阻器，该电阻器连接于该驱动子电路112的第二电极152与该发光元件120的第一电极121之间，可以起到升高或降低第一节点S电位的作用，从而可以缓解或避免闩锁效应，提高电路的可靠性，并提高显示效果。
图25A为本公开至少一实施例提供的像素电路的示意图。如图25A所示，该像素电路还包括电阻器130，电阻器130的第一端131与驱动子电路112的第二电极152电连接，第二端132与发光元件120的第一电极121电连接，也即驱动子电路112的第二电极152通过电阻器130与发光元件120的第一电极121电连接。
例如，该电阻器130为恒定电阻或可变电阻，也可以是其它器件(如晶体管)形成的等效电阻。
例如，该电阻器130与驱动子电路112的控制电极150同层绝缘设置，且所述电阻器的电阻率高于所述驱动子电路的控制电极的电阻率。例如，电阻器的电阻率为该控制电极的电阻率的十倍以上。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
通过这种设置，可以使得驱动子电路控制电极与电阻器在同一构图工艺中形成，从而节省工艺。
例如，电阻器和所述驱动子电路的控制电极的材料均为多晶硅材料，且电阻器的掺杂浓度低于控制电极的掺杂浓度，因此电阻器具有比控制电极高的电阻率。例如，电阻器可以是本征多晶硅或轻掺杂多晶硅，控制电极为重掺杂多晶硅。
在另一些示例中，控制电极和电阻器的材料可以不同。例如，控制电极和电阻器的材料可以分别包括金属以及该金属对应的金属氧化物。例如，该金属可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料。
在本公开至少一实施例中，该数据写入子电路111可以包括由互补的两个晶体管彼此并联构成的传输门电路；该控制信号包括反相的两个控制信号。该数据写入子电路111采用传输门结构的电路可以有助于使数据信号没有损失地传输到存储子电路113的第一端。
例如，数据写入子电路包括第一控制电极、第二控制电极、第一端和第二端，数据写入子电路的第一控制电极和第二控制电极分别配置为接收第一控制信号和第二控制信号，数据写入子电路的第一端配置为接收数据信号，数据写入子电路的第二端与存储子电路的第一端电连接，并配置为响应于所述第一控制信号和所述第二控制信号将所述数据信号传输至所述存储子电路的第一端。
需要注意的是，在本公开实施例的说明中，第一节点S并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符号SEL既可以表示控制信号，也可以表示控制信号端，符号Vcom1、Vcom2既可以表示第一公共电压、第二公共电压，也可以表示第一公共电压端和第二公共电压端；符号VDD既可以表示第一电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。
图25B示出了图24A所示像素电路的一种具体实现示例的电路图。如图25B所示，该数据写入子电路111包括彼此并联的第一数据写入晶体管P1和第二数据写入晶体管N1。该第一数据写入晶体管P1和第二数据写入晶体管N1分别为P型金属-氧化物半导体场效应晶体管(PMOS)和N型金属-氧化物半导体场效应晶体管(NMOS)。该控制信号包括互为反相的第一控制信号SEL和第二控制信号SEL_B，该第一数据写入晶体管P1的栅极作为该数据写入子电路的第一控制电极，并配置为接收该第一控制信号SEL，该第二数据写入晶体管N1的栅极作为该数据写入子电路的第二控制电极，并配置为接收该第二控制信号SEL_B。该第二数据写入晶体管N1的第一极和第一数据写入晶体管P1的第一极电连接作为该数据写入子电路的第一端，并配置为接收数据信号Vd；第二数据写入晶体管N1的第二极与第一数据写入晶体管P1的第二极电连接作为该数据写入子电路的第二端，并与驱动子电路112的控制电极150电连接。
例如，该第一数据写入晶体管P1和第二数据写入晶体管N1大小相同，具有相同的沟道宽长比。
该数据写入子电路111利用了晶体管互补的电学特性，无论传输高电平还是低电平，都具有较低的开态电阻，从而具有电学信号传输完整性的优势，可以将数据信号Vd没有损失地传输至存储子电路113的第一端。
例如，如图25B所示，该驱动子电路112包括驱动晶体管N2，例如，该驱动晶体管N2为NMOS。该驱动晶体管N2的栅极、第一极和第二极分别作为驱动子电路112的控制电极、第一电极和第二电极。
例如，该存储子电路113包括存储电容Cst，该存储电容Cst包括第一电容电极141和第二电容电极142，该第一电容电极141和第二电容电极142分 别作为该存储子电路113的第一端和第二端。
例如，该电阻器130包括电阻R。例如，驱动子电路112的第二电极152与衬底基板之间形成PN结，电阻器130的阻值配置为当驱动晶体管N2工作在饱和区时，也即该像素电路工作以驱动发光元件120发光时，该PN结关断。在这种情形，即便发光元件120的两个电极之间发生短路，由于该电阻器130上存在压降，可以对该第二电极152的电位进行保护，从而避免了闩锁效应的发生。
例如，发光元件120具体实现为有机发光二极管(OLED)。例如，发光元件120可以为顶发射结构的OLED，可以发红光、绿光、蓝光或白光等。例如，该发光元件120为微型OLED(Micro OLED)。本公开的实施例对发光元件的具体结构不作限制。例如，该发光元件120的第一电极121为OLED的阳极，第二电极122为OLED的阴极，也即该像素电路为共阴极结构。然而，本公开实施例对此不作限制，根据电路结构的变化，该像素电路也可以是共阳极结构。
例如，该偏置子电路114包括偏置晶体管N3，该偏置晶体管N3的栅极、第一极和第二极分别作为偏置子电路114的控制端、第一端和第二端。
图25C示出了图25B所示像素电路的信号时序图，以下将结合图25B所示的信号时序图对图25C所示的像素电路的工作原理进行说明。例如，第二数据写入晶体管、驱动晶体管、偏置晶体管均为N型晶体管，第一数据写入晶体管为P型管，然而本公开实施例对此不做限制。
图25C示出了各信号在连续两个显示周期T1和T2中的波形图，例如该数据信号Vd在显示周期T1为高灰阶电压，在显示周期T2为低灰阶电压。
例如，如图25C所示，每一帧图像的显示过程包括数据写入阶段1以及发光阶段2。该像素电路的一种工作过程包括：在数据写入阶段1，第一控制信号SEL和第二控制信号SEL_B均为开启信号，第一数据写入晶体管P1和第二数据写入晶体管N1导通，数据信号Vd经第一数据写入晶体管P1和第二数据写入晶体管N1传输至驱动晶体管N2的栅极；在发光阶段2，第一控制信号SEL和第二控制信号SEL_B均为关闭信号，由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，驱动晶体管N2工作在饱和状态且电流不变，并驱动发光元件120发光。当像素电路从显示周期T1进入到显示周期T2，数据信号Vd由高灰阶电压变为低灰阶电压，偏置晶体管N3在第二 公共电压Vcom2的控制下产生稳定的漏极电流，该漏极电流在OLED的显示灰阶需要快速变化时，可以快速泄放OLED阳极存储的电荷。例如，该放电过程发生于显示周期T2的数据写入1，因此在该显示周期T2的发光阶段2，该OLED阳极的电压得以快速下降，从而实现较好的动态对比度，提高了显示效果。
例如，当该第一节点S与发光元件120直接电连接时，电压V0直接加载到该发光元件120的第一电极121上，例如为OLED的阳极电压；当第一节点S通过电阻器130与该发光元件120电连接，由于流过发光元件120的电流极小，因此该第一节点S的电压可以近似等于该发光元件120的第一电极121的电压；也即使得发光元件120的第一电极121的电压与数据信号(数据电压)Vd成线性关系，从而可以实现对灰阶实现精细的控制，提高了显示效果。
例如，第一控制信号SEL和第二控制信号SEL_B为差分互补信号，振幅相同，相位相反。这样有助于提高电路的抗干扰性能。例如，该第一控制信号SEL和第二控制信号SEL_B可以由同一栅驱动电路单元(如GOA单元)输出，从而简化电路。
例如，如图24A所示，显示基板10还可以包括数据驱动电路13和扫描驱动电路14。数据驱动电路13配置为根据需要(例如输入显示装置的图像信号)可发出数据信号，例如上述数据信号Vd。扫描驱动电路14配置为输出各种扫描信号，例如包括上述第一控制信号SEL和第二控制信号SEL_B，其例如为集成电路芯片(IC)或者为直接制备在显示基板上的栅驱动电路(GOA)。
例如，该显示基板采用硅基板作为衬底基板101，该像素电路、数据驱动电路13和扫描驱动电路14都可以集成于该硅基板上。在此情形下，由于硅基电路可以实现较高的精度，该数据驱动电路13和扫描驱动电路14例如也可以形成于对应于该显示基板的显示区的区域中，而并不一定位于非显示区。
例如，显示基板10还包括控制电路(未示出)。例如，该控制电路配置为控制数据驱动电路13施加该数据信号Vd，以及控制栅极驱动电路13施加各种扫描信号。该控制电路的一个示例为时序控制电路(T-con)。控制电路可以为各种形式，例如包括处理器和存储器，存储器包括可执行代码，处理器 运行该可执行代码以执行上述检测方法。
例如，处理器可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储装置可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器121可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据，例如在上述检测方法中获取的电特性参数等。
以下以采用图25B所示像素电路为例对本公开至少一实施例提供的显示基板进行示例性说明，然而本公开实施例并不限于此。
图26A为本公开至少一个实施例提供的显示基板10的示意图。例如，如图26A所示，该显示基板10包括衬底基板101，多个子像素100位于该衬底基板101上。多个子像素100布置为子像素阵列，该子像素阵列的行方向为第一方向D1，列方向为第二方向D2，第一方向D1与第二方向D2交叉，例如正交。图26A中示例性地示出了两行六列子像素，也即两个像素行20和六个像素列30，并用虚线框分别示出了彼此间隔的三个像素列的区域。
例如，衬底基板101可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。本公开实施例均以该衬底基板101为硅基板为例进行说明，然而本公开实施例并不限于此。
例如，该衬底基板101包括单晶硅或者高纯度硅。像素电路通过CMOS半导体工艺形成于衬底基板10上，例如，通过掺杂工艺在衬底基板101中形成晶体管的有源区(包括晶体管的沟道区、第一极和第二极)，并通过硅氧化工艺或者化学气相淀积工艺(CVD)形成各绝缘层、以及通过溅射工艺形成 多个导电层从而形成走线结构等。各晶体管的有源区位于衬底基板101的内部。
图26B示出了图26A沿剖面线I-I’的剖视图。为了清楚起见，图26B中省略了一些没有直接连接关系的走线或电极结构。
例如，如图26B所示，该显示基板10包括衬底基板101、依次位于衬底基板101上的第一绝缘层201、多晶硅层102、第二绝缘层202、第一导电层301、第三绝缘层203、第二导电层302、第四绝缘层204、第三导电层303、第五绝缘层205和第四导电层304。以下将对该显示基板10中的结构分层次进行说明，图26B将作为一个参照并一并得到说明。
为了清楚起见并方便说明，图27A示出了该显示基板10位于第一导电层301以下的部分，也即衬底基板101以及其上的第一绝缘层201和多晶硅层102，包括各晶体管(P1、N1-N3)、存储电容Cst以及电阻器130；图27B示出了图27A中一个子像素100的放大示意图；为了清楚起见，在图27A中还对应示出了图26A中剖面线I-I’。图28A-图28E示出了图27A所示的基板结构的形成过程。
如图27B所示，例如，在平行于衬底基板101的板面的方向上，第一数据写入晶体管P1和驱动晶体管N2位于存储电容Cst的相对两侧，例如，在第二方向D2上位于该存储电容Cst的相对两侧。
结合参考图24C，这种设置有助于拉大第一数据写入晶体管P1与驱动晶体管N2的距离，从而增大寄生电路的电阻，进一步降低了CMOS电路的闩锁效应的风险。
例如，存储电容140的第二电容电极142的材料为导体或半导体。例如，结合图26B和图27B所示，存储电容140的第二电容电极142为衬底基板101的第一区401；例如，该衬底基板101为P型硅基衬底，该第二电容电极142的材料为P型单晶硅。当第一电容电极141上施加电压，衬底基板101中位于该第一电容电极141下方的半导体性质的第一区401形成反型区而变为导体，从而与该第一区401两侧的接触孔区(如图4B所示的接触孔区145a、145b)形成电连接。在这种情形，并未对该第一区401进行额外掺杂等处理。
在另一示例中，该第一区401例如为衬底基板101中的导体化区域，例如重掺杂区域，从而可以使得第二电容电极142获得稳定的较高的导电率。
例如，该衬底基板101还包括第二区402，该第二区402为衬底基板101中的N型阱区。如图27B所示，例如，第一数据写入晶体管P1和电阻器130在第二方向D2上并排设置于第二区402中。将多晶硅材料的电阻器130设置于N型衬底中有助于减少寄生效应，提高电路特性。
例如，在平行于衬底基板101的板面的方向上，电阻器(R)130与第一数据写入晶体管P1位于第二电容电极142的同一侧。例如，在平行于衬底基板101的板面的方向上，驱动晶体管N2和偏置晶体管N3位于第二电容电极142的同一侧。
例如，如图27B所示，第一数据写入晶体管P1和第二数据写入晶体管P1在第一方向D1上并排设置，并关于沿第二方向D2的对称轴对称。例如，第一数据写入晶体管P1的栅极160和第二数据写入晶体管N1的栅极170在第一方向D1并排设置，并关于沿第二方向D2的对称轴对称。
例如，电阻器130为U型结构，例如为不对称的U型结构，例如该U型结构的两个分支的长度不等。例如，如图27B所示，电阻器130的第二端132更靠近驱动晶体管N2。
将电阻器130设置为U型结构有助于节省电阻器所占用的版图面积，从而提高版图的空间利用率，有助于提高显示基板的分辨率。例如，在相同的空间内，U型结构的电阻器可以增大电阻器的长度，从而得到期望的电阻值。
此外，将电阻器130设计为非对称结构同样是为了合理利用版图空间，例如，如图27B所示，该U型电阻器较短分支的上方设计了接触孔区411a，该接触孔区411a在第一方向D1上与该电阻器130的第二端132并列。例如，该接触孔区411a为N型重掺杂区(N+)。例如，该接触孔区411是为了对第一数据写入晶体管P1所在的阱区401进行偏置，从而避免闩锁效应和衬底偏置效应引起的阈值电压变化，提高电路的稳定性。例如，参照图26B，通过将P型衬底101进行低压偏置，N型阱区402进行高压偏置，可以使得二者之间的寄生PN结反偏，对器件进行电性隔离，并降低器件之间的寄生效应，提高电路的稳定性。
例如，U型结构的开口朝向第一电容电极141，电阻器130的第一端131和第二端132分别位于U型结构的两个端部。如图所示，该电阻器130的第一端131设置有接触孔区133，用于与驱动晶体管N2的栅极150电连接；该 电阻器130第二端132设置有接触孔区134，用于与发光元件120的第一电极121电连接。
例如，该电阻器130的材料包括多晶硅材料，该接触孔区133、134为掺杂区，用于降低接触电阻；该电阻器130除该接触孔区以外的主体区域例如为本征区或低掺杂区，从而得到期望的电阻值。
例如，存储电容140的第一电容电极141与电阻器130同层绝缘设置，且都包括多晶硅材料；存储电容140的第一电容电极141的掺杂浓度高于电阻器130的主体区的掺杂浓度。例如，该电阻器130的主体区为本征多晶硅材料。
例如，各晶体管P1、N1-N3的栅极160、170、150、180与存储电容140的第一电容电极141同层设置，均包括多晶硅材料。例如，如图27B所示，驱动晶体管N2的栅极150与第一电容电极141彼此连接为一体的结构。
图27B中还分别示出了各晶体管P1、N1-N3的有源区P1a、N1a、N2a和N3a，并示出了第一数据写入晶体管P1的第一极161和第二极162，第二数据写入晶体管N1的第一极171和第二极172，驱动晶体管N2的第一极151和第二极152，偏置晶体管N3的第一极181和第二极182。
图27B中还分别示出了第一数据写入晶体管P1的栅极接触区165、第一接触区163和第二极接触区164，第二数据写入晶体管N1的栅极接触区175、第一接触区173和第二极接触区174，驱动晶体管N2的栅极接触区155、第一接触区153和第二极接触区154，以及偏置晶体管N3的栅极接触区185、第一接触区183和第二极接触区184。例如，各第一极接触区为所对应的第一极用于形成电接触的区域，各第二极接触区为对应的第二极接触区为用于形成电接触的区域，各栅极接触区为对应的栅极用于形成电接触的区域。
例如，第一数据写入晶体管P1的有源区P1a与第二数据写入晶体管N1的有源区N1a在第一方向D1并排设置，并关于沿第二方向D2的对称轴对称。
如图27B所示，驱动晶体管N2的有源区N2a的面积相较于其它晶体管的有源区的面积大，可以获得较大的宽长比，有助于提高驱动晶体管N2的驱动能力，从而提高显示效果。
如图27B所示，对于有源区较大的晶体管，如驱动晶体管N2和偏置晶 体管N3，由于有足够空间，可以在其第一极和第二极上分别设置至少两个接触孔区，从而可以与待连接结构获得充分的接触并形成并联结构，从而降低接触电阻。
图27B中还示出了与第一电容电极141上的接触孔区144以及配置为与第二电容电极142电连接的接触孔区145a、145b。如图27B所示，第一电容电极141和第二电容电极142分别对应设置至少两个接触孔区以降低接触电阻。
结合参考图27A，在第一方向D1上相邻的两个子像素100中晶体管(例如包括各晶体管的形状、尺寸等)以及存储电容、电阻器的分布关于沿第二方向D2的对称轴对称，也即该两个子像素中对应的结构分别关于沿第二方向D2的对称轴对称。在第二方向D2上相邻的两个子像素100中晶体管的分布关于第一方向轴对称。
这种对称设置可以尽量提高工艺误差的均一性，从而提高显示基板的均一性。此外，这种对称设置使得基板中一些同层设置且可以彼此连接的结构可以一体形成，相较于分开设置，可以使得像素布局更加紧凑，提高空间的利用率，从而提高了显示基板的分辨率。
例如，如图27A所示，在第一方向D1上相邻的两个子像素100的第二区402为一体的结构，在第二方向D2上相邻的两个子像素100的第二区402为一体的结构，也即该相邻的四个子像素100中的第一数据写入晶体管N1和电阻器130位于同一阱区。相较于分别设置独立的阱区，这种设置可以在满足设计规则的前提下使得像素的排布更加紧凑，有助于提高显示基板的分辨率。
例如，如图27A所示，在第二方向D2上相邻的两个子像素的第一数据写入晶体管P1的有源区P1a彼此连接为一体的结构，也即该两个第一数据写入晶体管P1的有源区P1a位于同一第二区402的同一掺杂区A1(P阱)中，且该两个第一数据晶体管P1的第一极彼此连接为一体的结构，以接收同一数据信号Vd。
例如，如图27A所示，在第二方向D2上相邻的两个子像素的第二数据写入晶体管N1的有源区N1a彼此连接为一体的结构，也即该两个第二数据写入晶体管N1的有源区N1a位于衬底基板101的同一掺杂区A2(N阱)中，且该两个第二数据写入晶体管N1的第一极彼此连接为一体的结构，以接 收同一数据信号Vd。
例如，如图27A所示，在第一方向D1上相邻的两个子像素100的第一数据写入晶体管P1的栅极或者第二数据写入晶体管N2的栅极彼此连接为一体的结构。
由于对于每行像素，第一数据写入晶体管P1的栅极都配置为接收同一第一控制信号SEL，第二数据写入晶体管N1的栅极都配置为接收同一第二控制信号SEL_B。又由于在第一方向D1上相邻的两个子像素的晶体管镜像对称，在第一方向D1上交替出现两个子像素的第一写入晶体管P1相邻的情形与第二写入晶体管N1相邻的情形。因此相邻两个第一数据写入晶体管P1的栅极可以直接连接为一体的结构，形成第一控制电极组191，相邻的第二数据写入晶体管N1的栅极可以直接连接为一体的结构，形成第二控制电极组192。这种设置可以在满足设计规则的前提下使得像素的排布更加紧凑，有助于提高显示基板的分辨率。
如图27A所示，对于第一方向D1上相邻的两个子像素100，当它们的驱动晶体管N2相邻的情形，两个驱动晶体管N2的有源区N2a彼此连接为一体的结构，也即该两个驱动晶体管N2的有源区N2a位于衬底基板101的同一掺杂区B(N阱)中，且该两个驱动晶体管N2的第一极彼此连接为一体的结构，形成第三控制电极组193，以接收同一第一电源电压VDD；当它们的偏置晶体管N3相邻的情形，两个偏置晶体管N3的栅极彼此连接为一体的结构，以接收同一第二公共电压Vcom2；两个偏置晶体管N3的有源区N3a彼此连接为一体的结构，也即该两个偏置晶体管N3的有源区N3a位于衬底基板101的同一掺杂区C(N阱)中，且该两个偏置晶体管N3的第一极彼此连接为一体的结构，以接收同一第二电源电压VSS。
这种设置可以在满足设计规则的前提下使得像素的排布更加紧凑，有助于提高显示基板的分辨率。
图28A-图28D示出了图27A所示的基板结构的形成过程，为了清楚起见，图中仅示出了两行两列子像素，也即相邻的四个子像素100。以下结合图28A-28D对本公开实施例提供的显示基板的形成过程进行示例性说明，然而这并不作为对本公开的限制。
例如，提供一块硅基衬底基板，例如其材料为P型单晶硅。N型晶体管(例如驱动晶体管)可以直接在该P型硅衬底上制作，也即该P型衬底充当 该N型晶体管的沟道区，有利于发挥NMOS器件高速的优势，提高了电路性能。
如图28A所示，例如，在P型硅衬底基板上进行N型掺杂，形成N型阱区，也即第二区402，以作为第一数据写入晶体管P1和电阻器130的衬底。
例如，在第一方向D1上相邻的两个子像素的第二区402可以彼此连接，在第二方向D2上相邻的两个子像素的第二区402可以彼此连接。例如，在进行该N型掺杂时对该衬底基板101上不掺杂的区域进行遮挡。
结合图27B和图28B所示，例如，在该衬底基板101上形成第一绝缘层201，接着在该第一绝缘层201上形成多晶硅层102。
该第一绝缘层201包括各晶体管的栅极绝缘层，还包括存储电容Cst的介质层104。该多晶硅层102包括第一电容电极141、电阻器130以及各晶体管(P1、N1-N3)的栅极150、160、170、180。
该第一数据写入晶体管P1的栅极位于该第二区402，该N型阱区充当该P型晶体管的沟道区。该电阻器130也位于该第二区402，将多晶硅材料的电阻器130形成于N型衬底中有助于减少寄生效应，提高电路特性。各N型晶体管直接形成在P型衬底上。
如图28B所示，在第一方向D1上相邻的两个子像素中的多晶硅层的图案关于沿第二方向D2的对称轴对称；在第二方向D2上相邻的两个子像素中的多晶硅层的图案关于沿第一方向D1的对称轴对称。
例如，在第一方向D1上相邻的两个子像素的第一数据写入晶体管P1和第二数据写入晶体管N1的栅极可以分别一体成型。
例如，通过热氧化法在衬底基板上形成该第一绝缘层。例如，该第一绝缘层的材料为硅的氮化物、氧化物或氮氧化物。
例如，通过化学气相淀积工艺(PVD)在该第一绝缘层上形成多晶硅材料层，然后对该多晶硅材料层进行光刻工艺形成该多晶硅层102。
图28C示出了衬底基板的掺杂窗口区103(左图)，并在图28B所示基板结构上示出了该掺杂窗口区(右图)。例如，该掺杂为重掺杂，以在衬底基板上形成用于电连接的接触孔区。例如，该掺杂窗口区包括各晶体管的源极区和漏极区。例如，该掺杂窗口区还包括衬底的各接触孔区以及电阻器130的接触孔区，例如包括图27B所示的接触孔区400a、400b、411a、411b、145a、145b、133、134。例如，由于晶体管的栅极由多晶硅材料形成，也需 要对该多晶硅栅极进行掺杂。在进行掺杂时，需要形成阻挡层以遮挡非掺杂区域，而仅仅暴露出相应的掺杂窗口区及非晶硅区。
需要说明的是，图28C仅对各掺杂窗口区进行了示意，在实际进行掺杂工艺时再设置相应的阻挡层/掩模层暴露相应的掺杂窗口区及多晶硅区进行掺杂即可。例如，该阻挡层/掩模层的材料可以是光刻胶或者氧化物材料。
如图28D所示，对应电阻器130形成阻挡层135。为了保护电阻器130的阻值，需要在掺杂过程中对电阻器130进行遮挡以避免电阻器130因掺杂而被破坏。该阻挡层135遮挡住了电阻器130的主体部分，仅暴露出电阻器130两端的接触孔区133、134。
例如，该阻挡层135可以是硅的氮化物、氧化物或者氮氧化物，也可以是光刻胶材料。待掺杂工艺结束后，该阻挡层135可以保留在显示基板中，也可以去除。
在另一些示例中，该电阻器130的阻挡层135也可以在掺杂时同其它区域的阻挡层/掩模层一同形成，本公开实施例对此不作限制。
例如，在掺杂过程中，需要分别进行N型掺杂和P型掺杂，例如以形成N型晶体管的源极区和漏极区以及P型晶体管的源极区和漏极区。在进行N型掺杂工艺时，需要形成阻挡层不进行N型掺杂的区域遮挡；在进行P型掺杂工艺时，需要形成阻挡层将不进行P型掺杂的区域遮挡。
图28E中用不同的阴影图案(左图)示出了N型掺杂区SN和P型掺杂区SP，并在图28D所示的基板上示出了该N型掺杂区SN和P型掺杂区SP(右图)。该N型掺杂区SN和P型掺杂区SP在图27B中也示出，可以一并参照。
例如，进行N型掺杂工艺包括形成阻挡层覆盖该P型掺杂区SP，并覆盖N型掺杂区SN中除掺杂窗口区及多晶硅区以外的区域，仅保留N型掺杂区SN中的掺杂窗口区以及多晶硅区，也即该SN区与图28C所示掺杂窗口区103及多晶硅区的重叠区域；然后进行N型掺杂工艺。对照图27B，通过该N型掺杂工艺可以形成晶体管N1-N3的栅极以及第一极和第二极，以及接触孔区411a、411b、145a、145b。该N型掺杂工艺可例如可以为离子注入工艺，掺杂元素例如可以是硼元素。
例如，进行P型掺杂工艺包括形成阻挡层覆盖该N型掺杂区SN，并覆盖P型掺杂区SP中除掺杂窗口区及多晶硅区以外的区域，仅保留P型掺杂区 SP中的掺杂窗口区及多晶硅区，也即该SP区与图28C所示掺杂窗口区103及多晶硅区的重叠区域；然后进行P型掺杂工艺。对照图27B，通过该P型掺杂工艺可以形成晶体管P1的栅极、第一极和第二极，以及接触孔400a、400b、133、134。该P型掺杂工艺可例如可以为离子注入工艺，掺杂元素例如可以是磷元素。
在掺杂过程中，例如采用离子注入工艺，多晶硅图案可以充当掩模，使得离子对于硅基衬底的注入正好发生在该多晶硅的两侧，从而形成了各晶体管的第一极和第二极，实现了自对准。此外，原本电阻较高的多晶硅经过掺杂工艺电阻率降低，可以形成各晶体管的栅极以及该第一电容电极。因此，采用多晶硅材料作为电阻器及栅极材料具有多种有益效果，并节省了工艺成本。
如此，就形成了图27A所示的显示基板的结构，包括各晶体管P1、N1-N3以及电阻器130、存储电容Cst。
例如，在第一方向D1上相邻的两个子像素中相应的晶体管、电阻器及存储电容Cst分别关于沿第二方向D2的对称轴对称；在第二方向D2上相邻的两个子像素中相应的晶体管、电阻器及存储电容Cst分别关于沿第一方向D1的对称轴对称。
需要说明的是，在本实施例中，存储电容Cst为场效应形成的电容，在第一电容电极141上施加电压后，衬底基板101中位于该第一电容电极141下方的区域产生反型电荷，将该存储电容Cst的下极板，也即第二电容电极142导体化。
在另一些实施例中，也可以预先对衬底基板101位于该第一电容电极141下方的区域进行导体化处理(例如掺杂处理)形成该第二电容电极142。本公开实施例对此不作限制。
在图27A所示的基板上依次形成第二绝缘层202、第一导电层301、第三绝缘层203、第二导电层302、第四绝缘层204、第三导电层303、第五绝缘层205和第四导电层304，就形成了图26A所示的显示基板。
图29A和图29B分别示出了第一导电层301的图案以及该第一导电层301设置于图27A所示基板结构上的情形，图29C示出了图29B沿剖面线IV-IV’的剖视图；图29B中还示出了第二绝缘层202中的过孔，该过孔与图27B中的各接触区一一对应，用于将各接触孔区与第一导电层301中的图案 电连接。为了清楚起见，图中仅示出了两行六列子像素，并用虚线框示出了一个子像素100的区域；此外在图29B中还对应示出了图26A中剖面线I-I’所在的位置。
如图29A所示，在第一方向D1上相邻的两个子像素中的第一导电层的图案关于沿第二方向D2的对称轴对称；在第二方向D2上相邻的两个子像素中的第一导电层的图案关于沿第一方向D1的对称轴对称。以下将以一个子像素为例对该第一导电层的图案进行示例性说明。
如图29A所示，该第一导电层301包括连接电极313，该连接电极313用于将电阻器130的第一端131与驱动子电路112的第二电极152电连接。
例如，结合参考图29B，该连接电极313的第一端通过第二绝缘层202中的过孔225与电阻器130的第一端131电连接；该连接电极313的第二端包括第一支部331和第二支部332，结合图26B，该第一支部331通过第二绝缘层202中的过孔226a与驱动晶体管N2的第一极151电连接，该第二支部332通过第二绝缘层202中的过孔226b与偏置晶体管N3的第一极181电连接。
例如，如图29B所示，在第二方向D2上，该过孔225与过孔226a分别位于第一电容电极141的相对两侧；也即该连接电极313在衬底基板101上的正投影在第二方向D2上穿过该第一电容电极141在衬底基板101上的正投影。
例如，该过孔226a和过孔226b可以设置为至少两个，以降低接触电阻。
例如，结合参考图29A和图29B，该第一导电层301还包括连接电极314，该连接电极314通过第二绝缘层202中的过孔229与电阻器130的第二端132电连接，该连接电极314用于与发光元件120的第一电极121电连接。
例如，该连接电极314为L型，其一个分支与电阻器130的第二端132电连接，另一分支用于与发光元件120的第一电极121电连接。
例如，结合图29B和图29C所示，该第一导电层301还包括第三电容电极315，该第三电容电极315与第一电容电极141在垂直于衬底基板的方向上重叠。该第三电容电极315通过第二绝缘层202中的过孔227与接触孔区145a电连接，以与第二电容电极142电连接；也即，在垂直于衬底基板的方 向上，第二电容电极142和第三电容电极315分别位于第一电容电极141的两侧，且彼此电连接，从而形成并联电容的结构，增大存储电容Cst的电容值。
例如，结合图29B和图29C所示，该第一导电层301还包括第四电容电极316，该第四电容电极316与第一电容电极141及第二电容电极142在垂直于衬底基板的方向上均重叠。该第四电容电极316通过第二绝缘层202中的过孔228与接触孔区145b电连接，以与第二电容电极142电连接。该第四电容电极316可以进一步增大存储电容Cst的电容值，提高电路性能。
例如，第三电容电极315和第四电容电极316在第一方向D1上位于连接电极313的两侧。
例如，如图29A所示，在第一方向上D1相邻的两个子像素中相邻的第三电容电极315可以一体形成以接收同一第二电源电压VSS，在第一方向上D1相邻的两个子像素中相邻的第四电容电极316可以一体形成以接收同一第二电源电压VSS。
例如，该过孔227和过孔228可以分别至少设置两个以降低接触电阻；例如，该至少两个过孔227沿第二方向D2排列，该至少两个过孔228沿第二方向D2排布。
例如，该第一导电层301还包括连接电极317，该连接电极317用于将数据写入子电路的第二端与存储子电路的第一端电连接，也即将第一数据写入晶体管P1的第二极161、第二数据写入晶体管N1的第二极171以及第一电容电极141电连接。
结合参考图29A和图29B，该连接电极317包括三个端部，例如为T型结构。结合参考图26B，该连接电极317的第一端通过第二绝缘层202中的过孔261a与第一数据写入晶体管P1的第二极电连接，该连接电极317的第二端通过第二绝缘层202中的过孔261b与第二数据写入晶体管N1的第二极电连接，该连接电极317的第三端通过第二绝缘层202中的过孔261c与第一电容电极141电连接。
例如，如图29B所示，在第二方向D2上，连接电极314与连接电极317的第三端至少部分重叠。这种设置使得像素布局更为紧凑，从而提高了显示基板的空间利用率，提高了显示基板的分辨率。
结合参考图29A和图29B，该第一导电层301还包括第一扫描线连接部 311和第二扫描线连接部312，该第一扫描线连接部311用于与第一扫描线电连接以使得该第一数据写入晶体管P1的栅极接收第一控制信号SEL。该第二扫描线连接部312用于与第二扫描线电连接以使得该第二数据写入晶体管N1的栅极接收第一控制信号SEL_B。
例如，该第一扫描线连接部311通过第二绝缘层202中的过孔221与第一数据写入晶体管P1的栅极电连接，第二扫描线连接部312通过第二绝缘层202中的过孔222与第二数据写入晶体管N1的栅极电连接。
例如，如图29A所示，在第一方向D1上相邻的子像素共用第一扫描线连接部311或第二扫描线连接部312。
如图29A所示，该第一导电层301还包括数据线连接部245(本公开第三连接电极的一个示例)，该数据线连接部245用于与数据线电连接，以使得该第一数据写入晶体管P1的第一极和第二数据写入晶体管N1的第一极接收到数据线传输的数据信号Vd。
如图29B所示，该数据线连接部245通过第二绝缘层202中的过孔223与第一数据写入晶体管P1的第一极161电连接，通过第二绝缘层202中的孔224与第二数据写入晶体管N1的第一极171电连接。
例如，如图29A所示，多个数据线连接部245在第一方向D1上间隔排布，例如位于两个子像素行的分界处。例如，在第二方向D2上相邻的两个子像素共用一个数据线连接部245。
参考图29A和图29B，该第一导电层301还包括连接电极318，该连接电极318通过第二绝缘层202中的过孔230与驱动晶体管N2的第一极电连接。
参考图27A和图27B，该第一导电层301还包括连接电极319a、319b、319c，这些连接电极均是为了对晶体管的衬底进行偏置而设置，例如用于将N型衬底连接至第一电源电压端以接收第一电源电压VDD(高电压)，或者用于将P型衬底连接至第二电源电压端以接收第二电源电压VSS(低电压)，由此可以避免衬偏效应等寄生效应，提高电路的稳定性。
结合参考图27B，该连接电极319a、319b分别通过第二绝缘层202中的过孔262a、262b与衬底基板101中的第二区(N阱区)402中的接触孔区411a、411b电连接，该连接电极319a和319b用于连接到第一电压端VDD以对该第一数据写入晶体管P1的N型衬底进行偏置。该连接电极319c通过第 二绝缘层202中的过孔262c与衬底基板101中的接触孔区400a电连接，该连接电极319c用于连接到第二电压端VSS以对与第二数据写入晶体管N1所在的P型衬底进行偏置。
结合参考图29A-29B，该第一导电层301还包括偏置电压线250，该偏置电压线250沿第一方向D1延伸，并通过第二绝缘层202中的过孔263与偏置晶体管N3的栅极电连接，以提供第二公共电压Vcom2。
结合参考图27B、图29A-29B，该第一导电层301还包括电源线260(本公开第九电源线的一个示例)，该电源线260沿第一方向D1延伸，用于传输第二电源电压VSS。该电源线260通过第二绝缘层202中的过孔264a与偏置晶体管N3的第一极电连接以提供第二的电源电压VSS，并通过第二绝缘层202中的过孔264b与衬底基板101中的接触孔区400b电连接，以对与第二数据写入晶体管N1所在的P型衬底(本公开的第二掺杂区的一个示例)进行偏置。
图30A示出了第二导电层302的示意图，图30B在第一导电层301的基础上示出了第二导电层302，图30B中还示出了第三绝缘层203中的过孔，该第三绝缘层203中的过孔用于连接第一导电层301中的图案和第二导电层302中的图案。为了清楚起见，图中仅示出了四行六列子像素，并用虚线示出了两个子像素行的分界线；此外在图30B中还对应示出了图26A中剖面线I-I’所在的位置。
如图30A所示，在第一方向D1上相邻的两个子像素中的第二导电层的图案关于沿第二方向D2的对称轴对称；在第二方向D2上相邻的两个子像素中的第二导电层的图案关于沿第一方向D1的对称轴对称。以下将以一个子像素为例对该第二导电层的图案进行示例性说明。
如图30A所示，该第二导电层302包括沿第一方向D1延伸的电源线270a、270b、280a、280b，该电源线270a、270b用于传输第二电源电压VSS，该电源线280a、280b用于传输第一电源电压VDD。该电源线270a、280a、270b、280b在第二方向D2上一一交替排列。
结合参考图26B、图30A和图30B，该电源线270a(本公开第一电源线的一个示例)通过第三绝缘层203中的多个过孔235与第一导电层301中的电源线260电连接，从而形成并联结构，有效降低了走线上的电阻；该多个过孔235沿第一方向D1排列。例如，该电源线270b通过第三绝缘层203中 的过孔236与第四电容电极316电连接以提供该第二电源电压VSS；例如，多个过孔236沿第二方向D2排列。例如，该电源线270b还通过第三绝缘层203中的过孔267与第三电容电极315电连接以提供该第二电源电压VSS；例如，多个过孔267沿第二方向D2排列。
例如，在第二方向D2上，电源线270b(本公开第七电源线的一个示例)的平均线宽大于电源线270a的平均线宽，这是由于与该电源线270b电连接的第四电容电极316与第三电容电极315均具有较大的面积，将电源线270b设置为具有较大的宽度可以便于与第四电容电极316之间和第三电容电极315形成多个连接孔236、267，从而有效降低接触电阻。
结合参考图30A和图30B，该电源线280a(本公开第二电源线的一个示例)通过第三绝缘层203中的过孔237与第一导电层301中的连接电极318(本公开第五连接电极的一个示例)电连接，从而连接到驱动晶体管N2的第一极以提供第一电源电压VDD。该电源线280b通过第三绝缘层203中的过孔238与第一导电层301中的连接电极319a电连接，从而对衬底基板101中的第二区(N阱区)402(本公开的第一掺杂区的一个示例)进行高压偏置；例如，多个过孔238沿第二方向D2排列。
例如，在第二方向D2上，电源线280b(本公开第八电源线的一个示例)的平均线宽大于电源线280a的平均线宽，这是由于与该电源线280b电连接的连接电极319a在第二方向D2上具有较大的尺寸，将电源线280b设置为具有较大的宽度可以便于与连接电极319a之间形成多个连接孔238，从而增大与连接电极319a的接触面积，有效降低接触电阻。
例如，该第二导电层302还包括沿第一方向D1延伸的多条第一扫描线210和多条第二扫描线220。例如，图24A所示的扫描线11可以是该第一扫描线210或第二扫描线220。
结合参考图29A和图29B，该第一扫描线210通过第三绝缘层203中的过孔231与第一扫描线连接部311电连接，该第二扫描线220通过第三绝缘层203中的过孔232与第二扫描线连接部312电连接。
例如，结合参考图26B、图30A和图30B，该第二导电层302还包括连接电极323，该连接电极323通过第三绝缘层203中的过孔239与第一导电层301中的连接电极314电连接，从而连接到电阻器130的第二端132。该连接电极323用于与发光元件120的第一电极121电连接。例如，该过孔239的 数目至少为两个。
例如，结合参考图30A和图30B，该第二导电层302还包括连接电极324，该连接电极324通过第三绝缘层203中的过孔265与第一导电层301中的连接电极319b电连接，以与衬底基板101中的第二区(N阱区)402中的接触孔区411b电连接。
例如，结合参考图30A和图30B，该第二导电层302还包括连接电极325，该连接电极325通过第三绝缘层203中的过孔266与第一导电层301中的连接电极319c电连接，以与衬底基板101中的接触孔区400a电连接。
例如，该连接电极325为十字型结构。例如，该连接电极324与连接电极325在第一方向D1上交替分布，并位于两个子像素行的分界处。
例如，如图30A所示，该第二导电层302还包括数据线连接部244(本公开第四连接电极的一个示例)。结合参考图30B，该数据线连接部244通过过孔233与第一导电层301中的数据线连接部245电连接。
例如，如图30A所示，多个数据线连接部244在第一方向D1上间隔排布，每相邻两个数据线连接部244之间设置有一个连接电极324或者连接电极325。
例如，该数据线连接部244位于两个子像素行的分界处。例如，在第二方向D2上相邻的两个子像素共用一个数据线连接部244。
例如，结合参考图30A和图30B，在第二方向D2上，位于每列子像素中的数据线连接部244交替位于数据线连接部245的两侧，分别通过过孔233、234与该数据线连接部245的第一端和第二端电连接，这是为了将该数据线连接部245连接到不同的数据线。
图31A示出了第三导电层303的示意图，图31B在第二导电层302的基础上示出了第三导电层303，图31B中还示出了第四绝缘层204中的过孔，该第四绝缘层204中的过孔用于连接第二导电层302中的图案和第三导电层303中的图案。为了清楚起见，图中仅示出了四行六列子像素对应的导电图案，并用虚线在图31A中示出了两行子像素的分界线；此外在图31B中还对应示出了图26A中剖面线I-I’所在的位置。
例如，该第三导电层303包括沿第二方向D2延伸的多条数据线，该数据线用于与子像素中的数据写入子电路的第一端连接以提供数据信号Vd。例如，如图31A所示该多条数据线包括多条第一数据线241和多条第二数据线 242，第一数据线241和第二数据线242在第一方向D1上一一交替排布。例如，图24A所示的数据线12可以是该第一数据线241或第二数据线242。
例如，该数据线分成多个数据线组，每个数据线组包括一条第一数据线241和一条第二数据线242。例如，每个子像素列分别与一个数据线组对应连接，也即连接一条第一数据线241和一条第二数据线242；也即一列子像素通过两条数据线驱动。这样有助于降低每条数据线上的负载，从而提高数据线的驱动能力，降低信号的延迟，提高显示效果。
参考图31B，第一数据线241通过第四绝缘层204中的过孔403与图30B中所示的第二导电层302中位于第一行子像素和第二行子像素之间的数据线连接部244电连接，从而给该第一和第二行子像素提供数据信号；该第二数据线242通过第四绝缘层204中的过孔404与图30B中所示的第二导电层302中位于第三行子像素和第四行子像素之间的数据线连接部244电连接，从而给该第三和第四行子像素提供数据信号。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (92)

  1. 一种显示基板，包括：
    驱动基板，包括衬底和驱动电路；
    第一平坦层，位于所述驱动电路上；
    阳极层，位于所述第一平坦层远离所述驱动基板的一侧；
    像素限定层，位于所述阳极层远离所述驱动基板的一侧；
    发光功能层，位于所述阳极层远离所述驱动基板的一侧；
    阴极层，位于所述发光功能层远离所述驱动基板的一侧；以及
    封装层，位于所述阴极层远离所述驱动基板的一侧；
    其中，所述驱动电路包括至少一个晶体管，所述晶体管包括半导体层，
    所述阳极层包括多个阳极，所述显示基板包括多个像素开口，且位于所述多个阳极远离所述驱动基板的一侧，所述多个像素开口被配置为与所述多个阳极至少存在交叠；
    各所述阳极包括主体部和凸起部，所述凸起部与所述主体部相连，所述凸起部在第一方向上的尺寸大于所述主体部在所述第一方向上的尺寸，所述发光功能层包括多个发光部，所述多个发光部与所述多个阳极的所述主体部接触设置。
  2. 根据权利要求1所述的显示基板，其中，所述凸起部设置在所述主体部的周边。
  3. 根据权利要求1所述的显示基板，其中，所述像素限定层在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影交叠。
  4. 根据权利要求3所述的显示基板，其中，所述像素限定层包括像素限定部，所述像素限定部包括：
    像素限定平坦部，位于相邻的两个所述阳极之间；以及
    突起结构，分别位于相邻两个所述阳极的所述凸起部远离所述驱动基板的一侧，
    其中，所述像素限定平坦部将所述突起结构相连。
  5. 根据权利要求4所述的显示基板，其中，所述像素限定部关于所述相邻所述阳极之间的间隔区的中心呈对称设置。
  6. 根据权利要求4所述的显示基板，其中，各所述突起结构包括：
    第一侧壁，位于所述突起结构靠近所述主体部的中心的一侧；以及
    第二侧壁，与所述第一侧壁相连，
    其中，所述第二侧壁相对于所述第一侧壁，更远离所述驱动基板；所述第一侧壁的坡度角大于所述第二侧壁的坡度角。
  7. 根据权利要求6所述的显示基板，其中，所述第一侧壁的坡度角的取值范围为75-89度，所述第二侧壁的坡度角的取值范围为15-45度。
  8. 根据权利要求6所述的显示基板，其中，各所述突起结构还包括：
    第三侧壁，位于所述突起结构靠近所述像素限定平坦部的一侧，
    其中，所述第三侧壁的坡度角大于所述第二侧壁的坡度角，且小于所述第一侧壁的坡度角。
  9. 根据权利要求6所述的显示基板，其中，各所述突起结构还包括：
    第三侧壁，位于所述突起结构靠近所述像素限定平坦部的一侧，
    其中，所述第一侧壁的坡度角为α，所述第二侧壁的坡度角为β，所述第三侧壁的坡度角为γ，并满足下列公式：
    β<γ<α。
  10. 根据权利要求8所述的显示基板，其中，所述第一侧壁的坡度角与所述第二侧壁的坡度角的差值等于所述第三侧壁的坡度角的i倍，i的取值范围为0.8-1.2。
  11. 根据权利要求9所述的显示基板，其中，所述第一侧壁的坡度角α，所述第二侧壁的坡度角β，所述第三侧壁的坡度角γ满足下列公式：
    (α-β)＝i*γ，
    其中，i的取值范围为0.8-1.2。
  12. 根据权利要求8所述的显示基板，其中，所述第一侧壁的坡度角与所述第二侧壁的坡度角的差值等于所述第二侧壁的坡度角与第三侧壁的坡度角的差值的j倍，j的取值范围为1.5-3。
  13. 根据权利要求9所述的显示基板，其中，所述第一侧壁的坡度角α，所述第二侧壁的坡度角β，所述第三侧壁的坡度角γ满足下列公式：
    (α-β)＝j*(γ-β)，
    其中，j的取值范围为1.5-3。
  14. 根据权利要求8所述的显示基板，其中，所述第一侧壁的坡度角与所述第二侧壁的坡度角之和等于所述第三侧壁的坡度角的k倍，k的取值范围为 2-3。
  15. 根据权利要求9所述的显示基板，其中，所述第一侧壁的坡度角α，所述第二侧壁的坡度角β，所述第三侧壁的坡度角γ满足下列公式：
    (α+β)＝k*γ-β，
    其中，k的取值范围为2-3。
  16. 根据权利要求8所述的显示基板，其中，所述第三侧壁的坡度角的取值范围为45-60度。
  17. 根据权利要求8所述的显示基板，其中，所述第三侧壁在所述驱动基板上的正投影在第二方向上的尺寸大于所述第二侧壁在所述驱动基板上的正投影在所述第二方向上的尺寸，所述第二侧壁在所述驱动基板上的正投影在第二方向上的尺寸大于所述第一侧壁在所述驱动基板上的正投影在所述第二方向上的尺寸。
  18. 根据权利要求9所述的显示基板，其中，所述第一侧壁在所述第一方向上的尺寸为H1，所述第二侧壁在所述第一方向上的尺寸为H2，所述第三侧壁在所述第一方向上的尺寸为H3，H1、H2和H3满足下列公式：
    H3*cosγ>H2*cosβ>H1*cosα。
  19. 根据权利要求8所述的显示基板，其中，各所述阳极的所述凸起部包括第四侧壁，位于所述凸起部靠近所述主体部的中心的一侧，
    其中，所述第四侧壁的坡度角大于所述第二侧壁的坡度角，且小于所述第一侧壁的坡度角。
  20. 根据权利要求9所述的显示基板，其中，各所述阳极的所述凸起部包括第四侧壁，位于所述凸起部靠近所述主体部的中心的一侧，
    其中，所述第四侧壁的坡度角为δ，且满足以下公式：
    β<δ<α。
  21. 根据权利要求19所述的显示基板，其中，各所述阳极的所述凸起部包括：
    第一子阳极层，位于所述驱动电路远离所述衬底的一侧；
    第二子阳极层，位于所述第一子阳极层远离所述驱动基板的一侧；及
    第三子阳极层，位于所述第二子阳极层远离所述驱动基板的一侧。
  22. 根据权利要求21所述的显示基板，其中，所述第一子阳极层在第二方向上的尺寸大于所述第三子阳极层在所述第二方向上的尺寸，所述第三子阳极 层在所述第二方向上的尺寸大于所述第二子阳极层在所述第二方向上的尺寸。
  23. 根据权利要求22所述的显示基板，其中，所述第三子阳极层在所述第二方向上超出所述第二子阳极层的尺寸小于所述像素限定层在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影的交叠区域在所述第二方向上的尺寸。
  24. 根据权利要求21所述的显示基板，其中，所述第一子阳极层远离所述主体部的一端包括隆起部，所述隆起部在所述第一方向上的厚度大于所述第一子阳极层在所述第一方向上的平均厚度。
  25. 根据权利要求21所述的显示基板，其中，所述第三子阳极层远离所述主体部的一端向靠近所述第一子阳极层的方向弯曲。
  26. 根据权利要求21所述的显示基板，其中，各所述阳极的所述凸起部还包括：
    第四子阳极层，位于所述第二子阳极层和第三子阳极层之间，所述第四子阳极层在所述第二方向上的尺寸小于所述第二子阳极层在所述第二方向上的尺寸。
  27. 根据权利要求26所述的显示基板，其中，所述第三子阳极层在所述第二方向上超出所述第四子阳极层的尺寸小于所述像素限定层在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影的交叠区域在所述第二方向上的尺寸。
  28. 根据权利要求26所述的显示基板，其中，所述第二子阳极层包括第五侧壁，位于所述第二子阳极层远离所述主体部的一侧，所述第四子阳极层包括第六侧壁，位于所述第四子阳极层远离所述主体部的一侧，
    所述第五侧壁的坡度角大于所述第四侧壁的坡度角，所述第六侧壁的坡度角大于所述第四侧壁的坡度角，所述第五侧壁的坡度角大于所述第六侧壁的坡度角。
  29. 根据权利要求26所述的显示基板，其中，所述第一子阳极层在垂直于驱动基板的所述第一方向上的厚度与所述第二子阳极层在垂直于驱动基板的所述第一方向上的厚度之比的范围在1/15-1/5。
  30. 根据权利要求26所述的显示基板，其中，所述第一子阳极层在垂直于驱动基板的所述第一方向上的厚度与所述第三子阳极层在垂直于驱动基板的所述第一方向上的厚度之比的范围在1/3-4/5。
  31. 根据权利要求26所述的显示基板，其中，所述第一子阳极层在垂直于驱动基板的所述第一方向上的厚度与所述第四子阳极层在垂直于驱动基板的所述第一方向上的厚度之比的范围在1/24-1/8。
  32. 根据权利要求21所述的显示基板，其中，相邻两个所述阳极之间的距离与所述阳极的凸起部在所述驱动基板上的正投影的长度之比的范围为2-4。
  33. 根据权利要求32所述的显示基板，其中，相邻两个所述阳极之间的距离与所述阳极的凸起部在所述驱动基板上的正投影的长度之比的范围为2.5-3.5。
  34. 根据权利要求1-33中任一项所述的显示基板，其中，所述凸起部围绕所述主体部设置。
  35. 根据权利要求34所述的显示基板，其中，所述阳极在所述驱动基板上的正投影的形状包括六边形。
  36. 根据权利要求1-35中任一项所述的显示基板，还包括：
    反射电极层，位于所述第一平坦层靠近所述阳极层的一侧；以及
    第二平坦层，位于所述反射电极层靠近所述阳极层的一侧。
  37. 根据权利要求36所述的显示基板，其中，所述反射电极层在所述像素开口中连续设置。
  38. 根据权利要求1-37中任一项所述的显示基板，其中，所述发光功能层与所述主体部之间存在第一孔隙，所述发光功能层与所述像素限定层之间存在至少一个第二孔隙，所述第一孔隙占据的空间大于所述第二孔隙占据的空间。
  39. 根据权利要求1-38中任一项所述的显示基板，其中，所述封装层包括：
    无机封装层，位于所述阴极层远离所述驱动基板的一侧，
    其中，所述无机封装层包括多个子无机封装层。
  40. 根据权利要求39所述的显示基板，其中，所述多个子无机封装层之中至少存在两个相邻的采用不同的材料制作的子无机封装层，所述多个子无机封装层中至少存在两个相邻的采用相同的材料制作的子无机封装层。
  41. 根据权利要求39所述的显示基板，其中，在远离所述驱动基板的方向上，所述多个子无机封装层的折射率先增大后减小。
  42. 根据权利要求39所述的显示基板，其中，在远离所述驱动基板的方向上，所述多个子无机封装层在所述第一方向上的厚度逐渐减小。
  43. 根据权利要求39所述的显示基板，其中，各所述子无机封装层包括： 交替设置的平坦区和双拱间隔区、位于所述平坦区远离所述双拱间隔区的一侧的第一拱形区、位于所述平坦区和所述双拱间隔区之间的第二拱形区、以及位于所述平坦区远离所述第二拱形区的第三拱形区，
    所述第一拱形区和所述第二拱形区关于所述平坦区的中心对称设置。
  44. 根据权利要求43所述的显示基板，其中，所述平坦区在第二方向上的尺寸为L，所述第二拱形区的中心和所述第三拱形区的中心在所述第二方向上的距离为第一距离D1，所述第一拱形区的中心和所述第二拱形区的中心在所述第二方向上的距离为第二距离D2，所述第一拱形区、所述第二拱形区和所述第三拱形区的曲率半径均为R，
    所述第一距离D1满足以下公式：
    D2≤(L+D1)<(L+R)。
  45. 根据权利要求43所述的显示基板，其中，所述平坦区在第二方向上的尺寸为L，所述第二拱形区的中心和所述第三拱形区的中心在所述第二方向上的距离为第一距离D1，所述第一拱形区的中心和所述第二拱形区的中心在所述第二方向上的距离为第二距离D2，所述第一拱形区、所述第二拱形区和所述第三拱形区的曲率半径均为R，
    所述第一距离D1满足以下公式：
    (L+D1)≤D2<(L+R)。
  46. 根据权利要求43所述的显示基板，其中，所述第一拱形区、所述第二拱形区或所述第三拱形区在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影交叠，所述平坦区在所述驱动基板上的正投影与所述主体部在所述驱动基板上的正投影交叠，
    所述第一拱形区、所述第二拱形区或所述第三拱形区远离所述驱动基板的表面与所述驱动基板之间的距离大于所述平坦区远离所述驱动基板的表面与所述驱动基板之间的距离。
  47. 根据权利要求43所述的显示基板，其中，所述双拱间隔区在所述驱动基板上的正投影与相邻两个所述阳极之间的间隔区在所述驱动基板上的正投影交叠。
  48. 根据权利要求43所述的显示基板，其中，所述多个子无机封装层包括：
    第一子无机封装层，位于所述阴极层远离所述驱动基板的一侧；
    第二子无机封装层，位于所述第一子无机封装层远离所述驱动基板的一侧；
    第三子无机封装层，位于所述第二子无机封装层远离所述驱动基板的一侧；以及
    第四子无机封装层，位于所述第三子无机封装层远离所述驱动基板的一侧。
  49. 根据权利要求48所述的显示基板，其中，所述第一子无机封装层的折射率小于所述第二子无机封装层的折射率，所述第四子无机封装层的折射率小于所述第三子无机封装层的折射率。
  50. 根据权利要求49所述的显示基板，其中，所述第二子无机封装层的折射率与所述第三子无机封装层的折射率相等。
  51. 根据权利要求48所述的显示基板，其中，所述第一子无机封装层的所述平坦区在所述第二方向上具有第一宽度，所述第二子无机封装层的所述平坦区在所述第二方向上具有第二宽度，所述第三子无机封装层的所述平坦区在所述第二方向上具有第三宽度，所述第四子无机封装层的所述平坦区在所述第二方向上具有第四宽度，
    所述第一宽度大于所述第二宽度，所述第二宽度大于所述第三宽度，所述第三宽度大于所述第四宽度。
  52. 根据权利要求48所述的显示基板，其中，所述第一子无机封装层的所述平坦区靠近所述第二拱形区的边缘、所述第二子无机封装层的所述平坦区靠近所述第二拱形区的边缘、所述第三子无机封装层的所述平坦区靠近所述第二拱形区的边缘和所述第四子无机封装层的所述平坦区靠近所述第二拱形区的边缘的第一连线与所述驱动基板远离所述阳极层的表面之间的夹角为第一夹角，
    所述第一子无机封装层的所述第二拱形区的顶点、所述第二子无机封装层的所述第二拱形区的顶点、所述第三子无机封装层的所述第二拱形区的顶点和所述第四子无机封装层的所述第二拱形区的顶点的第二连线与所述驱动基板远离所述阳极层的表面之间的夹角为第二夹角，
    所述第一夹角小于所述第二夹角。
  53. 根据权利要求52所述的显示基板，其中，所述第一夹角的范围为60-85度，所述第二夹角的范围为85-89度。
  54. 根据权利要求52所述的显示基板，其中，所述第一连线和所述第二连线的交点位于所述驱动基板之内。
  55. 根据权利要求54所述的显示基板，其中，所述驱动电路包括：
    半导体层，位于所述衬底之中；
    第一导电层，位于所述半导体层上；
    第二导电层，位于所述第一导电层远离所述衬底的一侧；
    第三导电层，位于所述第二导电层远离所述衬底的一侧；以及
    第四导电层，位于所述第三导电层远离所述衬底的一侧。
  56. 根据权利要求55所述的显示基板，其中，所述第一连线和所述第二连线的交点位于所述第三导电层远离所述衬底的上表面与所述阳极层之间。
  57. 根据权利要求55所述的显示基板，其中，所述第一连线与所述第二连线的交点与所述像素限定层的突起结构远离所述衬底的上表面的顶点之间距离大于所述第一子无机封装层在所述第一方向上的厚度。
  58. 根据权利要求55所述的显示基板，其中，所述第一连线与所述第二连线的交点与所述像素限定层的突起结构远离所述衬底的上表面的顶点之间距离小于所述第一子无机封装层在所述第一方向上的厚度和所述第二子无机封装层在所述第一方向上的厚度之和。
  59. 根据权利要求55所述的显示基板，其中，所述第一子无机封装层的所述第二拱形区靠近所述双拱间隔区的边缘、所述第二子无机封装层的所述第二拱形区靠近所述双拱间隔区的边缘、所述第三子无机封装层的所述第二拱形区靠近所述双拱间隔区的边缘和所述第四子无机封装层的所述第二拱形区靠近所述双拱间隔区的边缘的第三连线与所述驱动基板远离所述阳极层的表面之间的夹角为第三夹角，所述第三夹角小于所述第二夹角。
  60. 根据权利要求59所述的显示基板，其中，所述第一连线和所述三连线的交点位于所述第二导电层远离所述衬底的上表面与所述第三导电层靠近所述衬底的下表面之间。
  61. 根据权利要求59所述的显示基板，其中，所述第二连线和所述第三连线的交点位于所述第一导电层靠近所述衬底的下表面与所述衬底远离所述第一导电层的下表面之间。
  62. 根据权利要求59所述的显示基板，其中，所述第一子无机封装层的所述第三拱形区远离所述双拱间隔区的边缘、所述第二子无机封装层的所述第三拱形区远离所述双拱间隔区的边缘、所述第三子无机封装层的所述第三拱形区远离所述双拱间隔区的边缘和所述第四子无机封装层的所述第三拱形区远离 所述双拱间隔区的边缘的第四连线与所述驱动基板远离所述阳极层的表面之间的夹角为第四夹角，所述第四夹角小于所述第二夹角。
  63. 根据权利要求62所述的显示基板，其中，所述第一连线与所述第四连线的交点位于所述衬底远离所述第一导电层的一侧。
  64. 根据权利要求62所述的显示基板，其中，所述第三连线与所述第四连线的交点位于所述衬底远离所述第一导电层的一侧。
  65. 根据权利要求48所述的显示基板，其中，所述第一子无机封装层的所述第一拱形区远离所述衬底的上表面具有第一曲率半径，所述第二子无机封装层的所述第一拱形区远离所述衬底的上表面具有第二曲率半径，所述第三子无机封装层的所述第一拱形区远离所述衬底的上表面具有第三曲率半径，所述第四子无机封装层的所述第一拱形区远离所述衬底的上表面具有第四曲率半径，
    所述第一曲率半径小于所述第二曲率半径，所述第二曲率半径小于所述第三曲率半径，所述第三曲率半径小于所述第四曲率半径。
  66. 根据权利要求65所述的显示基板，其中，所述第四子无机封装层的所述第一拱形区的虚设圆心位于所述第一子无机封装层远离所述衬底的上表面和所述第四子无机封装层靠近所述衬底的下表面之间。
  67. 根据权利要求48所述的显示基板，其中，所述第一子无机封装层在所述第一方向上具有第一厚度，所述第二子无机封装层在所述第一方向上具有第二厚度，所述第三子无机封装层在所述第一方向上具有第三厚度，所述第四子无机封装层在所述第一方向上具有第四厚度，
    所述第一厚度大于所述第二厚度，所述第二厚度大于所述第三厚度，所述第三厚度大于所述第四厚度。
  68. 根据权利要求67所述的显示基板，其中，所述第一厚度与所述第二厚度的差值和所述第三厚度与所述第四厚度的差值的比例范围为1.5-2倍。
  69. 根据权利要求67所述的显示基板，其中，所述第二厚度和所述第三厚度之和与所述第一厚度的比例范围为0.8-1.2。
  70. 根据权利要求67所述的显示基板，其中，所述第一厚度的范围为1000-1200纳米，所述第二厚度的范围为500-660纳米，所述第三厚度的范围480-560纳米，所述第四厚度的范围为180-260纳米。
  71. 根据权利要求70所述的显示基板，其中，所述第一子无机封装层的材料包括氧化硅和氮氧化硅，所述第二子无机封装层的材料包括氮化硅，所述第 三子无机封装层的材料包括氮化硅，所述第四子无机封装层的材料包括氧化硅。
  72. 根据权利要求39所述的显示基板，其中，所述封装层还包括：
    有机封装层，位于所述无机封装层远离所述驱动基板的一侧，
    其中，所述有机封装层包括第一区域、第二区域和第三区域，所述第一区域的平均厚度小于所述第二区域的平均厚度，所述第二区域的平均厚度小于所述第三区域的平均厚度。
  73. 根据权利要求1-72中任一项所述的显示基板，还包括：
    彩膜层，位于所述封装层远离所述驱动基板的一侧，
    其中，所述彩膜层包括第一彩色滤光片、第二彩色滤光片和第三彩色滤光片。
  74. 根据权利要求73所述的显示基板，其中，所述第一彩色滤光片和所述第二彩色滤光片存在第一交叠区，所述第二彩色滤光片和所述第三彩色滤光片存在第二交叠区，所述第三彩色滤光片和所述第一彩色滤光片存在第三交叠区。
  75. 根据权利要求74所述的显示基板，其中，所述第一交叠区、所述第二交叠区和所述第三交叠区在所述驱动基板上的正投影与所述凸起部在所述驱动基板上的正投影交叠。
  76. 根据权利要求74所述的显示基板，其中，所述第一交叠区、所述第二交叠区和所述第三交叠区在所述驱动基板上的正投影与相邻两个所述阳极之间的间隔区在所述驱动基板上的正投影交叠。
  77. 根据权利要求74所述的显示基板，其中，所述第一交叠区在所述第二方向上的尺寸大于所述第二交叠区在所述第二方向上的尺寸，所述第二交叠区在所述第二方向上的尺寸大于所述第三交叠区在所述第二方向上的尺寸。
  78. 根据权利要求77所述的显示基板，其中，所述第一交叠区在所述第二方向上的尺寸范围为400-600纳米，所述第二交叠区在所述第二方向上的尺寸范围为250-350纳米，所述第三交叠区在所述第二方向上的尺寸范围为100-200纳米。
  79. 根据权利要求74所述的显示基板，其中，所述第一彩色滤光片在所述第一方向上的平均尺寸大于所述第二彩色滤光片在所述第一方向上的平均尺寸，且小于所述第三彩色滤光片在所述第一方向上的平均尺寸。
  80. 根据权利要求79所述的显示基板，其中，所述第一彩色滤光片在所述第一方向上的平均尺寸的范围为2.3-2.6微米，所述第二彩色滤光片在所述第 一方向上的平均尺寸的范围为1.7-1.95微米，所述第三彩色滤光片在所述第一方向上的平均尺寸的范围为2.3-2.7微米。
  81. 根据权利要求80所述的显示基板，其中，所述第一彩色滤光片在所述第一方向上的平均尺寸与所述第二彩色滤光片在所述第一方向上的平均尺寸的差值和所述第一彩色滤光片在所述第一方向上的平均尺寸与所述第三彩色滤光片在所述第一方向上的平均尺寸的差值之比的范围为2-3。
  82. 根据权利要求79所述的显示基板，其中，所述第一彩色滤光片包括第一边缘部、第二边缘部和位于所述第一边缘部和所述第二边缘部之间的中间部，所述中间部在所述第一方向上的平均尺寸小于所述第一边缘部在所述第一方向上的平均尺寸和所述第二边缘部在所述第一方向上的平均尺寸。
  83. 根据权利要求79所述的显示基板，其中，所述第一彩色滤光片包括与所述第二彩色滤光片接触的第一接触面，所述第二彩色滤光片包括与所述第三彩色滤光片接触的第二接触面，所述第三彩色滤光片包括与所述第一彩色滤光片接触的第三接触面，
    所述第一接触面在垂直于所述驱动基板的第一方向上的尺寸与所述第二接触面在所述第一方向上的尺寸相等，且小于所述第三接触面在所述第一方向上的尺寸。
  84. 根据权利要求74所述的显示基板，其中，所述第一彩色滤光片与所述驱动基板远离所述阳极层的表面的距离大于所述第三彩色滤光片与所述驱动基板远离所述阳极层的表面的距离，且小于所述第二彩色滤光片与所述驱动基板远离所述阳极层的表面的距离。
  85. 根据权利要求74所述的显示基板，其中，所述第一彩色滤光片为红色滤光片，所述第二彩色滤光片为绿色滤光片，所述第三彩色滤光片为蓝色滤光片。
  86. 根据权利要求74所述的显示基板，其中，所述彩膜层的材料包括干燥剂。
  87. 根据权利要求74所述的显示基板，其中，所述彩膜层包括铝元素。
  88. 根据权利要求74所述的显示基板，还包括：
    保护层，位于所述彩膜层远离所述驱动基板的一侧。
  89. 根据权利要求74所述的显示基板，其中，所述彩膜层还包括：
    黑矩阵，位于第一彩色滤光片、第二彩色滤光片和第三彩色滤光片中任意 相邻的两个之间。
  90. 根据权利要求74所述的显示基板，还包括：
    玻璃盖板，位于所述彩膜层远离所述驱动基板的一侧。
  91. 根据权利要求1-90中任一项所述的显示基板，其中，所述驱动电路包括：
    驱动晶体管，包括控制极、第一极和第二极；
    第一晶体管，包括控制极、第一极和第二极；以及
    第二晶体管，包括控制极、第一极和第二极，
    其中，所述第一晶体管的所述第一极与所述第二晶体管的所述第一极与所述驱动晶体管的控制极相连，所述第一晶体管的所述第二极和所述第二晶体管的所述第二极被配置为接收数据信号，所述第一晶体管的所述控制极和所述第二晶体管的所述控制极被配置为接收扫描信号，
    所述驱动晶体管的所述第二极与所述阳极电连接，并被配置为驱动与所述阳极接触的所述发光功能层发光。
  92. 一种显示装置，包括根据权利要求1-91中任一项所述的显示基板。
PCT/CN2022/102336 2022-04-22 2022-06-29 显示基板和显示装置 Ceased WO2023201888A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP22790435.6A EP4287810A4 (en) 2022-04-22 2022-06-29 Display substrate and display device
JP2022573738A JP2025513959A (ja) 2022-04-22 2022-06-29 表示基板及び表示装置
CN202280002029.6A CN117280887A (zh) 2022-04-22 2022-06-29 显示基板和显示装置
KR1020227033452A KR20250004402A (ko) 2022-04-22 2022-06-29 표시 기판 및 표시 장치
US18/020,301 US20240276772A1 (en) 2022-04-22 2022-06-29 Display substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210423991.9 2022-04-22
CN202210423991.9A CN114551769B (zh) 2022-04-22 2022-04-22 显示基板和显示装置

Publications (1)

Publication Number Publication Date
WO2023201888A1 true WO2023201888A1 (zh) 2023-10-26

Family

ID=81667394

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/102336 Ceased WO2023201888A1 (zh) 2022-04-22 2022-06-29 显示基板和显示装置

Country Status (7)

Country Link
US (1) US20240276772A1 (zh)
EP (1) EP4287810A4 (zh)
JP (1) JP2025513959A (zh)
KR (1) KR20250004402A (zh)
CN (6) CN116997201A (zh)
TW (1) TWI844157B (zh)
WO (1) WO2023201888A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116997201A (zh) * 2022-04-22 2023-11-03 北京京东方技术开发有限公司 显示基板和显示装置
CN115425090B (zh) * 2022-08-30 2026-02-10 武汉华星光电技术有限公司 薄膜晶体管及其电子器件
CN116113267B (zh) * 2022-12-07 2025-12-16 京东方科技集团股份有限公司 显示面板和显示装置
CN119233706A (zh) * 2023-06-30 2024-12-31 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN119968666B (zh) * 2023-09-06 2026-01-09 京东方科技集团股份有限公司 驱动电路、显示基板和显示装置
WO2025137890A1 (zh) * 2023-12-26 2025-07-03 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
CN118890926A (zh) * 2024-09-09 2024-11-01 武汉天马微电子有限公司 一种显示面板和显示装置
WO2026081039A1 (en) * 2024-10-14 2026-04-23 Boe Technology Group Co., Ltd. Array substrate and display apparatus
CN120548039B (zh) * 2025-07-25 2025-12-02 维信诺科技股份有限公司 显示面板、显示装置及设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017273A (ja) * 2001-07-05 2003-01-17 Sony Corp 表示装置および表示装置の製造方法
JP2006054199A (ja) * 2005-10-18 2006-02-23 Idemitsu Kosan Co Ltd 有機電界発光素子用電極基板および有機ｅｌ発光装置
CN102969329A (zh) * 2011-08-30 2013-03-13 三星显示有限公司 含具有反射结构的电极的有机发光显示装置及其制造方法
CN111668382A (zh) * 2020-06-19 2020-09-15 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN114551769A (zh) * 2022-04-22 2022-05-27 北京京东方技术开发有限公司 显示基板和显示装置

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7897979B2 (en) * 2002-06-07 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and manufacturing method thereof
KR101318072B1 (ko) * 2008-06-04 2013-10-15 엘지디스플레이 주식회사 유기발광다이오드 표시장치 및 이의 제조 방법
JP5276222B2 (ja) * 2010-08-25 2013-08-28 パナソニック株式会社 有機発光素子とその製造方法、および有機表示パネルと有機表示装置
JP5919807B2 (ja) * 2011-03-30 2016-05-18 ソニー株式会社 有機発光素子、有機発光素子の製造方法および表示装置
KR102160417B1 (ko) * 2014-02-28 2020-10-05 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조 방법
KR102352283B1 (ko) * 2014-11-03 2022-01-18 삼성디스플레이 주식회사 유기발광 디스플레이 장치
CN107170904B (zh) * 2017-06-30 2019-10-15 京东方科技集团股份有限公司 Oled显示基板及其制作方法、显示装置
JP7020566B2 (ja) * 2018-11-19 2022-02-16 ソニーグループ株式会社 発光素子
CN109873089B (zh) * 2019-02-28 2021-09-03 合肥鑫晟光电科技有限公司 发光二极管显示面板及其制造方法
CN111180603A (zh) * 2019-02-28 2020-05-19 广东聚华印刷显示技术有限公司 显示器件及其制备方法、显示装置
KR102869825B1 (ko) * 2019-05-17 2025-10-10 엘지디스플레이 주식회사 발광 표시 장치
CN112820763B (zh) * 2019-07-31 2024-06-28 京东方科技集团股份有限公司 电致发光显示面板及显示装置
AU2019279939B2 (en) * 2019-07-31 2021-04-08 Boe Technology Group Co., Ltd. Display substrate and display device
WO2021030971A1 (zh) * 2019-08-16 2021-02-25 京东方科技集团股份有限公司 显示装置及制备方法、电子设备
US12029065B2 (en) * 2019-08-23 2024-07-02 Boe Technology Group Co., Ltd. Display device and manufacturing method thereof and driving substrate
CN111312768A (zh) * 2020-02-24 2020-06-19 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板
CN114628610B (zh) * 2020-03-25 2023-09-12 京东方科技集团股份有限公司 显示基板和显示装置
US12563903B2 (en) * 2020-03-27 2026-02-24 Boe Technology Group Co., Ltd. Display device, display panel and method of manufacturing the same
JPWO2021201144A1 (zh) * 2020-03-31 2021-10-07
US11882731B2 (en) * 2020-04-21 2024-01-23 Boe Technology Group Co., Ltd. Display device, display panel and manufacturing method thereof
CN111584568B (zh) * 2020-05-12 2023-10-31 Tcl华星光电技术有限公司 显示装置及其制备方法
CN111599937B (zh) * 2020-05-25 2022-10-14 视涯科技股份有限公司 一种有机发光显示面板及有机发光显示面板制备方法
CN113745272B (zh) * 2020-05-29 2024-08-23 京东方科技集团股份有限公司 显示基板和显示装置
CN114190108B (zh) * 2020-07-15 2025-07-18 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
CN111816684A (zh) * 2020-07-16 2020-10-23 合肥维信诺科技有限公司 显示面板、其制作方法和显示装置
CN212695182U (zh) * 2020-09-03 2021-03-12 合肥维信诺科技有限公司 一种显示面板及显示装置
KR102820793B1 (ko) * 2020-12-31 2025-06-13 엘지디스플레이 주식회사 터치 디스플레이 장치
CN112864344A (zh) * 2021-01-28 2021-05-28 合肥维信诺科技有限公司 显示面板制备方法及显示面板
CN215955282U (zh) * 2021-04-15 2022-03-04 京东方科技集团股份有限公司 显示面板及其显示装置
CN113793908A (zh) * 2021-09-08 2021-12-14 南京国兆光电科技有限公司 一种硅基有源矩阵式有机发光显示器及其制作方法
CN113948660B (zh) * 2021-10-14 2024-03-01 武汉天马微电子有限公司 一种显示面板及其制作方法和显示装置
CN114005865B (zh) * 2021-12-30 2022-03-22 北京京东方技术开发有限公司 显示基板及其制备方法、电子装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017273A (ja) * 2001-07-05 2003-01-17 Sony Corp 表示装置および表示装置の製造方法
JP2006054199A (ja) * 2005-10-18 2006-02-23 Idemitsu Kosan Co Ltd 有機電界発光素子用電極基板および有機ｅｌ発光装置
CN102969329A (zh) * 2011-08-30 2013-03-13 三星显示有限公司 含具有反射结构的电极的有机发光显示装置及其制造方法
CN111668382A (zh) * 2020-06-19 2020-09-15 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN114551769A (zh) * 2022-04-22 2022-05-27 北京京东方技术开发有限公司 显示基板和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4287810A4 *

Also Published As

Publication number Publication date
EP4287810A4 (en) 2024-02-21
TW202343849A (zh) 2023-11-01
CN116997202A (zh) 2023-11-03
CN116997200A (zh) 2023-11-03
EP4287810A1 (en) 2023-12-06
US20240276772A1 (en) 2024-08-15
JP2025513959A (ja) 2025-05-02
KR20250004402A (ko) 2025-01-08
CN116997201A (zh) 2023-11-03
CN114551769A (zh) 2022-05-27
CN116997203A (zh) 2023-11-03
TWI844157B (zh) 2024-06-01
CN114551769B (zh) 2022-08-26
CN117280887A (zh) 2023-12-22

Similar Documents

Publication Publication Date Title
WO2023201888A1 (zh) 显示基板和显示装置
EP4123630B1 (en) DISPLAY SCREEN AND DISPLAY DEVICE
US20250287800A1 (en) Display substrate and display device
WO2022174404A1 (zh) 显示面板及显示装置
CN113763883A (zh) 显示基板及显示装置
EP4131239A1 (en) Display panel and display device
US12317703B2 (en) Display substrate having connection electrode in a same layer with one capacitor electrode and electrically connecting the other capacitor electrode to data writing sub-circuit, and display device
WO2021035416A1 (zh) 显示装置及其制备方法
CN112740317B (zh) 显示装置及其制备方法
WO2021035415A1 (zh) 显示装置及其制备方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280002029.6

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 2022790435

Country of ref document: EP

Effective date: 20221028

WWE Wipo information: entry into national phase

Ref document number: 202247067035

Country of ref document: IN

WWE Wipo information: entry into national phase

Ref document number: 2022573738

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 18020301

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE